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RapidIO II MegaCore Function v12.1 SP1 User Guide

1. nee 4 49 Pass Through Interface Usage Examples 4 53 Transport Layer er CURE X E SEI AA RE a Ea ado tace gota pede drei 4 59 RECEIVER dc od nese 4 60 Transmilltero oid arate adie ents cade d RG Steed trata 4 61 Physical Layer ee PER CUP CH PA RE S E PR OPE rv P E RU PIRE 4 62 Features oore aE E a eee 4 62 Physical Layer Int rfac s ategu metae tea d el e ORA god 4 63 Low level Interface Receiver nen nen 4 63 Receiver Transceiver i iius eseu oye P ewe beu HAE OV e WAN a ea eS a ecd 4 63 CRC Checking and Removal 4 eere eR Re ue Re RESO E RE EDI de 4 64 Low Level Interface Transmiittei sry crees netman ne 4 64 Error Detection and Management 42 nnn 4 65 Physical Layer Error Management nen 4 65 Protocol Violations Ute den cede cce OU enc are 4 66 Fatal Errors icco aA p began E Dd i A ele ue Ve RE M Rr des 4 66 Logical Layer Error Management ssssssssseeees ee 4 66 February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide vi Contents Maintenance Avalon MM Slave 0 cece
2. Error Management Registers The RapidIO IP core implements the Error Management Extensions registers These registers are configured in your RapidIO IP core variation if you turn on Enable error management extension registers on the Error Management Registers tab of the RapidIO II parameter editor Table 6 65 shows the memory map for the RapidIO II IP core error management registers The offset values within the address space for these registers are defined by the RapidIO standard February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide Chapter 6 Software Interface Transport and Logical Layer Registers Table 6 66 through Table 6 71 describe the error management registers These registers can be used by software to diagnose problems with packets that are received by the local endpoint If enabled the detected error triggers the assertion of std reg mnt Information about the packet that caused the error is captured in the capture registers After an error condition is detected the information is captured and the capture registers are locked until the Error Detect CSR is cleared Upon being cleared the capture registers are ready to capture a new packet that exhibits an error condition Table 6 65 Error Management Extensions Register Map Address Name 0x300 Error Management Extensions Block Header 0x308 Logical Transport Layer Er
3. ZAMSBS 1 0 ii requests for responses if available 210 Table 6 70 Logical Transport Layer Device ID Capture CSR Offset 0x318 Part 1 of 2 Field Bits Access Function Default Reserved if the system does not support 16 bit device ID LARGE DESTINATION ID Msg 31 24 RO MSB of the Destination ID if the system supports 16 bit 8 h0 device ID DESTINATION ID U 23 16 RO The destination ID associated with the error 8 h0 Reserved if the system does not support 16 bit device ID LARGE SOURCE ID MSB 15 8 RO MSB of the Source ID if the system supports 16 bit device 8 h0 ID RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 6 Software Interface 6 47 Transport and Logical Layer Registers Table 6 70 Logical Transport Layer Device ID Capture CSR Offset 0x318 Part 2 of 2 Field Bits Access Function Default SOURCE ID 7 0 RO The source ID associated with the error 8 h0 Notes to Table 6 70 1 For errors the RapidlO II IP core does not detect internally set this field using the external capture destinationID wr and external capture destinationID in input signals For errors the RapidlO II IP core does not detect internally set this field using the external capture sourceID wr and external capture sourceID in input signals Table 6 71 Logical Transport Layer Control Capture CSR Offset 0x31C Fie
4. 10 Il MegaCore Function RYN 101 Innovation Drive San Jose CA 95134 www altera com UG 01116 1 1 User Guide Document last updated for Altera Complete Design Suite version Document publication date 12 1 SP1 February 2013 MA Feedback Subscribe 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks eb Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ISO 9001 2008 Registered February 2013 Altera Corporation RapidlO II MegaCore Function User Guide N DTE RYN Contents Chapter 1 About The
5. 7 3 Maintenance Write and Read Transactions 0 c cece ce ence 7 4 SW RITE Transachons teer Cete Ea HARI eet CR RA P db oec eec ee cR Redde a 7 5 NREAD TransactiOris Base eet ee e ee Ede Moe ee c e eR Ree ee 7 6 NWRITE R Iransactons du ooo roe e t dee ea RC a ek t Me d uc I de edes 7 7 NWRITE Tr nsactiols nee ere tem eE E e a gen ERR EAER 7 8 Doorbell Transact Ons triere irii i e aide a e Ele i i 7 8 RapidlO II MegaCore Function February 2013 Altera Corporation User Guide Contents vii Port Write Lransactons scusa ku de aa AG ex a a E RHE A RRR iA E 7 9 Transactions Across the Avalon ST Pass Through Interface 7 10 Testbench Completion rec er ten EE ae ENG Conde b REPE ee be e petu 7 10 Appendix A Initialization Sequence Appendix B Differences Between RapidlO II MegaCore Function and 10 MegaCore Function v12 1 Additional Information Document Revision History 2 2 nnne Info 1 How to Contact Altera sci ac cet aps e denten ode eee bee Deu e E eg Info 1 Typographic Conventions Ferme e eee ek ee Renee Id RR he a e ee Re ex Info 1 February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide viii Contents RapidlO II MegaCore Function February 2013 Altera Corporation User Guide 1 About The RapidlO Il JN DTE RYAN MegaCore Function
6. RapidlO II MegaCore Function User Guide February 2013 Altera Corporation Chapter 6 Software Interface 6 51 Transport and Logical Layer Registers Table 6 78 Port 0 Packet Capture 1 CSR Offset 0x350 Field Bits Access Function Default Contains the fifth through eighth bytes of the packet or long CAPTURE 1 31 0 RO control symbol based on the zNFO field of the Port 0 32 h0 Attributes Capture CSR Table 6 79 Port 0 Packet Capture 2 CSR Offset 0x354 Field Bits Access Function Default Contains the ninth through twelfth bytes of the packet or long CAPTURE 2 31 0 RO control symbol based on the zNFO field of the Port 0 32 h0 Attributes Capture CSR Table 6 80 Port 0 Packet Capture 3 CSR Offset 0x358 Field Bits Access Function Default Contains the thirteenth through sixteenth bytes of the packet or CAPTURE 3 31 0 RO long control symbol based on the INFO TYPEfield ofthe Port o 32 h0 Attributes Capture CSR Table 6 81 Port 0 Error Rate CSR Offset 0x368 Part 1 of 2 Field Bits Access Function Default Specifies the rate at which the ERR RATE COUNTER field is decremented This field supports the following valid values 8 h00 Do not decrement the error rate counter 8 h01 Decrement every 1 ms 34 8 h02 Decrement every 10 ms 34 8 h04 Decrement every 100 ms 34 8 h08 Decrement
7. e n 5 9 Chapter 6 Software Interface Memory Map ie bcm Fue Ug e ote Uie eee i e P een tee cde ae geese eee Partes tg 6 2 Physical Layer Registers oc etate dett a agi hare dest desee tese e oae ides 6 6 Transport and Logical Layer Registers ee 6 25 Capability Registers CARs 0 s Hen 6 26 Command and Status Registers CSRs 6 31 Maintenance Interrupt Control Registers 2 0 06 eens 6 34 Transmit Maintenance Registers scisreirersesireidii tit e 6 35 Transmit Port Write Registers ete nent ees 6 36 Receive Port Write Registers sedes erue Qd Cet eee e d eiae ied e eed 6 36 Input Output Master Address Mapping Registers 0 0 e eee eee eee eee 6 37 Input Output Master Interrupts 000s 6 38 Input Output Slave Mapping Registers 000s 6 38 Input Output Slave 6 40 Input Output Slave Pending Transactions ee 6 41 Error Management Registers cick cout eH R y Y e Re a eeu Red RAE ene 6 41 Doorbell Message Registers pienesti nnn nents 6 52 Chapter 7 Testbench Testbench Overview ee een eet eee bene e a een 7 1 Testbench Sequence pirer dete Hint qoiedety hg oet eal lentes nee Rees 7 3 Reset Initialization and Configuration 0 00 cece
8. oof 1 R XAMO Offset register 0x10418 0 o 1 0 Don t Care a Vv 33 32 31 30 29 3 RapidlO Address 33 0 o o 1 o 26 h3555999 23 16 Control register 0x1041C OxAA Destination ID RapidlO II MegaCore Function February 2013 Altera Corporation User Guide Chapter 4 Functional Description 4 21 Logical Layer Interfaces Translation Window 2 An Avalon MM address in which the two most significant bits have a value of 2 b11 matches window 2 The RapidIO transaction corresponding to the Avalon MM operation has a destination ID value of 0xcC This value corresponds to processing endpoint 2 Figure 4 13 shows address translation window 2 Figure 4 13 Translation Window 2 31 30 29 32 1 0 Avalon Address 31 0 1 1 26 h3555999 Base register 0x10420 1 4 Don t Care sj Mask register 0x10424 1 1 000000000000000000 00 1 R XAMO Offset register 0 10428 0 o 1 1 Don t Care E NA 33 32 31 30 29 3 RapidlO Address 33 0 o oli 1 26 h3555999 0 23 16 Control register 0x1042C OxCC Destination ID Avalon MM Burstcount and Byteenable Encoding in RapidlO Packets The RapidIO IP core converts Avalon MM transactions to RapidIO packets The IP translates the Avalon MM burst count byteenable and address bit 3 values to the RapidIO packet read size write size and word pointer fields For information about th
9. 10 Il MegaCore Function Features cti betta ea ee tede den aba BAG pit debe an dab reae En dede oe iei eee 1 1 New Features in the RapidIO IL IP Core v12 1 SP1 Release 12 RapidIO ILIP Core Features ccc tebe tad cea ie EROS UE RR be ned IRE S We Y wa ea ey 1 2 Supported Transactions ce eov S atomes hats nct iens Aceto eee de gy oes 1 3 Device Family Support sva Mn RE get eet eat b deba Von te pi 1 4 out 1 4 Sim latop Lesung cece hele beue eee Or week Ra ws ex d Va Sa e as s E vare P Vae 1 4 Hardware TeStih x cet cetus uM UEM M meten 1 5 Interoperability Testing 252 i Cert ER IE OPES d pe Hep bk Leg ene Pp qoos 1 6 Performance and Resource Utilization 0 66 nnn 1 6 Device Speed Grades iot neds ete UR ERI Bae ae Oe ek DEE ves nC e a ees 1 7 Release Information ceste a aaah reece amos ea EE UN UN CS 1 7 Installation and Licensing er e eR PERRA OPE an teas eae ee ae Ae bla 1 8 OpenGore Plus Evaluation conoce eer Eee e RERO Ue meds dae st eed ease 1 8 OpenCore 1 eene 1 9 Chapter 2 Getting Started Design FLOWS qe 2 1 MegaWizard Plug In Manager Design Flow e 2 2 QsyS Desi FIOW POP Ln 2 2 MegaWizard Plug In Manager Design Flow 6 66 e 2 2 Specifying
10. then it is considered out of bounds and this bit is set Table 6 40 Maintenance Interrupt Enable Offset 0x10084 Field Bit Access Function Default RSRV 31 7 RO Reserved 25 h0 PORT WRITE ERROR 6 RW Port write error interrupt enable 1 b0 RX PACKET DROPPED 5 RW Rx port write packet dropped interrupt enable 1 bo RX_PACKET_STORED 4 RW Rx port write packet stored in buffer interrupt enable 1 b0 RSRV 3 2 RO Reserved 2 b00 WRITE OUT OF BOUNDS 1 RW Tx write request address out of bounds interrupt enable 1 00 READ OUT OF BOUNDS 0 RW Tx read request address out of bounds interrupt enable 1 b0 RapidlO II MegaCore Function User Guide February 2013 Altera Corporation Chapter 6 Software Interface Transport and Logical Layer Registers Transmit Maintenance Registers Table 6 41 through Table 6 44 describe the transmitter maintenance registers When transmitting a MAINTENANCE packet an address translation process occurs using a base mask offset and control register As many as sixteen groups of four registers can exist The 16 register address offsets are shown in the table titles For more details on how to use these windows refer to Initiating MAINTENANCE Read and Write Transactions on page 4 34 6 35 Table 6 41 Tx Maintenance Mapping Window n Base Offset 0x10100 0x10110 0x10120 0x10130 0x10140 0x10150 0x10160 0x10170 0x10180 0x10190 0x101A0 0 101 0 0x101C0 0x101D0 0x101
11. 0x10210 0x1024C Tx Port Write Buffer Write Registers on page 6 36 0x10250 0x10254 Rx Port Write Control Rx Port Write Status 0x10260 0x1029C Rx Port Write Buffer Maintenance module These registers are described in Receive Port Write Registers on page 6 36 0x102A0 0x102FC Reserved 0x10300 I O Master Window 0 Base 0x10304 I O Master Window 0 Mask Input Output Master Logical layer 0x10308 I O Master Window 0 Offset NP These registers are described in Input Output 0x1030C Reserved Master Address Mapping Registers on page 6 37 0x10310 0x103F8 with gaps I O Master Windows 1 15 0x103DC I O Master Interrupt Input Output Master Logical layer These registers are described Input Output 0x103FC I OMaster Interrupt Enable Master Interrupts on page 6 38 0x10400 I O Slave Window 0 Base 0x10404 1 0 Slave Window 0 Mask Input Output Slave Logical layer 0x10408 1 0 Slave Window 0 Offset These registers are described in Input Output Slave 0x1040C 1 0 Slave Window 0 Control Mapping Registers on page 6 38 0x10410 0x104FC I O Slave Windows 1 15 0x10500 I O Slave Interrupt Input Output Slave Logical layer These registers are described in Input Output Slave 0x10504 I O Slave Interrupt Enable Interrupts on page 6 40 I O Slave Pending NWRITE R 0x10508 x Transactions Input Output Slave Logical layer
12. 2 The reset value of the Source Operations CAR is the result of the bitwise exclusive or operation applied to the default values and the value you specify for Source operations CAR override in the RapidlO Il parameter editor 3 The default value is 1 b1 if you turn on Enable 1 0 Logical layer Slave module in the RapidlO II parameter editor The default value is 1 bo if you turn off Enable 1 0 Logical layer Slave module in the RapidlO II parameter editor 4 Thedefault value is 1 b1 if you turn on Enable Doorbell support in the RapidlO Il parameter editor The default value is 1 bo if you turn off Enable Doorbell support in the RapidlO Il parameter editor 5 The default value is 1 b1 if you turn on Enable Maintenance module in the RapidlO II parameter editor The default value is 1 bo If you turn off Enable Maintenance module Table 6 29 Destination Operations CAR Offset Ox1C 2 Part 1 of 2 Field Bits Access Comment Default RSRV 31 20 RO Reserved 12 h0 DATA STRM TRAFFIC 19 RO Processing element can support data streaming traffic 10 _ MANAGEMENT management DATA STREAMING 18 RO Processing element can support a data streaming operation 1 0 RSRV 17 16 RO Reserved 2 b0 READ 15 RO Processing element can support a read operation 3 February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 6 30 Chapter 6 Software Interface Transport and Logical Layer Registe
13. Doorbell Refer to Table 4 22 on page 4 46 Avalon ST Pass Through Interface Signals This section tells you where you can find the Avalon ST pass through interface signals Table 5 10 lists the location of the signal lists and descriptions for the Avalon ST pass through interface Table 5 10 Avalon ST Pass Through Interface Signals Interface Location of Signal Table Avalon ST sink transmit side of the IP core Refer to Table 4 24 on page 4 49 data signals Avalon ST source receive side of the IP core Refer to Table 4 25 on page 4 50 header signals Avalon ST source receive side of the IP core Refer to Table 4 26 on page 4 51 Data Streaming Support Signals The RapidIO II IP core provides support for your custom implementation of data streaming using the Avalon ST pass through interface In addition to Error Management Extension block signals for user defined data streaming the IP core provides dedicated signals to read and write the Data Streaming Logical Layer Control CSR described in Table 6 32 on page 6 31 Table 5 11 lists the signals provided to read and write the Data Streaming Logical Layer Control CSR Table 5 11 Data Streaming Support Signals Part 1 of 2 Signal Direction Description tm types 3 0 Output These output signals reflect the values of the fields with the corresponding names in tm mode 3 0 Output the Data Streaming
14. FIFO Tx Output FIFO Tx Tx Staging FIFO FFO Preserving Transaction Order If you select Prevent doorbell messages from passing write transactions in the RapidIO parameter editor each DOORBELL message from the Avalon MM interface is kept in the Tx staging FIFO until all I O write transactions that started on the write Avalon MM slave interface before this DOORBELL message arrived on the Doorbell module Avalon MM interface have been transmitted to the Transport layer An I O write transaction is considered to have started before a DOORBELL transaction if the ios rd wr write signal is asserted while the ios rd wr waitrequest signal is not asserted on a cycle preceding the cycle on which the drbell s write signal is asserted for writing to the Tx Doorbell register while the drbell s waitrequest signal is not asserted If you do not select Prevent doorbell messages from passing write transactions in the RapidIO II parameter editor the Doorbell Tx staging FIFO is not configured in the RapidIO IL IP core February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide Chapter 4 Functional Description Logical Layer Interfaces Doorbell Module Signals Table 4 9 lists the Doorbell module interface signals Table 4 22 Doorbell Module Interface Signals Signal Direction Description drbell s wai
15. the corresponding request packet Transport Layer The Transport layer is a required module of the RapidIO II IP core It is intended for use in an endpoint processing element and must be used with at least one Logical layer module or the Avalon ST pass through interface You can optionally turn on the following two parameters m Enable Avalon ST pass through interface If you turn on this parameter the Transport layer routes all unrecognized packets to the Avalon ST pass through interface February 2013 Altera Corporation RapidlO II MegaCore Function User Guide 4 60 Chapter 4 Functional Description Transport Layer m Disable destination ID checking by default If you turn on this parameter request packets are considered recognized even if the destination ID does not match the value programmed in the Base Device ID CSR Offset 0x60 This feature enables the RapidIO II IP core to process multi cast transactions correctly The Transport layer module is divided into receiver and transmitter submodules Figure 4 23 shows a block diagram of the Transport layer module Figure 4 23 Transport Layer Block Diagram Logical Layer Avalon ST Pass Through scheduler E Transport Layer Rx Buffer Tx Rx Y Physical Layer Receiver On the receive side the Transport layer module receives packets from the
16. 000 e 3 6 Processing Element Features CAR lisse n 3 7 Bridge Support eek s Rr AP Rae Eas ha rea ade a e aee 3 7 Memory Access oes aC pene E REA I D P IE e EE cde a ee gem Rata 3 7 Processor Present ise er UR a NEP eee eR PAGG p REPE Y A ete 3 7 Enable Flow Arbitration Support e 3 7 Enable Standard Route Table Configuration Support 3 7 Enable Extended Route Table Configuration 3 8 Enable Flow Control Support 0 eessbet e rrr see e hn ds 3 8 Enable Switch Support ie eee re ee Rc a eee eee e RR bad E Rr EET 3 8 Switch Port Information CAR 2 5 EE eh hh res 3 8 ot Ports sii he Riad aa ea 3 8 Port Number 450 rr rer ERE We A REPE ARA dee RE nct aer ens 3 8 Switch Route Table Destination ID Limit CAR seeeeeeeeeeee e 3 8 Switch Route Table Destination ID Limit eeeeeeeeeee nee nent nen eee 3 9 Data Streaming Information CAR n 3 9 bb INR ERES ERE RR KE ERG A EOS EE Ed EDS 3 9 Number of Segmentation Contexts enn 3 9 Source Operations CAR ia xus septi Y sepes ce EA Vale 3 9 Destination Operations CAR e Cb dated deae Pasa e Peces 3 9 Command and Status Registers
17. 0x1050C I O Slave Avalon MM Write These registers are described in Input Output Slave Transactions Pending Transactions on page 6 41 0x10510 I O Slave RapidIO Write Requests Physical Layer Registers The RapidIO II IP core implements the following Physical layer registers in Extended Features space m Allofthe LP Serial Extended Features block registers RapidlO II MegaCore Function User Guide February 2013 Altera Corporation Chapter 6 Software Interface 6 7 Physical Layer Registers m TheLP Serial Lane Extended Features block for up to four lanes including three implementation specific registers per lane The LP Serial Lane Extended Features block implementation specific registers support software driven control of transmitter pre emphasis for both the local and remote ends of the RapidIO link Table 6 5 shows the memory map for the RapidIO IL IP core Physical layer Table 6 6 through Table 6 21 describe the registers for the Physical layer of the RapidIO IP core The offset values within each of the two Extended Feature spaces LP Serial and LP Serial Lane are defined by the RapidIO standard Table 6 5 Physical Layer Register Map Extended Features Address Name Extended Features Space LP Serial 0x100 LP Serial Register Block Header 0x104 0x11C Reserved 0x120 Port Link Time out Control CSR 0x124 Port Response Time out Control CSR 0x13C Port General Control CSR 0x140
18. ERR RATE DEGR THRESHOLD field of the Port 0 Error Rate Threshold CSR at offset 0x36C Table 6 82 on page 6 52 is enabled is non zero and this value is reached If the PORT DEGR EN bit in the Port 0 Control CSR at offset 0x15C Table 6 15 on page 6 16 has the value of 1 b1 when this signal is raised the RapidlO II IP core asserts the std reg mnt irginterrupt signal port degraded Output February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 5 10 Chapter 5 Signals Error Management Extension Signals RapidlO II MegaCore Function February 2013 Altera Corporation User Guide N DTE RYN 6 Software Interface The RapidIO IP core supports the following sets of registers that control the RapidIO IP core or query its status Standard RapidIO capability registers CARs Standard RapidIO command and status registers CSRs Extended features registers Implementation defined registers Doorbell specific registers Some of these register sets are supported by specific RapidIO II IP core layers only This chapter organizes the registers by the layers they support The Physical layer registers are described first followed by the Transport and Logical layers registers All of the registers are 32 bits wide and are shown as hexadecimal values The registers can be accessed only on a 32 bit 4 byte basis The addressing for the registers therefore increments by units of 4 57 Reserved
19. ee 3 3 Disable Destination ID Checking 66 06 3 3 Logical Layer Settings ee teer een e eene imet eck alte dentin aod ene oe Rp tech deme d ign 3 3 Maintenance Configuration Settings 2000 6 6 ehe 3 4 Doorbell Configuration Settings 2 0 6 een 3 4 I O Master Contiguration ic caeci eee ee Pa Va Hee iced ecce ae ree uoce 3 4 February 2013 Altera Corporation RapidlO II MegaCore Function User Guide iv Contents 1 O Slave Configuration es n rk Rea rer de bx e LEY EPA Y REEGU REP Eric he 3 5 Capability Registers Settings sies oc rk eere e ed ond bac a ce ba rad e e Er E ERE 3 5 Device Identity CAR ted cea Sie vad ga we wa d aae e ex Yd Fe PRETI RE 3 5 Device lD dece REG DRA RAIS DES ea EAR TAA RR EPEUERA EAE 3 5 Vendor ID 2 2 b deg b aep a udis ee repa teo eileen eee Ae Un RI eg 3 5 Device Information CAR 2 0 0 0 cc e e teen eens 3 6 Revision ID dee Wee e RUP vx Nh Ge eae ee V da eate yat 3 6 Assembly Identity CAR rinra aee ieri 3 6 Assembly ID c eR re e EE crepe E RR CIPUE 3 6 Assembly Vendor hx e pao eas rh hc a Ee EE ees 3 6 Assembly Information CAR e n 3 6 Revision i 23cm REI RR FEED UG eU RI hs GU ERREUR EAR ERE 3 6 Extended Features Pointer
20. 15 0 RO Hard wired assembly vendor identifier 1 Note to Table 6 24 1 The value is set in the RapidlO Il parameter editor Table 6 25 Assembly Information CAR Offset 0x0C Field Bits Access Function Default AssyRev 31 16 RO Hard wired assembly revision level 1 Hard wired pointer to the first entry in the extended feature ExtendedFeaturesPtr 15 0 RO The value of this field is 0x100 which points to the LP Serial 32 h100 Extended Features block Note to Table 6 25 1 The value is set in the RapidlO II parameter editor Table 6 26 Processing Element Features CAR Offset 0x10 Part 1 of 3 Field Bits Access Function Default Processing element can bridge to another interface Processing element has physically addressable local address space and can be accessed as an endpoint through non maintenance operations Bridge 31 RO 2 1 Memory 891 9 This local address space may be limited to local configuration registers on chip SRAM or other device RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 6 Software Interface Transport and Logical Layer Registers Table 6 26 Processing Element Features CAR Offset 0x10 Part 2 of 3 6 27 Critical Request Flow 1 b1 Processing element supports Critical Request Flow Field Bits Access Funct
21. Defining the Input Output Avalon MM Slave Address Mapping Windows on page 4 22 for a description of how to use these registers Table 6 56 Input Output Slave Mapping Window n Base Offset 0x10400 0x10410 0x10420 0x10430 0x10440 0x10450 0x10460 0x10470 0 10480 0x10490 0x104A0 0x104B0 0x104C0 0x104D0 0x104E0 0 104 0 Field Bits Access Function Default Start of the Avalon MM address window to be mapped The BASE 31 4 RW four least significant bits of the 32 bit base are assumed to be 28 ho all zeros RSRV 3 0 RO Reserved 4 h0 RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 6 Software Interface 6 39 Transport and Logical Layer Registers Table 6 57 Input Output Slave Mapping Window n Mask Offset 0x10404 0x10414 0x10424 0x10434 0x10444 0x10454 0x10464 0x10474 0x10484 0x10494 0x104M 0x104B4 0x104C4 0x104D4 0x104E4 0x104F4 Field Bits Access Function Default 28 most significant bits of the mask for the address mapping MASK 31 4 RW window The four least significant bits of the 32 bit mask are 28 ho assumed to be zeros RSRV 3 RO Reserved 1 ho WEN 2 RW Window enable Set to one to enable the corresponding window RSRV 1 0 RO Reserved 2 h0 Table 6 58 Input Output Slave Mapping Window n Offset Q0ffset 0x10408 0x10418 0x10428 0x10438 0x10448 0x10458 0x10468 0x10478 0x1048
22. 3 b000 The following values are valid 3 b011 reset device 3 b100 input status Table 6 11 Port 0 Link Maintenance Response CSR Offset 0x144 Field Bits Access Function Default Value is the status of the most recent 1ink request control symbol this RapidlO II IP core sent on the RapidlO link If the 1ink response control symbol is a link request input status control symbol this bit if set indicates that the 1ink response control symbol has RESPONSE VALID 31 RO RC been received and the status fields in this register are valid If the 160 link response control symbol is a link request reset device control symbol this bit if set indicates that the 1ink request was transmitted This bit automatically clears in response to a read operation RSRV 30 11 RO Reserved 20 b0 Value of the ackID status field in the 1ink response control symbol This field holds the value of the next expected acklD Refer to Table 3 3 in the RapidlO Interconnect Specification v2 2 Part 6 LP Serial Physical Layer Specification ACKID STATUS 10 5 RO Value of the port status field in the 1ink response control PORT STATUS 4 0 RO symbol Refer to Table 3 6 in the RapidlO Interconnect Specification 5 0 v2 2 Part 6 LP Serial Physical Layer Specification February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 6 10 Chapter 6 Software Interface Physical Layer
23. IP core includes one set of Tx Maintenance Mapping Window registers for each translation window The following registers define address translation window n A base register Tx Maintenance Mapping Window Base Table 6 41 on page 6 35 A mask register Tx Maintenance Mapping Window n Mask Table 6 42 An offset register Tx Maintenance Mapping Window n Offset Table 6 43 A control register Tx Maintenance Mapping Window n Control Table 6 44 To enable a window set the window enable WEN bit of the window s Tx Maintenance Window Mask register Table 6 42 on page 6 35 to the value of 1 To disable it set the WEN bit to the value of zero For each defined and enabled window the RapidIO II IP core masks out the Avalon MM address s least significant bits with the window mask and compares the resulting address to the window base If the address matches multiple windows the IP core uses the lowest number matching window After determining the appropriate matching window the RapidIO II IP core creates the config offset value in the converted MAINTENANCE transaction based on the following equation If mnt s address amp mask base then config offset offset 25 3 amp mask 25 3 mit s address 23 1 amp mask 25 3 where mnt s address 23 0 is the Avalon MM slave interface address signal which holds bits 25 2 of the 26 bit byte address m mask 31 0 is the mask register base 31 0 is the base a
24. burstcount 4 0 00 m iom rd wr byteenable 15 0 00 00 0 iom rd wr readdatavalid iom rd wr readresponse iom rd wr readdata 127 0 fs Da Figure 4 7 NWRITE Transaction on the Input Output Avalon MM Master Interface Sys clk iom rd wr waitrequest iom rd wr write iom rd wr address 31 0 iom rd wr writedata 127 0 iom rd wr byteenable 15 0 iom rd wr burstcount 7 0 RapidlO II MegaCore Function User Guide o Xd AdrA AdrB 02 February 2013 Altera Corporation Chapter 4 Functional Description 4 19 Logical Layer Interfaces Input Output Avalon MM Slave Module The Input Output I O Avalon MM slave Logical layer module is an optional component of the I O Logical layer The I O Avalon MM slave Logical layer module receives Avalon MM transactions from user logic and converts these transactions to RapidIO read and write request packets The module sends the RapidIO packets to the Transport layer to be sent on the RapidIO link For each RapidIO read or write request the target remote RapidIO processing element implements the actual read or write transaction and sends back a response if required Avalon MM read transactions complete when the RapidIO II IP core receives
25. port MISSING DATA STRM CNTXT EN 21 RW Enable reporting of a continuation or end data streaming segment for a closed or non existent segmentation context Save and lock capture information in the appropriate Logical Transport Layer Control Capture CSRs User logic must provide the correct capture information on the appropriate input signals when assserting the missing data streaming context set input port OPEN EXSTG DATA STRM CNTXT EN 20 RW Enable reporting of an initial or single data streaming segment for an already open segmentation context Save and lock capture information in the appropriate Logical Transport Layer Control Capture CSRs User logic must provide the correct capture information on the appropriate input signals when assserting the open existing data streaming context set input port 1 b0 February 2013 Altera Corporation RapidlO II MegaCore Function User Guide 6 46 Chapter 6 Software Interface Transport and Logical Layer Registers Table 6 68 Logical Transport Layer Error Enable CSR Offset Ox30C Part 3 of 3 Field Bits Access Function Default Enable reporting of a data streaming segment with a payload size greater than the MTU Save and lock capture information in the appropriate Logical Transport Layer LONG DATA STRM SGMNT EN 19 RW Control Capture CSRs User logic must provide the correct 1 b0 capture information on the appropriate input s
26. process them User Sending MAINTENANCE Read Requests and Receiving Responses Table 4 19 lists the Maintenance Avalon MM interface usage example this section describes Table 4 19 Maintenance Interface Usage Example Sending MAINTENANCE Read Request and Receiving Response User Operation Device ID Width Payload Size Bytes Send MAINTENANCE read request 16 Receive MAINTENANCE read response 16 RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 4 Functional Description 4 41 Logical Layer Interfaces Figure 4 18 shows the behavior of the signals for two read transfers on the Maintenance Avalon MM slave interface Figure 4 18 Read Transfers on the Maintenance Avalon MM Slave Interface System clock mnt s waitrequest ___ mnt s read mnt s address mnt s readdatavalid mnt s readdata um um mnt s readerror W In the first active clock cycle of the example user logic specifies that the active transaction is a read request by asserting the mnt s read signal while specifying the source address for the read data on the mnt s address signal However the RapidIO IL IP core throttles the incoming transaction by asserting the mnt s writerequest signal until it is ready to receive the read transaction In the example the IP core throttles the incoming transaction for four clock cycles The user logic maintains the values on the mit 8 read and mnt
27. the doorbell interrupts must be enabled To enable interrupts the testbench sets the lower three bits in the Doorbell Interrupt Enable register located at address 0x0000 0020 The test also programs the DUT to store all of the successful and unsuccessful DOORBELL messages in the Tx Completion FIFO For more information refer to Table 6 91 on page 6 54 Next the test pushes five DOORBELL messages to the transmit DOORBELL Message FIFO of the DUT The test increments the message payload for each transaction which occurs when the drbl master bfm read write cmd task is invoked with a WRITE operation to the TX doorbell register at offset 0x0000 000C This action programs the 16 bit message an incrementing payload in this example as well as the DESTINATION ID OxCD for an 8 bit device ID or 0xCDCD for a 16 bit device ID which is used in the DOORBELL transaction packet RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 7 Testbench Testbench Sequence To verify that the DOORBELL request packets have been sent the test waits for the drbell s irqsignalto be asserted The test then reads the Tx Doorbell Completion register refer to Table 6 89 on page 6 54 This register provides the DOORBELL messages that have been added to the Tx Completion FIFO Five successfully completed DOORBELL messages should appear in that FIFO and each one should be accessible by reading the Tx Doorbell Completion register five
28. your design has only a single Transceiver Reconfiguration Controller which has eleven dynamic reconfiguration interfaces If you choose to use two Transceiver Reconfiguration Controllers for example to accommodate placement and timing constraints for your design each of the RapidIO IP cores must connect to a single Transceiver Reconfiguration Controller RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 2 Getting Started 2 9 Instantiating Multiple RapidlO II IP Cores Figure 2 3 illustrates an example design with two Transceiver Reconfiguration Controllers and four RapidIO IP cores In the example Altera Transceiver Reconfiguration Controller 0 has seven reconfiguration interfaces and Altera Transceiver Reconfiguration Controller 1 has four reconfiguration interfaces Each sub block shown in a Transceiver Reconfiguration Controller block represents a single reconfiguration interface The example shows only one possible configuration for this combination of RapidIO II IP cores subject to the constraints described you may choose a different configuration Figure 2 3 Example Connections Between Two Transceiver Reconfiguration Controllers and Four RapidlO Il IP Cores reconfig from xcvr N 1 0 lt reconfig fromgxb N 1 0 reconfig to xcvr M 1 0 gt reconfig togxb M 1 0 m reconfig fromgxb 2N 1 N reconfig from xcvr N 1 0 lreconfig 2M 1 M reconfig to xcvr M 1 0
29. 1 However because the registers defined in the Error Management Extension specification are not all implemented in the RapidlO IP core the error management registers are mapped in the Implementation Defined Space instead of being mapped in the Extended Features Space The RapidlO IP core does not implement the LP Serial Lane Extended Features registers RapidlO II MegaCore Function User Guide February 2013 Altera Corporation Appendix B Differences Between RapidlO II MegaCore Function and RapidlO MegaCore Function v12 1 B 3 Table B 1 Major Differences Between the RapidlO Il IP Core v12 1 and the RapidlO IP Core v12 1 Part 3 of 3 value for read requests on the 1 0 Logical layer Master and Slave interfaces Read transactions on the 1 0 Logical layer Master and Slave interfaces have associated byteenable values Property RapidlO Il IP Core v12 1 RapidlO IP Core v12 1 The RapidlO IP core generates interrupts on two The RapidlO II IP core generates interrupts on output signals the sys mnt s signal and the multiple module and block specific output signals drbell s irqsignal The sys mnt s Signal Interrupt The specific triggering conditions are noted in indicates all interrupt conditions that the RapidlO IP signals registers as in the RapidlO IP core The RapidlO II core indicates in registers except the Doorbell IP core generates all Doorbell module specific module specific interrupt condition
30. 1 0000 0000 1000 0000 0000 1 1 1000 0000 0000 0000 1 0 1 0000 0000 0000 1000 1 1 0000 1000 0000 0000 0 0 1 0000_0000_0100_0000 0001 1 1 0100_0000_0000_0000 1 0 1 0000 0000 0000 0100 1 1 0000 0100 0000 0000 0 0 1 0000_0000_0010_0000 0010 1 1 0010_0000_0000_0000 1 0 1 0000 0000 0000 0010 1 1 0000 0010 0000 0000 0 0 1 0000_0000_0001_0000 0011 1 1 0001 0000 0000 0000 1 0 1 0000 0000 0000 0001 1 1 0000 0001 0000 0000 0 0 1 0000_0000_1100_0000 0100 1 1 1100_0000_0000_0000 1 0 1 0000 0000 0000 1100 1 1 0000 1100 0000 0000 0 0 1 0000_0000_1110_0000 0101 1 1 1 1110 0000 0000 0000 1 0 1 0000 0000 0000 0111 1 1 0000 0111 0000 0000 0 0 1 0000_0000_0011_0000 0110 1 1 0011 0000 0000 0000 1 0 1 0000 0000 0000 0011 1 1 0000 0011 0000 0000 0 0 1 0000_0000_1111_1000 01110 1 1 1111 1000 0000 0000 1 0 1 0000 0000 0001 1111 1 1 0001 1111 0000 0000 0 0 1 0000_0000_1111_0000 1000 1 1 1111 0000 0000 0000 1 0 1 0000 0000 0000 1111 1 1 0000 1111 0000 0000 RapidlO II MegaCore Function User Guide February 2013 Altera Corporation Chapter 4 Functional Description Logical Layer Interfaces 4 15 Table 4 6 Avalon MM 1 0 Master Read Transaction Burstcount Part 2 of 2 RapidlO Field Values Avalon MM Signal Values rdsiz wdptr r Byteenahl 4 nel d pe Burstcount 16 0 0 1 0000 0000 1111 1100 10010 1 1 1
31. 2 RW 1 h0 is in a disallowed position in the received code group stream In the first two cases bit 16 is also set to the value of 1 RapidlO II MegaCore Function User Guide February 2013 Altera Corporation Chapter 6 Software Interface Transport and Logical Layer Registers Table 6 74 Port 0 Error Detect CSR Offset 0x340 Part 2 of 2 6 49 Field symbol Unsolicited ACK control 1 Bits Access RW Function Received an unexpected packet acknowledgement control symbol Default Link timeout 0 RW Did not receive expected packet acknowledgement or link response control symbol within the time out interval specified in the VALUE field of the Port Link 1 h0 Time Out Control CSR Table 6 7 on page 6 8 or the Port Response Time Out Control CSR Table 6 8 Table 6 75 Port 0 Error Rate Enable CSR Offset 0x344 Part 1 of 2 Field RSRV Bits 31 Access RO Function Reserved for this implementation Default 1 h0 RSRV 30 24 RO Reserved T hO RSRV 23 RO Reserved for this implementation The RapidlO II IP core does support the Parallel RapidlO protocol 1 0 Received corrupt control symbol enable 22 RW Received ACK control symbol with unexpected ackID enable 21 RW Received packet not accept ed control symbol enable 20 RW Rece
32. 4 b1100 Supports basic and rate types 4 b1010 Supports basic and credit types 4 b1110 Supports basic rate and credit types All other values are invalid Traffic management mode The following values are valid 4 b0000 TM disabled 4 b0001 Basic mode TM 1 27 24 RW 4 b0010 Rate mode 2 4 b0011 Credit mode 4 b0101 4 b0111 Reserved 4 b1000 4 b1111 Available for user defined modes RSRV 23 8 RO Reserved 29 h0 February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 6 32 Chapter 6 Software Interface Transport and Logical Layer Registers Table 6 32 Data Streaming Logical Layer Control CSR Offset 0x48 Part 2 of 2 MTU 1 Notes to Table 6 32 Field Bits Access 7 0 Function Maximum transmission unit This field controls the data payload size for segments of an encapsulated PDU All segments of a PDU except the final segment must have a data payload of the length specified in this field The MTU is a multiple of four bytes The following values are valid 8 b0000 1000 32 byte block size 8 b0000 1001 64 byte block size 8 b0000 1010 40 byte block size 8 b0100 0000 256 byte block size The following values are invalid 8 b0000 0000 8 b0000 0111 Reserved 8 b0100 0001 8 b1111 1111 Reserved Default 1 change the value of this field dynamically during normal operation use the corresponding wr and
33. February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide Table 6 3 CAR and CSR Memory Map Part 2 of 2 Chapter 6 Software Interface Memory Map Address Processing Element Logical Register Specification Available in PARC Layer Control 0x58 Local Configuration Space Base Rapid O Interconnect Specification v2 2 Part 1 Address 0 Input Output Logical Specification Local Configuration Space Base mes Address 1 0x60 Base Device ID RapidlO Interconnect Specification Part 3 Common 0x68 Host Base Device ID Lock Transport Specification 0x6C Component Tag Table 6 4 Extended Features and Implementation Defined Registers Memory Map Part 1 of 3 Address Extended Features Space LP Serial These registers are defined in Rapid O Interconnect Specification v2 2 Part 6 LP Serial Physical Layer Specification and described in Physical Layer Registers on page 6 6 Used by Module Physical layer 0x100 LP Serial Register Block Header 0x104 0x11C Reserved 0x120 Port Link Time out Control 0x124 Port Response Time out Control 0x13C Port General Control 0x140 Port 0 Link Maintenance Request 0x13C Port 0 Link Maintenance Response 0x148 Port 0 Local AckID 0x14C 0x150 0x154 Reserved Port 0 Control 2 0x158 0x15C Port 0 Error and Status Port 0 Control Extended Features Space LP Serial Lane These registers ar
34. Function Default Transmit emphasis Tap 1 update command This field is active only when the cmp field has the value of 1 Tap 1 7 6 RW 2 b00 Hold 2000 command 2 b01 Decrease emphasis by one step 2 b10 Increase emphasis by one step 2 b11 Reserved Transmit emphasis Tap 1 update command This field is active only when the cp field has the value of 1 Tap 1 5 4 RW 2 b00 Hold 2 b00 command 2 b01 Decrease emphasis by one step 2 b10 Increase emphasis by one step 2 b11 Reserved Transmit emphasis reset command to the connected transceiver This field Reset is active only when the cmp field has the value of 1 3 RW 160 emphasis 2 b0 Ignore 2 b1 Reset all transmit emphasis taps to no emphasis Transmit emphasis command to the connected transceiver to force initial or preset values This field is active only when the field has the value 2 RW of 1 1 b0 2 b0 Ignore 2 b1 Set all transmit emphasis settings to their preset values Indicates that a transmit emphasis update command from the RapidlO link partner is being accepted ACK 1 RW 1 bO 1 b0 Command not accepted 1 b1 Command accepted Indicates that a transmit emphasis update command from the RapidlO link partner is being refused NACK 0 RW 160 100 Command not refused 1 b1 Command refused Preset emphasis The RapidIO IP core transmits the values in the LP Seri
35. Interfaces m Increments the COMPLETED OR CANCELLED WRITES field of the Input Output Slave RapidIO Write Requests register Table 6 64 on page 6 41 if the transaction is a write request User logic can clear an interrupt by writing 1 to the interrupt register s corresponding bit location The Avalon MM slave interface burstcount and byteenable signals determine the values of the RapidIO packet header fields wdptr and rdsize or wrsize Avalon MM Burstcount and Byteenable Encoding in RapidIO Packets on page 4 27 describes the conversion The RapidIO II IP core copies the values you program in the PRIORITY and DESTINATION ID fields of the control register for the matching window to the RapidIO packet header fields prio and destinationID respectively Figure 4 9 shows the I O slave Logical window translation process Figure 4 9 Input Output Slave Window Translation RapidlO Address Space Ox3FFFFFFFF Avalon MM m Offset Address Space OxFFFFFFFF Window Base 0x00000000 0x000000000 t Window Size J94 Initial 91 43 0 Avalon MM Address Bits 1 Window Base 1 Don t Care Window Mask 11111111 41 000000000000000 Window Offset Don t Care EE i i Resulting 33 31 43 0 RapidlO Address Note to Figure 4 9 1 These bits must have the same value in the initial Avalon MM address and in the window bas
36. Management Port Write Reception Module The Port Write reception module processes receive port write request MAINTENANCE packets The following bits in the Maintenance Interrupt register Table 6 39 on page 6 34 in the implementation defined space report any detected anomaly The mnt mnt s irginterrupt signal is asserted if the corresponding bit in the Maintenance Interrupt Enable register Table 6 40 on page 6 34 is set m The PORT WRITE ERROR bit is set when the packet is either too small no payload or too large more than 64 bytes of payload or if the actual size of the packet is larger than indicated by the wrsize field These errors do not cause any of the standard defined errors to be declared and recorded in the error management registers m The PACKET DROPPED bit is set when a port write request packet is received but port write reception is not enabled by setting bit PORT WRITE in the Rx Port Write Control register described in Table 6 48 on page 6 36 or if a previously received port write has not been read out from the Rx Port Write Buffer register Table 6 50 on page 6 37 Port Write Transmission Module Port write requests do not cause response packets to be generated Therefore the port write transmission module does not detect or report any errors Input Output Avalon MM Slave The I O Avalon MM slave module creates request packets for the Avalon MM transaction on its read and write slave interfaces and
37. NS 1 b0 Scrambling descrambling is not enabled 1 b1 Scrambling descrambling is enabled RSRV 14 0 RO Reserved 15 h0 Table 6 19 LP Serial Lane n Status 2 Lane n Interrupt Enable Offset 0x218 0x238 0x258 0x278 Field Bits Access Function Default Enable IDLE2 31 RW Controls whether the IDLE2 received field in the Lane n Status 1 Received interrupt CSR triggers an interrupt Enable CMD changed Controls whether the reception of a changed CS field value triggers an interrupt d interrupt nm When set enables automatic processing of CS field values received in 29 RO the IDLE2 sequence The RapidlO II IP core does not yet implement 1 bO this feature 28 RSRV 0 RO Reserved 29 h0 Table 6 20 LP Serial Lane n Status 3 Received CS Field Commands Offset 0x21C 0x23C 0x25C 0x27C Part 1 of 2 Field Bits Access Function Default A changed cmd value in the CS field received cmd value is different from the previously received value If the Enable CMD changed interrupt 15 bit the LP Serial Lane n Status 2 register is set this change triggers an interrupt CMD changed 31 RW1C CMD 30 RO cmd value of most recently received CS field RSRV 29 RO Reserved 1 b0 Data scrambling 28 RO Value received most recently from the far end enabled L
38. Physical layer Packets travel through the Rx buffer and any errored packet is eliminated The Transport layer module routes the packets to one of the Logical layer modules or to the Avalon ST pass through interface based on the packet s destination ID format type type and target transaction ID targetTID header fields The destination ID matches only if the transport type tt field matches If you turn off destination ID checking in the RapidIO II parameter editor the Transport layer routes incoming packets from the Physical layer that are not already marked as errored according to the following rules m Routes packets with unsupported ftype to the Avalon ST pass through interface if the Avalon ST pass through interface is instantiated in the IP core variation RapidlO II MegaCore Function User Guide February 2013 Altera Corporation Chapter 4 Functional Description 4 61 Transport Layer m Routes packets with a tt value that does not match the RapidIO II IP core s device ID width support level according to the following rules m Ifyou turned on Enable 16 bit device ID width in the RapidIO II parameter editor routes packets with an 8 bit device ID to the Avalon ST pass through interface if the Avalon ST pass through interface is implemented in the IP core variation If this interface is not implemented in your variation drops the packet m Ifyou turned off Enable 16 bit device ID width in the RapidIO II parameter edito
39. Pipelined master read transfers MAINTENANCE read and write operations that target the address range for the RapidIO IP core registers do not appear on the Avalon MM master interface Instead the RapidIO IP core routes them internally to implement the register read and write operations Refer to the Avalon Interface Specifications for more information about the supported transfers MAINTENANCE port write transactions do not appear on the Maintenance Avalon MM interface Refer to Handling Port Write Transactions on page 4 36 RapidlO II MegaCore Function February 2013 Altera Corporation User Guide Chapter 4 Functional Description 4 33 Logical Layer Interfaces Maintenance Interface Transactions The Maintenance slave module accepts read and write transactions from the Avalon MM interconnect converts them to RapidIO MAINTENANCE request packets and sends them to the Transport layer of the RapidIO II IP core to be sent to the Physical layer and transmitted on the RapidIO link The Maintenance slave module uses the valid MAINTENANCE response packets that it receives on the RapidIO link to complete the read transactions on the Maintenance slave interface The Maintenance master module executes register read and write transactions in response to MAINTENANCE requests that the RapidIO II IP core receives on the RapidIO link and sends the appropriate MAINTENANCE response packets For discussion and examples of the conversion b
40. Port 0 Link Maintenance Request CSR 0x144 Port 0 Link Maintenance Response CSR 0x148 Port 0 Local AckID CSR 0x14C 0x50 Reserved 0x154 Port 0 Control 2 CSR 0x158 Port 0 Error and Status CSR 0x15C Port 0 Control CSR Space LP Serial Lane 0x200 LP Serial Lane Register Block Header 0x210 Lane 0 Status 0 Local 0x214 Lane 0 Status 1 Far End 0x218 Lane 0 Status 2 Interrupt Enable 0x21C Lane 0 Status 3 Received CS Field Commands 0x220 Lane 0 Status 4 Outgoing CS Field 0 230 0 280 Lane 1 3 Status Table 6 6 LP Serial Register Block Header 0x100 Field Bits Access Function Default Hard wired pointer to the next block in the data structure The value in EF PTR 31 16 RO this field is the address of the LP Serial Lane Extended Features block 16 h0200 which is 0x200 EF ID 15 0 RO Hard wired extended features ID 16 h0002 February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 6 8 Chapter 6 Software Interface Physical Layer Registers Table 6 7 Port Link Time Out Control CSR 0x120 Field Bits Access Function Default Time out interval value for link layer event pairs such as the time interval between sending a packet and receiving the corresponding acknowledge control symbol or between sending a link request and receiving the corresponding VALUE 31 8 RW link response 24 hFF FFFF The duration of the link response time out is appr
41. RapidIO Trade Association to verify the functionality of the IP core The regression suite tests various functions including the following functionality Link initialization Packet format Packet priority Error handling Throughput Flow control Constrained random techniques generate appropriate stimulus for the functional verification of the IP core Functional and code coverage metrics measure the quality of the random stimulus and ensure that all important features are verified Hardware Testing Altera tests and verifies the RapidIO II IP core in hardware for different platforms and environments The hardware tests cover serial 1x 2x and 4x variations running at 1 25 2 5 3 125 5 0 and 6 25 Gbaud and processing the following traffic types NREADs of various payload sizes NWRITEs of various payload sizes NWRITE Rs of various payload sizes SWRITEs of various payload sizes WB Port writes DOORBELL messages MAINTENANCE reads and writes The hardware tests also cover the following control symbol types E Status E Packet accepted E Packet retry E Packet not accepted Start of packet E End of packet E Link request Link response Stomp E Restart from retry February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 1 6 Chapter 1 About The RapidlO Il MegaCore Function Performance and Resource Utilization E Multicast event Interoperability Testing Altera perf
42. RapidlO Il IP Core Memory Map Ranges Address Range Name Module 0x00 0x3C Capability registers CARs Standard registers 0x40 0x6F Command and Status registers CSRs Standard registers 0x100 0x15F 0x200 0x27F LP Serial Extended Features block LP Serial Lane Extended Features block Physical layer Physical layer 0x300 0x36F Error Management Extensions Extended Features block Standard registers Implementation Defined Space 0x10080 0x107FF 0x10080 0x1029F Maintenance module registers Maintenance module 0x10300 0x103FC 1 0 Logical layer Master module registers 1 0 Logical layer Master module 0x10400 0x10510 1 0 Logical layer Slave module registers 1 0 Logical layer Slave module 0x10600 0x10624 Doorbell module registers Doorbell module 0x10700 0x107FF Reserved Detailed register descriptions for the CARs and CSRs are available in the RapidIO Interconnect Specification v2 2 This user guide also includes the information in the individual register descriptions with the addition of the RapidIO II IP core default values for the individual fields Bit numbering for register fields in the RapidIO II IP core is reversed from the bit numbering the register descriptions in the RapidIO Interconnect Specification v2 2 Refer to Avalon MM Interface Byte Ordering on page 4 1 The descriptions provided in this user guide list the bit numbering in the
43. Registers Table 6 12 Port 0 Local AckID CSR Offset 0x148 Field Bits Access Function Default Writing 1 to this bit causes the RapidlO II IP core to discard all outstanding unacknowledged packets Reading this bit always returns 3 RW thevalue of 0 150 Software can write a 1 to this bit when attempting to recover a failed link RSRV 30 RO Reserved 1 b0 INBOUND ACKID 29 24 RO Next expected packet ackID 6 b0 RSRV 23 14 RO Reserved 10 b0 al 13 8 RO Next expected acknowledge control symbol acklD 6 b0 RSRV 7 6 RO Reserved 2 b0 Next transmitted packet ackID Software can write to this field to force OUTBOUND_ACKID 5 0 RW retransmission of outstanding unacknowledged packets in order to 6 b0 manually implement error recovery Table 6 13 Port 0 Control 2 CSR Offset 0x154 Part 1 of 3 Field Bits Access Function Default The baud rate at which the port is initialized Valid values are 4 b0000 No baud rate selected 400001 1 25 Gbaud 4 b0010 2 5 Gbaud SELECTED_BAUD_ 31 28 RO bd 3 125 Gbaud 40 40100 5 0 Gbaud 4 b0101 6 25 Gbaud All other values are reserved The RapidlO II IP core operates at the highest supported and enabled baud rate DRE DISCON Indicates whether the RapidlO implementation supports automatic 27 RO baud rate discovery The RapidlO Il IP core does not support 1 b0 duds automatic baud rate discovery so this field a
44. Settings 6 6 3 10 Data Streaming Logical Layer Control CSR 10 0 6 ee 3 10 Supported Traffic Management Types Reset Value 3 10 Traffic Management Mode Reset Value en 3 10 Maximum Transmission Unit Reset Value 0 ccc cnet en 3 10 Port General Control CSR 2 2 22 88 cn en en ht 3 10 Host Reset Value i ouo eae he RP hee Behe MY aue Eu Y YER PS RS E 3 10 Master Enable Reset Value onnon unnn ccc cence Rh t 3 11 Discovered Reset Value 2 0 0 0 ccc enc enn en ence rs 3 11 Port0 Control CSR idet exer se UG KG RO e e cec RA 3 11 Flow Control Participant Reset Value e 3 11 Enumeration Boundary Reset Value 6 006 ccs 3 11 Flow Arbitration Participant Reset Value 0 3 11 Lanen Status CSR is cee nk Se eR XE ra T ee ra RE 3 11 Transmitter Type Reset Value crei nesre e EESE 3 11 Receiver Type Reset Value 2 enn 3 11 Error Management Registers Settings 3 11 Chapter 4 Functional Description Interfaces ee oe emot Ae haa term iE 4 1 Avalon Memory Mapped Avalon MM Master and Slave 4 1 Avalon MM In
45. The 32 byte payload requires two clock cycles In the second clock cycle of data transfer the IP core asserts gen rx pd endofpacket to indicate this is the final clock cycle of data transfer and specifies in gen rx pd empty that in the current clock cycle all of the bytes of gen rx pd data are valid Following the clock cycles in which valid data is available on gen rx pd data the IP core deasserts gen rx pd valid Table 4 32 lists the header fields of the received response packet in this example Table 4 32 NREAD Response Receive Example RapidlO Header Fields in gen rx hd data Bus i gen_rx_hd_data Field Bits Value Comment pd size 8 0 114 106 9 h020 Payload data size is 0x20 decimal 32 vc 105 0 The RapidlO II IP core supports only VCO CRF 104 0 Priority of the response packet Value must be higher than the priority value of the request packet In this 1 0 103 102 2010 example the response packet has a priority value of 2 b10 and the original request has a priority value of 2 b01 tt 1 0 101 100 2 b01 Indicates 16 bit device IDs The value of 4 hD decimal 13 indicates a Response 3 0 99 96 4 b1101 Class packet destinationID 15 0 95 80 16hAAAA The sourcelD and destinationID of the NREAD request sourceID 15 0 79 64 16 hDDDD are swapped in the response transaction The value of 8 indicates a Response transaction with ttype
46. and processes the corresponding response packet IL The I O Avalon MM slave module is referred to as a slave module because it is an Avalon MM interface slave L gt The maximum number of outstanding transactions I O Requests the RapidIO IL IP core supports on this interface is 16 8 NREAD requests 8 NWRITE R requests Figure 4 8 shows a block diagram of the I O Avalon MM Logical layer Slave module and its interfaces Figure 4 8 Input Output Avalon MM Slave Logical Layer Block Diagram m Pending Reads 3 j From Transport Layer 128 bits HSik Read Pending Writes lt q and Write Avalon MM Slave Input Output gt Avalon MM Slave Interface Data Path Read Request lt e Read and Write Buffer Avalon MM Bus To Transport Layer 88 128 bits de Write Request Buffer February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 4 20 Chapter 4 Functional Description Logical Layer Interfaces Input Output Avalon MM Slave Signals Table 4 9 lists the Input Output Avalon MM Slave module interface signals Table 4 9 Input Output Avalon MM Slave Interface Signals Signal Direction Description ios rd wr waitrequest Output 1 0 Logical Layer Avalon MM Slave module wait request ios rd wr write Input 1 0 Logical Layer Avalon MM Slave module write request ios r
47. as defined in Part 8 of the RapidlO Interconnect Specification Revision 2 2 57 For information about the Error Management registers refer to their descriptions in Error Management Registers on page 6 41 When enabled each error defined in the Error Management Extensions triggers the assertion of an interrupt on its module specific interrupt output signal and causes the capture of various packet header fields in the appropriate capture CSRs In addition to the errors defined by the RapidIO specification each Logical layer module has its own set of error conditions that can be detected and managed Maintenance Avalon MM Slave The Maintenance Avalon MM slave module creates request packets for the Avalon MM transaction on its slave interface and processes the response packets that it receives Anomalies are reported through one or more of the following three channels m Standard error management registers m Registers in the implementation defined space m The Avalon MM slave interface s error indication signal The following sections describe these channels Standard Error Management Registers The following standard defined error types can be declared by the Maintenance Avalon MM slave module The corresponding error bits are then set and the required packet information is captured in the appropriate error management registers m IO Error Response is declared when a response with ERROR status is received for a pending MAINTENANCE
48. available at www rapidio org Logical Layer Interfaces This section describes the features of the Logical layer module interfaces and how your system can interact with these interfaces to communicate with a RapidIO link partner The Logical layer consists of the following optional modules m I O slave and master modules that initiate and terminate NREAD NWRITE SWRITE and NWRITE R transactions m Maintenance module that initiates and terminates MAINTENANCE transactions m Doorbell module that transacts RapidIO DOORBELL messages m Avalon ST pass through interface for implementing your own custom Logical layer logic In addition the Logical layer provides an Avalon MM slave interface called the Register Access interface which provides access to all of the RapidIO IL IP core registers except the Doorbell Logical layer registers This interface is present in all RapidIO core variations RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 4 Functional Description 4 7 Logical Layer Interfaces Figure 4 3 shows a high level block diagram of the Logical layer with all of the Logical layer modules Figure 4 3 RapidlO Il IP Core Functional Block Diagram Register Access Maintenance Input Output Input Output Doorbell Slave Master Slave Master Slave Message Avalon ST Avalon MM Avalon MM Avalon MM Avalon MM Ava
49. available with the Altera software release v12 1 To compare the RapidIO II MegaCore function to previous releases of the RapidIO MegaCore function refer to Table B 1 and to the Altera documentation about the revision history of the RapidIO MegaCore function For information about the changes in the RapidIO MegaCore function in the different software releases refer to the Document Revision History table in the Additional Information chapter of the RapidIO MegaCore Function User Guide and to the Product Revision History section in the RapidIO chapter of the Altera Megacore IP Library Release Notes and Errata For information about changes to the RapidIO II MegaCore function in the different software releases refer to the Document Revision History table in Additional Information Table B 1 lists the major differences between these two MegaCore functions in the 12 1 software release Table B 1 Major Differences Between the RapidlO Il IP Core v12 1 and the RapidlO IP Core v12 1 Part 1 of 3 Property Protocol Device Support RapidlO II IP Core v12 1 Complies with RapidlO specification v2 2 Supports Arria V and Stratix V device families RapidlO IP Core v12 1 Complies with RapidlO specifications v1 3 and v2 1 Supports multiple legacy device families in addition to Arria V Cyclone V and Stratix V device families Lane support Supports 1x 2x and 4x variations Supports 1x and 4x variations Suppo
50. by performing the following tasks m For each incoming Avalon MM read request composes the RapidIO MAINTENANCE read request packet m For each incoming Avalon MM write request composes the RapidIO MAINTENANCE write request packet m Maintains status related to the composed MAINTENANCE packet to track responses m Presents the composed MAINTENANCE packet to the Transport layer for transmission on the RapidIO link At any time the Maintenance module can maintain a maximum of 64 outstanding MAINTENANCE requests that can be MAINTENANCE reads MAINTENANCE writes or port write requests The Maintenance module slave port asserts the mnt s waitrequest signal to throttle incoming requests above the limit Defining the Maintenance Address Translation Windows Two address translation windows available for interpreting incoming Avalon MM requests to the Maintenance module slave interface You must program the Tx Maintenance Window registers to support the address ranges you wish to distinguish The RapidIO II IP core Maintenance module populates the following RapidIO Type 8 Request packet fields with values you program for the relevant address translation window E prio WB destinationID E hop count You can disable an address translation window that is available in your configuration RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 4 Functional Description 4 35 Logical Layer Interfaces The RapidIO
51. core uses 8 bit or 16 bit device IDs whether the Transport layer has an Avalon ST pass through interface and where the RapidIO II IP core routes a request packet with a supported type but a destination ID not assigned to this endpoint Enable 16 Bit Device ID Width The Enable 16 bit device ID width setting specifies a device ID width of 8 bit or 16 bit RapidIO packets contain destination ID and source ID fields which have the specified width If this IP core uses 16 bit device IDs it supports large common transport systems If you turn on this option the IP core supports user logic that processes packets with 8 bit device IDs However if you turn off this option the RapidIO II IP core drops all incoming packets with a 16 bit device ID Refer to Transport Layer on page 4 59 RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 3 Parameter Settings 3 3 Logical Layer Settings Enable Avalon ST Pass Through Interface Turn on Enable Avalon ST pass through interface to include the Avalon ST pass through interface in your RapidIO II variation The Transport layer routes all unrecognized packets to the Avalon ST pass through interface Unrecognized packets are those that contain Format Types ftypes for Logical layers not enabled in this IP core or destination IDs not assigned to this endpoint However if you disable destination ID checking the packet is a request packet with a supported fty
52. corresponds to the 8 byte double word at RapidIO address N and the most significant half of the Avalon MM 128 bit word corresponds to the 8 byte double word at RapidIO address N 8 If two 8 byte double words appear in the RapidIO packet in the order dw0 followed by dw1 they appear on the 128 bit Avalon MM interface as the 128 bit word dw1 dw0 Table 4 1 shows the ordering of the bytes in each 8 byte double word Table 4 2 shows the ordering of the 8 byte double words in each 128 bit Avalon MM word Table 4 2 Double Word Ordering in a 128 Bit Avalon MM Interface Protocol RapidlO Protocol Second Transmitted Double Word 0 63 First Transmitted Double Word 0 63 Big Endian RapidlO Byte Address N 8 RapidlO Byte Address N 29 hn 3 b000 Avalon MM Protocol 64 Bit Double Word 63 0 64 Bit Double Word 63 0 Little Endian Avalon MM Byte Address N 8 Avalon MM Byte Address N Note to Table 4 2 1 Bit 0 of the RapidlO double word is transmitted first on the RapidlO link Avalon Streaming Avalon ST Interface The Avalon ST interface provides a standard flexible and modular protocol for data transfers from a source interface to a sink interface The Avalon ST interface protocol allows you to easily connect components together by supporting a direct connection to the Transport layer The Avalon ST interface is 128 bits wide This interface is available to create custom Logical layer functions like message passin
53. data is returned for the read operation The read data is checked after it is received by the DUT SWRITE Transactions The next set of operations performed are Streaming Writes SWRITE To perform SWRITE operations one register in the IP core must be reconfigured as shown in Table 7 2 Table 7 2 SWRITE Register Register Module Address Name Value Description Sets the DESTINATION ID for outgoing transactions Input Output to the value or depending on the 32 h00CD 0002 Or rio 0x1040C Slave Mapping 0002 device ID width of the sister_rio This value matches Window 0 Control the base device ID of the sister rio module Enables SWRITE Operations With the setting in Table 7 2 any write operation presented across the Input Output Avalon MM slave interface on the rio module is translated to a RapidIO Streaming Write transaction February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide Chapter 7 Testbench Testbench Sequence The Avalon MM write address must map into Input Output Slave Window 0 However in this example the window is set to cover the entire Avalon MM address space by setting the mask to all zeros The testbench generates a predetermined series of burst writes across the Avalon MM slave I O interface on the DUT These write bursts are each converted to an SWRITE request packet sent on the RapidIO serial interface Because Streaming Wri
54. device rd n 0 Input td n 0 Output February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 5 2 Chapter 5 Signals Physical Layer Signals Status Packet and Error Monitoring Signals Table 5 4 lists the status packet and error monitoring signals All of these signals are output signals synchronized with the sys_clk clock Table 5 4 Status Packet and Error Monitoring Output Signal Description packet transmitted Pulsed high for one clock cycle when a packet s transmission completes normally Pulsed high for one clock cycle when a packet s transmission is cancelled by sending a stomp packet cancelled restart from retry Or a link request control symbol packet accepted cs Pulsed high for one clock cycle when a packet accepted control symbol has been sent transmitted E Tm Pulsed high for one clock cycle when a packet accepted control symbol has been received received Lo UE Pulsed high for one clock cycle when a packet retry control symbol has been transmitted packet retry ce Pulsed high for one clock cycle when a packet retry control symbol has been received received packet not accepted Pulsed high for one clock cycle when a packet not accepted control symbol has been CS sent transmitted packet not accepted Pulsed high for one clock cycle when a packet not accepted control symbol has been received received packet crc error Pulsed hig
55. endpoint devices Large base _deviceID 15 0 The value of this field appears on the 16 hFFFF large base device id output signal RO Reserved if the system does not support 16 bit device ID Note to Table 6 36 1 In a small common transport system the Base deviceID field is Read Write and the Large base devicelID field is Read only In a large common transport system the Base deviceID field is Read only and the Large base devicelID field is Read Write Table 6 37 Host Base Device ID Lock CSR Offset 0x68 Field Bits Access Function Default RSRV 31 16 RO Reserved 16 h0 RW 0 This is the base device ID for the processing element that is initializing this processing element HOST BASE DEVICE ID 15 0 16 hFFFF Note to Table 6 37 1 Write once can be reset For more information refer to 83 5 2 of the Rapid O Interconnect Specification v2 2 Part 3 Common Transport Specification Table 6 38 Component Tag CSR Offset 0x6C Field Bits Access Function Default COMPONENT TAG 31 0 RW This is a component tag for the processing element 32 h0 February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 6 34 Chapter 6 Software Interface Transport and Logical Layer Registers Maintenance Interrupt Control Registers Table 6 39 and Table 6 40 describe the registers that relate to the Maintenance module interrupts If any of these e
56. every 1 s 34 8 h10 Decrement every 10 s 23496 8 h20 Decrement every 100 s 23496 8 h40 Decrement every 1000 s 34 8 h80 Decrement every 10 000 s 34 All other values are reserved RSRV 23 18 RO Reserved 6 h0 Specifies the additional incrementing of the ERR RATE COUNTER that is allowed beyond the current value of the Error rate failed threshold trigger ERR RATE FAILED THRESHOLD field of the Port 0 Error Rate Threshold CSR Table 6 82 This field ERR RATE RECOVERY 17 16 RW supports the following values 2011 2 b00 Can increment 2 errors about the specified threshold 2 b01 Can increment 4 errors above the specified threshold 2 b10 Can increment 16 errors above the specified threshold 2 b11 Do not limit incrementing the error rate count ERR RATE BIAS 31 24 RW February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 6 52 Chapter 6 Software Interface Transport and Logical Layer Registers Table 6 81 Port 0 Error Rate CSR Offset 0x368 Part 2 of 2 Doorbell Message Registers The RapidIO IP core has registers accessible by the Avalon MM slave port in the Doorbell module These registers are described in the following sections Table 6 83 Doorbell Message Module Memory Map Field Bits Access Function Default The highest value attained by ERR RATE COUNTER since the i PEAK ERR RATE 1
57. high Table 4 27 lists the fields of the gen rx hd data bus Table 4 27 RapidlO Header Fields in gen rx hd data Bus Field gen rx hd data Bits Value Comment pd size 8 0 114 106 Size of payload data in bytes vc 105 0 The RapidlO II IP core supports only VCO CRF 104 prio 1 0 103 102 tt 1 0 101 100 ftype 3 0 99 96 For packets with an 8 bit device ID bits 95 88 bits 35 80 15 8 of the destinationID are set to 8 100 When type 3 0 has the value of 7 this field is used as the tgtDestinationID field sourceID 15 0 79 64 For packets with 8 bit device ID bits 79 72 bits 15 8 of the sourcelD are set to 8 h00 63 0 nis format type specified in ftype February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 4 52 Table 4 28 lists the format of the specific header field Chapter 4 Functional Description Logical Layer Interfaces Table 4 28 specific header Fields in gen rx hd data Bus Part 1 of 2 ftype Field specific header Bits 3 0 63 60 size 3 0 59 56 transactionID 7 0 55 48 2 5 0r6 address 28 0 47 19 wdptr 18 xamsbs 1 0 17 16 Reserved 15 0 15 0 XON XOFF 63 FAM 2 0 62 60 7 Reserved 3 0 59 56 flowID 6 0 55 49 soc 48 Reser
58. indicates an address outside the range of the II IP core internal register set RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 4 Functional Description 4 43 Logical Layer Interfaces Figure 4 19 shows the signal relationships for an example sequence of three read requests that the RapidIO IP core presents on the Maintenance Avalon MM master interface and the data responses from user logic Figure 4 19 Read Transfers on the Maintenance Avalon MM Master Interface System clock mnt m waitrequest mnt m read mnt m address C mnt m readdatavalid NIU NIU X mnt m readdata MN NNNM In the first active clock cycle the RapidIO II IP core indicates the start of a read request by asserting the usr mnt read signal Simultaneously the IP core presents the target address on the usr mnt address address bus User logic presents the read responses on the Maintenance Avalon MM master interface by asserting the mnt readdatavalid signal while presenting the data on the usr mnt data bus Maintenance Packet Error Handling The Maintenance Interrupt register at 0x10080 and the Maintenance Interrupt Enable register at 0x10084 described in Table 6 39 and Table 6 40 determine the error handling and reporting for MAINTENANCE packets The following errors can also occur for MAINTENANCE packets A MAINTENANCE read or MAINTENANCE write requ
59. is assumed to contain well formed RapidIO packets with the following exceptions m The streaming data includes placeholder bits for the ackID field of the RapidIO packet but does not include the ackID value which is assigned by the IP core m The streaming data does not include the RapidIO packet CRC bits and padding bytes The Avalon ST pass through interface does not check the integrity of the streaming data but rather passes the bits on directly to the Transport layer The RapidIO II IP core fills in the ackID bits and adds the CRC bits and padding bytes before transmitting each packet on the RapidIO link Table 4 24 Avalon ST Pass Through Interface Transmit Side Avalon ST Sink Signals Part 1 of 2 Signal Name Type Function Indicates that the IP core is ready to receive data on the current clock cycle Asserted by the Avalon ST sink to mark ready cycles which are the cycles in which transfers can take place If ready is asserted on cycle N the cycle Output N READY LATENCY is a ready cycle In the RapidlO II IP core READY LATENCY is equal to 0 This signal may alternate between o and 1 when the Avalon ST pass through transmitter interface is idle Used to qualify all the other transmit side input signals of the Avalon ST gen tx valid Input pass through interface On every ready cycle in which gen tx validis high data is sampled by the IP core 1 Marks the active cycle containing the start of the packet The use
60. level output port m Four transmission queues and four retransmission queues to handle packet prioritization Physical Layer Interfaces Figure 4 24 shows the interfaces that the Physical layer supports Figure 4 24 Physical Layer High Level Block Diagram Transport Layer Register related 4 signals Status Packet Registers and Error Monitoring Signals l Low Latency sys_clk i MS gt Signals Low Level Interface Transmitter Receiver tx_clkout gt IX Clkout ix refcik td rd M Y M Y 2 RapidlO Interface Transceiver RapidlO Interface Signals Low level Interface Receiver The receiver in the low level interface receives the input from the RapidIO interface and performs the following tasks Separates packets and control symbols Removes IDLE2 idle sequence characters Detects multicast event and stomp control symbols Detects packet size errors Checks the control symbol 13 bit CRC and asserts symbol errorif the CRC is incorrect Receiver Transceiver The receiver transceiver is an embedded Altera Transceiver Native PHY IP core T For information about the Altera Transceiver Native PHY IP core refer to the Altera Transceiver PHY IP Core User Guide February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 4 64 Chapter 4 Func
61. m x4 RapidlO II reconfig from xcvr N 1 0 reconfig_fromgxb 3N 1 2N IP Core reconfig to xcvr M 1 0 gt reconfig_togxb 3M 1 2M Altera 1 Transceiver reconfig from xcvr N 1 0 m reconfig fromgxb 4N 1 3N Reconfiguration reconfig to xcvr M 1 0 gt reconfig_togxb 4M 1 3M Controller reconfig from xcvr N 1 0 q reconfig_fromgxb 5N 1 4N 0 reconfig to xcvr M 1 0 gt reconfig_togxb 5M 1 4M ig to xcvr reconfig recon from xcvr N 1 0 Le 3 reconfig_fromgxb N 1 0 M 1 0 reconfig togxb M 1 0 1 RapidlO II reconfig from xcvr N 1 0 lt q reconfig_fromgxb 2N 1 N IP Core reconfig to xcvr M 1 0 p reconfig_togxb 2M 1 M reconfig fromgxb N 1 0 reconfig from xcvr N 1 0 x1 RapidlO Il reconfig_togxb M 1 0 e reconfig to xcvr M 1 0 IO reconfig fromgxb 2N 1 N L reconfig from xcvr N 1 0 Altera reconfig togxb 2M 1 M q reconfig to xcvr M 1 0 Transceiver Reconfiguration reconfig_fromgxb N 1 0 __y reconfig from xcvr N 1 0 Controller x1 RapidlO reconfig togxb M 1 0 reconfig to xcvr M 1 0 1 IP Core reconfig_fromgxb 2N 1 N _y reconfig from xcvr N 1 0 reconfig togxb 2M 1 M Le reconfig to xcvr M 1 0 Refer to Table 5 7 on page 5 4 for the values of N and M in Figure 2 3 Refer to the Transceiver R
62. on page 6 26 CAR Assembly ID Assembly ID corresponds to the AssyIdent ity field of the Assembly Identity register Table 6 24 which uniquely identifies the type of assembly This field is assigned and managed by the vendor specified in the AssyVendorIdentity field of the Assembly Identity register Assembly Vendor ID Assembly Vendor ID uniquely identifies the vendor who manufactured the assembly This value corresponds to the AssyVendorIdentity field of the Assembly Identity register Assembly Information CAR The Assembly Information CAR options identify the vendor who manufactured the assembly or subsystem of the device and the pointer to the first entry in the Extended Features list and sets these values in the Assembly Information Table 6 25 CAR Revision ID Revision ID indicates the revision level of the assembly and sets the AssyRev field of the Assembly Information CAR Table 6 25 In the Osys design flow this parameter is labeled Assembly revision ID Extended Features Pointer The ExtendedFeaturesPtr in the Assembly Information CAR is set to the value of 0x100 which is the offset for the LP Serial Extended Features block refer to Table 6 2 on page 6 2 The parameter is mislabeled you cannot modify the value of the ExtendedFeaturesPtr in the Assembly Information CAR Instead Extended features pointer points to the final entry in the extended features list This parameter supports the addition of custom
63. port does not support a 4x RapidlO link 1 b1 This port supports a 4x RapidlO link Width of the port after being initialized 3 b000 Single lane port lane 0 3 b001 Single lane port lane R redundancy lane 3 b010 Four lane port 3 b011 Two lane port INTI WIDIH 29 27 RO 3 b100 Eight lane port 3 b101 Sixteen lane port 3 b110 3 b111 Reserved This field is reset to the largest supported port width which can be any of 3 b000 3 b010 and 3 b011 based on your selection in the RapidlO II parameter editor Together with the EXTENDED PWIDTH OVRIDE field bits 15 14 indicates soft port configuration to control the width modes available for port initialization m When bit 26 has the value of 1 b0 bits 15 14 are Reserved m When bit 26 has the value of 1 b1 m Bit 25 is the Enable bit for 4x mode m Bit 24 is the Enable bit for 2x mode m Bit 15 is the Enable bit for 8x mode m Bit 14 is the Enable bit for 16x mode The RapidlO II IP core supports the following valid values for PWIDTH OVRIDE 26 24 RW PWIDTH OVRIDE EXTENDED PWIDTH OVRIDE 3 b000 5 b000xx All lane widths that the port supports are enabled 5 b010xx Force single lane lane R not forced 5 b011xx Force single lane force lane R 5 b10100 2x mode is enabled 4x mode is disabled 5 b11000 4x mode is enabled 2x mode is disabled 5 b11100 2x and 4x modes are enabled All other values are Reserved When the va
64. read or write request m Unsolicited Response is declared when a response is received that does not correspond to any pending MAINTENANCE read or write request m Packet Response Timeout is declared when a response is not received within the time specified by the Port Response Time Out CSR Table 6 8 on page 6 8 for a pending MAINTENANCE read or write request February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 4 68 Chapter 4 Functional Description Error Detection and Management m Illegal Transaction Decode is declared for malformed received response packets occurring from any of the following events m Response packet to pending MAINTENANCE read or write request with status not DONE nor ERROR m Response packet with payload with a transaction type different from MAINTENANCE read response m Response packet without payload with a transaction type different from MAINTENANCE write response m Response to a pending MAINTENANCE read request with more than 32 bits of payload The RapidIO core issues only 32 bit MAINTENANCE read requests Registers in the Implementation Defined Space The Maintenance register module defines the Maintenance Interrupt register Table 6 39 on page 6 34 in which the following two bits report Maintenance Avalon MM slave related error conditions WRITE OUT OF BOUNDS READ OUT OF BOUNDS These bits are set when the address of a write or read transfer on the Maintenan
65. registers using the Register Access interface When the RapidIO II IP core receives a MAINTENANCE port write request packet on the RapidIO link it processes the transaction according to the values you program in the receive port write registers and if you have enabled this interrupt signal asserts the mnt_mnt_s_irg signal to inform the system that the IP core has received a port write transaction IP Core Actions The port write processor in the Maintenance module performs the following tasks m Composes the RapidIO MAINTENANCE port write request packet m Presents the port write request packet to the Transport layer for transmission Processes port write request packets received across the RapidIO link from a remote device m Alerts the user of a received port write using the mnt mnt s irqsignal Port Write Transmission To send a RapidIO MAINTENANCE port write packet to a remote device you must program the transmit port write control and data registers The Tx Port Write Control register is described in Table 6 45 on page 6 36 and the Tx Port Write Buffer RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 4 Functional Description 4 37 Logical Layer Interfaces is described in Table 6 47 on page 6 36 You access these registers using the Register Access Avalon MM slave interface You must program the values for the following header fields in the corresponding fields in the Tx Port Write Control r
66. request has not been received within the specified time out interval Set when the message_request_timeout_set input signal changes value from 0 to 1 1 b0 PKT RSP TIMEOUT 0 24 RO A required response has not been received within the specified time out interval Set when the RapidlO II IP core detects this situation or when the slave packet response timeout set input signal changes value from 0 to 1 1 b0 UNSOLICIT RSP 23 RO 1 Received an unsolicited or unexpected response packet I O message or GSM logical for endpoints Maintenance for switches Set when the RapidlO II IP core detects this situation or when the unsolicited response set input signal changes value from 0 to 1 1 b0 UNSUPPORT TRAN 22 RO Received a transaction that is not supported in the Destination Operations CAR Set when the RapidlO II IP core detects this situation or when the unsupported transaction set input signal changes value from 0 to 1 MISSING DATA STRM CNTXT 2 February 2013 Altera Corporation 21 RO Received a continuation or end data streaming segment for a closed or non existent segmentation context Set when the missing data streaming context set input signal changes value from 0 to 1 RapidlO II MegaCore Function User Guide Chapter 6 Software Interface Transport and Logical Layer Registers Table 6 67 Logical Transport Layer Error Detect CSR Offset
67. s ad ress signals until one clock cycle after the IP core deasserts the mnt s waitrequest signal In the following clock cycle user logic sends the next read request which the IP core also throttles for four clock cycles The RapidIO II IP core presents the read responses it receives on the RapidIO link as read data responses on the Maintenance Avalon MM slave interface The IP core presents the read data responses in the same order it receives the original read requests by asserting the mnt s readdatavalid signal while presenting the data on themnt s data bus The RapidIO II IP core converts the read requests to RapidIO transactions Table 4 20 lists the fields in the corresponding RapidIO transactions Table 4 20 Maintenance Read Request Transmit Example RapidlO Packet Fields Part 1 of 2 Field Value Comment Value is written by the Physical layer before the packet is transmitted on the REMO 6h00 mabidlO link vc 0 The RapidlO II IP core supports only VCO CRF 0 The IP core assigns to this field the value programmed in the PRIORITY field of the Tx Maintenance Mapping Window n Control register Table 6 44 on prio 1 0 page 6 35 for the matching address translation window n Refer to Defining the Maintenance Address Translation Windows on page 4 34 for matching details tt 1 0 2 b01 The value of 1 indicates 16 bit device IDs ftype 3 0 4 b1000 The value of 8 indicates a Maintenance Clas
68. sister rio module The two instances are interconnected through their high speed serial interfaces In the testbench each IP core s td output is connected to the other IP core s rd input The sister rio module named sis rio inst responds to transactions initiated by the DUT and generates transactions to which the DUT responds Bus functional models BFM are connected to the Avalon MM and Avalon ST interfaces of both the DUT and sister rio modules to generate transactions to which the link partner responds when appropriate and to monitor the responses Figure 7 1 is a block diagram of the testbench in which all of the available Avalon MM interfaces are enabled The two IP cores communicate with each other using the Serial RapidIO interface The testbench initiates the following transactions at the DUT and targets them to the sister rio module E SWRITE E NWRITE R E NWRITE E NREAD February 2013 Altera Corporation II MegaCore Function User Guide 7 2 DOORBELL messages MAINTENANCE writes and reads MAINTENANCE port writes and reads Chapter 7 Testbench Testbench Overview Type 9 Data Streaming transactions using the Avalon ST interface 5 Your specific variation may not have all of the interfaces enabled If an interface is not enabled the transactions supported by that interface are not exercised by the testbench In addition the RapidIO II IP core modules implement the following features m Mult
69. table shows the typographic conventions this document uses Visual Cue Meaning Indicate command names dialog box titles dialog box options and other GUI Capital labels For example Save As dialog box For GUI elements capitalization matches Leners the GUI Indicates directory names project names disk drive names file names file name bold type extensions software utility names and GUI labels For example qdesigns directory D drive and chiptrip gdf file February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide Info 2 Additional Information Typographic Conventions Visual Cue Italic Type with Initial Capital Letters Meaning Indicate document titles For example Stratix IV Design Guidelines italic type Indicates variables For example n 1 Variable names are enclosed in angle brackets For example file name and lt project name pof file Initial Capital Letters Subheading Title Indicate keyboard keys and menu names For example the Delete key and the Options menu Quotation marks indicate references to sections in a document and titles of Quartus Help topics For example Typographic Conventions Courier type Indicates signal port register bit block and primitive names For example data1 tdi and input The suffix n denotes an active low signal For example resetn Indicates command line com
70. the appropriate range to the local register set internally m Fully complies with Part 8 Error Management Extensions Specification of the RapidlO Interconnect Specification Revision 2 2 m Supports the LP Serial Lane Extended Features registers described in Rapid O Interconnect Specification v2 2 Part 6 LP Serial Physical Layer Specification for up to four lanes with two implementation specific registers per lane m Various register field differences with RapidlO IP core m For example the NWRITE RS COMPLETED field the 1 0 Slave Interrupt and I O Slave Interrupt Enable registers is not available in the RapidlO II IP core However these two registers support INVALID READ BYTEENABLE and INVALID READ BURSTCOUNT interrupts m For example the information found in the PROMISCUOUS MODE field of the Rx Transport Control register in the RapidlO IP core is found in the DIS DEST ID CHK field of the Port 0 Control CSR the RapidlO II IP core which has no Rx Transport Control register For details of the registers in the RapidlO II IP core refer to Chapter 6 Software Interface Requires that your system connect the Maintenance master interface to the Register Access slave interface The RapidlO IP core does not implement this routing internally The RapidlO IP core implements a subset of the optional Error Management Extensions as defined in Part 8 of the RapidlO Interconnect Specification Revision 2
71. the following substitution In step 3 instead of typing the name of the transceiver serial data input node type the name of the transceiver serial data output put node This name is the variation specific version of the td signal Compiling the Full Design and Programming the FPGA You can use the Start Compilation command on the Processing menu in the Quartus IT software to compile your design After successfully compiling your design program the targeted Altera device with the Programmer and verify the design in hardware February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 2 8 Chapter 2 Getting Started Instantiating Multiple RapidlO II IP Cores Before compiling your design in the Quartus II software you must perform the modifications described in Adding Transceiver Analog Settings on page 2 7 For Information About Refer To Quartus Il Incremental Compilation for Hierarchical and Team Compiling your design Based Design chapter in volume 1 of the Quartus II Handbook Device Programming section in volume 3 of the Quartus II Programming the device Handbook Instantiating Multiple RapidlO II IP Cores If you want to instantiate multiple RapidIO II IP cores a few additional steps are required The following sections outline these steps Clock and Signal Requirements The transceivers are configured with the Altera Native PHY IP core When your design contains multiple RapidIO II IP c
72. the lane is assigned Port Number 31 24 RO The RapidlO II IP core implements only a single RapidlO port so this 8 hO field always has the value of 0 Lane Number 23 20 RO The number of the lane in the port 4 hn Transmitter type Transmitter 19 RO 1 b0 Short run 1 1 b1 Long run This value is identical for all lanes of the port Transmitter operating mode 1 b0 Short run Transmitter 18 Ei 1 b1 Long run Mode The value in this field is identical for all lanes and is identical to the value ofthe Transmitter Type field The value in this field does not affect the physical transceiver Software must modify this bit if relevant physical transceiver properties change Receiver type 2 b00 Short run 2 b01 Medium run Receiver Type 17 16 RO 1 2 b10 Long run 2 b11 Reserved This value is identical for all lanes of the port Indicates that the lane receiver has detected that the polarity of its input Receiver signal is inverted and has inverted the receiver input to correct the Input 15 RO polarity A value of 1 bO indicates the receiver input is not inverted 1 b0 Inverted The RapidlO II IP core does not support automatic detection of inverted inputs and this field always has the value of 0 RapidlO II MegaCore Function User Guide February 2013 Altera Corporation Chapter 6 Software Interface 6 21 Physical Layer Registers Table 6 17 LP Serial La
73. then sends an input status link request control symbol to which the receiver responds with link response control symbol to indicate which packet requires transmission The input and output error detection and recovery state machines can be monitored by software that you create to read the status of the Port 0 Error and Status CSR Table 6 14 on page 6 12 In addition to the registers defined by the specification the RapidIO II IP core provides several output signals that enable user logic to monitor error detection and the recovery process Refer to Status Packet and Error Monitoring Signals on page 5 2 Protocol Violations Some protocol violations such as a packet with an unexpected ackID or a time out on a packet acknowledgment can use the same error recovery mechanisms as the transmission errors described in Physical Layer Error Management on page 4 65 Some protocol violations such as a time out on a link request or the RapidIO II IP core receiving a link response with an ackID outside the range of transmitted ackIDs can lead to unrecoverable or fatal errors Fatal Errors Software determines the behavior of the RapidIO II IP core following a fatal error For example you can program software to optionally perform any of the following actions among others m Set the PORT DIS bit of the Port 0 Control CSR Table 6 15 on page 6 16 to force the initialization state machine to the SILENT state m Write to the OUTSTAN
74. times in succession To perform this verification the test invokes the read data task defined in the instance drbl master bfm The test waits for the DUT to assert the drbell s irqsignal which indicates that a DOORBELL message has been received The test then reads the five received DOORBELL messages by calling the read write task with a READ operation to the Rx DOORBELL register at offset 0x0000 0000 The task is called five times once for each message to return the received DOORBELL message Port Write Transactions To test port writes the test performs some basic configuration of the port write registers in the DUT and the sister rio module It then programs the DUT to transmit port write request packets to the sister rio module The port writes are received by the sister rio module and retrieved by the test program The configuration enables the RX PACKET STORED interrupt in the sister rio module If this interrupt is enabled the sister rio module asserts its mnt s irqsignal when the sister rio module receives a Port Write transaction and the payload can be retrieved To enable the interrupt the testbench calls the sister sys mnt master bfm read write cmd task A write operation is performed by the task with the address 0x10084 and data 0x10 passed as parameters In addition the sister rio module must be enabled to receive Port Write transactions from the DUT The task is called with the address 0x10250 and data 0x
75. user defined registers to your RapidIO IP core This parameter sets the value of one of the following two register fields RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 3 Parameter Settings 3 7 Capability Registers Settings m Ifyou do not instantiate the Error Management Extension registers refer to Error Management Registers Settings on page 3 11 this parameter determines the value of the EF PTR field of the LP Serial Lane Extended Features Block Header register at offset 0x200 Table 6 16 on page 6 20 m If you instantiate the Error Management Extension registers in your RapidIO II IP core variation this parameter determines the value of the EF PTR field of the Error Management Extensions Block Header register at offset 0x300 Table 6 66 on page 6 42 Processing Element Features CAR The Processing Element Features CAR Table 6 26 on page 6 26 identifies the major features of the processing element Bridge Support Bridge support when turned on sets the Bridge bit in the Processing Element Features CAR and indicates that this processing element can bridge to another interface such as PCI Express a proprietary processor bus such as Avalon MM DRAM or other interface Memory Access Memory access when turned on sets the Memory bit in the Processing Element Features CAR and indicates that the processing element has physically addressable local address space that can be accesse
76. 0 where C is the number of channels 1 2 or sd t lint 4 This width supports communication from an Altera Reconfiguration ye Controller with C 1 reconfiguration interfaces one dedicated to each channel and another for the transceiver PLL to the transceiver If you omit the Altera Reconfiguration Controller from your simulation model you must ensure all bits of this bus are tied to 0 For more information about the Altera Reconfiguration Controller component refer to the A fera Transceiver PHY IP Core User Guide Driven to an external dynamic reconfiguration block The bus identifies the transceiver channel whose settings are being transmitted to the dynamic reconfiguration block If no external dynamic reconfiguration block is used then this output bus can be left unconnected 1 Output The width of this bus is C 1 x 46 where C is the number of channels 1 2 or recontig_ trom xevr p 4 This width supports communication from the transceiver to C 1 reconfiguration interfaces in an Altera Reconfiguration Controller one interface dedicated to each channel and an additional interface for the transceiver PLL For more information about the Altera Reconfiguration Controller component refer to the Altera Transceiver PHY IP Core User Guide tx cal busy n 0 Output rx cal busy n 0 Output pll locked Output Type input As documented in the device family specific Native PHY IP core chapters and the Transceive
77. 0000 0 0001 0 1 0000 0000 1000 0000 0 0000 0 1 0000 0001 0000 0000 1 0011 1 1 0000 0010 0000 0000 1 0010 1 1 0000 0100 0000 0000 1 0001 1 1 0000 1000 0000 0000 1 0000 1 1 0001 0000 0000 0000 0 0011 1 1 0010 0000 0000 0000 0 0010 1 1 0100 0000 0000 0000 0 0001 1 1 1000 0000 0000 0000 0 0000 1 1 0000 0000 0000 0011 1 0110 0 1 0000 0000 0000 1100 1 0100 0 1 0000 0000 0011 0000 0 0110 0 1 0000 0000 1100 0000 0 0100 0 1 0000 0011 0000 0000 1 0110 1 1 0000 1100 0000 0000 1 0100 1 1 0011 0000 0000 0000 0 0110 1 1 1100 0000 0000 0000 0 0100 1 1 0000 0000 0000 1111 1 1000 0 1 0000 0000 1111 0000 0 1000 0 1 0000 1111 0000 0000 1 1000 1 1 1111 0000 0000 0000 0 1000 1 1 0000 0000 1111 1111 0 1011 0 1 1111 1111 0000 0000 0 1011 1 1 1111 1111 1111 1111 1 1011 0 Note to Table 4 10 1 Forread transfers the 1 0 Logical layer slave module does not handle byteenable values and byteenable burstcount combinations that the Avalon MM interface does not allow In case of an invalid combination the RapidlO II IP core asserts the ios rd wr readresponse signal when it asserts the ios rd wr readdatavalid signal and sets the INVALID READ BYTEENABLE bit of the 1 0 Slave Interrupt register Table 6 60 on page 6 40 if this interrupt is enabled in the 1 0 Slave Interrupt Enable register Table 6 61 page 6 40 RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 4 Functional Description Logical L
78. 0x308 1 Part 2 of 2 Field Bits Access Function Default Received an initial or single data streaming segment for an OPEN EXSTG DATA STRM 20 ROW already open segmentation context Set when the 1 bo CNTXT 2 open existing data streaming context set input signal changes value from 0 to 1 Received a data streaming segment with a payload size greater LONG DATA STRM SGMNT t9 ROM than the MTU Set when the 1 b0 2 long data streaming segment set input signal changes value from 0 to 1 Received a non final data streaming segment with a payload size SHRT DATA STRM SGMNT 18 ROM less than the MTU Set when the 1 bo 2 short_data_streaming_segment_set input signal changes value from 0 to 1 The length of a reassembled PDU differs from the PDU length specified in the end data streaming segment packet header Set 2 1 DS PDU DEN ERR DOE BS whenthe data streaming pdu length error set input kag signal changes value from 0 to 1 RSRV 16 8 RO Reserved 9 ene Specific 7 0 RO This feature is not supported 8 b0 Notes to Table 6 67 1 To clear bits in the Logical Transport Layer Error Detect CSR write the value of 32 h0000 to the register You cannot clear the bits individually 2 This error is registered for endpoint devices only Table 6 68 Logical Transport Layer Error Enable CSR Offset 0x30C Part 1 of 3 Field Bits Access Fu
79. 1 After the configuration is complete the test performs the operations listed in Table 7 5 Table 7 5 Port Write Test Places data into the TX PORT WRITE BUFFER Operation Action Write incrementing payload to registers at addresses 0x10210 t0 0x1024C Write DESTINATION ID OxCD Or OxCDCD Indicates to the DUT that Port Write data is ready depending on the device ID width setting and PACKET READY 0x1 to 0x10200 Waits for the sister rio module to receive the port write Monitor the sister rio module mnt mnt s irq signal Verifies that the sister rio module has the interrupt bit PACKET STORED Set Read register at address 0x10080 Retrieves the Port Write payload from the sister rio module and checks for data integrity Read registers at addresses 0x10260 0x1029C Checks the sister rio module Rx Port Write Status register for correct payload size Read register at address 0x10254 February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 7 10 Chapter 7 Testhench Testbench Completion Table 7 5 Port Write Test Operation Action Clears the PACKET STORED interrupt in the sister rio module Write 1 to bit 4 of register at address 0x10080 Waits for the next interrupt at the sister rio module a The testbench performs this test five times All testbench port write operations have a payload of 32 bytes Each operation is performed one of the s
80. 111 1100 0000 0000 1 0 1 0000 0000 0011 1111 1 1 0011 1111 0000 0000 0 0 1 0000_0000_1111_1110 1010 0 1 1 0000 0000 0111 1111 1 0 1 1111 1110 0000 0000 1 1 0111 1111 0000 0000 0 0 1 0000_0000_1111_1111 4011 1 1 1111_1111_0000_0000 1 0 1 1111 1111 1111 1111 1 2 1100 6 0 0 2 1111 1111 1111 1111 1 0 4 1111 1111 1111 1111 11016 0 0 6 1111 1111 1111 1111 1 0 8 1111 1111 1111 1111 11106 0 0 10 1111 1111 1111 1111 1 0 12 1111 1111 1111 1111 11116 0 0 14 1111 1111 1111 1111 1 0 16 1111 1111 1111 1111 Notes to Table 4 6 1 The RapidlO link partner should avoid read requests with this rdsize value because the resulting byteenable value is not allowed by the Avalon MM specification However if the RapidlO II IP core receives a read request with this rdsize value the IP core issues these transactions on the 1 0 Logical layer Avalon MM master interface with the illegal byteenable values to support systems in which user logic handles these byteenable values N This combination of wdptr and rdsize values is reserved If the RapidlO II IP core receives this combination it sets the Unsupported Transaction bit UNSUPPORT_TRAN in the Logical Transport Layer Error Detect CSR Table 6 67 on page 6 43 and returns an ERROR response If rdsize has a value greater than 4 b1011 and address 0 has the value of 1 the RapidlO II IP core sets the Unsupported Transaction bit UNSUPPORT TRAN in the Logical Transpor
81. 167 maon wdptr wrsize address 0 128 bit u nit s Initial Final 1 bx 4 bxxxx rio_addr 3 FFOO OOFF 1 1011 1 2 FFFF 0 1100 1 FFFF OOFF 0 1100 0 FFFF 0 1100 0 FFOO OOFF 0 1100 1 3 FFFF 1 1100 1 FFFF OOFF 1 1100 0 FFFF 1 1100 0 FFOO OOFF 1 1100 1 4 FFFF 1 1100 1 FFFF OOFF 1 1100 0 FFFF 1 1100 0 FFOO OOFF 1 1100 1 5 FFFF 1 1101 1 EFEF OOFF 1 1101 0 FFFF 1 1101 0 FFOO OOFF 1 1101 1 6 FFFF 1 1101 1 FFFF OOFF 1 1101 0 FFFF 1 1101 0 FFOO OOFF 1 1101 1 7 FFFF 1 1101 1 EFEF OOFF 1 1101 0 FFFF 1 1101 0 FFOO OOFF 1 1101 1 8 FFFF 1 1101 1 FFFF OOFF 1 1101 0 FFFF 1 1101 0 FFOO OOFF 1 1101 1 9 FFFF 1 1111 1 EFEF OOFF 1 1111 0 FFFF 1 1111 0 FFOO OOFF 1 1111 1 10 11 16 FFFF 1 1111 1 5 FFFF OOFF 1 1111 0 FFFF 1 1111 0 RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 4 Functional Description 4 31 Logical Layer Interfaces Table 4 12 1 0 Logical Layer Slave Write Request Size Encoding Il Part 2 of 2 Avalon MM Signal Values 1 RapidlO Header Field Values jii rg byteenable 16 wdptr wrsize address 0 128 hit units Initial Final 1 bx 4 bxxxx rio addr 3 17 FFOO OOFF 1 1111 1 Note to Table 4 12 1 The 1 0 Logical layer slave module does not handle byteenable values and byteenable burstcount combinations that the Avalon MM interface does not allow In case of an invalid byteenable or burstcount value the RapidlO II IP core sets the INVALI
82. 2 Send MAINTENANCE read request 16 0 Receive MAINTENANCE read response 16 32 Receive MAINTENANCE read request 16 0 Send MAINTENANCE read response 16 32 User Sending MAINTENANCE Write Requests Table 4 16 lists the Maintenance Avalon MM interface usage example this section describes Table 4 16 Maintenance Interface Usage Example Sending MAINTENANCE Write Request User Operation Device ID Width Payload Size Bytes _ To write to a register in a remote endpoint using a MAINTENANCE write request you must perform the following actions 1 Set up the registers 2 Perform a write transfer on the Maintenance Avalon MM slave interface Figure 4 16 shows the behavior of the signals for four write transfers on the Maintenance Avalon MM slave interface Figure 4 16 Write Transfers on the Maintenance Avalon MM Slave Interface sse TU UU UU UU UU UU UU UU U UU UU UU mnt_s_waitrequest J J NN mnt s write L mnt_s_address J 0x4 0x8 0xC mnt s writedata 2 sznscscscsc 32nBEEFBEEF 2 In the first active clock cycle of the example user logic specifies the active transaction to be a write request by asserting the mnt s write signal while specifying the write data on the mnt s writedata signal and the target address for the write data on the mnt s address signal However the RapidIO II IP core throttles the incoming transaction by a
83. 2013 Altera Corporation User Guide Chapter 4 Functional Description 4 9 Logical Layer Interfaces The interface supports the following interrupt lines std reg mnt irq when enabled the interrupts registered in the CSRs and Error Management registers assert the std reg mnt irqsignal io m mnt irq this interrupt signal reports interrupt conditions related to the I O Avalon MM master interface When enabled the interrupts registered in the Input Output Master Interrupt register at offset 0x103DC assert the io m mnt signal io s mnt irq this interrupt signal reports interrupt conditions related to the I O Avalon MM slave interface When enabled the interrupts registered in the Input Output Slave Interrupt register at offset 0x10500 assert the io s mnt irq signal mnt mnt s irg this interrupt signal reports interrupt conditions related to the Maintenance interface slave port When enabled the interrupts registered in the Maintenance Interrupt register at offset 0x10080 assert the mnt s irqsignal Input Output Logical Layer Modules This section describes the following Input Output Logical layer modules m Input Output Avalon MM Master Module m Input Output Avalon MM Slave Module on page 4 19 Input Output Avalon MM Master Module The Input Output I O Avalon MM master Logical layer module is an optional component of the I O Logical layer This module receives RapidIO read and write request pack
84. 25 Gbaud operation 1 b1 6 25 GB ENABLE 16 RW Indicates whether port operation at 6 25 Gbaud is enabled in the RapidlO implementation 1 b0 The IP core cannot support 6 25 Gbaud operation 1 b1 The IP core can support 6 25 Gbaud operation This field can only have this value if 6 25 GB SUPPORT has the value of 1 1 b1 RSRV 15 4 RO Reserved 12 b0 INACTIVE LNS EN RO Indicates whether the RapidlO implementation supports enabling inactive lanes for testing The RapidlO II IP core does not support enabling inactive lanes for testing so this bit always has the value of 0 1 b0 February 2013 Altera Corporation RapidlO II MegaCore Function User Guide 6 12 Chapter 6 Software Interface Physical Layer Registers Table 6 13 Port 0 Control 2 CSR Offset 0x154 1 Part 3 of 3 Field Bits Access Function Default Indicates whether data scrambling is disabled 1 b0 The transmit scrambler and the receive descrambler enabled 1 b1 The transmit scrambler and the receive descrambler are DATA SCRMBL DIS 2 RW disabled However the transmit scrambler remains enabled for the 1 b0 generation of pseudo random data characters for the IDLE2 random data field This bit is for test use only Do not assert this bit during normal operation Indicates whether the port can transmit commands to control the transmit emphasis in the connect
85. 3 0 63 60 4 b1000 data payload The value of 0 indicates Done The current packet Status 3 0 59 56 200000 successfully completes the requested transaction Value in the response packet matches the transactionID 7 0 55 48 transactionID of the corresponding request packet Reserved 47 0 47 0 48 h0 RapidlO II MegaCore Function User Guide February 2013 Altera Corporation Chapter 4 Functional Description 4 51 Logical Layer Interfaces User Receiving Read Request and Sending Read Response Table 4 33 lists the Avalon ST pass through interface usage example this section describes Refer to Transaction ID Ranges on page 4 48 and Receiver on page 4 60 for a description of the RapidIO core variations in which this example transaction is processed through the Avalon ST pass through interface rather than being processed through one of the I O Logical layer modules Table 4 33 Avalon ST Pass Through Interface Usage Example Receiving NREAD Request and Sending Response Operation fe Device ID Payload Size User Operation Type RapidlO Transaction Priority Width Bytes Receive read request Rx NREAD 1 16 32 Send read response Tx Response with payload 2 16 32 Figure 4 22 shows the behavior of the signals on the Avalon ST pass through interface for this example transaction sequence Figure 4 22 Avalon ST Pass Through Interface NREAD Request Receive and Respon
86. 32 bits wide Data Streaming Logical Layer Control CSR The Data Streaming Logical Layer Control CSR is described in Table 6 32 on page 6 31 Supported Traffic Management Types Reset Value Supported traffic management types reset value sets the reset value of the TM TYPE SUPPORT field of the Data Streaming Logical Layer Control CSR Traffic Management Mode Reset Value Traffic management mode reset value sets the reset value of the TM_MODE field of the Data Streaming Logical Layer Control CSR Maximum Transmission Unit Reset Value Maximum transmission unit reset value sets the reset value of the MTU field of the Data Streaming Logical Layer Control CSR Port General Control CSR The Port General Control CSR is described in Table 6 9 on page 6 8 Host Reset Value Host reset value sets the reset value of the HOST field of the Port General Control CSR RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 3 Parameter Settings 3 11 Error Management Registers Settings Master Enable Reset Value Master enable reset value sets the reset value of the ENA field of the Port General Control CSR Discovered Reset Value Discovered reset value sets the reset value of the DISCOVER field of the Port General Control CSR Port 0 Control CSR The Port 0 Control CSR is described in Table 6 15 on page 6 16 Flow Control Participant Reset Value Flow control participant reset value sets the reset v
87. 330 0x10340 0x10350 0x10360 0x10370 0 10380 0x10390 0x103A0 0x103B0 0x103C0 0x103D0 0x103E0 0 103 0 Field Bits Access Function Default Start of the RapidlO address window to be mapped The four BASE 31 4 RW least significant bits of the 34 bit base are assumed to be 28 h0 Zeros RSRV 3 2 RO Reserved 2 b0 XAMB 1 0 RW Extended Address two most significant bits of the 34 bit base 2 ho Table 6 52 Input Output Master Mapping Window n Mask Offset 0x10304 0x10314 0x10324 0x10334 0x10344 0x10354 0x10364 0x10374 0x10384 0x10394 0 103 4 0x103B4 0x103C4 0x103D4 0 103 4 0x103F4 Field Bits Access Function Default Bits 31 to 4 of the mask for the address mapping window The MASK 31 4 RW four least significant bits of the 34 bit mask are assumed to be 28 ho zeros RSRV 3 RO Reserved 1 b0 2 RW Window enable Set to one to enable the corresponding window ZANM 1 0 RW Extended Address two most significant bits of the 34 bit es mask February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 6 38 Chapter 6 Software Interface Transport and Logical Layer Registers Table 6 53 Input Output Master Mapping Window n Offset Offset 0x10308 0x10318 0x10328 0x10338 0x10348 0x10358 0x10368 0x10378 0 10388 0x10398 0x103A8 0x103B8 0x103C8 0x103D8 0x103E8 0x103F8 Field Bits Access Fun
88. 5 8 RW field was last reset 8 h0 The number of Physical layer errors that have been detected by the IP core counting the errors enabled by the Port 0 Error ERR RATE COUNTER 7 0 RW Rate Enable CSR saturated according to the 8 0 ERR_RATE_RECOVERY mechanism and decremented by the ERR_RATE_BIAS mechanism Provides an indication of the Physical layer error rate Table 6 82 Port 0 Error Rate Threshold CSR Offset 0x36C Field Bits Access Function Default Threshold value for reporting to the system host an error ERR RATE FAILED THRESHOLD 31 24 RW condition due to a possibly broken link The value of 0 8 hFF indicates the threshold is disabled Threshold value for reporting to the system host an error ERR RATE DEGR THRESHOLD 23 16 RW condition due to a degrading link The value of O indicates 8 hFF the threshold is disabled RSRV 15 0 RO Reserved 16 h0 Refer to Doorbell Module on page 4 43 for a detailed explanation of the DOORBELL messaging support Address Name Used by Doorbell Message Space 0x10600 Rx Doorbell 0x10604 Rx Doorbell Status 0x10608 Tx Doorbell Control 0x1060C Tx Doorbell 0x10610 Tx Doorbell Status External Avalon MM master that generates or receives 0x10614 Tx Doorbell Completion doorbell messages 0x10618 Completion 0x1061C Tx Doorbell Status Control 0x10620 Doorbell Interrupt Enable 0x10624 Doorbell Interrupt Status Rapi
89. 6 26 CAR Device ID Device ID sets the DeviceIdentity field of the Device Identity register This option uniquely identifies the type of device from the vendor specified in the DeviceVendorIdentity field of the Device Identity register This DeviceIdentity field of the Device Identity register Table 6 22 should not be confused with the Base deviceID field in the Base Device ID CSR Table 6 36 on page 6 33 Vendor ID Vendor ID uniquely identifies the vendor and sets the DeviceVendorIdentity field in the Device Identity register Set Vendor ID to the identifier value assigned by the RapidIO Trade Association to your company February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 3 6 Chapter 3 Parameter Settings Capability Registers Settings Device Information CAR The Device Information CAR option identifies the revision ID and sets its value in the Device Information Table 6 23 on page 6 26 CAR Revision ID Revision ID identifies the revision level of the device and sets the value of the DeviceRev field in the DeviceRev field of the Device Information register Table 6 23 This value is assigned and managed by the vendor specified in the VendorIdentity field of the Device Identity register Table 6 22 Assembly Identity CAR The Assembly Identity CAR options identify the vendor who manufactured the assembly or subsystem of the device and sets these values in the Assembly Identity Table 6 24
90. 8 0x10498 0x104A8 0x104B8 0x104C8 0x104D8 0x104E8 0x104F8 Field Bits Access Function Default Bits 31 3 of the starting offset into the RapidlO address OFFSET 31 4 RW space The three least significant bits of the 34 bit offset are 28 ho assumed to be zeros RSRV 3 2 RO Reserved 2 b0 ZAMO 1 0 RW Address two most significant bits of the 34 bit SER Table 6 59 Input Output Slave Mapping Window n Control Offset 0x1040C 0x1041C 0x1042C 0x1043C 0x1044C 0x1045C 0x1046C 0x1047C 0x1048C 0x1049C 0x104AC 0x104BC 0x104CC 0x104DC Ox104EC 0x104FC Field Bits Access Function Default RO Reserved if the system does not support 16 bit device ID LARGE DESTINATION ID MSB 31 24 RW MSB of the Destination ID if the system supports 16 bit 8 h0 device ID DESTINATION ID 23 16 RW Destination ID 8 h0 RSRV 15 8 RO Reserved 8 ho Request Packet s priority 2 b11 is not a valid value for the PRIORITY 7 6 RW priority field Any attempt to write 2 b11 to this field is 2 h0 overwritten with 2 b10 RSRV 5 3 RO Reserved 3 h0 CRF 2 RW Critical Request Flow bit 1 b0 SIRTE TAREE 1 RW SWRITE enable Set to to generate sWwRITE request ihi packets 1 NWRITE R ENABLE 0 RW NWRITE R enable 1 1 b0 Note to Table 6 59 1 Bits 1 NWRITE R ENABLE and SWRITE ENABLE are mutually exclusive An attempt to w
91. AR Table 6 28 on page 6 29 You can use this parameter to specify that your RapidIO II IP core variation handles some specific functionality through the Avalon ST pass through port The 32 bit default value of the Source Operations CAR is determined by the functionality you enable in the RapidIO II IP core with other settings in the parameter editor For example if you turn on Enable Maintenance module the PORT WRITE field is set by default to the value of 1 b1 However the actual reset value of the Source Operations CAR is the result of the bitwise exclusive or operation applied to the default values and the value you specify for the Source operations CAR override parameter For example by default the Data Message field of this CAR is turned off However you can set the value of the Source operations CAR override parameter to 32 h00000800 to override the default value of the Data Message field to indicate that user logic attached to the Avalon ST pass through interface supports data message operations The RapidIO II IP core supports reporting of data message related errors through the standard Error Management Extensions registers Destination Operations CAR The Destination operations CAR override parameter supports user input to the values of all of the fields of the Destination Operations CAR Table 6 29 on page 6 29 You can use this parameter to specify that your RapidIO II IP core variation handles some specific functionality t
92. ARGE_DESTINATION_ID 31 24 RO MSB of the targeted RapidlO processing element device ID if 8 ho the system supports 16 bit device ID DESTINATION ID 23 16 RO The device ID of the targeted RapidlO processing element 8 ho MSB of the information field of an outbound DOORBELL INFORMATION 15 8 RO message that has been confirmed as successful or 8 ho unsuccessful LSB of the information field of an outbound DOORBELL INFORMATION 7 0 RO message that has been confirmed as successful or 8 ho unsuccessful Note to Table 6 89 1 The completed Tx DOORBELL message comes directly from the Tx Doorbell Completion FIFO Table 6 90 Tx Doorbell Completion Status Offset 0x18 Field Bits Access Function Default RSRV 31 2 RO Reserved 30 h0 This error code corresponds to the most recently read message from the Tx Doorbell Completion register After software reads the Tx Doorbell Completion register a read to this register should follow ERROR CODE 1 0 to determine the status of the message Sus 2 b00 Response DONE status 2 b01 Response with ERROR status 2 b10 Time out error Table 6 91 Tx Doorbell Status Control Offset 0x1C Field Bits Access Function Default RSRV 31 2 RO Reserved 30 h0 If set outbound DOORBELL messages that received a response with ERROR 1 RW ERROR Status or were timed out are stored in the Tx Completion 1 ho FIFO Otherwise no error reporting occurs If set responses to successful outbound DOORBELL messa
93. D MSB 31 24 RW MSB of the Destination ID if the system supports 16 bit 8 ho device ID DESTINATION ID 23 16 RW Destination ID 8 h0 HOP COUNT 15 8 RW Hop count 8 hFF Packet priority PRIORITY 7 6 RW 2 b11 is nota valid value for the PRIORITY field Any attempt 2 boo to write 2 b11 to this field is overwritten with 2 b10 RSRV 5 0 RO Reserved 6 ho February 2013 Altera Corporation RapidlO II MegaCore Function User Guide 6 36 Chapter 6 Software Interface Transport and Logical Layer Registers Transmit Port Write Registers Table 6 45 through Table 6 47 describe the transmit port write registers Refer to Handling Port Write Transactions on page 4 36 for information about using these registers to transmit a port write Table 6 45 Tx Port Write Control Offset 0x10200 Field Bits Access Function Default RO Reserved if the system does not support 16 bit device ID LARGE DESTINATION ID MSB 31 24 RW MSB of the Destination ID if the system supports 16 bit 8 h0 device ID DESTINATION ID 23 16 RW Destination ID 8 ho RSRV 15 8 RO Reserved 8 h00 Request packet s priority PRIORITY 7 6 RW 2 b11 is not a valid value for the priority field An attempt 2 boo to write 2 b11 to this field is overwritten as 2 b10 Packet payload size in number of double words If set to 0 SIZE 5 2 RW the payload size is single word If size is s
94. D WRITE BYTEENABLE bit or the INVALID WRITE BURSTCOUNT bit or both of the 1 0 Slave Interrupt register Table 6 60 on page 6 40 if this interrupt is enabled in the 1 O Slave Interrupt Enable register Table 6 61 on page 6 40 Input Output Avalon MM Slave Module Timing Diagrams Figure 4 14 shows the timing dependencies on the Avalon MM slave interface for an outgoing RapidIO NREAD request Figure 4 15 shows the timing dependencies on the Avalon MM slave interface for an outgoing NWRITE transaction Both transaction requests are initiated by local user logic and appear on the Avalon MM interface of the slave module The timing diagrams in Input Output Avalon MM Master Module Timing Diagrams on page 4 17 show the same transactions after they are transmitted on the RapidIO link and received by an Altera RapidIO II IP core link partner when the RapidIO II link partner Input Output Avalon MM master module sends the requests as Avalon MM transactions Figure 4 14 NREAD Transaction on the Input Output Avalon MM Slave Interface Sys M ios rd wr waitrequest 3 ios_rd_wr_read MEE ios_rd_wr_address 27 0 ios rd wr burstcount 4 0 ios rd wr byteenable 15 0 mu ios rd wr readdatavalid f ES M ios rd wr readdata 127 0 00000000 0 r2 ios_rd_wr_readres
95. D value an unexpected ackID out of sequence acklD Received packet with bad CRO 18 RW Received a packet with a bad CRC value 1 h0 Received a packet that exceeds the maximum allowed Received packet 17 RW size For MAINTENANCE packets the maximum allowed 1 h0 exceeding max size size is 78 bytes For non Maintenance packets the maximum allowed size is 276 bytes Received an 8B10B code group that is invalid has no Piece or decode with the current running disparity or illegal valid inalia a 16 RW code group not allowed by the Serial RapidlO protocol 1 h0 When this bit is set bit 2 Delineation error is also set Received data character 15 RW Reserved for this implementation The RapidlO II IP core 1 h0 in IDLEl sequence does not support the IDLE1 sequence Loss of descrambler 14 RW Loss of receiver descrambler synchronization while t ho synchronization receiving scrambled control symbol and packet data RSRV 13 6 RO Reserved Received a 1ink response control symbol with an Non outstanding ackID 5 RW that is not outstanding Only triggers if at least one ackID 1 h0 is outstanding Protocol error 4 RW Received an unexpected control symbol 1 h0 RSRV 3 RO Reserved for this implementation 1 h0 Received an 8B10B code group that is invalid has no decode with the current running disparity or illegal valid code group not allowed by the Serial RapidlO protocol or Delineation error
96. DING ACKID field of the Port 0 Local AckID CSR Table 6 12 on page 6 10 to specify the next expected packet ackID from the RapidIO link partner m Set the CLR OUTSTANDING ACKIDS field of the Port 0 Local AckID CSR Table 6 12 on page 6 10 to clear the queue of outstanding unacknowledged packets If the link partner is reset when its expected ackID is not zero a fatal error occurs when the link partner receives the next transmitted packet because the link partner s expected ackID is reset to zero which causes a mismatch between the transmitted ackID and the expected ackID When that occurs you can use the Port 0 Local AckID CSR to resynchronize the expected and transmitted ackID values Logical Layer Error Management The Logical layer modules only need to process Logical layer errors because errors detected by the Physical layer are masked from the Logical layer module If an errored packet arrives at the Transport layer the Transport layer does not pass it on to the Logical layer modules The RapidIO specification defines the following common errors and the protocols for managing them RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 4 Functional Description 4 67 Error Detection and Management m Malformed request or response packets m Unexpected Transaction ID m Missing response time out m Response with ERROR status The RapidIO II IP core implements the optional Error Management Extensions
97. DUT 32 h6000 0000 February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 1 4 Table 7 1 Testbench Registers Part 2 of 2 Chapter 7 Testbench Testbench Sequence Register Description Val Module Address Register Name escriptio alue Program the sister rio module to have an 8 bit 32 h00CD FFFF Sister rio 0x00060 BaseDevice IDCSR base device ID of oxcp or a 16 bit device ID of or OxCDCD 32 h00FF CDCD General Control Enable Request packet generation by the ister ri 0x0013 32 h6000 0000 SISIE iude agp sister_rio module Set the DESTINATION ID for outgoing transactions to a value 0xCD or oxcpcp The ri Input Output Slave Width of the DESTINATION field depends on 32 hoocD 00000 Window 0 Control the sister_rio device ID width This value 32 hCDCD 0000 matches the base device ID of the sister rio module Define the Input Output Avalon MM Slave Input Output Slave rio 0 10404 dowO0 Mask Window 0 to cover the whole address space 32 h0000 0004 mask set to all zeros and enable it I Output S1 rio 10504 Taput Output Slave Enable the 1 0 slave interrupts 32 h0000 000F Interrupt Enable Input Output Enable the sister rio 2 0 Master Window 0 sister rio 0 10304 Master Window 0 which allows the sister rio to receive 1 0 32 h0000 0004 Mask transactions Set the DESTINATION ID for outgoing TX Maintenance MAINT
98. E0 0 101 0 Field Bits Access Function Default Start of the Avalon MM address window to be mapped The BASE 31 3 RW three least significant bits of the 32 bit base are assumed to be 29 ho zero RSRV 2 0 RO Reserved 3 h0 Table 6 42 Tx Maintenance Mapping Window n Mask Offset 0x10104 0x10114 0x10124 0x10134 0x10144 0x10154 0x10164 0x10174 0x10184 0x10194 0x101A4 0x101B4 0x101C4 0x101D4 0x101E4 0x101F4 Field Bits Access Function Default Mask for the address mapping window The three least MASE 31 3 RW significant bits of the 32 bit mask are assumed to be zero ds WEN 2 RW Window enable Set to one to enable the corresponding Tm window RSRV 1 0 RO Reserved 2 h0 Table 6 43 Tx Maintenance Mapping Window n Offset Q0ffset 0x10108 0x10118 0x10128 0x10138 0x10148 0x10158 0x10168 0x10178 0x10188 0x10198 0x101A8 0x101B8 0x101C8 0x101D8 0x101E8 0x101F8 Field Bits Access Function Default RSRV 31 24 RO Reserved 8 ho OFFSET 23 0 RW Window offset 24 h0 Table 6 44 Tx Maintenance Mapping Window Control Offset 0x1010C 0x1011C 0x1012C 0x1013C 0x1014C 0x1015C 0x1016C 0 1017 0x1018C 0x1019C 0x101AC 0x101BC 0 101 0x101DC 0 101 0x101FC Field Bits Access Function Default RO Reserved if the system does not support 16 bit device ID LARGE DESTINATION I
99. EAMING 18 RO Processing element can support a data streaming operation 1 b0 RSRV 17 16 RO Reserved 2 b0 READ 15 RO Processing element can support a read operation 3 WRITE 14 RO Processing element can support a write operation 3 SWRITE 13 RO Processing element can support a streaming write operation 3 NWRITE R 12 RO Processing element can support a write with response operation 3 Data Message 11 RO Processing element can support data message operation 1 b0 DOORBELL 10 RO Processing element can support a DOORBELL operation 4 COMP SWP 9 RO element can support an ATOMIC compare and swap 10 TEST 8 RO m element can support an ATOMIC test and swap 1 b0 ATM_INC 7 RO Processing element can support an ATOMIC increment operation 1 b0 ATM DEC 6 RO Processing element can support an ATOMIC decrement operation 10 ATM SET 5 RO Processing element can support an ATOMIC set operation 1 0 CLEAR 4 RO Processing element can support an ATOMIC clear operation 1 b0 ATM SWAP 3 RO Processing element can support an ATOMIC swap operation 1 b0 PORT WRITE 2 RO Processing element can support a port write operation 6 EE 1 0 RO Reserved for this implementation 2 b00 Notes to Table 6 28 1 If one of the Logical layers supported by the RapidlO II IP core is not selected in the RapidlO II parameter editor the corresponding bits in the Source Operations CARs are set to zero by default
100. ENANCE packets 10 OXCD Or OxCDCD o e FFOO rio 0x1010C WE depending on the sister rio device ID width This iSo CDD value matches the base device ID of the sister rio module Set the hop count to oxFF TX Maint rio 0x10104 Enable the TX Maintenance window 0 32 h0000 0004 Window 0 Mask Read and write tasks that are defined in the BFM instance sys_mnt_master_bfm program the DUT s registers Read and write tasks defined in the BFM instance sister sys mnt master bfm program the sister rio module s registers For the exact parameters passed to these tasks refer to the file tb rio v The tasks drive read and write transactions across the Register Access Avalon MM slave interface In the configuration shown in Figure 7 1 on page 7 2 the IP cores can exchange basic packets across the serial link Maintenance Write and Read Transactions If the Maintenance module is present the testbench sends a few MAINTENANCE read and write request packets from the DUT to the sister rio module Transactions are initiated by Avalon MM transactions on the DUT s Maintenance Avalon MM slave interface and are checked on the sister rio s Maintenance Avalon MM master interface RapidlO II MegaCore Function User Guide February 2013 Altera Corporation Chapter 7 Testbench Testbench Sequence 1 5 The first set of tests performed are MAINTENANCE write and read requests The DUT sends two MAINTENANCE write requests t
101. ERROR RESPONSE 2 30 RO 1 Received a response of ERROR for a MSG Logical Layer Request Set when the RapidlO II IP core detects this situation or when the message error response set input signal changes value from 0 to 1 1 b0 GSM ERROR RESPONSE 0 MSG FORMAT ERROR 2 29 28 RO 1 RO Received a response of ERROR for a GSM Logical Layer Request Set when the RapidlO II IP core detects this situation or when the gsm error response set input signal changes value from 0 to 1 Received MESSAGE packet data payload with an invalid size or segment Set when the RapidlO II IP core detects this situation or when the message format error response set input signal changes value from 0 to 1 1 b0 1 b0 ILL TRAN DECODE 27 RO Received illegal fields in the request response packet for a supported transaction Set when the RapidlO II IP core detects this situation or whenthe illegal transaction decode set input signal changes value from 0 to 1 1 b0 ILL TRAN TARGET 26 RO Received a packet that contained a destination ID that is not defined for this end point Set when the RapidlO II IP core detects this situation or when the illegal transaction target error set input signal changes value from 0 to 1 An endpoint with multiple ports and a built in switch function might not report this situation as an error 1 b0 MSG REQ TIMEOUT 2 25 ROM A required message
102. Function User Guide February 2013 Altera Corporation
103. Layer Control 0x320 0x324 Reserved 0x328 Port Write Target Device ID Maintenance module 0x32C Packet Time to Live 0x330 0x33C Reserved 0x340 Port 0 Error Detect 0x344 Port 0 Error Rate Enable 0x348 Port 0 Attributes Capture Physical layer 0x34C ine 0 Packet Control Symbol Capture 0x350 Port 0 Packet Capture 1 0x354 Port 0 Packet Capture 2 0x358 Port 0 Packet Capture 3 0x35C 0x364 Reserved 0x368 Port 0 Error Rate 0x36C Port 0 Error Rate Threshold Implementation Defined Space 0x10000 0x1007C Reserved 0x10080 0x10084 Maintenance Interrupt Maintenance Interrupt Enable Maintenance module These registers are described in Maintenance Interrupt Control Registers on page 6 34 0x10088 0x100FC Reserved February 2013 Altera Corporation RapidlO II MegaCore Function User Guide 6 6 Chapter 6 Software Interface Physical Layer Registers Table 6 4 Extended Features and Implementation Defined Registers Memory Map Part 3 of 3 Address Name Used by Module 0x10100 Tx Maintenance Window 0 Base 0x10104 Tx Maintenance Window 0 Mask Maintenance module 0x10108 Tx Maintenance Window 0 Offset These registers are described in Transmit 0x1010C Tx Maintenance Window 0 Control Maintenance Registers on page 6 35 0x10110 0x101FC Tx Maintenance Windows 1 15 0x10200 Tx Port Write Control Maintenance module 0x10204 Tx Port Write Status These registers are described in Transmit Port
104. Logical Layer Control CSR at offset 0x48 Table 6 32 on mtu 7 0 Output page 6 31 RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 5 Signals 5 7 Logical and Transport Layer Signals Table 5 11 Data Streaming Support Signals Part 2 of 2 Signal Direction Description tm mode wr Input Support user logic in setting the TM MODE field in the Data Streaming Logical tm mode in 3 0 Input Layer Control CSR at offset 0x48 1 mtu wr Input Support user logic in setting the MTU field in the Data Streaming Logical Layer mtu in 7 0 Input Control CSR at offset 0x48 1 Note to Table 5 11 1 To write to the register field for any of these signal pairs drive the value on the insignal and then set the wr signal to the value of 1 b1 When the wr signal has the value of 1 b1 on the rising edge of sys clk the value of the signal is written directly to the register field Packet and Error Monitoring Signal for the Transport Layer Table 5 12 shows the packet and error monitoring signal for the Transport layer For Physical layer packet and error monitoring signals refer to Table 5 4 on page 5 2 Table 5 12 Transport Layer Packet and Error Monitoring Signal Signal Direction Description Pulsed high one Avalon clock cycle when a received packet is dropped by the Transport layer Examples of packets that are dropped include packets that have an incorrect destination ID are of a
105. Logical Layer Registers Table 6 49 Rx Port Write Status Offset 0x10254 Field Bits Access Function Default RSRV 31 6 RO Reserved 26 h0 Packet payload size in number of double words If the size is zero the payload size is single word RSRV 1 RO Reserved 1 b0 Port write busy Set if a packet is currently being stored in the PAYLOAD SIZE 5 2 RO 4 h0 POMI ARITE BUSY 0 no buffer or if the packet is stored and has not been read ERE Table 6 50 Rx Port Write Buffer n Offset 0x10260 0x1029C Field Bits Access Function Default PORT WRITE DATA n 31 0 RO Port write data This buffer is implemented in memory and is not initialized at reset Input Output Master Address Mapping Registers Table 6 51 through Table 6 53 describe the Input Output master registers When the IP core receives an NREAD NWRITE NWRITE R or SWRITE request packet the RapidIO address has to be translated into a local Avalon MM address If you specify at least one address mapping window the translation involves the base mask and offset registers The IP core has up to 16 register sets one for each address mapping window The 16 possible register address offsets are shown in the table titles Refer to Defining the Input Output Avalon MM Master Address Mapping Windows on page 4 11 for more details Table 6 51 Input Output Master Mapping Window n Base Offset 0x10300 0x10310 0x10320 0x10
106. O Reserved if the system does not support 16 bit device ID LARGE DESTINATION ID MSB 31 24 RW MSB of the targeted RapidlO processing element device ID if 8 ho the system supports 16 bit device ID DESTINATION ID 23 16 RW Device ID of the targeted RapidlO processing element 8 h0 INFORMATION MSB 15 8 RW MSB information field of the outbound DOORBELL message 8 INFORMATION LSB 7 0 RW LSB information field of the outbound DOORBELL message 8 ho Table 6 88 Tx Doorbell Status Offset 0x10 Field Bits Access Function Default RSRV 31 24 RO Reserved 8 ho Number of DOORBELL messages that have been transmitted but PENDING 23 16 RO for which a response has not been received There can be a 8 ho maximum of 16 pending DOORBELL messages The number of DOORBELL messages in the staging FIFO plus the TX FIFO LEVEL 15 8 RO number of DOORBELL messages in the Tx FIFO The maximum 8 ho value is 16 7 0 RO The number of available completed Tx DOORBELL messages in Es the Tx Completion FIFO The FIFO can store a maximum of 16 RapidlO II MegaCore Function User Guide 6 54 Chapter 6 Software Interface Transport and Logical Layer Registers Table 6 89 Tx Doorbell Completion Offset 0x14 1 Field Bits Access Function Default Reserved if the system does not support 16 bit device ID L
107. Parameters eese ER hene deser pce pee e ise eq eadera 2 2 Simulating the Design eee erbe eld RET CEU dE gd e dete ren et 2 3 Simulating with the ModelSim Simulator 2 3 Simulating with the VCS Simulator ssssssssseeeeeeese eee eens 2 4 Osys Design FloW rd eere p tes ebenso spe Regen decenas ease e Re a ag tas lous ate ee pneu 2 4 Specitytng Parameters ne oe ee ee at 2 5 Completing the Osys System cer eene 2 6 simulating the Systemi eer Ea ded Mah ae dn 2 7 Adding Transceiver Analog Settings e 2 2 esneyen er niecki itikad 2 7 Compiling the Full Design and Programming the FPGA 0 ccc cence nes 2 7 Instantiating Multiple RapidIO ITIP Cores 2 0 III 2 8 Clock and Signal Requirements nunnana nnn nnr ne eens 2 8 Chapter 3 Parameter Settings Physical Layer Settings et etuer RERO m eite deed rgo need teen eed tna 3 1 Supported Modes tonta id ba d eet SEHE te ee b Ee aee P lea e 3 1 Maximum Baud Rate ir skepsis tameg eh n een d e e ahead adhesin denar ete 3 2 Reference Clock Frequency edi ieee ad aid RC He Pep dae e aie eoe a eer eec 3 2 Transport Layer Seting Se seice eene ee epe pr OPER epe tel ate de po etcetera 3 2 Enable 16 Bit Device ID Width ee 3 2 Enable Avalon ST Pass Through Interface
108. RapidIO core RapidlO II MegaCore Function User Guide February 2013 Altera Corporation Chapter 6 Software Interface 6 3 Memory Map Table 6 3 lists the CARs and CSRs Table 6 4 on page 6 4 lists all the registers in the extended features address spaces and all of the implementation defined address spaces that are accessed through the Maintenance Avalon MM slave interface Table 6 83 on page 6 52 lists the doorbell registers The individual register descriptions appear in the following sections Table 6 3 CAR and CSR Memory Map Part 1 of 2 Address Name Register Specification Available in Capability Registers CARs 1 These registers are described in Capability Registers CARs on page 6 26 0x0 Device Identity 0x4 Device Information RapidlO Interconnect Specification v2 2 Part 1 0x8 Assembly Identity Input Output Logical Specification OxC Assembly Information m RapidlO Interconnect Specification v2 2 Part 1 Input Output Logical Specification m RapidlO Interconnect Specification v2 2 Part 3 Common Transport Specification m RapidlO Interconnect Specification v2 2 Part 6 LP Serial Physical Layer Specification RapidlO Interconnect Specification v2 2 Part 1 Input Output Logical Specification m RapidlO Interconnect Specification v2 2 Part 1 Input Output Logical Specification m RapidlO Interconnect Specification v2 2 Part 2 Message Passing Logical Specification m RapidlO I
109. Started The dynamic reconfiguration block lets you reconfigure the following PMA settings m Pre emphasis m Equalization m Offset cancellation m Vopona per channel basis m Reset controller block Refer to Reset for RapidIO II IP Cores on page 4 4 St For more information about the Altera dynamic reconfiguration and PHY reset controller IP cores refer to the Altera Transceiver PHY IP Core User Guide For more information about offset cancellation refer to the relevant device handbook Register Related Signals Table 5 8 lists the Physical layer register related signals These signals are output signals that reflect useful register field values Table 5 8 Register Related Signals Signal Direction Description This output reflects the value of the Master Enable bit of the Port General Control CSR Table 6 9 on page 6 8 which indicates whether this device is allowed to issue request packets If the Master Enable bit is not set the device may only respond to requests User logic connected to the Avalon ST pass through interface should honor this value and not cause the Physical layer to issue request packets when it is not allowed This output reflects the value of the TIME TO LIVE field of the Packet time to live 15 0 Output Time to Live CSR Table 6 73 on page 6 47 which is the maximum time duration that a packet is allowed to remain in a switch device EP This output reflects the value of the Base deviceIpfield in t
110. The RapidIO interconnect an open standard developed by the RapidIO Trade Association is a high performance packet switched interconnect technology designed to pass data and control information between microprocessors digital signal processors DSPs communications and network processors system memories and peripheral devices The Altera RapidIO II MegaCore function complies with the RapidIO v2 2 specification and targets high performance multicomputing high bandwidth and coprocessing I O applications Figure 1 1 shows an example system implementation Figure 1 1 Typical RapidlO Application Proprietary CPRI OBSAI Ethernet etc RapidlO 11 MegaCore Function Features This section outlines the features and supported transactions of the RapidIO ILIP core February 2013 Altera Corporation RapidlO II MegaCore Function User Guide Chapter 1 About The RapidlO Il MegaCore Function Features New Features in the RapidlO Il IP Core v12 1 SP1 Release The RapidIO II IP core v12 1 SP1 adds the following new features m Support for Cyclone V devices m Support for Arria V GZ devices m Device programming support for Arria V devices RapidlO 1 IP Core Features The RapidIO II IP core has the following features m Compliant with the RapidIO Trade Association RapidIO Interconnect Specification RapidlO II MegaCore Function User Guide Revision 2 2 June 2011 available from the RapidIO Trade A
111. W Status CSR offset 0x158 The port resumes normal operation 1 b0 when the value in the Error Rate Counter field of the Port 0 Error Rate CSR offset 0x368 falls below the failed error threshold This value is valid only for switch devices 2 b10 The port stops trying to send packets to the link partner until software resets the oUT FAIL ENC field of the Port 0 Error and Status CSR offset 0 158 2 b11 The port discards all output packets until software resets the OUT_FAIL ENC field of the Port 0 Error and Status CSR offset 0x158 When the port discards a packet it sets the OUT PKT DROPD bitinthe Port 0 Error and Status CSR Together with the STOP ON PRT FAIL ENCOUNTER ENABLE field specifies the behavior of the port when the failed error threshold in the Port 0 Error Rate Threshold register offset 0 36 has been reached or exceeded 160 Refer the description of the STOP ON PRT FAIL ENCOUNTER ENABLE field This bit indicates whether the port is stopped or the IN PENA bit 21 and OUT PENA bit 22 register fields control the port 1 b0 The Input Port Enable PENA and Output Port Enable 00 PENA fields in this register control which packets the port may receive and transmit on the RapidlO link 1 b1 Port is stopped and is not enabled to issue or receive any packets The input port can still follow the training procedure and can still send and respond to link requests All received packets
112. WRITE Transactions rio Register Address 0x1040C Name Value Description Sets the DESTINATION ID for outgoing transactions to the value or OxCDCD depending on the device ID width of the sister rio This value matches the base device ID of the sister rio Sets the write request type back to NWRITE Input Output Slave 32 h00CD 0000 Mapping Window 0 or Control 32 hCDCD 0000 The testbench generates a predetermined series of burst writes across the Input Output Avalon MM slave module s Avalon MM write interface on the DUT These write bursts are each converted into an NWRITE request packet that is sent over the RapidIO serial interface The testbench cycles from two to 128 in steps of 8 bytes Two tasks are run to carry out the burst writes rw_addr_data and rw_data The rw_addr_data task initiates the burst and the rw_data task completes the remainder of the burst The ios_128_rd_wr_master_bfm read write cmd task generates the burst writes The sister rio module receives the NWRITE request packets and presents them across the I O master Avalon MM slave interface as write transactions The testbench calls the sister iom128 rd wr slave bfm read write data task to capture the written data The written data is checked against the expected value The RapidIO II IP core testbench also demonstrates NWRITE transactions with an invalid destination ID Doorbell Transactions To test DOORBELL messages
113. _0000_1100_0000 0100 1 1 1100_0000_0000_0000 1 0 1 0000 0000 0000 1100 1 1 0000 1100 0000 0000 0 0 1 0000_0000_1110_0000 0101 1 1 1 0000_0000_0000_0111 1 0 1 1110 0000 0000 0000 1 1 0000 0111 0000 0000 0 0 1 0000_0000_0011_0000 0110 1 1 0000 0000 0000 0011 1 0 1 0011 0000 0000 0000 1 1 0000 0011 0000 0000 0 0 1 0000_0000_1111_1000 01110 1 1 0000 0000 0001 1111 1 0 1 1111 1000 0000 0000 1 1 0001 1111 0000 0000 0 0 1 0000_0000_1111_0000 1000 1 1 1111 0000 0000 0000 1 0 1 0000 0000 0000 1111 1 1 0000 1111 0000 0000 0 0 1 0000_0000_1111_1100 4001 0 1 1 0000_0000_0011_1111 1 0 1 1111 1100 0000 0000 1 1 0011 1111 0000 0000 0 0 1 0000_0000_1111_1110 4010 1 1 1 0000_0000_0111_1111 0 1 1 1 0111_1111_0000_0000 RapidlO II MegaCore Function User Guide February 2013 Altera Corporation Chapter 4 Functional Description 4 17 Logical Layer Interfaces Table 4 7 Avalon MM 1 0 Master Write Transaction Burstcount and Byteenable Part 3 of 3 RapidlO Field Values Avalon MM Signal Values wrsize wdptr address 0 4 1 1 bx Burstcount Byteenable 16 bXXXX_XXXX_XXXX_XXXX 0 0 1 0000_0000_1111_1111 1011 1 1 1111_1111_0000_0000 1 0 1 1111 1111 1111 1111 1 2 2 Notes to Table 4 7 1 The RapidlO link partner should avoid this combination of and wrsize values because the resulting byteenable value presented on the Avalon MM master i
114. a being transferred on the Avalon ST sink interface Pass Through Interface Receive Side Data Signals Table 4 25 lists the Avalon ST pass through interface receive side payload data signals The application should sample payload data only when both gen rx pd ready and gen rx pd valid are asserted Table 4 25 Avalon ST Pass Through Interface Receive Side Avalon ST Source Data Signals Signal Name Type Function Indicates to the IP core that the user s custom logic is ready to receive data on the current cycle Asserted by the sink to mark ready cycles which are cycles in gen rx pd ready Input which transfers can occur If ready is asserted on cycle N the cycle N READY LATENCY is a ready cycle The RapidlO II IP core is designed for READY LATENCY equal to 0 Used to qualify all the other output signals of the receive side pass through gen rx pd valid Output interface On every rising edge of the clock during which gen xx validis high gen rx pd data can be sampled gen rx pd startofpacket Output Marks the active cycle containing the start of the packet 1 gen rx pd endofpacket Output Marks the active cycle containing the end of the packet 1 gen rx pd data 127 0 Output A 128 bit wide data bus for data payload This bus identifies the number of empty two byte segments on the 128 bit wide Bet s bubo Output 92 pd data bus on the final data transfer of the packet which occurs duri
115. able 6 67 on page 6 43 If your design does not use one or more of these signals you should tie the unused signals low Table 5 14 Capture Signals 2 Part 1 of 2 Signal Direction Description external capture destinationID wr Input external capture destinationID in Input Support user logic in setting the corresponding fields in the 15 0 Logical Transport Layer Device ID Capture CSR at external capture sourceID wr Input offset 0x308 For information about the register fields these signals can write refer to Table 6 70 on page 6 46 external capture sourceID in Input 15 0 capture ftype wr Input Support user logic in setting the FTYPE field in the Logical Transport Layer Control Capture CSR at offset capture ftype in 3 0 Input 0x308 For information about the register fields these signals can i write refer to Table 6 71 on page 6 47 capture ttype wr Input Support user logic in setting the TTYPE field in the Logical Transport Layer Control Capture CSR at offset capture ttype in 3 0 Input 0x308 For information about the register fields these signals can write refer to Table 6 71 on page 6 47 RapidlO II MegaCore Function User Guide February 2013 Altera Corporation Chapter 5 Signals 5 9 Error Management Extension Signals Table 5 14 Capture Signals 2 Part 2 of 2 Signal Direction Description letter wr Input Support user log
116. acket without payload with incorrect payload size or with a transaction type indicating absence of payload Registers in the Implementation Defined Space The I O Avalon MM slave module defines the Input Output Slave Interrupt registers with the following bits For details on when these bits are set refer to their descriptions in Table 6 60 on page 6 40 E INVALID READ BURSTCOUNT B INVALID READ BYTEENABLE B INVALID WRITE BYTEENABLE B INVALID WRITE BURSTCOUNT WRITE OUT OF BOUNDS E READ OUT OF BOUNDS When any of these bits are set the system interrupt signalio s mnt is also asserted if the corresponding bit in the Input Output Slave Interrupt Enable register Table 6 61 on page 6 40 is set The Avalon MM Slave Interface s Error Indication Signal The ios rd wr readresponse output is asserted when a response with ERROR status is received for an NREAD request packet when an NREAD request times out or when the Avalon MM address falls outside of the enabled address mapping window As required by the Avalon MM interface specification a burst in which the ios rd wr readresponse signalis asserted completes despite the error signal assertion Input Output Avalon MM Master The I O Avalon MM master module processes the request packets that it receives and generates response packets when required Anomalies are reported through one or both of the following two channels m Standard error management register
117. age passing A round robin priority supporting outgoing scheduler chooses packets to transmit from various Logical layer modules m Logicallayer features Generation and management of transaction IDs Automatic response generation and processing Response Request Timeout checking Capability registers CARs command and status registers CSRs and Error Management Extensions registers Direct register access either remotely or locally Maintenance master and slave Logical layer modules Input Output Avalon Memory Mapped Avalon MM master and slave Logical layer modules with 128 bit wide datapath and burst support Doorbell module supporting 16 outstanding DOORBELL packets with time out mechanism Optional preservation of transaction order between outgoing DOORBELL messages and I O write requests Registers and interrupt indicate NWRITE R transaction completion Preservation of transaction order between outgoing I O read requests and I O write requests from Avalon MM interfaces m Cycle accurate simulation models for use in Altera supported Verilog HDL simulators m IEEE encrypted HDL simulation models for improved simulation efficiency m Support for OpenCore Plus evaluation Supported Transactions The RapidIO II IP core supports the following RapidIO transactions NREAD request and response NWRITE request NWRITE R request and response SWRITE request MAINTENANCE read request and response MAINTENANCE write request and res
118. al Lane n Status 4 CSR on the outgoing CS field for lane n Transport and Logical Layer Registers This section lists the Transport and Logical layer registers Table 6 3 provides memory map of all accessible registers This address space is accessible to the user through the Maintenance Avalon MM slave interface February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 6 26 Chapter 6 Software Interface Transport and Logical Layer Registers Capability Registers CARs Table 6 3 provides a memory map of all CARs in the RapidIO IP core This address space is accessible to the user through the Register Access Avalon MM slave interface Table 6 22 through Table 6 31 describe the capability registers Table 6 22 Device Identity CAR Offset 0x00 Field Bits Access Function Default DeviceIdentity 31 16 RO Hard wired device identifier 1 DeviceVendorIdentity 15 0 Hard wired device vendor identifier 1 Note to Table 6 22 1 The value is set in the RapidlO II parameter editor Table 6 23 Device Information CAR Offset 0x04 Field Bits Access Function Default 31 0 RO Hard wired device revision level Note to Table 6 23 1 The value is set in the RapidlO II parameter editor Table 6 24 Assembly Identity CAR Offset 0x08 Field Bits Access Function Default AssyIdentity 31 16 RO Hard wired assembly identifier AssyVendorIdentity
119. alon MM Byte7 and for all values of i from 0 to 63 bit i of the RapidIO 64 bit double word 0 63 of payload is bit 63 i of the Avalon MM 64 bit double word 63 0 Table 4 1 Byte Ordering Part 1 of 2 Byte Lane Binary RapidlO Protocol Big Endian 1000 0000 0100_0000 0010 0000 0001 0000 0000 1000 0000 0100 0000 0010 0000 0001 0 0 7 1 0 7 Byte2 0 7 Byte3 0 7 Byte4 0 7 Byte5 0 7 Byte6 0 7 Byte7 0 7 32 Bit Word 0 31 32 Bit Word 0 31 wdptr 0 wdptr 1 Double Word 0 63 RapidlO Byte Address N 29 hn 3 b000 February 2013 Altera Corporation RapidlO II MegaCore Function User Guide 4 2 Chapter 4 Functional Description Interfaces Table 4 1 Byte Ordering Part 2 of 2 Byte Lane 1000 0000 0100 0000 0010 0000 0001 0000 0000 1000 0000 0100 0000 0010 0000 0001 Binary Byte7 7 0 Byte6 7 0 Byte5 7 0 Byte4 7 0 Byte3 7 0 Byte2 7 0 Byte1 7 0 Byte0 7 0 Avalon Address Address Address Address Address Address Address Address MM 7 N 6 N 5 N 4 N 3 N 2 N 1 N Protocol 32 Bit Word 31 0 32 Bit Word 31 0 Little Avalon MM Byte Address N44 Avalon MM Byte Address N Endian 64 bit Double Word0 63 0 Avalon MM Byte Address In variations of the RapidIO II IP core that have 128 bit wide Avalon MM interfaces the least significant half of the Avalon MM 128 bit word
120. alon MM Master Interface Signals Signal Direction Description iom rd wr waitrequest Input 1 0 Logical Layer Avalon MM Master module wait request iom rd wr write Output 1 0 Logical Layer Avalon MM Master module write request iom_rd_wr_read Output 1 0 Logical Layer Avalon MM Master module read request iom_rd_wr_address 31 0 Output 1 0 Logical Layer Avalon MM Master module address bus iom rd wr writedata 127 0 Output 1 0 Logical Layer Avalon MM Master module write data bus iom rd wr byteenable 15 0 Output 1 0 Logical Layer Avalon MM Master module byte enable iom rd wr burstcount 4 0 Output 1 0 Logical Layer Avalon MM Master module burst count iom rd wr readresponse Input 1 0 Logical Layer Avalon MM Master module read error response iom rd wr readdata 127 0 Input 1 0 Logical Layer Avalon MM Master module read data bus iom rd wr readdatavalid Input 1 0 Logical Layer Avalon MM Master module read data valid The I O Avalon MM Master module supports an interrupt line io m mnt the Register Access interface When enabled the following interrupts assert the io m mnt signal m Address out of bounds RapidlO II MegaCore Function User Guide February 2013 Altera Corporation Chapter 4 Functional Description 4 11 Logical Layer Interfaces For more information about the I O Logical layer Avalon MM master module interrupts refer to Table 6 54 and Table 6 55 on page 6 38 D
121. alue of the Flow Control Participant field of the Port 0 Control CSR Enumeration Boundary Reset Value Enumeration boundary reset value sets the reset value of the Enumeration Boundary field of the Port 0 Control CSR Flow Arbitration Participant Reset Value Flow arbitration participant reset value sets the reset value of the Flow Arbitration Participant field of the Port 0 Control CSR Lane n Status 0 CSR The Lane n Status 0 CSR is described in Table 6 17 on page 6 20 Transmitter Type Reset Value Transmitter type reset value sets the value of the Transmitter Type field and the reset value of the Transmitter Mode field of the Lane n Status 0 CSR Receiver Type Reset Value Receiver type reset value sets the value of the Receiver Type field of the Lane n Status 0 CSR Error Management Registers Settings The Error Management Registers tab lists a single parameter Enable error management extension registers If you turn on Enable error management extension registers your RapidIO II IP core instantiates the Error Management Extensions register block defined in the RapidIO Interconnect Specification Part 8 Error Management Extensions Specification The RapidIO II IP core instantiates these registers at register block offset 0x300 If you do not instantiate these registers you can specify user defined registers at offset 0x300 February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 3 12 Chapter 3 Parame
122. ameter available If the RapidlO II IP core identifies a fatal error it notifies software by setting the PORT ERR bitinthe Port 0 Error and Status CSRand asserting the error output signal which may be used as an interrupt output signal Number of The Link request attempts parameter allows you to Link Request The number of times that a RapidlO II IP core sends specify the number of times the RapidlO IP core Attempts link request reset device control symbol sends a link request reset device control Before following a link request time out before symbol following a link request time out before Declaring declaring a fatal error is seven This value cannot be declaring a fatal error This parameter can have Fatal Error modified in the parameter editor values 1 through 7 The default value in a new parameter variation is 7 The Send link request reset device on fatal errors Sending In the RapidlO II IP core this parameter is not option specifies that if the RapidlO IP core identifies a fatal error it transmits four 1ink request control symbols with cmd set to reset device on the RapidlO link By default this option is turned off The option is available for backward compatibility because previous releases of the RapidlO IP core implement this behavior February 2013 Altera Corporation RapidlO II MegaCore Function User Guide B 4 RapidlO II MegaCore Function User Guide Appendix B Differences Betwe
123. ane number x of CS field s Dx y value Should match n This field is updated with each post 27 23 RO received CS field Se Active port y of CS frame s Dx y value This register field is updated with each width 22 20 RO received CS field oe RSRV 19 8 RO Reserved 12 h000 February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 6 24 Chapter 6 Software Interface Physical Layer Registers Table 6 20 LP Serial Lane n Status 3 Received CS Field Commands Offset 0x21C 0x23C 0x25C 0x27C Part 2 of 2 Field Bits Access Function Default Tap 1 Command 7 6 RO 2 b00 ae IX ee 2 b00 Value of this field in the most recently received CS field Reset 3 RO 1 b0 emphasis Preset emphasis 2 i RSRV 1 0 RO Reserved 2 b00 Table 6 21 LP Serial Lane n Status 4 Outgoing CS Field Offset 0x220 0x240 0x260 0x280 Part 1 of 2 RapidlO II MegaCore Function User Guide Field Bits Access Function Default Indicates to the connected port that an emphasis update command is present CMD 31 RW 1 b0 No request present 1 b1 Request present Impl Defined 30 RW Implementation defined 160 When the lane receiver controls transmit or receive adaptive equalization this bit indicates whether all adaptive equalizers controlled by the lane receiver are trained sas 29 RW 1 b0 One or mo
124. apidIO II IP core variation in your design note the connection and I O assignment requirements described in Completing the Qsys System on page 2 6 In the Qsys flow you perform these steps in the Quartus II software but in the MegaWizard Plug In Manager flow you must implement them manually in your design Simulating the Design You can simulate your RapidIO II IP core variation using the simulation model that the MegaWizard Plug In Manager generates When you generate the RapidIO II IP core you can optionally generate a Verilog HDL demonstration testbench for your IP core variation The simulation model and testbench files are generated in vendor specific subdirectories of your project directory These directories also include scripts to compile and run the demonstration testbench The testbench demonstrates how to instantiate a model in a design and includes some simple stimulus to control the user interfaces of the RapidIO II IP core For information about the demonstration testbench refer to Chapter 7 Testbench The following sections teach you how to simulate your MegaWizard Plug In Manager flow generated RapidIO II IP core variation with the generated simulation model and the Verilog HDL demonstration testbench Simulating with the ModelSim Simulator To simulate using the Mentor Graphics ModelSim simulator perform the following steps 1 Start the ModelSim simulator 2 In ModelSim change directory to the project simulat
125. apidlO Address 1 E XAMB Window Base 1 Don t Care Window Mask 11 11111111 1 110000000000000090 Window Offset Don t Care EH db NA Resulting 2 43 0 Avalon MM Address E Note to Figure 4 5 1 These bits must have the same value in the initial RapidlO address and in the window base RapidlO Packet Data wdptr and Data Size Encoding Avalon MM Transactions The RapidIO II IP core converts RapidIO packets to Avalon MM transactions The RapidIO packets read size write size and word pointer fields and the least significant bit of the address field are translated to the Avalon MM burst count and byteenable values February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 4 14 Chapter 4 Functional Description Logical Layer Interfaces For information about the burst count and byteenable values that the RapidIO II IP core determines in the conversion process for read transactions refer to Table 4 6 For information about the burst count and byteenable values that the RapidIO II IP core determines in the conversion process for write transactions refer to Table 4 7 on page 4 15 and Table 4 8 on page 4 17 Table 4 6 Avalon MM 1 0 Master Read Transaction Burstcount Part 1 of 2 RapidlO Field Values Avalon MM Signal Values i wdptr r Byteenabl i boni vip i pe Burstcount 16 0 0
126. apidlO II MegaCore Function User Guide 6 28 Chapter 6 Software Interface Transport and Logical Layer Registers Table 6 26 Processing Element Features CAR Offset 0x10 Part 3 of 3 Field Bits Access LARGE TRANSPORT 4 RO Extended features 3 RO Function Processing element supports common transport large systems 1 b0 Processing element does not support common transport large systems processing element requires that the device ID width be 8 bits and does not support a device ID width of 16 bits 1 b1 Processing element supports common transport large systems processing element supports a device ID width of 16 bits The value of this field is determined by the device ID width you select in the RapidlO II parameter editor with the Enable 16 bit device ID width setting Refer to Transport Layer Settings on page 3 2 Processing element has extended features list the extended features pointer is valid Default 1 Extended addressing 2 0 RO support Indicates the number of address bits supported by the processing element both as a source and target of an operation All processing elements support a minimum 34 bit address The RapidlO IP core supports the following valid value 3 b001 Processing element supports 34 bit addresses 3 b001 Note to Table 6 26 1 The value is set in the RapidlO Il parameter editor 2 Ifthe Standard route tab
127. ariation When you select the RapidIO II IP core in the MegaWizard Plug In Manager the RapidIO II parameter editor appears The RapidIO II parameter editor lets you interactively set parameter values and select optional ports This flow is best for manual instantiation of an IP core in your design Qsys Design Flow The Osys design flow enables you to integrate a RapidIO IP core in a Qsys system The Osys design flow allows you to connect component interfaces with the system interconnect eliminating the requirement to design low level interfaces and significantly reducing design time When you add a RapidIO II IP core instance to your design a RapidIO II parameter editor guides you in selecting the properties of the RapidIO II IP core instance MegaWizard Plug In Manager Design Flow The MegaWizard Plug In Manager flow allows you to customize the RapidIO II IP core and manually integrate the function in your design The following sections describe this design flow Specifying Parameters To specify RapidIO II IP core parameters using the MegaWizard Plug In Manager follow these steps 1 Create a Quartus II project using the New Project Wizard available from the File menu Ensure you select a device family that supports the IP core Refer to Table 1 2 on page 1 4 for device support information 2 On the Tools menu click MegaWizard Plug In Manager 3 Follow the prompts in the MegaWizard Plug In Manager interface to create a cus
128. atus Command and Status register CSR 0x00158 of the first RapidIO IP core to confirm port initialization Set the following registers in the first RapidIO IP core a To set the base ID of the device to 0x01 set the Base deviceID field bits 23 16 or the Large base deviceID field bits 15 0 of the Base Device ID register 0x00060 to 0x1 To allow request packets to be issued write 1 to the ENA field bit 30 of the Port General Control CSR 0x13C To set the destination ID of outgoing maintenance request packets to 0x02 set the DESTINATION ID field bits 23 16 or the combined LARGE DESTINATION ID MSB DESTINATION ID fields bits 31 16 of the Tx Maintenance Window 0 Control register 0x1010C to 0x02 To enable an all encompassing address mapping window for the maintenance module write 1 b1 to the WEN field bit 2 of the Tx Maintenance Window 0 Mask register 0x10104 Set the following registers in the second RapidIO IP core a To set the base ID of the device to 0x02 set the Base deviceID field bits 23 16 or the Large base deviceID field bits 15 0 of the Base Device ID register 0x00060 to 0x02 To allow request packets to be issued write 1 b1 to the ENA field bit 30 of the Port General Control CSR 0x13C To set the destination ID of outgoing maintenance packets to 0x0 set the DESTINATION ID field bits 23 16 or the combined LARGE DESTINATION ID MSB DESTINATION ID fields bits 31 16 of the T
129. ayer Interfaces 4 29 In read requests if ios rd wr burstcount has a value greater than 1 the only valid value for ios rd wr byteenableisthe value of 16 xFFFF Table 4 11 lists the encoding in the packet header fields of a RapidIO read or write request packet when ios rd wr burstcount has a value greater than 1 Table 4 11 1 0 Logical Layer Slave Read Request Size Encoding Il Avalon MM Signal Values RapidlO Header Field Values 2 E byteenable wdptr rdsize 2 address 0 128 bit units 16 hxxxx 1 bx 4 bxxxx rio addr 3 2 FFFF 0 1100 0 3 FFFF 1 1100 0 4 FFFF 1 1100 0 5 FFFF 0 1101 0 6 FFFF 0 1101 0 7 FFFF 1 1101 0 8 FFFF 1 1101 0 9 FFFF 0 1110 0 10 FFFF 0 1110 0 11 FFFF 1 1110 0 12 FFFF 1 1110 0 13 FFFF 0 1111 0 14 FFFF 0 1111 0 15 FFFF 1 1111 0 16 FFFF 1 1111 0 Notes to Table 4 11 1 The 1 0 Logical layer slave module does not handle byteenable values and byteenable burstco unt combinations that the Avalon MM interface does not allow In case of an invalid byteenable or burstcount value the RapidlO II IP core asserts the ios rd wr readresponse signal when it asserts the ios rd wr readdatava id signal and sets the INVALID READ BYTEENABLE bit or the INVALID READ BURSTCOUNT bit or both of the 1 O Slave Interrupt register Table 6 60 on page 6 40 if this interrupt is enabled in the 1 0 Slave Interrupt Enable r
130. b0001 indicating a MAINTENANCE Write request config offset has a value that indicates an address outside the range of the RapidIO II IP core internal register set Figure 4 17 shows the signal relationships when the RapidIO II IP core presents a sequence of four write transfers on the Maintenance Avalon MM master interface Figure 4 17 Write Transfers on the Maintenance Avalon MM Master Interface System clock mnt m waitrequest mnt m write mnt m address L lij s dj c wv mnt m writedata ACACACAC 5C5C5C5C BEEFBEEF FACEFACE In the first active clock cycle the RapidIO II IP core indicates the start of a write transfer by asserting the usr mnt write signal Simultaneously the IP core presents the target address on the usr mnt address address bus and the data on the usr mnt writedata data bus In this example user logic does not assert the mnt waitrequest signal However when user logic asserts the usr mnt waitrequest signal during a write transfer the IP core maintains the address and data values on the buses until at least one clock cycle after user logic deasserts the mnt waitrequest signal User logic can use the usr mnt waitrequest signal to throttle requests on this interface until it is ready to
131. b0100 The value of 4 indicates an NREAD transaction The size and wdptr values encode the maximum size of the payload field In this example they decode to a value of 32 size 3 0 75 72 4 b1100 bytes For details refer to Table 4 3 in Part 1 Input Output Logical Specification of the RapidlO Interconnect Specification Revision 2 2 transactionID 7 0 71 64 8 hBB 128 h7654321 address 28 0 63 35 1 bO wdptr 34 0 Refer to the comment for size xamsbs 1 0 33 32 2 b00 February 2013 Altera Corporation RapidlO II MegaCore Function User Guide 4 56 Chapter 4 Functional Description Logical Layer Interfaces NREAD Response Transaction In the first clock cycle of the NREAD response on the Avalon ST pass through interface as shown in Figure 4 21 user logic asserts gen rx hd ready and gen rx pd ready and the IP core asserts gen rx hd valid and gen rx pd valid indicating it is providing valid data on gen rx hd data and gen rx pd data respectively The assertion of both the ready signal and the valid signal on each of the header and payload data Avalon ST interfaces makes the current cycle an Avalon ST ready cycle for both header and data The IP core asserts gen rx pd startofpacket to indicate the current cycle is the first valid data cycle of the packet In this clock cycle the IP core also makes the header and the first 128 bits of payload data available on gen rx hd data and gen rx pd data respectively
132. b1 Use the large transport device ID RSRV 14 0 RO Reserved 15 h0 Table 6 73 Packet Time to Live CSR Offset 0x32C Field Bits Access Function Default Maximum time duration that a packet is allowed to remain in a switch device where the value of OxFFFF indicates 100 ms 34 TAME TO EMT The RapidlO IP core does not use the contents of this field The 1619 field value is available on the time to live output signal RSRV 15 0 RO Reserved 16 h0 February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide Chapter 6 Software Interface Transport and Logical Layer Registers Table 6 74 Port 0 Error Detect CSR Offset 0x340 Part 1 of 2 Field Bits Access Function Default RSRV 31 RO Reserved for this implementation 1 h0 RSRV 30 24 RO Reserved Reserved for this implementation The RapidlO Il IP core PEDE 23 ix does not support the Parallel RapidlO protocol Received corrupt gontrol evibol 22 RW Received a control symbol with a bad CRC value 1 h0 Received ACK control with Unexpected 121 RW Received a packet accepted 0r packet retry control 1 h0 symbol with an unexpected acklD ackID Received packet not accepted 20 RW Received a packet not accepted control symbol 1 h0 control symbol Received packet with 19 RW Received a packet with an unexpected ackl
133. bitration transactions to this port 1 b1 Route or issue flow arbitration transactions to this port February 2013 Altera Corporation RapidlO II MegaCore Function User Guide 6 18 Chapter 6 Software Interface Physical Layer Registers Table 6 15 Port 0 Control CSR Offset 0x15C Part 3 of 4 Field EXTENDED PWIDTH OVRIDE Bits 15 14 Access RW Function Together with the PWIDTH_OVRIDE field bits 26 24 of this register indicates soft port configuration to control the width modes available for port initialization Refer to the description of the PWIDTH_OVRIDE field Default 2 b0 EXTENDED PORT_ WIDTH 13 12 RO Together with the PORT WIDTH field indicates the hardware widths this port supports Bit 13 8x support 1 b0 This port does not support a 8x RapidlO link 1 b1 This port supports a 8x RapidlO link Bit 12 16x support 1 b0 This port does not support a 16x RapidlO link 1 b1 This port supports a 16x RapidlO link The RapidlO II IP core does not support 8 lane or 16 lane variations so this field is always set to 2 b00 RSRV 11 8 RO Reserved 4 b0 DIS DEST ID CHK 7 RW This bit determines whether the RapidlO II IP core checks destination IDs in incoming request packets or promiscuously accepts all incoming request packets with a supported type The reset value is set in the RapidlO 1 parameter editor 1 b0 C
134. ble 6 93 Upon detecting the interrupt software can fetch the completed message and determine its status by reading the Tx Doorbell Completion Table 6 89 register and Tx Doorbell Completion Status register Table 6 90 respectively An outbound DOORBELL message is assigned a time out value based on the VALUE field of the Port Response Time Out Control register Table 6 8 on page 6 8 and a free running counter When the counter reaches the time out value if the DOORBELL transaction has not yet received a response the transaction times out Refer to Table 6 8 for information about how the time out value is calculated An outbound message that times out before its response is received is treated in the same manner as an outbound message that receives an error response if the TX_CPL field of the Doorbell Interrupt Enable register Table 6 92 on page 6 54 is set the Doorbell module generates an interrupt by asserting the drbell_s_irq signal and setting the ERROR_CODE field in the Tx Doorbell Completion Status register Table 6 90 to indicate the error If the interrupt is not enabled the Avalon MM master must periodically poll the Tx Doorbell Completion Status register to check for available completed messages before retrieving them from the Tx Completion FIFO DOORBELL request packets for which RETRY responses are received are resent by hardware automatically No retry limit is imposed on outbound DOORBELL messages Receiv
135. ce Avalon MM slave interface falls outside of all the enabled address mapping windows When these bits are set the system interruptsignalmnt mnt s is also asserted if the corresponding bit in the Maintenance Interrupt Enable register Table 6 40 on page 6 34 is set Maintenance Avalon MM Slave Interface s Error Indication Signal Themnt s readerror output signal is asserted when a response with ERROR status is received for a MAINTENANCE read request packet when a MAINTENANCE read times out or when the Avalon MM read address falls outside of all the enabled address mapping windows Maintenance Avalon MM Master The Maintenance Avalon MM master module processes the MAINTENANCE read and write request packets that it receives and generates response packets Anomalies are reported by generating ERROR response packets A response packet with ERROR status is generated in the following cases m Received a MAINTENANCE write request packet without payload or with more than 64 bytes of payload m Received a MAINTENANCE read request packet of the wrong size too large or too small m Received a MAINTENANCE read or write request packet with an invalid rdsize or wrsize value La These errors do not cause any of the standard defined errors to be declared and recorded in the Error Management registers RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 4 Functional Description 4 69 Error Detection and
136. ce family only Cyclone V GT devices support the 5 0 GBaud rate Release Information Table 1 5 provides information about this release of the RapidIO II IP core Table 1 5 10 Release Information Item Description Version 12 1 SP1 Release Date February 2013 Ordering Code IP RAPIDIOII Product ID 0108 Vendor ID 6AF7 February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 1 8 Chapter 1 About The RapidlO Il MegaCore Function Installation and Licensing Altera verifies that the current version of the Quartus II software compiles the previous version of each IP core Any exceptions to this verification are reported in the MegaCore IP Library Release Notes and Errata Altera does not verify compilation with IP core versions older than the previous release Installation and Licensing The RapidIO II IP core is part of the Altera MegaCore IP Library which is distributed with the Quartus II software and downloadable from the Altera website www altera com Figure 1 2 shows the directory structure after you install the RapidIO II IP core where path is the installation directory The default installation directory on Windows is C altera lt version number on Linux it is opt altera lt version number Figure 1 2 Directory Structure 3 path Installation directory pn Contains the Altera MegaCore IP Library and third party IP cores altera Con
137. cessing the received message when the internal hardware is busy for example when the Rx doorbell buffer is full February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide Chapter 4 Functional Description Logical Layer Interfaces Avalon ST Pass Through Interface The Avalon ST pass through interface is an optional interface that is generated when you select the Avalon ST pass through interface in the Transport and Maintenance page of the RapidIO II parameter editor refer to Enable Avalon ST Pass Through Interface on page 3 3 The Avalon ST pass through interface supports the following applications m User implementation of a RapidIO function not supported by this IP core for example data message passing m User implementation of a custom function not specified by the RapidIO protocol but which may be useful for the system application After packets appear on your RapidIO II IP core Rx Avalon ST pass through interface your application can route them to a local processor or custom user function to process them according to your design requirements Transaction ID Ranges To limit the required storage the RapidIO II IP core shares a single pool of transaction IDs among all destination IDs although the RapidIO specification allows for independent pools for each Source Destination pair To simplify the routing of incoming ftype 13 response packets the IP core assigns an exclusive range of transaction IDs to eac
138. cle is an Avalon ST ready cycle The user logic provides valid data on gen tx data for the IP core to sample and asserts gen tx startofpacket to indicate the current value of gen tx data is the initial piece of the current packet the start of packet gen tx packet size user logic reports the full length of the packet is OxC which is decimal 12 because the packet comprises 12 bytes of header The NREAD request transaction contains no payload data The NREAD request requires a single clock cycle During this clock cycle user logic asserts gen tx endofpacket and reports on gen tx empty that the number of empty bytes is 4 The initial 12 bytes of the NREAD request packet contain header information Table 4 31 lists the header fields and their values in this example Table 4 31 NREAD Request Transmit Example RapidlO Header Fields on the gen tx data Bus gen tx data Field Bits Value Comment Value is a don t care because it is overwritten by the Physical ackID 127 122 6 h00 layer ackID value before the packet is transmitted on the RapidlO link vc 121 0 The RapidlO II IP core supports only VCO CRF 120 0 prio 1 0 119 118 2 b01 tt 1 0 117 116 2 b01 The value of 1 indicates 16 bit device IDs ftype 3 0 115 112 4 b0010 The value of 2 indicates a Request Class packet destinationId 15 0 111 96 8 hDDDD sourceId 15 0 95 80 8 hAAAA ttype 3 0 79 76 4
139. ction Default Starting offset into the Avalon MM address space The four OFFSET 31 4 RW least significant bits of the 32 bit offset are assumed to be 28 h0 zero RSRV 3 0 RO Reserved 4 h0 Input Output Master Interrupts Table 6 54 and Table 6 55 describe the available Input Output master interrupt and corresponding interrupt enable bit The RapidIO IP core asserts the io m mnt signal if the interrupt bit is enabled Table 6 54 Input Output Master Interrupt Offset 0x103DC Field Bits Access Function Default RSRV 31 1 RO Reserved 31 h0 Address out of bounds ADDRESS OUT OF BOUNDS 0 RW1C Asserted when the RapidlO address does not fall within any 1 bO enabled address mapping window Table 6 55 Input Output Master Interrupt Enable Offset 0x103FC Field Bits Access Function Default RSRV 31 1 RO Reserved 31 h0 ADDRESS OUT OF BOUNDS 0 RW Address out of bounds interrupt enable 1 b0 Input Output Slave Mapping Registers Table 6 56 through Table 6 61 describe the Input Output slave registers The registers define windows in the Avalon MM address space that are used to determine the outgoing request packet s ftype DESTINATION ID priority and address fields There are up to 16 register sets one for each possible address mapping window The 16 possible register address offsets are shown in the table titles Refer to
140. cy Signals The low latency signals connect to the lowest level of the Physical layer module to minimize latency Table 5 5 and Table 5 6 list the low latency signals RapidlO II MegaCore Function User Guide February 2013 Altera Corporation Chapter 5 Signals 5 3 Physical Layer Signals Multicast Event Signals Table 5 5 lists the multicast event signals Table 5 5 Multicast Event Signals Signal Direction Description Change the value of this signal to indicate the RapidlO II IP core should transmit a multicast event control symbol After you assert the send multicast event signal await asssertion of the send multicast event Input sent multicast event signal before you toggle this signal again If you toggle this signal before you see the sent multicast event confirmation from the previous change of value the number of multicast events that are sent is undefined multicast event rx Output Changes value when a multicast event control symbol is received Indicates the RapidlO II IP core has queued a multicast event control symbol for transmission sent multicast event Output Link Request Reset Device Signals Table 5 6 lists the link request reset device control symbol request and confirmation signals Table 5 6 Link Request Reset Device Signals Signal Direction Description Change the value of this signal to indicate the RapidlO II IP core should transmit five 1ink request rese
141. d as an endpoint through non maintenance operations This local address space may be limited to local configuration registers or can be on chip SRAM or another memory device Processor Present Processor present when turned on sets the Processor bit in the Processing Element Features CAR and indicates that the processing element physically contains a local processor such as the Nios II embedded processor or similar device that executes code A device that bridges to an interface that connects to a processor should set the Bridge bit as described in Bridge Support instead of the Processor bit Enable Flow Arbitration Support Enable flow arbitration support when turned on sets the Flow Arbitration Support bit in the Processing Element Features CAR and indicates that the processing element supports flow arbitration Enable Standard Route Table Configuration Support Enable standard route table configuration support when turned on sets the Standard route table configuration support bit in the Processing Element Features CAR and indicates that the processing element supports the standard route table configuration mechanism This property is relevant in switch processing elements only February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 3 8 Chapter 3 Parameter Settings Capability Registers Settings If you turn on Enable standard route table configuration support user logic must implement the functi
142. d signal for this lane has ERE changed since this bit was last read Reading the register resets this bit eae 6 RO to the value of 1 00 A change in the signal value indicates that the 9 training state of the adaptive equalization under the control of this receiver has changed frequent changes indicate a problem on the lane RSRV 5 4 RO Reserved 200 UE Indicates whether the RapidlO implementation includes the Lane n i 3 RO Status 1 CSR for the current lane The RapidlO II IP core P implements this register so this bit always has the value of 1 b1 Number of implementation specific Lane Status m CSRs for the Status 2 7 current lane n The RapidlO II IP core implements the Lane n Status 2 CSRs 2 0 RO Lane n Status and Lane n Status 4 CSRs so this field always has the 3 b011 Implemented value of 2 b011 For the value encoding refer to Rapid O Interconnect Specification v2 2 Part 6 LP Serial Physical Layer Specification Note to Table 6 17 1 Reflects the choice made in the RapidlO II parameter editor February 2013 Altera Corporation RapidlO II MegaCore Function User Guide 6 22 Chapter 6 Software Interface Physical Layer Registers Table 6 18 LP Serial Lane n Status 1 Far End Lane n Status Offset 0x214 0x234 0x254 0x274 Part 1 of 2 Field IDLE2 received IDLE2 information current Bits 31 30 Access RW1C RO Functi
143. d wr read Input 1 0 Logical Layer Avalon MM Slave module read request 1 0 Logical Layer Avalon MM Slave module address bus Refer to Defining the Input Output Avalon MM Slave Address Mapping ios rd wr address N 0 input Windows on page 4 22 for information about the RapidlO II IP core for N 9 10 OF 31 p process to determine the values for the corresponding RapidlO packet header fields You determine the width of the ios rd wr address bus in the RapidlO parameter editor ios rd wr writedata 127 0 Input 1 0 Logical Layer Avalon MM Slave module write data bus ios rd wr byteenable 15 0 Input 1 0 Logical Layer Avalon MM Slave module byte enable ios rd wr burstcount 4 0 Input 1 0 Logical Layer Avalon MM Slave module burst count 1 0 Logical Layer Avalon MM Slave module read error response 1 0 ios rd wr readresponse Output Logical Layer Avalon MM Slave module read error Indicates that the burst read transfer did not complete successfully ios rd wr readdata 127 0 Output 1 0 Logical Layer Avalon MM Slave module read data bus ios rd wr readdatavalid Output 1 0 Logical Layer Avalon MM Slave module read data valid The I O Avalon MM Slave module supports an interrupt line io s mnt on the Register Access interface When enabled the following interrupts assert the signal The interface supports an interruptline s mnt When enabled the following interrupts assert th
144. dIO II IP core you can enable or disable the DOORBELL operation feature depending on your application requirements If you do not need the DOORBELL feature disabling it reduces device resource usage If you enable the feature 32 bit Avalon MM slave port is created that allows the RapidIO core to receive and generate RapidIO DOORBELL messages Doorbell Module Block Diagram Figure 4 20 illustrates the Doorbell module This module includes a 32 bit Avalon MM slave interface to user logic The Doorbell module contains the following logic blocks m Register and FIFO interface that allows an external Avalon MM master to access the Doorbell module s internal registers and FIFO buffers m Txoutput FIFO that stores the outbound DOORBELL and response packets waiting for transmission to the Transport layer module m Acknowledge RAM that temporarily stores the transmitted DOORBELL packets pending responses to the packets from the target RapidIO device m Txtime out logic that checks the expiration time for each outbound Tx DOORBELL packet that is sent m Rxcontrol that processes DOORBELL packets received from the Transport layer module Received packets include the following packet types m Rx DOORBELL request m response DONE to a successfully transmitted DOORBELL packet m Rx response RETRY to a transmitted DOORBELL message m Rx response ERROR to a transmitted DOORBELL message m FIFO that stores the received DOORBELL
145. ddress register offset 23 0 is the OFFSET field of the window offset register Responding to MAINTENANCE Read and Write Requests To respond to a MAINTENANCE read or write request packet it receives on the RapidIO link the RapidIO II IP core sends a read or write request to the Maintenance module master interface Refer to Maintenance Interface Transaction Examples on page 4 38 for examples of how the RapidIO MAINTENANCE request appears on the Maintenance module master port and the expected format of your system response IP Core Actions In response to incoming MAINTENANCE requests on the RapidIO link that do not target the RapidIO II IP core internal register set the RapidIO II IP core Maintenance module generates Avalon MM requests on the Maintenance module master interface by performing the following tasks m For a MAINTENANCE read converts the received request packet to an Avalon read request and presents it across the Maintenance Avalon MM master interface m ForaMAINTENANCE write converts the received request packet to an Avalon write transfer and presents it across the Maintenance Avalon MM master interface February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 4 36 Chapter 4 Functional Description Logical Layer Interfaces m For each Avalon read request the IP core presents on the Maintenance Avalon MM master interface the Maintenance module accepts the data response generates a Type 8 Respon
146. dlO II MegaCore Function User Guide February 2013 Altera Corporation Chapter 6 Software Inter face Transport and Logical Layer Registers Table 6 84 Rx Doorbell Offset 0x00 6 53 February 2013 Altera Corporation Field Bits Access Function Default Reserved if the system does not support 16 bit device ID LARGE SOURCE ID YT MSB E 31 24 RO MSB of the DOORBELL message initiator device ID if the system 8 b0 supports 16 bit device ID SOURCE_ID 23 16 RO Device ID of the DOORBELL message initiator 8 b0 INFORMATION MSB 15 8 RO Received DOORBELL message information field MSB 8 b0 INFORMATION LSB 7 0 RO Received DOORBELL message information field LSB 8 b0 Table 6 85 Rx Doorbell Status Offset 0x04 Field Bits Access Function Default RSRV 31 8 RO Reserved 24 b0 Shows the number of available DOORBELL messages in the Rx FIFO ee ee A maximum of 16 received messages is supported i Table 6 86 Tx Doorbell Control Offset 0x08 Field Bits Access Function Default RSRV 31 2 RO Reserved 30 h0 Request Packet s priority 2 11 is not a valid value for the PRIORITY 1 0 RW priority field An attempt to write 2 11 to this field will be 2 h0 overwritten as 2 b10 Table 6 87 Tx Doorbell Offset 0x0C Field Bits Access Function Default R
147. dptr packet fields determine the value of the PAYLOAD SIZE field in the Rx Port Write Status register Table 6 49 on page 6 37 E wdptr the values in the wrsize and wdptr packet fields determine the value of the PAYLOAD SIZE field in the Rx Port Write Status register Table 6 49 on page 6 37 B payload the Maintenance module copies the value of the payload packet field to the Rx Port Write Buffer starting at register address 0x10260 This buffer holds a maximum of 64 bytes While the IP core is writing the payload to the buffer it holds the PORT WRITE BUSY bit of the Rx Port Write Status register asserted After the payload is completely written to the buffer if you have set the RX PACKET STORED bit of the Maintenance Interrupt Enable register Table 6 40 on page 6 34 the IP core asserts the interrupt signal mnt mnt s the Register Access interface to alert your system of the port write request February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 4 38 Chapter 4 Functional Description Logical Layer Interfaces Maintenance Interface Transaction Examples This section contains examples of communication on the RapidIO II IP core Maintenance interface Table 4 15 lists the examples Table 4 15 Maintenance Interface Usage Examples User Operation Device ID Width Payload Size Bytes Send MAINTENANCE Write request 8 32 Receive MAINTENANCE Write request 8 3
148. dule 0666s 4 19 Initiating Read and Write Transactions 0 2 2 0c cc 4 20 Avalon MM Burstcount and Byteenable Encoding in RapidIO Packets 4 27 Input Output Avalon MM Slave Module Timing Diagrams 4 31 Maintenance Module ecce terere tes rea CERERI qa Rea EE E 4 32 Maintenance Interface Transactions 4 33 Maintenance Interface Signals sneren ce be dee hd Re ea b hr hei eee 4 33 Initiating MAINTENANCE Read and Write Transactions 4 34 Responding to MAINTENANCE Read and Write Requests 4 35 Handling Port Write Transactions 000000 ne 4 36 Maintenance Interface Transaction Examples 4 38 Maintenance Packet Error Handling 00 eens 4 43 Doorbell Modules Em 4 43 Doorbell Module Block Diagram III e 4 44 Preserving Transaction Onder ced e aie ha ele eee Soe 4 45 Doorbell Module Signals tag er beg er en 4 46 Generating a Doorbell Message 2 6 occ nee 4 46 Receiving a Doorbell Message e lee 4 47 Avalon ST Pass Through Interface ten nacie ii nee 4 48 Transaction ID Ranges ated Ex eru epe utes we e Rai ons 4 48 Pass Through Interface Signals
149. e RapidlO II MegaCore Function February 2013 Altera Corporation User Guide Chapter 4 Functional Description 4 25 Logical Layer Interfaces Input Output Slave Translation Window Example This section contains an example illustrating the use of I O slave translation windows In this example a RapidIO IP core with 8 bit device ID communicates with three other processing endpoints through three I O slave translation windows For this example the bits are set to 2 b00 for all three windows The offset value differs for each window which results in the segmentation of the RapidIO address space that is shown in Figure 4 10 Figure 4 10 Input Output Slave Translation Window Address Mapping RapidlO Address Space Ox3FFFFFFFF Avalon MM Address Space 0x100000000 OxFFFFFFFF OxOFFFFFFFF PE2 PE2 0xC0000000 0x0C0000000 OxBFFFFFFF OxOBFFFFFFF PE 1 PE 1 0x80000000 0x080000000 Ox7FFFFFFF Ox07FFFFFFF PEO PEO 0x40000000 0x040000000 Ox3FFFFFFF Ox03FFFFFFF 0x00000000 0x000000000 In the example the two most significant bits of the Avalon MM address are used to differentiate between the processing endpoints Figure 4 12 through Figure 4 20 show the address translation implemented for each window Each figure shows the value for the destination ID of the control register for one window Translation Window 0 An Avalon MM address in which the two mo
150. e Function User Guide February 2013 Altera Corporation Chapter 6 Software Interface 6 15 Physical Layer Registers Table 6 14 Port 0 Error and Status CSR Offset 0x158 1 Part 4 of 4 Field Bits Access Function Default This bit is set if the input port error recovery state machine encounters an unrecoverable error or the output port error recovery state machine enters the fatal error state The input port error recovery state machine encounters an unrecoverable error if it times out while waiting for a 1ink request after sending a packet not accepted control symbol The output port error recovery state machine enters the fata error state if the following sequence of events occurs 1 The output port error recovery state machine enters the stop output state when it receives a packet not accepted control symbol In response it sends the input status link request input status restart from error control symbol EBR 2 Be 2 One of the following events occurs in response to the Link request Hu control symbol m If the link response is received but the ackID is outside of the outstanding ackID set or the port status value is Error then the output port error recovery state machine enters the error state m Ifthe port times out before receiving 1ink response for seven attempts to send a 1ink request then the output port error recovery state machine enters the error state When t
151. e Tx Maintenance Address Translation Window registers as defined in Table 6 41 through Table 6 44 Refer to Defining the Maintenance Address Translation Windows on page 4 34 for the matching and conversion calculations wdptr The IP core assigns to this field the negation of mmt s address 2 The IP core assigns to this field the value programmed in the HoP COUNT field ofthe Tx Maintenance Mapping Window n Control register Table 6 44 hop count on page 6 35 for the matching address translation window n Refer to Defining the Maintenance Address Translation Windows on page 4 34 for matching details payload 63 0 February 2013 Altera Corporation The IP core assigns the value of mmt s writedata 31 0 to the appropriate half of this field RapidlO 11 MegaCore Function User Guide 4 40 Chapter 4 Functional Description Logical Layer Interfaces User Receiving MAINTENANCE Write Requests Table 4 18 lists the Maintenance Avalon MM interface usage example this section describes Table 4 18 Maintenance Interface Usage Example Receiving MAINTENANCE Write Request User Operation Device ID Width Payload Size Bytes Receive MAINTENANCE Write request 8 32 The RapidIO II IP core generates write transfers on the Maintenance Avalon MM master interface in response to Type 8 MAINTENANCE Write request packets on the RapidIO link with the following properties ttype has the value of 4
152. e defined in Rapid O Interconnect Specification v2 2 Part 6 LP Serial Physical Layer Specification and described in Physical Layer Registers on page 6 6 0x200 LP Serial Lane Register Block Header 0x210 Lane 0 Status 0 Local 0x214 Lane 0 Status 1 Far End 0x218 Lane 0 Status 2 Interrupt Enable Lane 0 Status Received CS uae Commands 0x220 Lane 0 Status 4 Outgoing CS Field Physical layer 0 230 0 280 Lan e 1 3 Status RapidlO II MegaCore Function User Guide February 2013 Altera Corporation Chapter 6 Software Interface Memory Map 6 5 Table 6 4 Extended Features and Implementation Defined Registers Memory Map Part 2 of 3 Address Extended Features Space Error Management Extensions These registers are defined the RapidlO Interconnect Specification Part 8 Error Management Extensions Specification and described in Error Management Registers on page 6 41 Used by Module Error Management Extensions Block 0 304 Reserved 0x308 Logical Transport Layer Error Detect 0x30C Logical Transport Layer Error Enable Logical Transport Layer High Address 0x310 Capture Reserved RapidlO II IP core has only 34 bit RapidlO addressing 0x314 Logical Transport Layer Address Logical Transport layer Capture 0x318 E ee Layer Device ID Ox31C oo
153. e io s mnt irqsignal Read out of bounds Write out of bounds Invalid write Invalid read or write burstcount Invalid read or write byteenable value For more information about the I O Logical layer Avalon MM slave module interrupts refer to Table 6 60 on page 6 40 and Table 6 61 on page 6 40 Initiating Read and Write Transactions To initiate a read or write transaction on the RapidIO link your system sends a read or write request to the I O Logical layer Slave module Avalon MM interface RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 4 Functional Description 4 21 Logical Layer Interfaces IP Core Actions In response to incoming Avalon MM read requests to the I O Logical layer Slave module the RapidIO II IP core generates read request packets on the RapidIO link by performing the following tasks For each incoming Avalon MM read request composes the RapidIO read request packet For each incoming Avalon MM write request composes the RapidIO write request packet Maintains status related to the composed packet to track responses m Sendsread request information to the Pending Reads buffer to wait for the corresponding response packet m Sends NWRITE Rrequest information to the Pending Writes buffer to wait for the corresponding response packet m Does not send SWRITE and NWRITE request information to the Pending Writes buffer because these transactions do not require a response to
154. e output port is in the Output Error Stopped state Output port has been stopped due to a transmission error and is trying to recover The port enters this state when it receives a packet not accepted control symbol To exit from this state the port issues an input status link request input status restart from error control symbol The port waits for the 1ink response control symbol and exits the Output Error Stopped state RSRV 15 11 RO Reserved 5 b0 February 2013 Altera Corporation RapidlO II MegaCore Function User Guide 6 14 Chapter 6 Software Interface Physical Layer Registers Table 6 14 Port 0 Error and Status CSR Offset 0x158 1 Part 3 of 4 this bit always has the value of 0 Field Bits Access Function Default Input port is stopped due to a retry This bit is set when the input port is in the nput Retry Stopped state When the receiver issues a packet retry control symbol to its link partner it enters the nput Retry IN RTY STOP 10 RO Stopped state The receiver issues a packet retry when sufficient 1 b0 buffer space is not available to accept the packet for that specific priority The receiver continues in the Input Retry Stopped state until it receives a restart from retry control symbol Input port has encountered a transmission error This bit is set if the IN ERR ENC 9 RW1iC IN_ERR STOP bit is set After it is set this bit i
155. e packet size encoding that the RapidIO ILIP core implements for read requests refer to Table 4 10 and Table 4 11 For information about the packet size encoding that the RapidIO IL IP core implements for write requests refer to Table 4 10 and Table 4 12 Table 4 10 lists the allowed Avalon MM ios rd wr byteenable values if ios rd wr burstcount has the value of 1 and the corresponding encoding in the packet header fields of a RapidIO read or write request packet Table 4 10 1 0 Logical Layer Slave Read or Write Request Size Encoding Part 1 of 2 Avalon MM Signal Values 1 RapidiO Header Field Values con byteenable wdptr address 0 128 bit units 16 Ipoox xxxx xxxx xxxx 1 bx 4 bxxxx rio addr 3 1 0000 0000 0000 0001 1 0011 0 1 0000 0000 0000 0010 1 0010 0 1 0000 0000 0000 0100 1 0001 0 1 0000 0000 0000 1000 1 0000 0 February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 4 28 Chapter 4 Functional Description Logical Layer Interfaces Table 4 10 1 0 Logical Layer Slave Read or Write Request Size Encoding Part 2 of 2 Avalon MM Signal Values 1 RapidlO Header Field Values pris ag byteenable wdptr ear rd address 0 128 hit units 16 Ipoxx xxxx xxxx xxxx 1 bx 4 maxx rio addr 3 1 0000 0000 0001 0000 0 0011 0 1 0000 0000 0010 0000 0 0010 0 1 0000 0000 0100
156. e processed through the Avalon ST pass through interface rather than being processed through one of the I O Logical layer modules Table 4 29 lists the examples Table 4 29 Avalon ST Pass Through Interface Usage Examples User Operation e RapidlO Transaction Priority sac 5 Send read request Tx NREAD 1 16 32 Receive read response Rx Response with payload 2 16 32 Receive read request Rx NREAD 1 16 32 Send read response Tx Response with payload 2 16 32 February 2013 Altera Corporation RapidlO II MegaCore Function User Guide 4 54 User Sending Read Request and Receiving Read Response Table 4 30 lists the Avalon ST pass through interface usage example this section describes Refer to Transaction ID Ranges on page 4 48 and Receiver on page 4 60 for a description of the RapidIO II IP core variations in which this example transaction is processed through the Avalon ST pass through interface rather than being processed through one of the I O Logical layer modules Chapter 4 Functional Description Logical Layer Interfaces Table 4 30 Avalon ST Pass Through Interface Usage Example Sending Read Request and Receiving Response Device ID Payload Size User Operation Type RapidlO Transaction Priority Width Bytes Send read request Tx NREAD 1 16 32 Receive read response Rx Response with payload 2 16 32 Figure 4 21 shows the behavior o
157. easserted the testbench waits until both the DUT and the sister rio modules have driven their port initialized output signals high These signal transitions indicate that both IP cores have completed their initialization sequence The testbench then waits an additional 5000 ns to allow time for a potential reset link request control symbol exchange between the DUT and the sister rio module The testbench again waits until both the DUT and the sister rio modules have driven their port initializedoutput signals high Following the 5000 ns wait the testbench checks that the port initialization process completed successfully by reading the Error and Status CSR to confirm the expected values of the PORT OK and PORT UNINIT register bits These register fields indicate that the link is established and the Physical layer is ready to exchange traffic Next basic programming of the internal registers is performed in the DUT and the sister rio module Table 7 1 shows the registers that are programmed in both the DUT and the sister rio IP cores For a full description of each register refer to Chapter 6 Software Interface Table 7 1 Testbench Registers Part 1 of 2 rio rio Register Ei Address Register Name Description Value 32 h00AB FFFF Program the DUT to have an 8 bit base device ID REDI year eee errr of oxaB or a 16 bit device ID of 4 32 h00FF 0x0013C Control Enable Request packet generation by the
158. econfiguration Controller chapter of the Altera Transceiver PHY IP Core User Guide for more information about the Transceiver Reconfiguration Controller interfaces and how to control dynamic reconfiguration for multiple transceiver channels Refer to Table 5 7 on page 5 4 for information about the reconfig fromgxb and reconfig togxb signals that connect a single RapidIO II IP core to multiple Transceiver Reconfiguration Controller interfaces of the same Transceiver Reconfiguration Controller February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 2 10 Chapter 2 Getting Started Instantiating Multiple RapidlO II IP Cores RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide N DTE YN 3 Parameter Settings You customize the RapidIO II IP core by specifying parameters in the RapidIO H parameter editor which you access from the MegaWizard Plug In Manager or the Qsys system integration tool in the Quartus II software This chapter describes the parameters and how they affect the behavior of the IP core Each section corresponds to a tab in the RapidIO II parameter editor In the RapidIO II parameter editor you use the following tabs to parameterize the RapidIO II IP core Physical Layer Transport Layer Logical Layer Capability Registers Command and Status Registers Error Management Registers Physical Layer Settings The Physical layer includes RapidIO II specific logic configuration and t
159. ection Description Sys clk Input Avalon system clock tx pll refclk Input Physical layer reference clock Receive side recovered clock This signal is derived from the incoming RapidlO data Refer to Recovered Data Clock on page 4 3 tx clkout Output Transceiver transmit side clock rx clkout Output Table 5 2 Global Reset Signal Signal Direction Description Active low system reset This reset is associated with the Avalon system clock rst n Can be asserted asynchronously but must stay asserted at least one clock cycle and must be de asserted synchronously with sys 1 To reset the IP core correctly you must also assert this signal together with the reset input signal to the Altera Transceiver PHY Reset Controller IP core to which you must connect the RapidlO II IP core Refer to Reset for RapidlO II IP Cores on page 4 4 Altera recommends that you apply an explicit 1 to o transition on the rst_n input port in simulation to ensure that the simulation model is properly reset rst n Input Physical Layer Signals Table 5 3 through Table 5 8 list the signals the Physical layer of the RapidIO core Table 5 3 RapidlO Interface Signal Direction Description Receive data a unidirectional data receiver It is connected to the td bus of the transmitting device Transmit data a unidirectional data driver The td bus of one device is connected to the rd bus of the receiving
160. ed off Logical Layer Settings The Logical layer settings specify properties of the following Logical layer modules m Maintenance module m Doorbell module m I O master module m I Oslave module February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 3 4 Chapter 3 Parameter Settings Logical Layer Settings Maintenance Configuration Settings The Maintenance module settings specify properties of the Maintenance Logical layer If you turn on Enable Maintenance module a Maintenance module is configured in your RapidIO II IP core If the Maintenance module is enabled the Maintenance address bus width parameter is available to determine the Maintenance slave interface address bus width This parameter currently supports only a 26 bit address width This parameter controls the width of the Maintenance slave interface address bus only The Maintenance master interface address bus is 32 bits wide The Maintenance module supports RapidIO MAINTENANCE read and write operations and MAINTENANCE port write operations For more information about the Maintenance module refer to Maintenance Module on page 4 32 Doorhell Configuration Settings The Doorbell module settings specify properties of the Doorbell Logical layer module If you turn on Enable Doorbell support a Doorbell module is configured in your RapidIO II IP core to support generation of outbound RapidIO DOORBELL messages and reception and processing of
161. ed port REMOTE TX EMPH S 1 b0 The port does not support adjusting the transmit emphasis in i IR t RO 1 b1 UPPORT the connected port 1 b1 The port supports adjusting the transmit emphasis in the connected port Indicates whether the port may transmit commands to control the transmit emphasis in the connected port 1 b0 Adjusting the transmit emphasis in the connected port is ac em RW disabled in this port 11 1 b1 Adjusting the transmit emphasis in the connected port is enabled in this port This field can only have this value if REMOTE TX EMPH SUPPORT has the value of 1 Table 6 14 Port 0 Error and Status CSR Offset 0x158 1 Part 1 of 4 Field Bits Access Function Default Indicates whether the port supports the IDLE2 sequence for baud rates of 5 0 and below 1 b0 Port does not support the IDLE2 sequence for baud rates of 5 0 and below IDLE2 SUPPORT 31 RO 1 b1 1 b1 Port supports the IDLE2 sequence for baud rates of 5 0 and below The RapidlO II IP core currently supports only the IDLE2 sequence so this bit always has the value of 1 Indicates whether the the IDLE2 sequence is enabled in the RapidlO implementation for baud rates of 5 0 and below 1 bO The IDLE2 sequence is disabled for baud rates of 5 0 and below IDLE2 ENABLE 30 RO 1 b1 1 b1 The IDLE2 sequence is enabled for baud rates of 5 0 and below The RapidlO II IP core currently supports only the IDLE2 sequence so this bit always has the va
162. ee rarere 4 67 Maintenance Avalon MM Master 0 ccc ccc en een 4 68 Port Write Reception Module 2 e e rre er x ep PEE E PER ETE ed 4 69 Port Write Transmission Module 0 c ec 4 69 Input Output Avalon MM Slave 00 4 69 Input Output Avalon MM Master n 4 70 Avalon ST Pass Through Interface 1 0 0 0 ne 4 71 Chapter 5 Signals Global Signals itte pte i pete e ERR REE edocet M 5 1 Physical Layer Signals e reete EUR ERU NR CEU eae PERO Pa vex ed ree dtes 5 1 Status Packet and Error Monitoring Signals 0 00 66 5 2 Low Latency Signals etes as teer o e ERR HORA ee a t diee aod 5 2 Multicast Event Signals b e ke eb e dH ee E e rd Re ECC a 5 3 Link Request Reset Device Signals eh 5 3 Transceiver Signals esaeet aaiae aad eria Hess Adee pressa ig esc bak e acea eer 5 3 Register Related Signals ies m Remb em eed ha m eoe d bie oed e Er 5 5 Logical and Transport Layer Signals n 5 5 Avalon MM Interface Signals 0 0 0 00 ccc ccc e en 5 5 Avalon ST Pass Through Interface Signals 000 e eee eee ee 5 6 Data Streaming Support Signals sss enn 5 6 Packet and Error Monitoring Signal for the Transport Layer 5 7 Error Management Extension Signals sss n 5 8 Error Reporting Signals 222
163. efining the Input Output Avalon MM Master Address Mapping Windows When you specify the value for Number of Rx address translation windows in the RapidIO II parameter editor you determine the number of address translation windows available for translating incoming RapidIO read and write transactions to Avalon MM requests on the I O Logical layer Master port You must program the Input Output Master Mapping Window registers to support the address ranges you wish to distinguish You can disable an address translation window that is available in your configuration but the maximum number of windows you can program is the number you specify in the RapidIO II parameter editor with the Number of Rx address translation windows value The RapidIO IP core includes one set of Input Output Master Mapping Window registers for each translation window The following registers define address translation window n baseregister Input Output Master Mapping Window Base Table 6 51 on page 6 37 m Amaskregister Input Output Master Mapping Window Mask Table 6 52 m Anoffset register Input Output Master Mapping Window Offset Table 6 53 You can change the values of the window defining registers at any time You should disable a window before changing its window defining registers To enable a window set the window enable WEN bit of the window s Input Output Master Mapping Window Mask register Table 6 52 on page 6 37 to the value
164. egister E DESTINATION ID WB priority E wrsize The RapidIO IP core assigns the following values to the fields of the MAINTENANCE port write packet m Assigns ftype the value of 4 b1000 m Assigns ttype the value of 4 b0100 m Calculates the values for the wdptr and wrsize fields of the transmitted packet from the size of the payload to be sent as defined by the size field of the Tx Port Write Control register m Assigns the value of 0 to the Reserved source tidand config offset fields The IP core creates the packet s payload from the contents of the Tx Port Write Buffer sequence of registers starting at register address 0x10210 This buffer can store a maximum of 64 bytes The IP core starts the packet composition and transmission process after you set the PACKET READY bit in the Tx Port Write Control register The RapidIO IP core composes the Maintenance port write packet and transmits it on the RapidIO link Port Write Reception When the RapidIO II IP core Maintenance module receives a MAINTENANCE port write request packet type has the value of 4 b1000 and ttype has the value of 4 b0100 from the Transport layer it extracts information from the packet header and uses the information to write to registers Rx Port Write Control Table 6 48 on page 6 36 through Rx Port Write Buffer Table 6 50 on page 6 37 The Maintenance module extracts information from the following fields wrsize the values in the wrsize and w
165. egister Table 6 61 page 6 40 2 For read transfers the read size of the request packet is rounded up to the next supported size but only the number of words corresponding to the requested read burst size is returned For write requests if ios rd wr burstcount has a value greater than 1 the value of ios rd wr byteenable can be different in the first intermediate and final clock cycles of the same request In all intermediate clock cycles when ios rd wr burstcount has a value greater than 2 ios rd wr byteenable must have the value of 16 xFFFF Table 4 12 lists the allowed Avalon MM ios rd wr burstcount and initial and final clock cycle ios rd wr byteenable value combinations if the value of ios rd wr burstcount is greater than 1 and their encoding in the packet header fields of a RapidIO write request packet February 2013 Altera Corporation RapidlO II MegaCore Function User Guide 4 30 Chapter 4 Functional Description Logical Layer Interfaces Avalon MM value combinations not listed in Table 4 12 flag interrupts in the RapidIO II IP core For more information about the relevant interrupts refer to Table 6 60 on page 6 40 Table 4 12 1 0 Logical Layer Slave Write Request Size Encoding Il Part 1 of 2 Avalon MM Signal Values 1 RapidlO Header Field Values M
166. egraded error threshold in the Port 0 Error Rate Threshold register Table 6 82 on page 6 52 has been reached After it is set this bit is cleared only when software writes the value of 1 to it Reserved 1 0 300 OUT RTY OUT RETRIED 20 19 RW1C RO Output port has encountered a retry condition In all cases this condition is caused by the port receiving a packet retry control symbol This bit is set if the OUT RTY STOP bitis set Output port has received a packet retry control symbol and cannot make forward progress This bit is cleared when a packet accepted Or packet not accepted control symbol is received 1 b0 OUT RTY STOP 18 RO Indicates that the output port is in the Output Retry Stopped state Output port has been stopped due to a retry and is trying to recover When a port receives a packet retry control symbol it enters the Output Retry Stopped state In this state the port transmits a restart from retry control symbol to its link partner The link partner exits the nput Retry Stopped state and normal operation resumes The port exits the Output Retry Stopped state OUT ERR ENC 17 RW1C Output port has encountered a transmission error and has possibly recovered from it This bit is set when the OUT ERR STOP bit is set After it is set this bit is cleared only when software writes the value of 1 to it OUT ERR STOP 16 RO Indicates that th
167. en RapidlO Il MegaCore Function and RapidlO MegaCore Function v12 1 February 2013 Altera Corporation N DTE BAAN Additional Information This chapter provides additional information about the document and Altera Document Revision History The following table shows the revision history for this user guide Date Version Changes m Added device programming Programming Object File pof support for Arria V devices m Added support for Arria V GZ devices February 2013 121 sp4 Added support for Cyclone V devices Cyclone V GT devices support rates up to 5 0 Gbaud and other Cyclone V devices support rates up to 3 125 Gbaud m Clarified in Adding Transceiver Analog Settings on page 2 7 that this procedure is required only for Arria V GZ and Stratix V devices November 2012 12 1 Initial release How to Contact Altera To locate the most up to date information about Altera products refer to the following table Contact 1 Contact Method Address Technical support Website www altera com support A Website www altera com training Technical training Email custrain altera com Product literature Website www altera com literature Nontechnical support general Email nacomp altera com software licensing Email authorization altera com Note to Table 1 You can also contact your local Altera sales office or sales representative Typographic Conventions The following
168. en rx pd valid because the NREAD request transaction contains no payload data Table 4 34 lists the header fields of the request packet in this example Table 4 34 NREAD Request Receive Example RapidlO Header Fields in gen rx hd data Bus Field Value Comment pd size 8 0 114 106 9 h000 An NREAD request transaction has no payload data vc 105 0 The RapidlO II IP core supports only VCO CRF 104 0 prio 1 0 103 102 2 b01 tt 1 0 101 100 2 b01 Indicates 16 bit device IDs ftype 3 0 99 96 4 b0010 The value of 2 indicates a Request Class packet destinationID 15 0 95 80 16 hDDDD sourceID 15 0 79 64 16 hAAAA ttype 3 0 63 60 4 b0100 The value of 4 indicates an NREAD transaction The size and wdptr values encode the maximum size of the payload field In this example they decode to a size 3 0 59 56 4 b1100 value of 32 bytes For details refer to Table 4 3 in Part 1 Input Output Logical Specification of the RapidlO Interconnect Specification Revision 2 2 transactionID 7 0 55 48 8 hBB address 28 0 47 19 SR wdptr 18 0 Refer to the comment for size xamsbs 1 0 17 16 2 b00 Reserved 15 0 15 0 16 h0000 NREAD Response Transaction In the first clock cycle of the NREAD response on the Avalon ST pass through interface as shown in Figure 4 22 the IP core asserts gen tx ready to indicate it is ready to sample data In the same cycle u
169. entation 1 b0 The IP core cannot support 2 5 Gbaud operation 1 b1 The IP core can support 2 5 Gbaud operation This field can only have this value if 2 5 GB SUPPORT has the value of 1 Indicates whether the RapidlO II IP core supports port operation at 3 125 Gbaud 1 b0 The IP core does not support 3 125 Gbaud operation 1 b1 The IP core supports 3 125 Gbaud operation 1 b1 1 b1 3 125 GB ENABLE 20 RW Indicates whether port operation at 3 125 Gbaud is enabled in the RapidlO implementation 1 b0 The IP core cannot support 3 125 Gbaud operation 1 b1 The IP core can support 3 125 Gbaud operation This field can only have this value if 3 125 GB SUPPORT has the value of 1 1 b1 5 0 GB SUPPORT 19 RO Indicates whether the RapidlO II IP core supports port operation at 5 0 Gbaud 1 b0 The IP core does not support 5 0 Gbaud operation 1 b1 The IP core supports 5 0 Gbaud operation 1 b1 5 0 GB ENABLE 18 RW Indicates whether port operation at 5 0 Gbaud is enabled in the RapidlO implementation 1 b0 The IP core cannot support 5 0 Gbaud operation 1 b1 The IP core can support 5 0 Gbaud operation This field can only have this value if 5 0 GB SUPPORT has the value of 1 1 b1 6 25 GB SUPPORT 17 RO Indicates whether the RapidlO II IP core supports port operation at 6 25 Gbaud 1 b0 The IP core does not support 6 25 Gbaud operation 1 b1 The IP core supports 6
170. erations and returns data by calling the sister iom128 rd wr slave bfm write read data task This task drives the data and read datavalid control signals on the Avalon MM master read port of the sister rio module The returned data is expected at the DUT s I O Avalon MM slave interface The ios 128 rd wr master bfm read data task captures the read data The read data and the expected value are then compared to ensure that they are equal RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 7 Testbench Testbench Sequence NWRITE R Transactions To perform NWRITE R operations one register in the IP core must be reconfigured as shown in Table 7 3 Table 7 3 NWRITE R Transactions rio Register Address 0x1040C Name Value Description Sets the DESTINATION ID for outgoing transactions to the value 0x55 Or 0x5555 depending on the device ID width of the Or 32 hCDCD 0001 Sister rio This value matches the base device ID of the sister rio module Enables NWRITE R Operations Input Output Slave 32 h00CD 0001 Mapping Window 0 m Control With the setting in Table 7 3 any write operation presented across the Input Output Avalon MM slave module s Avalon MM write interface is translated to a RapidIO NWRITE R transaction The Avalon MM write address must map to the range specified for the I O Slave window 0 To initialize testing of the new NWRITE R completion indica
171. essage request segment packet received User logic must provide the correct capture information on the appropriate input signals when assserting the message request timeout set input port Refer to Table 5 14 on page 5 8 for the relevant capture signals Default 1 b0 PKT RSP TIMEOUT EN 24 RW Enable reporting of a packet response time out error Save and lock original request address in Logical Transport Layer Address Capture CSRs Save and lock original request destination ID in Logical Transport Layer Device ID Capture CSR User logic must provide the correct capture information on the appropriate input signals when assserting the slave packet response timeout set input port UNSOLICIT RSP EN 23 RW Enable reporting of an unsolicited response error 1 0 message or GSM logical for endpoints Maintenance for switches Save and lock transaction capture information in Logical Transport Layer Device ID and Control Capture CSRs User logic must provide the correct capture information on the appropriate input signals when assserting the unsolicited response set input port UNSUPPORT TRAN EN 22 RW Enable reporting of an unsupported transaction error Save and lock transaction capture information in Logical Transport Layer Device ID and Control Capture CSRs User logic must provide the correct capture information on the appropriate input signals when assserting the unsupported transaction set input
172. est time out occurs and PKT RSP TIMEOUT interrupt bit 24 of the Logical Transport Layer Error Detect CSR described in Table 6 67 on page 6 43 is generated if a response packet is not received within the time specified by the Port Response Time Out Control register Table 6 8 on page 6 8 m The IO ERROR RSP bit 31 of the Logical Transport Layer Error Detect CSR is set when an ERROR response is received for a transmitted MAINTENANCE packet For information about how the time out value is calculated refer to Table 6 8 on page 6 8 For more information about the error management registers refer to Table 6 67 on page 6 43 Doorbell Module The Doorbell module is an optional component of the I O Logical layer The Doorbell module provides support for Type 10 packet format DOORBELL class transactions allowing users to send and receive short software defined messages to and from other processing elements connected to the RapidIO interface February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 4 44 Chapter 4 Functional Description Logical Layer Interfaces Figure 4 3 on page 4 7 shows how the Doorbell module is connected to the Transport layer module In a typical application the Doorbell module s Avalon MM slave interface is connected to the system interconnect fabric allowing an Avalon MM master to communicate with RapidIO devices by sending and receiving DOORBELL messages When you configure the Rapi
173. et to a value 4 h0 larger than 8 the payload size is 8 double words 64 bytes RSRV 1 RO Reserved 1 bo Write 1 to start transmitting the port write request This bit is cleared internally after the packet has been transferred to PACRET BRADY 0 i the Transport layer to be forwarded to the Physical layer for LR transmission Table 6 46 Tx Port Write Status Offset 0x10204 Field Bits Access Function Default RSRV 31 0 RO Reserved 31 h0 Table 6 47 Tx Port Write Buffer n Offset 0x10210 0x1024C Field Bits Access Function Default Port write data This buffer is implemented in memory and is PORT WRITE DATA n 31 0 RW not initialized at reset 32 hx Receive Port Write Registers Table 6 48 through Table 6 50 describe the receive port write registers Refer to Port Write Reception Module on page 4 69 for information about receiving port write MAINTENANCE packets Table 6 48 Rx Port Write Control Offset 0x10250 Field Bits Access Function Default RSRV 31 2 RO Reserved 30 h0 CLEAR BUFFER 1 RW Clear port write buffer Write 1 to activate Always read 0 1 bo Port write enable If set to 1 port write packets are accepted POR 0 BN If set to 0 port write packets are dropped 2 RapidlO II MegaCore Function February 2013 Altera Corporation User Guide Chapter 6 Software Interface 6 37 Transport and
174. ets from a remote endpoint through the Transport layer module TheI O Avalon MM master module translates the request packets into Avalon MM transactions and creates and returns RapidIO response packets to the source of the request through the Transport layer Figure 4 4 shows a block diagram of the I O Avalon MM master Logical module and its interfaces 5 TheI O Avalon MM master module is referred to as a master module because it is an Avalon MM interface master February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 4 10 Chapter 4 Functional Description Logical Layer Interfaces The I O Avalon MM master module can process a mix of NREAD and NWRITE R requests simultaneously The I O Avalon MM master module can process up to eight pending NREAD requests If the Transport layer module receives an NREAD request packet while eight requests are already pending in the I O Avalon MM master module the new packet remains in the Transport layer until one of the pending transactions completes Figure 4 4 1 0 Master Block Diagram From Transport Layer 128 bis Sink Rx Datapath p gt Read and Write Read Avalon MM Interface and 128 bits Write Avalon MM Master 4 To Transport Layer 128 bits cuna Input Output Avalon MM Master Signals Table 4 5 lists the Input Output Avalon MM Master module interface signals Table 4 5 Input Output Av
175. etween Avalon MM transactions and RapidIO MAINTENANCE packets refer to Maintenance Interface Transaction Examples on page 4 38 Maintenance Interface Signals Table 4 13 lists the Maintenance Avalon MM interface slave port signals Table 4 13 Maintenance Avalon MM Slave Interface Signals Signal Direction Description mnt s waitrequest Output Maintenance slave wait request mnt s read Input Maintenance slave read request mnt s write Input Maintenance slave write request mnt s address 25 2 Input Maintenance slave address bus mnt s writedata 31 0 Input Maintenance slave write data bus mnt s readdata 31 0 Output Maintenance slave read data bus mnt s readdatavalid Output Maintenance slave read data valid Maintenance slave read error which indicates that the read transfer did mnt s readerror Output not complete successfully This signal is valid only when the mnt s readdatavalid signal is asserted The Maintenance module supports an interrupt line mnt mnt s on the Register Access interface When enabled the following interrupts assert the mot mnt s signal m Received port write m Various error conditions including a MAINTENANCE read request or MAINTENANCE write request that targets an out of bounds address For more information about the Maintenance module interrupts refer to Table 6 39 on page 6 34 and Table 6 40 on page 6 34 Table 4 14 lists the Mainte
176. evices Arria V SAGXFB3H4F3515 m Cyclone V 5SCGXFC7C6U19I7 RapidlO II MegaCore Function February 2013 Altera Corporation User Guide Chapter 1 About The RapidlO Il MegaCore Function 1 7 Device Speed Grades m Stratix V 5SGXEA7H3F35C3 Table 1 3 RapidlO Il IP Core FPGA Resource Utilization Parameters Registers Memory Variation Baud Rate Gbaud Primary Secondary tk or M20K 1 Minimal Full featured Aria V Full featured on Cyclone V 3 125 Full featured Minimal Stratix V 6 25 Note to Table 1 3 1 for Arria V and Cyclone V devices and M20K for Stratix V devices Device Speed Grades Table 1 4 shows the recommended device family speed grades for the supported link widths and internal clock frequencies Table 1 4 Recommended Device Family and Speed Grades 1 Rate 1 25 Ghaud s 3 125 Gbaud Ade Device Family fmax 31 25 MHz 62 50 MHz 78 125 MHz ig 156 25 MHz Arria V 4 5 6 4 5 6 4 5 6 4 5 4 5 Arria V GZ 3 4 3 4 3 4 3 4 3 4 Cyclone V 6 7 6 7 6 7 7 2 Stratix V 2 3 4 2 3 4 2 3 4 2 8 4 2 8 4 Notes to Table 1 4 1 In this table the entry n indicates that both the industrial speed grade In and the commercial speed grade Cn are supported for this device family and baud rate 2 Inthe Cyclone V devi
177. f the signals on the Avalon ST pass through interface for this example transaction sequence Figure 4 21 Avalon ST Pass Through Interface NREAD Request and Response Receive Example ok _ Lo f gen tx ready gen tx valid _ gen_tx_startofpacket c gen tx endofpacket o 1 1 gen 127 0 0052DDDDAAAA4CBB7654321000000000 gen tx empty 3 0 I 4 M gen tx packet size 8 0 I 00C S gen_rx_hd_ready J SSS gen_rx_hd_valid W WT ososDAAAADDDDS0BB000000000000 gen rx hd data 114 0 gen rx pd ready W gen x pd valid y L gen_rx_pd_startofpacket gen rx pd endofpacket m y 00112233445566778899AABBCCDDEEFF 0123456789ABCDEFFEDCBA9876543210 gen rx pd data 127 0 gen rx pd empty 2 0 0 The following two sections describe the behavior shown in Figure 4 21 m NREAD Request Transaction m NREAD Response Transaction RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 4 Functional Description Logical Layer Interfaces NREAD Request Transaction 4 55 In the first clock cycle of the example the IP core asserts gen tx ready to indicate it is ready to sample data In the same cycle user logic asserts gen tx valid Because both gen tx ready and gen tx valid asserted this clock cy
178. face you can abort the transmission of an errored packet by asserting the Avalon ST pass through interface gen_tx_error signal and gen_tx_endofpacket For more information about the Transport layer refer to Part 3 Common Transport Specification of the RapidIO Interconnect Specification Revision 2 2 Physical Layer This section describes features and interfaces of the serial Physical layer of the RapidIO II IP core Features The Physical layer has the following features m Port initialization m Transmitter and receiver with the following features One two or four lane high speed data serialization and deserialization Clock and data recovery receiver 8B10B encoding and decoding Lane synchronization receiver Packet control symbol assembly and delineation Packet cyclic redundancy code CRC CRC 16 generation and checking Control symbol CRC 13 generation and checking Error detection Pseudo random IDLE2 sequence generation IDLE2 sequence removal Scrambling and descrambling Software interface status control registers Flow control ackID tracking Time out on acknowledgements Order of retransmission maintenance and acknowledgements ackID assignment through software interface ackID synchronization after reset Error management m Clock decoupling RapidlO II MegaCore Function User Guide February 2013 Altera Corporation Chapter 4 Functional Description 4 63 Physical Layer m FIFO buffer with
179. fields are labeled in the register tables These fields are reserved for future use and your design should not write to nor rely on a specific value being found in any reserved field or bit The following sets of registers are accessible through the Maintenance Avalon MM slave interface m CARs Capability registers m CSRs Command and status registers m Extended features registers m Implementation defined registers A remote device can access these registers only by issuing read write MAINTENANCE operations destined for the local device The RapidIO II IP core routes read write MAINTENANCE requests that address the IP core registers internally The doorbell registers can be accessed through the Doorbell Avalon MM slave interface These registers are implemented only if you turn on Enable Doorbell support in the RapidIO II parameter editor Table 6 1 lists the access codes used tin the individual register descriptions to specify the type of register bits Table 6 1 Register Access Codes Part 1 of 2 Code Description RW Read write RO Read only RC Read to clear February 2013 Altera Corporation RapidlO II MegaCore Function User Guide 6 2 Memory Map Table 6 1 Register Access Codes Part 2 of 2 Chapter 6 Software Interface Memory Map RW1C Read Write 1 to clear Code Description URO Unused bits read as 0 Table 6 2 lists the RapidIO II IP core memory map overview Table 6 2
180. g For more information about how to use the RapidIO II IP core Avalon ST interface refer to the Avalon ST Pass Through Interface on page 4 48 For more information about the Avalon ST interface refer to Avalon Interface Specifications RapidlO Interface The RapidIO interface complies with revision 2 2 of the RapidIO serial interface standard described in the RapidIO Trade Association specifications The protocol is divided into a three layer hierarchy Physical layer Transport layer and Logical layer RapidlO II MegaCore Function User Guide February 2013 Altera Corporation Chapter 4 Functional Description 4 3 Clocking and Reset Structure More detailed information about the RapidIO interface specification is available from the RapidIO Trade Association website at www rapidio org Clocking and Reset Structure All RapidIO IP core variations have the following two clock inputs m Avalon system clock sys c1k m Reference clock for the transceiver Tx PLL tx 11 refclk The RapidIO II IP core provides the following two clock outputs from the transceiver m Recovered data clock rx clkout Transceiver transmit side clock tx clkout Avalon System Clock The Avalon system clock sys_clk is an input to the RapidIO core that drives the Transport and Logical layer modules and most of the Physical layer module Reference Clock The reference clock tx 11 refclk is the incoming reference clock for
181. gaCore Function User Guide February 2013 Altera Corporation Chapter 6 Software Interface 6 33 Transport and Logical Layer Registers Table 6 35 Local Configuration Space Base Address 1 CSR Offset 0x5C 1 Field Bits Access Function Default LCSBA 31 RO Reserved for a 34 bit local physical address 1 b0 LCSBA 30 0 RW Bits 33 4 of a 34 bit physical address 31 h0 Note to Table 6 35 1 This register holds the local physical address double word offset of the processing element s configuration register space If the Input Output Avalon MM master interface is connected to the Register Access Avalon MM slave interface then regular read and write operations rather than MAINTENANCE operations can be used to access the processing element s registers for configuration and maintenance based on this address User logic must write the correct offset value in this register to ensure that these read and write operations can work correctly Table 6 36 Base Device ID CSR Offset 0x60 Field Bits Access Function Default RSRV 31 24 RO Reserved 8 h0 This is the base ID of the device in a small common RW transport system The value of this field appears on the Base devicelD 23 16 base device id output signal 8 hFF RO Reserved if the system does not support 8 bit device ID This is the base ID of the device in a large common transport RW system This field value is valid only for
182. ges are COMPLETED 0 RW stored in the Tx Completion FIFO Otherwise these responses are 1 ho discarded Table 6 92 Doorbell Interrupt Enable Offset 0x20 Field Bits Access Function Default RSRV 31 3 RO Reserved 29 b0 TX CPL OVERFLOW 2 RW Tx Doorbell Completion Buffer Overflow Interrupt Enable 1 ho TX_CPL 1 RW Tx Doorbell Completion Interrupt Enable 1 ho RX 0 RW Doorbell Received Interrupt Enable 1 ho RapidlO II MegaCore Fun User Guide ction February 2013 Altera Corporation Chapter 6 Software Interface Transport and Logical Layer Registers Table 6 93 Doorbell Interrupt Status Offset 0x24 6 55 Field Bits Access Function Default RSRV 31 3 RO Reserved 29 h0 Interrupt asserted due to Tx Completion buffer overflow This bit remains set until at least one entry is read from the Tx TX CPL OVERFLOW 2 RW1C Completion FIFO After reading at least one entry software 1 ho should clear this bit It is not necessary to read all of the Tx Completion FIFO entries TX_CPL 1 RW1C Interrupt asserted due to Tx completion status 1 h0 RX 0 RW1C Interrupt asserted due to received messages 1 ho February 2013 Altera Corporation II MegaCore Function User Guide 6 56 Chapter 6 Software Interface Transport and Logical Layer Registers RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide RYN 1 Testbench T
183. h for one clock cycle when a CRC error is detected in a received packet control symbol error Pulsed high for one clock cycle when a corrupted control symbol is received port init ialized Indicates that the serial RapidlO initialization sequence has completed successfully This is a level signal asserted high while the initialization state machine is in the 7X MODE 2X MODE or 4X MODE state as described in paragraph 4 12 of the RapidlO Interconnect Specification v2 2 Part 6 LP Serial Physical Layer Specification This signal holds the inverse of the value of the PORT_UNINIT field of the Port 0 Error and Status CSR offset 0x158 described in Table 6 14 on page 6 12 port error This signal holds the value of the PORT ERR bit of the Port 0 Error and Status CSR offset 0x158 described in Table 6 14 on page 6 12 link init ialized Indicates that the RapidlO port successfully completed link initialization port ok This signal holds the value of the PoRT bit of the Port 0 Error and Status CSR offset 0x158 described in Table 6 14 on page 6 12 four lanes aligned Indicates that all four lanes of the 4x RapidlO port are in sync and aligned This signal is present only in variations that support four lanes two lanes aligned Indicates that the both lanes of the 2x RapidlO port are in sync and aligned This signal is present only in variations that support two lanes Low Laten
184. h of the instantiated Logical layer modules This set of assignments simplifies response routing but places a constraint on your design If you implement custom logic that communicates to the RapidIO II IP core through the Avalon ST pass through interface you must ensure your logic does not use a transaction ID assigned to another instantiated Logical layer module for transmitting request packets that expect an type 13 response packet If you use such a transaction ID the response will be routed away from the Avalon ST pass through interface and your custom module will never receive the response Table 4 23 shows the transaction ID ranges assigned to various Logical layers Table 4 23 Transaction ID Ranges and Assignments Range Assignments 0 63 This range of Transaction IDs is used for type 8 responses by the Maintenance Logical layer Avalon MM slave module 64 127 ftype 13 responses in this range are reserved for exclusive use by the Input Output Logical layer Avalon MM slave module 128 143 ftype 13 responses in this range are reserved for exclusive use by the Doorbell Logical layer module 144 255 This range of Transaction IDs is currently unused and is available for use by Logical layer modules connected to the pass through interface The RapidIO IP core Transport layer routes response packets of ftype 13 with transaction IDs outside the 64 143 range to the Avalon ST pass through interface Your system should
185. he Base Output pevice CSR Table 6 36 on page 6 33 This output reflects the value of the Large base devicerD field in the Base Device ID Table 6 36 on page 6 33 master enable Output large base device id 15 0 Output Logical and Transport Layer Signals This section shows you the signals used by the Transport layer and the Logical layer modules of the RapidIO IP core For a list of descriptions of the signals used and generated by the Physical layer see Physical Layer Signals on page 5 1 Avalon MM Interface Signals This section tells you where you can find information about the signals for the Avalon MM interfaces Signals on Avalon MM interfaces are in the Avalon system clock domain February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 5 6 Chapter 5 Signals Logical and Transport Layer Signals T Refer to the Avalon Interface Specifications for details Table 5 9 lists the location of the signal lists and descriptions for the Logical layer Avalon MM interfaces Table 5 9 Avalon MM Interface Signals Interface Register Access Location of Signal Table Refer to Table 4 4 on page 4 8 Input Output master Refer to Table 4 5 on page 4 10 Input Output slave Refer to Table 4 9 on page 4 20 Maintenance slave Refer to Table 4 13 on page 4 33 Maintenance master Refer to Table 4 14 on page 4 33
186. he PORT ERR bitis set software determines the behavior of the RapidlO II IP core as described in Fatal Errors on page 4 66 After it is set this bit is cleared only when software writes the value of 1 to it The port error output signal mirrors this register bit Input and output ports are initialized and can communicate with the PORT OK 1 RO adjacent device This bit is asserted when the link is initialized The value 1 bO in this field appears on the port ok output signal Input and output ports are not initialized and are in training mode This bit and the PoRT bit are mutually exclusive at any time at most one ner 1 b1 0 Be of them can be asserted The RapidlO II IP core deasserts this bit when b the port is initialized Note to Table 6 14 1 Refer to Error Detection and Management on page 4 65 for details February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 6 16 Chapter 6 Software Interface Physical Layer Registers Table 6 15 Port 0 Control CSR Offset 0x15C Part 1 of 4 Field Bits Access Function Default Together with the EXTENDED PORT WIDTH field indicates the hardware widths this port supports in addition to the 1x single lane width Bit 31 2x two lane support PORT WIDTH 31 30 RO 1 b0 This port does not support a 2x RapidlO link a 1 b1 This port supports a 2x RapidlO link Bit 30 4x four lane support 1 b0 This
187. he RapidIO II IP core includes a demonstration testbench for your use The purpose of the supplied testbench is to provide an example of how to parameterize the IP core and how to use the Avalon Memory Mapped Avalon MM and Avalon Streaming Avalon ST interfaces to generate and process RapidIO transactions The testbench demonstrates the following functions m Portinitialization process m Transmission reception and acknowledgment of packets with 8 to 256 bytes of data payload m Support for 8 bit or 16 bit device ID fields m Reading from the software interface registers m Transmission and reception of multicast event control symbols The testbench also demonstrates how to connect your RapidIO II IP core variation to an Altera Transceiver PHY Reset Controller IP core Testbench Overview The testbench generates and monitors transactions on the Avalon MM interfaces and Avalon ST interface MAINTENANCE Input Output or DOORBELL transactions are generated if you select the corresponding modules during parameterization of the IP core Type 9 Data Streaming packets are transferred through the Avalon ST pass through interface if present The testbench instantiates two symmetrical RapidIO II IP core variations each associated with an Altera Transceiver PHY Reset Controller IP core One instance is the Device Under Test DUT named rio inst The other instance acts as a RapidIO link partner for the RapidIO DUT module and is referred to as the
188. heck Destination ID 1 bi Disable Destination ID checking 1 LOG TRANS ERR _EN 6 RW Controls whether an interrupt is generated when the logical transport error input signal changes from the value of 0 to the value of 1 PORT FAIL IRQ EN 5 RW Controls whether an interrupt is generated when the port failed input signal changes from the value of 0 to the value of 1 PORT DEGR IRQ EN 4 RW Controls whether an interrupt is generated when the port degraded input signal changes from the value of 0 to the value of 1 RapidlO II MegaCore Function User Guide February 2013 Altera Corporation Chapter 6 Software Interface 6 19 Physical Layer Registers Table 6 15 Port 0 Control CSR Offset 0x15C Part 4 of 4 Field Bits Access Function Default Together with the DROP_PKT ENABLE field specifies the behavior of the port when the failed error threshold in the Port 0 Error Rate Threshold register offset 0 36 has been reached or exceeded The RapidlO II IP core supports the following valid values for STOP ON PRT FAIL ENCOUNTER ENABLE DROP PKT ENABLE 2 b00 The port continues to attempt to transmit packets to the RapidlO link partner 2 b01 The port discards packets that receive a packet not accepted response When the port discards a STOP ON PRT FAIL packet it sets the OUT PKT DROPD bitin the Port 0 Error and ENCOUNTER RNAB 119 R
189. hrough the Avalon ST pass through port February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 3 10 Chapter 3 Parameter Settings Command and Status Registers Settings The 32 bit default value of the Destination Operations CAR is determined by the functionality you enable in the RapidIO II IP core with other settings in the parameter editor For example if you turn on Enable Maintenance module the PORT WRITE field is set by default to the value of 1 b1 However the actual reset value of the Destination Operations CAR is the result of the bitwise exclusive or operation applied to the default values and the value you specify for the Destination operations CAR override parameter For example by default the Data Message field of this CAR is turned off However you can set the value of the Destination operations CAR override parameter to 32 h00000800 to override the default value of the Data Message field to indicate that user logic attached to the Avalon ST pass through interface supports data message operations that the RapidIO II IP core receives on the RapidIO link The RapidIO II IP core supports reporting of data message related errors through the standard Error Management Extensions registers Command and Status Registers Settings The Command and Status Registers tab lets you set the reset values for some of the command and status registers CSRs which exist in every RapidIO processing element All CSRs are
190. ic in setting bits 3 0 of the Msc 1NFo field in letter in 1 0 Input the Logical Transport Layer Control Capture CSR at offset 0x308 The two signal pairs write to distinct bits and can be mbox wr Input written simultaneously For information about the register fields mbox in 1 0 Input these signals can write refer to Table 6 71 on page 6 47 msgseg wr Input Support user logic in setting bits 7 4 of the the sc field in 3 0 Input inthe Logical Transport Layer Control Capture CSR at iat ah offset 0x308 For information about this register field refer to xmbox wr Input Table 6 71 on page 6 47 The two signal pairs write to the same register bits The value of xmbox in 3 0 Input xmbox s written to MSG_INFO 7 4 only when xmbox wr has the value of 1 b1 and msgseg wr has the value of 1 b0 Note to Table 5 14 1 To write to the register field for any of these signal pairs drive the value on the signal and then set the wr signal to the value of 1 b1 When the wr signal has the value of 1 b1 on the rising edge of sys_clk the value of the in signal is written directly to the register field 2 ensure the signals are captured as required by the Error Management Extensions block you must assert the wr signal for each of these signals at the same time you assert the relevant error setting signal from Table 5 13 Error Reporting Signals Table 5 15 lists the Er
191. icast event control symbol transmission and reception The RapidIO II IP core under test generates and transmits multicast event control symbols in response to transitions on its send multicast event input signal The sister module checks that these control symbols arrive as expected Disabled destination ID checking or not selected at configuration Indication of NWRITE R transactions that do not complete before the end of the test sequence Figure 7 1 RapidlO II IP Core Testbench Avalon MM sister sys mnt master bfm t Register Access Slave Doorbell Sister drbl master bfm Slave sister iom128 rd wr slave b fm JFL I O Master Sister rio A y o sister ios 128 rd wr master Slave Sister mnt master bfm Maintenance Slave Maintenance Master sister pt hdr bfm aa sister_pt_pld_bfm l Avalon ST Serial RapidlO Interface Register Access Slave Doorbell Avalon MM sys mnt master bfm drbl master bfm Slave VO Master Maintenance iom128_rd_wr_slave_bfm ios_128_rd_wr_master_bfm mnt_master_bfm Slave Maintenance Master tx_pt_src_bfm Avalon ST Figure 7 1 illustrates the system specified in Verilog HDL The testbench ge
192. ignals when assserting the long data streaming segment set input port Enable reporting of a non final data streaming segment with a payload size less than the MTU Save and lock capture information in the appropriate Logical Transport Layer SHRT DATA STRM SGMNT EN 18 RW Control Capture CSRs User logic must provide the correct 1 b0 capture information on the appropriate input signals when assserting the short data streaming segment set input port Enable reporting of a reassembled PDU that differs from the PDU length specified in the end data streaming segment packet header Save and lock capture information in the DS PDU LEN ERR EN 17 RW appropriate Logical Transport Layer Control Capture CSRs 1 b0 User logic must provide the correct capture information on the appropriate input signals when assserting the data streaming pdu length error set input port RSRV 16 8 RO Reserved 9 h0 Implementation Specific R error enable 7 0 The RapidlO II IP core does not support this feature 8 b0 Table 6 69 Logical Transport Layer Address Capture CSR Offset 0x314 Field Bits Access Function Default Least significant 29 bits of the RapidlO address associated with the error for requests for responses if available RSRV 2 RO Reserved 1 b0 Extended address bits of the address associated with the error for ADDRESS 31 3 RW 29 h0
193. in signals to control the timing of the value changes 2 The reset value is set in the RapidlO Il parameter editor Table 6 33 Processing Element Logical Layer Control CSR Offset 0x4C Field Bits Access Function Default RSRV 31 3 RO Reserved 29 h0 Controls the number of address bits generated by the Processing element as a Source and processed by the Processing element as the target of an operation 3 b100 Processing element supports 66 bit addresses EXT ADDR CTRL 2 0 RO 3 b010 Processing element supports 50 bit addresses 3 b001 7 3 b001 Processing element supports 34 bit addresses All other values are reserved The RapidlO II IP core supports only 34 bit addresses so the value of this field is always 3 b001 Table 6 34 Local Configuration Space Base Address 0 CSR Offset 0x58 1 Field Bits Access Function Default RSRV 31 RO Reserved 1 b0 LCSBA 30 15 RO Reserved for a 34 bit local physical address 16 h0 LCSBA 14 0 RO Reserved for a 34 bit local physical address 15 h0 Note to Table 6 34 1 The Local Configuration Space Base Address 0 register is hard coded to zero If the Input Output Avalon MM master interface is connected to the Register Access Avalon MM slave interface regular read and write operations rather than MAINTENANCE operations can be used to access the processing element s registers for configuration and maintenance RapidlO II Me
194. inbound DOORBELL messages If this parameter is turned off received DOORBELL messages are routed to the Avalon ST pass through interface if it is enabled or are silently dropped if the pass through interface is not enabled If the Doorbell module and the I O slave module are both enabled the Prevent doorbell messages from passing write transactions parameter is available This parameter controls support for preserving transaction order between DOORBELL messages and I O write request transactions sent to the IP core by user logic For more information about the Doorbell module refer to Doorbell Module on page 4 43 1 0 Master Configuration The I O Master module settings specify properties of the I O Logical layer Avalon MM Master module If you turn on Enable I O Logical layer Master module an I O Master module is configured in your RapidIO core If the I O Logical layer Master module is enabled the Number of Rx address translation windows parameter is available This parameter allows you to specify a value from 1 to 16 to define the number of receive address translation windows the I O Master Logical layer supports For more information about the I O Master receive address translation windows refer to Defining the Input Output Avalon MM Master Address Mapping Windows on page 4 11 RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 3 Parameter Settings 3 5 Capability Registers Sett
195. ing a Doorbell Message When the Doorbell module receives a DOORBELL request packet from the Transport layer module the module stores the request in an internal buffer and generates an interrupt on the DOORBELL Avalon MM slave interface asserts the drbell s irq signal if this interrupt is enabled The corresponding interrupt status bit is set every time a DOORBELL request packet is received and resets itself when the Rx FIFO is empty Software can clear the interrupt status bit by writing a 1 to this specific bit location of the Doorbell Interrupt Status register Table 6 93 The RapidIO core generates an interrupt when it receives a valid response packet and when it receives a request packet Therefore when user logic receives an interrupt the drbell s irqsignalis asserted you must check the Doorbell Interrupt Status register to determine the type of event that triggered the interrupt If the interrupt is not enabled user logic must periodically poll the Rx Doorbell Status register Table 6 85 to check the number of available messages before retrieving them from the Rx doorbell buffer The Doorbell module generates and sends appropriate Type 13 response packets for all the DOORBELL messages it receives The module generates a response with the following status depending on its ability to process the message m With DONE status if the received DOORBELL packet can be processed immediately m With RETRY status to defer pro
196. ings 1 0 Slave Configuration The I O Slave module settings specify properties of the I O Logical layer Avalon MM Slave module If you turn on Enable I O Logical layer Slave module an I O Slave module is configured in your RapidIO II IP core Turning on this parameter makes the following I O Slave module parameters available in the parameter editor m Number of Tx address translation windows allows you to specify a value from 1 to 16 to define the number of transmit address translation windows the I O Slave Logical layer supports For more information about the I O Slave transmit address translation windows refer to Defining the Input Output Avalon MM Slave Address Mapping Windows on page 4 22 m I O Slave address bus width currently supports widths between 10 and 32 bits inclusive Capability Registers Settings The Capability Registers tab lets you set values for some of the capability registers CARs which exist in every RapidIO processing element and allow an external processing element to determine the endpoint s capabilities through MAINTENANCE read operations All CARs are 32 bits wide The settings on the Capability Registers page do not cause any features to be enabled or disabled in the RapidIO II IP core Instead they set the values of certain bit fields in some CARs Device Identity CAR The Device Identity CAR options identify the device and vendor IDs and set values in the Device Identity Table 6 22 on page
197. ion Default Processing element physically contains a local PR 29 RO processor or similar device that executes code A i TUE device that bridges to an interface that connects to a processor does not count Processing element can bridge to another external Switch 28 RO RapidlO interface an internal port to a local 1 endpoint does not count as a switch port Processing element implements multiple external RapidlO ports MULTIPORT 27 RO The RapidlO II IP core implements only a single 1 hO RapidlO port so this field always has the value of 1 b0 RSRV 26 12 RO Reserved 25 h0 Plow APER 11 RO Processing element supports flow arbitration 1 Support RSRV 10 RO Reserved 1 h0 Processing element supports extended route table Extended route configuration mechanism table configuration 9 RO This property is relevant in switch processing i support 2 elements only In non switch processing elements itis ignored Processing element supports standard route table Standard route configuration mechanism table configuration 8 RO This property is relevant in switch processing m support elements only In non switch processing elements itis ignored Flow Control 7 RO Processing element supports flow control i Support extensions RSRV 6 RO Reserved 1 h0 Processing element supports the Critical Request Flow CRF indicator CRF Support 5 RO 1 b0 Processing element does not support t bi February 2013 Altera Corporation R
198. ion directory variation sim mentor 3 Type the following commands to set up the required libraries compile the generated simulation model and exercise the simulation model with the provided testbench do msim setup tcl set TOP LEVEL NAME variation tb rio 1d run all February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 2 4 Simulating with the VCS Simulator Chapter 2 Getting Started Qsys Design Flow To simulate using the Synopsys VCS simulator type the following commands cd variation sim synopsys vcs sh vcs setup sh TOP LEVEL NAME tb rio simv For Information About Quartus software MegaWizard Plug In Manager Refer To See the Quartus II Help topics About the Quartus II Software About the MegaWizard Plug In Manager A complete list of models or libraries required to simulate the RapidlO 11 IP core variation name run modelsim tcl script provided with the demonstration testbench in Chapter 7 Testbench Altera simulation models Simulating Altera Designs chapter in volume 3 of the Quartus II Handbook sys Design Flow You can use Qsys to build a system that contains your customized RapidIO II IP core You can easily add other components and quickly create a Qsys system can automatically generate HDL files that include all of the specified components and interconnections The HDL files are ready to be compiled by the Quartus II s
199. is sys mnt master bfm orsys mnt master bfm read write cmdor read data tasks Transactions Across the Avalon ST Pass Through Interface The demonstration testbench tests the Avalon ST pass through interface by exchanging Type 9 Data Streaming traffic between the DUT and the sister rio module Testbench Completion The testbench concludes by checking that all of the packets have been received If no error is detected and all packets are received the testbench issues a TESTBENCH PASSED message stating that the simulation was successful If an error is detected a TESTBENCH FAILED message is issued to indicate that the testbench has failed A TESTBENCH INCOMPLETE message is issued if the expected number of checks is not made For example this message is issued if not all packets are received before the testbench is terminated The variable tb rio exp chk cnt determines the number of checks done to ensure completeness of the testbench To generate a value change dump file called dump vcd for all viewable signals uncomment the line dumpvars 0 tb rio inthe tb rio sv file RapidlO II MegaCore Function February 2013 Altera Corporation User Guide N DTE RYN Initialization Sequence This appendix describes the most basic initialization sequence for a RapidIO system that contains two RapidIO IP cores connected through their RapidIO interfaces To initialize the system perform these steps 1 Read the Port 0 Error and St
200. ived packet with unexpected ackID enable 19 RW Received packet with bad CRC enable 18 RW Received packet exceeding max Size enable 17 RW Received illegal or invalid character enable 16 RW Enable error rate counting of corresponding error 1 0 1 0 Received data character in IDLE1 sequence enable 15 RW Reserved for this implementation The RapidlO II IP core does not support the IDLE1 sequence 1 hd Loss of descrambler synchronization enable 14 RW Enable error rate counting of corresponding error RSRV 13 6 RO Reserved February 2013 Altera Corporation RapidlO II MegaCore Function User Guide 6 50 Chapter 6 Software Interface Transport and Logical Layer Registers Table 6 75 Port 0 Error Rate Enable CSR Offset 0x344 Part 2 of 2 Field Bits Access Function Default Non outstanding i ackID enable 5 RW 108 Enable error rate counting of corresponding error rotocol error 1 nable 4 RW 1 h0 RSRV 3 RO Reserved for this implementation 1 h0 Delineation error i eis 2 RW 1 h0 Unsolicited ACK control symbol 1 RW Enable error rate counting of corresponding error 1 h0 enable Link timeout i ze 0 RW 1 h0 Table 6 76 Port 0 Attributes Capture CSR Offset 0x348 Field Bits Access Func
201. l the current transaction is completed You can determine the combined fill level of the staging FIFO and the Tx FIFO by reading the Tx Doorbell Status register Table 6 88 The total number of Doorbell messages stored in the staging FIFO and the Tx FIFO together is limited to 16 by the assertion of the drbell s waitrequest signal After a write to the Tx Doorbell register is detected internal control logic generates and sends a Type 10 packet based on the information in the Tx Doorbell and Tx Doorbell Control registers A copy of the outbound DOORBELL packet is stored in the Acknowledge RAM When the response to an outbound DOORBELL message is received the corresponding copy of the outbound message is written to the Tx Doorbell Completion FIFO if enabled and an interrupt is generated if enabled on the Avalon MM slave interface by asserting the drbell s irqgsignal of the Doorbell module The ERROR CODE field in the Tx Doorbell Completion Status register Table 6 90 indicates successful or error completion RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 4 Functional Description 4 41 Logical Layer Interfaces The corresponding interrupt status bit is set each time a valid response packet is received and resets itself when the Tx Completion FIFO is empty Software optionally can clear the interrupt status bit by writing a 1 to this specific bit location of the Doorbell Interrupt Status register Ta
202. ld Bits Access Function Default FTYPE 0 31 28 RO Format type associated with the error 410 TTYPE 2 27 24 RO Transaction type associated with the error 410 Letter mbox and msgseg for the last message request received 3 MSG_INFO 23 16 RO for the mailbox that had an error eng iiag Reserved for this implementation 16 h0 Specific Votes to Table 6 71 1 For errors the RapidlO II IP core does not detect internally set this field using the capture ftype wrand capture ftype in input signals 2 For errors the RapidlO II IP core does not detect internally set this field using the capture ttype wrand capture ttype input signals 3 For errors the RapidlO II IP core does not detect internally set this field using the letter wr mbox wr msgseg wr and xmbox wr and letter in mbox in msgseg and xmbox in input signals Table 6 72 Port Write Target Device ID CSR Offset 0x328 Field Bits Access Function Default RO Reserved if the system does not support 16 bit device ID deviceID MSB 31 24 RW MSB of the Maintenance port write target device ID to report 8 hO errors to a system host if the system supports 16 bit device ID deviceID 23 16 RW Port write target device ID 8 h0 Specifies the correct device ID size for a Maintenance port write transaction to report errors to a system host TARGE TRANSPORT 15 i 1 b0 Use the small transport device ID TOR 1
203. le configuration support bit or the Extended route table configuration support bit is set user logic must implement the functionality and registers to support the standard or extended route table configuration The RapidlO II IP core does not implement the Standard Route CSRs at offsets 0x70 0x74 and 0x78 Table 6 27 Switch Port Information CAR Offset 0x14 Field Bits Access RSRV 31 16 RO Function Reserved Default 16 h0 PortTotal 15 8 RO The maximum number of RapidlO ports on the processing element 8 hO Reserved 8 h1 1 port 8 h2 2 ports 8 hFF 255 ports PortNumber 7 0 RO 8 h0 This is the port number from which the MAINTENANCE read operation accessed this register Ports are numbered starting with 1 Note to Table 6 27 1 The value is set in the RapidlO Il parameter editor 2 Ifthe Switch Port Information CAR is accessible from multiple ports user logic must implement shadowing of the PortNumber field RapidlO II MegaCore Function User Guide February 2013 Altera Corporation Chapter 6 Software Interface 6 29 Transport and Logical Layer Registers Table 6 28 Source Operations CAR Offset 0x18 1 2 Field Bits Access Function Default RSRV 31 20 RO Reserved 12 h0 DATA STRM TRAFFIC 19 RO Processing element can support data streaming traffic 10 _ MANAGEMENT management DATA STR
204. lon MM Pass Through A A A A A A Y v v v v MIS RD WR RD WR S Registers Maintenance I O Master I O Slave Doorbell A A Error Management Extension Block Logical Layer v v v Sink SR Transport layer 1 Physical layer V RapidlO Link Register Access Interface All RapidIO IP core variations include a Register Access interface This Avalon MM slave interface provides access to all of the registers in the RapidIO II IP core except the Doorbell Logical layer registers The Doorbell Logical layer registers are available only in RapidIO core variations that instantiate a Doorbell Logical layer module and you must access them through the Doorbell module s Avalon MM slave interface Non Doorbell Register Access Operations The RapidIO II IP core registers are 32 bits wide and are accessible only on a 32 bit 4 byte basis The addressing for the registers therefore increments by units of 4 The Register Access interface supports simple reads and writes with variable latency The interface provides access to 32 bit words addressed by a 22 bit wide word address corresponding to a 24 bit wide byte address This address space provides access to the entire RapidIO configuration space including any user defined registers A local host can access the RapidIO IP core registers through the Register Access Avalon MM slave interface Feb
205. lue in the PWIDTH OVRIDE Or EXTENDED PWIDTH OVRIDE field changes the port re initializes using the new field values RapidlO II MegaCore Function February 2013 Altera Corporation User Guide Chapter 6 Software Interface Physical Layer Registers Table 6 15 Port 0 Control CSR Offset 0x15C Part 2 of 4 6 17 Field PORT DIS Bits 23 Access RW Function Port disable b0 Port receivers drivers are enabled b1 Port receivers are disabled and are unable to receive or transmit any packets or control symbols While this bit is set the initialization state machines force reinit signal is asserted This assertion forces the port to the S LENT state Default OUT PENA 22 RW Output port transmit enable b0 Port is stopped and not enabled to issue any packets except to route or respond to 1 0 logical MAINTENANCE packets Control symbols are not affected and are sent normally b1 Port is enabled to issue packets The value in the PORT field bit 1 of this register can override the values in the oUT PENA and IN PENA fields 1 b0 IN PENA 21 RW Input port receive enable b0 Port is stopped and only enabled to respond to 1 0 Logical MAINTENANCE requests Other requests return packet not accepted control symbols to force an error condition to be signaled by the sending device However the IP core still handles normall
206. lue of 1 Indicates which Idle control symbol is active 1 b0 IP core uses IDLE1 control symbols IDLE SEQUENCE 29 RO 1 b1 IP core uses IDLE2 control symbols 101 The RapidlO II IP core currently supports only the IDLE2 sequence so this bit always has the value of 1 RapidlO II MegaCore Function User Guide February 2013 Altera Corporation Chapter 6 Software Interface Physical Layer Registers Table 6 14 Port 0 Error and Status CSR Offset 0 158 1 Part 2 of 4 6 13 Field RSRV Bits 28 Access RO Function Reserved Default 1 b0 FLOW CTRL MODE 27 RO Indicates which flow control mode is active 1 b0 Receiver controlled flow control is active 1 b1 Transmitter controlled flow control is active 1 b0 OUT PKT DROPD 26 RW1C Output port has discarded a packet because the failed error threshold in the Port 0 Error Rate Threshold register has been reached After it is set this bit is cleared only when software writes the value of 1 to it 1 b0 OUT FAIL 25 RW1C Output port has encountered a failed condition the failed error threshold in the Port 0 Error Rate Threshold register Table 6 82 on page 6 52 has been reached After it is set this bit is cleared only when software writes the value of 1 to it OUT DGRD ENC RSRV 24 23 21 RW1C RO Output port has encountered a degraded condition the d
207. lways has the value of 0 Controls whether automatic baud rate discovery is enabled in the RapidlO implementation The RapidlO II IP core does not support 1 0 automatic baud rate discovery so this field always has the value of 0 BD RT DISCOVERY RT_DISCOVERY_ TR ENABLE Indicates whether the RapidlO II IP core supports port operation at 1 25 Gbaud 1 25 GB BUPPORT MES RO 1 b0 The IP core does not support 1 25 Gbaud operation UM 1 b1 The IP core supports 1 25 Gbaud operation Indicates whether port operation at 1 25 Gbaud is enabled in the RapidlO implementation 1 25 GB ENABLE 24 RW 1 b0 The IP core cannot support 1 25 Gbaud operation 1 b1 1 b1 The IP core can support 1 25 Gbaud operation This field can only have this value if 1 25 GB SUPPORT has the value of 1 RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 6 Software Interface Physical Layer Registers Table 6 13 Port 0 Control 2 CSR Offset 0x154 Part 2 of 3 6 11 Field 2 5 GB SUPPORT Bits 23 Access RO Function Indicates whether the RapidlO II IP core supports port operation at 2 5 Gbaud 1 b0 The IP core does not support 2 5 Gbaud operation 1 b1 The IP core supports 2 5 Gbaud operation Default 1 b1 2 5 GB ENABLE 3 125 GB SUPPORT 22 21 RW RO Indicates whether port operation at 2 5 Gbaud is enabled in the RapidlO implem
208. mands and anything that must be typed exactly as it appears For example c qdesigns tutorial chiptrip gdf Also indicates sections of an actual file such as a Report File references to parts of files for example the AHDL keyword SUBDESIGN and logic function names for example TRI An angled arrow instructs you to press the Enter key Numbered steps indicate a list of items when the sequence of the items is important such as the steps listed in a procedure Bullets indicate a list of items when the sequence of the items is not important e The hand points to information that requires special attention The question mark directs you to a software help system with related information ur The feet direct you to another document or website with related information The multimedia icon directs you to a related multimedia presentation CAUTION A caution calls attention to a condition or possible situation that can damage or destroy the product or your work WARNING A warning calls attention to a condition or possible situation that can cause you injury The envelope links to the Email Subscription Management Center page of the Altera website where you can sign up to receive update notifications for Altera documents The feedback icon allows you to submit feedback to Altera about the document Methods for collecting feedback vary as appropriate for each document RapidlO II MegaCore
209. me information in the Error Management Extension registers February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 4 22 Chapter 4 Functional Description Logical Layer Interfaces The RapidIO II IP core assigns a time out value to each outbound request that requires a response each NWRITE R or NREAD transaction The time out value is the sum of the VALUE field of the Port Response Time Out Control register Table 6 8 on page 6 8 and the current value of a free running counter When the counter reaches the time out value if the transaction has not yet received a response the transaction times out Refer to Table 6 8 for information about the duration of the time out Tracking 1 0 Write Transactions The following three registers are available to software to track the status of I O write transactions m The Input Output Slave Avalon MM Write Transactions register described in Table 6 63 on page 6 41 holds a count of the write transactions that have been initiated on the write Avalon MM slave interface m TheInput Output Slave RapidIO Write Requests register described in Table 6 64 on page 6 41 holds a count of the RapidIO write request packets that have been transferred to the Transport layer m TheInput Output Slave Pending NWRITE R Transactions register described in Table 6 62 on page 6 41 holds a count of the NWRITE R requests that have been issued but have not yet completed You can use these registe
210. ments a reset sequence that resets the device transceivers correctly The default parameter settings of the Transceiver PHY Reset Controller IP core are compatible with the RapidIO II IP core requirements For more information refer to Reset for RapidIO II IP Cores on page 4 4 St For information about the Altera Transceiver Reconfiguration Controller and about the Altera Transceiver PHY Reset Controller IP core refer to the Altera Transceiver PHY IP Core User Guide 4 If you intend to simulate your Qsys system on the Generation tab turn on Create simulation model and select Verilog HDL or VHDL to generate a functional simulation model 5 Click Generate to generate the system Osys generates the system and produces the lt system_name gt qip file that contains the assignments and information required to process the IP core or system in the Quartus II Compiler 6 In the Quartus II software on the Project menu click Add Remove Files in Project 7 In the Settings dialog box under Category highlight Files 8 Browse to the qip file and add it to your project RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 2 Getting Started 2 1 Adding Transceiver Analog Settings a Altera recommends that you maintain the default Native PHY IP core settings generated for the RapidIO II IP core If you edit the existing Native PHY IP core in the MegaWizard Plug In Manager the regenerated Native PHY IP co
211. messages until they are read by an external Avalon MM master device m Tx FIFO that stores DOORBELL messages that are waiting to be transmitted m Tx staging FIFO that stores DOORBELL messages until they can be passed to the Tx FIFO The staging FIFO is present only if you select Prevent doorbell messages from passing write transactions in the RapidIO II parameter editor m Txcompletion FIFO that stores the transmitted DOORBELL messages that have received responses This FIFO also stores timed out Tx DOORBELL requests RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 4 Functional Description 4 45 Logical Layer Interfaces m Error Management module that reports detected errors including the following errors m Unexpected response a response packet was received but its TransactionID does not match any pending request that is waiting for a response m Request time out an outbound DOORBELL request did not receive a response from the target device Figure 4 20 Doorbell Module Block Diagram To Register Module From I O Slave Module Doorbell Logical Modu Error Management From Transport Layer To Transport Layer Module lt Source c Sink H gt Rx Control FIFO Module Register and FIFO Interface Avalon MM 4t System Slave Interconnect m T Ted Fabric cknowledge Tx Completion p
212. nalogreset tx digitalreset reset the transmit side of the transceiver rx ready rx analogreset rx digitalreset reset the receive side of the transceiver pll powerdown reset one or more Tx PLLs in the transceiver The reset sequence and requirements vary among device families To implement the reset sequence correctly for your RapidIO II IP core you must connect the tx ready tx analogreset tx digitalreset rx ready rx analogreset rx digitalreset and pll powerdown reset signals to an Altera Transceiver PHY Reset Controller IP core User logic must drive the RapidIO IL IP core rst n active low input signal and the Transceiver PHY Reset Controller IP core reset active high input signal from a single reset source and connect the remaining input reset signals of the RapidIO II IP core to the corresponding output signals of the Transceiver PHY Reset Controller IP core RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 4 Functional Description 4 5 Clocking and Reset Structure T For information about the Altera Transceiver PHY Reset Controller IP core refer to the Altera Transceiver PHY IP Core User Guide For details about the requirements for the reset sequence for each device refer to the relevant device handbook The rst ninput signal can be asserted asynchronously but must last at least one Avalon system clock period and be deasserted synchronously to the rising edge of the Avalon
213. nance Avalon MM interface master port signals Table 4 14 Maintenance Avalon MM Master Interface Signals Part 1 of 2 Signal Direction Description usr mnt waitrequest Input Maintenance master wait request usr mnt read Output Maintenance master read request February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 4 34 Chapter 4 Functional Description Logical Layer Interfaces Table 4 14 Maintenance Avalon MM Master Interface Signals Part 2 of 2 Signal Direction Description usr mnt write Output Maintenance master write request usr mnt address 31 0 Output Maintenance master address bus usr mnt writedata 31 0 Output Maintenance master write data bus usr mnt readdata 31 0 Input Maintenance master read data bus usr mnt readdatavalid Input Maintenance master read data valid Initiating MAINTENANCE Read and Write Transactions To initiate a MAINTENANCE read or write transaction on the RapidIO link your system executes a read or write transfer on the Maintenance Avalon MM slave interface Refer to Maintenance Interface Transaction Examples on page 4 38 for examples of how the RapidIO II IP core converts Avalon MM requests to RapidIO MAINTENANCE request packets IP Core Actions In response to incoming Avalon MM requests to the Maintenance module slave interface the RapidIO II IP core Maintenance module generates MAINTENANCE requests on the RapidIO link
214. ncluding the target device s destination ID the request packet s priority and to select between the three available write request packet types NWRITE NWRITE and SWRITE Figure 4 9 on page 4 24 illustrates the address mapping RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 4 Functional Description 4 23 Logical Layer Interfaces You can change the values of the window defining registers at any time even after sending a request packet and before receiving its response packet However you should disable a window before changing its window defining registers To enable a window set the window enable WEN bit of the window s Input Output Slave Mapping Window Mask register Table 6 57 on page 6 39 to the value of 1 To disable it set the WEN bit to the value of zero For each defined and enabled window the RapidIO II IP core masks out the RapidIO address s least significant bits with the window mask and compares the resulting address to the window base The matching window is the lowest numbered window n for which the following equation holds ios rd wr addr 31 4 amp mask 31 4 base 31 4 amp mask 31 4 where m ios rd wr addr 31 0 is the I O Logical layer Avalon MM slave address bus If the field has fewer than 32 bits the IP core pads the actual bus value with leading zeroes for the matching comparison mask 31 4 is the MASK field of the Input Output Slave Mappi
215. nction Default IO ERROR RSP EN 31 RW Enable reporting of the relevant 1 0 error response Save and 1 b0 MSG ERROR RESPONSE EN 30 RW lock original request transaction information in all 1650 Logical Transport Layer Capture CSRs User logic must provide the correct capture information on the appropriate GSM ERROR RESPONSE EN 29 RW input signals when assserting the 10 T message error response set OF gsm error response set input port MSG FORMAT ERROR EN 28 RW Enable reporting of the relevant error Save and lock received 1 bO ILL TRAN DECODE EN 27 RW transaction capture information in Logical Transport Layer 1650 Device ID and Control Capture CSRs User logic must provide the correct capture information on the appropriate input signals when assserting the ILL TRAN_TARGET_EN 26 RW message format error response set 100 illegal transaction decode set Or illegal transaction target error set input port RapidlO II MegaCore Function User Guide February 2013 Altera Corporation Chapter 6 Software Interface Transport and Logical Layer Registers Table 6 68 Logical Transport Layer Error Enable CSR Offset 0x30C Part 2 of 3 6 45 Field MSG REQ TIMEOUT EN Bits 25 Access RW Function Enable reporting of a Message Request time out error Save and lock original request transaction information in Logical Transport Layer Device ID and Control Capture CSRs for the last M
216. ne n Status O Offset 0x210 0x230 0x250 0x270 Part 2 of 2 Field Bits Access Function Default If the lane receiver controls any transmit or receive adaptive equalization this bit indicates whether all of the adaptive equalizers that this lane controls are now trained The value of this field is the value in Receiver the Receiver trained bit in the CS field the lane transmits Trained 14 RO 1 b0 The lane receiver controls one or more adaptive equalizers and nbd at least one of these adaptive equalizers is not trained 1 b1 The lane receiver controls no adaptive equalizers or all of the adaptive equalizers it controls are trained Indicates the state of the lane n lane_sync signal Lane i43 RO l b0 lane_sync is FALSE 10 101 lane_sync is TRUE Indicates the state of the lane 1ane ready signal Lane 149 RO 100 Lane ready is FALSE 10 101 lane_ready is TRUE Number of 8B10B decoding errors detected on this lane since this 8B10B DEC ERR 11 8 RC register bit was last read The value saturates at OxF it does not roll 4 h0 over Reading the register resets this field to the value of 0 Indicates the state of the lane sync signal for this lane has changed Lane sync 7 RC since this bit was last read Reading the register resets this bit to the 1 b0 State Change value of 1 b0 This bit provides an indication of the burstiness of the transmission errors that the lane receiver detected Indicates the state of the rcvr_traine
217. nerates and checks activity across the Avalon MM interfaces by running tasks that are defined in the BFMs RapidlO II MegaCore Function User Guide February 2013 Altera Corporation Chapter 7 Testbench Testbench Sequence The file tb rio v implements the code that performs the test transactions The code performs a reset and initialization sequence necessary for the DUT and sister rio IP cores to establish a link and exchange packets Testbench Sequence The RapidIO II IP core testbench resets the DUT and the sister rio module and initiates a sequence of transactions on each Avalon MM and Avalon ST interface that is relevant to this RapidIO II IP core variation The following sections describe the reset and transaction sequences Reset Initialization and Configuration The clocks that drive the testbench are defined and generated in the tb rio sv file Refer to tb rio sv for the exact frequencies used for each of the clocks The frequencies depend on the configuration of the variation The reset sequence is simple the main reset signal for the DUT and the sister rio IP core rst n is driven low at the beginning of the simulation is kept low for 200 ns and is then deasserted The testbench also includes two Altera Transceiver PHY Reset Controller IP cores connected to the DUT and sister IP core While rst nis asserted the reset input signal to the Transceiver PHY Reset Controller IP core is also asserted After rst nis d
218. ng Window Mask register base 31 4 is the BASE field of the Input Output Slave Mapping Window Base register The RapidIO II IP core determines the value for the RapidIO packet header xamsbs and address fields from the least significant bits of the Avalon MM ios rd wr address signal and the matching window offset using the following equation rio addr 33 4 xamo offset 31 4 amp mask 31 4 ios rd wr address 31 4 where rio addr 33 0 is the 34 bit RapidIO address composed of xamsbs 1 0 address 28 0 3b 000 for RapidIO header fields xamsbs and address xamo 1 0 is the field of the Input Output Slave Mapping Window Offset register offset 31 4 is the OFFSET field of the Input Output Slave Mapping Window Offset register m The definitions of all other terms in the equation appear in the definition of the matching window If the address does not match any window the I O Logical layer Slave module performs the following actions m Setsthe WRITE OUT OF BOUNDS or READ OUT OF BOUNDS interrupt bit in the Input Output Slave Interrupt register Table 6 60 on page 6 40 Asserts the interrupt signal io s mnt irgifthis interrupt is enabled by the corresponding bit in the Input Output Slave Interrupt Enable register Table 6 61 on page 6 40 February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 4 24 Chapter 4 Functional Description Logical Layer
219. ng the clock cycle when gen_tx_endofpacket is asserted This signal is 4 bits wide 1 Note to Table 4 25 1 gen rx pd valid qualifies all the other output signals of the transmit side of the Avalon ST pass through interface RapidlO II MegaCore Function User Guide February 2013 Altera Corporation Chapter 4 Functional Description 4 51 Logical Layer Interfaces Pass Through Interface Receive Side Header Signals Table 4 26 lists the Avalon ST pass through interface receive side header signals The application should sample header data only when both gen_rx_hd_ready and gen_rx_hd_validare asserted Table 4 26 Avalon ST Pass Through Interface Receive Side Avalon ST Source Header Signals Signal Name Type Function Indicates to the IP core that the user s custom logic is ready to receive packet header bits on the current clock cycle Asserted by the sink to mark ready cycles gen rx hd ready Input which are cycles in which transfers can occur If ready is asserted on cycle the cycle N READY LATENCY is a ready cycle The RapidlO II IP core is designed for READY LATENCY equal to 0 Used to qualify the receive side pass through interface output header bus On gen rx hd valid Output every rising edge of the clock during which gen rx hd validis high gen rx hd data can be sampled A 115 bit wide bus for packet header bits Data on this bus is valid only when gen rx hd data 114 0 Output gen rx hd validis
220. not use transaction IDs in the 0 63 range if the Maintenance Logical layer Avalon MM slave module is instantiated because their use might cause the uniqueness of transaction ID rule to be violated RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 4 Functional Description 4 49 Logical Layer Interfaces If the Input Output Avalon MM slave module or the Doorbell Logical layer module is not instantiated the RapidIO II IP core Transport layer routes the response packets in the corresponding Transaction IDs ranges for these layers to the Avalon ST pass through interface Pass Through Interface Signals The Avalon ST pass through interface includes the following ports m Transmit interface this sink interface accepts incoming streaming data that the IP core sends to the RapidIO link m Receive data interface this source interface streams out the payload of packets the IP core receives from the RapidIO link m Receive header interface this source interface streams out packet header information the IP core receives from the RapidIO link Pass Through Transmit Side Signals Table 4 24 lists the Avalon ST pass through interface transmit side signals These signals receive incoming streaming data from user logic the IP core transmits this data on the RapidIO link The RapidIO II IP core samples data on this interface only when both gen tx ready and gen tx valid asserted The incoming streaming data
221. nslation window n Refer to Defining the Maintenance Address Translation Windows on page 4 34 for details tt 1 0 2 b00 The value of 0 indicates 8 bit device IDs ftype 3 0 4 b1000 The value of 8 indicates a Maintenance Class packet The IP core assigns to this field the value programmed in the DESTINATION ID field of the Tx Maintenance Mapping Window n Control register destinationID 7 0 Table 6 44 on page 6 35 for the matching address translation window n Refer to Defining the Maintenance Address Translation Windows on page 4 34 for matching details 35 9 The IP core assigns to this field the value programmed in the Base deviceID field of the Base Device ID register offset 0 60 ttype 3 0 4 b0001 The value of 1 indicates a MAINTENANCE write request The size and wdptr values encode the maximum size of the payload field In MAINTENANCE transactions the value of wrsize is always 4 b1000 which wrsize 3 0 4 b1000 decodes to a value of 4 bytes For encoding details refer to Table 4 4 in Part 1 Input Output Logical Specification of the RapidlO Interconnect Specification Revision 2 2 SrcTID 7 0 The RapidlO II IP core generates the source transaction ID value internally to track the transaction response The value depends on the current state of the RapidlO II IP core when it prepares the RapidlO packet config offset 20 0 Depends on the value on the mnt s address bus and the values programmed inth
222. nt Extensions block and registers This section describes the error detection and management features in the RapidIO II IP core Physical Layer Error Management Most errors at the Physical layer are in one of the following two categories m Protocol violations m Transmission errors Protocol violations can be caused by a link partner that is not fully compliant to the specification or can be a side effect of the link partner being reset Transmission errors can be caused by noise on the line and consist of one or more bit errors The following mechanisms exist for checking and detecting errors m Thereceiver checks the validity of the received 8B10B encoded characters including the running disparity m The receiver detects control characters changed into data characters or data characters changed into control characters based on the context in which the character is received m Thereceiver checks the CRC of the received control symbols and packets February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 4 66 Chapter 4 Functional Description Error Detection and Management The RapidIO II IP core Physical layer transparently manages these errors for you The RapidlO specification defines both input and output error detection and recovery state machines that include handshaking protocols in which the receiving end signals that an error is detected by sending a packet not accepted control symbol the transmitter
223. nt clock cycle are valid The initial eight bytes of the NREAD response packet contain header information Table 4 35 lists the header fields and their values in this example Table 4 35 NREAD Response Transmit Example RapidlO Header Fields on the gen tx data Bus gen tx data Field Bits Value Comment Value is a don t care because it is overwritten by the Physical ackID 127 122 6 h00 layer ackID value before the packet is transmitted on the RapidlO link vc 121 0 The RapidlO II IP core supports only VCO CRF 120 0 Priority of the response packet Value must be higher than the priority value of the request packet In this example the 1 1 0 2010 response packet has a priority value of 2 b10 and the original request has a priority value of 2 b01 tt 1 0 117 116 2 b01 The value of 1 indicates 16 bit device IDs ftype 3 0 15 112 201101 The value of 4 hD decimal 13 indicates a Response Class packet destinationld 15 0 111 96 16 hAAAA The sourcelD and destinationID of the NREAD request are sourceId 15 0 95 80 16 hDDDD Swapped in the response transaction ttype 3 01 79 76 471000 The value of 8 indicates a Response transaction with data payload The value of 0 indicates Done The current packet successfully 7 400000 completes the requested transaction Value in the response packet matches the transact ionID of
224. nterconnect Specification v2 2 Part 10 Data Streaming Logical Specification m RapidlO Interconnect Specification v2 2 Part 1 Input Output Logical Specification m RapidlO Interconnect Specification v2 2 Part 2 Message Passing Logical Specification m RapidlO Interconnect Specification v2 2 Part 10 Data Streaming Logical Specification Switch Route Table Destination RapidlO Interconnect Specification Part 3 Common ID Limit Transport Specification RapidlO Interconnect Specification v2 2 Part 10 Data Streaming Logical Specification 1 The CARs are not used by any of the RapidlO II IP core internal modules They do not affect the functionality of the RapidlO II IP core These registers are all Read Only Their values are set using the RapidlO II parameter editor when generating the IP core or with configuration input signals which should not change value during normal operation These registers inform either a local processor or a processor on a remote end about the IP core s capabilities 0x10 Processing Element Features 0x14 Switch Port Information 0x18 Source Operations 0x1C Destination Operations 0x34 0x3C Data Streaming Information Command and Status Registers CSRs These registers are described in Command and Status Registers CSRs on page 6 31 0x48 Data Streaming Logical Layer RapidlO Interconnect Specification v2 2 Part 10 Data Control Streaming Logical Specification
225. nterface is not allowed by the Avalon MM specification 2 When wrsize has the value of 1011 waptr has the value of 1 and address 0 has the value of 1 the byteenable value presented on the Avalon MM master interface in the first clock cycle is 16 b1111 1111 0000 0000 and the byteenable value presented the second cycle is 16 b0000 0000 1111 1111 Table 4 8 lists the write request conversions the RapidIO II IP core performs for RapidIO write request packets with wrsize value greater than 4 1011 Table 4 8 Avalon MM 1 0 Master Write Transaction Burstcount and Byteenable Il RapidlO Values Avalon MM Signal Values RapidlO Field Values Payload Byteenable 16 hXXXX Size is Multiple Burstcount wrsize address 0 Intermediate i of 16 First Cycle Final Cycle 4 bxxxx 1 bx Bytes 7 Cycles 0 FFFF FFFF FFFF Yes Payload size in bytes 1100 1111 1 16 FF00 FFFF OOFF plus 1 0 No 2 FFFF FFFF OOFF 3 FF00 FFFF FFFF Note to Table 4 8 1 Ifthe packet payload is larger than the maximum size allowed for the packet wrsize and wdptr values the RapidlO II IP core records an Illegal transaction decode error in the Error Management Extension registers and for NWRITE R request packets returns an ERROR response 2 Ifthe payload size is not a multiple of 16 bytes and address 0 has the value of zero the value of burstcount is the number of 8 byte words in the
226. o the Logical layer modules or pass through interface In these cases the transport rx packet dropped output signal is not asserted Transmitter On the transmit side the Transport layer module uses a modified round robin scheduler to select the Logical layer module to transmit packets The Physical layer continuously sends Physical layer transmit buffer status information to the Transport layer Based on this information the Transport layer either implements a standard round robin algorithm to select the Logical layer module from which to transmit the next packet or implements a modified algorithm in which the Transport layer only considers packets whose priority field is set at or above a specified threshold The incoming status information from the Physical layer determines the current priority threshold The status information can also temporarily backpressure the Transport layer by indicating no packets of any priority level can currently be selected February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 4 62 Chapter 4 Functional Description Physical Layer The Transport layer polls the various Logical layer modules to determine whether a packet is available When a packet of the appropriate priority level is available the Transport layer transmits the whole packet and then continues polling the next logical modules In a variation with a user defined Logical layer connected to the Avalon ST pass through inter
227. o the sister rio module The testbench performs the writes by running the mnt test rw trans task with the following parameter values WRITE transaction type to be executed mnt address address to be driven on the Avalon MM address bus mnt wr data write data to be driven on the Avalon MM write data bus The task performs the write transaction across the Maintenance Write Avalon MM slave interface The DUT then sends two MAINTENANCE read requests to the sister rio module The testbench performs the writes by running the mnt test rw trans task with the following parameter values READ transaction type to be executed mnt address address to be driven on the Avalon MM address bus mnt rd data parameter that stores the data read across the Avalon MM read data bus Themnt test rw trans task performs the read transaction across the Maintenance Read Avalon MM slave interface The write transaction the testbench sends across the Avalon MM interface is translated by the DUT to a RapidIO MAINTENANCE write request packet Similarly the read transaction across the Avalon MM interface is translated to a RapidIO MAINTENANCE read request packet The MAINTENANCE write and read request packets are received by the sister rio module and translated to Avalon MM transactions that are presented across the sister rio module s Maintenance master Avalon MM interface In the testbench the write and read transactions are checked and
228. of 1 To disable it set the WEN bit to the value of zero For each defined and enabled window the RapidIO II IP core masks out the RapidIO address s least significant bits with the window mask and compares the resulting address to the window base The matching window is the lowest numbered window for which the following equation holds rio addr 33 4 amp xamm 1 0 mask 31 4 1 0 base 31 4 amp xamm 1 0 mask 31 4 where m rio addr 33 0 is the 34 bit RapidIO address composed of xamsbs 1 0 address 28 0 3b 000 for RapidIO header fields xamsbs and address mask 31 0 is composed of Mask register 31 4 4b 0000 base 31 0 is composed of Base register 31 4 4b 0000 xamm 1 0 is the XAMM field of the I O Master Mapping Window Mask register xamb 1 0 is the XAMB field of the I O Master Mapping Window Base register The RapidIO II IP core determines the Avalon MM address from the least significant bits of the RapidIO address and the matching window offset using the following equation February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 4 12 Chapter 4 Functional Description Logical Layer Interfaces Avalon MM address 31 4 offset 31 4 amp mask 31 4 rio addr 31 4 amp mask 31 4 where offset 31 0 is the offset register The least significant four bits of this register are always 4 0000 The definitions of all other te
229. oftware to produce output files for programming an Altera device RapidlO II MegaCore Function User Guide February 2013 Altera Corporation Chapter 2 Getting Started Qsys Design Flow Figure 2 2 shows a block diagram of an example Osys system Figure 2 2 Qsys System 2 5 RapidlO Simulation Testbench Module RapidlO 11 MegaCore Function System Interconnect DMA On Chip On Chip FIFO Memory Qsys System 7 For Information About Refer To System interconnect Qsys Interconnect chapter in volume 1 of the Quartus II Handbook and the Avalon Interface Specifications Qsys Quartus software System Design with Qsys section in volume 1 of the Quartus Il Handbook Quartus 11 Help Specifying Parameters To specify RapidIO II parameters using the Osys flow follow these steps 1 Create a new Quartus II project using the New Project Wizard available from the File menu 2 On the Tools menu click Osys 3 On the System Contents tab in the Component Library pane select RapidIO and click Add The RapidIO II parameter editor appears 57 You can find RapidIO II by expanding Library Interface Protocols RapidIO 4 Specify the required parameters on all tabs of the RapidIO II parameter editor For detailed explanations of these parameters refer to Chapter 3 Parameter Settings Februar
230. on Indicates whether an IDLE2 sequence has been received by the lane since this field was last reset To reset this bit write the value of 1 b1 1 b0 No IDLE2 sequence has been received since the bit was last reset 1 b1 An IDLE2 sequence has been received since the bit was last reset At the rising edge of this bit the RapidlO II IP core generates a maskable interrupt Indicates that the information in this register collected from the received IDLE2 sequence is information from the most recent IDLE2 control symbol marker and CS field that were received by this lane without detected errors and that the lane s 1ane sync signal has remained asserted since the most recent control symbol marker and CS field were received 1 b0 The IDLE2 information is not current 1 b1 The IDLE2 information is current Default 1 b0 1 b0 Values changed 29 RO Indicates whether the values of any of the other 31 bits in this register have changed since the register was last read This bit is reset when the register is read 1 b0 The values have not changed 1 b1 One or more values have changed 1 b0 Implementation defined Connected port lane receiver trained Received port width 28 27 26 24 RO RO Holds the value of the implementation defined bit in the received CS field Indicates the receiver in the connected lane in the RapidlO link partner is trained 1 b0 Receiver not t
231. on User Guide 4 6 Chapter 4 Functional Description Logical Layer Interfaces In systems generated by Osys this circuit is generated automatically However if your RapidIO II IP core variation is not generated by Osys you must implement logic to ensure that rstt n and reset are driven from the same source and that each meets the minimal hold time and synchronous deassertion requirements While the module is held in reset the Avalon MM waitrequest outputs are driven high and all other outputs are driven low When the module comes out of the reset state all buffers are empty Refer to Chapter 6 Software Interface for the default value of registers after reset For more information about the requirements for reset signals refer to Chapter 5 Signals Consistent with normal operation following the reset sequence the Initialization state machine transitions to the SILENT state In this state the transmitters are turned off If two communicating RapidIO II IP cores are reset one after the other one of the IP cores may enter the Input Error Stopped state because the other IP core is in the SILENT state while this one is already initialized The initialized IP core enters the Input Error Stopped state and subsequently recovers For details of the RapidIO Initialization state machine refer to section 4 12 Port Initialization of Part 6 LP Serial Physical Layer Specification of the RapidIO Interconnect Specification Revision 2 2
232. on about valid values refer to Table 4 10 and Table 4 12 Write burst count invalid Asserted when io s burstcount has a value that is larger than 16 except in cases with first byteenable with a value of INVALID WRITE BURSTCOUNT 2 RW1C OxFFOO and final byteenable with a value of OxOOFF inan 1 bo Avalon MM write request on the 1 0 Logical slave interface For information about valid values refer to Table 4 10 and Table 4 12 Write request address out of bounds Asserted when the WRITE OUT OF BOUNDS 1 RW1C Avalon MM address does not fall within any enabled 1 b0 address mapping window Read request address out of bounds READ OUT OF BOUNDS 0 RW1C Asserted when the Avalon MM address does not fall 1 00 within any enabled address mapping window Table 6 61 Input Output Slave Interrupt Enable Offset 0x10504 Field Bits Access Function Default RSRV 31 6 RO Reserved 26 h0 INVALID READ BURSTCOUNT 5 RW Read burst count invalid interrupt enable 1 bo INVALID READ BYTEENABLE 4 RW Read byte enable invalid interrupt enable 1 b0 INVALID WRITE BYTEENABLE 3 RW Write byte enable invalid interrupt enable 1 b0 INVALID WRITE BURSTCOUNT 2 RW Write burst count invalid interrupt enable 1 b0 WRITE OUT OF BOUNDS 1 RW Write request address out of bounds interrupt enable 1 bo READ OUT OF BOUNDS 0 RW Read request address out of bounds interrupt enable 1 bo RapidlO II MegaCore Function User Guide February 2013 Altera Corpo
233. onality and registers to support standard route table configuration The RapidIO IP core does not implement the Standard Route CSRs at offsets 0x70 0x74 and 0x78 Enable Extended Route Table Configuration Support If you turn on Enable standard route table configuration support the Enable extended route table configuration support parameter is available Enable extended route table configuration support when turned on sets the Extended route table configuration support bit in the Processing Element Features CAR and indicates that the processing element supports the extended route table configuration mechanism This property is relevant in switch processing elements only If you turn on Enable extended route table configuration support user logic must implement the functionality and registers to support extended route table configuration The RapidIO II IP core does not implement the Standard Route CSRs at offsets 0x70 0x74 and 0x78 Enable Flow Control Support Enable flow control support when turned on sets the Flow Control Support bit in the Processing Element Features CAR and indicates that the processing element supports flow control Enable Switch Support Enable switch support when turned on sets the Switch bit in the Processing Element Features CAR Table 6 26 on page 6 26 and indicates that the processing element can bridge to another external RapidIO interface A processing element that only bridges to a local end
234. ore when it prepares the RapidlO packet Depends on the values programmed in the Tx Maintenance Address Translation Window registers as defined in Table 6 41 through Table 6 44 Refer to Defining the Maintenance Address Translation Windows on page 4 34 for the matching and conversion calculations wdptr The IP core assigns to this field the negation of mut s address 2 The IP core assigns to this field the value programmed in the HOP COUNT field ofthe Tx Maintenance Mapping Window n Control register Table 6 44 hop count on page 6 35 for the matching address translation window n Refer to Defining the Maintenance Address Translation Windows on page 4 34 for matching details config offset 20 0 User Receiving MAINTENANCE Read Requests and Sending Responses Table 4 21 lists the Maintenance Avalon MM interface usage example this section describes Table 4 21 Maintenance Interface Usage Example Receiving MAINTENANCE Read Request and Sending Response R Payload Size User Operation Device ID Width Bytes Receive MAINTENANCE read request 16 0 Send MAINTENANCE read response 16 32 The RapidIO II IP core generates read requests on the Maintenance Avalon MM master interface when it receives Type 8 MAINTENANCE Read packets on the RapidIO link with the following properties ttype has the value of 410000 indicating a MAINTENANCE Read request m config offset has a value that
235. ores the Quartus II Fitter handles the merge of multiple Native PHY IP cores in the same transceiver block automatically if they meet the merging requirements specified in the Altera Transceiver PHY IP Core User Guide If you have different RapidIO II IP cores in different transceiver blocks on your device you may choose to include multiple Transceiver Reconfiguration Controllers in your design However you must ensure that the Transceiver Reconfiguration Controllers that you add to your design have the correct number of interfaces to control dynamic reconfiguration of all your RapidIO II IP core transceivers The correct total number of reconfiguration interfaces is the sum of the reconfiguration interfaces for each RapidIO II IP core the number of reconfiguration interfaces for each RapidIO IP core is the number of channels plus one You must ensure that the reconfig togxb and reconfig fromgxb signals of an individual RapidIO II IP core connect to a single Transceiver Reconfiguration Controller For example if your design includes one x4 RapidIO II IP core and three x1 RapidIO II cores the Transceiver Reconfiguration Controllers in your design must include eleven dynamic reconfiguration interfaces five for the x4 RapidIO IP core and two for each of the x1 RapidIO II IP cores The dynamic reconfiguration interfaces connected to a single RapidIO II IP core must belong to the same Transceiver Reconfiguration Controller In most cases
236. orms interoperability tests on the RapidIO II IP core which certify that the RapidIO IL IP core is compatible with third party RapidIO devices Altera performs interoperability testing with processors and switches from various manufacturers including m Texas Instruments Incorporated m Integrated Device Technology Inc IDT Altera has performed interoperability tests with the IDT CPS 1848 and IDT CPS 1616 switches Testing of additional devices is an on going process Performance and Resource Utilization This section contains tables showing IP core variation sizes in the different device families Table 1 3 lists the resources and expected performance for selected variations that use these modules m Minimal variation m Physical layer m Transport layer m Avalon ST pass through interface m Full featured variation m Physical layer m Transport layer m Maintenance module m Doorbell module m Input Output Avalon MM master m Input Output Avalon MM slave m Error Management Registers block All variations are configured with the following parameter settings m Transceiver reference clock frequency of 156 25 MHz m The maximum RapidIO baud rate supported by the device m Support 1 2x and 4x modes of operation The numbers of ALMs primary logic registers and secondary logic registers in Table 1 3 are rounded up to the nearest 100 Table 1 3 shows results obtained using the Quartus II software v12 1 SP1 for the following d
237. ou can instantiate this IP core in the MegaWizard Plug In Manager or in the Qsys system integration tool The MegaWizard Plug In Manager flow offers the following advantages m Allows you to parameterize the IP core to create a variation that you can instantiate manually in your design The Osys flow offers the following advantages m Allows you to easily integrate other Altera provided custom components with the IP core in your design m Provides visualization of hierarchical designs m Automatically generates interconnect fabric and inserts adapters Figure 2 1 shows the stages for creating a system with the RapidIO II IP core and the Quartus II software Each stage is described in detail in subsequent sections Figure 2 1 RapidlO II IP Core Design Flow Select Design Flow MegaWizard Plug in Qsys Manager Flow Flow y y Specify Parameters Specify Parameters y Y Simulate with Complete Qsys System Testbench y y Instantiate IP Core Simulate System In Design Specify Constraints Compile Design Program Device February 2013 Altera Corporation RapidlO II MegaCore Function User Guide 2 2 Chapter 2 Getting Started MegaWizard Plug In Manager Design Flow MegaWizard Plug In Manager Design Flow You can use the MegaWizard Plug In Manager in the Quartus II software to parameterize a custom IP core v
238. oximately equal to 4 5 seconds multiplied by the contents of this field divided by 224 1 RSRV 7 0 URO Reserved 8 h0 Table 6 8 Port Response Time Out Control CSR 0x124 Field Bits Access Function Default Time out internal value for request response pairs the time interval between sending a request packet and receiving the corresponding response packet The duration of the port response time out for all transactions that require a response including MAINTENANCE DOORBELL NWRITE and NREAD transactions is approximately equal to 4 5 seconds multiplied by the VALUE 31 8 RW contents of this field divided by 2 1 2A hFF FFFF Note A new value in this field might not propagate quickly enough to be applied to the next transaction Note Avoid changing the value in this field when any packet is waiting to be transmitted or waiting for a response to ensure that in each FIFO the pending entries all have the same time out value RSRV 7 0 URO Reserved 8 hd Table 6 9 Port General Control Offset 0x13C Part 1 of 2 Field Bits Access Function Default A host device is a device that is responsible for system exploration initialization and maintenance Host devices typically initialize agent or slave devices HOST 34 RW 1 b0 agent or slave device 1 1 b1 host device This field is for software use only Its value has no effect on hardwa
239. packet payload divided by two and rounded up 3 Ifthe payload size is not a multiple of 16 bytes and address 0 has the value of one the value of burstcount is the number of 8 byte words in the packet payload divided by two rounded up and incremented by 1 Input Output Avalon MM Master Module Timing Diagrams Figure 4 6 shows the timing dependencies on the Avalon MM master interface for an incoming RapidIO NREAD transaction Figure 4 7 shows the timing dependencies on the Avalon MM master interface for an incoming RapidIO NWRITE transaction February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 4 18 Chapter 4 Functional Description Logical Layer Interfaces The RapidIO II IP core receives both transaction requests on the RapidIO link and sends them to the Logical layer Avalon MM master module If the RapidIO link partner is also an Altera RapidIO II IP core the timing diagrams in Input Output Avalon MM Slave Module Timing Diagrams on page 4 31 show the same transactions as they originate on the Avalon MM interface of the RapidIO link partner s Input Output Avalon MM slave module Figure 4 6 NREAD Transaction on the Input Output Avalon MM Master Interface sysclk iom_rd_wr_waitrequest iom_rd_wr_read iom rd wr address 31 0 00000000 Adro Adri iom rd wr
240. pe and the Transport Type tt field of the packet matches the device ID width setting of this IP core the packet is routed to the appropriate Logical layer The destination ID can match this endpoint only if the tt field in the packet matches the device ID width setting of the endpoint Request packets with a supported ftype and correct tt field but an unsupported ttype are routed to the Logical layer supporting the ftype which allows the following tasks An ERROR response can be sent to requests that require a response m Anunsupported transaction error can be recorded in the Error Management extension registers Response packets are routed to a Logical layer module or the Avalon ST pass through port based on the value of the target transaction ID field For more information refer to Table 4 23 on page 4 48 which defines the transaction ID ranges Disable Destination ID Checking Disable destination ID checking by default determines the default value of the option to route a request packet with a supported ftype but a destination ID not assigned to this endpoint The effect of this option is detailed in Transport Layer on page 4 59 You specify the initial value for the option in the RapidIO II parameter editor and software can change it by modifying the value of the DIS DEST ID CHK field of the Port 0 Control CSR Refer to Table 6 15 on page 6 16 for information about this register By default this parameter is turn
241. perations CAR is the result of the bitwise exclusive or operation applied to the default values and the value you specify for Destination operations CAR override in the RapidlO II parameter editor 3 The default value is 1 b1 if you turn on Enable 1 0 Logical layer Master module in the RapidlO Il parameter editor The default value is 1 bo if you turn off Enable 1 0 Logical layer Master module in the RapidlO Il parameter editor 4 The default value is 1 b1 if you turn on Enable Doorbell support in the RapidlO II parameter editor The default value is 1 bo if you turn off Enable Doorbell support in the RapidlO Il parameter editor 5 The default value is 1 b1 if you turn on Enable Maintenance module in the RapidlO II parameter editor The default value is 1 bo If you turn off Enable Maintenance module Table 6 30 Switch Route Table Destination ID Limit CAR Offset 0 34 1 Field Bits Access Function Default RSRV 31 16 RO Reserved 16 h0 Maximum configurable destination ID Value is the maximum number of destination IDs minus one Max destID 15 0 RO 2 Note to Table 6 30 1 Ifthe Standard route table configuration support bit or the Extended route table configuration support bit in the Processing Element Features CAR is set user logic must implement the functionality and registers to support the standard or extended route table configuration The RapidlO II IP core does not implement the Standard Ro
242. pidIO II IP core does not support automatic baud rate discovery Table 3 1 shows the baud rates supported by the RapidIO II IP core for each device family A device family may include devices at speed grades that do not support all the indicated baud rates For information about the speed grades the RapidIO II IP core supports for each device family RapidIO mode and baud rate combination refer to Table 1 4 on page 1 7 Table 3 1 RapidlO II IP Core Device Support Lanes 1x 2x Serial 4x Device Baud Family Rate 1250 2500 3125 5000 6250 1250 2500 3125 5000 6250 MBaud Arria V v v v v v v v v v v Cyclone V o ov 4nl Y v YO Stratix V v v Y v Y v Y Y Y v Note to Table 3 1 1 In the Cyclone V device family only Cyclone V GT devices support the 5 0 GBaud rate Reference Clock Frequency Reference clock frequency defines the frequency of the reference clock for your RapidIO II IP core internal transceiver The RapidIO II parameter editor allows you to select any frequency supported by the transceiver For more information about the reference clock in high speed transceiver blocks and the supported frequencies refer to Clocking and Reset Structure on page 4 3 Transport Layer Settings The Transport layer settings specify properties of the Transport layer in your RapidIO II IP core variation These parameters determine whether the RapidIO II IP
243. point is not considered a switch port Switch Port Information CAR If you turn on Enable switch support the following parameters are available Number of Ports Number of ports specifies the total number of ports on the processing element This value sets the PortTotal field of the Switch Port Information CAR Table 6 27 on page 6 28 Port Number Port number sets the PortNumber field of the Switch Port Information CAR This value is the number of the port from which the MAINTENANCE read operation accesses this register Switch Route Table Destination ID Limit CAR The Switch Route Table Destination ID Limit CAR is described in Table 6 30 on page 6 30 RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 3 Parameter Settings 3 9 Capability Registers Settings Switch Route Table Destination ID Limit Switch route table destination ID limit sets the Max destID field of the Switch Route Table Destination ID Limit CAR Data Streaming Information CAR The Data Streaming Information CAR is described in Table 6 31 on page 6 31 Maximum PDU Maximum PDU sets the MaxPDU field of the Data Streaming Information CAR Number of Segmentation Contexts Number of segmentation contexts sets the SegSupport field of the Data Streaming Information CAR Source Operations CAR The Source operations CAR override parameter supports user input to the values of all of the fields of the Source Operations C
244. ponse MAINTENANCE port write request DOORBELL request and response February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 1 4 Chapter 1 About The RapidlO Il MegaCore Function Device Family Support Device Family Support Table 1 1 defines the device support levels for Altera IP cores Table 1 1 Altera IP Core Device Support Levels FPGA Device Families HardCopy Device Families Preliminary support The core is verified with HardCopy Companion The IP core is verified with preliminary timing models for this device family The IP core preliminary timing models for the HardCopy companion meets all functional requirements but might still be device The IP core meets all functional requirements but undergoing timing analysis for the device family It can be might still be undergoing timing analysis for the HardCopy used in production designs with caution device family It can be used in production designs with caution Final support The IP core is verified with final timing HardCopy Compilation The IP core is verified with final models for this device family The IP core meets all timing models for the HardCopy device family The IP core functional and timing requirements for the device family and meets all functional and timing requirements for the device can be used in production designs family and can be used in production designs Table 1 2 shows the level of support offered b
245. ponse February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 4 32 Chapter 4 Functional Description Logical Layer Interfaces Figure 4 15 NWRITE Transaction on the Input Output Avalon MM Slave Interface ios rd wr waitrequest Sys ios rd wr write ios rd wr address 27 0 00000000 AdrA AdrB ios_rd_wr_writedata 127 0 wO A w2 X w3 A w4 5 ios rd wr byteenable 15 0 ios rd wr burstcount 4 0 Maintenance Module The Maintenance module is an optional component of the I O Logical layer The Maintenance module processes MAINTENANCE transactions including the following transactions m 8 MAINTENANCE read and write requests and responses m Type8 Port write packets The Avalon MM slave interface allows you to initiate a MAINTENANCE read or write operation on the RapidIO link The Avalon MM slave interface supports the following Avalon transfers m Single slave write transfer with variable wait states m Pipelined read transfers with variable latency The data bus on the Maintenance Avalon MM interface is 32 bits wide The Avalon MM master interface allows you to respond to a MAINTENANCE read or write operation on the RapidIO link The Avalon MM master interface supports the following Avalon transfers m Single master write transfer m
246. processes the response packets that it receives Anomalies are reported through one or more of the following three channels m Standard error management registers m Registers in the implementation defined space m The Avalon MM slave interface s error indication signal Standard Error Management Registers The following standard defined error types can be declared by the I O Avalon MM slave module The corresponding error bits are then set and the required packet information is captured in the appropriate error management registers m IO Error Response is declared when a response with ERROR status is received for a pending NREAD or NWRITE R request m Unsolicited Response is declared when a response is received that does not correspond to any pending NREAD or NWRITE R request m Packet Response Time Out is declared when a response is not received within the time specified by the Port Response Time Out Response CSR Table 6 8 on page 6 8 for an NREAD or NWRITE request February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 4 10 Chapter 4 Functional Description Error Detection and Management m Illegal Transaction Decode is declared for malformed received response packets occurring from any of the following events m NREAD or NWRITE R response packet with status not DONE nor ERROR m NWRITE R response packet with payload or with a transaction type indicating the presence of a payload m NREAD response p
247. r drops packets with a 16 bit device ID In any of the cases in which the packet is dropped the Transport layer module asserts the transport rx packet dropped signal m Request packets with a supported ftype and a tt value that matches the RapidIO II IP core s device ID width are routed to the Logical layer supporting the ftype If the request packet has an unsupported ttype the Logical layer module then performs the following tasks m Sends an ERROR response for request packets that require a response m Records an unsupported_transaction error in the Error Management extension registers m Packets that would be routed to the Avalon ST pass through interface in the case that the RapidIO II IP core does not implement an Avalon ST pass through interface are dropped In this case the Transport layer module asserts the transport rx packet dropped signal ftype 13 response packets are routed based on the value of their target transaction ID targetTID field Each Logical layer module is assigned a range of transaction IDs Table 4 23 specifies these ranges If the transaction ID of a received response packet is not within one of the ranges assigned to one of the enabled Logical layer modules the packet is routed to the Avalon ST pass through interface Packets marked as errored by the Physical layer for example packets with a CRC error or packets that were stomped are filtered out and dropped from the stream of packets sent t
248. r Detection and Management To meet the RapidIO specification requirements for packet priority handling and deadlock avoidance the Physical layer transmitter includes four transmit queues and four retransmit queues one for each priority level The transmit buffer is the main memory in which the packets are stored before they are transmitted The buffer is partitioned into 64 byte blocks to be used on a first come first served basis by the transmit and retransmit queues The following events cause any stored packets to be lost m Fatal error caused by receiving a link response control symbol with the port status set to Error m Fatal error caused by receiving a 1ink response control symbol with the port status set to OK but the ackid status set to an ackID that is not pending transmitted but not acknowledged yet m Fatal error caused by transmitter timing out while waiting for link response m Fatal error caused by receiver timing out while waiting for link request m Receive four consecutive link request control symbols with the cmd set to reset device Error Detection and Management The error detection and management mechanisms in the RapidIO specification and those built into the RapidIO II IP core provide a high degree of reliability In addition to error detection management and recovery features the RapidIO II IP core also provides debugging and diagnostic aids The RapidIO II IP core optionally implements the Error Manageme
249. r PHY Reset Controller IP Core chapter of the Altera rx digitalreset n 0 Input Transceiver PHY IP Core User Guide rx analogreset n 0 Input You must connect these signals to an Altera Transceiver PHY Reset Controller rx ready 1 0 Input IP core which implements the appropriate reset sequence for the device m Tem Connect each signal to the corresponding signal the Transceiver PHY Reset TET TUER MS p Controller IP core tx analogreset n 0 Input tx ready n 0 Input rx is lockedtodata n 0 Output rx is lockedtoref n 0 Output Indicates that the CDR is locked to tx p11 refclk rx syncstatus n 0 Output Indicates that the word aligner is synchronized to incoming data Output Indicates that the lane detects a sender at the other end of the link the signal is A u aa a p above the programmed signal detection threshold value Note to Table 5 7 1 Refer to Instantiating Multiple RapidlO II IP Cores on page 2 8 for information about how to successfully combine multiple high speed transceiver channels whether in two RapidlO IP core instances or in a RapidlO IP and in another component in the same transceiver block RapidlO II MegaCore Function User Guide February 2013 Altera Corporation Chapter 5 Signals 5 5 Logical and Transport Layer Signals To control the transceivers you must implement the following blocks in your design m Dynamic reconfiguration block Refer to Chapter 2 Getting
250. r ensures that a maximum of 63 unacknowledged packets are transmitted and that the ackIDs are used and acknowledged in sequential order To support retransmission of unacknowledged packets the Physical layer maintains a copy of each transmitted packet until the packet is acknowledged with a packet accepted control symbol The RapidIO II IP core supports receiver controlled flow control in both directions If the receiver detects that an incoming packet or control symbol is corrupted or a link protocol violation has occurred the Physical layer enters an error recovery process In the case of a corrupted incoming packet or control symbol and some link protocol violations the transmitter sends a packet not accepted symbol to the sender A link request link response control symbol pair is then exchanged between the link partners and the sender then retransmits all packets starting from the ackID specified in the link response control symbol The transmitter attempts the link request link response control symbol pair exchange seven times If the protocol and control block times out awaiting the response to the seventh 1ink request control symbol it declares a fatal error When a time out occurs for an outgoing packet the Physical layer starts the recovery process If a packet is retransmitted the time out counter is reset RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 4 Functional Description 4 65 Erro
251. r logic asserts gen tx ready gen tx startofpacket Input gen tx startofpacket and gen tx valid to indicate that a packet is available for the IP core to sample 1 gen tx endofpacket Input Marks the active cycle containing the end of the packet 1 February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 4 50 Chapter 4 Functional Description Logical Layer Interfaces Table 4 24 Avalon ST Pass Through Interface Transmit Side Avalon ST Sink Signals Part 2 of 2 2 Signal Name Type Function iz data t270 Input A 128 bit wide data bus Carries the bulk of the information transferred from the gen_ x put source to the sink This bus identifies the number of empty bytes on the final data transfer of the packet which occurs during the clock cycle when gen_tx_endofpacket is gen tx empty 3 0 Input asserted 1 The number of empty bytes must always be even E MCN Indicates the number of valid bytes in the packet being transferred The IP core X LUPUS RU EE Input samples this signal only while gen tx startofpacket is asserted User logic must ensure this signal is correct while gen tx startofpacket is asserted Notes to Table 4 24 1 gen tx validis used to qualify all the other input signals of the transmit side of the Avalon ST pass through interface 2 This signal is not defined in the Avalon Interface Specifications However it refers to dat
252. rained 1 b1 Receiver trained Received port width This field supports the following valid values 3 b000 One lane 3 b001 2 lanes 3 b010 4 lanes 3 b011 8 lanes 3 b100 16 lanes The values 3 b101 3 b111 are reserved 1 b0 3 b000 Lane number in connected port 23 20 Number of the lane 0 15 in the connected port Normally the value should be n 4h0 Connected port transmit emphasis Tap 1 status 17 16 Tap 1 status of the RapidlO link partner on the connected lane 2 b00 Tap 2 b01 Tap 2 b10 Tap 2 b11 Tap not implemented at minimum emphasis setting at maximum emphasis setting at intermediate emphasis setting 2 b00 RapidlO II MegaCore Function User Guide February 2013 Altera Corporation Chapter 6 Software Interface 6 23 Physical Layer Registers Table 6 18 LP Serial Lane n Status 1 Far End Lane n Status Offset 0x214 0x234 0x254 0x274 Part 2 of 2 Field Bits Access Function Default Tap 1 status of the RapidlO link partner on the connected lane port transmit 17 16 RO 2 b00 Tap 1 not implemented 2 b00 emphasis Tap 1 status 2 b01 Tap 1 at minimum emphasis setting 2 b10 Tap 1 at maximum emphasis setting 2 b11 Tap 1 at intermediate emphasis setting Indicates scrambling descrambling is enabled in the RapidlO Memes Je nig m R link partner on the connected lane m a n escra n 3
253. ransceiver configuration The RapidIO I IP core instantiates a Native PHY IP core to configure the transceivers The RapidIO II IP core provides no parameters to modify this configuration directly Altera recommends you do not modify the default transceiver settings configured in the Native PHY IP core instance generated with the RapidIO II IP core T For information about the transceiver block refer to Volume 3 Transceivers of the Arria V Device Handbook to Volume 2 Transceivers of the Cyclone V Device Handbook or to Volume 3 Transceivers of the Stratix V Device Handbook For information about the Native PHY IP core refer to the Altera Transceiver PHY IP Core User Guide The Physical Layer parameters define the following characteristics of the Physical layer m Supported modes m Maximum baud rate m Reference clock frequency Supported Modes The Supported modes parameter allows you to specify which of the 1x 2x and 4x modes of operation this RapidIO II IP core supports All RapidIO II IP core variations support 1x mode The RapidIO II MegaCore function initially attempts link initialization in the maximum number of lanes that the variation supports The IP core supports fallback to lower numbers of ports February 2013 Altera Corporation RapidlO II MegaCore Function User Guide 3 2 Chapter 3 Parameter Settings Transport Layer Settings Maximum Baud Rate Maximum baud rate defines the maximum supported baud rate The Ra
254. ration Chapter 6 Software Interface 6 41 Transport and Logical Layer Registers Input Output Slave Pending Transactions Table 6 62 Input Output Slave Pending NWRITE R Transactions Offset 0x10508 Field Bits Access Function Default RSRV 31 8 RO Reserved 24 h0 Number of pending NWRITE R write requests that PENDING NWRITE RS 7 0 RO have been initiated in the 1 0 Avalon MM slave Logical 8 bo layer module but have not yet completed Table 6 63 Input Output Slave Avalon MM Write Transactions Offset 0x1050C Field Bits Access Function Default RSRV 31 16 RO Reserved 16 h0 Number of write transfers initiated on Avalon MM Input Output Slave port so far Count increments on first system clock cycle in which the io s write SOFIA ENS How TRO signal is asserted and the io s wr waitrequest signal is not asserted This counter rolls over to 0 after its maximum value Table 6 64 Input Output Slave RapidlO Write Requests Offset 0x10510 Field Bits Access Function Default RSRV 31 16 RO Reserved 16 h0 Number of write request packets transferred from the Avalon MM Input Output Slave module to the Transport layer or cancelled COMPLETED OR CANCELLED WRITES 15 0 RO Count increments when the write request 16 b0 packet is sent to the Transport layer or when a write transaction is cancelled This counter rolls over to 0 after its maximum value
255. re The Master Enable bit controls whether or not a device is allowed to issue requests to the system If Master Enable is not set the device may only ENA 30 RW respond to requests 1 1 00 The processing element cannot issue requests 1 b1 The processing element can issue requests RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 6 Software Interface 6 9 Physical Layer Registers Table 6 9 Port General Control Offset 0x13C Part 2 of 2 Field Bits Access Function Default This device has been located by the processing element responsible for system configuration DISCOVER 29 RW 1 bO The device has not been previously discovered 1 1 b1 The device has been discovered by another processing element This field is for software use only Its value has no effect on hardware RSRV 28 0 RO Reserved 29 b0 Note to Table 6 9 1 The reset value of this field is set in the RapidlO II parameter editor Table 6 10 Port 0 Link Maintenance Request CSR Offset 0x140 Field Bits Access Function Default RSRV 31 3 RO Reserved 29 b0 Command to be sent in a 1ink request control symbol When a valid value is written to this field the RapidlO IP core generates link request control symbol with the specified command The IP core does not generate a 1ink request control symbol when an COMMAND 2 0 RW invalid value is written
256. re Function User Guide 4 4 Chapter 4 Functional Description Clocking and Reset Structure Table 4 3 lists the clock rates in the different RapidIO II IP core variations showing the relationship between baud rate default transceiver reference clock frequency and Avalon system clock frequency Table 4 3 Clock Frequencies in the RapidlO Il IP Core Default reference clock frequenc Avalon system clock Baud Rate 1 2 y 3 Gbaud MHz MHz 1 25 31 25 2 5 62 5 3 125 156 25 78 125 5 0 125 0 6 25 156 25 Notes to Table 4 3 1 For information about the allowed reference clock frequencies in Arria V Cyclone V and Stratix V devices refer to Reference Clock on page 4 3 2 The reference clock is called tx p11 refclk by default 3 The Avalon system clock is called sys c1k by default It runs at 1 40 the frequency of the maximum baud rate you configure in the RapidlO Il parameter editor irrespective of the baud rate you program in software Clock Domains in Your Qsys System In systems created with Osys the system interconnect manages clock domain crossing if some of the components of the system run on a different clock For optimal throughput run all the components in the datapath on the same clock Reset for RapidlO 1 IP Cores All RapidIO IP core variations have the following reset signals rst n resets the RapidIO II IP core tx ready tx a
257. re adaptive equalizers are controlled by the lane 1 b0 DU receiver and at least one of those adaptive equalizers is not trained 1 b1 The lane receiver controls no adaptive equalizers or all of the adaptive equalizers the receiver controls are trained Indicates whether scrambling descrambling is turned on in the IP core Scrambling 1 b0 Scrambling descrambling is disabled descrambling 28 101 Scrambling descrambling is enabled Control symbol and packet 10 enabled data characters are scrambled before transmission and descrambled when received Transmit emphasis Tap 1 status 2 b00 Transmit emphasis Tap 1 is not implemented Tap 1 27 26 RW 2 b01 Transmit emphasis Tap 1 Is at minimum emphasis 0 2 b00 status 2 b10 Transmit emphasis Tap 1 is at maximum emphasis 2 b11 Transmit emphasis Tap 1 is at an intermediate emphasis setting Transmit emphasis Tap 1 status 2 b00 Transmit emphasis Tap 1 is not implemented Tap 1 25 24 RW 2 b01 Transmit emphasis Tap 1 is at minimum emphasis 0 2 b00 status 2 b10 Transmit emphasis Tap 1 is at maximum emphasis 2 b11 Transmit emphasis Tap 1 is at an intermediate emphasis setting RSRV 23 8 RO Reserved 16 h0000 February 2013 Altera Corporation Chapter 6 Software Interface 6 25 Transport and Logical Layer Registers Table 6 21 LP Serial Lane n Status 4 Outgoing CS Field Offset 0x220 0x240 0x260 0x280 Part 2 of 2 Field Bits Access
258. re does not instantiate correctly in the top level RapidIO II IP core If you must modify transceiver settings perform the modifications by editing the project Quartus Settings File qsf Simulating the System During system generation Osys optionally generates a RapidIO II functional simulation model in the HDL you specify St For information about simulating Osys systems refer to the Creating a System with Qsys chapter in volume 1 of the Quartus II Handbook Adding Transceiver Analog Settings The current version of the RapidIO II IP core in variations that target an Arria V GZ or Stratix V device requires that you specify some analog transceiver settings Whether you instantiate your RapidIO II IP core in the MegaWizard Plug In Manager flow or in the Osys flow you must make these modifications After you generate your RapidIO II IP core in a Quartus II project that targets an Arria V GZ or Stratix V device perform the following steps 1 In the Quartus II software on the Assignments tab click Assignment Editor 2 In the Assignment Editor in the Assignment Name column double click lt lt new gt gt and select Transceiver Analog Settings Protocol 3 In the To column type the name of the transceiver serial data input node in your IP core variation This name is the variation specific version of the rd signal 4 In the Value column click and select SRIO 5 Repeat steps 2 to 4 to create an additional assignment with
259. return packet not accepted control symbols to force an error condition to be signaled by the sending device Indicates the port type parallel or serial 1 b0 Parallel port PORT TYPE 0 RO 1 b1 Serial port 1 b1 DROP PKT ENABLE 2 RW PORT LOCKOUT 1 RW The RapidlO II IP core supports only serial ports so this bit always has the value of 1 b1 Note to Table 6 15 1 Reflects the choice made in the RapidlO II parameter editor February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 6 20 Chapter 6 Software Interface Physical Layer Registers Table 6 16 LP Serial Lane Register Block Header 0x200 Field Bits Access Function Default Hard wired pointer to the next block in the data structure if one exists If this IP core variation instantiates the Error Management Extensions registers the value in this field is the address of the Error Management EF PTR 31 16 RO Extended Features block which is 0x300 If this IP core variation does not instantiate the Error Management Extensions registers the value of this field is determined by the Extended features pointer parameter in the RapidlO II parameter editor EF ID 15 0 RO Hard wired extended features ID 16 h000D Table 6 17 LP Serial Lane n Status 0 0ffset 0x210 0x230 0x250 0x270 Part 1 of 2 Field Bits Access Function Default The number of the port within the IP core to which
260. rite ones to both of these fields at the same time is ignored and that part of the register keeps its previous value February 2013 Altera Corporation RapidlO II MegaCore Function User Guide Input Output Slave Interrupts Table 6 60 and Table 6 61 describe the available Input Output slave interrupts and corresponding interrupt enable bits These interrupt bits assert the io s mnt irq signal if the corresponding interrupt bit is enabled Chapter 6 Software Interface Transport and Logical Layer Registers Table 6 60 Input Output Slave Interrupt Offset 0x10500 Field Bits Access Function Default RSRV 31 6 RO Reserved 26 h0 Read burst count invalid Asserted when io s burstcount has a value that is larger than 16 in INVALID READ BURSTCOUNT 5 RW1C an Avalon MM read request on the 1 0 Logical slave 1 b0 interface For information about valid values refer to Table 4 10 and Table 4 11 Read byte enable invalid Asserted when io s byteenable is set to an invalid value in an INVALID READ BYTEENABLE 4 RW1C Avalon MM read request on the 1 0 Logical slave 1 b0 interface For information about valid values refer to Table 4 10 and Table 4 11 Write byte enable invalid Asserted when io s byteenable is set to an invalid value in an INVALID WRITE BYTEENABLE 3 RW1C Avalon MM write request on the 1 0 Logical slave 1 bo interface For informati
261. rms in the equation appear in the definition of the matching window The value of the Avalon MM address 3 0 is always zero because the address is a byte address and the I O Logical layer master interface has a 128 bit wide datapath If the address does not match any window the I O Logical layer Master module performs the following actions Sets the Illegal Transaction Decode Error bit in the Error Management Extension registers Sets the ADDRESS OUT OF BOUNDS interrupt bit in the Input Output Master Interrupt register Table 6 54 on page 6 38 Asserts the interrupt signal io m mnt irqifthis interrupt is enabled by the corresponding bit in the Input Output Master Interrupt Enable register Table 6 55 on page 6 38 For a received NREAD or NWRITE R request packet that does not match any enabled window returns a RapidIO ERROR response packet User logic can clear an interrupt by writing 1 to the interrupt register s corresponding bit location RapidlO II MegaCore Function User Guide February 2013 Altera Corporation Chapter 4 Functional Description 4 13 Logical Layer Interfaces Figure 4 5 shows a block diagram of the I O master s window translation Figure 4 5 1 0 Master Window Translation RapidlO Address Space Ox3FFFFFFF8 Window Base Avalon MM Address Space OxFFFFFFF8 E _ 0x000000000 0x00000000 lt Window Size 39 Initial 33 31 43 0 R
262. roperty 1 0 Logical layer Master Avalon MM read and write ports 1 0 Logical layer Slave Avalon MM read and write ports RapidlO II IP Core v12 1 1 0 Logical layer Master module has a single Avalon MM interface for read and write transactions 1 0 Logical layer Slave module has a single Avalon MM interface for read and write transactions RapidlO IP Core v12 1 1 0 Logical layer Master module has one Avalon MM interface for read transactions and a separate Avalon MM interface for write transactions 1 0 Logical layer Slave module has Avalon MM interface for read transactions and a separate Avalon MM interface for write transactions Physical layer removes all CRC bits and padding Physical layer removes the 16 bit CRC that follows SILENT state machine is in the SILENT state CRC the 80th received byte of a RapidlO packet but not bytes from packets received from the RapidlO link the final CRC nor the padding bytes In 5 0 Gbaud variations the transmitter is turned off while the initialization state machine is in the Behavior in Transmitter is turned off while the initialization state SILENT state However in 1 25 2 5 and 3 125 Gbaud variations the transmitters send a continuous stream of K28 5 characters all of the same disparity in the SILENT state Remote host access to IP core registers Registers Handles incoming read and write MAINTENANCE requests with address in
263. ror Detect 0x30C Logical Transport Layer Error Enable 0x314 Logical Transport Layer Address Capture 0x318 Logical Transport Layer Device ID Capture 0x31C Logical Transport Layer Control Capture 0x328 Port Write Target Device ID 0x32C Packet Time to Live 0x340 Port 0 Error Detect 0x344 Port 0 Error Rate Enable 0x348 Port 0 Attributes Capture 0x34C Port 0 Packet Control Symbol Capture 0 0x350 Port 0 Packet Capture 1 0x354 Port 0 Packet Capture 2 0x358 Port 0 Packet Capture 3 0x368 Port 0 Error Rate 0x36C Port 0 Error Rate Threshold Table 6 66 Error Management Extensions Block Header 0x300 Field Bits Access Function Default Hard wired pointer to the next block in the data structure if one exists EF 31 16 RO The value of this field is determined by the Extended features pointer 16 h0000 parameter in the RapidlO II parameter editor EF ID 15 0 RO Hard wired extended features ID 16 h0007 Note to Table 6 66 1 The value of this field is determined in the RapidlO II parameter editor RapidlO II MegaCore Function User Guide February 2013 Altera Corporation Chapter 6 Software Interface Transport and Logical Layer Registers Table 6 67 Logical Transport Layer Error Detect CSR Offset 0x308 1 Part 1 of 2 6 43 Field IO ERROR RSP Bits 31 Access RO Function Received a response of ERROR for an 1 0 Logical Layer Request Default 1 b0 MSG
264. ror Management Extensions error reporting signals Table 5 15 Error Management Extensions Error Reporting Signals Signal Direction Description Asserted when an error is logged in the Logical Transport Layer Error Detect CSR Table 6 67 on page 6 43 and this error is enabled for reporting in the Logical Transport Layer Error Enable CSR Table 6 68 on page 6 44 If the LOG TRANS ERR IRQ EN bit in the Port logical transport error Output 0 Control CSR at offset 0 15 Table 6 15 on page 6 16 has the value of 1 b1 when this signal is raised the RapidlO II IP core asserts the Std reg mnt interrupt signal This signal remains asserted until the Logical Transport Layer Error Detect CSR is unlocked by user logic writing the value of 0 to the register This signal is available to report link status to the system host The signal is asserted when the Error Rate Failed Threshold trigger ERR_RATE FAILED THRESHOLD field of the Port 0 Error Rate Threshold CSR at offset 0x36C Table 6 82 on page 6 52 is enabled is non zero and this value is reached If the PORT FAIL IRQ EN bit in the Port 0 Control CSR at offset 0x15C Table 6 15 on page 6 16 has the value of 1 b1 when this signal is raised the RapidlO II IP core asserts the std reg mnt irginterrupt signal port failed Output This signal is available to report link status to the system host The signal is asserted when the Error Rate Degraded Threshold trigger
265. rror conditions are detected and if the corresponding Interrupt Enable bit is set the mnt mnt s signal is asserted Table 6 39 Maintenance Interrupt Offset 0x10080 Field Bits Access Function Default RSRV 31 7 RO Reserved 25 h0 PORT WRITE ERROR 6 RW1C Port write error 1 b0 A received port write packet was dropped A port write packet is dropped under the following conditions m A port write request packet is received but port write PACKET DROPPED 5 RWIC reception has not been enabled by setting bit ipo PORT WRITE ENABLE in the Rx Port Write Control register m A previously received port write has not been read out from the Rx Port Write register Indicates that the IP core has received a port write packet and PACKET STORED 4 RW1C thatthe payload can be retrieved using the Register Access 1 b0 Avalon MM slave interface RSRV 3 RO Reserved 1 b0 RSRV 2 RO Reserved 1 b0 If the address of an Avalon MM write transfer presented at the ETIE OUT OF BOUNDS 1 RWIC Maintenance Avalon MM slave interface does not fall within any T of the enabled Tx Maintenance Address translation windows d then it is considered out of bounds and this bit is set If the address of an Avalon MM read transfer presented at the Maintenance Avalon MM slave interface does not fall within any _ BEAD QUT ON BOUNDS 0 Ea of the enabled Tx Maintenance Address translation windows
266. rs Table 6 29 Destination Operations CAR Offset Ox1C 2 Part 2 of 2 Field Bits Access Comment Default WRITE 14 RO Processing element can support a write operation 3 SWRITE 13 RO Processing element can support a streaming write operation 3 NWRITE R 12 RO Processing element can support a write with response operation 3 Data Message 11 RO Processing element can support data message operation 1 b0 DOORBELL 10 RO Processing element can support a DOORBELL operation 4 COMP SWP 9 RO m element can support an ATOMIC compare and swap 10 TEST SWP 8 RO element can support ATOMIC test and swap 10 7 RO Processing element can support an ATOMIC increment operation 1 60 DEC 6 RO element can support an ATOMIC decrement 10 SET 5 RO Processing element can support an ATOMIC set operation 1 0 CLEAR 4 RO Processing element can support an ATOMIC clear operation 1 b0 ATM SWAP 3 RO Processing element can support an ATOMIC swap operation 1 b0 PORT WRITE 2 RO Processing element can support a port write operation 5 oH RE 1 0 RO Reserved for this implementation 2 b00 Notes to Table 6 29 1 If one of the Logical layers supported by the RapidlO II IP core is not selected the corresponding bits in the Destination Operations CAR are set to zero by default 2 The reset value of the Destination O
267. rs to determine if a specific I O write transaction has been issued or if a response has been received for any or all issued NWRITE R requests Defining the Input Output Avalon MM Slave Address Mapping Windows When you specify the value for Number of Tx address translation windows in the RapidIO II parameter editor you determine the number of address translation windows available for translating incoming Avalon MM read and write transactions to RapidIO read and write requests You must program the Input Output Slave Mapping Window registers to support the address ranges you wish to distinguish You can disable an address translation window that is available in your configuration but the maximum number of windows you can program is the number you specify in the RapidIO II parameter editor with the Number of Tx address translation windows value The RapidIO II IP core includes one set of Input Output Slave Mapping Window registers for each translation window The following registers define address translation window n A base register Input Output Slave Mapping Window Base Table 6 56 on page 6 38 m A mask register Input Output Slave Mapping Window n Mask Table 6 57 m Anoffset register Input Output Slave Mapping Window Offset Table 6 58 m A control register Input Output Slave Mapping Window n Control Table 6 59 The control register stores information the RapidIO II IP core uses to prepare the RapidIO packet header i
268. rts only variations that include a Transport Supports Physical layer only variations in the interface width interface presents data on a 128 bit wide interface and presents packet header information on a 115 bit wide interface PRY Only layer MegaWizard Plug In Manager flow arc or t An ST pase m ST Ran Tetras each Avalon ST g have a 32 bit wide interface in a 1x variation and a 64 bit wide interface in a 4x variation Header and data are transmitted or received on the same bus Avalon MM interface width 1 0 Logical layer Master and Slave modules each have a 128 bit wide Rx interface and a 128 bit wide Tx interface Doorbell and Maintenance modules each have one 32 bit wide Avalon MM interface in each direction February 2013 Altera Corporation 1 0 Logical layer Master and Slave modules in a 1x variation each have a 32 bit wide Rx interface and a 32 bit Tx interface and 1 0 Logical layer Master and Slave modules in a 4x variation each have a 64 bit wide Rx interface and a 64 bit Tx interface Doorbell and Maintenance modules each have one 32 bit wide Avalon MM interface in each direction in 1x and 4x variations RapidlO 11 MegaCore Function User Guide B 2 Appendix B Differences Between RapidlO 11 MegaCore Function and RapidlO MegaCore Function v12 1 Table B 1 Major Differences Between the RapidlO Il IP Core v12 1 and the 10 IP Core v12 1 Part 2 of 3 P
269. ruary 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 4 8 Chapter 4 Functional Description Logical Layer Interfaces If your RapidIO ILIP core variation includes a Maintenance module a remote host can access the RapidIO II IP core registers by sending MAINTENANCE transactions targeted to this local RapidIO II IP core If the transaction is a read or write to an address in the IP core register address range the RapidIO II IP core routes the transaction to the appropriate register internally If the transaction is a read or write to an address outside the address ranges of the Logical layer modules instantiated in the RapidIO II IP core the IP core routes the transaction to user logic through the Maintenance master interface For information about the RapidIO II IP core registers refer to Chapter 6 Software Interface Register Access Interface Signals Table 4 4 lists the signals in the Register Access interface Tahle 4 4 Register Access Avalon MM Slave Interface Signals Direction Description Register Access slave wait request The RapidlO II IP core uses this eat omni waitreguest signal to stall the requestor on the interconnect ext mnt read Input Register Access slave read request ext mnt write Input Register Access slave write request ext mnt address 23 2 Input Register Access slave address bus ext mnt writedata 31 0 Input Register Access slave write data bus e
270. s m Response packets with ERROR status Standard Error Management Registers The following two standard defined error types can be declared by the I O Avalon MM master module The corresponding bits are then set and the required packet information is captured in the appropriate error management registers RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 4 Functional Description 4 11 Error Detection and Management m Unsupported Transaction is declared when a request packet carries a transaction type that is not supported in the Destination Operations CAR Table 6 29 on page 6 29 whether an ATOMIC transaction type a reserved transaction type or an implementation defined transaction type m Illegal Transaction Decode is declared when a request packet for a supported transaction is too short or if it contains illegal values in some of its fields such as in these examples m Request packet with priority 3 m NWRITE NWRITE_R or SWRITE request packets without payload m NWRITE or NWRITE_R request packets with reserved wrsize and wdptr combination m NWRITE NWRITE_R SWRITE or NREAD request packets for which the address does not match any enabled address mapping window m NREAD request packet with payload m NREAD request with rdsize that is not an integral number of transfers on all byte lanes The Avalon MM interface specification requires that all byte lanes be enabled for read transfer
271. s The RapidlO interrupt conditions with the 11 s signal IP core generates all Doorbell module specific interrupt conditions with the drbe1l s signal byteenable Read transactions the 1 0 Logical layer Master and Slave interfaces have no associated byteenable value The byteenable value is assumed to be all ones User logic is responsible for enforcing any required byte masking in the read data it receives and is required to return full 32 or 64 bit words of read data Transport layer Tx scheduling The Transport layer implements a modified round robin scheduling algorithm to determine the next packet to accept among those available from the Avalon ST pass throuh interface and the Logical layer module Status information from the Physical layer determines whether the round robin algorithm considers all available packets or considers only available packets with a priority field value above a specified threshold This threshold can also be set to allow no packets through providing a temporary backpressure mechanism for the Physical layer to control input from the Transport layer The Transport layer implements a round robin scheduling algorithm to determine the next packet to accept among those available from the Avalon ST pass through interface and the Logical layer modules This algorithm does not consider the priority field values of the packets Link Request Reset Device on Fatal Errors par
272. s Therefore Read Avalon MM master modules do not have a byteenable signal m Payload size does not match the size indicated by the rdsize or wrsize and wdptr fields Response Packets with ERROR Status An ERROR response packet is sent for NREAD and NWRITE R and Type 5 ATOMIC request packets that cause an Illegal Transaction Decode error to be declared An ERROR response packet is also sent for NREAD requests if the iom rd wr readresponse input signal is asserted through the final cycle of the Avalon MM read transfer Avalon ST Pass Through Interface Packets with valid CRCs that are not recognized as being targeted to one of the implemented Logical layer modules are passed to the Avalon ST pass through interface for processing by user logic The RapidIO II IP core also provides hooks for user logic to report any error detected by a user implemented Logical layer module attached to the Avalon ST pass through interface February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 4 12 Chapter 4 Functional Description Error Detection and Management RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide RYN 5 Signals This chapter lists the RapidIO II IP core signals Signals are listed with their widths In this context the n in n 0 is the number of lanes minus one so that signal n 0 has one bit for each lane Global Signals Table 5 1 Clock Signals Signal Dir
273. s cleared only when 1 b0 software writes the value of 1 to it Input port is stopped due to a transmission error The port is in the Input Error Stop state The following conditions cause the input port to transition to this state m Cancellation of a packet by using the restart from retry control symbol m Invalid character or valid character that does not belong in an idle sequence m Single bit transmission errors m Any of the following link protocol violations Unexpected packet accepted Unexpected packet retry Unexpected packet not accepted packet Acknowledgment control symbol with an unexpected packet ackID INCBBR STOP 8 RE Link time out while waiting for an acknowledgment control symbol ie m Corrupted control symbols that is CRC violations on the symbol m Any of the following Packet Errors Unexpected ackID value Incorrect CRC value Invalid characters or valid nondata characters Max data payload violations The recovery mechanism consists of these steps 1 Issue a packet not accepted control symbol 2 Wait for Link request input status control symbol 3 Send 1ink response control symbol RSRV 7 5 RO Reserved 3 h0 This register is not implemented and is reserved The RapidlO II IP core PWRITE PEND 4 RO does not automatically issue Port write requests so this bit always 1 b0 has the value of zero PORT UNAVAIL 3 RO Indicates whether the port is available This port is always available so 1 b0 RapidlO 11 MegaCor
274. s packet February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 4 42 Chapter 4 Functional Description Logical Layer Interfaces Table 4 20 Maintenance Read Request Transmit Example RapidlO Packet Fields Part 2 of 2 Field Value Comment The IP core assigns to this field the value LARGE DESTINATION ID DESTINATION based on the values programmed in the LARGE DESTINATION ID and DESTINATION ID fields of the Tx destinationID 15 0 Maintenance Mapping Window n Control register Table 6 44 on page 6 35 for the matching address translation window n Refer to Defining the Maintenance Address Translation Windows on page 4 34 for matching details The IP core assigns to this field the value programmed in the Large base devicelID field of the Base Device ID register offset 0x60 ttype 3 0 4 b0000 The value of 0 indicates a MAINTENANCE read request The size and wdptr values encode the maximum size of the payload field In MAINTENANCE transactions the value of wrsize is always 4 b1000 which sourceID 15 0 rdsize 3 0 4 b1000 decodes to a value of 4 bytes For encoding details refer to Table 4 4 in Part 1 Input Output Logical Specification of the RapidlO Interconnect Specification Revision 2 2 The RapidlO II IP core generates the source transaction ID value internally to SrcTID 7 0 track the transaction response The value depends on the current state of the RapidlO II IP c
275. se Send Example at L INI LJ LT L1 gen rx hd ready Lp LLL gen rx hd valid gen rx hd data 114 0 0052DDDDAAAA4CBB765432100000 gen rx pd valid gen Ix pd startofpacket gen rx pd endofpacket gen rx pd data 127 0 gen rx pd empty 2 0 gen tx ready gen tx valid gen tx startofpacke L 009DAAAADDDD80BB001 1223344556677 85599 123458789 FEDCBA98765432100000000000000000 a gen tx endofpacket gen tx data 127 0 gen tx empty 8 0 RR ARR m m ee Le Le Le I gen tx packet size 8 0 028 The following two sections describe the behavior shown in Figure 4 22 m NREAD Request Transaction m NREAD Response Transaction February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 4 58 Chapter 4 Functional Description Logical Layer Interfaces NREAD Request Transaction The NREAD request requires a single clock cycle During this cycle user logic asserts gen_rx_hd_ready to indicate it is ready to sample data In the same cycle the IP core asserts gen rx hd valid Because both gen tx hd ready and gen tx hd validare asserted the current cycle is an Avalon ST ready cycle on the header Avalon ST interface The IP core provides valid header information on gen rx hd data for the user logic to sample The IP core does not assert g
276. se packet and presents the response packet to the Transport layer for transmission on the RapidIO link Refer to Avalon Interface Specifications for details on the supported transfers The Maintenance module only supports single 32 bit word transfers that is rdsize and wrsize 4 b1000 If the RapidIO II IP core receives a MAINTENANCE request on the RapidlO link with a different value in this field the IP core sends an error response packet on the RapidIO link and no transfer occurs The RapidIO II IP core uses the wdptr and config offset values in the incoming RapidIO request packet to generate the Avalon MM address in the transaction it presents on the Maintenance module master interface using the following formula usr mnt address 8 h00 config offset wdptr 2 b00 The IP core presents the data in the RapidIO transaction payload field on the usr mnt writedata 31 0 bus Handling Port Write Transactions The RapidIO II IP core supports RapidIO MAINTENANCE port write transactions However these transactions do not appear on the Maintenance Avalon MM interface User logic controls the processing of port write transactions by programming the registers that are described in the following sections m Transmit Port Write Registers on page 6 36 m Receive Port Write Registers on page 6 36 Your system controls the transmission of port write transactions on the RapidIO link by programming RapidIO IP core transmit port write
277. ser logic asserts gen tx valid Because both gen tx ready and gen tx valid asserted this clock cycle is an Avalon ST ready cycle The user logic provides valid data on gen tx data for the IP core to sample and asserts gen tx startofpacket to indicate the current value of gen tx data is the initial piece of the current packet the start of packet On gen tx packet size user logic reports the full length of the packet is 0x28 which is decimal 40 because the packet comprises eight bytes of header and 32 bytes of payload data RapidlO II MegaCore Function User Guide February 2013 Altera Corporation Chapter 4 Functional Description 4 59 The user logic provides the 32 byte payload and 8 byte header on the same bus gen tx data 127 0 Transferring these 40 bytes of information requires three clock cycles During all of these cycles the IP core holds gen tx ready high and user logic holds gen tx valid high indicating the cycles are all Avalon ST ready cycles In the second cycle user logic holds gen tx startofpacket and gen tx endofpacket low because the information on gen tx data is neither start of packet nor end of packet data In the third clock cycle user logic asserts gen tx endofpacket and sets gen tx empty to the value of 0x8 to indicate that eight bytes of the data in the current clock cycle are invalid in other words only the initial eight sixteen minus eight bytes of data available on gen tx data in the curre
278. sserting the mnt_s_writerequest signal until it is ready to receive the write transaction In the example the IP core throttles the incoming transaction for five clock cycles because it requires six clock cycles to process each write transaction RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 4 Functional Description Logical Layer Interfaces 4 39 The user logic maintains the values on the mnt write mnt s writedata and mnt s address signals until one clock cycle after the IP core deasserts the mnt s waitrequest signal as required by the Avalon MM specification In the following clock cycle user logic sends the next write request which the IP core also throttles for five clock cycles The process repeats for an additional two write requests The RapidIO II IP core converts these write transactions to RapidIO MAINTENANCE request packets Table 4 17 lists the fields in the corresponding RapidIO packets Table 4 17 Maintenance Write Request Transmit Example RapidlO Packet Fields Field Value Comment Value is written by the Physical layer before the packet is transmitted on the ae 6 h00 RapidlO link vc 0 The RapidlO II IP core supports only VCO CRF 0 The IP core assigns to this field the value programmed in the PRIORITY field of 2 b00 the Tx Maintenance Mapping Window n Control register Table 6 44 on page 6 35 for the matching address tra
279. ssociation website at www rapidio org Supports 8 bit or 16 bit device IDs Supports incoming and outgoing multi cast events Provides a 128 bit wide Avalon Streaming Avalon ST pass through interface for fully integrated implementation of custom user logic Physical layer features m 1x 2x 4x serial with integrated transceivers m Fallback to 1x from 4x and 2x modes m Allfive standard serial data rates supported 1 25 2 5 3 125 5 0 and 6 25 gigabaud Gbaud m Long control symbol m IDLE2 idle sequence m Extraction and insertion of command and status CS field m Support for software control of local and link partner transmitter emphasis m Insertion of clock compensation sequences m Receive transmit packet buffering scrambling descrambling flow control error detection and recovery packet assembly and packet delineation m Automatic freeing of resources used by acknowledged packets m Automatic retransmission of retried packets m Scheduling of transmission based on priority m Software support for ackID synchronization m Virtual channel VC 0 support m Reliable traffic RT support m Critical request flow CRF support February 2013 Altera Corporation Chapter 1 About The RapidlO Il MegaCore Function 1 3 Features m Transport layer features Supports multiple Logical layer modules Supports an Avalon Streaming Avalon ST pass through interface for custom implementation of capabilities such as data streaming and mess
280. st significant bits have the value 2 b01 matches window 0 The RapidIO transaction corresponding to the Avalon MM operation has a DESTINATION_ID value of 0x55 This value corresponds to processing endpoint 0 February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 4 26 Chapter 4 Functional Description Logical Layer Interfaces Figure 4 11 shows address translation window 0 Figure 4 11 Translation Window 0 31 30 29 32 1 Avalon Address 31 0 01 26 h3555999 o Mask register 0x10404 1 000000000000000000 00 Base register 0x10400 0 1 Don t Care EE 1 R n Offset register 0x10408 O 0 0 1 Don t Care J vy RapidlO Address 33 0 o o o 1 26 h3555999 23 16 Control register 0x1040C 0x55 Destination ID Translation Window 1 An Avalon MM address in which the two most significant bits have a value of 2 b10 matches window 1 The RapidIO transaction corresponding to the Avalon MM operation has a destination ID value of 0xAA This value corresponds to processing endpoint 1 Figure 4 12 shows address translation window 1 Figure 4 12 Translation Window 1 31 30 29 32 1 0 Avalon Address 31 0 1 0 26 3555999 Base register 0x10410 1 0 Don t Care mE Mask register 0x10414 1 1 000000000000000000
281. system clock Figure 4 1 shows a circuit that ensures these conditions Figure 4 1 Circuit to Ensure Synchronous Deassertion of rst n reset n RapidlO II IP Core P Sys clk In systems generated by Osys this circuit is generated automatically However if your RapidIO core variation is not generated by Osys you must implement logic to ensure the minimal hold time and synchronous deassertion of the rst n input signal to the RapidIO II IP core The assertion of rst n causes the whole RapidIO II IP core to reset The requirement that reset be asserted with rst nensures that the PHY IP core resets with the RapidIO IL IP core User logic must assert the Transceiver PHY Reset Controller IP core reset signal with rst n However each signal is deasserted synchronously with its corresponding clock Figure 4 2 shows a circuit that ensures these conditions In this figure clock is the Transceiver PHY Reset Controller IP core input clock Figure 4 2 Circuit to Also Ensure Synchronous Assertion of reset with rst n clock e _ V gt gt D Q D Q gt reset rst rst Transceiver PHY Reset RapidlO II rst Controller IP Core IP Core _ ret n rst n D Q D Q P rst_n gt gt A sys_clk e February 2013 Altera Corporation RapidlO 11 MegaCore Functi
282. t Layer Error Detect CSR Table 6 67 on page 6 43 and returns an ERROR response Table 4 7 lists the write request conversions the RapidIO II IP core performs for RapidlO write request packets with wrsize value less than 4 b1100 Table 4 7 Avalon MM 1 0 Master Write Transaction Burstcount and Byteenable Part 1 of 3 RapidlO Field Values Avalon MM Signal Values wrsize wdptr address 0 4 1 1 bx Burstcount Byteenable 16 bxxxx_XXXX_XXXX_XXXX 0 0 1 0000 0000 1000 0000 0000 1 1 1000 0000 0000 0000 1 0 1 0000 0000 0000 1000 1 1 0000 1000 0000 0000 February 2013 Altera Corporation RapidlO II MegaCore Function User Guide 4 16 Chapter 4 Functional Description Logical Layer Interfaces Table 4 7 Avalon MM 1 0 Master Write Transaction Burstcount and Byteenable Part 2 of 3 1111 1110 0000 0000 RapidlO Field Values Avalon MM Signal Values ias e en Burstcount Byteenahle 16 nox 0x ox 0 0 1 0000 0000 0100 0000 0001 1 1 0100 0000 0000 0000 1 0 1 0000 0000 0000 0100 1 1 0000 0100 0000 0000 0 0 1 0000_0000_0010_0000 0010 1 1 0010_0000_0000_0000 1 0 1 0000 0000 0000 0010 1 1 0000 0010 0000 0000 0 0 1 0000_0000_0001_0000 0011 1 1 0001 0000 0000 0000 1 0 1 0000 0000 0000 0001 1 1 0000 0001 0000 0000 0 0 1 0000
283. t device control symbols send link request reset device Input Await asssertion of the sent link request reset device signal before you toggle this signal again If you toggle this signal before you see the sent link request reset device confirmation from the previous change of value the RapidlO II IP core behavior is undefined Asserted for one sys clk cycle when four valid link request reset device control symbols in a row are received Indicates the RapidlO II IP core has queued a series of five link request reset device control symbols for transmission link req reset device received Output sent link request reset device Output Transceiver Signals Table 5 7 lists the transceiver signals These signals are connected directly to the transceiver block In some cases these signals must be shared by multiple transceiver blocks that are implemented in the same device February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide Table 5 7 Transceiver Signals Chapter 5 Signals Physical Layer Signals Signal Direction Description Driven from an external dynamic reconfiguration block Supports the selection of multiple transceiver channels for dynamic reconfiguration Note that not using a dynamic reconfiguration block that enables offset cancellation results in a non functional hardware design The width of this bus is C 1 x 7
284. tains the Altera MegaCore IP Library common Contains shared components altera rapidio2 Contains the RapidlO Il MegaCore function files You can use Altera s free OpenCore Plus evaluation feature to evaluate the IP core in simulation and in hardware before you purchase a license You must purchase a license for the IP core only when you are satisfied with its functionality and performance and you want to take your design to production After you purchase a license for the RapidIO II IP core you can request a license file from the Altera website at www altera com licensing and install it on your computer When you request a license file Altera emails you a license dat file If you do not have internet access contact your local Altera representative OpenCore Plus Evaluation With the Altera free OpenCore Plus evaluation feature you can perform the following actions m Simulate the behavior of a megafunction Altera IP core or AMPP5M megafunction in your system using the Quartus II software and Altera supported Verilog HDL simulators m Verify the functionality of your design and evaluate its size and speed quickly and easily m Generate time limited device programming files for designs that include IP cores m Program a device and verify your design in hardware RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 1 About The RapidlO Il MegaCore Function 1 9 Installa
285. ter Settings Error Management Registers Settings The RapidIO II IP core Error Management registers are described in Error Management Registers on page 6 41 RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide RA 4 Functional Description Interfaces The Altera RapidIO II IP core supports the following interfaces m Avalon Memory Mapped Avalon MM Master and Slave Interfaces m Avalon Streaming Avalon ST Interface m RapidlO Interface Avalon Memory Mapped Avalon MM Master and Slave Interfaces The Avalon MM master and slave interfaces execute transfers between the RapidIO II IP core and the system interconnect The system interconnect allows you to use the Qsys system integration tool to connect any master peripheral to any slave peripheral without detailed knowledge of either the master or slave interface The RapidIO II IP core implements both Avalon MM master and Avalon MM slave interfaces For more information about the Avalon MM interface refer to Avalon Interface Specifications Avalon MM Interface Byte Ordering The RapidIO protocol uses big endian byte ordering whereas Avalon MM interfaces use little endian byte ordering Table 4 1 shows the byte ordering for the 64 bit Avalon MM interface and the RapidIO interface No byte or bit order swaps occur between the 64 bit Avalon MM protocol and RapidIO protocol only byte and bit number changes For example RapidIO Byte0 is Av
286. terface Byte Ordering 60 6 eee 4 1 RapidlO II MegaCore Function February 2013 Altera Corporation User Guide Contents Avalon Streaming Avalon ST Interface sss nn 4 2 RapidIOInteriace 4 2 Clocking and Reset Structure ee ee eth ehh e ehe 4 3 Avalon oy Stem Clock teen Bae nea Gee ce trae ee CU 4 3 Reterence Clock e ERE ceed ye t eut bg an tees etie ei ger 4 3 Recovered Data Clock erone testis Uma ties tee aiebat 4 3 Clock Rate Relationships in the RapidIO IP Core 0 0 cece eens 4 3 Clock Domains in Your Qsys System 0 0000 e eee 4 4 R set for RapidlO IL IP Cores iiec se Ra eee 3 m bes ee se ne Ew noris 4 4 Logical Layer Interfaces MEE SEE REC ad bea ead ree pea ei 4 6 Register Access Interface kat E eD eE NUR becouse Peake Ya pta 4 7 Non Doorbell Register Access Operations 000 4 7 Register Access Interface Signals eens 4 8 Input Output Logical Layer Modules siss rssir srce renisr ciee kikita tenani nee eens 4 9 Input Output Avalon MM Master Module e 4 9 RapidIO Packet Data wdptr and Data Size Encoding in Avalon MM Transactions 4 13 Input Output Avalon MM Master Module Timing Diagrams 4 17 Input Output Avalon MM Slave Mo
287. tes only support bursts that are multiples of a double word multiple of 8 bytes the testbench cycles from 8 to MAX WRITTEN BYTES in steps of 8 bytes The ios 128 rd wr master bfm read write cmd task generates and checks the streaming write transaction At the sister rio module the SWRITE request packets are received and translated into Avalon MM transactions that are presented across the Input Output master Avalon MM interface The testbench calls the task read write data ofthe sister iom128 rd wr slave bfm to capture the written data The written data is then checked against the expected value by running an expect 1 task After completing the SWRITE tests the testbench performs NREAD operations NREAD Transactions The next set of transactions tested are NREADs The DUT sends a group of NREAD transactions to the sister rio module by cycling the read burst size from four to five in increments of 16 bytes For each iteration the ios 128 rd wr master bfm read write cmd and read data tasks are called The task performs the read request packets across the I O Avalon MM Slave Read interface The read transaction across the Avalon MM interface is translated into a RapidIO NREAD request packets The NREAD request packets are received by the DUT and are translated into Avalon MM read transactions that are presented across the sister rio module s I O master Avalon MM interface The sister iom128 rd wr slave bfm module checks the read op
288. the transceiver s PLL You specify the reference clock frequency in the RapidIO II parameter editor when you create the RapidIO II IP core instance The ability to program the frequency of the input reference clock allows you to use an existing clock in your system as the reference clock for the RapidIO II IP core This reference clock can have any of a set of frequencies that the PLL in the transceiver can convert to the required internal clock speed for the RapidIO II IP core baud rate The choices available to you for this frequency are determined by the baud rate and target device family For information about this clock including recommended frequency range refer to the Native PHY IP Core and Altera Transceiver Reconfiguration Controller chapters of the Altera Transceiver PHY IP Core User Guide For more information about using high speed transceiver blocks refer to the relevant device handbook Recovered Data Clock The clock and data recovery block CDR in the transceiver recovers this clock rx clkout from the incoming RapidIO data The RapidIO II IP core provides this output clock as a convenience You can use it to source a system wide clock with a 0 PPM frequency difference from the clock used to transmit the incoming data Clock Rate Relationships the RapidlO 1 IP Core The serial RapidIO v2 2 specification specifies baud rates of 1 25 2 5 3 125 5 0 and 6 25 Gbaud February 2013 Altera Corporation RapidlO 11 MegaCo
289. the user on the I O Logical layer Avalon MM slave interface Presents the composed packet to the Transport layer for transmission on the RapidIO link For each read response from the Transport layer removes the original request entry from the Pending Reads buffer and uses the packet s payload to complete the read transaction by sending the read data on the Avalon MM slave interface For each write response from the Transport layer removes the original request entry from the Pending Writes buffer At any time the I O Logical layer Slave module can maintain a maximum of eight outstanding read requests and a maximum of eight outstanding write requests The module asserts the ios rd wr waitrequest signalto throttle incoming requests above the limit The RapidIO II IP core performs the following actions in response to each read request transaction the I O Logical layer Slave module processes If the IP core receives a read response packet on the RapidIO link the read operation was successful After the I O Logical layer Slave module receives the response packet from the Transport layer it passes the read response and data from the Pending Reads buffer back through the Avalon MM slave interface If the remote processing element is busy the RapidIO II IP core resends the request packet If an error or time out occurs the I O Logical layer Slave module asserts the ios rd wr readresponse signal on the Avalon MM slave interface and captures so
290. tion Default Indicates the type of information logged The RapidlO II IP core supports only the following valid values for this field INFO_TYPE 31 29 RO 3 b000 Packet 3 h0 3 b011 Long control symbol The encoded value of the bit in the Port 0 Error Detect CSR ERROR TYPE 28 24 RO that describes the error captured in the Port 0 5 h0 Packet Control Symbol Capture 0 3 CSRs The RapidlO II IP core uses this field as recommended in the RapidlO v2 2 specification If the value of the INFo_TyPE field is 3 b000 indicating a packet this field captures the control bits of the first 16 packet IMPL DEPENDENT 23 8 RO characters 8 h0 If the value of the TYPE field is 3 b011 indicating a long control symbol bits 23 16 of this field capture the eight control bits of the delimited long control symbol RSRV 7 1 RO Reserved 16 h0 Indicates that the Port 0 Packet Control Symbol Capture 0 3 CSRs and the other bits in the Port 0 Attributes CAPTURE VALID INFO 0 RW Capture CSR contain valid information and are locked To reset 16 h0 this bit and unlock the other fields in this register you must write the value of 1 b0 to the CAPTURE VALID INFO bit Table 6 77 Port 0 Packet Control Symbol Capture 0 CSR Offset 0x34C Field Bits Access Function Default Contains the first four bytes of the packet or long control symbol CAPTURE 0 31 0 RO based on the INFO TYPE field of the Port 0 Attributes 32 h0 Capture CSR
291. tion and Licensing OpenCore Plus Time Out Behavior OpenCore Plus hardware evaluation supports the following two operation modes m Untethered the design runs for a limited time m Tethered requires a connection between your board and the host computer If tethered mode is supported by all megafunctions in a design the device can operate for a longer time or indefinitely All megafunctions in a device time out simultaneously when the most restrictive evaluation time is reached If there is more than one megafunction in a design a specific megafunction s time out behavior may be masked by the time out behavior of the other megafunctions 5 For Altera IP cores the untethered time out is 1 hour the tethered time out value is indefinite After the hardware evaluation time expires the RapidIO II IP core behaves as if its reset signal were held asserted and your design stops working For Information About Refer To Installation and licensing Altera Software Installation and Licensing Open Core Plus AN 320 OpenCore Plus Evaluation of Megafunctions February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 1 10 Chapter 1 About The RapidlO Il MegaCore Function Installation and Licensing RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide N DTE BAN 2 Getting Started Design Flows You can customize the RapidIO II IP core to support a wide variety of applications Y
292. tion feature the test first checks that the PENDING NWRITE RS field of the Input Output Slave Pending NWRITE R Transactions register has value 0 before setting the Input Output Slave Mapping Window 0 Control register and starting the sequence of NWRITE R transactions The testbench generates a predetermined series of burst writes across the Input Output Avalon MM slave module s Avalon MM write interface on the DUT These write bursts are each converted into NWRITE R request packets sent over the RapidIO Serial interface The testbench cycles from 16 to 256 in steps of 8 bytes Two tasks are invoked to carry out the burst writes rw addr data and rw data The rw addr data task initiates the burst and the rw data task completes the burst At the sister rio module the NWRITE R request packets are received and presented across the I O master Avalon MM interface as write transactions The testbench calls the sister iom128 rd wr slave bfm read write data task to capture the written data The written data is checked against the expected value February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide Chapter 7 Testbench Testbench Sequence NWRITE Transactions To perform NWRITE operations one register in the IP core must be reconfigured as shown in Table 7 4 With these settings any write operation presented across the Input Output Avalon MM slave interface is translated into a RapidIO NWRITE transaction Table 7 4 N
293. tional Description Physical Layer CRC Checking and Removal The Physical layer checks the CRC bits in an incoming RapidIO packet and flags CRC and packet size errors It strips all CRC bits and padding bytes from the data it sends to the Transport layer Low Level Interface Transmitter The transmitter in the low level interface transmits output to the serial RapidIO interface This module performs the following tasks m Assembles packets and control symbols into a proper output format m Generates the 13 bit CRC to cover the 35 bit symbol and appends the CRC at the end of the symbol m Transmits an IDLE2 sequence during port initialization and when no packets or control symbols are available to transmit Transmits outgoing multicast event control symbols in response to user requests Transmits status control symbols and the rate compensation sequence periodically as required by the RapidIO specification The low level transmitter block creates and transmits outgoing multicast event control symbols Each time the multicast event txinput signal changes value this block inserts a multicast event control symbol in the outgoing bit stream as soon as possible The internal transmitters are turned off while the initialization state machine is in the SILENT state This behavior causes the link partner to detect the need to reinitialize the RapidIO link The transmitter transceiver is an embedded Native PHY IP core The Physical laye
294. tom megafunction variation 4 Under Installed Plug Ins select RapidIO II and click Add The RapidIO II parameter editor appears To select the RapidIO II IP core click Installed Plug Ins gt Interfaces gt RapidIO gt RapidIO II v lt version gt 5 Specify the parameters on all tabs in the RapidIO II parameter editor For details about these parameters refer to Chapter 3 Parameter Settings 6 Click Finish to generate the IP core and supporting files including simulation models You may have to wait several minutes for file generation to complete 7 If you generate the RapidIO II IP core instance in a Quartus II project you are prompted to add the Quartus IL IP File qip to the current Quartus II project You can also turn on Automatically add Quartus II IP Files to all projects RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 2 Getting Started 2 3 MegaWizard Plug In Manager Design Flow The qip is generated by the parameter editor and contains information about the generated IP core In most cases the qip contains all of the necessary assignments and information required to process the IP core or system in the Quartus II compiler The MegaWizard Plug In Manager generates a single qip for each IP core 8 Click Exit to close the MegaWizard Plug In Manager You can now integrate your custom IP core variation in your design simulate and compile When you integrate your R
295. trequest Output Doorbell module wait request drbell s write Input Doorbell module write request drbell s read Input Doorbell module read request drbell s address 3 0 Input Doorbell module address bus drbell s writedata 31 0 Input Doorbell module write data bus drbell s readdata 31 0 Output Doorbell module read data bus drbell s irq Output Doorbell module interrupt 5 Generating a Doorbell Message To generate a DOORBELL request packet on the RapidIO serial interface follow these steps using the set of registers described in Doorbell Message Registers on page 6 52 1 Optionally enable interrupts by writing the value 1 to the appropriate bit of the Doorbell Interrupt Enable register Table 6 92 2 Optionally enable confirmation of successful outbound messages by writing 1 to the COMPLETED bit of the Tx Doorbell Status Control register Table 6 91 3 Setup the PRIORITY field of the Tx Doorbell Control register Table 6 86 4 Write the Tx Doorbell register Table 6 87 to set up the DESTINATION ID and Information fields of the generated DOORBELL packet format Before writing to the Tx Doorbell register you must be certain that the Doorbell module has available space to accept the write data Ensuring sufficient space exists avoids a waitrequest signal assertion due to a full FIFO When the waitrequest signal is asserted you cannot perform other transactions on the DOORBELL Avalon MM slave port unti
296. type not supported by the selected Logical layers or have a transaction ID outside the range used by the selected Logical layers For more information refer to Transport Layer on page 4 59 transport rx packet dropped Output February 2013 Altera Corporation RapidlO 11 MegaCore Function User Guide 5 8 Chapter 5 Signals Error Management Extension Signals Error Management Extension Signals Table 5 13 to Table 5 15 describe the signals that are added when you enable the Error Management Extensions registers in the RapidIO II parameter editor All of these signals are clocked in the sys c1k clock domain Table 5 13 Error Setting Signals set Signal Direction message error response set Input gsm error response set Input message format error response set Input illegal transaction decode set Input illegal transaction target error Aic Input message request timeout set Input Slave packet response timeout set Input unsolicited response set Input unsupported transaction set Input Hd ME E Input open existing data streaming Input context set long data streaming segment set Input short data streaming segment set Input data streaming pdu length error Input Description Support user logic in setting the corresponding fields in the Logical Transport Layer Error Detect CSR at offset 0x308 For information about the register fields these signals can set refer to T
297. ute CSRs at offsets 0x70 0x74 and 0x78 2 The default value is set in the RapidlO Il parameter editor RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 6 Software Interface 6 31 Transport and Logical Layer Registers Table 6 31 Data Streaming Information CAR Offset 0x3C 1 Field Bits Access Function Default Indicates the maximum PDU size that this destination end point supports Unit is bytes MaxPDU 31 16 RO 2 Indicates the number of segmentation contexts that this destination end point supports 16 h0000 65536 segmentation contexts SegSupport 15 0 RO 16 h0001 1 segmentation context 2 16 h0002 2 segmentation contexts 16 hFFFF 65535 segmentation contexts Note to Table 6 31 1 Userlogic must implement the functionality and registers to support data streaming configuration The values in this register do not affect the IP core 2 The default value is set in the RapidlO Il parameter editor Command and Status Registers CSRs Table 6 32 through Table 6 38 describe the command and status registers Table 6 32 Data Streaming Logical Layer Control CSR Offset 0x48 Part 1 of 2 Field Bits Access Function Default TM types supported This field indicates the TM types that the RapidlO II IP core variation supports The following values are valid 4 b1000 Supports basic type SUERORT MO
298. ved 47 0 47 0 ttype 3 0 63 60 status 3 0 Or size 3 0 59 56 transactionID 7 0 55 48 8 hop count 7 0 47 40 config offset 20 0 39 19 wdptr 18 Reserved 17 0 17 0 cos 7 0 63 56 S 55 E 54 xtype 2 0 53 51 xh 50 e 49 9 P 48 streamID 15 0 47 32 TM OP 3 0 31 28 reserve 27 wildcard 2 0 26 24 mask 7 0 23 16 parameter1 7 0 15 8 parameter2 7 0 7 0 RapidlO II MegaCore Function User Guide February 2013 Altera Corporation Chapter 4 Functional Description Logical Layer Interfaces 4 53 Tahle 4 28 specific header Fields in gen rx hd data Bus Part 2 of 2 ftype Field specific header Bits 3 0 63 60 status 3 0 59 56 transactionID 7 0 55 48 10 info msb 7 0 47 40 info lsb 7 0 39 32 crc 15 0 31 16 Reserved 15 0 15 0 msglen 3 0 63 60 ssize 3 0 59 56 44 letter 1 0 55 54 mbox 1 0 53 52 msgseg 3 0 Or xmbox 3 0 51 48 Reserved 47 0 47 0 ttype 3 0 63 60 13 status 3 0 59 56 transactionID 7 0 Or target info 7 0 55 48 Reserved 47 0 47 0 Pass Through Interface Usage Examples This section contains examples of communication on the RapidIO II IP core Avalon ST pass through interface Refer to Transaction ID Ranges on page 4 48 and Receiver on page 4 60 for a description of the RapidIO ITIP core variations in which these examples ar
299. x Maintenance Window 0 Control register 0x1010C to 0x0 To enable an all encompassing address mapping window for the maintenance module write 1 b1 to the WEN field bit 2 of the Tx Maintenance Window 0 Mask register 0x10104 These register settings allow one RapidIO IP core to remotely access the other RapidIO IP core To access the registers the system requires an Avalon MM master for example a Nios II processor The Avalon MM master can program these registers You can use the Osys system integration tool available with the Quartus II software to rapidly and easily build and evaluate your RapidIO system February 2013 Altera Corporation RapidlO II MegaCore Function User Guide A 2 Appendix A Initialization Sequence St For more information about initializing a RapidIO system refer to Fuller Sam 2005 RapidIO The Embedded System Interconnect John Wiley amp Sons Ltd Chapter 10 RapidlO Bringup and Initialization Programming RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide RA B Differences Between RapidlO Il MegaCore Function and RapidlO MegaCore Function v12 1 This appendix lists the basic differences between the Altera RapidIO MegaCore function a product available through many previous Altera software releases and the new RapidIO II MegaCore function in the 12 1 software release The comparison is defined relative to the version of the RapidIO MegaCore function
300. xt mnt readdata 31 0 Output Register Access slave read data bus ext mnt readdetevalid Output sten pipelined read transfers on tts rte Register Access read error which indicates that the read transfer did ext mnt readresponse Output not complete successfully This signal is valid only when the ext mnt readdatavalid signal is asserted std reg mnt irq Standard registers interrupt request This interrupt signal is associated with the error conditions registered in the Command and Output Status Registers CSRs and the Error Management Extensions registers Refer to Command and Status Registers CSRs on page 6 31 and Error Management Registers on page 6 41 io m mnt irq 1 0 Logical Layer Avalon MM Master module interrupt signal This interrupt is associated with the conditions registered in the Input Output Master Interrupt register at offset Ox103DC Refer to Table 6 54 on page 6 38 Output io s mnt irq 1 0 Logical Layer Avalon MM Slave module interrupt signal This interrupt signal is associated with the conditions registered in the Input Output Slave Interrupt register at offset 0x10500 Refer to Table 6 60 on page 6 40 Output mnt mnt s irq Maintenance slave interrupt signal This interrupt signal is associated with the conditions registered in the Maintenance Interrupt register at offset 0x10080 Refer to Table 6 39 on page 6 34 Output RapidlO 11 MegaCore Function February
301. y 2013 Altera Corporation RapidlO II MegaCore Function User Guide 2 6 Chapter 2 Getting Started Qsys Design Flow 5 Click Finish to complete the RapidIO II IP core instance and add it to the Osys system Completing the Qsys System To complete the Osys system follow these steps 1 Add and parameterize any additional components 2 Connect the components using the Connection panel on the System Contents tab 3 If some signals are not displayed click the Filter icon to display the Filters dialog box In the Filter list click All Interfaces Alternatively if you right click in the System Contents tab a Filter menu option appears 57 You must add a dynamic reconfiguration block Transceiver Reconfiguration Controller to your design using the MegaWizard Plug In Manager or Qsys and connect it to the RapidIO II IP core PHY IP reconfiguration signals This block supports offset cancellation The design compiles without the Transceiver Reconfiguration Controller but it cannot function correctly in hardware An informational message in the RapidIO II parameter editor tells you the number of reconfiguration interfaces you must configure in your dynamic reconfiguration block For more information refer to Table 5 7 on page 5 4 57 You must add a reset controller Transceiver PHY Reset Controller IP core to your design using the MegaWizard Plug In Manager or Osys and connect it to the RapidIO IP core reset signals This block imple
302. y any control symbols it receives b1 Port is enabled to respond to any packet The value in the PORT field bit 1 of this register can override the values in the oUT PENA and IN PENA fields ERR CHK DIS 20 RO This bit enables 1 bO or disables 1 b1 all RapidlO transmission error checking The RapidlO II IP core does not support the disabling of error checking and recovery so this bit always has the value of 1 b0 Multicast event Participant 19 RW Indicates that the system should send incoming Multicast event control symbols to this port multiple port devices only 1 b1 Flow Control Participant 18 RW Enables or disables flow control transactions 1 b0 Do not route or issue flow control transactions to this port 1 b1 Route or issue flow control transactions to this port This field does not affect the IP core configuration Enumeration Boundary 17 RW Indicates whether this port should delimit enumeration Any enumeration boundary aware system enumeration algorithm should honor this flag The algorithm on either the Rx port or the Tx port should not enumerate past a port in which this bit is set to the value of 1 b1 This field supports software enforced enumeration domains in the RapidlO network Flow Arbitration Participant 16 RW Enables or disables flow arbitration transactions 1 b0 Do not route or issue flow ar
303. y the RapidIO II IP core for each Altera device family Table 1 2 Device Family Support Device Family Support Arria V GX and GT Preliminary Arria V GZ Preliminary Cyclone V Preliminary Stratix V Preliminary Other device families No support IP Core Verification Before releasing a publicly available version of the RapidIO II IP core Altera runs a comprehensive verification suite in the current version of the Quartus II software These tests use standalone methods and the Osys system integration tool to create the instance files These files are tested in simulation and hardware to confirm functionality Altera tests and verifies the RapidIO II MegaCore function in hardware for different platforms and environments Altera also performs interoperability testing to verify the performance of the IP core and to ensure compatibility with ASSP devices Simulation Testing Altera verifies the RapidIO II IP core using the following industry standard simulators m ModelSim simulator m VCS RapidlO 11 MegaCore Function February 2013 Altera Corporation User Guide Chapter 1 About The RapidlO Il MegaCore Function 1 5 IP Core Verification The test suite contains testbenches that use the Cadence Serial RapidIO Verification IP VIP the Cadence Compliance Management System CMS implementation of the RapidIO Trade Association interoperability checklist and the RapidIO bus functional model BFM from the

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