Virtex-4™ MB Development Board User's Guide
Contents
1. 23 3 12 2 System ACE Module 24 _ 26 gt gt 31 GAZ a a 31 3 13 NOE TAGE Fre GGA 32 3 14 BANK VO VOLTAGE c Pu O 33 3 15 P240 EXPANSION MODULE SIGNAL ASSIGNMENTS 33 REVISIONS 36 2 37 December 20 2005 Figures FIGURE 1 VIRTEX 4 MB DEVELOPMENT PLATFORM BLOCK 3 FIGURE ee ___ __ ____ EU 4 FIGURE SAMTEC TYPE CONNECTOR FOR THE SPI 4 2 7 FIGURE 4 DDR SDRAM 7 FIGURE 5 FLASH 0 8 FIGURE 6 CLOCK SOURCES ON THE V IRTEX 4 MB BOARD 10 FIGURE 7 1658442 CLOCK SYNTHESIZER 12 FIGURE 8 ICS8442 CLOCK SYNTHESIZER INTERFACE THE FPGA 15 FIGURE 9 ICS8442 CLOCK SYNTHESIZER M AND DIP SWITCHES 16 FIGURE 10 M AND N DIP SWITCHES FOR THE 52545 IRR eminens 16 FIGURE 11 10 100 ETHERNET2. 2 SAM Connector TMS TCK TMS XC9536XV CPLD JTAG Port PC4 Figure 14 Vitex 4 MB Development Board JTAG Chain Virtex 4 FPGA 3 12 2 System ACE Module Connector The Virtex 4 MB development board provides the SAM 50 pin connector on the board for using the Memec System ACE Module SAM The SAM can be used to configure the FPGA or to provide bulk flash memory to the MicroBlaze processor The Virtex 4 MB development board provides a System ACE interface that can be used to configure the Virtex 4 FPGA The interface also gives software designers the ability to run real time operating systems RTOS from removable CompactFlash cards The Memec System ACE module DS KIT SYSTEMACE can be used to perform both of these functions The figure below shows the System ACE module connected to the header on the Virtex 4 board December 20 2005 24 0 E o lt F inludes VCC and GND JTAG Configuration Port includes VCC and GND for stand alone operation SystemACE Controller 50 pin Connector connects to a 40 pin 0 1 square post header on the main board 4 28 2 10 6 JTAG MPU Reset amp Power amp Misc Configuration Port Interface Clock Ground Signals Figure 15 SystemACE Module 3 12 2 1 System ACE Controller Signal Description The following table shows the System ACE Module signal assignments to th
3. 95 TDa Ci maro 67 C2 ee NO Fo 99 09 rP 2 80 GND 23 RSTATO 25 26 NG December 20 2005 5 ___ GND RDat_N 15 45 6 1 GND 8 GND v8 mang 5 GND GND RDCLK_N ___ 7 80 00 Aart 82 GND 3 1 3 LVDS Connector The design of the SPI 4 2 interface requires use of a high speed and high quality connector The VAMB development board uses the SAMTEC 5 type connector for this interface The 040 01 L Dx A connector from SAMTEC provides up to 28 LVDS signal connections in addition to an adequate number of ground connections for improving the signal quality Two of these connectors are used on the VAMB development board to implement the SPI 4 2 interface In addition a mating LVDS extension cable is available from Samtec part number EQCD 040 06 00 TTR TBL 1 The following figure shows the QSE type connector from SAMTEC the picture is obtained from the SAMTEC web site http www samtec com December 20 2005 6 Figure 3 QSE Type Connector for SPI
4. 0 60 ROSES ADi4 RISE 6 66 ROSES Roso 67 68 ACH NENNEN ojo GND RIO LVDS P14 RIO 1VDS PiS ROIs N2 79 80 aca __ 85 86 December 20 2005 35 AB20 AER RIOIVDS N8 89 90 055 _____ 20 Jaje AD22 N 95 96 057 023 oo 397 98 RIOIVDSP4 99 100 RIO1VDSPS 4021 GND 8 18 RIO_LVDS_PO sae RIO CLKOUT P 4 Revisions V3 0 Initial release for Rev board Dec 20 2005 December 20 2005 36 Appendix 1 Double click CP2101 Install hield Wizard welcome to the 5 Aard for ihe LIEB to VARAT Contraller The instal Shield Wizard wall install the Gygnal USB ta Bridge Controller an aur campar contnue click Hat Launching CP2101 Driver Installation 2 Click Next 3 Read the license agreement and then click Yes InstallShield Wizard License Agreement Flease read the following license agreement Fress the PAGE DOW key to see the rest of the agreement EYGNAL INTEGRATED PRODUCTS INC SOFTWARE LICENSE AGREEMENT Licensee and Cygnal Integrated Products I
5. 4 DDR SDRAM 64MB 16 Bit LVDS Transmit amp Receive P240 Module Flash 4MB 132 Pin Connector A 132 Pin Connector SAM Connector Parallel Cable IV 10 100 PHY JTAG Port XC9536XV CPLD Virtex4 FPGA XC4VLX25 LX60 Parallel Cable IV SX35 Flash SPI Port FF668 Atmel Serial Flash AT45DB321B TC LCD Panel Voltage Regulators Programmable 3 3V LVDS Clock Source Regulator SMA Clock Output 2 5V Regulator LVTTL Clock 100MHz LVTTL OSC Socket Regulator 4 8 Pin User LEDs 1 2V USB RS232 Bridge Figure 1 Virtex 4 MB Development Platform Block Diagram 3 1 LVDS Interface The Virtex 4 MB development board provides high speed LVDS connectors supporting a SPI 4 2 interface This interface consists of 36 LVDS signal pairs 72 FPGA signals and 6 single ended signals In addition to the SPI 4 2 interface the LVDS interface is designed to support XSBI 16 bit LVDS 644Mbps to support a 10GbE interface on the Virtex 4 MB development platform The following sections provide a brief description of the LVDS interface on this development board December 20 2005 3 311 SPFA 2 Interface The Virtex 4 MB development board provides SPI 4 2 a 16 bit parallel LVDS electrical interface The following figure shows the SPI 4 2 interface on the board The transmit and r
6. Figure 17 Virtex 4 MB Development Board JTAG Chain Virtex 4 FPGA The following table shows jumper settings for the JTAG chain on the Virtex 4 MB development board Since CPLD is already programmed by Memec prior to shipment the board is shipped with jumpers installed on pins 1 2 and 4 5 FPGA only in the JTAG chain Table 25 JTAG Chain Jumper Settings Devices in the JTAG Chain JP18 Jumpers Installed CPLD and FPGA Pins 1 2 3 4 and 5 6 CPLD Pins 2 3 and 5 6 FPGA Pins 1 2 and 4 5 3 12 3 2 Configuration Flash on the Virtex 4 MB Development Board The following figure shows the detail interface between the FPGA and the serial flash A PC4 cable is used to program the serial flash with the FPGA bitstream Once the flash is programmed the CPLD will read the data from the flash and configure the FPGA over the Master Serial interface December 20 2005 28 Atmel XC9536XV AT45DB321B Virtex 4 FPGA CPLD JP17 Serial Flash Flash Programming Header PC4 SI 5 50 RESETn Normal Mode E JP12 RDY BUSYn Jumper Figure 18 Serial Flash Configuration Interface 3 12 3 3 Procedure for Programming the Serial Flash 1 Ihe Memec Virtex 4 MB development board is shipped with a selfextracting zip file called Serial Flash Programming Double click on this self extracting zip file to unzip it After unzipping this file a folder called C Flas
7. 5 5 nFOUT1 MR TEST XTAL1 XTAL2 Clock Input Figure 7 1CS8442 Clock Synthesizer Table 6 1CS8442 Clock Synthesizer Pin Description Signal Name Direction Pull up Pull down M 0 4 M 6 8 The M divider inputs latched on the rising edge N 0 1 Input Pull down The N divider inputs latched on the ris ing edge TT TEST Output The TEST output is active during the serial mode of operations Please refer to the datasheet for the device on the rising edge of this clock 5 LOAD Pull down Serial interface load signal The contents of the serial data shift register is loaded into the internal dividers on the rising edge of this signal TEST_CLK Pull down Test clock input nP_LOAD Input Pull down The rising edge of this signal is used to load the M and N divider inputs into the device XTAL1 XTAL2 Input Crystal clock input output December 20 2005 12 Input Pull up This signal is used to select between the crystal and the TEST CLK input to the device When this high crystal is selected Input Pull up This signal is used to place the internal PLL in the bypass mode When this signal is set to low the PLL is placed in the bypass mode For normal operations this signal must be set to high FOUTO FOUT1 Output Positive LVDS clock outputs nFOUTO nFOUT1 Output Negative LVDS clock outputs The Input Clock Select signals of the 58442
8. can be used to provide a reference clock input to the device other than the 25MHz crystal oscillator for test purposes The following table shows how these Input Clock Select signals are used to generate the output clock or to test the 1 58442 device Please refer to the 1 58442 datasheet for more information on using the TEST CLK clock input Table 7 Input Clock Select Signal Description VCO_SEL XTAL_SEL Reference Clock Input FOUT 0 1 TEST CLK TEST CLK N the TEST must be between 10 and 25MHz This mode can be used to test the 1 58442 device by routing the input clock to the outputs 25MHz crystal 25MHz crystal N This mode can be used to test crystal clock to the UN 1 O 1C688442PLL Output N Normal Operation IT 1688442 PLE Normal Operation 3 4 3 ICS8442 Clock Generation The ICS8442 output clocks are generated based on the following formula assuming the crystal clock input is set to 25 2 FOUT 0 1 25 x M N Where 8 M 28 and N can take a value of 1 2 4 or 8 The variable M is determined by setting the binary number M 0 8 while N is set according to the following table Table 8 1CS8442 N Settings OLI 700 01 1 2 085 3 1 8 28 For example to generate a 62 5MHz clock N 1 0 will be set to 10 it can also be set to 11 since ei
9. 0 000001001 01 112 5 000010011 00 475 000010010 10 1125 000010100 00 000010011 10 1187 000010101 00 525 000001010 01 125 000010110 00 000010100 125 000010111 00 575 000010101 10 131 25 000011000 00 600 000001011 01 1875 000011000 00 625 000010110 137 5 000011010 00 000010111 10 1435 000011011 00 675 000001100 01 000011100 00 700 Table 13 FPGA Pin Assignments for the Synthesizer Interface Signal Name Virtex 4 Pin Comments SYNTH_PLOAD V2 This input is used to load the M and N values into the synthesizer using the parallel mode configuration along with the DIP switch settings for M and N the synthesizer using serial mode configuration N values ee __ tnetsymtnesizor using te seria mode configuraton the synthesizer using the serial mode configuration SYNTH_TEST A test clock can be provided to the synthesizer using a purposes _XTALSEL This input signal is used to select between the test clock input and the on board crystal as clock source to the synthesizer SYNTH DOUT K2 This output signal is used as the test clock output 3 5 10 100 Ethernet PHY The Virtex 4 MB development board provides a 10 100 Ethernet port for network connection A high level block diagram of the 10 100 Ethernet interface is shown in t
10. 10FF6E68C FPGA The board includes 64MB of DDR SDRAM 4 of Flash 16 bit LVDS Transmit and Receive ports programmable LVDS clock source USB RS232 Bridge a 10 100 Ethernet PHY 100 MHz clock source RS 232 port and additional user support circuitry to develop a complete system The board also supports the Memec P240 expansion module standard allowing application specific expansion modules to be easily added 2 The Virtex 4 MB System Board ee gt 2 T E n Memet 1 Liu rpe 7 z Ls ij a A E TOS i December 20 2005 1 s X Meme 3 Functional Description A high level block diagram of the Virtex 4 M MB development platform is shown below followed by a brief description of each sub section A list of features for this board is shown below December 20 2005 Xilinx XC4VLX25 LX60 SX35 10F F668 FPGA 64MB of DDR SDRAM 4MB of Flash 16 Bit LVDS Transmit and Receive Interfaces 10 100 Ethernet PHY Programmable LVDS Clock Source 25 700 MHz User LVDS Clock Outputs via Differential SMA Connectors On board 100MHz LVTTL Oscillator On board LVTTL Oscillator Socket 4 8Pin Oscillators P240 Connectors LCD Panel 32Mb Serial Flash for FPGA configuration PC4 JTAG Programming Configuration Port SystemACE Module Connector RS232 Port Four User LEDs Four User Push Button Switches An 8 position DIP Switch USB RS232 Bridge 1
11. 2102 is a highly integrated USB to UART Bridge Controller providing a simple solution for USB serial communications using a minimum of components and PCB space The CP2102 includes a USB 2 0 full speed function controller USB transceiver oscillator EEPROM and asynchronous serial data bus UART with full modem control signals in a compact 5mm X 5mm MLP 28 package No other external USB components are required The on chip EEPROM may be used to customize the USB Vendor 10 Product ID Product Description String Power Descriptor Device Release Number and Device Serial Number as desired The EEPROM is programmed on board via the USB allowing the programming step to be easily integrated into the product manufacturing and testing process Royalty free Virtual COM Port VCP device drivers provided by Cygnal allow the Virtex 4 MB development board to appear as COM port to PC applications The CP2102 UART interface implements RS232 signals including control and handshaking signals These signals are interfaced to the Virtex 4 FPGA as follows December 20 2005 20 USB2 0 to RS232 USB CP2102 Connector USB_SIN USB_ SOUT Virtex 4 FPGA USB RESETn Figure 12 USB 2 0 to RS232 Serial Interface The following table shows the 5232 interface signal names and their Virtex 4 FPGA pin assignments Table 16 USB 2 0 to RS232 Port Signal Description FPGA Signal Name Virtex 4 Pin RS232 Signals Common Signal U
12. 2V Regulator Regulator Regulator 3 3V 2 5V 1 2V 5 0V Connector Connector Connector Connector Figure 20 Voltage Regulators The following table shows the power provided on the development board for the on board voltage sources A 32 5W power adapter 5V 6 5A is used to provide power to the on board regulators The following table shows typical power usage on the Virtex 4 MB development board December 20 2005 32 Table 29 Power Voltage Current Power W ___12 15 18 FPGA Core voltage 257 20 50 __ FPGA voltage P240 supply voltage 33V 3 99 __ FPGA voltage P240 supply voltage Total Power For the on board digital voltages 1 2V 2 5V and 3 3V if the current provided by the on board regulator is not sufficient for some applications the user can directly drive the voltage source and bypass the on board regulators 3 14 Bank Voltage The following table shows the Virtex 4 bank I O voltages on the Virtex 4 MB development board Table 30 I O Bank Voltages _ 25V ELEME _ e 3 15 240 Expansion Module Signal Assignments The following tables show the Virtex 4 pin assignments to the P240 Expansion Module connectors JX1 amp JX2 located on the Virtex 4 MB development board Table 31 P240 Connector Pin Assignments Virtex 4 FPGA Pin I O Connector I O Connector Virtex 4 F
13. 4 2 Interface 3 2 DDRSDRAM The Virtex 4 MB development board provides 64MB of DDR SDRAM memory x16 A high level block diagram of the DDR SDRAM interface is shown below followed by a table describing the SDRAM memory interface signals Address 0 12 Virtex 4 FPGA Data 0 15 DDR SDRAM LX25 LX60 FF668 64MB Control Figure 4 DDR SDRAM Interface Table 3 DDR SDRAM Interface Pin Assignments Signal Name ddr ddr addr 2 ddr addr 3 ddr ddr ddr addr 6 ddr addr 7 ddr addr 8 ddr addr 9 ddr addi 10 ddr addi 11 ddr 44 12 ddr 99707 ddr ddr da 2 December 20 2005 3 3 Flash The Virtex 4 M MB development board provides 4MB of flash memory x16 A high level block diagram of the flash interface is shown below followed by a table describing the flash memory interface signals Address 0 20 Virtex 4 FPGA Data 0 15 Flash LX25 FF668 4MB Control Figure 5 Flash Interface Table 4 Flash Interface Pin Assignments Signal Name FPGA Pin flash_addr 0 Address 0 flash addi flash add December 20 2005 8 aesa _ 600 Addes amp P8 flash 40 d 10 L4 fish d 12 4118 fish 4118 flash_cen flash_oen flash_wen flash_rdy fish reset 3 4 Clock Sources The Clock Generation section of the Virtex 4 MB board provides all the necessary clocks for a MicroBlaze pr
14. Click Finish in the Found New Hardware Wizard Found New Hardware Wizard Completing the Found New Hardware Wizard The wizard has finished installing the software for y CP2101 USB to UART Bridge Controller Click Finish to close the wizard CP2101 Driver Installation Complete Open the Device Manager Control Panel gt System gt Hardware tab gt Device Manager Under the Ports heading a new device shows up called CP2101 USB to UART Bridge Controller Ports COM amp LPT Communications Port COM1 CP2101USB to UART Bridge Controller COM7 ECP Printer Port LPT 1 2101 Recognized as Port the CP2101 does not show up under ports it may show up under Other Devices with a yellow exclamation mark In this case unplug the USB cable run the setup manually C Cygnal CP2101 WIN Setup exe and then plug the USB cable back in The O S automatically assigns a COM Port number typically between For consistency the COM number will be manually changed Right click on CP2101 USB to UART Bridge Controller and select Properties December 20 2005 40 Ports amp LPT Y Communications Port 1 1 to UART Bridge Controller 7 ECP Printer Port LPT1 Update Driver 8 Processors Disable amp 8 Sound video and game controllers Uninstall System devices s Scan for hardware cha
15. NE ik 3 iSSIDUO GLK ieri iragcsb2ctirx ws 19 FIGURE 12 USB 2 0 TO RS232 SERIAL INTERFACE III I mmm nnnm 21 FIGURE 13 RS232 INTERFACE QU 22 FIGURE 14 VITEX 4 MB DEVELOPMENT BOARD JTAG mH mmm emn rns 24 FIGURE 15 SYSTEMACE 00 25 FIGURE 16 VIRTEX 4 MB DEVELOPMENT BOARD CONFIGURATION INTERFACE 26 FIGURE 17 VIRTEX 4 MB DEVELOPMENT BOARD JTAG CHAIN cee Imm Hmmm 28 FIGURE 18 SERIAL FLASH CONFIGURATION INTERFACE cccececccccccccccccccccccccccececuaueeeeeeuuuueees 29 FIGURE 19 PC4 JTAG PORT CONNECTOR 2ccccccccceccccccccecccccccececcccccccencuauececeneuuueeeeeneucunees 31 FIGURE 20 VOLTAGE REGULATORS 32 December 20 2005 1 AX Memec 1 Overview The Memec Virtex 4 M MB Development Kit provides a complete development platform for designing and verifying applications based on the Xilinx Virtex 4 FPGA family This kit enables designers to implement DSP and embedded processor based applications with extreme flexibility using IP cores and customized modules The Virtex 4 FPGA along with Xilinx MicroBlaze soft processor core makes it possible to prototype processor based applications enabling software design teams early access to a hardware platform prior to working with the final product target board The Virtex 4 MB system board utilizes the Xilinx XC4VLX25 LX60 SX35
16. PGA Pin signatname 50 i 2 5 pv 7 EM 5 0V _ 8 5 SE gt 9 10 SE 43 SE 40 5 41 az aes ee December 20 2005 33 A rja 0 f 28 feje 28 o oooO y o 2 5V 2 5V 2 5V 2 5V oes 5 60 0969 die Ee 6 66 moss EM oso 67 68 a fojo oo y 14 756 fos 79 80 movos Ne ete feje GND y UOIVDS Ne 89 90 Jaje TO LOS Ne 95 Fi7 C o 97 68 GND y 96 100 ovos s A2 1 GND 1090 CLKIN N eee i23 i244 i25 i26 December 20 2005 34 Table 32 240 Connector Pin Assignments uxzping Signet Name _ CAPA Signal Name JX2 Pin Signal Name po 59 OV sw 3 4 __ Ooo S Sw 5 6 CL sw 7 8 5 0V BEDV ws mosa o 10 mosa ws eee 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 2 5 2 5 2 5 2 5 28 6 7 0
17. SB RESETn Re J CP2102reset signal To use the USB port the CP2102 device drivers must be installed These drivers are included on the Virtex 4 MB Development Kit CD and contained in the sel extracting file CP2101 exe To install the CP2101 2 virtual COM port device drivers refer to Appendix A 3 8 RS232 The Virtex 4 MB development board provides an RS232 interface with RX and TX signals and jumpers for connecting the RTS and CTS signals The following figure shows the RS232 interface to the Virtex 4 LX25 LX60 SX35 FPGA December 20 2005 21 2 Drivers RS232 Connector Virtex 4 221 3 7 5 8 5 Figure 13 5232 Interface Table 17 85232 Signals Table 18 5232 Jumper Settings Mode of Operation JP19 JP21 DCE Install a jumper on pins 2 3 Install a jumper on pins 1 2 DTE Install a jumper on pins 1 2 Install a jumper on pins 2 3 A Jumper must be installed on JP22 if RTS and CTS signal connections are needed 3 9 User DIP and PB Switches The Virtex 4 MB development board provides four user push button switches as described in the following table An active low signal is generated when a given switch is pressed Table 19 Push Button Switch Pin Assignments Signal Name Virtex 4 Pin PUSH E PUSH PUSHS PUSHA The Virtex 4 MB development board provides an 8 position DIP switch as described in the following table An active low s
18. Virtex 4 MB Development Board User s Guide VIRTEX Version 3 0 December 2005 Memec Table of Contents MESSIS 1 2 THE VIRTEX 4 MB SYSTEM BOARD 1 3 FUNCTIONAL DESCRIPTION 2 2 2 3 1 LVDS 3 P 4 19 FIN Und is 4 OnE O 6 7 2 ee re E MCA 8 FA 2 9 eres SOURCES 3 4 Programmable LVDS Clock 11 3 4 1 ICS8442 Programmable LVDS Clock 11 3 4 2 ICS8442 Clock enean nnne rna 13 3 4 3 ICS8442 Programming 14 3 4 4 1 58442 M and N 5 senes annis 14 3 4 5 Boo 6 OO ETHERNET EER 0 0 unu esc ase uo huM pU ge Us 18 cr S 20 3 USB2 0 TO 5232 PORT piene ones PRU du 20 gt 21 3 0 USERDIP AND PB 22 3 10 U ER LED 6 23 3 11 23 3 12 CONFIGURATION AND DEBUG PORTS ecitccieecesedeeectendivgccsGeneacdbedidesscedapecinedivicevieseesi 23 gt
19. ck frequency of 25 to 700MHz Refer to the Programmable CLKIN 0 D12 P240 Module Single ended Clock Input s These clock inputs LIO CLKIN 1 E13 are connected to the P240 connector located on the Virtex 4 board connector on the Virtex 4 MB board For the SPI 4 2 CLK C1 DDR Feedback Clock Input This clock input is connected to the clock SPI TSCLK SPI 4 2 Transmit Status Clock Input This clock input is connected to the SPI 4 2 transmit status clock output SAM CLK AE10 SystemACE Module Clock Input This clock input is connected to the SystemACE Module connector generate a reference clock input to the LVDS interface The use of this variable clock source external DACs or ADCs 3 4 2 1658442 Programmable LVDS Clock Synthesizer The Virtex 4 MB development board design uses the 1 58442 LVDS clock synthesizer for generating various clock frequencies A list of features included in the 1 58442 device is shown below e Output frequency range 25MHz to 7OOMHz e RMS period jitter 2 7ps typical Cycle to cycle jitter 2705 typical e Output rise and fall time 65005 maximum e Output duty cycle 48 52 December 20 2005 11 The following figure shows high level block diagram of the 1 58442 programmable LVDS clock synthesizer M 0 8 0 1 9 nP_LOAD 5 DATA 5 CLOCK 6 S LOAD FOUTO 0 nFOUTO VCO SEL ICS8442 XTAL SEL 2 gt 2 FOUT1 TEST_CLK
20. e FPGA I O pins Table 23 SAM Interface Signals 4 System SAM Connector Pin System ACE 4 Pin Name eet Signal Name td 6 10 CLOCK 7 o 7 8 _____ PROGRAMn OND GND December 20 2005 25 1 42 m 48 DONE 4 48 BHSIREAM 5 Nc 1 3 12 3 Serial Data Flash This section describes the procedure for programming the Atmel serial data flash on the Memec Virtex 4 MB development board This serial flash along with a CPLD is used to configure the Virtex 4 FPGA located on the development board on power up The following figure shows a high level block diagram of the serial flash interface to the Virtex 4 FPGA Master Serial Interface SPI Interface Virtex 4 Atmel AT45DB321B FPGA Serial Flash FPGA SI FPGA SO FPGA SCK FPGA CSn FPGA WPn WPn FPGA RESETn RESETn FPGA RDY BUSYn RDY BUSYn Figure 16 4 MB Development Board Configuration Interface December 20 2005 26 A An interface is provided between the FPGA and the CPLD to allow access to the serial flash after the FPGA has been configured This interface uses FPGA I O pins to interface to the serial flash via the SPI port The Virtex 4 FPGA uses 8Mb 18 3Mb 14 5Mb LX25 LX60 SX35 of the serial flash memory for configuration and t
21. e refer to Table 6 for the information on pull up and pull down resistors provided internal to the 1 58442 device for the M and N input signals 3 3V 6 Synthesizer 9 8 7 6 5 4 3 2 1 Figure 10 DIP Switches for the Synthesizers December 20 2005 16 Table 10 DIP Switch Setting for 8 0 Switch Position SW1 SW10 and SW2 or ___ DIP 0 rt o DIP2 4 DIP3 DIP4 Note 1 The polarity of M5 DIP4 is the opposite of all other DIP switch positions Table 11 DIP Switch Setting for N 1 0 The following table shows a complete list of frequencies generated by the 1 58442 device based on a 25MHz crystal reference clock input Table 12 Synthesizer Clock Outputs for M and N Values H 1 9 ___ 80 1 0 FOUT 1 0 MHz 000001000 10 50 X 000001000 O0 000001001 10 5625 000001001 0 000001010 10 625 000001010 250 ___ 000001011 10 6875 000001011 0 275 ___ 000001100 10 75 X 000001100 30 ___ December 20 2005 17 000001101 10 8125 000001101 00 325 000001110 875 000001110 00 000001111 10 9375 000001111 00 375 000001000 01 X 000010000 00 000010000 10 000010001 00 425 000010001 10 106 25 000010010 00 45
22. eceive interface of the SPI 4 2 are implemented using LVDS signals while the status flow control signals are implemented using single ended LVTTL signals LVDS Signals SysCIk P TDat 15 0 SysCIk N Transmit Link Layer TStat 1 0 TStat 1 0 TSCIk TSCIk LVTTL Signals LVDS Virtex 4 FPGA Connectors 4VLX25 FF668 LVDS Signals RDat 15 0 Receive Link Layer RStat 1 0 RStat 1 0 RSCIk RSCIk LVTTL Signals Figure 2 SPI 4 2 Interface 3 1 2 SPEF4 2 Pin Assignments The following table shows the SPI 4 2 pin assignments for the 4VLX25 LX60 SX35 FPGA in the FF668 pin package These pin assignments must be used in the board design in order to meet the SPI 4 2 interface core requirements Table 1 SPI 4 2 Transmit Pin Assignments Virtex 4 Pin LVDS Signal J4 Connector Pin LVDS Signal Virtex 4 Pin Name LVDS TX Name o 1 1 2 p 1 8e 3 4 J GND 8 ii 12 GND 1 December 20 2005 4 asi 25 17 27 28 X 30 29 l ____ 7 31 832 _ 07 0 38 ps man 9 E58 eND 6 G7 TDa
23. h_Utilities is created 2 n order to program the flash flash programming utilities included in the xapp800 must be downloaded from the following web site http www xilinx com products xaw coolvhdlg htm 3 Click on the above link to download the xapp800 zip file and unzip it to a temporary folder on your hard drive You need to register prior to downloading the xapp800 zip file 4 Copy xmcsutil exe and xspi at exe files from this temporary folder to the CAFlash Utilities folder The following table shows the contents of the C Flash Utilities folder after copying these two executable files Table 26 Files in the Flash Utilities Folder y FileName Description December 20 2005 29 xmcsutil exe A utility that is used to reverse the bytes in an MCS file This is needed by the xspi at utility xspi at exe This utility is used to erase program 0 and verify the Atmel serial flash the Virtex 4 MB development board prog flash bat This batch file calls the xmcsutil and xspi at utilities to erase program and verify the Atmel serial flash on the Virtex 4 MB development board spi cpld jed Programming file for the XC9536XV CPLD Generate a bit file for the FPGA 6 Use iMPACT to generate an MCS file for the bit file generated in the previous step When generating the MCS file select a single platform flash device that will hold the entire design configuration bits The following table shows the platform fla
24. he following figure followed by FPGA pin assignments for this interface December 20 2005 18 ETH RXD 0 3 ETH RXDV ETH RXER ETH RXC ETH TXD 0 3 ETH TXEN Broadcom irtex 4 ETH TXER BCM5221 FPGA 10 100 PHY ETH TXC ETH COL ETH CRS ETH MDC ETH RESETn ETH MDIO Figure 11 10 100 Ethernet Interface RJ45 Connector built in magnetics Crystal 20Mhz The following table shows the FPGA pin assignments for the Ethernet interface Table 14 Ethernet Pin Assignments Virtex 4 Pin ETH CRS December 20 2005 3 6 LCD Panel The Virtex 4 MB development board provides an 8 bit interface to a 2x16 LCD panel MYTECH MOC 16216B B The following table shows the LCD interface signals Table 15 LCD Interface Signals Virtex 4 Pin LCD Data Bit 6 AC17 LCD Data Bit 7 AB17 LCD Enable Signal LCD Write Signal this signal is connected to logic 0 on the Virtex 4 MB board enabling write only cycles D D D D D D E R DO pope 8 05 1 5 AE12 L 7 MERC ANN EN 1 2 3 4 5 7 85 RS 1 Register Select Signal 37 USB 2 0 to RS232 Port The Virtex 4 MB development board implements a USB 2 0 port This is accomplished using the Cygnal CP2101 USB to UART Bridge Controller The FPGA interfaces to the CP2102 as a simple UART The UART interface to the CP2102 can run at speeds ranging from 300 to 921 600 baud The CP
25. his interface allows the rest of the flash to be used for general purpose application after the FPGA has been configured The following table shows the signals used to implement the interface between the FPGA and the CPLD after the FPGA has been configured Table 24 FPGA SPI Interface Pin Assignments The primary function of the CPLD is to translate the Master Serial interface to the SPI interface of the serial flash The XC9536XV CPLD uses the FPGA CCLK clock along with the INITn and DONE signals to drive the SPI SI SCK and CSn signals The SO output of the serial flash is used by the CPLD to drive the DIN signal of the FPGA For more information on detail of the CPLD design please refer to the Xilinx XAPP800 3 12 3 1 JTAG Chain on the Virtex 4 MB Development Board The following figure shows the JTAG chain on the Virtex 4 MB development board As mentioned in the above section the CPLD is used for interfacing to the configuration flash and does not provide any user logic Hence this CPLD is programmed by Memec prior to shipping the board The programming file for the CPLD is provided in case re programming of the CPLD becomes necessary The CPLD must be programmed prior to performing any operations on the serial flash such as erasing programming reading or verifying December 20 2005 27 2 SAM Connector TMS TCK TMS XC9536XV CPLD JTAG Port PC4
26. ignal is generated when a given switch is ON December 20 2005 22 Table 20 DIP Switch Pin Assignments DIP3 X UserSwitchinputS BS 6 UserSwitchinpt 4 3 10 User LEDs The Virtex 4 MB development board provides four user LEDs that can be turned ON by driving the LEDx signal to logic 0 The following table shows the user LEDs and their associated Virtex 4 FPGA pin assignments Table 21 LED Pin Assignments DSTI 3 11 VBAT Jumper A 3 pin jumper is used to provide user access to the VBAT input of the FPGA If user is not sourcing the VBAT voltage a jumper must be installed on pins 1 2 of the JP27 jumper User can source voltage to the VBAT input via pins 2 and 3 of this jumper The following table shows the pin assignments for the VBAT jumper Table 22 VBAT Jumper JP27 PinNumber Descripton VBAT 3 12 Configuration and Debug Ports Various methods of configuration and debug support are provided on the Virtex 4 MB development board to assist designers during the testing and debugging of their applications The following sections provide brief descriptions of each of these interfaces 3 12 1 JTAG Chain The following figure shows the JTAG chain on the Virtex 4 MB development board The XC9536XV along with a serial flash is used to configure the FPGA The serial flash programming procedure is explained in section 3 11 3 December 20 2005 23
27. ing modes of loading the M and N values into the device 345 1658442 M and N Settings The following figure shows how the ICS8442 programmable LVDS clock synthesizer is used on the Virtex 4 MB board DIP Switches are provided on the board for manual setting of the M and N values December 20 2005 14 nFOUTO 0 8 5 Virtex 4 3 CLOCK FPGA S LOAD VCO SEL XTAL SEL TEST CLK TEST CLKOUTO CLKOUT1 Parallel Load ICS8442 Serial Load Control Inputs Figure 8 ICS8442 Clock Synthesizer Interface to the FPGA As shown in the above figure the 1 58442 device outputs two identical LVDS clock sources One of these clock sources can be used to provide the reference clock input to the LVDS interface on the Virtex 4 MB development board while the other clock output can be used to trigger a scope during testing The second output could also be used to provide a low jitter LVDS clock source to a user board such as the P240 module December 20 2005 15 nm 9 lt lt lt lt e T E x x 6 6 SMA Connectors Virtex 4 FPGA ICS8442 M 8 0 25Mhz N1 0 Figure 9 ICS8442 Clock Synthesizer M and DIP Switches The following tables show the DIP Switch settings for M and N selections Pleas
28. nc C GWNAL located at 4301 Westbank Drive Suite 100 Austin Texas 874b collectively the Parties or individually Fart hereby enter Into this Software License Agreement in accordance the Terms and Conditions the Agreement TERMS AND CONDITIONS d you accept all the terms of the preceding License Agreement Ifyou choose the setup will close To install the Cygnal CP2101 USB to UART Bridge Controller you must accept this agreement Cygnal License Agreement December 20 2005 3 4 Browse an acceptable installation directory and then click Next InstallShield Wizard Choose Destination Location Select folderwhere Setup will install tiles Setup wili install the Cycnal CP2101 USB io UAT Bridge Controller in the following tolder install to his oldar click Mand To insteallio a dolder clic Browse and another taler Destination Folder Ernage a CP2101 Destination Location 5 The drivers are extracted to the selected directory Click Finish once the extraction completes InstallShield Wizard installshield Wizard Complete Seip has installing te CFZ1IO01 USE to LAAT Bndge Controller on vour computer CP2101 Installation Successful 6 To finish the installation plug the USB cable into the board and a USB port on the PC December 20 2005 38 7 Turn board power swi
29. nges Universal Serial Bus controllers Properties COM Port Properties 15 Change to the Port Settings tab and select Advanced CP2101 USB to UART Bridge Controller COM7 Propert General Port Settings Driver Bits per second 9600 None Stop bits 1 How control None v Restore Defaults Port Settings Advanced 16 Select COM10 in the COM Port Number field and then click OK twice December 20 2005 41 Advanced Settings for COM10 Use FIFO buffers requires 16550 compatible OK Select lower settings to correct connection problems Cancel Select higher settings for faster performance Defaults Receive Buffer Low 1 High 14 Transmit Buffer 1 High 16 COM Port Number M10 Changing the Port Number 17 Close the Device Manager and then re open it Under Ports the CP2101 USB to UART Bridge Controller is now assigned to COM10 as shown below Ports COM amp LPT Communications Port COM1 n X CP2101 USB to UART Bridge Controller COM10 ECP Printer Port LPT1 CP2101 Assigned to COM10 December 20 2005 42
30. ocessor the I O devices located on the board as well as the DDR SDRAM memory In general the clock sources on the board are grouped into two categories differential and single ended clock sources The differential clock sources are primarily used by the LVDS interface while the single ended clock sources are used by the processor section r Bi C1 o1 9 n5o 2 on board 100MHz oscillator provides the system clock input to the processor section This 100Mhz clock will be used by the Virtex 4 Digital Clock Managers DCMs to generate various processor clocks In addition to the above clock inputs a socket is provided on the board that can December 20 2005 9 A used to provide single ended LVTTL clock input the FPGA 8 or 4 pin oscillator The following figure shows the clock resources on the Virtex 4 MB development board SMA Connectors P240 DDR P240 Programmable Single ended Feedback Differential LVDS Clock CLock Clock CLock Source 2 x 2 gt lt 5 2 5 5 5 cc E 9 g x g E V 5 5 5 l d O O Virtex 4 XC4VL25 LX60 FF668 Bank 10 Bank 4 R8 AF11 14 a E y e _ E q 4 0 0 6 aa OSC SAM Socket CLock Figure 6 Clock Sources on the Virtex 4 MB Board December 20 2005 10 The following table provides b
31. ogramming was NOT successful Check the following jumper settings a Make sure JP9 jumpers are un installed b Make sure JP12 jumper is un installed After checking these jumper settings go back to the step 11 and re program the flash 13 Upon completion of the serial flash programming power down the board and remove the cable from the Flash Programming header 14 Set the mode jumpers to Master Serial install all mode jumpers on JP9 15 Install a jumper on JP12 16 Power up the board and FPGA will configure 3 12 4 JTAG Port The Virtex 4 MB development board provides a JTAG port PC4 type connector for configuration of the FPGA The following figure shows the pin assignments for the PC4 header on this development board 2 5V PCA Connector Figure 19 JTAG Port Connector 3 12 5 Configuration Modes The following table shows the Virtex 4 configuration modes December 20 2005 31 Table 28 FPGA Configuration Mode Jumper Settings PC Pull up Configuration Mode Jumpers mae oo oo oS 3 13 Voltage Regulators The following figure shows the voltage regulators that are used on 4 MB development board to provide various on board voltage sources As shown in the following figure a connector is used to provide the main 5 0V voltage to the board This voltage source is provided to all on board regulators to generate the 1 2V 2 5V and 3 3V voltages 3 3V 2 5V 1 2V 3 3V 2 5V 1
32. rief description of each clock input to the Virtex 4 FPGA Table 5 Clock Inputs FPGA Pin CLK PROG P Positive and Negative Differential System Clock Inputs CLK PROG N B10 These clock inputs are connected to the output of an LVDS clock gt synthesizer This programmable clock source can generate a LVDS Clock Source section for more information LIO CLKIN P B17 P240 Module Differential Clock Input This clock input is LIO CLKIN N A17 connected to the P240 connector located on the Virtex 4 board SPI RDCLK P AF11 Positive and Negative Differential SPI 4 2 Receive Clock SPI RDCLK N AF10 Inputs These clock inputs are connected to the LVDS receive applications these clock inputs are the SPI 4 2 receive clock outputs 7 100 13 System Clock This clock input is connected to 100 2 LVTTL oscillator CLK SOCKET AE14 LVTTL Clock Input LVTTL socket on the Virtex 4 board ETH RXC A16 Ethernet Receive Clock Input This clock input is connected to the Ethernet receive clock ETH TXC B15 Ethernet Transmit Clock Input This clock input is connected to the Ethernet transmit clock 3 4 1 Programmable LVDS Clock Source A programmable LVDS clock synthesizer is used on the Virtex 4 MB development board to allows designers to prototype various interconnect technologies with different clock source requirements The differential output port is also well suited for DSP applications when driving clo
33. sh devices that must be used when generating the MCS file in iMPACT for the Virtex 4 MB board Table 27 Platform Flash Selection FPGA Platform Flash Used LX25 XCFO8P XCF16P XCF32P LX60 XCF32P XCF16P or XCF32P 7 Un install JP9 jumpers 8 Make sure JP12 jumper is un installed When JP12 jumper is un installed the CPLD outputs are placed in the tri state mode allowing the Flash Programming Header to drive the serial flash SPI bus 9 Connect a PC4 cable to the Flash Programming Header JP17 and power up the Virtex 4 MB development board 10 Copy the MCS file to the C Flash_Utilities folder 11 Open a DOS window in the C Flash_Utilities folder and enter the following command to program the serial flash C Flash_Utilities gt prog flash design name mcs flash number Where design name mcs The mcs file generated using the bit file flash part number lt Either AT45DB321B or AT45DB321C VAMB board is populated with one or the other device The prog flash batch file will erase the flash program and verify it December 20 2005 30 12 Once the flash programming is completed open verify_result txt file in the C Flash_Utilities folder If the flash programming was successful you should see the following line in the verify_result txt file gt Total byte mismatches 0 there is anything other than this line in the verify_result txt file the flash pr
34. tch to the ON position 8 The Found New Hardware Wizard launches Click the radio button to Install the software automatically Recommended and then click Next Found New Hardware Wizard Welcome to the Found New Hardware Wizard This wizard helps you install software for CP2101 USB to UART Bridge Controller 9 your hardware came with an installation lt 3 or floppy disk insert it now What do you want the wizard to do Install the software automatically Recommended CO Install from a list or specific location Advanced Click Nest to continue Found New Hardware Wizard 9 The driver installation begins If installing on WindowsXP a warning is received stating that Windows Logo testing has not passed as shown below Click Continue Anyway Hardware Installation The software you are installing for this hardware CP2101 USB ta UART Bridge Controller has not pr Windows es to 5 compatibility all m r this 5 impi Continuing your installation of this software may impair or destabilize the correct operation of your system either immediately or in the future Microsoft strongly recommends that you stop this installation now and contact the hardware vendor for software that has passed Windows Logo testing Continue Anyway STOP Installation Windows Logo Testing Not Passed December 20 2005 39 10 11 12 13 14 The driver installation completes this point
35. ther one will be the correct frequency range for the 62 5MHz clock and M will be set to 000001010 decimal 10 So from the above formula FOUT 0 1 25 x 10 4 12 December 20 2005 13 The following table shows how the values can be set to generate a clock source for a few common applications All the values for M and N are based on the 25MHz crystal clock input to the 1 58442 device A complete list of frequencies generated by the ICS8442 based 25MHz input clock is provided in the following sections Table 9 Examples of the ICS8442 M and N Settings Interconnect FOUTO and FOUTI MHz FEET ME PMS M2 Mr Wo GigabtEthemet 5 __ o o o 0 Fiber Channel 53125 0 t J1 1 _ 1962 0 0 jo Infiniband 125 0 jO 1 XAUI 195625 0 jo jo ji ji 3 4 4 58442 Programming Modes The ICS8442 provides two different methods of programming the M N values into the device a Parallel Mode and a Serial Mode In parallel mode M and N values are programmed into the device when the nP_LOAD signal pulses low In the serial mode the I2C pins S DATA and o CLOCK along with the 5 LOAD signal are used to shift the M and N values into the device Please refer to the 1658442 datasheet for more information on programm
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