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altmult_add Megafunction User Guide

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1. z Show in Available devices list Specific device selected in Available devices list Core voltage 1 5 EDN MMMM n D IEAM MMMMMMMH PMI MMMM NN NP gt Migration compatibility ompanion device Migration Devices HardCopy Il m 0 migration devices selected VV Limit DSP amp RAM to Hardt Cancel 2 Inthe Family list select Stratix 3 Under Target device select Specific device selected in Available devices list 4 Inthe Available devices list select EP1S10F780C5 5 Click OK 6 Inthe Processing menu click Start Compilation to compile the design 7 When the Full compilation was successful box appears click OK 2 30 Altera Corporation altmult_add Megafunction User Guide March 2007 Getting Started Functional Results Simulate the Complex Multiplier Design This section describes how to verify the design example you just created by simulating the design using the Quartus II Simulator To set up the Quartus II Simulator perform the following steps 1 10 Altera Corporation March 2007 On the Processing menu select Generate Functional Simulation Netlist When the Functional Simulation Netlist Generation was successful box appears click OK On the Assignments menu click Settings The Settings dialog box appears In the Category list select Simulator Settings The Simulator Settings page appears In the Simulation mode
2. Note to Table 3 3 1 This parameter is available only for Stratix III devices 2 This parameter is available only for Stratix II devices 3 This parameter is available only for Stratix II and Stratix III devices 3 22 altmult_add Megafunction User Guide Altera Corporation March 2007
3. multipliers How wide should the A input buses be How wide should the B input buses be How wide should the result output bus be C Create a 4th asynchronous clear input option This forces all registers to have an associated asynchronous clear input Mi Create an associated dock enable for each dock Input Representation Whatis the representation format for A inputs Variable M signa input controls the sign 1 signed 0 unsigned What is the representation format for B inputs Variable E signb input controls the sign 1 signed 0 unsigned ue eer 25 Click Next 26 Under Outputs Configuration turn off Create a shiftout output from A input of the last multplier and Create a shiftout output from B input of the last multiplier 27 Turn on Register output of the adder unit and click More Options The Output Register Configuration dialog box appears 28 In the What is the source for clock input list select Clock0 2 42 Altera Corporation altmult_add Megafunction User Guide March 2007 Getting Started 29 In the What is the source for asynchronous clear input list select None Figure 2 35 shows the Output Register Configuration dialog box after you have made these selections Figure 2 35 Output Register Configuration Dialog Box Output Register Configuration What is the source for clock input Clock p J
4. MegaWizard Plug In Manager page 5 of 7 ALTMULT_ADD Version 6 1 dataa_1 8 0 penal 7 Wa Input Configuration M Register input A of the multiplier Options M Register input B of the multiplier Options What is the input A of the multiplier connected to Multiplier input What is the input B of the multiplier connected to Multiplier input Ka r Output Configuration Register output of the multiplier Altera Corporation March 2007 2 19 altmult_add Megafunction User Guide Example 1 46 Click Finish The final page of the wizard shows the file that is generated for your custom megafunction variation The gray check marks indicate files that are always generated the other files are optional and are generated only if selected indicated by a red check mark Turn on the boxes to select the files that you want generated 47 Turn on VHDL Component declaration file and Instantiation template file 48 Turn off Quartus symbol file and AHDL include file Leave the other options in their default settings Figure 2 16 shows the wizard after you have made these selections Figure 2 16 MegaWizard Plug In Manager altmult_add Page 7 of 7 Summary MegaWizard Plug In Manager page 7 of 7 Summary ALTMULT_ADD Version 6 1 Z Simulation Summary When the Finish button is pressed the MegaWizard Plug In Manager will create
5. Italic Type with Initial Capital Letters Italic type External timing parameters directory names project names disk drive names filenames filename extensions and software utility names are shown in bold type Examples fmax qdesigns directory d drive chiptrip gdf file Document titles are shown in italic type with initial capital letters Example AN 75 High Speed Board Design Internal timing parameters and variables are shown in italic type Examples tpa n 1 Variable names are enclosed in angle brackets lt gt and shown in italic type Example lt file name gt lt project name gt pof file Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters Examples Delete key the Options menu Subheading Title References to sections within a document and titles of on line help topics are shown in quotation marks Example Typographic Conventions Courier type Signal and port names are shown in lowercase Courier type Examples data1 tdi input Active low signals are denoted by suffix n e g resetn Anything that must be typed exactly as it appears is shown in Courier type For example c qdesigns tutorial chiptrip gdf Also sections of an actual file such as a Report File references to parts of files e g the AHDL keyword SUBDESIGN as well as logic function names e g TRI are shown in Courier 1 2 3 an
6. Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO 7 3 14 altmult_add Megafunction User Guide Altera Corporation March 2007 Specifications Table 3 3 altmult_add Megafunction Parameters Part 11 of 18 Parameter CHAINOUT_ROUND_ PIPELINE ACLR Type String Required No Comments Specifies the asynchronous clear source for the second register on the chainout_round input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and CHAINOUT_ROUND_ PIPELINE REGISTER is used the default value is ACLR3 1 CHAINOUT_ ROUND OUTPUT_ REGISTER String Specifies the clock source for the third register on the chainout_round input Values are UNREGISTERED CLOCKO0 CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO 7 CHAINOUT ROUND OUTPUT_ ACLR String Specifies the asynchronous clear source for the third register on the chainout_round input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and CHAINOUT_ROUND_ OUTPUT_REGISTER is used the default value is ACLR3 7 CHAINOUT_ SATURATION String Enables saturation handling at the chainout stage Values are YES NO and VARIABLE A value of YES or NO specifies saturation handling setting permanently to on or off A value of VARIABLE allows dynamically controlled saturation handling If omitted the default value is NO 7 CHAINOUT_SATURATE _ RE
7. Whatis the source for asynchronous dear input None p 30 Click Done 31 Under Adder Operation in the What operation should be performed on outputs of the first pair of multipliers and the What operation should be performed on outputs of the second pair of multipliers lists select Add 32 Under Implementation select Use the default implementation Figure 2 36 shows the wizard after you have made these selections Altera Corporation 2 43 March 2007 altmult_add Megafunction User Guide Example 2 Figure 2 36 altmult_add Wizard Page 4 MegaWizard Plug In Manager page 4 of 7 ALTMULT_ADD Version 6 1 Parameter Settings Outputs Configuration Create a shiftout output from A input of the last multiplier Create a shiftout output from B input of the last multiplier O o Register output of the adder unit Adder Operation What operation should be performed on outputs of the first pair of multipliers What operation should be performed on outputs of the second pair of multipliers Implementation Which multiplier adder implementation should be used Use the default implementation Use dedicated multiplier circuitry Not available for all families Use logic elements oot oe 33 Click Next 34 Under Input Configuration turn on Register input A of the multiplier and click More Options T
8. 2 addnsub3_ round No Enables adding or subtracting for the fourth multiplier 2 the first and second multiplier 01 or the third and fourth multiplier 23 mult round No Enables rounding for Port 01 23 Port is required when the the first and second corresponding MULTIPLIER ROUNDING multiplier 01 orthe parameter has a value of VARIABLE 2 third and fourth multiplier 23 mult saturation No Enables saturation for Port 01 23 Portis required when the corresponding MULTIPLIER SATURATION parameter has a value of VARIABLE 2 Notes to Table 3 1 1 This parameter is available only for Stratix III devices 2 This parameter is available only for Stratix II devices Table 3 2 altmult_add Megafunction Output Ports Port Name Required Description Comments result Yes Multiplier output port Output port WIDTH RESULT 1 0 wide overflow No Overflow flag If output_saturation is enabled overflow flag is set chainout_sat_overflow No Overflow flag for the 1 chainout saturation 3 4 altmult_add Megafunction User Guide Altera Corporation March 2007 Specifications scanouta No Output of scan chain A Output port WIDTH_A 1 0 wide When designing with Stratix III devices port cannot be selected when scaninb is in use Note Do not use scani
9. Summary When the Finish button is pressed the MegaWizard Plug In Manager will create the checked files in the following list You may choose to include or exclude a file by checking or unchecking its corresponding checkbox respectively The state of checkboxes will be remembered for the next MegaWizard Plug In Manager session 0 The MegaWizard Plug In Manager will create these files in the directory datab_0 8 0 C Documents and Settings Temp cplx_mult_restored imag_mult vhd Variation file dataa_1 8 0 O imag_mult ine AHDL Include file rs E imag_mult cmp VHDL Component declaration file A o imag_mult bsf Quartus symbol file i f E imag_mult_inst vhd Instantiation template file p e E imag_mult_waveforms html Sample waveforms in summary imag_mult_wave jpg Sample waveform file s datab Unsigned ee eee Le 50 Click Finish The altmult_add variation is now built Combine real_mult and image_mult to Create a Complex Multiplier This section describes how to create a new top level Verilog HDL file in the Quartus II software 1 From your working directory open the cplx_mult vhd file 2 On the Project menu click Add Remove Files in Project The Settings dialog box appears Figure 2 22 Altera Corporation 2 27 March 2007 altmult_add Megafunction User Guide Example 1 Figure 2 22 Settings Dialog Box Settings cplx_mult Category General F
10. click the icon to expand Simulator Settings and select Simulator Power The Simulator Power page appears Turn off Generate Signal Activity File and Generate VCD File Click OK On the Processing menu click Start Simulation to run a simulation You may be prompted to save the file if so click OK When the Simulation was successful box appears click OK 2 53 altmult_add Megafunction User Guide Example 2 13 The Simulation Report window appears Verify the simulation waveform results Figure 2 43 Figure 2 43 Timing Simulation Waveform Simulation Waveforms Simulation mode Timing N Master Time Bar Ops 4 gt Pointer Ops Interval Ops Start End v Dps 20 0ns 40 0ns 60 0ns 80 0ns 100 0ns 1200ns 140 0ns 160 0ns 180 0ns 200 0ns z 0ps Name clock0 E dataa_0 0 GULGA Gaana 0 E datab_0 3 a E datab_1 T H E datab_2 5 2 E datab_3 2 ga enad i E resut o DES E CS O28 C E 4 E A 9 CED EPA i at signa signb 2 l Simulate the FIR Filter Design in the ModelSim Altera Software Simulate the design in ModelSim to compare the results of both simulators Setup the ModelSim Altera simulator by performing the following steps 1 Unzip almult_add_ex2_msim zip to any working directory on your PC 2 Start ModelSim Altera 3 On the File menu click Change Directory The Choose folder dialog box appears in whcih to select the folder where you have un
11. resuhjis N DES E Bere Latency Implement the 9 x 9 Complex Multiplier Design This section describes how to assign the EP1S10F780C5 device to the project and compile the project in the Quartus II software 1 On the Assignment menu click Device The Settings dialog box appears Figure 2 24 2 29 Altera Corporation altmult_add Megafunction User Guide March 2007 Example 1 Figure 2 24 Settings Dialog Box Settings cplx_mult Category General Files User Libraries Current Project Select the family and device you want to target for compilation Device Operating Conditions j z T parema Family Stratis Compilation Process Settings J i z arn Package Any v EDA Tool Settings Device amp Pin Options Analysis amp Synthesis Settings Pin count Any Se Fitter Settings Target device 3 Timing nalysis Settings Auto device selected by the Fitter Speed grade Any zl TimeQuest Timing Analyzer Classic Timing Analyzer Settings FRN Assembler alee Show advanced devices Design Assistant I HardCopy compatible only SignalT ap II Logic Analyzer Available devices Logie Analyzer Interface Name les Memon DSP PLL DLL Simulator Settings r EP1S10B672C6 920448 PowerPlay Power Analyzer Settings EP1S10B672C7 920448 EP1S10F484C5 920448 EP1S10F484C6 920448 EP1S10F484C7 920448 EP1S10F 48416 920448 EP1S10F672C6 920448 EP1S10F672C7 920448 920448
12. Arithmetic G ALTACCUMULATE A ine ALTFP_ADD_SUB Verilog HDL ALTFP_MULT ALTMEMMULT What name do you want for the output file Browse ALTMULT_ACCUM MAC Settings T emp cplx_mult_restored real_mult ALTMULT_ADD ALTSQRT I Generate clear box netlist file instead of a default wrapper file LPM_ABS for use with supported EDA synthesis tools only LPM_ADD_SUB LPM_COMPARE LPM_COUNTER Note To compile a project successfully in the Quartus II software LPM DIVIDE your design files must be in the project directory in the global user LPM MULT libraries specified in the Options dialog box Tools menu or a user P ARALLEL ADD library specified in the User Libraries page of the Settings dialog box Assignments menu a Gates S 1 0 Your current user library directories are E Interfaces Memory Compiler I Return to this page for another create operation g SignalT ap Il Logic Analyzer Storage Cancel lt Back 10 11 12 13 14 Altera Corporation March 2007 Click Next In the What is the number of multipliers list select 2 Turn on All multipliers have similar configurations In both the How wide should the A input buses be and How wide should the B input buses be lists select 9 In the How wide should the result output bus be list select 19 Turn off Create a 4th asynchronous clear input option and Create an associated clock enable for each clock In the What is the represent
13. C AHDL Sj Arithmetic e ALTACCUMULATE a vipe ALTFP_ADD_SUB Verilog HDL ALTFP_DIV i es TFP MULT What name do you want for the output file Browse ALTMEMMULT C project real_mult ALTMULT_ACCUM MAC ALTMULT_ADD Generate clear box netlist file instead of a default wrapper file ALTSORT for use with supported EDA synthesis tools only LPM_ABS LPM_ADD_SUB LPM_COMPARE Note To compile a project successfully in the Quartus II software LPM COUNTER your design files must be in the project directory in the global user LPM DIVIDE libraries specified in the Options dialog box Tools menu or a user LPM MULT library specified in the User Libraries page of the Settings dialog box Assignments menu PARALLEL_ADD Gates Your current user library directories are amp 1 0 amp Interfaces a Memory Compiler a Parallel Flast ade A SignalT ap II Logic Analyzer I Return to this page for another create operation Cancel lt Back Next gt t On page 3 of the altmult_add wizard specify the number of multipliers to be created the width of the input bus whether the input bus is signed unsigned or variable You can also set options to configure signa and signb inputs Figure 2 3 2 2 Altera Corporation altmult_add Megafunction User Guide March 2007 Getting Started Figure 2 3 MegaWizard Plug In Manager altmult_add Page 3 of 7 MegaWizard Plug In Manager page 3 of 7 ALTMULT_ADD Versio
14. III information to tables No new screenshots were taken November 2006 2 2 e Made some minor adjustments pertaining to the Stratix III release November 2006 2 1 e Updated for the Quartus II software version 6 1 GUI changes and functionality e Updated design examples August 2006 2 0 e Updated for the Quartus Il software version 6 0 GUI changes and functionality e Updated design examples March 2005 1 0 Initial release How to Contact Altera Altera Corporation March 2007 For the most up to date information about Altera products go to the Altera world wide web site at www altera com For technical support on this product go to www altera com mysupport For additional information about Altera products consult the sources shown below Information Type Contact Technical support www altera com mysupport Product literature www altera com Altera literature services literature altera com 1 FTP site ftp altera com Note to table 1 You can also contact your local Altera sales office or sales representative v altmult_add Megafunction User Guide Typographic Conventions Typographic Conventions This document uses the typographic conventions shown below Visual Cue Bold Type with Initial Capital Letters Meaning Command names dialog box titles checkbox options and dialog box options are shown in bold initial capital letters Example Save As dialog box bold type
15. Interface Check outputs AE i upi I Setup and hold time violation detection Simulation Power it ion 1 t Y PowerPlay Power Analyzer Settings Glitch detection j zl Simulation coverage reporting Report Settings Overwrite simulation input file with simulation results Disable setup and hold time violation detection for input registers of bi directional pins More Settings Description P the type of simulation to perform for the current Simulation focus Cancel 8 Inthe Category list click the icon to expand Simulator Settings 9 Select Simulation Power The Simulation Power page appears 10 Turn off Generate Signal Activity File and Generate VCD File 11 Click OK 12 On the Processing menu Click Start Simulation to run simulation 13 The Simulation was successful box appears Click OK 14 The Simulation Report window appears Verify the simulation waveform results Figure 2 28 2 34 Altera Corporation altmult_add Megafunction User Guide March 2007 Getting Started Figure 2 28 Timing Simulation Waveform a_imag a real b_imag b_real clk unsig_siga unsig_sigb result_imag result_real 3 1 3 1 0 j CS E E MFE Gr Er E E E EE cy A Ar Altera Corporation March 2007 Simulate the Complex Multiplier Design in ModelSim Altera To simulate the design in ModelSim compare the results of both simulat
16. Specifies saturation for the first and second multiplier 01 or the third and fourth multiplier 23 Values are NO YES and VARIABLE If omitted the default is NO 2 ADDER ROUNDING String Parameter 1 3 Specifies adder rounding for the first multiplier 1 or the third multiplier 3 Values are NO YES and VARIABLE If omitted the default is NO 2 PORT MULT IS_ SATURATED String Parameter 0 3 Specifies whether to use the corresponding mult is saturated output port Values are NO and YES If omitted the default is NO 2 PORT SIGN OUTPUT ROUNDING String String Parameter A B Specifies the corresponding sign input port usage Values are PORT USED PORT_UNUSED and PORT CONNECTIVITY If omitted the default is PORT _CONNECTIVITY Enables rounding handling at second adder stage If original design uses a Stratix II device in some cases this parameter can be derived from the Stratix Il rounding settings Values are YES NO and VARIABLE A value of YES or NO specifies saturation handling setting permanently to on or off A value of VARIABLE allows dynamically controlled saturation handling 7 OUTPUT _ROUND_TYPE String Specifies the rounding mode Values are NEAREST EVEN and NEAREST INTEGER e Avalue of NEAREST_EVEN specifies round to nearest even e A value of NEAREST INTEGER specifies round to nearest integer If omitted the default is N
17. and ACLR3 If omitted and CHAINOUT_REGISTER is used the default is ACLR3 7 ADDNSUB_MULTIPLIER_ REGISTER String Parameter 1 3 Specifies the clock signal for the first register on the corresponding addnsub input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If the corresponding addnsub port is UNUSED this parameter is ignored If omitted the default is CLOCKO 2 Altera Corporation March 2007 3 9 altmult_add Megafunction User Guide Ports and Parameters Table 3 3 altmult_add Megafunction Parameters Part 6 of 18 Parameter Type ADDSUB_MULTIPLIER_ ACLR String Required No Comments Parameter 1 3 Specifies the asynchronous clear signal for the first register on the corresponding addnsub input Values are ACLRO ACLR1 ACLR2 and ACLR3 If the corresponding addnsub port value is UNUSED this parameter is ignored If omitted and corresponding ADDNSUB MULTIPLIER REGISTER is used the default is ACLR3 2 ADDNSUB_MULTIPLIER_ PIPELINE REGISTER String Parameter 1 3 Specifies the clock signal for the second register on the corresponding addnsub input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If the corresponding addnsub portis UNUSED this parameter is ignored If omitted the default is CLOCKO 2 ADDNSUB_MULTIPLIER_ PIPELINE ACLR String Parameter 1 3 Specifies t
18. and simulate the design 2 11 altmult_add Megafunction User Guide Example 1 Generate a 9 x 9 Bit Multiplier Adder the Real Expression To generate a 9 x 9 bit multiplier adder perform the following steps 1 Open the altmult_add_DesignExample_ex1 zip file and extract cplx_mult qar In the Quartus II software open the cplx_mult qar project and restore the archive file into your working directory On the Tools menu click MegaWizard Plug In Manager The MegaWizard Plug In Manager dialog box appears Figure 2 1 on page 2 1 Select Create a new custom megafunction variation and click Next In the Which megafunction would you like to customize list click the icon to expand Arithmetic and select ALTMULT_ADD In the Which device family will you be using list select Stratix Under Which type of output file do you want to create select VHDL Specify the name of your output file as real_mul1t Figure 2 7 shows the wizard after you have made these selections 2 12 Altera Corporation altmult_add Megafunction User Guide March 2007 Getting Started Figure 2 7 MegaWizard Plug In Manager altmult_add Page 2a MegaWizard Plug In Manager page 2a Which megafunction would you like to customize Which device family will you be Stratix X Select a megafunction from the list below using J Installed Plug Ins Which type of output file do you want to create A Altera SOPC Builder C AHDL
19. fir_fourtap Category General Simulator Settings Files User Libraries Current Project Select simulation options Device Operating Conditions i i 7 Compilation Process Settings Simulation mode Functional x EDA Tool Settings Simulation input fir four _tap vwf ie Add multiple files Analysis amp Synthesis Settings Fitter Settings Simulation period E Timing Analysis rora i Run simulation until all vector stimuli are used TimeQuest Timing Analyzer Classic Timing Analyzer Settings End simulation at 1 us v Assembler Design Assistant IV Automatically add pins to simulation output waveforms SignalT ap Il Logic Analyzer Logic Analyzer Interface J Check outputs EZONE i upi Simulation Power PowerPlay Power Analyzer Settings T Glitch ct fi fr zl IV Simulation coverage reporting Report Settings I Overwrite simulation input file with simulation results fiz ible setup and hold tir ition detection for input More Settings Description Reports coverage that is the ratio of nodes actually simulated to the number of nodes in the netlist expressed as a percentage Cancel 10 In the Category list click the icon to expand Simulator Settings and select Simulator Power The Simulator Power page appears 11 Turn off Generate Signal Activity File and Generate VCD File 12 Click OK 13 On the Processing menu click Start Simulation to run a simulation 14 When
20. format should the result output bus be Available when device is Cyclone II HardCopy Il Stratix Il Stratix II GX or Stratix Ill and if the hardware saturation and rounding option is selected Specify the rounding format of result output bus Create a 4th asynchronous clear input option This forces all registers to have an associated asynchronous clear input Select to create an asynchronous clear input Create an associated clock enable for each clock Select to create an associated clock enable for each clock What is the representation format for A inputs Specify the representation format for A inputs When device is HardCopy Il Stratix II Stratix Il GX or Stratix III and if the hardware saturation and rounding option is selected representation format for A inputs is default to signed What is the representation format for B inputs Specify the representation format for B inputs When device is HardCopy II Stratix Il Stratix II GX or Stratix Ill and if the hardware saturation and rounding option is selected representation format for B inputs is default to signed signa input controls the sign 1 signed O unsigned Available when representation format for A inputs is variable Specify the input register and or pipeline register signb input controls the sign 1 signed O unsigned Available when representation format for B inputs is variable Sp
21. multiplier circuitry Not available for all families a ts 33 Click Next 34 Under Input Configuration turn on Register input A of the multiplier and click More Options The Data A input Register Configuration Multiplier 0 dialog box appears 35 In the What is the source for clock input list select Clock0 2 24 Altera Corporation altmult_add Megafunction User Guide March 2007 Getting Started Altera Corporation March 2007 36 37 38 39 40 41 42 43 44 45 46 In the What is the source for asynchronous clear input list select None Click Done Under Input Configuration turn on Register input B of the multiplier and click More Options The Data B input Register Configuration Multiplier 0 dialog box appears In the What is the source for clock input list select Clock0 In the What is the source for asynchronous clear input list select None Click Done Under Input Configuration select Multiplier input from both the What is the input A of the multiplier connected to and What is the input B of the multiplier connected to lists Under Output Configuration turn on Register output of the multiplier and click More Options The Output Register Configuration dialog box appears In the What is the source for clock input list select Clock0 In the What is the source for asynchronous clear input list select None Click Done Fig
22. position The value is determined by counting the bits that become the sign bits after saturation Values are calculated according to the following modes WIDTH_A WIDTH_B and WIDTH_RESULT Value must be an unsigned integer If a positive number is unavailable no saturation is allowed in your input output width and mode setting If omitted the default value is 1 3 OUTPUT SATURATE_ REGISTER String Specifies the clock source for the first register onthe output_ saturate input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is UNREGISTERED 1 OUTPUT SATURATE ACLR String Specifies the asynchronous clear source for the first register on the output_saturate input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and OUTPUT_SATURATE _ REGISTER is used the default value is ACLR3 1 Altera Corporation March 2007 3 13 altmult_add Megafunction User Guide Ports and Parameters Table 3 3 altmult_add Megafunction Parameters Part 10 of 18 Parameter Type OUTPUT_SATURATE _ String PIPELINE REGISTER Required No Comments Specifies the clock source for the second register on the output_saturate input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO 7 OUTPUT SATURATE_ PIPELINE ACLR String Specifies the asynchronous clear source for the second registe
23. qmegawiz This section provides descriptions of the options available on the individual pages of the altmult_add wizard Page 1 of the MegaWizard Plug In Manager is shown in Figure 2 1 Figure 2 1 MegaWizard Plug in Manager Page 1 MegaWizard Plug In Manager page 1 The MegaWizard Plug In Manager helps you create or modify design files that contain custom variations of megafunctions Which action do you want to perform Create a new custom megafunction variation Edit an existing custom megafunction variation Copy an existing custom megafunction variation Copyright 1991 2006 Altera Corporation Cancel Next gt 2 1 altmult_add Megafunction User Guide MegaWizard Page Descriptions You can choose to create edit or copy a custom megafunction variation On page 2a of the altmult_add wizard specify the plug in family of device you want to use type of output file to create and the name of the output file Figure 2 2 Choose AHDL tdf VHDL vhd or Verilog HDL v as the output file type You can also create a clearbox instantiation for third party EDA tools Figure 2 2 MegaWizard Plug In Manager Page 2a MegaWizard Plug In Manager page 2a Which megafunction would you like to customize Which device family will you be Stratis X ing Select a megafunction from the list below Gak Installed Plug Ins Which type of output file do you want to create E Altera SOPC Builder
24. represents the sequence of input samples and B t represents the filter coefficients This example implements a simple FIR filter with n 4 which is called a 4 tap filter The number of taps n can be any value but the example shown in Equation shows the FIR filter with four taps To implement this filter the coefficients of data B is loaded into the B registers in parallel and a shiftin register moves data A 0 toA 1 toA 2 and soon With a 4 tap filter at a given time T the sum of four products is computed This function is implemented using the shift register chain option in the altmult_add megafunction In the example shown in Equation input B represents the coefficients and data A represents the data that is shifted into The A input data is shifted in with the main clock clock0 The B input coefficients is loaded with clock1 rising edge and enable signal held high 2 37 altmult_add Megafunction User Guide Example 2 Design Files The design files are available in the Quartus II Projects section on the Design Examples page of the Altera web site http www altera com support examples quartus quartus html Select the Examples for altmult_add Megafunction User Guide link from the examples page to download the design files Example 2 This design example uses the altmult_add megafunction to create a multiplier add that targets the default implementation which goes into DSP blocks In this example you perfor
25. saturation WIDTH CHAININ Integer No Width of the chainin port WIDTH_CHAININ equals WIDTH_RESULT if port chainin is used If omitted the default value is 1 7 Altera Corporation 3 5 March 2007 altmult_add Megafunction User Guide Ports and Parameters Table 3 3 altmult_add Megafunction Parameters Part 2 of 18 Parameter INPUT REGISTER A Type String Required No Comments Parameter 0 3 Specifies the clock port for the dataa operand of the first multiplier Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default is CLOCK 0 For Stratix III devices values 1 3 should follow INPUT_REGISTER_AO INPUT _ACLR_A String Parameter 0 3 Specifies the asynchronous clear for the dataa operand of the first multiplier Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and corresponding INPUT_REGISTER_A is used the default is ACLR3 Values 1 3 should follow INPUT_ACLR_AO INPUT SOURCE _A String Parameter 0 3 Specifies the data source to the first multiplier Values are DATAA and SCANA If this parameter is set to DATAA the adder uses the values from the dataa port If this parameter is set to SCANA the adder uses values from the scan chain If omitted the default is DATAA For Stratix II devices a value of VARIABLE is also available REPRESENTATION A String Specifies the numerical representation of the d
26. the Simulation was successful box appears click OK 15 The Simulation Report window appears Verify the simulation waveform results Figure 2 41 Altera Corporation 2 51 March 2007 altmult_add Megafunction User Guide Example 2 Figure 2 41 Functional Simulation Waveform Simulation Waveforms Simulation mode Functional Master Time Bar Ops 4 gt Pointer Ops Interval Ops Start End v Ops 20 01ns 40 01ns 60 0ns 80 0ns 100 0ns 120 0ns 140 0ns 160 0ns 180 0ns 200 0ns 2 Ops a clockO E dataa_0 0 Ye XwWy2X3X4 V5 YON 3X N28 T E datab_0 3 L E datab_1 T E datab_2 5 E datab_3 Z on enal 4 E resut T EDEDED UA CIES UD ENCO EC ECD TSE NB T Z signa signb 2 ks Timing Results This section describes how to verify the timing after implementation using the Quartus II Simulator To set up the Quartus II Simulator perform the following steps 1 On the Assignments menu click Settings The Settings dialog box appears 2 Inthe Category list select Simulator Settings 3 Inthe Simulation mode list select Timing 4 Inthe Simulation Input box type fir four _tap vwf or click Browse to select the file in the project folder 5 Turn on the End simulation at type 1 and select us 6 Turn on Automatically add pins to simulation output waveforms and Simulation coverage reporting 7 Turn off Check outputs Setup and hold time violation detection Glitch detectio
27. the first register on the corresponding addnsub _ round input port Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and corresponding ADDNSUB _ ROUND_REGISTER is used the default is ACLR3 2 3 20 altmult_add Megafunction User Guide Altera Corporation March 2007 Specifications Table 3 3 altmult_add Megafunction Parameters Part 17 of 18 Parameter ADDNSUB ROUND PIPELINE ACLR Type String Required No Comments Parameter 1 3 Specifies the asynchronous clear source for the second register on the corresponding addnsub _ round input port Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and corresponding ADDNSUB__ _ ROUND PIPELINE REGISTER is used the default is ACLR3 2 ADDNSUB ROUND PIPELINE REGISTER ADDNSUB ROUND REGISTER String String Parameter 1 3 Specifies the clock source for the second register on the corresponding addnsub _round input port Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO 2 Parameter 1 3 Specifies the clock source for the first register on the corresponding addnsub _round input port Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO 2 DEDICATED MULTIPLIER CIRCUITRY String Specifies whether to use the DSP block to implement the circuit Values are YES NO and AUTO The circuit is i
28. the last multiplier Turn on Register output of the adder unit Click More Options The Output Register Configuration dialog box appears In the What is the source for clock input list select Clock0 In the What is the source for asynchronous clear input list select None Click Done Under Outputs configuration turn on Register output of the adder unit 2 23 altmult_add Megafunction User Guide Example 1 30 Under Outputs configuration turn on Register output of the adder unit 31 Under Adder Operation in the What operation should be performed on outputs of the first pair of multipliers list select Add 32 Under Implementation select Use logic elements Figure 2 19 shows the wizard after you have made these selections Figure 2 19 MegaWizard Plug In Manager Page 4 of 7 MegaWizard Plug In Manager page 4 of 7 Sg ALTMULT_ADD Version 6 1 Parameter Settings General gt gt Multipliers gt Outputs Configuration imag_mult H Create a shiftout output from A input of the last multiplier C Create a shiftout output from B input of the last multiplier MULTOJ Register output of the adder unit Adder Operation What operation should be performed on MULT1 outputs of the first pair of multipliers p Implementation datab Unsigned Which multiplier adder implementation should be used EE CO Use the default implementation Use dedicated
29. EAREST INTEGER 1 Altera Corporation March 2007 3 11 altmult_add Megafunction User Guide Ports and Parameters Table 3 3 altmult_add Megafunction Parameters Part 8 of 18 Parameter WIDTH _MSB Type Integer Required No Comments Specifies the fractional rounding width The value is determined by counting the bits from the MSB before saturation to the LSB after rounding Values are calculated according to the following modes WIDTH A WIDTH_B and WIDTH RESULT Value must be an unsigned integer and must be less than WIDTH RESULT If a positive number is unavailable no saturation is allowed in your input output width and mode setting If omitted the default value is 17 which is compatible with Stratix II device settings 2 OUTPUT _ROUND_REGISTER String Specifies the clock source for the first register on the output_round input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO 7 OUTPUT _ROUND_ACLR String Specifies the asynchronous clear source for the first register on the out put_ round input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and OUTPUT_ROUND REGISTER is used the default value is ACLR3 1 OUTPUT REGIS T ROUND PIPELINE TER OUTPUT ROUND PIPELINE _ ACLR String String Specifies the clock source for the second register on the output_ round input V
30. GISTER String Specifies the clock source for the first register on the chainout_saturate input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO 7 CHAINOUT_SATURATE ACLR String Specifies the asynchronous clear source for the first register on the chainout_saturate input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and CHAINOUT_SATURATE _ REGISTER is used the default value is ACLR3 1 CHAINOUT_SATURATE _ PIPELINE REGISTER String Specifies the clock source for the second register on the chainout_saturate input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO 7 Altera Corporation March 2007 3 15 altmult_add Megafunction User Guide Ports and Parameters Table 3 3 altmult_add Megafunction Parameters Part 12 of 18 Parameter CHAINOUT_SATURATE__ OUTPUT REGISTER Type String Required No Comments Specifies the clock source for the third register on the chainout_ saturate input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO 7 CHAINOUT_SATURATE _ OUTPUT_ACLR String Specifies the asynchronous clear source for the third register on the chainout_saturate input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and CHAINOUT_SATURATE _ OUTPUT_REGISTER is used the default va
31. OAD_ACLR Altera Corporation March 2007 String Specifies the asynchronous clear source for the first register on the accum_sload input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and ACCUM_SLOAD_ REGISTER is used the default value is ACLR3 7 3 17 altmult_add Megafunction User Guide Ports and Parameters Table 3 3 altmult_add Megafunction Parameters Part 14 of 18 Parameter Type ACCUM_SLOAD_PIPELINE_ String REGISTER Required No Comments Specifies the clock source for the second register on the accum_s1oad input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO 7 ACCUM_SLOAD PIPELINE_ String ACLR Specifies the asynchronous clear source for the second register on the accum_sload input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and ACCUM_SLOAD PIPELINE _ REGISTER is used the default value is ACLR3 1 SHIFT MODE String Specifies the shift mode Values are No LEFT RIGHT ROTATION and VARIABLE If VARIABLE is selected rotate and shift _right are used to specify shift left shift right or rotation If omitted the default value is NO 7 Note This parameter is supported only when inputs equal 32 bits each output equals 32 bits and the number of multipliers equals 1 ROTATE REGISTER String Specifies the clock source for the first register on the rotate input Values are UN
32. R1 ACLR2 and ACLR3 If omitted and corresponding MULTIPLIER_REGISTER is used the default is ACLR3 3 8 altmult_add Megafunction User Guide Altera Corporation March 2007 Specifications Table 3 3 altmult_add Megafunction Parameters Part 5 of 18 Parameter MUTIPLIER1 DIRECTION Type String Required No Comments Specifies whether the second multiplier adds or subtracts its value from the sum Values are ADD and SUB If the addnsub1 port is used this parameter is ignored If omitted the default is ADD MUTIPLIER3 DIRECTION String Specifies whether the fourth and all subsequent odd numbered multipliers add or subtract their results from the total Values are ADD and SUB If the addnsub3 port is used this parameter is ignored If omitted the default is ADD ACCUM_DIRECTION CHAINOUT_ REGISTER CHAINOUT_ACLR String String String Specifies whether to use the accumulator and whether the accumulator adds or subtracts its value from the sum Values are ADD and SUB If omitted the default is ADD Specifies the clock source for the chainout mode result register This is an additional stage after the second adder Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default is CLOCKO 7 Specifies the asynchronous clear for the chainout mode result register This is an additional stage after the second adder Values are ACLRO ACLR1 ACLR2
33. REGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO 1 ROTATE ACLR String Specifies the asynchronous clear source for the first register on the rotate input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and ROTATE REGISTER is used the default value is ACLR3 7 ROTATE PIPELINE _ String REGISTER Specifies the clock source for the second register on the rotate input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO 7 ROTATE PIPELINE ACLR String Specifies the asynchronous clear source for the second register on the rotate input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and ROTATE PIPELINE REGISTER is used the default value is ACLR3 1 3 18 altmult_add Megafunction User Guide Altera Corporation March 2007 Specifications Table 3 3 altmult_add Megafunction Parameters Part 15 of 18 Parameter ROTATE OUTPUT_ REGISTER Type String Required No Comments Specifies the clock source for the third register on the rotate input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO 7 ROTATE OUTPUT _ACLR String Specifies the asynchronous clear source for the third register on the rotate input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and ROTATE OUTPUT REGISTER is used the default v
34. String Required No Comments Specifies the asynchronous clear source for the third register on the shift right input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and SHIFT RIGHT OUTPUT _ REGISTER is used the default value is ACLR3 1 PORT_OUTPUT_IS_ OVERFLOW String Specifies port usage Values are PORT_UNUSED and PORT_USED When the value is set to PORT_USED output pin overflow is added If omitted the default value is PORT_UNUSED 1 PORT CHAINOUT_SAT IS_ OVERFLOW String Specifies port usage Values are PORT _UNUSED and PORT_USED When the value is set to PORT_USED output pin chainout_sat_overflow is added If omitted the default value is PORT_UNUSED 1 EXTRA _ LATENCY String Specifies the number of clock cycles of latency LPM_HINT String Allows you to specify Altera specific parameters in VHDL Design Files vhd The default is UNUSED LPM_TYPE String Identifies the library of parameterized modules LPM entity name in VHDL design files INTENDED DEVICE FAMILY String This parameter is used for modeling and behavioral simulation purposes Create the altmult_add megafunction with the MegaWizard Plug in Manager to calculate the value for this parameter DSP_BLOCK BALANCING String If omitted the default is AUTO ADDNSUB _ ROUND _ACLR String Parameter 1 3 Specifies the asynchronous clear source for
35. ack Next gt 7 Click Next Altera Corporation 2 21 March 2007 altmult_add Megafunction User Guide Example 1 10 11 12 13 14 15 16 17 18 19 20 21 22 2 22 In the What is the number of multipliers list select 2 Turn on All multipliers have similar configurations option In both the How wide should the A input buses be and How wide should the B input buses be lists select 9 In the How wide should the result output bus be list select 19 Turn off the Create a 4th asynchronous clear input option and Create an associated clock enable for each clock In the What is the representation format for A inputs list select Variable Click More Options for signa The signa Register Configuration dialog box appears Turn on Register signa input and Add an extra pipeline register Under input Register and Pipeline Register select the following options e Inthe What is the source for clock input list select Clock0 e Inthe What is the source for asynchronous clear input list select None Click Done In the What is the representation format for B inputs list select Variable Click More Options for signb The signb Register Configuration dialog box appears Turn on Register signb input and Add an extra pipeline register Under input Register and Pipeline Register select the following options e Inthe What is the so
36. ally the Altera provided functions may offer more efficient logic synthesis and device implementation You can scale the megafunction s size by simply setting parameters The altmult_add megafunction implements a basic adder multiplier and offers many additional features including Parameterizable input data and output data widths Active high asynchronous clear and clock enable control inputs Support for both signed and unsigned data representation formats Ability to add or subtract the product pair Facility to added extra latency to have additional registers required to pipeline the output of the multiplier adder The altmult_add megafunction allows you to implement a multiplier adder A multiplier adder accepts pairs of inputs The members of each pair are multiplied together and the multiplier adder then adds or subtracts the products of all other pairs This function can be expressed as an equation Equation 1 y AoBo A B A B In this equation n denotes the number of pairs 1 1 altmult_add Megafunction User Guide General Description Figure 1 1 illustrates a basic multiplier adder with two pair of 2 bit inputs Figure 1 1 Basic 2 bit Input Multiplier Adder AO 1 0 ic Bo 1 0 A Y 4 0 A1 1 0 a ae J B1 1 0 A The altmult_add variations provide the following options for your design These include the ability to Change the operation to subtraction i
37. altmult_add Megafunction A DTE RYAN 101 Innovation Drive San Jose CA 95134 408 544 7000 www altera com User Guide Quartus II Software Version Document Version Document Date 7 0 2 3 March 2007 Copyright 2007 Altera Corporation All rights reserved Altera The Programmable Solutions Company the stylized Altera logo specific device des ignations and all other words and logos that are identified as trademarks and or service marks are unless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other countries All other product or service names are the property of their respective holders Al tera products are protected under numerous U S and foreign patents and pending applications maskwork rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the ap plication or use of any information product or service described herein except as expressly agreed to in writing by Altera NSAI Corporation Altera customers are advised to obtain the latest version of device specifications before relying on any published in formation and before placing orders for products or services I S EN ISO 9001 UG 030805 2 3 ii Altera Corporation altm
38. alue is ACLR3 7 SHIFT RIGHT REGISTER String Specifies the clock source for the first register onthe shift right input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO 7 SHIFT RIGHT ACLR String Specifies the asynchronous clear source for the first register on the shift right input Values are NONE ACLRO ACLR1 ACLR2 and ACLR3 If omitted and SHIFT_RIGHT_REGISTER is used the default value is ACLR3 7 SHIFT RIGHT PIPELINE_ REGISTER String Specifies the clock source for the second register on the shift right input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO 7 SHIFT RIGHT PIPELINE_ ACLR String Specifies the asynchronous clear source for the second register on the shift right input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and SHIFT RIGHT PIPELINE _ REGISTER is used the default value is ACLR3 1 SHIFT RIGHT OUTPUT_ REGISTER String Specifies the clock source for the third register onthe shift right input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO 7 Altera Corporation March 2007 3 19 altmult_add Megafunction User Guide Ports and Parameters Table 3 3 altmult_add Megafunction Parameters Part 16 of 18 Parameter SHIFT RIGHT OUTPUT ACLR Type
39. alues are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO 7 Specifies the asynchronous clear source for the second register on the output_round input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and OUTPUT_ROUND_ PIPELINE _ REGISTER is used the default value is ACLR3 1 3 12 altmult_add Megafunction User Guide Altera Corporation March 2007 Specifications Table 3 3 altmult_add Megafunction Parameters Part 9 of 18 Parameter OUTPUT _ SATURATION Type String Required No Comments Enables saturation handling at second adder stage If original design uses a Stratix II device in some cases this parameter can be derived from the Stratix II rounding settings Values are YES NO and VARIABLE A value of YES or NO specifies saturation handling setting permanently to on or off A value of VARIABLE allows dynamically controlled saturation handling If omitted the default value is NO 7 OUTPUT SATURATE TYPE String Specifies the saturation mode Values are SYMMETRIC and ASYMMETRIC A value of SYMMETRIC specifies the absolute value of the maximum negative number equal to the maximum positive number A value of ASYMMETRIC specifies the maximum negative number as large as the maximum positive number If omitted the default value is ASYMMETRIC 3 E Eal WIDTH_SATURATE_SIGN String Specifies the saturation
40. and save valuable design time Altera recommends using these functions during design implementation so you can consistently meet your design goals 2 56 Altera Corporation altmult_add Megafunction User Guide March 2007 Chapter 3 Specifications Ports and Parameters Altera Corporation March 2007 The options listed in this section describe all of the ports and parameters that are available for each device to customize the altmult_add megafunction according to your application Figure 3 1 shows the ports and parameters for the altmult_add megafunction Figure 3 1 Port and Parameter Description ALTMULT_ADD addnsub1 addnsub3 clockO enal chainout_sat_overflow clock1 enat clock2 ena2 clock3 ena3 output_round output_saturate chainout_round chainout_saturate zero_chainout accum_sload zero_loopback chainin shift_right rotate acirO i aciri i aclr2 aclr3 Table 3 1 shows the input ports Table 3 2 shows the output ports and Table 3 3 shows the parameters for the altmult_add megafunction 3 1 altmult_add Megafunction User Guide Ports and Parameters The parameter details are only relevant for users who by pass the MegaWizard Plug In Manager interface and use the megafunction as a directly parameterized instantiation in their design The details of these parameters are hidden from the user of the MegaWizard Plug In Manager interface Refer to the latest version of the Qua
41. arameter 0 3 Specifies the clock port for the datab operand of the corresponding multiplier Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default is CLOCKO INPUT_ACLR B String Parameter 0 3 Specifies the asynchronous clear for the datab operand of the corresponding multiplier Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and corresponding INPUT_REGISTER_B is used the default is ACLR3 INPUT_SOURCE_B String Parameter 0 3 Specifies the data source of the corresponding multiplier Values are DATAB SCANB and VARIABLE If this parameter is set to DATAB then the adder uses the values from the datab port If this parameter is set to SCANB then the adder uses values from the scan chain If omitted the default is DATAB Stratix devices support value DATAB only Stratix Il devices support values DATAB SCANB and VARIABLE only Stratix III devices supports values DATAB SCANB and LOOPBACK LOOPBACK value is in sum2 mode MULTIPLIER REGISTER String Parameter 0 3 Specifies the clock source for the register immediately following the corresponding multiplier Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default is CLOCKO MULTIPLIER ACLR String Parameter 0 3 Specifies the asynchronous clear signal for the register immediately following the corresponding multiplier Values are ACLRO ACL
42. asynchronous clear input Pipeline Register What is the source for clock input What is the source for asynchronous clear input ClockO M None Clock0 M None 20 Turn on Register signb input and Add an extra pipeline register 21 Under both Input Register and Pipeline Register select the following options e Inthe What is the source for clock input option select Clock e Inthe What is the source for asynchronous clear input option select None 22 Click Done Figure 2 10 shows the wizard after you have made these selections Altera Corporation 2 15 March 2007 altmult_add Megafunction User Guide Example 1 Figure 2 10 MegaWizard Plug In Manager altmult_add Page 3 of 7 MegaWizard Plug In Manager page 3 of 7 E ALTMULT_ADD Version 6 1 Parameter f Simulation Summary ttings Library Page General gt Extra Modes 5 Multiplier Currently selected device family real_mult r General What is the number of multipliers multipliers M All multipliers have similar configurations How wide should the A input buses be MULTOJ How wide should the B input buses be How wide should the result output bus be Create a 4th asynchronous clear input option This forces all registers to have an associated asynchronous clear input Create an associated clock enable for each dock Inpu
43. ataa port Values are UNSIGNED and SIGNED When this parameter is set to UNSIGNED the adder interprets the dataa input as an unsigned number When this parameter is set to SIGNED the adder interprets the dataa input as a signed two s complement number If the signa port is used this parameter is ignored If omitted the default is UNSIGNED REPRESENTATIONS B String Specifies the numerical representation of the datab port Values are UNSIGNED and SIGNED When this parameter is set to UNSIGNED the adder interprets the datab input as an unsigned number When this parameter is set to SIGNED the adder interprets the datab input as a signed two s complement number If the signb port is used this parameter is ignored If omitted the default is UNSIGNED 3 6 altmult_add Megafunction User Guide Altera Corporation March 2007 Specifications Table 3 3 altmult_add Megafunction Parameters Part 3 of 18 Parameter SIGNED REGISTER Type String Required No Comments Parameter A B Specifies the clock signal for the first register on the corresponding sign port Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If the corresponding sign port value is UNUSED this parameter is ignored If omitted the default is CLOCKO SIGNED_ACLR_ String Parameter A B Specifies the asynchronous clear signal for the first register on the corre
44. ation format for A inputs option select Variable Click More Options for signa The signa Register Configuration dialog box appears Figure 2 8 2 13 altmult_add Megafunction User Guide Example 1 Figure 2 8 signa Register Configuration signa Register Configuration M Register signa input Add an extra pipeline register Input Register What is the source for clock input Clock0 M What is the source for asynchronous clear input None Pipeline Register What is the source for clock input ClockO What is the source for asynchronous clear input None 15 16 17 18 19 2 14 Turn on Register signa input and Add an extra pipeline register Under both input Register and Pipeline Register select the following options e Inthe What is the source for clock input option select Clock e Inthe What is the source for asynchronous clear input option select None Click Done In the What is the representation format for B inputs option select Variable Click More Options for signb The signb Register Configuration dialog box appears Figure 2 9 Altera Corporation altmult_add Megafunction User Guide March 2007 Getting Started Figure 2 9 signh Register Configuration signb Register Configuration Mi Add an extra pipeline register Input Register What is the source for clock input What is the source for
45. box appears In the Category list select Simulator Settings The Simulator Settings page appears In the Simulation mode list select Timing In the Simulation Input box type altmult_add vwf or click Browse to select the file in the project folder Under Simulation period select End simulation at type 1 and select us Turn on Automatically add pins to simulation output waveforms and Simulation coverage reporting Turn off Check outputs Setup and hold time violation detection Glitch detection and Overwrite simulation input file with simulation results Figure 2 27 shows the Settings dialog box after you have made these selections 2 33 altmult_add Megafunction User Guide Example 1 Figure 2 27 Simulator Settings Page Settings cplx_mult Category General Simulator Settings Files User Libraries Current Project Select simulation options Device Operating Conditions i i p Compilation Process Settings Simulatori mods Timing E EDA Tool Settings Simulation input altmult_add vf ie Add multiple files Analysis amp Synthesis Settings Fitter Settings Simulation period Timing Analysis Settings Run simulation until all vector stimuli are used TimeQuest Timing Analyzer Classic Timing Analyzer Settings End simulation at 1 us X Assembler Design Assistant JV Automatically add pins to simulation output waveforms SignalT ap Il Logic Analyzer we Logic Analyzer
46. ced in the dedicated DSP Block circuitry of Stratix devices If all of the input data widths are 9 bits wide or smaller the function uses the 9 x 9 bit input multiplier configuration in the DSP Block If not the DSP block uses 18 x 18 bit input multipliers to process data with widths between 10 bits 1 3 altmult_add Megafunction User Guide General Description and 18 bits If multiple altmult_add megafunctions occur in a design the functions are distributed to as many different DSP blocks as possible so that routing to these blocks is more flexible Fewer multipliers per DSP block allow more routing choices into the block by minimizing paths to the rest of the device The registers and extra pipeline registers for the following signals are also placed inside the DSP block Data input Signed unsigned select Add subtract select Products of multipliers In the case of the output result the first register is placed in the DSP block however the extra latency registers are placed in logic elements outside the block Peripheral to the DSP block including data inputs to the multiplier control signal inputs and outputs of the adder use regular routing to communicate with the rest of the device All connections in the function use dedicated routing inside the DSP block This dedicated routing includes the shift register chains when you select the option to shift a multiplier s registered input data from one multiplier to an adjacent mult
47. chronous clear source for the first register on the zero_loopback input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and ZERO_LOOPBACK _ PIPELINE REGISTER is used the default value is ACLR3 7 ZERO LOOPBACK PIPELINE REGISTER String Specifies the clock source for the second register on the zero_loopback input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO 7 ZERO LOOPBACK PIPELINE ACLR String Specifies the asynchronous clear source for the second register on the zero_ loopback input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and ZERO_LOOPBACK _ PIPELINE REGISTER is used the default value is ACLR3 1 ZERO_LOOPBACK_OUTPUT_ REGISTER String Specifies the clock source for the third register onthe zero loopback input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO 7 ZERO LOOPBACK OUTPUT _ ACLR String Specifies the asynchronous clear source for the third register on the zero_ loopback input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and ZERO LOOPBACK OUTPUT _ REGISTER is used the default value is ACLR3 1 ACCUM _SLOAD_REGISTER String Specifies the clock source for the first register on the accum_sload input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO 7 ACCUM_SL
48. ction from the list below dh 4 Installed Plug Ins Which type of output file do you want to create A Altera SOPC Builder C AHDL Arithmetic ALTACCUMULATE Se ALTFP_ADD_SUB C Verilog HDL ALES MKT What name do you want for the output file Browse ALTMEMMULT jings mmitchel Local Settings T emp fir_fourtap_restored fir_fourtap ALTMULT_ACCUM MAC ALTMULT_ADD Generate clear box netlist file instead of a default wrapper file ALTSQRT for use with supported EDA synthesis tools only LPM_ABS LPM_ADD_SUB LPM_COMPARE Note To compile a project successfully in the Quartus II software LPM COUNTER your design files must be in the project directory in the global user LPM DIVIDE libraries specified in the Options dialog box Tools menu or a user LPM MULT library specified in the User Libraries page of the Settings dialog box Assignments menu PARALLEL_ADD Communications Your current user library directories are a DSP aj Gates a 1 0 J Interfaces a Memory Compiler I Return to this page for another create operation Cancel lt Back Next gt 8 Click Next 9 Inthe What is the number of multipliers list select 4 10 Turn on All multipliers have similar configurations 11 In both the How wide should the A input busses be and How wide should the B input busses be lists select 16 12 In the How wide should the result output bus be list select 34 13 Turn off the Creat
49. d Numbered steps are used in a list of items when the sequence of the Items is a b c etc important such as the steps listed in a procedure E o Bullets are used in a list of items when the sequence of the items is not important Y The checkmark indicates a procedure that consists of one step only Ls The hand points to information that requires special attention A caution calls attention to a condition or possible situation that can damage or CAUTION destroy the product or the user s work A warning calls attention to a condition or possible situation that can cause injury to the user The angled arrow indicates you should press the Enter key oP The feet direct you to more information on a particular topic vi altmult_add Megafunction User Guide Altera Corporation March 2007 N DTE RYN 1 About this Megafunction Device Family Support Introduction Features General Description Altera Corporation March 2007 The altmult_add megafunction supports the following target Altera device families Stratix series Cyclone series HardCopy series MAX series APEX series ACEX devices FLEX series As design complexities increase use of vendor specific IP blocks has become a common design methodology Altera provides parameterizable megafunctions that are optimized for Altera device architectures Using megafunctions instead of coding your own logic saves valuable design time Addition
50. dd megafunction wizard specify where the inputs of the multiplier are connected Connect inputs to either the multiplier input or shift input Register the multiplier outputs and inputs Figure 2 5 Figure 2 5 MegaWizard Plug In Manager altmult_add Page 5 of 7 MegaWizard Plug In Manager page 5 of 7 Input Configuration Register input A of the multiplier More Options M Register input B of the multiplier More Options What is the input A of the multiplier connected to Multiplier input 4 What is the input B of the multiplier connected to Multiplier input 4 Output Configuration M Register output of the multiplier 2 6 Altera Corporation altmult_add Megafunction User Guide March 2007 Getting Started Table 2 3 shows the options available on page 5 of the altmult_add MegaWizard Plug In Manager Table 2 3 altmult_add Plug In Manager Page 5 Options Function Register input A of the multiplier Description Select to create register for input A of the multiplier Select More Options to configure the register Register input B of the multiplier Select to create register for input B of the multiplier Select More Options to configure the register What is the input A of the multiplier connected to Specify if input A of the multiplier is connected to a multiplier input or shiftin input What is the input B o
51. dialog box appears Figure 2 13 Figure 2 13 Data B Input Register Configuration Multiplier 0 Data B Input Register Configuration Multiplie What is the source for clock input ClockO B What is the source for asynchronous clear input None E 38 39 40 41 42 2 18 In the What is the source for clock input list select Clock0 In the What is the source for asynchronous clear input list select None Click Done Under Input Configuration in both the What is the input A of the multiplier connected to and What is the input B of the multiplier connected to lists select Multiplier input Under Output Configuration turn on Register output of the multiplier Click More Options The Output Register Configuration Multiplier 0 dialog box appears Figure 2 14 Altera Corporation altmult_add Megafunction User Guide March 2007 Getting Started Figure 2 14 Output Register Configuration Multiplier 0 Output Register Configuration Multiplier 0 x What is the source for clock input ClockO v What is the source for asynchronous clear input None 43 45 In the What is the source for clock input list select Clocko In the What is the source for asynchronous clear input list select None Click Done Figure 2 15 shows the wizard after you have made these selections Figure 2 15 MegaWizard Plug In Manager altmult_add Page 5 of 7
52. e a 4th asynchronous clear input option 14 Turn on Create an associated clock enable for each clock 15 In the What is the representation format for A inputs list select Variable Altera Corporation 2 39 March 2007 altmult_add Megafunction User Guide Example 2 16 17 18 Click More Options for signa The signa Register Configuration dialog box appears Turn on Register signa input and Add an extra pipeline register Under both input Register and Pipeline Register select the following options e Inthe What is the source for clock input list select Clock0 e Inthe What is the source for asynchronous clear input list select None Figure 2 32 shows the signa Register Configuration dialog box after you have made these selections Figure 2 32 signa Register Configuration Dialog Box signa Register Configuration Register signa input Add an extra pipeline register Input Register What is the source for clock input ClockO What is the source for asynchronous dear input None v Pipeline Register What is the source for dock input ClockO 9 What is the source for asynchronous clear input None Ej Cancel 19 20 21 22 23 2 40 Click Done In the What is the representation format for B inputs list select Variable Click More Options for signb The signb Register Configuration dialog box appears Turn on the R
53. ecify the input register and or pipeline register On page 4 of the altmult_add wizard specify which operation is performed on the first pair of Add Sub multipliers and select the implementation type Specify whether to use default or dedicated multiplier circuitry or logic elements Figure 2 4 i 2 4 altmult_add Megafunction User Guide This parameter is available only for Stratix series and HardCopy Stratix devices Altera Corporation March 2007 Getting Started Figure 2 4 MegaWizard Plug In Manager altmult_add Page 4 of 7 MegaWizard Plug In Manager page 4 of 7 ALTMULT_ADD Version 6 1 Parameter Settings General gt Multipliers gt real_mult MULTOJ MULTI Outputs Configuration C Create a shiftout output from A input of the last multiplier C Create a shiftout output from B input of the last multiplier Register output of the adder unit More Options Adder Operation What operation should be performed on outputs of the first pair of multipliers Subtract Implementation Which multiplier adder implementation should be used Use the default implementation 2 alt_mac_multt 1 alt_mac_out Use dedicated multiplier circuitry Not available for all families Use logic elements lt Back Table 2 2 shows the options available on page 4 of the altmult_add MegaWizard Plug In Manager Funct
54. ecking or unchecking its corresponding checkbox respectively The state of checkboxes will be remembered for the next MegaWizard Plug In Manager session MULTOJ The MegaWizard Plug In Manager will create these files in the directory C Documents and Settings mmitchel Local Settings Temp fir_fourtap_restored Z fir_fourtap vhd Variation file O fit_fourtap ine AHDL Include file E fir_fourtap cmp VHDL Component declaration file O fit_fourtap bst Quartus symbol file E fir_fourtap_inst vhd Instantiation template file 50 Click Finish Altera Corporation 2 47 March 2007 altmult_add Megafunction User Guide Example 2 Implement the FIR 4 Tap Design This section describes how to assign the EP1S10F780C5 device to the project and compile the project in the Quartus II software 1 2 48 On the Assignments menu click Device The Settings dialog box appears In the Family list select Stratix Under Target device click Specific device selected in Available devices list Under Show in Available devices list select the following settings e Inthe Package list select FBGA e Inthe Pin count list select 780 e Inthe Speed grade list select 5 In the Available devices list select EP1S10F780C5 Figure 2 39 shows the wizard after you have made these selections Altera Corporation altmult_add Megafunction User Guide March 2007 Getting Started F
55. egister signb input and Add an extra pipeline register options Under both input Register and Pipeline Register select the following options e Inthe What is the source for clock input list select Clock1 Altera Corporation altmult_add Megafunction User Guide March 2007 Getting Started e Inthe What is the source for asynchronous clear input list select None Figure 2 33 shows the signa Register Configuration dialog box after you have made these selections Figure 2 33 signb Register Configuration Dialog Box signb Register Configuration M Register signb input Mi Add an extra pipeline register Input Register What is the source for clock input Clock E Whatis the source for asynchronous dear input None E Pipeline Register What is the source for clock input Clock1 K What is the source for asynchronous clear input None E Cancel 24 Click Done Figure 2 34 shows the wizard after you have made these selections Altera Corporation 2 41 March 2007 altmult_add Megafunction User Guide Example 2 Figure 2 34 altmult_add Wizard Page 3 MegaWizard Plug In Manager page 3 of 7 ALTMULT_ADD Version 6 1 Parameter 2 Simulation E Summary Settings Library Page gt Extra Modes gt Multipliers gt Currently selected device family fir_fourtap r General What is the number of multipliers M All multipliers have similar configurations
56. esource usage for an altmult_add function used to implement an 8 bit signed multiplier You can force the compiler to implement the function in logic resources or DSP blocks or allow the compiler to use the default implementation Table 1 1 altmult_add Resource Usage Part 1 of 2 Note 1 Device Family Optimization 2 width _ b 9 DSP Blocks Elements Balanced 9 bit Balanced 16 bit 4 Stratix Il Balanced 9 bit 182 ALUT Balanced 16 bit 513 ALUT Altera Corporation 1 5 March 2007 altmult_add Megafunction User Guide Resource Utilization and Performance Table 1 1 altmult_add Resource Usage Part 2 of 2 Note 1 ede ae Logic Device Family Optimization 2 Width Elements DSP Blocks Balanced 9 bit Balanced 16 bit Stratix GX Balanced 9 bit Balanced 16 bit Balanced 9 bit 2 Balanced 16 bit 4 Stratix Balanced 9 bit 311 Balanced 16 bit 777 Balanced 9 bit 2 Balanced 16 bit 4 HardCopy Stratix Balanced 9 bit 324 Balanced 16 bit 798 Balanced 9 bit 293 Cyclone II Balanced 16 bit 756 Balanced 9 bit 311 _ Cyclone Balanced 16 bit 777 Note to Table 1 1 1 The performance information is available from the MegaWizard The information in this table is valid and accurate as of this document release 2 Choose a design imple
57. f the multiplier connected to Specify if input B of the multiplier is connected to a multiplier input or shiftin input Register output of the multiplier Select to create a register for the output of the multiplier Select More Options to configure the register On page 7 of the altmult_add megafunction wizard specify the types of files to be generated You can choose from the HDL wrapper file lt function name gt v vhd tdf Block Symbol file bsf instantiation template file lt function name gt _inst v or Verilog Black Box declaration file lt function name gt _bb v Figure 2 6 The HDL generated wrapper files Verilog HDL VHDL or AHDL are selected automatically based on the choices you make on page 6 of the wizard Altera Corporation March 2007 2 7 altmult_add Megafunction User Guide MegaWizard Page Descriptions Figure 2 6 MegaWizard Plug In Manager altmult_add Page 7 of 7 MegaWizard Plug In Manager page 7 of 7 Summary ALTMULT_ADD Ea Parameter Summary Settings Library Turn on the files you wish to generate A gray checkmark indicates a file that is automatically generated and a red checkmark indicates an optional file Click Finish to generate the selected files The state of each checkbox is maintained in subsequent MegaWizard Plug In Manager sessions real_mult MULTOJ The MegaWizard Plug In Manager creates the selected files in the following direct
58. function using the Node Finder click the browse button in the Look In box and select the megafunction in the Select Hierarchy Level dialog box 2 9 altmult_add Megafunction User Guide Simulation Simulation 2 10 The Quartus II Simulator provides an easy to use integrated solution for performing simulations The following sections describe the simulation options Quartus II Simulator With the Quartus II Simulator you can perform functional and timing simulations A functional simulation in the Quartus II software enables you to verify the logical operation of your design without taking into consideration the timing delays in the FPGA This simulation is performed using only your RTL code When performing a functional simulation you are able to view signals that exist before synthesis You can find these signals with the Registers pre synthesis Design Entry or Pin filters in the Node Finder The top level ports of megafunctions are found using these three filters By contrast timing simulations in the Quartus II software verify the operation of your design with annotated timing information This simulation is performed using the post place and route netlist When performing a timing simulation you can view signals that exist after place and route These signals are found with the Post Compilation filter in the Node Finder During synthesis and place and route the names of your RTL signals change Therefore it might be diff
59. he asynchronous clear signal for the second register on the corresponding addnsub input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and corresponding ADDNSUB_MULTIPLIER_ PIPELINE REGISTER is used the default is ACLR3 2 OUTPUT REGISTER String OUTPUT _ACLR String Specifies the clock signal for the second adder register Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default is CLOCKO Specifies the asynchronous clear signal for the second adder register Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted the default is ACLR3 PORT _ADDNSUB String Parameter 1 3 Specifies the usage of the corresponding addnsub input port Values are PORT_USED PORT UNUSED and PORT CONNECTIVITY A value of PORT CONNECTIVITY specifies the port usage by checking port connectivity If omitted the default is PORT _CONNECTIVITY 2 3 10 altmult_add Megafunction User Guide Altera Corporation March 2007 Specifications Table 3 3 altmult_add Megafunction Parameters Part 7 of 18 Parameter MULTIPLIER ROUNDING Type String Required No Comments Parameter 01 23 Specifies rounding for the first and second multiplier 01 or the third and fourth multiplier 23 Values are NO YES and VARIABLE If omitted the default is NO 2 MULTIPLIER SATURATION String Parameter 01 23
60. he Data A input Register Configuration Multiplier 0 dialog box appears 35 In the What is the source for clock input list select Clock0 36 Inthe What is the source for asynchronous clear input list select None 37 Click Done 2 44 Altera Corporation altmult_add Megafunction User Guide March 2007 Getting Started Altera Corporation March 2007 38 39 40 41 42 43 44 45 46 Under Input Configuration turn on Register input B of the multiplier and click More Options The Data B input Register Configuration Multiplier 0 dialog box appears In the What is the source for clock input list select Clock1 In the What is the source for asynchronous clear input list select None Click Done Under Input Configuration in the What is the input A of the multiplier connected to list select Shiftin input and in the What is the input B of the multiplier connected to list select Multiplier input Under Output Configuration turn on Register output of the multiplier and click More Options The Output Register Configuration Multiplier 0 dialog box appears In the What is the source for clock input list select Clock0 In the What is the source for asynchronous clear input list select None Click Done Figure 2 37 shows the wizard after you have made these selections 2 45 altmult_add Megafunction User Guide Example 2 Figure 2 37 altmult_add Wizard Page 5 MegaW
61. his will force all inputs to be in Q1 15 format Specify if all the multipliers have the same configurations If unchecked individual settings is done for every multiplier This option is selected by default when device is Stratix III Available when device is Cyclone II HardCopy II Stratix II or Stratix II GX Select hardware saturation and rounding support Default rounding for all input is set to Q1 15 format fixed point arithmetic notation with 15 bits of precision Altera Corporation March 2007 2 3 altmult_add Megafunction User Guide MegaWizard Page Descriptions Table 2 1 altmult_add Plug In Manager Page 3 Options Part 2 of 2 Function Add hardware support for hardware saturation and rounding Description Only available when device is Stratix III Select hardware saturation and rounding support How wide should the A input buses be Specify the width of A input buses If device is Cyclone II HardCopy II Stratix Il Stratix II GX or Stratix III the width of A is fixed at 16 bits when hardware saturation and rounding is selected How wide should the B input buses be Specify the width of B input buses If device is Cyclone II HardCopy II Stratix Il Stratix II GX or Stratix IIl the width of A is fixed at 16 bits when hardware saturation and rounding is selected How wide should the result output bus be Specify the width of result output buses In what
62. icult to find signals from your megafunction instantiation in the Post Compilation filter However if you want to preserve the names of your signals during the synthesis and place and route stages you must use the synthesis attributes keep or preserve These are Verilog and VHDL synthesis attributes that direct analysis and synthesis to keep a particular wire register or node intact You can use these synthesis attributes to keep a combinational logic node so you can observe the node during simulation For more information refer to the Quartus II Integrated Synthesis chapter in volume 1 of the Quartus IT Handbook EDA Simulation Depending on which third party simulation tool you are using refer to the appropriate chapter in the Simulation section in volume 3 of the Quartus II Handbook These tool specific chapters show you how to perform functional and gate level timing simulations that include the megafunctions including the necessary files and directories where the files are located Altera Corporation altmult_add Megafunction User Guide March 2007 Getting Started SignalTap Il Embedded Logic Analyzer Design Example Complex Multiplication Example 1 Altera Corporation March 2007 The SignalTap II Embedded Logic Analyzer provides you with a method of debugging all of the Altera megafunctions within your design With the SignalTap II Embedded Logic Analyzer you can capture and analyze data samples for the top le
63. ignb No Specifies the numerical If the signb port is high the multiplier treats representation of the the datab port as a signed two s datab port complement number If the signb portis low the multiplier treats the datab port as an unsigned number scanina No Input for scan chain A Input port WIDTH_A 1 0 wide When the INPUT_SOURCE_A parameter has a value of SCANA or VARIABLE the scanina portis required Do not use scanina and scaninb simultaneously 2 scaninb No Input for scan chain B Input port WIDTH _B 1 0 wide When the INPUT_SOURCE_A parameter has a value of SCANB or VARIABLE the scaninb portis required Do not use scanina and scaninb simultaneously 2 sourcea No Input source for scan 2 chain A sourceb No Input source for scan 2 3 3 altmult_add Megafunction User Guide Ports and Parameters Table 3 1 altmult_add Megafunction Input Ports Part 3 of 3 Port Name Required Description Comments addnsub1 No Controls the If the addnsub1 port is high the adder functionality of the performs an add function If the addnsub1 adder port is low the adder performs a subtract function 2 addnsubl_ round No Enables adding or subtracting for the second multiplier 2 addnsub3 No Controls the functionality of the adder If the addnsub3 port is high the adder performs an add function If the addnsub3 port is low the adder performs a subtract function
64. igure 2 39 Device Settings Settings fir_fourtap Category General Files User Libraries Current Project Select the family and device you want to target for compilation Device Operating Conditions 7 Compilation Process Settings Fami Strati c Package FBGA EDA Tool Settings Device amp Pin Options z Analysis amp Synthesis Settings Pin count 780 X Fitter Settings r Target device Timing Analysis Settings Auto device selected by the Fitter Speed grade 5 z TimeQuest Timing Analyzer 5 Specific device selected in Available devices list Core voltage 1 5 Classic Timing Analyzer Settings C ot Assembler E IV Show advanced devices Design Assistant 7 I HardCopy compatible only SignalT ap II Logic Analyzer Available devices Logic Analyzer eters Mame Ls Mem osp ea o Simulator Settings EP1510F780C5 1057 0 920448 6 6 2 Simulation Power EP1S10F780C5ES 10570 920448 PowerPlay Power Analyzer Settings EP1S20F780C5 18460 1669248 EP1S25F780C5 25660 1944576 EP1S30F780C5 32470 3317184 EPIS30F780C5_HARDC 32470 2137536 EP1S40F780C5 41250 3423744 EP1540F780C5_HARDC 41250 2244096 z Show in Available devices list NNNNNN NG Migration compatibility p Companion device Migration Devices HardCopy Il l z O migration devices selected VV Limit DSP amp RAM to HardCopy I device resource Cancel 6 Leave the other options i
65. iles User Libraries Current Project Device Operating Conditions Compilation Process Settings EDA Tool Settings Analysis amp Synthesis Settings Fitter Settings Timing Analysis Settings TimeQuest Timing Analyzer Classic Timing Analyzer Settings Assembler Design Assistant SignalT ap Il Logic Analyzer Logic Analyzer Interface Simulator Settings PowerPlay Power Analyzer Settings Select the design files you want to include in the project Click Add All to add all design files in the Project directory to the project Fier Add File name Type Add All teal_mult vhd VHDL File imag_mult vhd VHDL File cplx_mult vhd VHDL File alt_muladd vwf Vector Wavef cplx_mult_timing sim Other cplx_mult_func sim Other cplx_mult_timing vwf Vector Wave cplx_mult_func vw Vector Wave Cancel 2 28 4 Click browse to select the cplx_mult vhd file in the project folder click Open and click Add in the Settings dialog box to add the file to the project Click OK The top level file is now added to the project You have now created a complete design file Figure 2 23 Note that this image is extracted from the symbol file which we have not created in this design example Altera Corporation altmult_add Megafunction User Guide March 2007 Getting Started Figure 2 23 Complex Multiplier Design File rea _mut
66. ion Create a shiftout output from A input of the last multiplier Table 2 2 altmult_add Plug In Manager Page 4 Options Part 1 of 2 Select to create a shiftout output When device is Stratix Ill More Description Options is available for shiftout register configuration Create a shiftout output from B input of the last multiplier Select to create a shiftout output This option is not available when device is Stratix III Register output of the adder unit Select to create register to the output What operation should be performed on outputs of the first pair of multipliers Specify the operation to be performed on the outputs of the first pair of multipliers What operation should be performed on outputs of the second pair of multipliers Altera Corporation March 2007 Specify the operation to be performed on the outputs of the second pair of multipliers Note Only available when the number of multipliers is 4 2 5 altmult_add Megafunction User Guide MegaWizard Page Descriptions Table 2 2 altmult_add Plug In Manager Page 4 Options Part 2 of 2 Function Description Implementation Specify implementation configurations Which multiplier adder implementation Specify which implementation to use for the multiplier adder Use should be used dedicated multiplier circuitry is only available on devices which have DSP block support On page 5 of the altmult_a
67. iplier Common Applications Multiplier adder applications include serial finite impulse response FIR filters with fixed or variable coefficients fast fourier transform FFT and additional designs requiring a serial summation of products Designing with the altmult_add megafunction is most efficient when a design requires the summation of products Such designs can take advantage of the speed offered by the dedicated DSP circuitry blocks Use the altmult_add megafunction with devices that offer DSP blocks Currently this feature is available in Stratix devices When accumulating results from multipliers in the Stratix devices consider using the altmult_accum megafunction as described in the altmult_accum Megafunction User Guide If it is required to place adding or subtracting results of multipliers in logic elements or in device families other than Stratix devices consider using lpm_mult and lpm_add_sub megafunctions together 2 For details about these megafunctions refer to the lIpm_mult Megafunction User Guide the lpm_add_sub Megafunction User Guide and the altmult_accum Megafunction User Guide 1 4 Altera Corporation altmult_add Megafunction User Guide March 2007 About this Megafunction For more information about the multiply add mode of the Stratix series DSP blocks and details on using accumulators in FIR filter applications refer to the Stratix II Architecture chapter in volume 1 of the Stratix II Handbook DSP Bloc
68. izard Plug In Manager page 5 of 7 ALTMULT_ADD Parameter Settings Input Configuration Register input A of the multiplier Options M Register input B of the multiplier Options What is the input A of the multiplier connected to Shiftin input E Whatis the input B of the multiplier connected to Multiplier input B Output Configuration M Register output of the multiplier 47 Click Finish The final page of the wizard shows the file that is generated for your custom megafunction variation The gray check marks indicate files that are always generated the other files are optional and are generated only if selected indicated by a red check mark Turn on the boxes to select the files that you want generated 48 Turn on VHDL Component declaration file and Instantiation template file 2 46 Altera Corporation altmult_add Megafunction User Guide March 2007 Getting Started 49 Turn off Quartus symbol file and AHDL include file Leave the other options in their default settings Figure 2 38 shows the wizard after you have made these selections Figure 2 38 altmult_add Wizard Page 6 Summary MegaWizard Plug In Manager page 7 of 7 Summary ALTMULT_ADD Version 6 1 When the Finish button is pressed the MegaWizard Plug In Manager will create the checked files in the following list You may choose to include or exclude a file fir_fourtap by ch
69. ks in Stratix and Stratix GX Devices and Implementing High Performance DSP Functions in Stratix and Stratix GX Devices chapters in volume 2 of the Stratix Device Handbook Resou rce The altmult_add megafunction is implemented using either logic ope gk resources or dedicated multiplier circuitry in Altera devices Typically Uti izati on and the altmult_add megafunction is translated to the dedicated multiplier Pe rfo rmance circuitry when available providing improved performance and resource utilization 2 For detailed information about the architecture of the DSP blocks and embedded multipliers and detailed information on the hardware conversion process refer to the following sources E Introduction and Stratix Architecture chapters in volume 1 of the Stratix Device Handbook DSP Blocks in Stratix and Stratix GX Devices and Implementing High Performance DSP Functions in Stratix and Stratix GX Devices chapters in volume 2 of the Stratix Device Handbook E Introduction and Stratix II Architecture chapters in volume 1 of the Stratix II Device Handbook and DSP Blocks in Stratix II Devices and Configuring Stratix II Devices chapters in volume 2 of the Stratix II Device Handbook E Introduction and Cyclone II Architecture chapters in volume 1 of the Cyclone II Device Handbook and Embedded Multipliers in Cyclone II Devices and Configuring Cyclone II Devices chapters in volume 2 of the Cyclone II Device Handbook Table 1 1 summarizes the r
70. lator To further check the timing simulation perform the following steps 1 Inthe Tools menu click Execute Macro The Execute Do File dialog box appears 2 Select cplx_mult_timing do and click OK cplx_mult_timing do is a script file for ModelSim that automates all the necessary settings for the timing simulation You can verify the results in the Waveform Viewer window Figure 2 30 Altera Corporation altmult_add Megafunction User Guide March 2007 Getting Started Figure 2 30 ModelSim Waveform Viewer for Timing Simulation iM wave default File Edit View Insert Format Tools Window oplx_mult_vig_vec_tst t__wire__a_imag cplx_mult_vig_vec_tst t__wire__a_real oplx_mult_vig_vec_tst t__wire__b_imag cplx_mult_vig_vec_tst t__wire__b_real cplx_mult_vig_vec_tst t__wire__clk cplx_mult_vig_vec_tst t__wire__unsig_siga cplx_mult_vig_vec_tst t__wire__unsig_sigb cplx_mult_vig_vec_tst t__wire__result_imag cplx_mult_vig_vec_tst t__wire__result_real Now 1us Delta 0 Design Example implementing a Simple FIR Filter Altera Corporation March 2007 If needed you can rearrange signals remove redundant signals and change the radix to suit the results in the Quartus II Simulator This design example uses the altmult_add megafunction to implement a FIR filter in the form shown in Equation n 1 y t YAt iBd i 0 In this equation n represents the number of taps A t
71. list select Functional In the Simulation Input box type altmult_add vwf or click the browse to select the file in the project folder Under Simulation period select End simulation at type 1 and select us Turn on Automatically add pins to simulation output waveforms and Simulation coverage reporting Turn off Check outputs Turn off Overwrite simulation input file with simulation results Figure 2 25 shows the Settings dialog box after you have made these selections 2 31 altmult_add Megafunction User Guide Example 1 Figure 2 25 Functional Simulation Settings Settings cplx_mult Category General Simulator Settings Files User Libraries Current Project Select simulation options Device Operating Conditions i A 7 Compilation Process Settings Simulation mode Functional EDA Tool Settings Simulation input Jaltmult_add vt ie Add multiple files Analysis amp Synthesis Settings Fitter Settings Simulation period E Timing Analysis rora i Run simulation until all vector stimuli are used TimeQuest Timing Analyzer Classic Timing Analyzer Settings End simulation at 1 us v Assembler Design Assistant JV Automatically add pins to simulation output waveforms SignalT ap Il Logic Analyzer Logic Analyzer Interface J Check outputs EZONE i upi Simulator Settings I7 Setup and hold time violation det PowerPlay Power Analyzer Settings I Glitch de v IV Simulation coverage rep
72. lt i Create a shiftout output from A input of the last multiplier Outputs Configuration Create a shiftout output from B input of the last multiplier Register output of the adder unit Adder Operation What operation should be performed on outputs of the first pair of multipliers Implementation Which multiplier adder implementation should be used Use the default implementation Use dedicated multiplier circuitry Not available for all families Use logic elements Altera Corporation March 2007 32 Click Next 33 Under Input Configuration turn on Register input A of the multiplier and click More Options The Data A Input Register Configuration Multiplier 0 dialog box appears Figure 2 12 2 17 altmult_add Megafunction User Guide Example 1 Figure 2 12 Data A Input Register Configuration Multiplier 0 Data A Input Register Configuration Multiplie What is the source for clock input ClockO vl What is the source for asynchronous clear input None M 34 35 36 37 In the What is the source for clock input list select Clock In the What is the source for asynchronous clear input list select None Click Done Under Input Configuration turn on the Register input B of the multiplier option Click More Options The Data B input Register Configuration Multiplier 0
73. lue is ACLR3 7 ACCUMULATOR String Specifies the accumulator mode of the final adder stage Values are YES and NO If omitted the default value is No When value is set to YES rounding is dynamic and you must initialize the accumulator while rounded data is acquired 3 CHAINOUT ADDER String Specifies the chainout mode of the final adder stage Values are YES and NO If omitted the default value is NO 3 ZERO_CHAINOUT_OUTPUT_ REGISTER String Specifies the clock source for the first register on the zero_chainout input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO 1 ZERO_CHAINOUT_OUTPUT_ ACLR String Specifies the asynchronous clear source for the first register on the zero_chainout input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and ZERO_CHAINOUT_OUTPUT_ REGISTER is used the default value is ACLR3 1 ZERO_LOOPBACK_ REGISTER String Specifies the clock source for the first register onthe zero loopback input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO 7 3 16 altmult_add Megafunction User Guide Altera Corporation March 2007 Specifications Table 3 3 altmult_add Megafunction Parameters Part 13 of 18 Parameter ZERO_LOOPBACK_ACLR Type String Required No Comments Specifies the asyn
74. m the following activities Create a FIR filter using the altmult_add megafunction and the MegaWizard Plug in Manager Implement the design and assign the EP1S10F780C5 device to the project Compile and simulate the design Generate a 4 Tap FIR Filter To generate a 4 tap FIR filter perform the following steps 1 2 38 Open the altmult_add_DesignExample_ex2 zip file and extract fir_fourtap qar In the Quartus II software open the fir_fourtap qar project and restore the archive file into your working directory In the Tools menu click MegaWizard Plug In Manager The MegaWizard Plug In Manager dialog box appears Figure 2 1 on page 2 1 Select Create a new custom megafunction variation and click Next In the Which megafunction would you like to customize list click the icon to expand Arithmetic and select ALTMULT_ADD In the Which device family will you be using list select Stratix Under Which type of output file do you want to create select VHDL In the What name do you want for the output file enter fir fourtap or click Browse to select the filename Figure 2 31 shows the wizard after you have made these selections Altera Corporation altmult_add Megafunction User Guide March 2007 Getting Started Figure 2 31 MegaWizard Plug In Manager MegaWizard Plug In Manager page 2a Which megafunction would you like to customize which device family will you be Stratix X ing Select a megafun
75. mentation that balances high performance with minimal logic usage This setting is available for APEX 20K Cyclone series MAX II Stratix and Stratix II devices only The balanced optimization logic option can be set in Analysis and Synthesis settings Assignments menu The MegaWizard Plug In Manager reports approximate resource utilization based on user specification and parameters available in the lower left corner of the MegaWizard Plug In Manager screen 1 6 altmult_add Megafunction User Guide Altera Corporation March 2007 N D TE PYA 2 Getting Started Software and System Requirements MegaWizard Plug In Manager Customization MegaWizard Page Descriptions Altera Corporation March 2007 The instructions in this section require the following hardware and software E For operating system support information refer to the support page of the Altera website www altera com E The Quartus II software version 6 1 or later Use the MegaWizard Plug In Manager to specify the altmult_add megafunction features for each multiplier in your design In the Quartus II software start the MegaWizard Plug In Manager in one of the following ways On the Tools menu click MegaWizard Plug In Manager Double click in the Block Editor to open the Symbol dialog box Click MegaWizard Plug In Manager E Start the stand alone version of the MegaWizard Plug In Manager by typing the following command at the command prompt
76. mplemented using the DSP block when the value is set to YES If omitted the default is AUTO MULT _ROUND_ACLR String Parameter 01 23 Specifies the asynchronous clear source for the second register on the corresponding mult round input port Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and corresponding MULT ROUND REGISTER is used the default is ACLR3 2 MULT _ ROUND REGISTER String Parameter 01 23 Specifies the clock source for the register on the corresponding mult round input port Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO 2 Altera Corporation March 2007 3 21 altmult_add Megafunction User Guide Ports and Parameters Table 3 3 altmult_add Megafunction Parameters Part 18 of 18 Parameter Type Required Comments MULT _ SATURATION _ACLR String No Parameter 01 23 Specifies the asynchronous clear source for the register on the corresponding mult _ saturation input port Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and corresponding MULT _ SATURATION REGISTER is used the default is ACLR3 2 MULT _ SATURATION _ String No Parameter 01 23 Specifies the clock REGISTER source for the register on the corresponding mult saturation input port Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO 2
77. n and Overwrite simulation input file with simulation results Figure 2 42 shows the Simulator Settings page after you have made these selections 9 52 Altera Corporation altmult_add Megafunction User Guide March 2007 Getting Started Figure 2 42 Simulator Settings Page Settings fir_fourtap Category General Files Device Timing Analysis Settings EDA Tool Settings Fitter Settings Assembler Design Assistant SignalT ap Il Logic Analyzer Logic Analyzer Interface SignalProbe Settings Simulator Settings Simulation Power Operating Conditions User Libraries Current Project Compilation Process Settings Analysis amp Synthesis Settings PowerPlay Power Analyzer Settings Select simulation options Simulation mode Timing zl Simulation input fir_four_tap vwf Si Simulation period Run simulation until all vector stimuli are used End simulation at 1 ns X J Automatically add pins to simulation output waveforms I Check outputs l I Setup and hold time violation detection J7 Glitch detection n M Simulation coverage reporting Report Settings Overwrite simulation input file with simulation results Disable setup and hold time violation detection for input registers of bi directional pins More Settings Description Specifies the end time for simulation Cancel Altera Corporation March 2007 10 11 12 In the Category list
78. n 6 1 Parameter Simulation Summary General gt ExtraModes gt Multipliers gt real_mult MULTOJ MULTI Currently selected device family General What is the number of multipliers multipliers All multipliers have similar configurations How wide should the A input buses be How wide should the B input buses be How wide should the result output bus be C Create a 4th asynchronous clear input option This forces all registers to have an associated asynchronous clear input C Create an associated clock enable for each dock Input Representation 2dsp_9bit What is the representation format for A inputs Variable More Options Variable i signa input controls the sign 1 signed 0 unsigned What is the representation format for B inputs signb input controls the sign 1 signed 0 unsigned More Options lt Back Cancel Finish Table 2 1 shows the options available on page 3 of the altmult_add MegaWizard Plug In Manager Function Currently selected device family Table 2 1 altmult_add Plug In Manager Page 3 Options Part 1 of 2 Description Specify the family device you want to use What is the number of multipliers Specify the number of multipliers All multipliers have similar configurations Add hardware support for hardware saturation and rounding T
79. n the default state and click OK 7 On the Processing menu click Start Compilation 8 When the Full compilation was successful box appears click OK Altera Corporation 2 49 March 2007 altmult_add Megafunction User Guide Example 2 Functional Results Simulate the FIR 4 Tap Design This section describes how to verify the design example you just created by simulating the design using the Quartus II Simulator To set up the Quartus II Simulator perform the following steps 1 2 50 On the Processing menu click Generate Functional Simulation Netlist When the Functional Simulation Netlist Generation was successful box appears click OK On the Assignments menu click Settings The Settings dialog box appears In the Category list select Simulator Settings The Simulator Settings page appears In the Simulation mode list select Functional Type fir_four_tap vwf in the Simulation Input box or click Browse to select the file in the project folder Turn on End simulation at type 1 and select us Turn on Automatically add pins to simulation output waveforms and Simulation coverage reporting Turn off Check outputs and Overwrite simulation input file with simulation results Figure 2 40 shows the Simulator Settings page after you have made these selections Altera Corporation altmult_add Megafunction User Guide March 2007 Getting Started Figure 2 40 Simulator Settings Page Settings
80. na and scaninb simultaneously scanoutb No Output of scan chain B Output port WIDTH_B 1 0 wide When designing with Stratix III devices port cannot be selected when scanina is in use Note Do not use scanina and scaninb simultaneously multO is saturated No Signal indicating This port is required when DE saturation of the first PORT MULTO IS SATURATED has a multiplier value of USED 2 multl is saturated No Signal indicating This port is required when saturation of the second PORT_MULT1_IS_ SATURATED has a multiplier value of USED 2 mult2 is saturated No Signal indicating This port is required when or saturation of the third PORT _MULT2_IS SATURATED has a multiplier value of USED 2 mult3 is saturated No Signal indicating this port is required when saturation of the fourth PORT_MULT3_IS_ SATURATED has a multiplier value of USED 2 Note to Table 3 2 1 This parameter is available only for Stratix III devices 2 This parameter is available only for Stratix II devices Table 3 3 altmult_add Megafunction Parameters Part 1 of 18 Parameter Type Required Comments NUMBER_OF MULTIPLIERS String Yes Number of multipliers to be added together Values are 1 up to 4 WIDTH_A String Yes Width of the dataa port WIDTH _B String Yes Width of the datab port WIDTH RESULT String Yes Width of the result port Value includes all bits before rounding and
81. nstead of addition Accommodate the signed unsigned data representation Provide data shifting chains and additional registers Control asynchronous clear of the registers Use a DSP block in the multiplier adder Size the data width of the input and output A multiplier adder with these optional features is shown in Figure 1 2 1 2 Altera Corporation altmult_add Megafunction User Guide March 2007 About this Megafunction Figure 1 2 Multiplier Adder with Optional Features T A i Add Sub 0 Sign B i i gt Scanout B Scanout A Altera Corporation March 2007 The altmult_add megafunction implements the multiplier adder described in Figure 1 2 and offers many variations in dedicated digital signal processing DSP block circuitry Data input sizes of up to 18 bits are accepted Because the DSP blocks allow for one or two levels of 2 input add subtract operations on the product this function creates up to four multipliers Additional features include dynamically changing signed or unsigned data support dynamically changing add subtract based operation setting up data shifting chains and additional registers for latency and controlling asynchronous clear of the registers The multipliers and adders of the altmult_add megafunction are pla
82. ors Setup the ModelSim Altera simulator by performing the following steps 1 Unzip almult_add_ex1_msim zip to any working directory on your PC 2 Start ModelSim Altera 3 On the File menu click Change Directory The Choose folder dialog box appears and select the folder where you have unzipped your files Click OK 4 On the Tools menu click Execute Macro The Execute Do File dialog box appears 5 Select cplx_mult_functional do and click Open cplx_mult_functional do is a script file for ModelSim that automates all the necessary settings for the functional simulation You can verify the results in the Waveform Viewer window Figure 2 29 2 35 altmult_add Megafunction User Guide Example 1 Figure 2 29 Mode lSim Waveform Viewer for Functional Simulation Te wave default File Edit View Insert Format Tools Window 2X m4 B m4 m4 cplx_mult_vlg_vec_tst t__wire__a_imag cplx_mult_vig_vec_tst t_wire__a_teal cplx_mult_vlg_vec_tst t__wire__b_imag cplx_mult_vig_vec_tst t__wire__b_real cplx_mult_vig_vec_tst t__wire__clk cplx_mult_viq_vec_tst t__wire__unsig_siga cplx_mult_vig_vec_tst t__wire__unsig_sigb cplx_mult_vig_vec_tst t__wire__result_imag cplx_mult_vig_vec_tst t__wire__tesult_teal 0 ps to 85014 ps Now 1us Delta 0 2 36 If needed you can rearrange signals remove redundant signals and change the radix to suit the results in the Quartus II Simu
83. orting Report Settings I Overwrite simulation input file with simulation results fiz ible setup and hold tir ition detection for input More Settings Description Specifies the source of input vectors to be used for incremental input simulation Cancel 11 In the Category list click the icon to expand Simulator Settings 12 Select Simulation Power The Simulation Power page appears 13 Turn off Generate Signal Activity File and Generate VCD File 14 Click OK 15 On the Processing menu Click Start Simulation to run simulation 16 The Simulation was successful box appears Click OK 17 The Simulation Report window appears Verify the simulation waveform results Figure 2 26 2 32 Altera Corporation altmult_add Megafunction User Guide March 2007 Getting Started Figure 2 26 Simulation Waveform D ps 20 0 ns 40 0 ns 60 0 ns 80 0 ns 100 0 ns 0ps a_imag 0 i 2 a i owes oF 0 a_teal ET K ko ee a a 0 b_imag Oo ioe amp l GEIS A 0 b_real 1 3 5 7 3 il 0 clk unsig_siga unsig_sigb result_imag 0 6 20 42 F2 6 0 result_real 1 8 21 40 65 8 0 Timing Results This section describes how to verify the timing after implementation using the Quartus II Simulator To set up the Quartus II Simulator perform the following steps in the Quartus II software 1 Altera Corporation March 2007 On the Assignments menu click Settings The Settings dialog
84. ory C Documents and Sattinne ehriz ial Necbtan Nar imantstinn MensEiinctinne IZ Altmidt add MElev E teal_mult vhd Variation file O realmult inc AHDL Include file teal_mult cmp VHDL component declaration file O real_mult bst Quartus II symbol file O real_mult_inst vhd Instantiation template file E teal_mult_waveforms html Sample waveforms in summary bo feal_mult_wave jpg Sample waveform file s e For more information about the ports for the altmult_add megafunction refer to the Specifications chapter in this user guide Inferring Megafunctions from HDL Code Synthesis tools including the Quartus II integrated synthesis recognize certain types of HDL code and automatically infer the appropriate megafunction when a megafunction will provide optimal results That is the Quartus II software uses the Altera megafunction code when compiling your design even though you did not specifically instantiate the megafunction The Quartus II software infers megafunctions because they are optimized for Altera devices so the area and or performance may be better than generic HDL code Additionally you must use megafunctions to access certain Altera architecture specific features such as memory DSP blocks and shift registers which generally provide improved performance compared with basic logic elements 2 8 Altera Corporation altmult_add Megafunction User Guide March 2007 Ge
85. ourtap_timing do is a script file for ModelSim that automates all the necessary settings for the timing simulation You can verify the results in the Waveform Viewer window Figure 2 45 Altera Corporation 2 55 March 2007 altmult_add Megafunction User Guide Conclusion Figure 2 45 ModelSim Waveform Viewer for Timing Simulation RA wave default File Edit View Insert Format Tools Window fit_fourtap_vhd_vec_tst t_sig_clockO fit_fourtap_vhd_vec_tst t_siq_clock1 fit_fourtap_vhd_vec_tst t_sig_dataa_O fit_fourtap_vhd_vec_tst t_siq_datab_O fi_fourtap_vhd_vec_tst t_siq_datab_1 fit_fourtap_vhd_vec_tst t_siq_datab_2 fit_fourtap_vhd_vec_tst t_siq_datab_3 fit_fourtap_vhd_vec_tst t_siq_enaO fit_fourtap_vhd_vec_tst t_sig_enal fit_fourtap_vhd_vec_tst t_sigq_result fit_fourtap_vhd_vec_tst t_sig_signa fir_fourtap_vhd_vec_tst t_sig_signb Now 2us Delta 1 If needed you can rearrange signals remove redundant signals and change the radix to suit the results in the Quartus II Simulator Conclusion The Quartus II software provides parameterizable megafunctions ranging from simple arithmetic units such as adders and counters to advanced phase locked loop PLL blocks multipliers and memory structures These megafunctions are performance optimized for Altera devices and therefore provide more efficient logic synthesis and device implementation because they automate the coding process
86. r on the output_saturate input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and OUTPUT_SATURATE _ PIPELINE REGISTER is used the default value is ACLR3 7 CHAINOUT ROUNDING String Enables rounding handling at the chainout stage Values are YES NO and VARIABLE A value of YES or NO specifies saturation handling setting permanently to on or off A value of VARIABLE allows dynamically controlled saturation handling If omitted the default value is NO 7 CHAINOUT_ROUND_TYPE String Specifies the rounding mode at the chainout stage Values are BIASED and UNBIASED A value of BIASED specifies round to nearest integer A value of UNBIASED specifies round to nearest even CHAINOUT_ROUND_ FRACTION WIDTH Integer Specifies the fractional rounding width at the chainout stage Values are 0 15 CHAINOUT ROUND REGISTER String Specifies the clock source for the first register on the chainout_round input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO 7 CHAINOUT_ROUND_ACLR String Specifies the asynchronous clear source for the first register on the chainout_round input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and CHAINOUT_ROUND_ REGISTER is used the default value is ACLR3 1 CHAINOUT_ROUND_ PIPELINE REGISTER String Specifies the clock source for the second register on the chainout_round input
87. ression Generate a 9 x 9 Bit Multiplier Adder the Imaginary Expression cscsssssesesesteseeseeee 2 21 Combine real_mult and image_mult to Create a Complex Multiplier ccccccceeeseeseees 2 27 Implement the 9 x 9 Complex Multiplier Design Functional Results Simulate the Complex Multiplier Design ccccesesseeeseeseseeeeeeees 2 31 Timing Results sissioni cass dage snag a ai a aaeei aiaa asa iinta euina Simulate the Complex Multiplier Design in ModelSim Altera Design Example Implementing a Simple FIR Filter Design Fils tec csisvsictsnsecciinteisvadadeiescneuieiie EXAM Ple 2 osiinsa Generate a 4 Tap FIR Filter Implement the FIR 4 Tap Design Functional Results Simulate the FIR 4 Tap Design Timing RESUS esseen ereraa REA en ra Eae a SEEE eee E EE EE EEEE AIEE Altera Corporation iii Contents Simulate the FIR Filter Design in the ModelSim Altera Software ccccsessesssesseseseseetenenees 2 54 oa E Lb EIO g seis AEE E E EE E ETEEN AE E NET 2 56 Chapter 3 Specifications Ports and Parameters aii secsevcvesvesivecvaeccececdececosesevelaansovnsesvsuvaeccedaecedeccissiavasdivetsinssaseveiedetasaioase diiebeinsascass 3 1 iv Altera Corporation altfp_mult Megafunction User Guide About this User Guide Revision History The table below displays the revision history for the chapters in this User Guide Date Version Changes Made March 2007 2 3 e Added Cyclone
88. round enables the stage rounding chainout stage of rounding 7 chainout_saturate No Enables dynamically When CHAINOUT_SATURATION is set to controlled chainout VARIABLE chainout_saturate stage saturation enables the chainout stage of saturation 1 zero _chainout No Dynamically specifies 7 whether the chainout value is zero 3 2 altmult_add Megafunction User Guide Altera Corporation March 2007 Specifications Table 3 1 altmult_add Megafunction Input Ports Part 2 of 3 Altera Corporation March 2007 chain B Port Name Required Description Comments zero loopback No Dynamically specifies 7 whether the loopback value is zero accum_sload No Dynamically specifies 7 whether the accumulator value is zero chainin No Adder result input bus Input port WIDTH _CHAININ 1 0 from the preceding wide 7 stage rotate No Specifies dynamically 7 controlled port rotation in shift mode shift right No Specifies dynamically Values are 0 and 1 A value of 0 specifies a controlled port shift right shift to the left a value of 1 specifies a shift to or left in shift mode the right 7 signa No Specifies the numerical If the signa port is high the multiplier treats representation of the the dataa portas a signed two s dataa port complement number If the signa portis low the multiplier treats the dataa portas an unsigned number s
89. rtus II Help for the most current information on the ports and parameters for this megafunction IS LOOPBACK mode is only supported when each input is 18 bits wide width_result is 36 bits wide and the number of multipliers is either 1 or 2 Table 3 1 altmult_add Megafunction Input Ports Part 1 of 3 Port Name Required Description Comments dataa Yes Data input to the Input port NUMBER_OF MULTIPLIERS multiplier WIDTH_A 1 0 wide datab Yes Data input to the Input port NUMBER_OF MULTIPLIERS multiplier WIDTH_B 1 0 wide clock No Clock input usable by Input port 0 3 Clock input to the any register in the corresponding register megafunction aclr No Asynchronous clear Input port 0 3 Asynchronous clear input input to the corresponding register ena No Clock enable for the Input port 0 3 Clock enable for the clock port corresponding clock port output_round No Enables dynamically When OUTPUT _ROUNDING is set to controlled output VARIABLE output_ round enables the rounding final adder stage of rounding 7 output_saturate No Enables dynamically When OUTPUT _SATURATION is set to controlled output VARIABLE output_saturate enables saturation the final adder stage of saturation 7 chainout_round No Enables dynamically When CHAINOUT_ROUNDING is set to controlled chainout VARIABLE chainout_
90. sponding sign port Values are NONE ACLRO ACLR1 ACLR2 and ACLR3 If omitted and corresponding SIGNED_REGISTER_ is used the default is ACLR3 SIGNED PIPELINE _ REGISTER _ String Parameter A B Specifies the clock signal for the second register on the corresponding sign port Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If the corresponding sign port value is UNUSED this parameter is ignored If omitted the default is CLOCKO SIGNED PIPELINE ACLR_ String Parameter A B Specifies the asynchronous clear signal for the second register on the corresponding sign port Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and the corresponding SIGNED PIPELINE REGISTER _ is used the default is ACLR3 SCANOUTA_REGISTER String Specifies the clock source for the scanouta data bus registers UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default is UNREGISTERED 7 SCANOUTA_ACLR String Specifies the asynchronous clear source for the scanouta data bus registers Legal values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and SCANOUTA_REGISTER is used the default is ACLR3 7 Altera Corporation March 2007 3 7 altmult_add Megafunction User Guide Ports and Parameters Table 3 3 altmult_add Megafunction Parameters Part 4 of 18 Parameter Type INPUT REGISTER B String Required No Comments P
91. t Representation Whatis the representation format for A inputs Variable E signa input controls the sign 1 signed 0 unsigned More Options Whatis the representation format for B inputs Variable signb input controls the sign 1 signed 0 unsigned More Options L cance lt Back net gt 23 Click Next 24 Under Outputs Configuration turn off Create a shiftout output from A input of the last multiplier and Create a shiftout output from B input of the last multiplier 25 Turn on Register output of the adder unit 26 Click More Options for Register output of the adder unit The Output Register Configuration dialog box appears 27 In the What is the source for clock input option select Clock0 28 In the What is the source for asynchronous clear input option select None 29 Click Done 2 16 Altera Corporation altmult_add Megafunction User Guide March 2007 Getting Started 30 Under Adder Operation in the What operation should be performed on outputs of the first pair of multipliers list select Subtract 31 Under implementation select Use logic elements Figure 2 11 shows the wizard after you have made these selections Figure 2 11 MegaWizard Plug In Manager altmult_add Page 4 of 7 MegaWizard Plug In Manager page 4 of 7 ALTMULT_ADD Version 6 1 General gt Extra Modes gt Multipliers dataa_0 8 0 onal x real_mu
92. the checked files in the following list You may choose to include or exclude a file real_mult by checking or unchecking its corresponding checkbox respectively The state of checkboxes will be remembered for the next MegaWizard Plug In Manager session MULTOJ The MegaWizard Plug In Manager will create these files in the directory C Documents and Settings mmitchel Local Settings Temp cplx_mult_restored Z teal_mult vhd Variation file O teal_mult inc AHDL Include file E teal_mult cmp VHDL Component declaration file O teal_mult bsf Quartus symbol file E teal_mult_inst vhd Instantiation template file E teal_mult_waveforms html Sample waveforms in summary i feal_mult_wave jpg Sample waveform file s Resource Usage 2 alt_mac_mult 1 alt_mac_outj 49 Click Finish The altmult_add variation is now built 2 20 Altera Corporation altmult_add Megafunction User Guide March 2007 Getting Started Generate a 9 x 9 Bit Multiplier Adder the Imaginary Expression 1 In the Tools menu click MegaWizard Plug In Manager The MegaWizard Plug In Manager page 1 dialog box appears Figure 2 1 on page 2 1 2 Select Create a new custom megafunction variation and click Next 3 Inthe Which megafunction would you like to customize list click the icon to expand Arithmetic and select ALTMULT_ADD 4 Inthe Which device family will you be using list select Stratix 5 Under Which
93. tting Started Instantiating Megafunctions in HDL Code Identifying a Megafunction after Compilation Altera Corporation March 2007 For more information refer to the Recommended HDL Coding Styles chapter in volume 1 of the Quartus II Handbook When you use the MegaWizard Plug In Manager to set up and parameterize a megafunction it creates either a VHDL or Verilog HDL wrapper file that instantiates the megafunction a black box methodology For some megafunctions you can generate a fully synthesizable netlist for improved results with EDA synthesis tools such as Synplify and Precision RTL Synthesis a clear box methodology Both clear box and black box methodologies are described in the following third party synthesis support chapters in the Quartus IT Handbook m Recommended HDL Coding Styles chapter in volume 1 of the Quartus II Handbook Quartus II Integrated Synthesis chapter in volume 1 of the Quartus II Handbook Synplicity Synplify and Synplify Pro Support chapter in volume 1 of the Quartus II Handbook m Mentor Graphics Precision RTL Synthesis Support chapter in volume 1 of the Quartus II Handbook During compilation with the Quartus II software analysis and elaboration is performed to build the structure of your design Locate your megafunction in the Project Navigator window by expanding the compilation hierarchy and locating the megafunction by its name Similarly to search for node names within the mega
94. type of output file do you want to create select VHDL 6 Specify the output file name as imag_mult Figure 2 17 shows the wizard after you have made these selections Figure 2 17 MegaWizard Plug In Manager altmult_add Page 2a MegaWizard Plug In Manager page 2a Which megafunction would you like to customize Which device family will you be Stratix X ing Select a megafunction from the list below Sick M4 Installed Plug Ins Which type of output file do you want to create a Altera SOPC Builder C AHDL Arithmetic G ALTACCUMULATE 3 HDL ALTFP_ADD_SUB Verilog HDL ALTFP_DIV a ile ALTFP_ MULT What name do you want for the output file Browse ALTMEMMULT hoplx_mult_restored imag_mult ALTMULT_ACCUM MAC ALTMULT_ADD Generate clear box netlist file instead of a default wrapper file ALTSQRT for use with supported EDA synthesis tools only LPM_ABS LPM_ADD_SUB LPM_COMPARE Note To compile a project successfully in the Quartus II software LPM COUNTER your design files must be in the project directory in the global user LPM DIVIDE libraries specified in the Options dialog box Tools menu or a user LPM MULT library specified in the User Libraries page of the Settings dialog box Assignments menu PARALLEL_ADD Communications Your current user library directories are a DSP aj Gates fq 1 0 Interfaces Memory Compiler I Return to this page for another create operation Cancel lt B
95. ult_add Megafunction User Guide March 2007 N D TE RYN Contents About this User GU Boss oaisaneee wee eciieewsceeoeseuaieeafnesraedetahatteenacaanseaedeteeaasvs V Revision History How to Contact Altera Typographic Conventions Chapter 1 About this Megafunction Device Family Support Introduction cccceeeeeee Features ccccccceeee General Description siisii iii Common Applications Resource Utilization and Performance Chapter 2 Getting Started Software and System Requirement 0c0 MegaWizard Plug In Manager Customization MepgaWizard Page Descriptions ss its cscestssisisafiicttsdeccedssshsessescatsasscetyetnoscenseasbecpeetestviaessuaiavssesiedaibidestoa Inferring Megafunctions from HDL Code ccceeseesesesesseseeseseeresesessensseseeessssssssessssnseensseeeneens Instantiating Megafunctions in HDL Code Identifying a Megafunction after Compilation SULA BION rnaro deca vasaes fein aazeesie dasa a E A a esas Quartus II Simulator EDA Simula th nic scs0c5sge8 E E E AE decease devia vsaedssaoeaaespusevaes NAN SignalTap II Embedded Logic Analyzer c ccccssscssssssessssesessssssresssessesesesessescesesssesesesessesesssesseseesees Design Example Complex Multiplication Design Files ci ct tice sti ctssctaescetecsstsovsalsen asicnssuasseSecseasvacataasssatsiieg E AEE E Example T oenn rn E e E A cgrvnasossaceneeas asaacavasvatpiogs N Generate a 9 x 9 Bit Multiplier Adder the Real Exp
96. urce for clock input list select Clock e Inthe What is the source for asynchronous clear input list select None Click Done Figure 2 18 shows the wizard after you have made these selections Altera Corporation altmult_add Megafunction User Guide March 2007 Getting Started Figure 2 18 MegaWizard Plug in Manager Page 3 of 7 MegaWizard Plug In Manager page 3 of 7 imag_mult MULTOJ Currently selected device family r General What is the number of multipliers multipliers M All multipliers have similar configurations How wide should the A input buses be How wide should the B input buses be How wide should the result output bus be Create a 4th asynchronous clear input option This forces all registers to have an associated asynchronous clear input Create an associated clock enable for each dock datab Unsigned FF I Input Representation Whatis the representation format for A inputs Variable E signa input controls the sign 1 signed 0 unsigned More Options Whatis the representation format for B inputs Unsigned ra 23 24 25 26 27 28 29 Altera Corporation March 2007 Click Next Under Outputs Configuration turn off Create a shiftout output from A input of the last multplier and Create a shiftout output from B input of
97. ure 2 20 shows the wizard after you have made these selections 2 25 altmult_add Megafunction User Guide Example 1 Figure 2 20 MegaWizard Plug In Manager Page 5 of 7 MegaWizard Plug In Manager page 5 of 7 ALTMULT_ADD Version 6 1 Parameter Input Configuration Register input A of the multiplier Register input B of the multiplier What is the input A of the multiplier connected to Multiplier input Whats the input B of the multiplier connected to Multiplier input A r Output Configuration Register output of the multiplier datab Unsigned ff 47 Click Finish The final page of the wizard shows the files that are generated for your custom megafunction variation The gray check marks indicate files that are always generated the other files are optional and are generated only if selected indicated by a red check mark Turn on the boxes to select the files that you want generated 48 Turn on VHDL Component declaration file and Instantiation template file 49 Turn off Quartus symbol file and AHDL Include file Leave the other options in their default settings Figure 2 21 shows the wizard after you have made these selections 2 26 Altera Corporation altmult_add Megafunction User Guide March 2007 Getting Started Figure 2 21 MegaWizard Plug In Manager altmult_add Page 7 of 7 Summary MegaWizard Plug In Manager page 7 of 7
98. vel ports of the Altera megafunctions in your design while your system is running at full speed To monitor signals from your Altera megafunctions you must first configure the SignalTap II Embedded Logic Analyzer in the Quartus II software then include the analyzer as part of your Quartus II project The Quartus II software will then seamlessly embed the analyzer along with your design in the selected device For more information about using the SignalTap II Embedded Logic Analyzer refer to the Design Debugging Using the SignalTap II Embedded Logic Analyzer chapter in volume 3 of the Quartus II Handbook This design example uses the altmult_add megafunction to implement a complex multiplier Consider the complex multiplication of Ao iA x Bo iB This expression can be expanded to Ao x By Ay x B1 i A x By Ay x Bo To implement this two multiplier adder functions are required one for the real expression and one for the imaginary expression Design Files The design files are available in the literature page of the Altera web site under user guides Select the Examples for altmult_add Megafunction User Guide link from the examples page to download the design files In this example you perform the following activities m Create a complex multiplier using the altmult_add megafunction and the MegaWizard Plug in Manager Implement the design and assign the EP1S10F780C5 device to the project E Compile
99. zipped your files Click OK 4 On the Tools menu click Execute Macro The Execute Do File dialog box appears 5 Select fir_fourtap_functional do and click Open fir_fourtap_functional do is a script file for ModelSim that automates all the necessary settings for the functional simulation You can verify the results in the Waveform Viewer window Figure 2 44 9 54 Altera Corporation altmult_add Megafunction User Guide March 2007 Getting Started Figure 2 44 Mode lSim Waveform Viewer for Functional Simulation MI wave default File Edit View Insert Format Tools Window tit_fourtap_vhd_vec_tst t_sig_clock0 tir_fourtap_vhd_vec_tst t_sig_clock1 tir_fourtap_vhd_vec_tst t_sig_dataa_0 fit_fourtap_vhd_vec_tst t_sig_datab_O tit_fourtap_vhd_vec_tst t_sig_datab_1 fit_fourtap_vhd_vec_tst t_sig_datab_2 fir_fourtap_vhd_vec_tst t_sigq_datab_3 fi_fourtap_vhd_vec_tst t_sig_ena0 Ifi_fourtap_vhd_vec _tst t_si_enal tir_fourtap_vhd_vec_tst t_sig_tesult fit_fourtap_vhd_vec_tst t_sig_signa tir_fourtap_vhd_vec_tst t_sig_signb Now 2us Delta 1 If needed you can rearrange signals remove redundant signals and change the radix to suit the results in the Quartus II Simulator To further check the timing simulation perform the following steps 1 Inthe Tools menu click Execute Macro The Execute Do File dialog box appears 2 Select fir_fourtap_timing do and click Open fir_f

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