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SAM4S-EK Development Board User Guide

1. 4 16 4 4 1 PIO Usage n 4 16 442 4 19 4 4 3 Tes 4 20 4 4 4 Solder 4 20 4 4 5 Assigned PIO Lines Disconnection Possibility 4 20 4 5 un 4 22 4 5 1 Power Supply Connector 99 4 22 4 5 2 USART Connector J5 With RTS CTS Handshake 4 22 453 UART Connector J7 enint etre n exer dot eder 4 23 4 5 4 USB Device Connector 15 a 4 23 455 TFT LCD Connector JB aee Detur nt e aries 4 24 4 5 6 JTAG Debugging Connector J6 a 4 25 4 5 7 SD MMC MCI Connector J3 a 4 26 4 5 8 Analog Connector CN1 amp 4 27 4 5 9 5485 Connector 14 24 2440 einen nnne innt nter nennt nnns 4 27 4 5 10 Headphone Connector J11 a 4 28 4 5 11 ZigBEE 16 4 28 4 5 12 PIO Expansion Port C 12 4 29 4 5 13 Expansion Port A Connector J13 4
2. R24 R30 Differential impedance matching for RS485 cable 5 45 Development Board User Guide 4 21 11139A ATARM 29 Nov 11 Evaluation Kit Hardware Table 4 9 Default Not Populated Parts Reference Function D1 Optional ESD protection for LCD touch panel R61 R63 RA2 RA3 Optional data bus termination for LCD controller JP4 Test mode selection for the SAM chip J2 Optional QFP socket for the SAM4 chip K1 Virtual component for QTouch keys set implemented as copper areas S1 Virtual component for QTouch slider set implemented as copper areas TPxx Surface mounted test points copper area 4 5 Connectors 4 5 1 Power Supply Connector J9 The SAMAS EK evaluation board can be powered from a 5VDC power supply connected to the external power supply jack J9 The positive pole is the center pin Figure 4 25 Power Supply Connector J9 DC 5V Table 4 10 Power Supply Connector J9 Signal Descriptions Signal Description Mnemonic Center 5vcc Gnd Ground reference USART Connector J5 With RTS CTS Handshake Support 4 5 2 Figure 4 26 Male RS232 USART Connector J5 12 3 4 5 OOOO 6 7 8 9 4 22 5 45 Development Board User Guide 11139 29 11 Evaluation Kit Hardware Table 4 11 Serial COM1 Connector J5 Signal Descriptions Pin Mnemonic Signal Description 1 4 6 9 NC NO CONNECTION 2 TX
3. 29 Poo _ 6 17 30 PCS ALE 31 Poa 18 RE 102 32 PCS 1 5 WE vos ja Pea Headerp 42 Ei POIs 004 24 cE vos 3 07 PC18 R19 AAA SB 3 RB m I N C28 47 3V3 1 N C27 is T Bet 47K 2 161 26 45 WWW 3 2 N C25 29 d i N C24 39 2 nga 5 N C4 N C23 3g nm N C5 PRE 15 N C6 n c22 88 TT N C21 33 N C8 N C20 14 N C9 N C19 28 22 N C10 N C18 43V3 ST NCH 37 22 N C12 VCC 12 2211 NES NOS C27 e C28 e C29 24 Nis 100nFT 100nFT tuF 25 NC16 vss Ee s 4 4 N C17 vss x z DGND USART 21 485 MN5 PDMSS12EARU 21 2 VCC C31 el C32 e C33 C34 PA21 232 4 7uF 100nFT 100nF T 100nF Lv c1 20 lt gt 21 C2 35 DGND 7T 100nF T 100nF 4 2 24 pu 832 se 3 19 1 1 7T 100nF 6 PA23 R31 pyy Slax as 2 2 TXD1 PA22 R33 7 18 3 RXD1 PA21 232 R34 TUN 45 8 RTS1 PA24 R35 AAA OR OUT SUN ETT 4 CTS1 PA25 R36 OR TOU 9 F37 47 g R2OUT R2IN tag OR 5 43V3 QN 12 T3OUT 13 WV R3IN DGND DGND UART FGND MING MAX3232CSE 313 3 33 3V3 cao eis 100nF y C2 4 P P c42 1 R45 L 2 T 5 GND ea 2 UTXDO PAT gt 7 OR H4 3 URXDO Pas lt gt WA 16 R1OUT RAIN 7 5
4. 5 4 3 2 4 lt gt 0 31 s els een scho ke RIS S SMA nm a 0 jaja 1 R1 nm e NN 2 3 PA O 31 R2 s 49 9R 1 BS gm ATSISAMAS LOFPAOD icd C 20 XIN a L szzszsoo O 8zE5an naozziis oud oounana DGND 3 mu Y2 12MHz qq OR nn 7 pac xi B22 25885 i225 SR Orr ON se 74 be T XOUT E225 2 23 4895990444 A17 75 PAT G AN SB5888 2225 229 775 1 _ PAT PWMH1 TIOBO A18 C2 1 20 Ti wa pel W 28e lt lt lt S els 5 67 2 DGND R7 nm PB8 R8 ORnm 96 e ool 5 205 9S S 3 NAAN oS G5 2 DATRG 66 ae WWW PB8_XOUT 209926 25 TWDO NPCS3 5 PAA a T lel PA4 TWCKO TCLKO 753 5 999 5 0 NPCS3 52 PAS 05 26 TXDO 4g 2 i Anm 7 Sal N95 PA7_RTSO_PWMH3 EWV 0589 48 XOUT32 R10 OR nm PAS e 5 cag 50 ADI2BTRG 46 SAN PAS 11 PAQ_URXDO_NPCS1 44 OR amp PA10 UTXDO N
5. 29 EDA FTM280C34D LED 31 PIN 1 LED K3 32 LEDK2 gt LED K4 33 LEDK3 Y UP 34 x Y DOWN 35 Y DGND X RIGHT 56 X LEFT 37 38 Nc 39 i H Six slots on PCB for LCD shield LCD DBO R61 ME nm LCD _1___8 S LCD DB2 2 7 DND ia LCD_DB8 1 8 rcD DBs 2 7 X_RIGHT LED ee 3 6 The part is placed as close as possible to J8 LCD R63 A 47Knm 4 Di PACDNO44Y5R nm DGND TVS SOT23 5 S NOT POPULATED DGND 3V3 R62 MN7 ADS7843E X_RIGHT 2 16 14 MN8 3 14 3V3 AAT3155ITP T1 DOUT ass 1 nee cz cs WW 100K ng 21 054 64 13 R67 OR 17 TP9 BUSY 711 M RED PAIS R68 9 PENIRQ EIE pits oR NE WS NER EN SET 4 g Ho TOuH 100mA BNO3K314S800R 1 SIN VCC2 R71 1R D i psi S nes csa e C59 C60 4 7uF 100K 21 GND 6 100nF 100nF Bs u 4 GND 4 4 7uF EN x 4 P LCD BACKLIGHT AGND_TP LCD TOUCH SCREEN AGND_TP DGND 25 51 1K Btw PC24 PC31 QTouch Key PC30 PC29 R 1K FS AAA C51 22nF PC28 2 857 1K SM EUN C52 22nF PC22 PC27 R 1K AW TT 22nF PC26 QTOUCH 51 QTouch Slider SR
6. 7 JP22 JP23 JP24 1 2 DC voltage selection between 3 3V and 5V on PIO expansion ports JP25 CLOSE Button BP2 disable JP26 CLOSE Button BP3 disable JP27 CLOSE Power consumption measure for ZigBEE module PIO MUXING PIOA USAGE PIOA USAGE PIOB USAGE PIOC USAGE PIOC USAGE D E FAU LT NO PO P U LATE PA RTS PAO TSLIDR SL SNS PA16 TSC IRQ ZB IRQO PBO MIC INPUT PCO DO PC16 NAND_ALE PAGE REFERENCE FUNCTION 1 TSLIDR_SL_SNSK PA17 TSC_BUSY ZB_IRQ1 PB1 ANA INPUT PC1 D1 PC17 NAND_CLE PA2 TSLIDR_SM_SNS PA18 ZB_RSTN PB2 ZB_NPCS2 PC2 D2 PC18 NAND_RDYBSY 3 J1 R1 External clock resource input TSLIDR SM SNSK PA19 LED BLUE PB3 USER PB1 PC3 D3 PC19 REGSEL_LCD Y1 R3 R7 Backup 12 2 crystal PA4 TSLIDR_SR_SNS PA20 LED_GREEN PB4 JTAG PC4 D4 PC20 LED_RED POWER R6 R8 Isolation between 12MHz clock source and GPIO line PA5 TSLIDR SR SNSK PA21 RXD1 PB5 JTAG PC5 D5 PC21 USB CNX R9 R10 Isolation between 32KHz clock source and GPIO line PA6 MCI CD PA22 TXD1 PB6 JTAG PC6 D6 PC22 TVALID_SNS 4 R22 Optional write protection on NAND flash PA7 CLK 32K PA23 COM1EN PB7 JTAG PC7 D7 PC23 TVALID_SNSK Pn SL els pd PES GUI TEM ROS dui R24 R30 Differential impedance matching for RS485 cable PA9 RX UARTO PA25 CTS1 PB9 CLK 12M PC9 NAND OE PC25 UP SNSK R25 Disconnect R8485 Receive data from 21 PA10 TX UARTO PA26 MCI PB10 USB DDM 10 WE PC26 TDWN SNS s me OR a Opina ESD pron er LCD par R61 R62 RA2 Optional data
7. 2 24 VECES PB7 a T 1 e 10 44 82 20 45 0 2 me JP7 T 95 PCTS C22 VDDIN Header 47 79 F 100nF e oo XOUTE 4819 a L 21 C23 XIN32 49 1077 JTAGSEL TT 47uF DGND 50 76 5 C24 VDDIO 0 t0uF e e e lo r o r 0 2 2 i lex eo VDDCORE poate x I3 x D ND AIMEL T col tel In WV 4 7uF Ss NOT POPULATED 29255 2 2 9 oss oxlozo DGND ROUSSET INIT EDIT JH 08 Mar 11 XXX s od d N EV DES DATE VER DATE As SM SAM4S EK SCALE 4 1 REV SHEET VDDCORE VDDio Ul 3 Microcontroller E A x 1 NS FLASH 815 Snie MN3 ega MT29F2GOBABAEA lt m 184
8. 4 30 4 5 14 Expansion Port B Connector J14 4 31 Section 5 SCHO uuu n una wis 5 1 Bel SchematicSu u u u uu au kaa 5 1 Section 6 SING OU BONO ERE ORE 6 1 6 1 _ l u ere oh n sense ob i bx ees eb 6 1 Section 7 Revision HISTORY 7 1 1 Fist me u 7 1 1 2 ANS 5 45 Development Board User Guide 11139 29 11 Introduction Section 1 Introduction 1 1 SAM4S Evaluation Kit The SAMAS Evaluation Kit SAMAS EK enables evaluation capabilities and code development of appli cations running on a SAM4S16 device 1 2 User Guide This guide focuses on the SAMAS EK board as an evaluation platform It is made up of 6 sections Section 1 includes references applicable documents acronyms and abbreviations Section 2 describes the kit contents its main features and specifications Section 3 provides board specifications Section 4 describes the development environment Section 5 provides instructions to power up the SAMAS EK and describes how to use it Section 6 describes the hardware resources default jumper and switch settings and connectors Section 7 provides sch
9. PB12 PWMLI ERASE _ x LM4040AIM3X 3 z 5 2 D ND B 25 Pip 8 8888 55559 88888 AM 57 gt gt gt o6 TEST a a zZ R107 DGND Header2 nm gt gt gt gt gt gt gt 0 9 O OG gt gt gt gt gt NA E e g s 9 ussss POND Sede fells VDDOUT VDDIN L 4 VBDIO PB O 14 J2 u 6 5 uf T 8 B3 B2B x 8 8 8 8 5 5 ajel Pel Pe Hel To DGND He He elle 18 Fe 8 5 100 Oo a a a aa GI Q O4 10 pgr V DDPLL ep e tep 4 4 PATS 28 98 lt S DDIO PCT 2915 97 XIN VDDCORE DGND DGND DGND PATS amp 96 31 95 PC6 Zlo PC25 33 93 PB13 24 34 5 o2 24 5 35 91 3619 0 9 pozz L VDDCORE 5a 71 9 92 1 PES 25 38 SOCKET THROUGHT HOLE 88 10 26 488 87 PB12 PC3 40 100 o 86 PC22 3 5 1 JP6 41 oles DDCORE VDDPLL Hegder2 VDDOUT VDDIO 3V3 42 84 peel TP TP2 TP3 4 0
10. close 1 2 and 2 5V close 2 3 JP3 ERASE OPEN Close to reinitialize the Flash contents and some of its NVM bits JP4 TEST k S Close for manufacturing test or fast programming mode JP5 VDDPLL CLOSE Access for current measurement on VDDPLL JP6 VDDIO CLOSE Access for current measurement on VDDIO JP7 VDDIN CLOSE Access for current measurement on VDDIN JP8 VDDCORE CLOSE Access for current measurement on VDDCORE JP9 CE FLASH CLOSE NCS0 enable NAND Flash chip select JP10 RS485 OPEN Maintain differential impedance for RS485 interface JP11 RS485 CLOSE Maintain impedance matching for RS485 interface JP12 RS485 OPEN Maintain differential impedance for RS485 interface JP13 CS CLOSE NCS1 chip select LCD CLOSE both 20db 14 15 GAINO Close both to lower gain stage on microphone input OPEN both 26db ibd JP16 ADC input OPEN Close for impedance matching on ADC BNC port JP17 JP19 MIC Gain stage Close to mux RIN LIN into MONO IN path within audio PA 1 2 ADC input potentiometer ELECT ADC INP gt x E 2 3 ADC input BNC JP20 MONO STEREO CLOSE Close to fix in mono speaker no matter the stereo plug state JP21 DAC output OPEN Close for impedance matching on DAC BNC port JP22 PIO expansioniJ12 2 3 Set to 3 3V position 1 2 sets to 5V voltage supply JP23 FID expansion 19 2 3 Set to 3 3V position 1 2 sets to 5V voltage supply JP24 PIO expansion J14 2 3 Set to 3 3V position 1 2 sets to 5V voltage supply JP25 BP2 CLOSE Open
11. 10K V T Potentiometer ADC amp e DGND CN3 BNC R106 OR 1 WN C90 2 2uF leader2 g ira 2 14 109 49 98 AUDIO_OUTL DGND DAC ROUSSET A INIT EDIT 08 Mar 11 XXX MODIF DES DATE VER DATE SAM4S EK SCALE 1 1 REV SHEET 6 Audio amp Power supply A 74 1 This agreement is our property Reproduction and publication without our will authorization shal expose ofender to legal proceedings PB O 14 PA O 31 PC 0 31 aval 39 40 DGND PIOC DGND J15 USB Micro B 8 9 FGND RV2 V5 5MLA0603 RVI V5 5MLAO603 21 T isa DGND FGND PB10 8114 278 WWW 11 R11 27R S Av USB ZB_RSTN SPIO_NPCS2 MISO Note Pin1 is not on the indentation side Pint 10 3V3 An j 3v3 Xo Xo R111 3348 19 2208 2 LED Blue 1 R113 PA20 220R D3 LEDGreen 20 RH 100K Si
12. 485 R23 2 R24 10K MN4 OR nm ADM3485ARZ 3V3 6 21 485 R25 nm 1 8 JP10 RXD1 WV VCC al Header2 CTS4 PA25 R26 pn Re 2 enp 100nF 51 24 R27 OR 3 PA22 R28 4 6 2 TXD1 WV DI 7 B o 0412 2 R29 JP11 2 420R o Header Header leader2 nm FGND R30 nm DGND 4 3 10 Display Interface The SAM4S EK carries a TFT Transmissive LCD module with touch panel FTM280C34D Its integrated driver IC is ILI9325 The LCD display area is 2 8 inches diagonally measured with a native resolution of 240 x 320 dots 4 3 11 LCD Module The LCD module gets reset from the NRST signal As explained this NRST is shared with the JTAG port and the push button BP1 The LCD chip select signal is connected to NCS1 the jumper JP13 can dis connect it so that this PIO line is available for other custom usage The SAM4S communicates with the LCD through PIOC where an 8 bit parallel 8080 like protocol data bus has to be implemented by software 4 6 5 45 Development Board User Guide 11139 29 11 Figure 4 8 LCD Block NRST gt 3V3 3043 el 344 eL 645 PC 0 31 1OuF T 100nF 100nF 25 DGND J8 FH26 39S 0 3SHW i PC7 LCD_DB1
13. B 5 45 Development Board User Guide ANS 4 27 11139A ATARM 29 Nov 1 1 Evaluation Kit Hardware 4 5 10 4 5 11 ZigBEE Connector J16 Figure 4 33 Headphone 11 Headphone Connector J11 Table 4 19 Headphone J11 Signal Descriptions Mnemonic AGND Out left Q O m Out Right Figure 4 34 ZigBee Connector J16 975 31 10 8 6 4 2 Table 4 20 Connector J16 Signal Descriptions Signal Signal Option on Misc Port Set by Function Name Port Pin Pin Port Name Function Zero Ohm Resistor or Solder Shunts EEPROM for MAC address CAP array R IRST settings and serial number esel 1 2 ue TST test mode activation CLKM RF chip clock output Interrupt 3 4 SLP_TR SLP TR Request 5 6 MOSI SPIMOSI select SPI MISO MISO 7 8 SCLK SPI CLK Power GND GND 9 10 vcc vcc Voltage range 1 8v to 5 5v typically Supply regulated to 3 3v 4 28 ANS 11139 29 11 5 45 Development Board User Guide 4 5 12 PIO Expansion Port Connector J12 Figure 4 35 PIO Expansion Connector J12 39 37 35 3331 29 2725 23 2119 171513 119 75 3 1 0 40 38 36 34 32 30 28 26 24 22 20 181614 1210 8 6 4 2 Table 4 21 Co
14. R 1K 1 99 AA sl C46 TT 2212 SL PAO PA3 NEN 1 SM 21 C48 FT 22nF PA2 sR 5 854 1K tw PA4 TP7 22 use X7R DGND EE ROUSSET INIT EDIT JH 08 Mar 11 XXX MODIF DES DATE VER DATE SAM4S EK SCALE 1 1 REV SHEET 5 TFT LCD 8 QTouch A 74 Tis ane pp Repent UU 1 AUDIO IN 62 AVDD T opF R77 m 470R R75 478 JP14 SA Header 876 ANE e c63 g R78 067 R80 7 1uF 1K 1K 2 R81 R83 AGND 1 1008 OR ISVB6050 R82 R84 OUT1 NN gt 1 1K 3 cn cum 4 IN1 29nF e C69 el C72 R85 uF 2 1K inF inF R86 gt R87 AGND E 47K AVDD VCC33 8 Pipe AGND AGND vcc L D F 22uF 2 A 15 2 AVDD Od Header2 74 BNO3K314S300R 100nF ETA R91 4 OUT2 4 oR AGND AGND 2 R90 6 GND WW IN2 x A 5 AGND DGND IN2 R93 100K JP14 and JP15 should set or removed together x s AGND AGND 4 J10 AUDIO OUT s 5V MN13 FB3 TPA0223DGQ BN03K314S300R VDD Hi 3 JP29 2 Qu on Ronan EG
15. amp Power Supply USB LEDs push buttons amp ZigBEE SAM4S EK Development Board User Guide 5 1 11139A ATARM 29 Nov 11 5 V Input POWER SUPPLY FOWER 3 3V NAND FLASH AUDIO In ADC PIO A B C Micro SD Samisk 27 AUDIO Out DAC PHONE mic JACK ATMEL Cortex M4 ARM Processor 5 45 LQFP100 RS232 USART1 ADC DAC PIO A B C USART1 ICE HE 10 RS485 QTOUCH Sheet 4 LCD INTERFACE 2 8 240x320 TFT FS DEVICE TOUCH SCREEN Sheet 5 ZIGBEE INTERFACE LEDs Buttons Board Configuration Sheet PIO A B C Extension Sheet 7 Sheet 2 Sheet 3 AIMEL ROUSSET A INIT EDIT JH 08 Mar 11 XXX MODIF DES DATE VER DATE SAM4S EK SCALE 1 1 REV SHEET L LUI Block Diagram 5 A agreement is our propery Paprducin and win wen authorizaton sal expose ofender legal proceeds 1 REVISION HISTORY SCHEMATICS CONVENTIONS JUMPER and SOLDERDROP REV DATA NOTE 1 Resistance Unit is Kohm R is Ohm PAGE REFE
16. are registered trademarks or trademarks of Microsoft Corporation in the US and or other coun tries Other terms and product names may be trademarks of others 11139 29 11
17. buttons Left and Right QTouch buttons Up Down Left Right Valid and Slider Full Speed USB device port JTAG ICE port On board power regulation Two user LEDs Power LED BNC connector for ADC input BNC connector for DAC output User potentiometer connected to the ADC input ZigBEE connector 2x32 bit PIO connection interfaces PIOA PIOC and 1x16 bit PIO connection interface PIOB 4 3 Function Blocks 4 3 1 Processor The SAM4S EK is equipped with a SAM4S16 device in LQFP100 package 4 3 2 Memory The SAMAS16 chip embeds 4 2 11139A ATARM 29 Nov 1 1 1024 Kbytes of embedded Flash 128 Kbytes of embedded SRAM 16 Kbytes of ROM with embedded BootLoader routines UART USB and In Application Programming functions IAP routines ANS 5 45 Development Board User Guide Evaluation Kit Hardware The SAM4S features an External Bus Interface EBI that permits interfacing to a broad range of external memories and virtually to any parallel peripheral The SAM4S EK board is equipped with a memory device connected to the SAM4 EBI One NAND Flash MT29F2GO8ABAEA Figure 4 2 Flash NAND FLASH Ri5 25 MIS RAN MT29F2GOBABAEA 17 16 29 16 17 voo 30 PCi PCS g ALE 10 184 RE 19217
18. low JTAG Reset Output from SAM ICE to the Reset signal on the target JTAG port 3 Output sianalthat resets the target Typically connected to nTRST on the target CPU This pin is normally pulled 9 HIGH on the target to avoid unintentional resets when there is no connection 4 GND Common ground TBI TEST DATA INBUT data data input of target CPU It is recommended that this pin is pulled to a 5 output line sampled on the rising edge 4 defined state on the target board Typically connected to TDI on target CPU of the TCK signal 6 GND Common ground JTAG mode set input of target CPU This pin should be pulled up on the target 7 TMS TEST MODE SELECT Typically connected to TMS on target CPU Output signal that sequences the target s JTAG state machine sampled on the rising edge of the TCK signal 8 GND Common ground 9 ee clock signal to target CPU It is recommended that this pin is pulled to a gna y 9 9 defined state on the target board Typically connected to on target CPU control register access 10 GND Common ground Some targets must synchronize the JTAG inputs to internal clocks To assist in RTCK meeting this requirement a returned and retimed TCK can be used to 11 Input Return test clock signal from the dynamically control the TCK rate SAM ICE supports adaptive clocking which target waits for TCK changes to be echoed correctly before making further changes Connect to RTCK if avail
19. 3222 Pos TPS vos 41 Pea Header Vos 42 P 55 94 co PC18 R19 AA R 4 ins a WP N C28 47 3V3 1 N C27 46 L 47K 2 N C26 45 NN 7 3 N c2 N C25 39 4 N C24 39 R22 s 4 N C23 3g OR nm 6 N C5 PRE 35 N C6 N C22 37 11 N C21 33 DGND 15 27 20 N C10 N C18 43V3 21 11 37 T 22 N C12 vcc iz 7 23 N C13 C27 9 C28 e C29 2415614 100nFT 100nFT 1uF 25 15 36 26 N C16 vss 535 1 7 N C17 vss DGND NCSO chip select signal is used for NAND Flash chip selection Furthermore a dedicated jumper JP9 can disconnect it from the on board memories thereby letting NCSO free for other custom purpose 4 3 3 Clock Circuitry The clock generator of a SAM4S microcontroller is made up of m A Low Power 32 768 Hz Slow Clock Oscillator with bypass mode m to 20 MHz Crystal Oscillator which can be bypassed 12 MHz needed in case of USB A factory programmed fast internal RC Oscillator 3 output frequencies can be selected 4 default value 8 or 12 MHz m A 60 to 130 MHz PLL providing a clock for the USB Full Speed Controller m A 60 to 130 MHz programmable PLL PLLA capable to provide the clock MCK to the processor and to the peripherals The input frequency of PLLA is from 7 5 and 20 MHz The 5 45 board is equipped with one 12 MHz crystal optional Pi
20. 4 27R 11 RUG AAY 278 Analog Interface 4 3 18 1 Analog Reference voltage reference is based on an LM4040 Precision Micropower Shunt Voltage Reference This ADVREF level can be set as 3V or 3 3V via the jumper JP2 Figure 4 15 Analog Vref VCC33 5 5 45 ADVREF ADVREF 2 E ue n 2 2K 5 _ 4 100 MN2 LM4040 2 5 DGND SAMAS EK Development Board User Guide AS 4 11 11139A ATARM 29 Nov 1 1 Evaluation Kit Hardware 4 3 18 2 Analog Input The BNC connector CN1 is connected to the ADC port PB1 as an external analog input An on board 50 Ohm resistor termination can be applied by closing jumper JP16 A low pass filter can be implemented for the BNC connector CN1 by replacing R94 and C78 with custom resistor and capacitor values depending on your application requirements A 10 KOhm potentiometer VR1 is also connected to this channel to implement an easy access to ADC programming and debugging or implement an analog user control like display brightness volume etc Either of these two functions can be selected by jumper JP 18 Figure 4 16 ADC Input R94 OR NN 0 JP16 Header2 _le c78 Roe 10nF 49 9R DGND 7 ADS VCC33 5 2 gt VR1 2 10K re 1 Potentiometer ADC e 8 DGND 4 3 18 3 Analog Output The BNC connector CN2 is connected to the DAC port PB1
21. 4 and JP15 are off m 26 dB both JP14 and JP15 are on Note 3 The TB1 series 0 Ohm resistor is a reservation for future impedance adaptation facility Under specific amplifier settings conditions this enables the easy insertion of a capaci tor or any other bipolar device on the audio path On the other hand R83 is a default 0 Ohm resistor that enables the disconnection of PBO from the audio input path for cus tom usage 4 The audio pre amplifier MN11 is powered by a dedicated low dropout regulator MIC5219 3 3 MN14 SAMAS EK Development Board User Guide ANS 4 9 11139A ATARM 29 Nov 1 1 Evaluation Kit Hardware Figure 4 12 Microphone Input gt PBO AUDIO IN C62 100pF AVDD sil R77 2 470R R75 pyp 47K JP14 7 Header 1 R76 AA 47 1 e 63 R78 22uF 2 C67 MN11 R79 R80 1K Re 15922 AGND t ig us 1 TOOR oR 5 6050 R82 R84 OUT1 ANN 1 1K 3 sj ANN IN1 FE C68 ie R86 gt R87 AGND 47K 47K i AVDD VCC33 AGND AGND 73 vec QD 2242 470R O9 15 FB2 AVDD Od Header2 74 03 3145300 T 100nF 52 OUT2 AGND AGND T 8 4 WWW IN2 s 4 AGND DGND IN2 R93 sl 677 100K JP14 and JP15 should be set or removed together AGND AGND 4 3 16 1 Headphone Output The SAM4S EK evaluation kit
22. 4 and provides an external analog output An on board 50 Ohm resistor termination can be enabled by closing jumper JP21 A filter can be imple mented on this output channel by replacing R106 and C90 with appropriate resistor and capacitor values depending on the application requirements Figure 4 17 DAC Output CN2 R106 SOLDER DROP 2 pins open Normal BNC 1 WV 1 2 lt lt 14 21 C90 2 2uF SD1 1 2 502 jo R109 49 9R 1 AUDIO OUTL DACO1 DGND DAC 4 3 19 QTouch Elements QTouch keys consist in a series of sensors formed by the association of a copper area and the capaci tive effect of human fingers approaching it 4 3 19 1 Keys The SAM4S EK implements five individual capacitive touch keys UP DOWN RIGHT LEFT and VALID using five pairs of PIO 4 12 5 45 Development Board User Guide 11139 29 11 Evaluation Kit Hardware Figure 4 18 QST Keys PC25 R51 1K ANN 2 47 T 22nF 24 K1 PC31 P53 AAA QTouch Key e T 22 PC30 1K PC29 R55 ANN C51 22nF PC28 1K PC23 R57 L C52 22nF PC22 27 R60 1K Pe WV _ C53 22nF QTOUCH 4 3 19 2 Slider A group of channels forms a Slider A Slider is composed of three channels for a QTouch acquisition method using three pairs of PIO Such a sensor is used to detect a l
23. 6 NC 14 LCD 0805 NC LCD DBO4 16 LCD 0803 LCD 0802 NC 18 LCD 01 NC LCD DBOO NC 20 3V3 RD PC11 22 WR PC8 RS PC19 24 CS 15 RESET 26 IMO IM1 28 GND LED A 30 LED K1 LED K2 32 LED K3 LED K4 34 Y UP Y DOWN 36 X RIGHT X LEFT 38 NC GND 4 24 5 45 Development Board User Guide 11139 29 11 4 5 6 JTAG Debugging Connector J6 Evaluation Kit Hardware This JTAG connector is a 20 way Insulation Displacement Connector IDC keyed box header 2 54 mm male that mates with IDC sockets mounted on a ribbon cable Its signal assignment is compatible with the SAM ICE or any similar third party interface Figure 4 29 JTAG ICE Connector J6 19 17151311975 3 1 20 181614 1210 8 6 4 2 Table 4 15 JTAG ICE Connector J13 Signal Descriptions Pin Mnemonic Description This is the target reference voltage It is used to check if the target has power to 1 VTref 3 3V power create the logic level reference for the input comparators and to control the output id logic levels to the target It is normally fed from Vdd on the target board and must not have a series resistor 2 Vsupplv 3 3V power This pin is not connected in SAM ICE It is reserved for compatibility with other equipment Connect Vdd or leave open target system nTRST TARGET RESET Active
24. 7 1 2 VoD PC6 LCD 0816 DB47 5 LCD 0815 5816 4 LCD 0814 g DB15 PC3 LCD DB13 5 BB14 2 LCD 0812 9818 PC1 LCD 8 0812 PCO LCD DBIO 9 DB11 LCD 089 10 5810 LCD 088 111 589 LCD 12 088 LCD_DB6 13 DB7 LCD_DB5 14 086 LCD_DB4 15 989 LCD 083 16 DB4 LCD 082 i7 DB3 LCD DB1 18 DB2 LCD_DBO 191 eed 11 20 DBO PCB 19 22 RD 25 WR PC15 JP13 Header2 24 RS NRST Gu 25 CS 36 RESET 57 0 58 M1 GND LED A R59 29 Ki 30 LED A 2 R58 IED K 31 LEDK1 4 7K LEDK2 LED K3 32 LED K4 33 LEDKS UP x lt Y DOWN 35 vt DGND XCRIGHT 36 Y 37 Xt 38 NC The part is placed as close as possible to J8 LCD D1 4 3 12 Backlight Control DGND PACDNO44Y5R nm TVS SOT23 5 Evaluation Kit Hardware DGND DGND DGND DGND PIN 39 FTM280C34D V P DGND DGND Six slots on PCB for LCD shield LCD DBO R61 2 083 3 6 47Kx4 nm LCD DB1 4 LCD 088 LCD 086 2 7 RAS LCD_DB7 3 6_4 7 nm LCD 4 5 LCD DB9 _R63 ATK ME DGND The LCD backlight is made of four integrated white chip LEDs arranged in parallel These are driven by an AAT3155 charge pump MN8 The AAT3155 is controlled by the S
25. A30 PWML2 NPCS2 MCDAO WKUP11 POI DC6 MCI data bit 0 32 PA31 NPCS1 PCK2 MCDA1 POI DC7 MCI data bit 1 Table 4 2 PIO Port B Pin Assignments and Signal Descriptions y o Peripheral Peripheral Peripheral System No Line A B Extra Function Function Comment 1 PBO PWMHO AD4 Microphone input 2 PB1 PWMH1 AD5 Analog input 3 PB2 URXD1 NPCS2 AD6 WKUP12 ZigBee chip select 4 PB3 UTXD1 PCK2 AD7 User push button 1 5 4 TWD1 PWMH2 TDI JTAG data in 6 PB5 TWCK1 PWMLO WKUP13 bu JTAG data out TRACESWO 7 PB6 TMS SWDIO JTAG test mode select 8 PB7 TCK SWCLK JTAG clock 9 PB8 XOUT CLK12MHz 10 PB9 XIN CLK12MHz 11 PB10 DDM USB DM 12 PB11 DDP USB DP 13 PB12 PWML1 ERASE Flash erase selector 14 PB13 PWML2 PCKO DACO Audio Output R 15 PB14 NPCS1 PWMH3 DAC1 Audio Output L 5 45 Development Board User Guide 4 17 11139 29 11 Evaluation Kit Hardware Table 4 3 PIO Port C Pin Assignments and Signal Descriptions Peripheral Peripheral Extra System No Line Peripheral A B C Function Function Comments 1 PCO DO PWMLO EBI DO 2 PC1 D1 PWML1 EBI D1 3 PC2 D2 PWML2 EBI D2 4 PWML3 EBI D3 5 PC4 D4 NPCS1 EBI D4 6 PC5 D5 EBI D5 7 PC6 D6 EBI D6 8 PC7 D7 D7 9 PC8 NWRO NWE TFT LCD write enable 10 PC9 NANDOE NAND Flash output enable 11 PC10 NANDWE NAN
26. AM4S through a single PIO line PC13 interface the 0 Ohm resistor R68 is mounted in series on this line which permits to use it for other custom purposes In that case the pull up resistor R64 maintains the charge pump permanently enabled by default On the anode drive line a 0 Ohm resistor R59 is implemented in series for an optional current limitation Figure 4 9 Backlight Control 5 45 Development Board User Guide AAT3155ITP T1 2 tt 21 C54 21 C55 ar tur FT R68 6 TP7 OR Cte 62 PC13 1i 4 EN SET 8 LED A 1 5 313 BN03K314S300R 3 LED_K1 t C56 C57 2 LED K2 FT 1uF QI 02 1 ral sub r2 LED DGND DGND LCD BACKLIGHT 4 7 11139A ATARM 29 Nov 1 1 Evaluation Kit Hardware 4 3 13 4 3 14 4 8 Touch Screen Interface The LCD module integrates a 4 wire touch panel controlled by MN7 ADS7843 which is a slave device on the SAM4S SPI bus The controller sends back the information about the X and Y positions as well as a measurement for the pressure applied to the touch panel The touch panel can be used with either a stylus or a finger ADS7843 touch panel controller connects to the SPIO interface via the NPCSO control signal Two interrupt signals are connected and provide events information back to the microcontroller Penlrq and Busy Note Penlrq PA16 is share
27. AND DISCLAIMS ANY EXPRESS IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABLLITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT INDIRECT CONSEQUENTIAL PUNITIVE SPECIAL OR INCIDEN TAL DAMAGES INCLUDING WITHOUT LIMITATION DAMAGES FOR LOSS OF PROFITS BUSINESS INTERRUPTION OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifica tions and product descriptions at any time without notice Atmel does not make any commitment to update the information contained herein Unless specifically pro vided otherwise Atmel products are not suitable for and shall not be used in automotive applications Atmel s products are not intended authorized or warranted for use as components in applications intended to support or sustain life OWERED 2011 Atmel Corporation All rights reserved Atmel logo and combinations thereof DataFlash SAM BA and others are registered trade marks or trademarks of Atmel Corporation or its subsidiaries ARM Thumb and the ARMPowered logo and others are registered trademarks or trademarks ARM Ltd Windows and others
28. C81 9 220uF TAN 6 3V 5 j VCC33 _c79 4080 e C82 R85 3 tuF 10 100nF D r97 1K 1 NGC NU ON F TAN6 3V DGND AGND uF LO MO PB13 gt G84 0 47uF R98 AA eK lt AGND 17 Heada99 47K 2P Mv VDD_AMP TP12 C85 0 47uF_R100 33K 1 cd R101 100K R102 100K TesPadsQ4orH WW MONO IN STN WwW 1 as 2 8103 100 JP19 7 3 HeadB204 47 SHUTDOWN Mv T BYPASS 4 C86 0 47 e 87 2 AUDIO_OUTL ces 0 470 1 8105 AA 33 S LN i Header 2 GND B s NU Nut AGND AGND AGND AGND MN14 45V MIC5219 3 3YMM VCC33 2 N 3 21 c91 1 5 C92 EN GND 100uF TAN 6 3V GND 5 4 GND Fg X BYP GND 2 DGND DGND DGND DGND 49 MN9 MN10 Power Jack 2 1mm ZEN056V130A24LS BNX002 01 5V 1 1 3 1 3 G a SV 2 4 D SG CG1 C64 C65 5 66 C98 CG2 a 100nF 22uF 1 22uF 220uF ELE 16V bd DGND MN12 MIC29152WU Micrel s 1 5A LDO TO263 5 5V 3V3 vour 4 7 1 5 080 xz ADJ R89 9 169 1 70 075 e C76 ae TT 100uF TAN 6 4V 100nF R92 102K 1 DGND BNC R94 OR JP16 od Header2 le C78 gt Roe 10 49 98 DGND VCC33 4 ADS 2 mE gt Pat VR1 2 A
29. D Flash write enable 12 PC11 NRD TFT LCD read enable 13 PC12 NCS3 AD12 User push button 2 14 PC13 NWAIT PWMLO AD10 LCD backlight control 15 PC14 NCSO NAND Flash chip select 16 PC15 NCS1 PWML1 AD11 TFT LCD chip select 17 PC16 A21 NANDALE NAND Flash ALE 18 PC17 A22 NANDCLE NAND Flash CLE 19 PC18 0 50 RDYBSY NAND Flash RDY BSY 20 PC19 1 1 TFT LCD RegSel 21 PC20 A2 PWMH2 Red LED Power 22 PC21 A3 PWMH3 USB Vbus detection 23 PC22 A4 PWML3 QTouch valid button SNS 24 PC23 5 QTouch valid button SNSK 25 PC24 A6 TIOB3 QTouch up button SNS 26 PC25 7 QTouch up button SNSK 27 PC26 A8 TIOA4 QTouch down button SNS 28 PC27 9 TIOB4 QTouch down button SNSK 29 PC28 A10 TCLK4 AD13 QTouch left button SNS 30 PC29 11 5 AD14 QTouch left button SNSK 31 PC30 12 5 QTouch right button SNS 32 PC31 A13 TCLK5 QTouch right button SNSK 4 18 5 45 Development Board User Guide 11139 29 11 4 4 2 Jumpers Evaluation Kit Hardware The SAM4S EK board jumpers are essentially used for two main purposes functional selection or cur rent measurement Details are given below Table 4 4 Jumpers Setting Designation Label Default Setting Feature JP1 JTAG OPEN Close to select the JTAG boundary scan of the SAM4S 2 ADVREF 1 2 Analog reference voltage selection between 3 3V
30. D TRANSMITTED DATA RS232 serial data output signal 3 RXD RECEIVED DATA RS232 serial data input signal 5 GND GROUND 7 RTS READY TO SEND Active positive RS232 input signal 8 CTS CLEAR TO SEND Active positive RS232 output signal 4 5 3 UART Connector J7 Male RS232 UART connector J7 Table 4 12 Male RS232 UART Connector J7 Signal Descriptions Pin Mnemonic Signal Description 1 4 6 7 8 9 CONNECTION 2 TXD TRANSMITTED DATA RS232 serial data output signal 3 RXD RECEIVED DATA RS232 serial data input signal 5 GND GROUND 4 5 4 USB Device Connector J15 Figure 4 27 Micro B USB Connector J15 Table 4 13 Micro B USB Connector J15 Signal Descriptions Mnemonic Signal Description power 2 DM Data 3 DP Data 4 Gnd Ground 5 Shield Shield SAMAS EK Development Board User Guide ANS 4 23 11139A ATARM 29 Nov 1 1 Evaluation Kit Hardware 4 5 5 TFT LCD Connector J8 One 39 pin connector is available on the board to connect the LCD module backlight and touch screen Figure 4 28 LCD Connector J8 I mn Table 4 14 LCD Connector J8 Signal Descriptions Mnemonic Pin Mnemonic 3V3 2 LCD_DB17 PC7 LCD_DB16 PC6 4 LCD_DB15 5 LCD_DB14 PC4 6 LCD_DB13 PC3 LCD_DB12 PC2 8 LCD_DB11 PC1 LCD_DB10 PCO 10 LCD 0809 NC LCD 0808 NC 12 LCD 0807 LCD 080
31. F TAN 6 3V GND GND Fg s lt BYP GND 1 470pF DGND DGND 4 10 11139A ATARM 29 Nov 11 5 45 Development Board User Guide 4 3 17 4 3 18 Evaluation Kit Hardware Using a readily available 1 8 in 3 5 mm stereo headphone jack the control switch is closed when no plug is inserted When closed a 100 kOhm 1 kOhm divider pulls the ST MN input low When a jack plug is inserted the 1 kOhm resistor is disconnected and the ST MN input is pulled high The mono speaker J10 connector is also physically disconnected from the RO MO output so that no sound is heard from the speaker while the headphones are inserted USB Device The SAMAS UDP port is compliant with the Universal Serial Bus USB rev 2 0 Full Speed device speci fication J15 is a micro B type receptacle for USB device Both 27 Ohm resistors R114 and R116 build up a 90 Ohm differential impedance together with the embedded 6 Ohm output impedance of the SAMAS full speed channel drivers R110 and R112 build up a divider bridge from VBUS 5V to implement plug in detection 5V level gets lowered to a PIO compatible 3 3V level through PC21 Figure 4 14 USB J15 USB Micro B 8 5V D Dt ID G 7 s CF FGND al o V5 5MLAO603 RV1 V5 5MLA0603 PC21 R110 47 e C94 112 68K 10pF x EEF DGND FGND DGND PB10 R11
32. INIT EDIT JH 08 Mar 11 XXX XX XXX EM DES DATE VER DATE SCALE 1 1 REV SHEET Ui 4 A X This agreements our propery Reproduction and publication without our writen authorization shal expose offender proceedings 1 043 1 C44 el C45 PA 0 31 PC 0 31 10uF T 100nF T 100 209 kri DGND DGND zs fs J8 EL FH26 39S 0 3SHW 1 F y PC7 LCD_DB17 T z7 VOD PCE DBIS DBIT PC5 8818 4 5 DB15 DBi4 PC2 5812 7 0813 1 _ 11 8 DB12 20810 g 0811 LCD DB9 10 DBI0 LCD 088 11 989 LCD DB7 42 DB8 LCD DB6 1 987 LCD 085 14 586 LCD DB4 15 LCD DB3 16 084 pene LCD 082 17 983 LCD DB1 18 DB2 LCD DB0 19 BB PCH 20 580 21 Hd 19 22 WR PIN 39 15 JP13 Header2 24 RS NRST woe 25 CS NRST gt gt Sg RESET 5H 2g 1 GND LED A R59 AAA
33. PCS 42 E ANN 11 NPCSO PWMHO PAi2 MISO PWMH1 33 FAIS 7 PA13 MOSI PWMH2 37 35 788 lt gt PB2 URXD1 NPCS2 AD12B6 14 SPCK PWMH3 35 PB3 9 PA15 TF 58 DII BET lt gt PB3_UTXD1_PCK2_AD12B7 PA16 TK PWML2 15 WW PA17 TD PCK1 PWMH3 AD12B0 44 PATE c4 R12 PA18 RD PCK2 A14 01281 ig PUE 20pF OR PA19 RK PWMLO A15 AD12B2 PB10 lt gt 88 PBi0 DDM AT91SAM4S LQFP100 PA20 RF PWML1 A16 AD12B3 28 2 puis 89 PA21 PCK1 AD12B8 55 PAOZ 11 lt lt gt PB11 PA22 TXDi NPCS3 NCS2 AD12B9 55 ADS p PA23 SCKi PWMHO A19 3q PRADA Header2 nm PA24 RTS1 PWMH1 A20 35 PT PA25 CTS1 PWMH2 A23 35 PADS F3 UTAGSEL 77 PA26_DCD1_TIOA2 MCDA2 5 JTAGSEL PA27 DTR1 TIOB2 29 S 51 PA28 DSR1 TCLK1 MCCDA 53 m VCC33 3g PB4 TWD1 PWMH2 TDI 29 TCLK2 MCCK 63 gt 53 PB6 TMS SWDIO PA30 PWML2 NPCS2 MCDAO 81 PAST 45V gt FES 76 SWCLK PA31_NPCS1_PCK2_MCDA1 Ed 5 5 PWMLO NRST C NAST 60 ADVREF 1 5 3 SONS gt PBO_PWMHO_AD12B4 93 PB13 cs gt PB1 PWMH1 AD12B5 PB13 PWML2 _ 22 12 gt PB13 iE E oe 7 PB14_NPCS1_PWMH3_DACO1 99 14 14 5
34. R113 iS 220R PA20 ANN D3 Green led d PC20 R115 100K 4 1 2 R117 LS IRLML2502 220R T 2 3 ANN 04 4 Red led DGND 4 3 22 SD MMC Card The SAM4S EK has a high speed 4 bit multimedia MMC interface which is connected to a 4 bit SD MMC micro card slot featuring a card detection switch Figure 4 22 SD Card 1 Sh2 6 ves 7 PA31 DATO 4 1 10 DGND esp PAG il C25 C26 100nF DGND 4 3 23 ZigBEE SAMAS has 10 pin male connector for the RZ600 ZigBEE module Note 0 Ohm resistors have been implemented in series with the PIO lines that are used else where in the design thereby enabling their individual disconnection should a conflict occur in your application 4 14 5 45 Development Board User Guide 11139 29 11 Evaluation Kit Hardware Figure 4 23 ZigBEE Interface 16 ZB RSTN PA18 8118 1 2 8120 OR 16 ZBEE IRQL_ZBEE 17 RTI oR 3 4 RIZ 15 SLP TR SPIO_NPCS2 PB2 5 6 1 MOSI JP27 MISO 12 14 5 19 4 C95 C96 C97 18pF 2 2nF 2 2uF DGND 4 3 24 Expansion SAM4S product features three PIO controllers PIOA w
35. R117 IRLML2502 2 a D4 LED Red 4 DGND J16 10 5x2 PA18 R118 OR 1 2 R120 OR 16 0 2 17 RIGOR 24514 RIZR OR 15 2 5 6 PATS JP27 2 ee 14 Header2 3 3 9 10 zx zx c95 c96 97 18 2 2nF 2 2uF ZIGBEE PEND 3V3 R122 TWD1 PB4 4 7K nm R123 TWCK1 PB5 4 7K nm 1 1 m 3 29 G44 gt 2 JP25 1 m 3 Header2 29 B4 JP26 1 ER 3 Header2 24 12 Mn BUTTONS 45V DGND PROTOTYPE AREA Pitch 2 54 ee ef ROUSSET INIT EDIT JH 08 Mar 11 XXX XX XXX EV MODIF DES DATE VER DATE SAM4S EK SCALE 1 1 REV SHEET prti 7 User IF amp ZigBee A art or pln ouw aoro exposa sgl procedit 1 AMEL Section 6 Troubleshooting 6 1 Board Recovery Closing JP3 and powering the board will assert ERASE and clear GPNVM bit 1 and thereby selects the boot from the ROM by default The MCU will boot from the internal ROM to enable a SAM BA connection through the UART Connect the SAM4S EK UART port J3 to a PC COM port through an RS232 cross over cable You can then run the SAM BA application from that PC to program the internal Flash of the MCU as well as the GPNVM bit 1 SAM4S EK Dev
36. RENCE DEFAULT FUNCTION 5 3 Close to select JTAG boundary scan 2908 ORIGINAL RELEASED b eae the component is not populated JP2 1 2 Analog reference voltage selection between 3 3V and 3 0V JP3 OPEN Close to reinitialize the Flash contents and some of its NVM bits JP4 OPEN Close for manufacturing test or fast programming mode JP5 JP6 7 CLOSE Access for current measurement on each power rail 4 JP9 CLOSE Nand Flash chip select enable JP11 CLOSE RS485 bus termination enable TABLE OF CONTENTS TEST POINT JP10 JP12 OPEN RS485 pull resistor selectors JP31 1 2 RS232 USART and 5485 selection PAGE DESCRIPTION PAGE REFERENCE FUNCTION 5 JP13 CLOSE LCD chip select enable 1 Block Diagram 3 TP1 TP2 TP3 TP4 GND 6 JP14 JP15 OPEN Sync close to degrade gain stage on microphone input 2 Reference guide TP5 UART TXD JP17 JP19 OPEN Close to mux RIN LIN into MONO IN path within audio PA 3 Microcontroller 4 YP6 WAGERS JP16 JP21 OPEN Close for impedance matching on AD DA BNC port 4 NAND Flash RS232 RS485 MCI JTAG JP18 1 2 ADC input selection between BNC port and potentiometer 5 LCD Touch items 5 TP7 LCD backlight driver anode JP20 OPEN Close to fix in mono speaker mode no matter stereo plug state 6 Audio AD DA Power TP8 9 Aux ADC input for TSC JP29 1 2 AUDIO Amplifier power select between 5V and VCC33 7 10 Expansion USB ZigBEE LED Button JP30 1 2 DAC output between AUDIO left channel and BNC connector 6
37. SAM4S EK Development Board User Guide AMEL 11139A ATARM 29 Nov 11 1 2 5 45 Development Board User Guide 11139 29 11 Section 1 1 1 11 SAMA4S Evaluation 1 1 IAN ECUDO 1 1 1 3 References and Applicable 1 1 Section 2 E S e P 2 1 21 a O a E a Sa T AAE EA EARE EAEE AANE TERNAT 2 1 2 2 Electrostatic 2 2 Section 3 REA 3 1 3 1 Power up the 9 3 1 3 2 Sample Code and Technical Support a 3 1 Section 4 Evaluation Kit HardWare 4 1 4 1 4 1 42 HH 4 2 CECI ele disce 4 2 4 3 1 Processorer as EXE EUR 4 2 4 3 2 ED 4 2 43 3 Clock Circuitry iot eene tse ra deve ea ace usu as 4 3 4 3 4 Reset Circuitry uie edu ag eden rea 4 4 4 3 5 Power Sup
38. UP4 QTouch slider right SNSK 7 PA6 TXDO PCKO MCI card detection 8 PA7 RTSO PWMH3 XIN32 CLK32KHz 9 PA8 CTSO WKUP5 XOUT32 CLK32KHz 10 9 URXDO NPCS1 PWMFIO WKUP6 UART receive data 11 PA10 UTXDO NPCS2 UART transmit data 12 PA11 NPCSO PWMHO WKUP7 NPCSO TSC 13 PA12 MISO PWMH1 MISO_TSC ZigBEE MISO 14 PA13 MOSI PWMH2 MOSI TSC ZigBEE MOSI 15 PA14 SPCK PWMHS WKUP8 SPCK_TSC ZigBEE CLK 16 PA15 TF TIOA1 PWML3 WKUP14 PIO ZigBEE SLPTR 17 PA16 TK TIOB1 PWML2 WKUP15 PIO_DCEN2 IRQ_TSC ZigBEE IRQO 18 PA17 TD PCK1 PWMH3 ADO BUSY_TSC ZigBEE IRQ1 19 PA18 RD PCK2 14 AD1 ZigBEE RSTN 20 PA19 RK PWMLO A15 AD2 WKUP9 Blue LED UserLED1 21 PA20 RF PWML1 A16 AD3 WKUP10 Green LED UserLED2 22 PA21 RXD1 PCK1 AD8 USART RXD 23 PA22 TXD1 NPCS3 NCS2 AD9 USART TXD 24 PA23 SCK1 PWMHO A19 POI DCCLK USART transceiver enable 25 PA24 RTS1 PWMH1 A20 POI DCO USART RTS 26 PA25 CTS1 PWMH2 A23 POI DC1 USART CTS 27 PA26 DCD1 TIOA2 MCDA2 POI DC2 MCI data bit 2 28 PA27 DTR1 TIOB2 MCDAS3 POI MCI data bit 3 29 PA28 DSR1 TCLK1 MCCDA POI DC4 MCI command 4 16 5 45 Development Board User Guide 11139 29 11 Table 4 1 PIO Port Pin Assignments and Signal Descriptions Continued Evaluation Kit Hardware yo Peripheral Peripheral Peripheral System No Line A B Extra Function Function Comment 30 PA29 TCLK2 MCCK POI DC5 MCI clock 31 P
39. able otherwise to GND 12 GND Common ground TDO JTAG TEST DATA OUTPUT 13 Serial data input from the target JTAG data output from target CPU Typically connected to TDO on target CPU 14 GND Common ground 5 45 Development Board User Guide 4 25 11139A ATARM 29 Nov 11 Evaluation Kit Hardware Table 4 15 JTAG ICE Connector J13 Signal Descriptions Continued Pin Mnemonic Description 15 nSRST RESET Active low reset signal Target CPU reset signal 16 GND Common ground 17 RFU This pin is not connected in SAM ICE 18 GND Common ground 19 RFU This pin is not connected in SAM ICE 20 GND Common ground 4 5 7 SD MMC MCI Connector J3 Figure 4 30 SD MMC Connector J3 Pin Mnemonic RSV DAT3 2 CDA GND 4 VCC CLK 6 GND DATO 8 DAT1 DAT2 10 Card Detect GND 12 4 26 5 45 Development Board User Guide 11139 29 11 Evaluation Kit Hardware 4 5 8 Analog Connector CN1 amp CN2 Figure 4 31 Analog Input Connector CN1 and Analog Output CN2 Bottom View 625 EY AS 9 3 Table 4 17 Analog Input Output Connector CN1 CN2 Signal Descriptions Analog input PB1 for CN1 and analog output PB13 for CN2 respectively 4 5 9 RS485 Connector J14 Figure 4 32 RS485 Connector J14 Mnemonic non inverted RS485 signal 2 Frame ground 3 B non inverted RS485 signal
40. annels to reduce the processor time on packet handling This two pin UART TXD and RXD only is buffered through an RS232 Transceiver MN6 and brought to the DB9 male connector J7 Figure 4 5 MN6 MAX3232CSE 3V3 16 vec H C39 2 c38 100nF 100nF 3 3v3 93 eL 40 is 100 6 54 2 2 e C41 el C42 R45 R46 S Mk 100nF 100nF GND C2 11 14 1 0 lt gt 1 Ra oR 127 T1OUT 13 9 lt gt Mt 107 RIOUT 7 tras JR g T2OUT SN R20UT R2IN e 5 PGND SMD SMD 4 3 7 USART The Universal Synchronous Asynchronous Receiver Transmitter USART provides one full duplex uni versal synchronous asynchronous serial link The data frame format is extensively configurable data length parity number of stop bits to support a broad range of serial communication standards The USART is also associated with PDC channels for TX RX data access Note For design optimization purposes both transmitters have been implemented on the same PIO lines that is PA21 22 23 24 25 To avoid any electrical conflict the RS485 transceiver is isolated from the receiving line PA21 Should you need to implement an RS485 channel in place of the RS232 follow the procedure below 1 make sure your software will permanently set PA23 to a high level this will permanently disa
41. at of your country and insert it in the power supply Connect the power supply DC connector to the board and plug the power supply to an AC power plug The board LCD should light up and display a welcome page Then click or touch icons displayed on the screen and enjoy the demo 3 2 Sample Code and Technical Support After boot up you can run some sample code or your own application on the development kit You can download sample code and get technical support from Atmel website http www atmel com dyn products tools asp category_id 163 amp family_id 605 amp subfamily_id 2404 Figure 3 1 Atmel Website for AT91SAM Products Find It Documents Tools Products By Device By Application List View Parametric Table Microcontrollers Atmel AVR 8 and 32 bit Atmel ARM based Solutions SAM3S SAM3U SAM3N 5 45 5 75 5 SAM7X XC SAM4S EK Development Board User Guide Home gt Microcontrollers gt Atmel ARM based Solutions gt Atmel 5 45 Atmel SAM4S Overview Parameters Documents Tools Scalable Performance and Memory Density Power Efficiency Based on the powerful Cortex M4 processor the Atmel SAM4S series extends the Atmel Cortex M portfolio to offer Increased performance and power efficiency Higher memory densities up to 1MB of Flash and 128KB of SRAM And a rich peripheral set for connectivity system control and analog interfacing Devices are pin to pin an
42. ble the RS232 receiver 2 solder a shunt resistor in place of R25 a solder drop will do SAMAS EK Development Board User Guide ANS 4 5 11139A ATARM 29 Nov 1 1 Evaluation Kit Hardware 4 3 8 RS232 SAMAS EK connects the USART1 bus including TXD RXD RTS CTS handshake signal controls and EN command to the DB9 male connector J5 through the RS232 Transceiver MN5 Figure 4 6 USART USART 21 485 MNS 3V3 ADM3312EARU PA21 2 T 3 L9 el c31 el C32 e C33 41 PA21 232 T 100nF T 100 100nF c1 20 2 C2 DGND elec 1 c36 100nF 100nF 23 C2 24 aa 832 gt T 19 elec sb 100nF PA23 R31 OR Slax TXD1 PA22 33 oR 7 18 RXD1 PA21_232 R34 PUR 10 cS RTS1 EN MH TN 51 25 R36 AA OR 14 R37 V VV 4TK g R20UT 16 R38 OR 43V3 NN 12 T3OUT 3 NN R30UT R3IN V DGND DGND 4 3 9 RS485 As noticed above the USART1 is shared with the RS485 port connected to the transceiver MN4 con nected to the 3 point connector J4 The design includes selectable jumpers for RS485 bus termination resistors selection JP10 JP11 JP12 Figure 4 7 RS485 3V3 3V3 RS
43. bus termination for LCD controller PA13 MOSI PA29 1 AUDIO OUT PC13 EN LCD PC29 TLEFT SNSK 14 5 PA30 14 AUDIO OUTL 14 NAND NCSO PC30 TRIGHT_SNS PA15 ZB SLPTR PA31 MCI PC15 LCD PC31 TRIGHT SNSK AIMEL ROUSSET INITEDIT 08 Mar 11 XXX MODIF DES DATE VER DATE SAM4S EK SCALE 1 1 REV SHEET XP 2 Board Configuration Tris agreement is our propery Reproduction and win ur writen authorizaton shal expose ofender ta legal posses 1
44. d software compatible with current SAM3 Cortex M3 based MCUs offering a smooth upwards migration path for performance and memory size 3 1 11139 29 11 AMEL Section 4 Evaluation Kit Hardware 4 1 Board Overview This section introduces the Atmel SAM4S Evaluation Kit design It introduces system level concepts such as power distribution memory and interface assignments The 5 45 board is based on the integration of an ARM Cortex M3 processor with on board NAND Flash and a set of popular peripherals It is designed to provide a high performance processor evaluation solution with high flexibility for various kinds of applications Figure 4 1 SAM4S EK Block Diagram 00000000 mm 00000000 99000000 _ 90000000 l 00000000 1 89000000 SAMAS EK Development Board User Guide 4 1 11139A ATARM 29 Nov 11 Evaluation Kit Hardware 4 2 Features List Here is the list of the main board components and interfaces SAM4S16 chip LQFP100 package with optional socket footprint 12 MHz crystal 32 768 KHz crystal Optional SMB connector for external system clock input NAND Flash 2 8 inch TFT color LCD display with touch panel and backlight UART port with level shifter circuit USART port with level shifter circuit multiplexed with RS485 port with level shifter circuit Microphone input and mono stereo headphone jack output SD MMC interface Reset button NRST User
45. d with ZigBEE signal IRQO Busy PA17 is shared with ZigBEE signal IRQ1 Therefore if using a ZigBEE interface in concurrence with the TouchScreen controller take care not to have both drivers enabled at the same time on either PA16 or PA17 For that purpose 0 Ohm resistors have been implemented on these PIO lines in order to disconnect either end driver from the other m On the touch panel controller side R67 and R69 On ZigBEE side 117 and R120 for further information refer to the Schematics section Touch ADC auxiliary inputs IN3 IN4 of the ADS7843 are connected to test point TP8 TP9 for optional function extension Figure 4 10 Touch Panel Control ne2 MN7 ADS7843E 100K X_LEFT 4 Mg 12 12 Y DOWN UT as Js nes TPs TP9 13 R67 OR PAI7 SMD SMD BUSY 969 pyy 1 e PENIRQ 33 3 7 VREF t 70 AAA SR IN3 VCC1 m vee 1 5 TOuH 100mA e e csi R72 7 S Wi ena R74 4 7uF AGND_TP AGND_TP DGND JTAG ICE A standard 20 pin JTAG ICE connector is implemented on the SAM4S EK for the connection of a com patible ARM JTAG emulator interface such as the SAM ICE from Segger Notes 1 The NRST signal is connected to BP1 system button and is also used to reset the LCD module The 0 o
46. elopment Board User Guide 6 1 11139A ATARM 29 Nov 11 AMEL Section 7 Revision History 7 1 Revision History Table 7 1 Change Request Comments Ref 11139A Initial version SAM4S EK Development Board User Guide 7 1 11139A ATARM 29 Nov 11 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 487 2600 International Atmel Asia Limited Unit 01 5 amp 16 19F BEA Tower Millennium City 5 418 Kwun Tong Road Kwun Tong Kowloon HONG KONG Tel 852 2245 6100 Fax 852 2722 1369 Product Contact Web Site www atmel com www atmel com AT91SAM Atmel Munich GmbH Business Campus Parkring 4 D 85748 Garching b Munich GERMANY Tel 49 89 31970 0 Fax 49 89 3194621 Technical Support AT91SAM Support Atmel technical support Atmel Japan 9F Tonetsu Shinkawa Bldg 1 24 8 Shinkawa Chuo ku Tokyo 104 0033 JAPAN Tel 81 3 3523 3551 Fax 81 3 3523 7581 Sales Contacts www atmel com contacts Literature Requests www atmel com literature Disclaimer The information in this document is provided in connection with Atmel products No license express or implied by estoppel or otherwise to any intellectual property right is granted by this document or in connection with the sale of Atmel products EXCEPT AS SET FORTH IN ATMEL S TERMS AND CONDI TIONS OF SALE LOCATED ON ATMEL S WEB SITE ATMEL ASSUMES NO LIABILITY WHATSOEVER
47. ematics Section 8 describes the troubleshooting 1 3 References and Applicable Documents Table 1 1 References and Applicable Documents SAMAS Datasheet http www atmel com dyn resources prod_documents 1 1100 pdf SAMAS EK Development Board User Guide 41 1 1 11139 29 11 AMEL Section 2 Kit Contents 2 1 Deliverables The Atmel SAM4S EK toolkit contains the following items Board aSAM4S EK board auniversal input AC DC power supply with US Europe and UK plug adapters Cables one USB cable one serial RS232 cable A Welcome Letter Figure 2 1 Unpacked SAM4S EK Unpack and inspect the kit carefully Contact your local Atmel distributor should you have issues con cerning the contents of the kit 5 45 Development Board User Guide 2 1 11139A ATARM 29 Nov 11 Kit Contents 2 2 Electrostatic Warning The SAM4S EK board is shipped in a protective anti static package The board must not be subjected to high electrostatic potentials A grounding strap or similar protective device should be worn when han dling the board Avoid touching the components or any other metallic element of the board 2 2 5 45 Development Board User Guide 11139 29 11 AMEL 3 1 Power up the Board Section 3 Power Up Unpack the board taking care to avoid electrostatic discharge Unpack the power supply select the right power plug adapter corresponding to th
48. ezoelectric Ceramic Resonator 12 Mhz Murata ref CSTCE12M0G15L99 RO0 one 32 768 Hz crystal and an external clock input con nector optional not populated by default Figure 4 3 External Clock Source NOT POPULATED 1 Ri AA PNP SF 2 3 INN XIN32 B R2 dl DNP 3 lt gt 49 98 1 ANN MN1 1 _132 768 DGND Ci RA AA OR 4 XIN b D ND ANN 00732 DGND 3 gt v2 12MHz Re 97 boo SAM4S Ca e mia 20 XOUT 2 7 roe BY AA PNP Pes DNP 96 peg xour 80 PWMH3 Rig WV DNP PA8_CTS0_AD12BTRG SAM4S EK Development Board User Guide 41 4 3 a 11139A ATARM 29 Nov 11 Evaluation Kit Hardware 4 3 4 4 3 5 4 4 The SAMAS chip internally generates the following clocks m SLCK the Slow Clock which is the only permanent clock of the system MAINCK the output of the Main Clock Oscillator selection either a Crystal Oscillator or a 4 8 12 MHz Fast RC Oscillator m PLLACK the output of the Divider and 60 to 130 MHz programmable PLL PLLA PLLBCK the output of the Divider and 60 to 130 MHz programmable PLL PLLB Reset Circuitry On board NRST button BP1 provides an external reset control of the SAM4S The NRST pin is bidirectional It is handled by the on chi
49. he receiver PIO lines of the SAM4S EK These are the PIO lines connected to an external driver on the board The 0 Ohm resistors allow disconnecting each of these for custom usage through PIO expansion connectors for example This feature gives the user an added level of versatility for prototyping a system of his own See the table below 4 20 AS SAMAS EK Development Board User Guide 11139 29 11 Table 4 8 Disconnecting Possibility Evaluation Kit Hardware Designation Default Assignment R19 OR PC18 RDY BSY on NAND Flash R20 OR PA29 R22 DNP Optional write protection on NAND Flash R25 OR PA21 R26 OR PA25 R27 OR PA24 R28 OR PA22 R31 OR PA23 R33 OR PA22 R34 OR PA21 R35 OR PA24 R36 OR PA25 R44 OR NRST R47 OR 9 R48 OR 2 5 R59 OR LCD backlight LED anode R66 OR PA11 R67 OR PA5 R68 OR PC13 R69 OR PA4 R70 OR Vref TSC R118 OR PA3 ZB_RSTN R119 OR 5 IRQ1_ZBEE R120 OR PA4 IRQO ZBEE R121 OR PA6 SLP_TR Table 4 9 Default Not Populated Parts Reference J1 R1 Function External clock resource input 1 R8 R7 Backup 12 MHz crystal R6 R8 Isolation on 12 MHZ clock source and GPIO expansion R9 R10 Isolation on 32 KHz clock source and GPIO expansion R22 Optional write protection NAND Flash R23 Optional pull up for open drain output or equivalent device
50. hich are multiplexed with the I O lines of the embedded peripherals Each PIO Controller controls up to 32 lines 16 for PIOB Expansion ports J12 J13 and J14 provide PIO lines access for customer defined usage Figure 4 24 PIO Expansion PB O 14 PA 0 31 0 31 3v3 3V3 3v3 3V3 DGND DGND DGND DGND Note All PIO lines are available on these expansion connectors except those that are used for the QTouch elements 5 45 Development Board User Guide 4 15 11139A ATARM 29 Nov 11 Evaluation Kit Hardware 4 4 Configuration This section describes the PIO usage the jumpers the test points and the solder drops of a SAM4S EK board 4 4 1 PIO Usage Table 4 1 PIO Port A Pin Assignments and Signal Descriptions yo Peripheral Peripheral Peripheral System No Line A B Extra Function Function Comment 1 PAO PWMHO TIOAO A17 WKUPO QTouch slider left SNS 2 PA1 PWMH1 TIOBO A18 WKUP1 QTouch slider left SNSK 3 PA2 PWMH2 SCKO DATRG WKUP2 QTouch slider middle SNS 4 PA3 TWDO NPCS3 QTouch slider middle SNSK 5 PA4 TWCKO TCLKO WKUP3 QTouch slider right SNS 6 RXDO NPCS3 WK
51. hm resistor R44 may be removed in order to isolate the JTAG port from this system reset signal 2 The TDO pin is in input mode with the pull up resistor disabled when the Cortex M3 is not in debug mode To avoid current consumption on VDDIO and or VDDCORE due to floating input the internal pull up resistor corresponding to this PIO line must be enabled SAM4S EK Development Board User Guide 11139 29 11 Evaluation Kit Hardware Figure 4 11 JTAG Interface 3V3 R39 R40 R41 R42 R43 100K 100K 100K 100K 100K J6 VTref nTRST GND1 1 3 lt 5 TDI GND2 PB6 g TMS GND3 PB lt q7 TCK GND4 RTCK GND5 PBs oF 15 GND6 NRST lt gt 17 SRST GND7 DBGRQ GND DBGACK GND9 4 3 15 Audio Interface The SAM4S EK board supports both audio recording and playback The audio volume can be adjusted using the potentiometer RV1 and the microphone amplifier gain can be adjusted via jumpers fixed gain of 24 or 26 dB 4 3 16 Microphone Input The embedded microphone is connected to an audio pre amplifier using the TS922 operational amplifier MN11 The gain is set by using JP14 and JP15 jumpers both must be set or removed at the same time By modifying the jumper positions you can select each of the following gain values m 20 dB default setting both JP1
52. inear finger displacement on a sen sitive area A typical implementation is volume control Figure 4 19 QT_Slider S1 QTouch Slider SR 1 R50 1K WV cas TT 22nF 852 ANTE es F 22nF 4 sa PA5 R54 1K WV F 22nF 22nF use X7R 4 3 20 User Buttons There are two mechanical user buttons on the SAM4S EK which are connected to PIO lines and defined to be left and right buttons by default In addition a mechanical button controls the system reset signal NRST Figure 4 20 System Buttons w 3 4 2 376 4 4 gt NAST 1 5 JP25 29 644 Ly 1 BET JP26 paa x DGND SAM4S EK Development Board User Guide ANS 4 13 11139A ATARM 29 Nov 1 1 Evaluation Kit Hardware 4 3 21 LEDs There are three LEDs on the SAM4S EK board m A blue LED D2 and a green LED 03 which are user defined and controlled by the GPIO Ared LED D4 which is a power LED indicating that the 3 3V power rail is active It is also controlled by the GPIO and can be treated as a user LED as well The only difference with the two others is that it is controlled through a MOS transistor By default the PIO line is disabled a pull up resistor controls the MOS to light the LED when the power is ON Figure 4 21 LEDs 111 220R PA19 A D2 Blue led 4
53. k 2 1mm ZENO56V130A24LS BNX002 01 A C66 98 22uF 220uF ELE 16V 2 cui SG 1001F 22uF DGND MN12 MIC29152WU Micrel s 1 5A LDO TO263 5 2 VIN VOUT 4 1 50 ADJ S 169K 1 GND1 GND2 C75 76 T 100uF TAN 6 3V 100nF m 102K 1 a DGND The SAMAS product series has different types of power supply pins m VDDIN pin Power for the internal voltage regulator ADC DAC and analog comparator power supplies The voltage ranges from 1 8V to 3 6V ANS 5 45 Development Board User Guide 11139 29 11 Evaluation Kit Hardware m VDDIO pins Power for the Peripherals lines The voltage ranges from 1 62V to 3 6V VDDOUT pin Output of the internal voltage regulator VDDCORE pins Power for the core including the processor embedded memories and peripherals The voltage ranges from 1 62V to 1 95V m VDDPLL pin Power for the PLL A PLL B and 12 MHz oscillator The voltage ranges from 1 62V to 1 95V Note VDDPLL should be decoupled and filtered from VDDCORE 4 3 6 UART The Universal Asynchronous Receiver Transmitter features a two pin UART that can be used for com munication and trace purposes It offers an ideal channel for in situ programming solutions This UART is associated with two PDC ch
54. nnector J12 Signal Descriptions 5 45 Development Board User Guide Mnemonic Pin Mnemonic 5V or 3v3 2 5V 3v3 GND 4 GND PCO 6 PC16 PC1 8 PC17 PC2 10 PC18 PC3 12 PC19 PC4 14 PC20 PC5 16 PC21 PC6 18 NC PC7 20 NC PC8 22 NC PC9 24 NC PC10 26 NC PC11 28 NC PC12 30 NC PC13 32 NC PC14 34 NC PC15 36 NC GND 38 GND 3V3 40 3V3 Evaluation Kit Hardware 4 29 11139A ATARM 29 Nov 11 Evaluation Kit Hardware 4 5 13 PIO Expansion Port A Connector J13 Figure 4 36 PIO Expansion Connector J13 39 37 35 3331 29 2725 23 2119 171513 119 75 3 1 0 40 38 36 34 32 30 28 26 24 22 20 181614 1210 8 6 4 2 Table 4 22 Connector J13 Signal Descriptions 4 30 11139A ATARM 29 Nov 11 Mnemonic Pin Mnemonic 5V 3v3 2 5V or 3v3 GND 4 GND NC 6 PA16 NC 8 PA17 NC 10 PA18 NC 12 PA19 NC 14 PA20 NC 16 PA21 18 PA22 20 PA23 22 PA24 24 PA25 26 PA26 28 PA27 30 PA28 32 PA29 34 PA30 36 PA31 38 GND 40 3V3 5 45 Development Board User Guide AMEL Section 5 Schematics 5 1 Schematics This section contains the following schematics Block diagram General information Microcontroller NAND Flash serial interface TFT LCD amp Touch Audio
55. p reset controller It can be driven low to provide a reset signal out to the external components Conversely it can be asserted low from the outside to reset the microcontroller Core and the peripherals The NRST pin integrates a permanent pull up resistor of about 100 to VDDIO On the SAM4S EK board the NRST signal is connected to the LCD module and JTAG port Note At power on the signal is asserted with a default duration of 2 clock cycles That duration may not be sufficient to correctly reset any other system or board devices connected to that signal First in your custom application you need to check for these devices datasheets about reset duration requirements Then you need to set an appropriate configuration in the NRST Manager This is done through the ERSTL field in the RSTC_MR register The NRST duration is thereby configurable between 60 us and 2 s whether it is subse quently activated by a software reset or a user reset Refer to the SAM4S datasheet for in depth information Power Supply and Management The SAM4S EK board is supplied with an external 5V DC block through input J9 It is protected by a PolyZen diode 9 and an combinatory filter MN10 The PolyZen is used in the event of an incorrect power supply connection The adjustable LDO regulator MN12 is used for the 3 3V rail main supply It powers all the 3 3V compo nents on the board Figure 4 4 Power Block J9 Power Jac
56. ply and 4 4 4 3 6 tea 4 5 SECUNDI UO 4 5 43 8 5292 ned net dea a ed 4 6 439 Mm 4 6 4 3 10 Display Interface nit ee i e n e 4 6 43 11 CCD Module M 4 6 4 3 12 4 7 4 3 13 Touch Screen INE HAC visa 4 8 43 14 ainsi nui nei ea u Be ede peel is 4 8 4 315 Audio 1 4 9 4 3 16 Microphone Input cec RR 4 9 4317 4 11 4 3 18 Analog Interface 4 11 4 3 19 QTouch Elemieris eerte iei err tint x De see cr qe bac 4 12 43 20 User 4 13 SAMAS EK Development Board User Guide ANS 1 1 11139A ATARM 29 Nov 1 1 C SCARE ZU c R 4 14 4 3 22 SD MMGQG rite di Fest futura al 4 14 4323 D 4 14 4 3 24 4 4 15 T
57. supports mono stereo audio playback driven by 0223 audio ampli fier connected to two DAC channels of the microcontroller The TPA0223 is a 2W mono Bridge Tied Load BTL amplifier designed to drive speakers with as low as 4 Ohm impedance The amplifier can be reconfigured on the fly to drive two stereo Single Ended SE into head phones signals Figure 4 13 Headphone Output J10 1 2 AUDIO OUT 5 MN13 FB3 TPA0223DGQ BNO3K314S300R VDD TM Es 3 JP29 2 EN 85 Romo L 220uF TAN 6 3V 5 j VCC33 i 80 C82 R95 1K 3 3E F 10 Tp tour T 100 7 VW pees 57 1K 1 5 m DGND AGND E LO MO gt R98 pa 33K S iy AGND JP17873 Head amp go 47K 9 NN TP12 C85 O47uF R100 4 4 33 1 R101 100K R102 100K TestPadsa 4oTH MONO IN STIMN V 4 2 R103 4 100K JP19F73 Heade704 47K SHUTDOWN NA 4 VVV UE C86 0 47uF 4 JP20 C87 si Header2 F AUDIO OUTL C88 0 47uF R105 AA 33K S od 1uF 2 GND k gt F 4 v a AGND AGND AGND AGND MN14 5V MIC5219 3 3YMM VCC33 1 1 5 C92 F 47uF 16 100u
58. to disconnect and free PB3 for custom usage JP26 BP3 CLOSE Open to disconnect and free PC12 for custom usage JP27 ZIGBEE CLOSE Power supply connection disconnection for the ZigBEE module May also be used as a current measurement point SAM4S EK Development Board User Guide 4 19 11139 29 11 Evaluation Kit Hardware Table 4 5 Audio Input Configuration MONO STEREO INPUT PIN test point TP12 OFF ON Left in only ON OFF Right in only ON ON Sum of Left in and Right in 4 4 3 Test Points Some test points have been placed on the SAM4S EK board for the verification of important signals Table 4 6 Test Points Designation Description TP1 Ring Hook GND TP2 Ring Hook GND TP3 Ring Hook GND TP4 Ring Hook GND 5 UART TXD TP6 Pad UART RXD TP7 Pad LCD Backlight driver anode TP8 Pad Aux ADC input for Touch Screen controller TP9 Pad Aux ADC input for Touch Screen controller TP10 Ring Hook 5V TP11 Ring Hook 3V3 TP12 Pad Optional Audio PA input 4 4 4 Solder Drops There are two solder drops designed on the SAMAS EK for isolation Table 4 7 Solder Drops Isolation of DAC output from shared channel PB14 Connects PB14 to the AUDIO_OUTL channel 4 4 5 Assigned PIO Lines Disconnection Possibility As pointed out in some previous interface description 0 Ohm resistors have been inserted on the path of t
59. tras oR T2IN T20UT Fg 5 SN R20UT R2IN K 5 7 DGND x TP5 TP6 FGND RXD1 CTS1 RTS1 TXD1 3V3 volaj SD CARD R17 R18 RA1 10K 10K 68Kx4 J3 PA26 1 deem 27 1 2 28 3 DATS 4 CMD 11 vec Shi PA29 R20 R 5 12 MAN CLK Sn 4 vss Sh3 PA30 7 1 8 10 DGND 1 5 GND PAG 1 25 C26 10uF T 10017 DGND 3 3 3V3 RS 485 R23 2 R24 10K MN4 nm ADM3485ARZ PA21 485 2 R 1 8 1 I we RO e _C30 param PA25 R26 AA 2 5 100 E 24 R27 oR 3 x T WW 1 DE DOND 219 22 R28 AA li 7 B 1 1 9 Li gt R29 JP11 JP12 28 HT oJ Headerz J Header2 leader2 nm FGND lt R30 nm DGND m ICE INTERFACE 2 9 SRo Grae 5 100K lt 100K 100K lt 100K lt 100K j VTref 57 GND1 lt __ 1 7 TDI GND2 PB6 lt g TMS GND3 PB7 lt 11 TCK GND4 st RTCK GND5 5 gt Tad oR 13 TDO GND6 NRST lt gt NN 17 SRST GND7 4g DBGRQ GND8 DBGACK GND9 SAM4S EK NAND Flash amp Serial IF A

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