Xilinx UG886 AMS101 Evaluation Card User Guide
Contents
1. YADI KEYED_RECEPT_2X10_SMT SSW 110 22 G D VS N 2g DACOUTB To XADC VP 23 J2 BNCINA jjj BNCINA R A sto XADC VN as toz XADC_VN S265 HDR 1X3 R15 Ts i C12 4 49 9 1000PF HDR 1X2 1 10W E 50V 2 m XADO VREF Neg 1 X7R Neg XADC_AGND XADC GPIO 1 XADC GPIO 0 2E u2 XAD AGND 2 g XADC GPIO 3 XADC GPIO 2 g2 1 J5 1 e 2 DACOUTA 10 VW 83 ol XADC AGND ju E T2 J6 BNCINB ypo BNCINB R afo 5 moss e s HDR 1X3 R19 il C16 XADC XGND GND HDR 1x2 49 9 zy 50V 1 10W X7R 1 V XADC AGND VY XADC_AGND UG886_aA_02_062512 Figure A 2 AMS101 Evaluation Card Schematic 2 of 2 Dynamic Performance Metric Calculation Methodology SNR is calculated by removing the DC the fundamental and the first five harmonics components from the FFT data All the remaining components are root sum squared together This number is divided by the fundamental component and converted into decibels dB THD is a measure of the ratio of the root sum square of the first seven harmonics to the fundamental also expressed in dB SINAD is similar to the SNR calculation except it does not throw out the first five harmonics SFDR is a measure of the difference between the magnitude of the largest spur and the magnitude of the fundamental in dB ENOB is calculated directly from the SINAD number AMS101 Evaluation Card User Guide www xilinx com 49 UG886 v1 3 November 62. 4465101 tvakontor GUI suga 7 ot med XILINX AMS101 Evaluator vias M Qui Time Domain Frequency Domain Linearity XADC Registers Sensor Data Power Monitor Debug Connection Manager Power Connect D Connected gt AC701 Veri 1 00 Voltage Vdc Current Ade Power W VCCINT MGTAVCC EI Egg Xe X XR YID eee 11 qu Em MMC SAX mmn dii 300 ne 303 x ws 3 xe i des we 380 GG VCCBRAM 15V SUPPLY VCCO ADJ 1 8V SUPPLY MGTAVTT AMO VER ERICH RT RUDI l dii xe i19 30 mo sm i dii xe n6 des e db 35 xe 25 3 3V SUPPLY MGTAVCC 7 MGTAVIT UG886 c2 18 020113 Figure 2 18 AC701 Power Monitor Design Measuring MGTAVCC and MGTAVTT 28 www xilinx com AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013 XILINX Chapter 3 AMS101 Evaluation Hardware The AMS evaluation card enables you to evaluate the performance of the XADC in many of the operating modes described in 7 Series FPGAs and Zunq 7000 All Programmable SoC XADC Dual 12 Bit 1 MSPS Analog to Digital Converter User Guide UG480 Ref 6 This evaluation can be done using either an external signal source or the DAC that is present on the card Figure 3 1 shows the block diagram of the card VO Level Translator Control VO Level Translator Reference Voltage AD8033 VP VAUXOP VAUX8P VN VAUXON VAUX8N o o G D T o Q lt x E o
3. UG886 c2 16 011513 Figure 2 16 AC701 Power Monitor Design Measuring Vccinr VccAUx VccBRAM and the 1 5V Supply 26 www xilinx com AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013 XILINX Power Monitoring with XADC on AC701 Four voltage rails can be selected at a time To select more voltage rails de select one or more of the existing voltage rails and select the desired new rails Figure 2 17 and Figure 2 18 show voltage current and power measurements of the remaining five rails Veco AD the 1 8V supply the 3 3V supply MGTAVCC and MGTAVTT E AMS101 Evaluator GUIs q a EE ATTI r TE i 7 F Y XILINX AMS101 Evaluator vios Ni Qui Time Domain Frequency Domain Linearity XADC Registers Sensor Data Power Monitor Debug Connection Manager Power E Connect Connected S jes Voltage Vdc Current Adc Power W 3 uppl Y os AC701 COMS 8 Ver 100 VCCINT lt L f o VCCAUX l VCCBRAM 303 129 340 350 380 400 1 5V SUPPLY 5 n VCCO ADJ g OEE A OP P 3 a 1 8V SUPPLY gt T 3 30 supply MGTAVCC 3 MGTAVTT 2 2 5 e Y gt a E l zw UG886_c2_17_011513 Figure 2 17 AC701 Power Monitor Design Measuring Vcco Ap the 1 8V Supply the 3 3V Supply and MGTAVCC AMS101 Evaluation Card User Guide www xilinx com 27 UG886 v1 3 November 6 2013 Chapter 2 AMS101 Evaluation Card Quick Start XILINX
4. 49 Appendix B Required Jumper Settings for Base Boards Jumper Settings for the KC705 Board rreraren 51 Jumper Settings for the VC707 Board 51 Jumper Settings for the ZC702 Board 51 Jumper Settings for the ZC706 Board nurnerr 52 Jumper Settings for the AC701 Board 52 Appendix C Additional Resources Xilinx Resources nn 53 Solution Centers cc RR le 53 References hole bt ee Sadi SUL IIa bM PULL EE a 53 AMS101 Evaluation Card User Guide www xilinx com UG886 v1 3 November 6 2013 Appendix D Regulatory and Compliance Information XILINX Declaration of Conformity cr kisba kas kok E EE E Er Vida a 55 Directives e n e lis a de de Babs Sd xe re 55 Standards iii 55 Markings pri pe eT e ER a lied 56 www xilinx com AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013 XILINX Chapter 1 AMS101 Evaluation Card Overview Overview AMS101 Evaluation Card The Xilinx 7 series FPGAs and Zynq 7000 All Programmable System on a Chip AP SoC each feature two 1 Mega sample per second MSPS 12 bit Xilinx analog to digital converters XADCs built into the device FPGA or SoC The Analog Mixed Signal AMS technology combines the XADC analog measurement with the device s logic for simple system monitoring to more signal processing intensive tasks like linearization calibration oversampling and filtering The AMS101 evalua
5. Ensure switch is in OFF position UG886 c2 02 062712 Figure 2 2 Power Switch on the FPGA Base Board Three connections are required for the FPGA base board power the USB UART connection to the PC and the JTAG Standard A plug to Micro B plug USB programming cable Figure 2 3 shows how to connect these on the KC705 base board Caution Do not turn on the power switch until step 6 page 16 AMS101 Evaluation Card User Guide www xilinx com 13 UG886 v1 3 November 6 2013 Chapter 2 AMS101 Evaluation Card Quick Start g XILINX AMS101 Evaluation Card Board Power USB Cable Switch SW12 Standard A Plug to Mini B Plug Host Computer Power Supply 100 VAC 240 VAC Input 12 VDC 5 0A Output USB Cable Standard A Plug to Micro B pPug UG886 c2 03 091012 Figure 2 3 FPGA Base Board Connectivity 4 Configure the FPGA base board jumper settings as listed in Appendix B Required Jumper Settings for Base Boards 5 Connect the AMS101 evaluation card to the XADC header on the base board The AMS101 evaluation card connects to the FPGA base board by plugging the card into the XADC header on the base board The AMS101 evaluation card connector and XADC header socket are keyed to align properly Pin 1 on the XADC header needs to connect to pin 1 of the 20 pin connector on the AMS101 evaluation card Figure 2 4 shows this connection AMS101 Evaluation Card XADC Header Installed on XADC Header KINTEX ii ce so 08 23 0
6. Table 4 2 AMS101 Evaluation Card Typical Results with Multiple Base Boards Effective Number of Bits ENOB Signal to Noise Ratio SNR dB Base Board Decimation 1 Decimation 16 Decimation 1 Decimation 16 ZC706 10 6 12 3 65 8 76 6 AC701 10 4 11 9 64 8 75 1 VC707 10 4 11 5 65 3 74 5 ZedBoard 10 4 11 5 65 1 74 4 KC705 10 3 11 3 64 6 73 3 ZC702 10 4 11 2 65 1 71 7 Decimate 1 Half Band Decimate FIR Filter by2 XADC Data Loop Back to Get a Further Decimate by 2 UG886 c4 09 062512 Figure 4 9 Decimation Block Diagram AMS101 Evaluation Card User Guide www xilinx com 45 UG886 v1 3 November 6 2013 Chapter 4 AMS Evaluator Tool 46 www xilinx com XILINX AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013 XILINX Appendix A largeted Design Platforms Schematics and Dynamic Performance Metric Calculation Methodology Supported Targeted Design Platforms Supported targeted design platforms include the AC701 KC705 VC707 and ZC702 targeted design platforms Supported demonstration design platforms include the ZC706 and ZedBoard See the AMS101 Evaluation Card website for the ZC706 and ZedBoard AMS demo designs Schematics Schematics for the AMS101 evaluation card are shown in Figure A 1 and Figure A 2 AMS101 Evaluation Card User Guide www xilinx com 47 UG886 v1 3 November 6 2013 Appendix A Targeted Design Platforms Schemat
7. UG886 c3 04 081612 Figure 3 4 Use Case 1 Jumper Configurations for Onboard DAC 32 www xilinx com AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013 XILINX Board Setup Use Case 1 enables all tests and all modes To operate the AMS101 evaluation card in any one of those modes see XADC Configuration page 38 If the optimum dvnamic performance is required use an external signal source Select an appropriate Use Case 2 or 3 for the desired operating conditions based on Table 3 1 The AMS Evaluator tool GUI allows you a good amount of control and flexibility over the two DAC outputs in the AD5065 See Figure 4 5 page 41 for more details Check the Generate Sinewave Using DAC box to output a sine wave on DAC A and DC bias voltage on DAC B Uncheck the Generate Sinewave Using DAC box and both DACs output the DC voltages as written in the Vp offset and Vy offset boxes DAC A Vp offset always supplies the analog voltage to the positive XADC inputs Vp Vauxpo and Vayxpg and DAC B Vy offset always supplies the analog voltage to the negative XADC inputs Vy Vauxno and Vauxns For simplicity on the AMS101 evaluation card all three positive XADC inputs Vp Vauxro and Vayxpg have been shorted together and all three negative XADC inputs Vw Vauxno and Vauxng have been shorted together Use Case 2 Single Ended External Analog Source o G o I o a L x E a Use Case 2 allows an external an
8. gas XILINX AMS101 Evaluator ne W ou Tose Demi Frequency Domain Limmawiiv RACC Regie emer Dote came tam Manager Coftect Data SERRA nidi fe e connectes Kumtex T e Ver na MU S Cann Config we mide Me UG886 c2 12 092512 Figure 2 12 Run Time Domain Data Capture AMS101 Evaluation Card User Guide www xilinx com 21 UG886 v1 3 November 6 2013 Chapter 2 AMS101 Evaluation Card Quick Start XILINX 22 Tee omai Freguancf Demis Limasrinz XADC Baginera Semar Bota Debug Perform Fast Fourier Transform Analysis To analyze the performance of the XADC in the frequency domain select the Frequency Domain tab see Figure 2 13 When selected a Fast Fourier Transform FFT is performed on the XADC data just viewed in the time domain The signal to noise ratio total harmonic distortion effective number of bits ENOB and other AC parameters are calculated and displayed in the data panel below the FFT plot as shown in Figure 2 13 A new data capture from the XADC can be collected by pressing the Collect Data button Select Frequency Pressing the Collect Data button collects 4 096 XADC data points Domain tab here and performs an FFT on it 7 AMS101 Evaluator w i o Cotect Data wre jp comet D connected Winter 7 Ver am chant oni FFT AC Data Analyisis UG886 c2 13 092512 Figure 2 13 Frequency Domain Analysis and Data Capture www xilinx com AMS101 Evaluation Card User Guide UG886 v1
9. 2013 Appendix A Targeted Design Platforms Schematics and Dynamic Performance Metric Calculation LINX 50 www xilinx com AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013 XILINX Appendix B Required Jumper Settings for Base Boards Jumper Settings for the KC705 Board Note The triangle indicates pin 1 for jumper settings on all Xilinx base boards To enable AMS evaluation ensure the KC705 board has the following jumper settings e J43 In place e J68 In place e J48 In place between pins 2 and 3 J69 In place between pins 1 and 2 e J47 In place between pins 1 and 2 e J42 Not in place See KC705 Evaluation Board for the Kintex 7 FPGA User Guide UG810 Ref 7 Jumper Settings for the VC707 Board To enable AMS evaluation ensure the VC707 board has the following jumper settings e J10 In place e J53 In place e J43 In place between pins 2 and 3 e J54 In place between pins 1 and 2 e J42 In place between pins 1 and 2 e J9 Not in place See VC707 Evaluation Board for the Virtex 7 FPGA User Guide UG885 Ref 8 Jumper Settings for the ZC702 Board To enable AMS evaluation ensure the ZC702 board has the following jumper settings e J8 Not in place e J9 In place e J65 In place e J37 In place between pins 1 and 2 e J38 In place between pins 2 and 3 AMS101 Evaluation Card User Guide www xilinx com 51 UG886 v1 3 November 6 2013 Appendix B Required Jumper Settings
10. 3 November 6 2013 XILINX Run Key Performance Tests Perform a Linearity Test To analyze the linearity of the XADC select the Linearity tab and click the Collect Data button After a short wait both the integral and differential non linearity data is displayed on two separate plots along with the minimum and maximum values at the bottom of the screen as shown in Figure 2 14 Perform Linearity Test and Initiate Analog Ramp Output at DAC E enm os XILINX AMS101 Evaluator ve m ca Tie Domain Pompeia Domea Limantiy LADC Regime Tene Data Debug Masa Cotect Data PU meque pom dota gi en lione y Ver UG886 c2 14 092512 Figure 2 14 Linearitv Error Data Capture and Analysis AMS101 Evaluation Card User Guide www xilinx com 23 UG886 v1 3 November 6 2013 Chapter 2 AMS101 Evaluation Card Quick Start XILINX Analvze Internal Voltage and Temperature Sensors The XADC also has several internal sensors that it digitizes These include a temperature sensor and FPGA voltage supplv sensors Select the Sensor Data tab to view the data corresponding to the four sensors as shown in Figure 2 15 foco EEE E Ge XILINX AMS101 Evaluator va M oa Tene Domala frequency Domalo Limmasitu HACC Regin Sem Data Debug comectun Manager Temp C Connost D connectes VccAUX VeciNT Power Control VccBRAM m UG886 c2 15 092512 Figure 2 15 Sensor Data Capture Power Monitoring with XADC
11. 7000 ZC706 AP SoC was added in Jumper Settings for the ZC706 Board page 52 Updated Appendix C Additional Resources links The link to the Declaration of Conformity page 55 was updated UG886 v1 3 November 6 2013 www xilinx com AMS101 Evaluation Card User Guide AMS101 Evaluation Card User Guide www xilinx com UG886 v1 3 November 6 2013 Table of Contents R visiom History sp iw quid ae teed le eo i a B e aS AR Ma 2 Chapter 1 AMS101 Evaluation Card Overview OVELVIEW ia ci isle ke e a 7 Chapter 2 AMS101 Evaluation Card Quick Start Ouick Start a a A a at 12 Run Key Performance Tests anunn anann uurre rrura 21 Analyze Internal Voltage and Temperature Sensors 24 Power Monitoring with XADC on AC701 urner 24 Chapter 3 AMS101 Evaluation Hardware Interfacing to the FPGA Base Board esses 30 Board Setup cuya covered eed aban eV Rie eR ep eic Rd E GEOP Er Va dae edi hada 31 Chapter 4 AMS Evaluator Tool AADC Conhputrdlon esses pegos cespisesaa p iba nadas ere ded ka edo 38 XADC Performance Tests eeee RR e 41 AMS Demonstration ern 44 Appendix A Targeted Design Platforms Schematics and Dynamic Performance Metric Calculation Methodology Supported Targeted Design Platforms nn erana 47 Schematics ia kr e ds 47 Dynamic Performance Metric Calculation Methodology
12. the XADC header Pin 1 on the XADC header on the FPGA base board needs to connect to Pin 1 of the 20 pin header on the AMS101 evaluation card p AGND VAUXON VAUX8P AGND DXN AVpp DGND DIO DIO zoa za L gt 000 gt SZ ox E ENAA ag 32 F Te gt CC l N 2zoaozaamarzaao ziuasDanroooo gt gt ZSSS rL 2 eg fa as 1o gt 5 gt gt 9 UG886 c3 02 071012 Figure 3 2 XADC Header Pinout www xilinx com AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013 XILINX Board Setup Onboard Signal Source The AMS101 card contains the Analog Devices AD5065 part which is a dual 16 bit DAC This DAC can be used for one of three functions e Provide a ramp for linearity testing e Generate a sine wave for a quick dynamic performance test e Provide DC levels for common mode shifts or to provide a DC level for code transition noise tests The DAC can be interfaced with the GUI See Signal Source Configuration page 40 for more details Signal Conditioning Circuitry The signal conditioning function of the AMS101 evaluation card consists of an AD8033 which functions as a gain of 2 amplifier supplying 2 5V to the reference voltage to the DAC Power Supplies The circuitry on the AMS101 evaluation card receives 5V power through the FPGA base board across the XADC header Board Setup Because of the level of flexibility of the XADC there area three operating modes supported by the AMS101 ev
13. the revision history for this document Date Version Revision 07 16 2012 1 0 Initial Xilinx release 10 19 2012 11 Section AMS101 Evaluation Card Overview page 7 explains that reference designs are now supplied for the ZC702 KC705 and VC707 base boards and how to download the designs Cable terminology changed to Standard A plug to Mini B plug USB cable and Standard A plug to Micro B plug USB cable and these two cables are added to the kit Board drawings and photographs in Figure 1 2 and Figure 1 2 were updated Procedures in Hardware and Software Setup page 12 were updated Figure 2 4 Figure 2 5 and Figure 2 9 were updated The AMS102 characterization card was removed In Analyze Internal Voltage and Temperature Sensors page 24 Open is replaced with Select Figure 3 4 and Figure 3 6 were replaced In Appendix B Required Jumper Settings for Base Boards a note was added that the triangle represents pin 1 Jumper J65 on the ZC702 board changed to In place Some references in the book and in Appendix C Additional Resources changed Appendix D Regulatory and Compliance Information now includes a link to the Declaration of Conformity and markings for waste electrical and electronic equipment WEEE restriction of hazardous substances RoHS and CE compliance AMS101 Evaluation Card User Guide www xilinx com UG886 v1 3 November 6 2013 Date 02 14 2013 Version 1 2 Revision Chapter 1 AMS101 Evaluati
14. 2 00 10 UG886_c2_04_101812 Figure 2 4 AMS101 Evaluation Card Installed on the Base Board XADC Header 14 www xilinx com AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013 XILINX Quick Start Ensure that all the jumper settings are correct on the AMS101 evaluation card Figure 2 5 shows an example of jumpers J3 and J5 DACs enabled Table 2 1 explains additional jumpers Note The image in Figure 2 5 is for reference only and might not reflect the current revision of the board s AGND ASSFRIO RO Sjc 9 R R Tacx LAUNSI UG886 c2 05 092612 Figure 2 5 AMS101 Evaluation Card Jumper Configuration Table 2 1 AMS101 Evaluation Card Jumper Configuration Notes Callout 7 dd oe Notes Schematics esignator Description 1 J2 Jumper External signal source to Vp positive analog input Figure A 2 page 49 2 J3 Jumper 1 2 selects DAC signal source Figure A 2 page 49 2 3 selects external input source on J2 3 Connector 20 pin connector to XADC header on FPGA base board Figure A 2 page 49 4 J5 Jumper 1 2 selects DAC signal source Figure A 2 page 49 2 3 selects external input source on J6 5 Je Jumper External signal source to VN negative analog input Figure A 2 page 49 6 DAC 16 bit DAC sets analog test voltage Figure A 1 page 48 7 Amplifier Reference buffer for DAC Figure A 1 page 48 AMS101 Evaluation Card User Guide UG886 v1 3 Novembe
15. 967 Ref 5 Set the USB UART connection to a known port in the Device Manager as follows e Right click My Computer and select Properties Select the Hardware tab Click the Device Manager button e Find and right click the Silicon Labs device in the list Then select Properties e Click the Port Settings tab and the Advanced button e Select the COM port that corresponds to Silicon Labs CP210x USB to UART Bridge see Figure 2 10 18 www xilinx com AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013 XILINX File Action View Help 9 mHE RE gt ql Computer amp ControlVault Device c Disk drives Sy Display adapters b DVD CD ROM drives P ta Human Interface Devices gt xg IDE ATA ATAPI controllers b A Imaging devices b AW Jungo gt EB Keyboards n Mice and other pointing devices Wi Monitors Network adapters i iu Bluetooth Device Personal Area Network Bluetooth Device RFCOMM Protocol TDI BY Cisco Systems VPN Adapter for 64 bit Windows Eu Intel R 82579LM Gigabit Network Connection Lu Intel R Centrino R Ultimate N 6300 AGN i amp Microsoft Virtual WiFi Miniport Adapter 4 SF Ports COM amp LPT 1 ECP Printer Port LPT1 gt Intel R Active Management Technology SOL COM3 Silicon Labs CP210x USB to UART Bridge COMA Standard Serial over Bluetooth link COMS Standard Serial over Bluetooth link COM6 Fl Processors Quick Start Figure 2 10
16. AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013 XILINX XILINX The information disclosed to you hereunder the Materials is provided solely for the selection and use of Xilinx products To the maximum extent permitted by applicable law 1 Materials are made available AS IS and with all faults Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS EXPRESS IMPLIED OR STATUTORY INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY NON INFRINGEMENT OR FITNESS FOR ANY PARTICULAR PURPOSE and 2 Xilinx shall not be liable whether in contract or tort including negligence or under any other theory of liability for any loss or damage of any kind or nature related to arising under or in connection with the Materials including your use of the Materials including for any direct indirect special incidental or consequential loss or damage including loss of data profits goodwill or any type of loss or damage suffered as a result of any action brought by a third party even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications You may not reproduce modify distribute or publicly display the Materials without prior written consent Certain products are subject to the terms and conditions of Xi
17. ART drivers A base board Getting Started Guide Eight steps are needed to get the AMS evaluation platform up and running This chapter covers how to perform these steps as well as how to run key ADC performance tests after setup Hardware and Software Setup 1 Install the AMS Evaluator tool GUI Download the AMS Evaluator installer files 7 Series FPGA and Zynq 7000 AP SoC AMS Evaluator Installer for AMS Targeted Reference Design from the AMS101 Evaluation Card Support Page Click the setup exe file to install the National Instruments LabVIEW RunTime Engine needed to host the AMS Evaluator tool The GUI itself has been built using National Instruments LabVIEW 2011 software To enable use of the GUI without the need for a LabVIEW license Xilinx has bundled the LabVIEW run time engine with the GUI installer During the installation process the run time engine is installed on the PC Connect the FPGA base board Ensure that the FPGA base board power switch e g SW15 on the KC705 base board is in the OFF position Figure 2 2 shows the position of the power switch on the board Connect the host PC to the UART port with the Standard A plug to Mini B plug USB cable Also connect the Standard A plug to Micro B plug USB cable to the JTAG port See the corresponding photo in the Getting Started Guide for each particular base board www xilinx com AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013 XILINX Quick Start
18. LINX Quick Start The LEDs on the FPGA base board should light up as the design is downloading Figure 2 7 shows an example of the LEDs lit up after the KC705 board is programmed UG886 c2 07 071012 Figure 2 7 LEDs after Programming the FPGA with the Design 8 Run the AMS101 evaluator LabVIEW GUI executable file If the AMS Evaluator tool GUI was successfully installed an icon should be displayed on the desktop and in the Windows start menu see Figure 2 8 To open the AMS Evaluator tool GUI click the red Xilinx X icon The GUI shown in Figure 2 9 should appear Note Do not press anything on the GUI until step 9 is performed AMSIUT Evaluator G UG886 c2 08 091012 Figure 2 8 AMS Icon AMS101 Evaluation Card User Guide www xilinx com 17 UG886 v1 3 November 6 2013 Chapter 2 AMS101 Evaluation Card Quick Start XILINX Select COM Port Here DET XILINX AMS101 Evaluator E Cotect Data ni Aso Roc ioni O UG886 c2 09 092512 Figure 2 9 AMS Evaluator Tool on Start Up 9 Connect to the UART port as detailed in the appropriate FPGA processor base board Getting Started Guide e Kintex 7 FPGA KC705 Evaluation Kit Getting Started Guide UG883 Ref 2 e Getting Started with the Virtex 7 FPGA VC707 Evaluation Kit UG848 Ref 3 e Zunq 7000 All Programmable SoC ZC702 Evaluation Kit and Video and Imaging Kit Getting Started Guide UG926 Ref 4 e Artix 7 FPGA AC701 Evaluation Kit Getting Started Guide UG
19. NX gd pe a e Mas bs ci on gt E sibi ar i 2g OAN 3 zio mm ae 5 3 S UG886 c1 01 091012 Figure 1 1 KC705 Evaluation Board with the AMS101 Evaluation Card Installed n Fe E UG886 c1 02 020113 Figure 1 2 AMS101 Evaluation Card Features 8 www xilinx com AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013 XILINX Overview Table 1 1 AMS101 Evaluation Card Features Callout Component Description 1 Jumpers to select DAC or external signal source 20 pin connector to the XADC header on the FPGA or AP SoC base board Pins allow for external analog input signals 16 bit DAC sets analog test voltage 2 3 4 Digital I O level translators 5 6 Reference buffer for DAC rpose oc X X A XILINX AMS101 Evaluator v ER Time Domain Frequency Domain Linearity XADC Registers Sensor Data Debug l Connection Manager Collect Data Coda jip Comat connected 483 4 E ARES SES CEES MESA oui deo QUSS A LESS Y uae 1 Clock Dwdet gt SMR 4 mo Om ence Channel Config eee Window Rectange Bend tee 5 l dossi EZ d s 5 wat Type GBAGL ET 06 092812 Figure 1 3 AMS Evaluator Tool GUI AMS101 Evaluation Card User Guide www xilinx com 9 UG886 v1 3 November 6 2013 Chapter 1 AMS101 Evaluation Ca
20. O a 3 way jumpers Positive External Negative Source External Source UG886 c3 01 062712 Figure 3 1 AMS101 Evaluation Card Block Diagram AMS101 Evaluation Card User Guide www xilinx com 29 UG886 v1 3 November 6 2013 Chapter 3 AMS101 Evaluation Hardware XILINX The block diagram includes these six sub blocks e 20 pin XADC header for interfacing to an FPGA base board e 16 bit DAC analog signal source Analog Devices DAC AD5065 e I O level translators for the serial peripheral interface SPI to the DAC SN74LVC2T45DCT e DAC reference amplifier buffer AD8033 e Connector pins to bring in external positive and negative sources e 3 way jumper pins to select DAC source or external source going to XADC header Interfacing to the FPGA Base Board 30 The AMS101 evaluation card has a 20 pin header that allows it to be plugged into the XADC header which is now available on all Xilinx 7 series FPGA and Zynq 7000 SoC base boards The XADC header provides a means to connect the analog inputs of the XADC to the AMS101 evaluation card circuitry as well as providing a reference power and DAC control signals Figure 3 2 shows the pinout and signal names for the XADC header on the FPGA base board As mentioned the XADC header on the FPGA base board and the 20 pin header on the AMS101 evaluation card are both keyed To ensure correct connectivity the keys must be properly aligned between the AMS101 evaluation card and
21. S e al Figure 3 7 Use Case 3 Circuit Diagram 34 www xilinx com AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013 Board Setup XILINX Jumpers J3 and J5 should both be set between positions 2 3 to disconnect the DAC outputs and enable the external signal connections at J2 and J6 pins 1 for both J2 and J6 See Figure 3 8 Triangle Near Jumpers Indicates Pin 1 Black Filled Boxes Indicate Jumper Position Jumper J2 Jumper J3 Jumper J6 Jumper J5 A uw r J 10 u suna UG886_c3_08_081612 Figure 3 8 Use Case 3 Jumper Configurations Differential External Analog Source AMS101 Evaluation Card User Guide www xilinx com UG886 v1 3 November 6 2013 35 Chapter 3 AMS101 Evaluation Hardware 36 www xilinx com XILINX AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013 XILINX Chapter 4 AMS Evaluator Tool The AMS Evaluator tool GUI uses the National Instruments LabVIEW environment The GUI can be used to e Configure the XADC e Configure the signal source on the AMS101 evaluation card e Initiate an XADC data capture e Perform frequency and time domain analysis on XADC data e Perform a linearity test and display the results e Monitor the internal supply voltage and temperature sensors e Export measurement results to a CSV file e Leverage the FPGA to improve the performance of the XADC using Xilinx Analog Mix
22. UART USB Port in Device Manager UG886 c2 10 092512 AMS101 Evaluation Card User Guide www xilinx com UG886 v1 3 November 6 2013 19 Chapter 2 AMS101 Evaluation Card Quick Start 20 pum XILINX XILINX Select the appropriate COM port from the pull down menu on the GUI as show in Figure 2 11 Then click the Connect button After the AMS Evaluator tool is connected the kit name is displayed below the green Connected circle If the AMS Evaluator tool is unable to connect be sure the correct COM port is selected and click refresh Dese rn Osnes Ley RAD Regem Sewn Cinta Oui amete 1111111111111111111 1 4 x a Hi t i a net Figure 2 11 Select COM Port Here AMS101 Evaluator UG886_c2_11_092512 AMS Evaluator Tool COM Port Selection www xilinx com AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013 XILINX Run Key Performance Tests Run Key Performance Tests All of the software and hardware should be configured and running The AMS101 evaluation card can now be used to perform measurement tests on the XADC Collect Time Domain Data To collect time domain data press the Collect Data button shown in Figure 2 12 A sine wave should display on the screen This sine wave has been generated by the digital to analog converter DAC on the AMS101 evaluation card and passed through to the XADC inputs where it was digitized Collect Data Button
23. alog voltage source on the positive input to the XADC Vp Vauxpo and Vayxpg The negative analog input Vy Vauxno and Vauxng is supplied by DAC B See Figure 3 5 This allows the common mode voltage on the negative input to range between OV and 1V This DAC voltage is configurable in the AMS Evaluator tool GUI For Use Case 2 connect jumper J3 between pins 2 and 3 and connect the external analog signal to pin 1 of jumper J2 Connect jumper J5 between pins 1 and 2 to supply the DAC B voltage as set by the Vy offset box in the AMS Evaluator tool See Figure 3 6 VP VAUXOP VAUX8P VN VAUXON VAUX8N Positive external source UG886 c3 05 092512 Figure 3 5 Use Case 2 Block Diagram AMS101 Evaluation Card User Guide www xilinx com 33 UG886 v1 3 November 6 2013 Chapter 3 AMS101 Evaluation Hardware g XILINX Triangle Near Jumpers Indicates Pin 1 Black Filled Boxes Indicate Jumper Position Jumper J2 Jumper J3 Jumper J5 UG886 c3 06 081612 Figure 3 6 Use Case 2 Jumper Configurations for Single Ended External Analog Source Use Case 3 Differential External Analog Source Use Case 3 covers the case where you want to apply an external differential signal source to the XADC positive and negative inputs Figure 3 7 shows a high level circuit diagram for this use case VP VAUXOP VAUX8P VN VAUXON VAUX8N Positive External Negative Source External Source UG886 c3 07 092512 G d LE O Q L x
24. aluation card Table 3 1 details these operating modes e Onboard DAC signal source for AC or DC measurements e External single ended source e Fully differential signal source Table 3 1 AMS101 Evaluation Card Use Cases a d External Use Case Analog Simul Sampled Uni polar Bi polar Signal Source Source Test FFT INL FFT INL FFT INL 1 x x x x x x x 2 x x x x Use Case 1 On Board DAC Default This is the most common use case and the default factory configuration of the board In this mode each output of the DAC is presented to the three input channels available on the analog header Figure 3 3 illustrates the high level circuit diagram for this use case AMS101 Evaluation Card User Guide www xilinx com 31 UG886 v1 3 November 6 2013 Chapter 3 AMS101 Evaluation Hardware g XILINX VP VAUXOP VAUX8P VN VAUXON VAUX8N 20 Pin XADC Header UG886 c3 03 092512 Figure 3 3 Use Case 1 Block Diagram To enable this use case connect jumpers J3 and J5 between pins 1 and 2 as shown in Figure 3 4 Only these two jumpers need to be populated DAC A always supplies the output to the positive XADC inputs Vp Vauxop and Vauxsp DAC B always supplies the output to the negative XADC inputs Vy Vauxon and VAUXaN Triangle Near Jumpers Indicates Pin 1 Black Filled Boxes Indicate Jumper Position dir Jumper J3 5 NU im AGND Jumper J5 A E 32 KA LINE
25. e UG850 10 Zynq 7000 All Programmable SoC ZC706 Evaluation Kit Getting Started Guide ISE Design Suite and Vivado Design Suite UG961 11 AC701 Evaluation Board for the Artix 7 FPGA User Guide UG952 54 www xilinx com AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013 XILINX Appendix D Regulatory and Compliance Information This product is designed and tested to conform to the European Union directives and standards described in this section Declaration of Conformity Directives Standards See the AMS101 Evaluation Card CE Declaration of Conformity 2006 95 EC Low Voltage Directive LVD 2004 108 EC Electromagnetic Compatibility EMC Directive EN standards are maintained by the European Committee for Electrotechnical Standardization CENELEC IEC standards are maintained by the International Electrotechnical Commission IEC Electromagnetic Compatibility EN 55022 2010 Information Technology Equipment Radio Disturbance Characteristics Limits and Methods of Measurement EN 55024 2010 Information Technology Equipment Immunity Characteristics Limits and Methods of Measurement This is a Class A product In a domestic environment this product can cause radio interference in which case the user might be required to take adequate measures Safety IEC 60950 1 2005 Information technology equipment Safety Part 1 General requirements EN 60950 1 2006 Information technolog
26. e by side as shown in Figure 4 3 To revert to the single channel data display change the Display Options pull down menu highlighted in Figure 4 3 Display Options o AMS101 Evaluator vs E Coliect Data m pe D comectea nas Kintex 7 vana i When the Simul Sampled option is selected VAUXO is displayed on the left and Da VAUX8 is displayed onthe vn Oat right OIENINYYT Resolution b o mo soo moe pooo aoo aio UG886 c4 03 092512 Figure 4 3 Data Display for Simultaneous Sampling Mode Clocking XADC Sample Rate The XADC is a dual 12 bit ADC running at speeds of up to 1 MSPS The speed of the ADC is dictated by the frequency of the clock which is the divided down version of the clock it receives at the block level The clock divider register of the XADC defines the division factor The GUI gives direct access to it see Figure 4 4 A clock divide ratio can be input directly or a desired ADC sample rate can be specified and the GUI in this instance calculates the most appropriate clock divider By default the clock divide register is set so that the XADC sample rate is 1 MSPS The XADC clock is 100 MHz and a clock divide ratio of four gives a sample rate of 961 54 kSPS See 7 Series FPGAs and Zyng 7000 All Programmable SoC XADC Dual 12 Bit 1 MSPS Analog to Digital Converter User Guide UG480 Ref 6 for more details on the clocking of the XADC AMS101 Evaluation Card Use
27. eck this box for DAC DC outputs Vn offset sets DAC A negative output voltage Vp offset sets DAC B positive output voltage 1 Me UG886 c4 05 062712 Figure 4 5 DAC Control Panel Options When various modes of operation are selected appropriate values are written to the Vp and Vn offset fields A change to the Input Type field or a change to Generate Sinewave Using DAC causes such actions Table 4 1 shows the default values set when the mode is changed Table 4 1 AMS Evaluator Tool DAC Voltage Defaults Configuration DAC B DAC A l Vp Offset Vy Offset Unipolar mode DAC sine wave generation Default power up mode und si Unipolar mode external source 0 25V OV Bipolar mode DAC sine wave generation 0 5V 0 5V Bipolar mode external source 0 25V 0 5V XADC Performance Tests A selection of tabs is located across the top of the AMS Evaluator tool under the Xilinx logo Time Domain Frequency Domain Linearity and Sensor Data tabs are associated with XADC performance tests Time Domain The Time Domain tab gives access to XADC data without any post processing In single channel mode when the Collect Data button is clicked 4 096 sequential XADC results are taken from the Vp VN result register stored in memory When all 4 096 samples are in www xilinx com 41 UG886 v1 3 November 6 2013 42 Chapter 4 AMS Evaluator Tool XILINX memory the data is transf
28. ed Signal AMS technology The AMS Evaluator tool allows selection of various measurements by choosing various tabs across the top of the GUI as shown in Figure 4 1 The configuration of the XADC and signal source is controlled by the panels on the right side of the tool Tabs to View XADC Data XILINX AMS101 Evaluator u Time Comma Frequency Damu Linearity XADC Registers Sense Data Debo tem on Collect Data mnan cn vy Oa ve Coat eee arl Decimation vt via AMS XADC Control 11111111111111111111111111 Signal Source we Generation i UG886 c4 01 110413 Figure 4 1 AMS Evaluator Tool GUI on Start Up AMS101 Evaluation Card User Guide www xilinx com 37 UG886 v1 3 November 6 2013 Chapter 4 AMS Evaluator Tool XILINX XADC Configuration The XADC control panel highlighted in Figure 4 2 allows changes to several internal XADC configuration registers These panels specify the XADC sampling rate the input signal type unipolar or bipolar and either single channel mode or simultaneous channel mode Changing any of the items on the XADC Control panel writes the appropriate data to the XADC register automatically The XADC sample rate can be set between 100 kilo samples per second kSPS and 1 MSPS Unipolar inputs force the negative analog input to ground and the positive input can swing between 0 and 1V Bipolar inputs allow both analog inputs to swing 500 mV with a comm
29. erred to the AMS Evaluator tool through the USB UART connection The AMS Evaluator tool then does a mean minimum maximum and standard deviation calculation on the data before displaving it In the case of simultaneous sampling mode 8 192 XADC results are taken 4 096 for Vauxo and 4 096 for Vayxg The AMS Evaluator tool receives all 8 192 pieces of data in one arrav and splits it appropriatelv The tool then does a mean minimum maximum and standard deviation calculation separately on Vayxo and Vauxs data The Vauxo and Vauxg data is then displayed side by side in a dual display The mean minimum maximum and standard deviation calculation results are shown below the graph of the XADC samples Frequency Domain The Frequency Domain tab enables an FFT on the XADC data Similar to the time domain data collection 4 096 sequential XADC results for Vp VN are taken when in single channel mode and 4 096 XADC results of Vauxo and 4 096 XADC results of Vauxg are taken in simultaneous sampling mode An FFT is then performed on this data and key ADC dynamic performance metrics are calculated and displayed These metrics include signal to noise ratio SNR total harmonic distortion THD signal to noise and distortion SINAD spurious free dynamic range SFDR and effective number of bits ENOB If the signal source is not the DAC on the evaluation card then windowing is carried out on the XADC data before the FFT is performed This is because the ex
30. for Base Boards XILINX J70 In place between pins 2 and 3 See ZC702 Evaluation Board for the Zynq 7000 XC7Z020 All Programmable SoC User Guide UG850 Ref 9 Jumper Settings for the ZC706 Board To enable AMS evaluation ensure the ZC706 board has the following jumper settings J12 Not in place XADC GND Bypass J13 In place XADC GND J14 In place XADC VCC5V0 J52 In place between pins 1 and 2 XADC VREP Sel J53 In place between pins 2 and 3 XADC VCC Sel J54 In place between pins 2 and 3 See Zunq 7000 All Programmable SoC ZC706 Evaluation Kit Getting Started Guide ISE Design Suite and Vivado Design Suite UG961 Ref 10 Jumper Settings for the AC701 Board To enable AMS evaluation ensure the AC701 board has the following jumper settings 52 J11 In place J53 In place J9 In place J10 In place J43 In place between pins 2 and 3 J54 In place between pins 2 and 3 J42 In place between pins 1 and 2 See AC701 Evaluation Board for the Artix 7 FPGA User Guide UG952 Ref 11 www xilinx com AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013 XILINX Appendix C Additional Resources Xilinx Resources For support resources such as Answers Documentation Downloads and Forums see the Xilinx Support website For continual updates add the Answer Record to your my Alerts For definitions and terms see the Xilinx Glossary Solution Centers See the Xilinx Sol
31. h channel is sampled once per second by the MicroBlaze processor program running as part of the AC701 AMS Targeted Reference Design The current sense values of 1 8V supply 3 3V supply MGTAVCC and MGTAVTT along with voltage levels of 3 3V supply MGTAVCC and MGTAVTT are available on the AC701 board s onboard MUX positioned at U14 The differential output of the MUX is connected to auxiliary pin 9 VayxP N 9 of XADC AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013 www xilinx com 25 Chapter 2 AMS101 Evaluation Card Quick Start XILINX The voltage current and power calculation of each rail is displayed in the Power Monitor tab on the AMS Evaluator GUI as shown in Figure 2 16 The Power Monitor tab is designed specifically for the AC701 board and is not available on the other AMS Targeted Reference Designs ZC702 KC705 or VC707 x EL AMS101 Evaluator GUI B summ Lo E es eed Soi a TE XILINX 7 AMS101 Evaluator vino TA Time Domain Frequency Domain Linearity XADC Registers Sensor Data Power Monitor Debug Connection Manager Power E Connect Connected Voltage Vdc Current Adc Power W a 9 Supplies AC701 COM5 E Ver 100 VCCINT S s VCCAUX VCCBRAM 1 5V SUPPLY x VCCO ADJ a S 18V SUPPLY gt 3 3V SUPPLY MGTAVCC MGTAVIT Fi Q Vv gt parar 420 40 gt a a gt amp
32. ics and Dynamic Performance Metric Calculation XILINX VADJ XADC_VCCSVO ib CI i C2 T 04UF QAUF zr XU SN74LVC2T4SDCT ou X5R X5R GND GND 3 gXADC GPIO 3 SYNC B 3 gXADC GPIO 2 DIN VADJ 7 ML Qua rela U1 dct8 14x70 GE GND e XADC VCC5VO XADC VCC5VO 3 7 0 aS at C4 1 C5 R6 11 R7 0 1UF 10UF 5 1K 5 1K 25V TZ 21 100 1 10W 1 10W 4 X5R X5R 1 22 1 4 Ls 5 a XADC AGND ADSOGSBRUZ 1 R4 LDACB SCLK 1 00K 1A6W SYNCB DIN 196 VDD PDLB Os 4 e e U8 VREF VREFA GND ress DACOUTB R ru VOUTA VOUTB E m c7 li TWIL 1 C6 POR VREFB 1 25V TE 21 25V X5R 800 21 Xn Ug SNPTETETS v XADYAGND XADC_AGND yY GND XADC AGND D AGND M VADJ XADC_VCCSVO Dx TO T Tute DACOUTA R as me m 1 C9 iL cio ME T 04UF 0 1UF 21 25V 25V X5R X5R GND GND XADC GPIO 1 SCLK ES 1 XADG_AGND 3 mXADC_GPIO_0 LDAG B H9 1 RIOJi VADJ DNP DNP E snow now a 5 2 5 2 E E U4 dct8 14x70 CSS Figure A 1 UG886_aA_01_062512 AMS101 Evaluation Card Schematic 1 of 2 48 www xilinx com AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013 XILINX Dynamic Performance Metric Calculation Methodologv XADC VCC5VO
33. linx s limited warranty please refer to Xilinx s Terms of Sale which can be viewed at http www xilinx com legal htm tos IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx Xilinx products are not designed or intended to be fail safe or for use in any application requiring fail safe performance you assume sole risk and liability for use of Xilinx products in such critical applications please refer to Xilinx s Terms of Sale which can be viewed at http www xilinx com legal htm tos Automotive Applications Disclaimer XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL SAFE PERFORMANCE SUCH AS APPLICATIONS RELATED TO I THE DEPLOYMENT OF AIRBAGS Il CONTROL OF A VEHICLE UNLESS THERE IS A FAIL SAFE OR REDUNDANCY FEATURE WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR OR Ill USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS Copyright 2012 2013 Xilinx Inc Xilinx the Xilinx logo Artix ISE Kintex Spartan Virtex Vivado Zvnq and other designated brands included herein are trademarks of Xilinx in the United States and other countries All other trademarks are the property of their respective owners Revision History The following table shows
34. nto a histogram This histogram data is then transferred to the GUI through the USB UART connection and a differential non linearitv DNL and integral non linearitv INL calculation are performed This data then displavs Sensor Data The XADC block contains four integrated sensors within the FPGA The first is a temperature sensor and the other three monitor the FPGA voltage supplies Vecaux Vccinr and Vccpram These sensors are all digitized by the XADC when the XADC is in default mode or when they are enabled as part of the channel sequence of the XADC When the Sensor Data tab is selected all of the XADC settings are stored in memory in the GUI The part is then forced into Default mode See 7 Series FPGAs and Zynq 7000 All Programmable SoC XADC Dual 12 Bit 1 MSPS Analog to Digital Converter User Guide UG480 Ref 6 The digitized representation for the XADC then displays The Power Control panel highlighted in Figure 4 7 can be used to modify physical voltages being applied to the three supplies in question Vccaux Vecint and VccBRAM After changing the voltages and clicking the Update UCD9248 button the corresponding plot should change showing the actual voltage now being applied to the part within the part itself foco 0 TESE E i 7 XILINX AMS101 Evaluator vo m cu Time Domain Frequency Domain Linearity XADC Registers Sensor Data Debug Connection Manager Temp C et 9 essas x ver a 5 L 1 a a Power Contr
35. ol gt VecAUX VeciNT VccBRAM i E Changethe actual voltages beingappliedto the FPGA with the Texas Instruments UCD9248 power controller UGB86 c4 7 110413 Figure 4 7 Sensor Data Tab and Power Control Panel AMS101 Evaluation Card User Guide www xilinx com 43 UG886 v1 3 November 6 2013 Chapter 4 AMS Evaluator Tool XILINX AMS Demonstration nto GUI XILINX Time Domain 44 Ampitede 83 bob a boh b 3 sanii The Analog Mixed Signal AMS technology leverages the digital signal processing capabilities of Xilinx FPGA interconnect logic to enhance the performance and functionality of the local XADC block The AMS101 evaluation card offers a very limited glimpse into the possibilities of the AMS concept by enabling efficient decimation Decimation The AMS Evaluator tool enables decimation of the XADC data by a certain factor effectively trading off input bandwidth for higher SNR performance This factor is defined by the field shown on Figure 4 8 Select between a decimation rate of 1 2 4 8 or 16 A decimation of 1 indicates that the XADC data is passed directly to the AMS Evaluator tool without any filtering or decimation The decimation function is carried out in the FPGA using very little resources The core building block is a decimate by 2 block It first passes the XADC data through a half band filter and then decimates by a factor of 2 as shown in Figure 4 9
36. on AC701 The AC701 evaluation board and AMS Evaluator tool offer a complete system monitoring solution The AC701 uses the XADC to measure voltage and load current on nine of the onboard power supplies Voltage is measured using remote sensing Current is measured across a sense resistor with individual current sense op amps Power is then calculated for each of the nine rails by multiplying voltage x current An external multiplexer is also used 24 www xilinx com AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013 XILINX Power Monitoring with XADC on AC701 to switch all 18 measurements into the XADC Table 2 2 details the power rails monitored on the AC701 Table 2 2 AC701 Voltage Rails Measured with AMS Targeted Reference Design Rail Name Voltage Current Veen No Yes Vecaux No Yes VcCHRAM M No Yes 1 5V Supply Yes Yes Vcco ADJ Yes Yes 1 8V Supply Yes Yes 3 3V Supply Yes Yes MGTAVCC Yes Yes MGTAVTT Yes Yes Notes 1 Vecint Vecaux and VccBRAM Voltage levels are measured by XADC onboard sensors and A Both the Sensor Data tab and the Power Monitor tab displayed i The current sense values of Vccinv Vecaux VecBRAm 1 9V supply and Vcco apy along with voltage levels of 1 5V supply Vcco app and 1 8V supply are available on the AC701 board s onboard MUX positioned at U13 The differential output of the MUX is connected to auxiliary pin 1 VauxP N 1 of XADC and eac
37. on Card Overview Instances of AMS101 evaluator tool were corrected to AMS evaluator tool Added part HW AMS101 G Reference design files are now downloaded from www xilinx com support documentation ams101 evaluation card htm The AC701 board is now supported The bullet with AMS evaluator tool graphical user interface was removed from section AMS101 Evaluation Card page 7 Download information for the AMS evaluator tool graphical user interface is listed in the last bullet on page 7 and the bullet about FPGA programming files was removed Chapter 2 AMS101 Evaluation Card Quick Start The onboard signal source is from a 16 bit dual DAC page 11 In step 1 page 12 download information changed In step 7 page 16 the AC701 kit and kit documentation references were added Various changes were added to step 9 page 18 Added section Power Monitoring with XADC on AC701 page 24 Chapter 4 AMS Evaluator Tool Decimation information and Table 4 2 were added on page 44 Appendix A Targeted Design Platforms Schematics and Dynamic Performance Metric Calculation Methodology AC701 was added to the Supported Targeted Design Platforms section Appendix B Required Jumper Settings for Base Boards Added Jumper Settings for the AC701 Board page 52 11 06 2013 1 3 Updated for Vivado Design Suite 2013 3 Procedures in step 7 page 16 were revised for the Vivado tool and the KC705 ZIP file name changed Support for Zynq
38. on mode range between 0 and 1V Single channel mode measures data on the Vp Vw channels Simultaneous sampling mode sends the same analog signals onto both DACSs over channels Vauxpo VAUXNO and VAUXP8 VAUXNS The default mode of operation is single channel bipolar and sampling at 961 4 kSPS XILINX AMS101 Evaluator n Time Domain 38 m Frequency Domain Linearity XADC Registers Sensor Dene Debug a Connect Collect Data trt O connected arm evt zi Ver Ea XADC Configuration T Control i Ld EE E E EEEE EE AG Hilitili m a tei E KI me me mo sa ma ma pa vu 1 m E Me Ma UG886 c4 02 062512 Figure 4 2 XADC Configuration Control Panel Channel Options Single Channel Simultaneous Sampling To select between the two modes of operation single channel mode and simultaneous sampling mode select the desired option from the Channel Options pull down menu located in the XADC control panel see Figure 4 2 After the Channel Options pull down menu changes the appropriate data is written to the XADC registers www xilinx com AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013 XILINX XADC Configuration In this mode the data for Vp Vn is captured processed and displayed every time you press the Collect Data button If you choose the simultaneous sampling option then the GUI changes to a dual display where XADC data for channel Vauxo and Vauxg display sid
39. r 6 2013 www xilinx com 15 Chapter 2 AMS101 Evaluation Card Quick Start XILINX 6 Power up the FPGA base board The power switch can now be put in the ON position switch toward the power plug Figure 2 6 shows the location of the power switch It also shows the LEDs illuminated on the FPGA base board This should occur directly after the FPGA base board switch is flipped into the ON position A few seconds after power up the DONE LED should illuminate At this stage hardware connection is complete Power Switch AASSIAS ZI UG886 c2 06 071012 Figure 2 6 Turning On the FPGA Base Board Power 7 Download the design to the FPGA See the individual kit AC701 ZC702 KC705 or VC707 Getting Started Guides or the 7 Series FPGA AMS Targeted Reference Design User Guide UG960 Ref 1 for more specific instructions on downloading the design For the AMS101 evaluation card to function the FPGA needs to be programmed with the appropriate design To do this download the design to the FPGA a Open the Vivado O Design Suite Here is one example path for Vivado tools Start menu Xilinx Design Tools Vivado 2013 3 Vivado 2013 3 b Create a Vivado Project c Opena Hardware Session d Open a new Hardware Target and run through the wizard Open AMS KC705 bitstream bit from the rdf0280 ams101 kc705 trd 2013 3 zip file 16 www xilinx com AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013 XI
40. r Guide www xilinx com 39 UG886 v1 3 November 6 2013 XILINX Chapter 4 AMS Evaluator Tool pura RE oa XILINX AMS101 Evaluator va mio a Tie Bum PP Do Ly ADC Right Sener Ds ng abu GR nina Collect Data Contran p mcd 3 Connes mas Kintex 7 EL Agitado ij AED EL ES XADC Sample m Rate Modification XADC Control Clocking TA X Sinec Channel Config seo pes xo o owe UG886 c4 04 062512 Figure 4 4 XADC Sample Rate Changes Signal Source Configuration The AMS101 evaluation card uses an AD5065 dual 16 bit DAC as a signal source to the XADC When either the Time Domain or Frequency Domain tabs are selected the GUI provides access to the control of the DAC through the DAC control panel on the GUI as shown in Figure 4 5 The Vp and Vy offset fields can be used to define the DC level of each output of the DAC Vp corresponds to DACB and Vy corresponds to DACA By selecting the Generate Sinewave Using DAC tick box a sine wave with a common mode defined by the Vy offset field is output on DACA which then drives the positive input of all three available channels 40 www xilinx com AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013 AMS101 Evaluation Card User Guide XILINX XADC Performance Tests T XILINX AMS101 Evaluator Time Domain Frequency Domain Linearity XADC Registers Sensor Dats Debug Cotact Osta cme n e gru Unch
41. rd Overview 10 www xilinx com XILINX AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013 XILINX Chapter 2 AMS101 Evaluation Card Quick Start To facilitate easy evaluation of key performance metrics of the XADC and AMS technology Xilinx developed the AMS evaluation platform for all 7 series FPGA and Zynq 7000 AP SoC base boards The AMS evaluation platform Figure 2 1 enables key ADC performance metrics to be observed and evaluated The remainder of this document describes in detail the hardware and software that comprise the AMS evaluation platform XADC Header DZ AMS101 FMC HPC FMC LPC Evaluation Card KX325T FFG900 1 Gb s Ethernet PHY PCIExpress KC705 Base Board PCI Express UG886 c2 01 101812 Figure 2 1 AMS Evaluation Platform AMS Evaluation Platform Features The AMS evaluation platform provides A complete XADC and AMS evaluation solution An onboard signal source from a 16 bit dual DAC Configurable analog inputs An interactive GUI Interfaces for all the latest Xilinx FPGA or AP SoC base boards including the KC705 Kintex 7 FPGA base board as detailed in this document See the full list of supported base boards in Appendix A AMS101 Evaluation Card User Guide www xilinx com 11 UG886 v1 3 November 6 2013 Chapter 2 AMS101 Evaluation Card Quick Start XILINX Each base board kit contains Quick Start 12 One AMS101 evaluation card USB U
42. ternal source might or might not be a coherent source The windowing method can be changed by adjusting the pull down menu shown in Figure 4 6 By default it is set to a fourth order Blackman Harris window and five bins on either side of the fundamental are discarded in the SNR calculation so rate GTP RN m 006 XILINX AMS101 Evaluator wo M Qu Time Domain Frequency Domain Linearity XADC Registers Sensor Data Debug zi E Connection Manager Collect Data ATE E Connect d Connected COM Ver _DAC Comi 7 Vea BA T ded Vp Offset 2 0 500 Vn Offset 0 000 Amplitude 5 Enable Internal Shorting Docimation Value 1 16 Bits XADC Control Clocking Desired ADC Sample Rate 96154 K Sisec Clock Divider SNR NaN mol Nan SINAO NaN SFORI Nan ENOB Nan Channel Config Channel Options 7j Single Window 5 Rectangle Band Bins 7 5 Input Type Bi Polar Windowing Method NumberofBins Ignored in Employed SNR Calculation UG886 c4 06 092512 Figure 4 6 Windowing Options www xilinx com AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013 XILINX Linearitv XADC Performance Tests Select the Linearitv tab to perform a linearitv test on the XADC During this test the signal source is used as a map source to the XADC When the Collect Data button is clicked in the GUI the DAC begins to ramp up and the XADC results are collected i
43. tion card part number HW AMS101 G provides an analog source to verify the XADC and AMS performance The AMS101 evaluation card plugs into all Xilinx 7 series FPGA and Zynq 7000 AP SoC base boards Reference designs are supplied for the ZC702 KC705 AC701 and VC707 base boards Download these files from either the individual kit support pages or the AMS101 Evaluation Card website For convenience the KC705 FPGA base board is used as the example in this document see Figure 1 1 The KC705 evaluation kit includes hardware and soft content required to evaluate XADC and to determine how it can be useful in the end system To evaluate the Xilinx Analog Mixed Signal AMS capability these items from the kit are needed e Access to the XADC header see Figure 1 1 e AMS101 evaluation card see Figure 1 2 and Table 1 1 for a description of features e Two USB cables 1x Standard A plug to Mini B plug USB cable and 1x Standard A plug to Micro B plug USB cable for download and debug e USB UART drivers Download AMS reference design files from the AMS101 Evaluation Card website e Download AMS evaluator tool graphical user interface 7 Series FPGA and Zynq 7000 AP SoC AMS Evaluator Installer for AMS Targeted Reference Design see Figure 1 3 AMS101 Evaluation Card User Guide www xilinx com 7 UG886 v1 3 November 6 2013 Chapter 1 AMS101 Evaluation Card Overview XILINX AMS101 Evaluation Card XADC Header Under AMS101 Card o E XU
44. to AMS101 Evaluator vo m qu Frequency Domain Linearity XADC Registers Sensor Data Debug Connection Manager f 1 E Connect 2 Connected Collect Data Cortmuout om Kintex 7 Ver DAC C 1 Generate Semen Using DAC Vp Ofset Va Ofset j ni Change m Decimation between 11 2 4 8 0r 16 29909 soio 75000 100000 125000 150000 178000 200000 226000 250006 178008 300000 124006 300 175009 430000 29000 80000 175000 500000 Svr Frequency He Chock Doador 714 S082 77 soa n 65 ENOBI cou Channel Config Channel Options g Window Bans Be leout Type UG886 c4 08 062512 Figure 4 8 Decimation Rate Selection Decimating by 2 cuts the input bandwidth in half The frequency graph in the Frequency Domain tab reflects this as the input bandwidth goes from 500 KHz with a decimation of 1 to 250 kHz with a decimation of 2 To achieve a decimate by 4 the FPGA passes the XADC data through the decimate by 2 block and feeds back its output to the block s input so that it can be band limited and decimated by 2 again giving an overall decimation rate of 4 For a decimation rate of 8 the data is looped back through the decimate by 2 block a second time www xilinx com AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013 XILINX AMS Demonstration Decimation is a powerful way of improving the SNR SINAD and ENOB Figure 4 2 details a sample of typical results with the AMS101 evaluation card connected to various base boards
45. ution Centers for support on devices software tools and intellectual property at all stages of the design cycle Topics include design assistance advisories and troubleshooting tips References The most up to date information related to the AMS101 Evaluation Card and its documentation is available on these websites AMS101 Evaluation Card AMS101 Evaluation Card documentation AMS101 Evaluation Card Master Answer Record AR 52165 Analog Mixed Signal AMS101 Instructor led Training and Online Training These Xilinx documents and sites provide supplemental material useful with this guide 1 7 Series FPGA AMS Targeted Reference Design User Guide UG960 2 Kintex 7 FPGA KC705 Evaluation Kit Getting Started Guide UG883 3 Getting Started with the Virtex 7 FPGA VC707 Evaluation Kit UG848 4 Zynq 7000 All Programmable SoC ZC702 Evaluation Kit and Video and Imaging Kit Getting Started Guide UG926 5 Artix 7 FPGA AC701 Evaluation Kit Getting Started Guide UG967 6 7 Series FPGAs and Zynq 7000 All Programmable SoC XADC Dual 12 Bit 1 MSPS Analog to Digital Converter User Guide UG480 7 KC705 Evaluation Board for the Kintex 7 FPGA User Guide UG810 8 VC707 Evaluation Board for the Virtex 7 FPGA User Guide UG885 AMS101 Evaluation Card User Guide www xilinx com 53 UG886 v1 3 November 6 2013 Appendix C Additional Resources XILINX 9 ZC702 Evaluation Board for the Zynq 7000 XC7Z020 All Programmable SoC User Guid
46. y equipment Safety Part 1 General requirements AMS101 Evaluation Card User Guide www xilinx com 55 UG886 v1 3 November 6 2013 Appendix D Regulatory and Compliance Information XILINX Markings This product complies with Directive 2002 96 EC on waste electrical and electronic equipment WEEE The affixed product label indicates that the user must not discard this electrical or electronic product in domestic household waste This product complies with Directive 2002 95 EC on the restriction of hazardous substances RoHS in electrical and electronic equipment This product complies with CE Directives 2006 95 EC Low Voltage Directive LVD and 2004 108 EC Electromagnetic Compatibility EMC Directive 56 www xilinx com AMS101 Evaluation Card User Guide UG886 v1 3 November 6 2013
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