NCO MegaCore function, v8.0 User Guide
Contents
1. Table 1 3 NCO MegaCore Function Performance Cyclone III Devices Accumulator Angular Magnitude Combinational Logic Memory 9x9 fmax Width Precision Precision LUTs Registers Bits M9K Blocks MHz Large ROM 1 32 12 12 166 161 458 752 56 298 Multiplier Based 2 32 16 16 351 287 12 288 2 8 229 Parallel CORDIC 2 32 14 14 1 173 1 158 300 Small ROM 2 32 14 16 363 298 61 440 8 300 Notes to Table 1 3 1 Using EP3C16F484C6 devices 2 Using EP3C10F256C6 devices Table 1 4 shows performance figures for Stratix III devices Table 1 4 NCO MegaCore Function Performance Stratix Devices Accumulator Angular Magnitude Combinational Logic Memory 18x18 fmax Width Precision Precision ALUTS Registers Blocks MHz Large ROM 1 32 12 12 69 149 98 304 12 512 Multiplier Based 1 32 16 16 117 206 12 288 2 4 498 Parallel CORDIC 1 32 14 14 1 370 1 536 0 513 Small ROM 1 32 14 16 189 298 61 440 8 503 Note to Table 1 4 1 Using EP3SE50F780C2 devices Altera Corporation MegaCore Version 8 0 1 5 May 2008 NCO MegaCore Function User Guide Installation and Licensing Installation and The NCO MegaCore Function is part of the MegaCore IP Library which is distributed with the Quartus II software and downloadable from the L Icensin 0 Altera website www altera com For system requirements and installation instructions refer to Quartus Ins2. Frequency Resolution 0 05 Hz Where f is the free running output frequency of the NCO Table A 1 shows the mapping of the symbols to output frequencies assuming that the free running frequency is set to 15 36 MHz by setting the phase increment of the oscillator to 299866808 Table A 1 Symbol Mapping Binary Symbol Frequency Modulation Value Output Frequency MHz 10 4182517243 9 60 11 4257483945 13 44 01 37483351 17 28 00 112450053 21 12 To meet these requirements the design uses the following NCO MegaCore function settings m Parallel CORDIC algorithm In the overall hypothetical design other system blocks use much of the Stratix device s internal memory and DSP blocks however logic elements LEs are in abundant supply The need for a high precision high performance oscillator that uses logic elements only makes the Parallel CORDIC algorithm a suitable choice MegaCore Version 8 0 A 3 NCO MegaCore Function User Guide Example Design 2 W Phase accumulator precision The frequency resolution specifications demand a phase accumulator precision of 32 bits Frequency modulator precision To maximize the frequency resolution of the modulating signal the resolution of the frequency modulator is also set to 32 bits of precision Angular and magnitude precision and dithering An angular precision of 15 bits a magnitude precision of 14 bits and a dithering level of 5 meet
3. is 2M1 where N is the magnitude precision and N is an integer in the range 10 32 Figure 4 1 shows a block diagram of a generic NCO Figure 4 1 NCO Block Diagram Peni equireg Dither OEE Optional Generator Frequency Phase Modulation Internal Modulation Input Dither Input em DITH om Phase Waveform P sine Increment gt C gt gt Generation Ng Unit I cosine D lt Phase Accumulator Altera Corporation MegaCore Version 8 0 4 3 May 2008 NCO MegaCore Function User Guide Functional Description 4 4 3 4 5 6 The generated output frequency f for a given phase increment inc is determined by the equation f m Hz where M is the accumulator precision and fis the clock frequency The minimum possible output frequency waveform is generated for the case where 1 This case is also the smallest observable frequency at the output of the NCO also known as the frequency resolution of the NCO fres given in Hz by the equation For example if a 100 MHz clock drives an NCO with an accumulator precision of 32 bits the frequency resolution of the oscillator is 0 0233 Hz If you want an output frequency of 6 25 MHz from this oscillator then you should apply an input phase increment of 6 623 x I0 232 268435456 100 x 10 The NCO MegaCore function automatically calculates this value given the parameters you choose IP
4. ccccccsscssccsscessceseessecssecsscesscesssesscesscesscessessecseesssessecseseaeceaeceatenseesecseserseseatesseens 4 9 Phase Dithering Multi Chame EO CETTE Timing DIASrams oen t edd tii teda ea set Here Avalon Streaming Interface ar s ISI Saa TREE DT ULTIME Altera Corporation MegaCore Version 8 0 iii May 2008 NCO MegaCore Function User Guide Contents Appendix A Example Designs Example ette e ie HH sce Example Design 2 Additional Information REVISION EISUOEV acre tette htl ritenere en M recie How to Contact Altera Typographic Conventions iv MegaCore Version 8 0 Altera Corporation NCO MegaCore Function User Guide May 2008 ANU 8 RYAN 1 About This MegaCore Function Release Information Device Family Support Altera Corporation May 2008 Table 1 1 provides information about this release of the Altera NCO MegaCore function Table 1 1 NCO MegaCore Function Release Information Item Description Version 8 0 Release Date May 2008 Ordering Code IP NCO Product ID s 0014 Vendor ID s 6AF7 For more information about this release refer to the IP Library Release Notes and Errata Altera verifies that the current version of the Quartus II software compiles the previous vers
5. or a user library specified in the User Libraries page of the Settings dialog box Assignments menu Your current user library directories are Cancel lt Back Next gt Finish Altera Corporation May 2008 MegaCore Version 8 0 2 3 NCO MegaCore Function User Guide MegaWizard Plug In Manager Flow 4 Checkthatthe device family is the same as you specified in the New Project Wizard Refer to the Quartus II help for more information about the MegaWizard Plug In Manager 5 Choose the top level output file name for your MegaCore function variation and click Next to launch IP Toolbench see Figure 2 3 Figure 2 3 IP Toolhench Parameterize X About this Core t Documentation Display Symbol step 1 FR Step 3 Generate 6 Click Step 1 Parameterize in IP Toolbench to display the Parameterize NCO window Use this dialog box to specify the required parameters for the MegaCore function variation UM Foran example of how to set parameters for the NCO MegaCore function see Chapter 3 Parameter Settings 7 Click Step 2 Setup Simulation in IP Toolbench to display the Set Up Simulation NCO page Figure 2 4 on page 2 5 2 4 MegaCore Version 8 0 Altera Corporation NCO MegaCore Function User Guide May 2008 Altera Corporation May 2008 Getting Started Figure 2 4 Set Up Simulation 9 set Up Simulation NCO B
6. ANU S RYA e 101 Innovation Drive San Jose CA 95134 www altera com MegaCore NCO MegaCore Function User Guide MegaCore Version 8 0 Document Date May 2008 Copyright 2008 Altera Corporation rights reserved Altera The Programmable Solutions Company the stylized Altera logo specific device des ignations and all other words and logos that are identified as trademarks and or service marks are unless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other countries other product or service names are the property of their respective holders 1 tera products are protected under numerous U S and foreign patents and pending applications maskwork rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the ap plication or use of any information product or service described herein except as expressly agreed to in writing by Altera NSAI Corporation Altera customers are advised to obtain the latest version of device specifications before relying on any published in formation and before placing orders for products or services I S EN ISO 9001 Part Number UG NCOCOMPILER 7 0 ii MegaCore Version 8 0 Altera Corporation NCO Me
7. The MathWorks MATLAB and Simulink system level design tools with Altera Quartus II software and third party synthesis and simulation tools You can combine existing Simulink blocks with Altera DSP Builder blocks and MegaCore function variation blocks to verify system level specifications and perform simulation After installing the NCO MegaCore function a Simulink symbol for the MegaCore function appears in the MegaCore Functions library of the Altera DSP Builder Blockset in the Simulink library browser You can use the NCO MegaCore function in the MATLAB Simulink environment by performing the following steps 1 Createa new Simulink model 2 Choose the NCO block from the MegaCore Functions library in the Simulink Library Browser add it to your model and give the block a unique name MegaCore Version 8 0 2 1 NCO MegaCore Function User Guide MegaWizard Plug In Manager Flow 3 Double click on the NCO MegaCore function block in your model to display IP Toolbench and click Step 1 Parameterize to parameterize the MegaCore function variation For an example of how to set parameters for the NCO MegaCore function see Chapter 3 Parameter Settings 4 Click Step 2 Generate in IP Toolbench to generate your NCO MegaCore function variation For information about the generated files see Table 2 1 on page 2 7 5 Connect your NCO MegaCore function variation to the other blocks in your model 6 Simulate the NCO MegaCore
8. a single stream and de multiplex the output streams into their respective down sampled channelized outputs Timing Diagrams Figure 4 4 shows the timing with a single clock cycle per output sample Figure 4 4 Single Cycle Per Output Timing Diagram clk clken phi_inc_i reset_n out_valid All NCO architectures except for serial CORDIC and multi cycle multiplier based architectures output a sample every clock cycle After the clock enable is asserted the oscillator outputs the sinusoidal samples at a rate of one sample per clock cycle following an initial latency of L clock cycles The exact value of L varies across architectures and parameterizations 4 10 MegaCore Version 8 0 Altera Corporation NCO MegaCore Function User Guide May 2008 Functional Description non single cycle per output architectures the optional phase and frequency modulation inputs need to be valid at the same time as the corresponding phase increment value The values should be sampled every 2 cycles for the two cycle multiplier based architecture and every N cycles for the serial CORDIC architecture where N is the magnitude precision Figure 4 5 shows the timing diagram for a two cycle multiplier based NCO architecture Figure 4 5 Two Cycle Multiplier Based Architecture Timing Diagram clk clken phi inc 346 reset out valid After the clock enable is asserted the oscillator outputs the sinus
9. domain graphs that dynamically display the functionality of the NCO based on your parameter settings A numerically controlled oscillator synthesizes a discrete time discrete valued representation of a sinusoidal waveform Designers typically use NCOs in communication systems In such systems they are used as quadrature carrier generators in I O mixers in which baseband data is modulated onto the orthogonal carriers in one of a variety of ways Figure 1 1 shows an NCO used in a simple modulator system Figure 1 1 Simple Modulator FIR gt Constellation gt Filter Mapper Q cos wt dq IF Signal sin wt FIR D Filter Designers also use NCOs in all digital phase locked loops for carrier synchronization in communications receivers or as standalone frequency shift keying FSK or phase shift keying PSK modulators In these applications the phase or the frequency of the output waveform varies directly according to an input data stream MegaCore Version 8 0 1 3 NCO MegaCore Function User Guide MegaCore Verification Meg aCore Before releasing a version of the NCO MegaCore function Altera runs Verification comprehensive regression tests to verify its quality and correctness First a custom variation of the NCO MegaCore function is created Next Verilog HDL and VHDL IP functional simulation models are exercised by their appropriate testbenches in Model
10. must be greater than or equal to the specified angular precision Phase Dithering digital sinusoidal synthesizers suffer from the effects of finite precision which manifests itself as spurs in the spectral representation of the output sinusoid Because of angular precision limitations the derived phase of the oscillator tends to be periodic in time and contributes to the presence of spurious frequencies You can reduce the noise at these frequencies by introducing a random signal of suitable variance into the derived phase thereby reducing the likelihood of identical values over time Adding noise into the data path raises the overall noise level within the oscillator but tends to reduce the noise localization and can provide significant improvement in SFDR The extent to which you can reduce spur levels is dependent on many factors The likelihood of repetition of derived phase values and resulting spurs for a given angular precision is closely linked to the ratio of the clock frequency to the desired output frequency An integral ratio clearly results in high level spurious frequencies while an irrational relationship is less likely to result in highly correlated noise at harmonic frequencies The Altera NCO MegaCore function allows you to finely tune the variance of the dither sequence for your chosen algorithm specified precision and clock frequency to output frequency ratio and dynamically view the effects on the output spect
11. the requirements of 80 dB SFDR for the four possible output frequencies as shown in Figure A 3 Figure A 3 Output Frequencies Spectral Plot of 9 5 MHz NCO Output Spectral Plot of 13 44 MHz NCO Output E 00 01 00 0 0 DoD 20 40 T 2 60 E E 2 100 100 120 120 140 140 0 1 2 2 4 5 2 D 8 9 10 Frequency Hz x10 Frequency Hz x10 Spectral Plot of 17 28 MHz NCO Output Spectral Plot of 21 12 MHz NCO Output Magnitude dB Magnitude dB Frequency Hz un Frequency Hz A 4 MegaCore Version 8 0 Altera Corporation NCO MegaCore Function User Guide May 2008 Example Designs Figure A 4 shows a segment of the resulting FSK modulated waveform in the time domain Figure A 4 FSK Modulated Waveform x 10 Quaternary FSK Modulator Ouptut Amplitude The generated output frequency for a given phase increment f and frequency modulation increment frm can be calculated using Equations 3 and 6 on page 4 4 The following parameters are specified in the nco design tb m file 299866808 drm 268435456 foe 220MHz 32 32 This parameterization gives the following values for f and frm fj 1536MHz B fry 13 76MHz Altera Corporation MegaCore Version 8 0 A 5 May 2008 NCO MegaCore Function User Guide Example Design 2 A 6 MegaCore
12. 2 18 4 258 5 Note for Table 4 3 1 Special case 9 lt lt 18 amp amp WANT SIN AND COS 2 Latency base latency dither latency frequency modulation pipeline phase modulation pipeline xN for serial CORDIC 3 Dither latency 0 dither disabled or 2 dither enabled 4 Minimum latency assumes N 8 5 Maximum latency assumes N 32 Figure 4 7 shows the timing diagram for a multi channel NCO in the case where the number of channels M is set to 4 The input phase increments for each channel P are interleaved and loaded sequentially Figure 4 7 Multi Channel NCO Timing Diagram clk Au clken phi inc i JR YRYR YR YR XR Y YRXRYRYRYR YR XR YR XR YR 8 reset n out valid fsin D SYSYS amp YS YS S SS SI Sf SS 5 YS f feos_0 YON CY CVC oye CLC NOY CY CY CY lt The phase increment for channel 0 is the first value read in on the rising edge of the clock following the de assertion of reset n assuming clken is asserted followed by the phase increments for the next M 1 channels 4 12 MegaCore Version 8 0 Altera Corporation NCO MegaCore Function User Guide May 2008 Functional Description Signals The output signal out validis asserted when th
13. AX EDA Language VHDL Mi An IP Functional Simulation Model is a cycle accurate VHDL or Verilog HDL model produced by the Quartus software These models allow fast functional simulations of IP using industry standard VHDL and Verilog HDL simulators You may only use these simulation model output files for simulation purposes and expressly notfor synthesis or any other purposes Using these models for synthesis will create a non functional design Generate netlist If you are synthesizing your design with a third party EDA synthesis tool you can generatea netlist for the synthesis tool to estimate timing and resource usage for this megafunction 8 Turn on Generate Simulation Model to create an IP functional model Iz An IP functional simulation model is a cycle accurate VHDL or CAUTION 10 11 Verilog HDL model produced by the Quartus II software Use the simulation models only for simulation and not for synthesis or any other purposes Using these models for synthesis creates a non functional design Choose the required language from the Language list Some third party synthesis tools can use a netlist that contains only the structure of the MegaCore function but not detailed logic to optimize performance of the design that contains the MegaCore function If your synthesis tool supports this feature turn on Generate netlist Click Step 3 Generate in IP
14. HDL and Verilog HDL simulators support for UNIX and Linux operating systems November 2002 2 0 2 e Updated the screen shots made some formatting and organization changes minor wording changes to several sections July 2002 2 0 1 e MegaCore functions now display a single DSP Builder library for OpenCore and OpenCore Plus in the Simulink Library Browser May 2002 2 0 0 e Updated functional description Added DSP Builder OpenCore Plus and licensing information Removed reference designs and replaced with example designs Updated all screen shots Made formatting and organization changes April 2000 1 0 je Version 1 0 of this user guide Altera Corporation May 2008 MegaCore Version 8 0 Info 1 NCO MegaCore Function User Guide How to Contact Altera How to Contact Altera Typographic Conventions For the most up to date information about Altera products refer to the following table ntact Contact 7 Address Technical support Website www altera com support Technical training Website www altera com training Email custrain altera com Product literature Website www altera com literature Non technical support General Email nacomp altera com Software Licensing Email authorization altera com Note to table 1 You can also contact your local Altera sales office or sales representative This document uses the typographic conventions shown in the following t
15. Phase Increment Value 42949673 Real Output Frequency 1 0000000009313226 MHz 0 62500 1 25 1 875 25 3 125 375 4375 50 Frequency x10 Hz 3 2 2 Click the Implementation tab when you are finished setting the general parameters 3 With the Implementation tab selected specify the frequency modulation phase modulation and outputs choose the target device family For some algorithms for example multiplier based you can also make device specific settings such as whether to implement the NCO MegaCore function in logic elements LEs or other hardware The Implementation tab displays the corresponding options available for the selected algorithm in the Parameters tab MegaCore Version 8 0 Altera Corporation NCO MegaCore Function User Guide May 2008 Parameter Settings Figure 3 2 shows the implementation parameter options when you specify the Small ROM or Large ROM algorithm Figure 3 2 Implementation Tab Large ROM Algorithm 6 Parameterize NCO Jeg Parameters Implementation Resource Estimate Frequency Modulation Phase Modulation Ouputs Frequency Modulation Input C Phase Modulation Input Dual Output Q Single Output Device Family Target Magnitude dB 0 20 0 40 0 60 0 80 0 100 0 120 0 140 0 160 0 Stratix III v Number of Channels 1 Frequency Domain Response Time Domain Response 0 0 0 62500 Mult
16. Sim simulators and the results are compared to the output of bit accurate models in the MATLAB software The regression suite covers various parameters such as architecture options frequency modulation phase modulation and precision Figure 1 2 shows the regression flow Figure 1 2 Regression Flow Parameter Per Sweep Script Y T NCO Compiler Eod Wizard Y MATLAB Verilog HDL VHDL y y y Output Output Output Output File File File File Performance This section shows typical expected performance for a NCO MegaCore function using the Quartus II software version 8 0 and a target fmax set and Resou rce to IGHz with Cyclone III and Stratix III devices Utilization NEN LS The performance for Stratix IV devices is similar to Stratix III devices Cyclone III devices use combinational look up tables LUTs and logic registers Stratix III devices use combinational adaptive look up tables ALUTS and logic registers It may be possible to significantly reduce memory utilization by setting a lower target fmax 1 4 MegaCore Version 8 0 Altera Corporation NCO MegaCore Function User Guide May 2008 About This MegaCore Function Table 1 3 shows performance figures for Cyclone III devices
17. Toolbench also sets the value of the phase increment in all testbenches and vector source files it generates Similarly the generated output frequency fry for a given frequency modulation increment is determined by the equation orm X Hz where F is the modulator resolution The angular precision of an NCO is the phase angle precision before the polar to cartesian transformation The magnitude precision is the precision to which the sine and or cosine of that phase angle can be represented The effects of reduction or augmentation of the angular magnitude accumulator precision on the synthesized waveform vary across NCO architectures and for different f f j ratios MegaCore Version 8 0 Altera Corporation NCO MegaCore Function User Guide May 2008 Functional Description Altera Corporation May 2008 You can view these effects in the NCO time and frequency domain graphs as you change the NCO MegaCore function parameters Architectures The NCO MegaCore function supports large ROM small ROM CORDIC and multiplier based architectures Large ROM Architecture Use the large ROM architecture if your design requires very high speed sinusoidal waveforms and your design can use large quantities of internal memory In this architecture the ROM stores the full 360 degrees of both the sine and cosine waveforms The output of the phase accumulator addresses the ROM Because the internal memory hold
18. Toolbench to generate your MegaCore function variation and supporting files The generation phase may take several minutes to complete The generation progress and status is displayed in a report window MegaCore Version 8 0 2 5 NCO MegaCore Function User Guide MegaWizard Plug In Manager Flow Figure 2 5 shows the generation report Figure 2 5 Generation Report NCO MegaCore function EL Report NCO p Memes m File Summary The MegaVVizard interface is creating the following files in the output directory MegaCore function variation file which defines a VHDL top level description of the custom MegaCore function Instantiate the entity defined by this file inside of your design Include this file when compiling your design in the Quartus Il software A VHDL component declaration for the MegaCore function variation Add ocn cmp ithe contents of this file to any VHDL architecture that instantiates the MegaCore function CHEN bst Quartus I symbol file for the MegaCore function variation You can use this file in the Quartus Il block 7 eE editor ocn VHDL functional simulation mod IP functional simulation model ES NCO synthesizable netlist This file is required for Quartus Il synthesis It will be added to your Quartus Il project ocn vhd Testbench vho_msim tcl Eo rc TCL Script to run the VHDL IP Functional Simulation model and
19. Version 8 0 Altera Corporation NCO MegaCore Function User Guide May 2008 Additional Information Revision Histo ry The following table displays the revision history for this user guide Date Version Changes Made May 2008 8 0 e Separated the design flows and parameter setting sections e Full support for Cyclone III e Preliminary support for Stratix IV October 2007 7 2 e Updated NCO block diagram e Added multi channel description and timing diagram e Added latency table e Updated GUI screenshots e Full support for Arria GX May 2007 7 1 e Added 32 bit precision for angle amp magnitude e Preliminary support for Arria M GX e Full support for Stratix and HardCopy II devices December 2006 7 0 e Preliminary support for Cyclone III December 2006 6 1 e Preliminary support for Stratix e Minor updates throughout the user guide April 2006 2 3 1 Maintenance release updated screen shots and format October 2005 2 8 0 e Maintenance release updated screen shots and format e Preliminary support for HardCopy Il HardCopy Stratix and Stratix Il GX e Removed Mercury and Excalibur device support June 2004 2 2 0 e Added Cyclone II support e Updated functional description tutorial instructions and screenshots February 2004 2 1 0 e Enhancements include support for Stratix Il devices support for easy to use IP Toolbench IP functional simulation models for use in Altera supported V
20. able Visual Cue Bold Type with Initial Capital Letters Meaning Command names dialog box titles checkbox options and dialog box options are shown in bold initial capital letters Example Save As dialog box bold type External timing parameters directory names project names disk drive names filenames filename extensions and software utility names are shown in bold type Examples fmax qdesigns directory d drive chiptrip gdf file Italic Type with Initial Capital Letters Document titles are shown in italic type with initial capital letters Example AN 75 High Speed Board Design Italic type Internal timing parameters and variables are shown in italic type Examples tpa 1 Variable names are enclosed angle brackets lt gt and shown in italic type Example file name gt project gt file Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters Examples Delete key the Options menu Subheading Title References to sections within a document and titles of on line help topics are shown in quotation marks Example Typographic Conventions Info 2 MegaCore Version 8 0 Altera Corporation NCO MegaCore Function User Guide May 2008 Additional Information Visual Cue Courier type Meaning Signal and port names are shown in lowercase Courier type Examples data1 tdi input Active
21. alue is 24 for small and large ROM algorithms 32 for CORDIC and multiplier based algorithms Table 3 2 shows the parameters that can be set in the Implementation page Table 3 2 NCO MegaCore Function Implementation Page Part 1 of 2 Parameter Value Description Frequency On or Off You can optionally enable the frequency modulation input Modulation input Modulator 4 64 Choose the modulator resolution for the frequency modulation Resolution Default 32 input Modulator Pipeline 1 2 Choose the modulator pipeline level for the frequency Level Default 1 modulation input Phase Modulation On or Off You can optionally enable the phase modulation input Input Modulator Precision 4 32 Choose the modulator precision for the phase modulation input Default 16 Altera Corporation May 2008 MegaCore Version 8 0 3 7 NCO MegaCore Function User Guide Parameter Descriptions Table 3 2 NCO MegaCore Function Implementation Page Part 2 of 2 Parameter Modulator Pipeline Level Value 1 2 Default 1 Description Choose the modulator pipeline level for the phase modulation input Outputs Dual Output Single Output Choose whether to use a dual or single output Device Family Target Stratix IV Stratix Stratix 1 Stratix Il GX Arria GX Stratix Stratix GX Cyclone Ill Cyclone II Cyclone Displays the target device family The target device family
22. d click Run EDA RTL Simulation Refer to Simulating Altera IP Using the Quartus II NativeLink Feature in volume 3 of the Quartus II Handbook for more information MegaCore Version 8 0 2 9 NCO MegaCore Function User Guide Compile the Design and Program a Device Compile the Design and Program a Device 2 10 Simulating the Design in ModelSim To simulate your design with the MegaWizard generated ModelSim Tcl script change your ModelSim working directory to the project directory specified in Selecting the MegaCore Function on page 2 3 and run the MegaWizard generated Tcl script If you selected VHDL as your functional simulation language run the Tcl script lt variation_name gt _vho_msim tcl Ifyou selected Verilog HDL as your functional simulation language run the Tcl script variation name vo msim tcl gt The Tcl script creates a ModelSim project maps the libraries compiles the top level design and associated testbench and then outputs the simulation results to the waveform viewer You can use the Quartus II software to compile your design To compile your design follow these steps 1 Ifyouare using the Quartus II software to synthesize your design skip to Step 2 If you are using a third party synthesis tool to synthesize your design follow these steps a Setablack box attribute for your MegaCore function custom variation before you synthesize the design Refer to Quartus II Help for instruc
23. diate frequency IF modulator The design targets the Altera Design 1 EP2S15F484C3 Stratix II device The top level design file is install path gt ip nco example_designs design1 design1 bdf The oscillator meets the following specifications SFDR 110 dB Output Sample Rate 300 MSPS Output Frequency 21 MHz Frequency Resolution 0 07 Hz To meet these requirements the design uses the following NCO MegaCore function settings Altera Corporation May 2008 Multiplier based algorithn By using the dedicated multiplier circuitry in Stratix devices the NCO architectures that implement this algorithm can provide very high performance Clock rate of 300 MHz and 32 bit phase accumulator precision These settings yield a frequency resolution of 70 mHz Angular and magnitude precision These settings are critical to meet the SFDR requirement while minimizing the required device resources Setting the angular precision to 17 bits and the magnitude precision to 18 bits results in the spectrum shown in Figure A 1 on page A 2 Dither level The angular and magnitude precision settings described above yield an SFDR of approximately 102 8 dB which is clearly not sufficient to meet the specification Using the dither control in the NCO MegaCore function the variance of the dithering sequence is increased until the trade off point between spur reduction and noise level augmentation is reached for these particular clock freq
24. e tethered timeout value is indefinite The reset n signal is forced low when the hardware evaluation time expires This keeps the NCO MegaCore function permanently in its reset state Altera Corporation MegaCore Version 8 0 1 7 May 2008 NCO MegaCore Function User Guide Installation and Licensing 1 8 MegaCore Version 8 0 Altera Corporation NCO MegaCore Function User Guide May 2008 N D TE SYN 2 Getting Started Design Flows DSP Builder Flow Altera Corporation May 2008 The NCO MegaCore function supports the following design flows DSP Builder Use this flow if you want to create DSP Builder model that includes a NCO MegaCore function variation MegaWizard Plug In Manager Use this flow if you would like to create a NCO MegaCore function variation that you can instantiate manually in your design This chapter describes how you can use a NCO MegaCore function in each of these flows The parameterization is the same in each flow and is described in Chapter 3 Parameter Settings After parameterizing and simulating a design in either of these flows you can compile the completed design in the Quartus II software Altera s DSP Builder product shortens digital signal processing DSP design cycles by helping you create the hardware representation of a DSP design in an algorithm friendly development environment DSP Builder integrates the algorithm development simulation and verification capabilities of
25. e a small ROM implementation is more likely to have periodic value repetition the resulting waveform s SFDR is generally lower than that of the large ROM architecture However you can often mitigate this reduction in SFDR by using phase dithering See Phase Dithering on page 4 9 for more information on this option CORDIC Architecture The CORDIC algorithm which can calculate trigonometric functions such as sine and cosine provides a high performance solution for very high precision oscillators in systems where internal memory is at a premium The CORDIC algorithm is based on the concept of complex phasor rotation by multiplication of the phase angle by successively smaller constants In digital hardware the multiplication is by powers of two only Therefore the algorithm can be implemented efficiently by a series of simple binary shift and additions subtractions In an NCO the CORDIC algorithm computes the sine and cosine of an input phase value by iteratively shifting the phase angle to approximate the cartesian coordinate values for the input angle At the end of the CORDIC iteration the x and y coordinates for a given angle represent the cosine and sine of that angle respectively See Figure 4 3 on page 4 7 4 6 MegaCore Version 8 0 Altera Corporation NCO MegaCore Function User Guide May 2008 Functional Description Figure 4 3 CORDIC Rotation for Sine amp Cosine Calculation A y With the NCO MegaCor
26. e first valid sine and cosine outputs for channel 0 So respectively are available The output values 5 and C corresponding to channels 1 through M 1 are output sequentially by the NCO The outputs are interleaved so that a new output sample for channel k is available every M cycles Avalon Streaming Interface The Avalon Streaming Avalon ST interface is an evolution of the Atlantic interface The Avalon ST interface defines a standard flexible and modular protocol for data transfers from a source interface to a sink interface and simplifies the process of controlling the flow of data in a datapath Avalon ST interface signals can describe traditional streaming interfaces supporting a single stream of data without knowledge of channels or packet boundaries Such interfaces typically contain data ready and valid signals The NCO MegaCore function is an Avalon ST source and does not support backpressure For more information on the Avalon ST interface including integration with other Avalon ST components which may support backpressure refer to the Avalon Interface Specification The NCO MegaCore function supports the input and output signals shown in Table 4 4 Table 4 4 NCO MegaCore FunctionSignals Signal Direction Description clk Input Clock clken Input Active high clock enable freq mod i F 1 0 Input Optional frequency modulation input You can specify the modulator reso
27. e function you can choose between parallel unrolled and serial iterative CORDIC architectures You an use the parallel CORDIC architecture to create a very high performance high precision oscillator implemented entirely in logic elements with a throughput of one output sample per clock cycle With this architecture there is a new output value every clock cycle The serial CORDIC architecture uses fewer resources than the parallel CORDIC architecture However its throughput is reduced by a factor equal to the magnitude precision For example if you select a magnitude precision of N bits in the NCO MegaCore function the output sample rate and the Nyquist frequency is reduced by a factor of N This architecture is implemented entirely in logic elements and is useful if your design requires low frequency high precision waveforms With this architecture the adder stages are stored internally and a new output value is produced every N clock cycles s Refer to Implementation Tab CORDIC Algorithm on page 3 4 Altera Corporation MegaCore Version 8 0 4 7 May 2008 NCO MegaCore Function User Guide Functional Description Multiplier Based Architecture The multiplier based architecture uses multipliers to reduce memory usage You can choose to implement the multipliers in either Logic elements Cyclone or combinational ALUTS Stratix W Dedicated multiplier circuitry for example dedicated DSP blocks in dev
28. ed algorithm 3 6 NCO MegaCore Function User Guide MegaCore Version 8 0 Altera Corporation May 2008 Parameter Settings Table 3 1 NCO MegaCore Function Parameters Page Part 2 of 2 Parameter Value Description Phase Accumulator 4 64 Choose the required phase accumulator precision Precision Default 32 Note 1 Angular Resolution 4 24 or 32 Choose the required angular resolution Note 2 Default 16 Magnitude Precision 10 32 Choose the required magnitude precision Default 18 Implement Phase On or Off Turn on to implement phase dithering Dithering Dither Level Min Max When phase dithering is enabled you can use the slider control to adjust the dither level between its minimum and maximum values Clock Rate 1 999 MHz kHz Hz mHz You can choose the clock rate using units of MegaHertz Default 100 MHz kiloHertz Hertz or milliHertz Desired Output Frequency 1 999 MHz kHz Hz mHz Default 1 MHz You can choose the desired output frequency using units of MegaHertz kiloHertz Hertz or milliHertz Phase Increment Value Displays the phase increment value calculated from the clock rate and desired output frequency Real Output Frequency Note for Table 3 1 1 Q Displays the calculated value of the real output frequency The phase accumulator precision must be greater than or equal to the specified angular resolution The maximum v
29. for Table 3 3 Number of 9 bit DSP Elements Displays the number of 9 bit DSP elements 1 Stratix GX Stratix Cyclone III Cyclone II and Cyclone devices use LEs all other devices use ALUTs 2 Stratix IV Stratix III and Cyclone III devices use M9K RAM blocks all other devices use M4K blocks 3 8 MegaCore Version 8 0 NCO MegaCore Function User Guide Altera Corporation May 2008 N D PYA 4 Functional Description Numerically Controlled Oscillators Altera Corporation May 2008 A numerically controlled oscillator NCO synthesizes a discrete time discrete valued representation of a sinusoidal waveform There are many ways to synthesize a digital sinusoid For example a popular method is to accumulate phase increments to generate an angular position on the unit circle and then use the accumulated phase value to address a ROM look up table that performs the polar to cartesian transformation You can reduce the ROM size by using multipliers Multipliers provide an exponential decrease in memory usage for a given precision but require more logic Another method uses the coordinate rotation digital computer CORDIC algorithm to determine given a phase rotation the sine and cosine values iteratively The CORDIC algorithm takes an accumulated phase value as input and then determines the cartesian coordinates of that angle by a series of binary shifts and compares For more information about the CORDIC a
30. function variation in your DSP Builder model For more information about the DSP Builder flow refer to the Using MegaCore Functions chapter in the DSP Builder User Guide When you are using the DSP Builder flow device selection simulation Quartus II compilation and device programming are all controlled within the DSP Builder environment DSP Builder supports integration with SOPC Builder using Avalon Memory Mapped Avalon MM master slave and Avalon Streaming Avalon ST source sink interfaces Refer to the Avalon Interface Specification for more information about these interface types Meg aWiz a rd The MegaWizard Plug in Manager flow allows you to customize a NCO MegaCore function and manually integrate the MegaCore function Plug In Manager variation into a Quartus II design Flow Follow the steps below to use the MegaWizard Plug in Manager flow 1 Create a new project using the New Project Wizard available from the File menu in the Quartus II software 2 Launch MegaWizard Plug in Manager from the Tools menu and choose the option to create a new custom megafunction variation Figure 2 1 on page 2 3 2 2 MegaCore Version 8 0 Altera Corporation NCO MegaCore Function User Guide May 2008 Getting Started Figure 2 1 MegaWizard Plug In Manager MegaWizard Plug In Manager page 1 i Pu The MegaWizard Plug In Manager helps you create or modify design files that contain c
31. gaCore Function User Guide N D TE SYN Contents Chapter 1 About This MegaCore Function Release Information Device Family Support Features General Description MegaCore Verification Performance and Resource Utilization sese nennen ennt nns 1 4 Installation and Licensing itinere itte ite OpenCore Plus Evaluation ET Plus Time Out etienne rre eren inten ttc tone eea EE o 1 7 Chapter 2 Getting Started psp DSP Builder Flow MegaWizard Plug In Manager Flow rrr teet rettet bine repete terere tita Generated Simulate the Design Simulating the Design in ModelSim Compile the Design and Program a Device c ccscssssssesesseesesessesssesesesssesesseasssssssesesssesessssseseseasens 2 10 Chapter 3 Parameter Settings Setting Parameters RE M 3 1 Parameter Descriptions nee de URN GER SERE hele esL REESE e ERREUR NER RSEN ERES 3 6 Chapter 4 Functional Description Numerically Controlled Oscillators seen 4 1 Spectral Purity Mt Maximum Output Frequency 4 2 Functional Description ssrin 4 3 Architectures Erequency Modulation 9 ein eee neni ie er SER EUH EET Ha E EEEE Ei 4 8 Phase Modulation
32. generated VHDL testbench in the Modelsim simulation software ocn wave Jocnwavedo ModelsmWaveformFle Waveform File ocn modem vete m file describing a Matlab bit accurate model veta Testbench Jocn_sin_t hex rte Hex format ROM initialization file ocn cos t nex rte Hex format ROM initialization file rte Hex format ROM initialization file cos_c hex a x Hex format ROM initialization file pmmusvectorFie Vector File A timing and resource estimation netlist for use with some third party s synthesis tools Contains Quartus Il project information for your MegaCore function variation ocn cnm The The MegaCore function reporte function report file MegaCore Function Generation Successful Cancel 2 6 MegaCore Version 8 0 Altera Corporation NCO MegaCore Function User Guide May 2008 Getting Started Generated Files Table 2 1 describes the generated files and other files that may be in your project directory The names and types of files specified in the report vary based on whether you created your design with VHDL or Verilog HDL Table 2 1 IP Toolbench Files Part 1 of 2 Filename Note 1 Note 2 entity name v Description Generated synthesizable netlist This file is required for Quartus Il synthesis It will be added to your Quartus II project variation name v
33. ho msim tcl variation name msim tcl ModelSim TCL Script that runs the VHDL or Verilog HDL IP functional simulation model and generated VHDL or Verilog testbench in the ModelSim simulation software variation name tb v or variation name tb vhd A VHDL or Verilog HDL testbench file for the MegaCore function variation The VHDL file is generated when a VHDL top level has been chosen or the Verilog HDL file when a Verilog HDL top level has been chosen variation name bsf Quartus 11 symbol file for the MegaCore function variation You can use this file in the Quartus II block diagram editor variation name cmp A VHDL component declaration file for the MegaCore function variation Add the contents of this file to any VHDL architecture that instantiates the MegaCore function variation name html MegaCore function report file variation name dip A MegaCore function variation file which defines a VHDL or Verilog HDL top level description of the custom MegaCore function Instantiate the entity defined by this file inside of your design Include this file when compiling your design in the Quartus II software variation name gt vec Quartus II Vector File variation name vhd v A MegaCore function variation file which defines a Verilog HDL or VHDL top level description of the custom MegaCore function Instantiate the entity defined by this file inside your des
34. i Channel NCO 1 25 1 875 25 3 125 3 75 4 375 5 0 Frequency x10 Hz Altera Corporation May 2008 Refer to Frequency Modulation on page 4 8 and Phase Modulation on page 4 9 for more information about these parameter options Figure 3 3 shows implementation parameter options when the CORDIC algorithm is specified With the CORDIC algorithm you can choose a parallel or serial CORDIC implementation MegaCore Version 8 0 3 3 NCO MegaCore Function User Guide Setting Parameters Figure 3 3 Implementation Tab CORDIC Algorithm 3 Parameterize NCO Ja Parameters Implementation Resource Estimate Frequency Modulation Phase Modulation Ouputs C Phase Modulation Input Dual Output O Single Output HH Device Family Multi Channel NCO Target Stratix IIl M Number of Channels 1 CORDIC Implementation Parallel One Output per Clock Cycle Serial One Output per 18 Clock Cycles Frequency Domain Response Time Domain Response Magnitude dB 0 20 0 40 0 60 0 80 0 100 0 120 0 140 0 160 0 0 0 0 62500 1 25 1 875 25 3 125 3 75 4375 5 0 Frequency x10 Hz Figure 3 4 on page 3 5 shows the implementation parameter options when you specify the Multiplier Based algorithm If you target the Stratix IV Stratix III Stratix II Stratix GX or Stratix device families you can choose whether to implement the multiplier ba
35. ible with the Avalon Interface Specification Easy to use IP Toolbench interface IP functional simulation models for use in Altera supported VHDL and Verilog HDL simulators Supports multiple NCO architectures e Multiplier based implementation using DSP blocks or logic elements LEs single cycle and multi cycle e Parallel or serial CORDIC based implementation e ROM based implementation using embedded array blocks EABs embedded system blocks ESBs or external ROM Supports single or dual outputs sine cosine Allows variable width frequency modulation input Allows variable width phase modulation input User defined frequency resolution angular precision and magnitude precision Generates simulation files and architecture specific testbenches e VHDL testbench e Verilog HDL testbench MegaCore Version 8 0 Altera Corporation NCO MegaCore Function User Guide May 2008 About This MegaCore Function General Description Altera Corporation May 2008 e MATLAB model and testbench e Quartus II Vector Files Includes dual output oscillator and quaternary frequency shift keying OFSK modulator example designs The Altera NCO MegaCore function generates numerically controlled oscillators NCOsSs customized for Altera devices You can use the IP Toolbench interface to implement a variety of NCO architectures including ROM based CORDIC based and multiplier based IP Toolbench also includes time and frequency
36. ice families that support this feature Stratix III Stratix II Stratix GX Stratix or Arria GX devices Le When you specify a dual output multiplier based NCO the MegaCore function provides an option to output a sample every two clock cycles This setting reduces the throughput by a factor of two and halves the resources required by the waveform generation unit Refer to Implementation Tab Multiplier Based Algorithm on page 3 5 Table 4 2 on page 4 8 summarizes the advantages of each algorithm Table 4 2 Architecture Comparison Architecture Advantages Large ROM Good for high speed and when a large quantity of internal memory is available Gives the highest spectral purity and uses the fewest logic elements for a given parameterization Small ROM Good for high output frequencies with reduced internal memory usage when a lower SFDR is acceptable CORDIC High performance solution when internal memory is at a premium The serial CORDIC architecture uses fewer resources than parallel although the throughput is reduced Multiplier Based Reduced memory usage by implementing multipliers in logic elements or dedicated circuitry Frequency Modulation In the NCO MegaCore function you can add an optional frequency modulator to your custom NCO variation You can use the frequency modulator to vary the oscillator output frequency about a center frequency set by the input phase increment This option is useful f
37. ign Include this file when compiling your design in the Quartus Il software variation name vho or variation name vo VHDL or Verilog HDL IP functional simulation model variation name bb v Verilog HDL black box file for the MegaCore function variation Use this file when using a third party EDA tool to synthesize your design variation name cos c hex variation name cos f hex variation name sin c hex variation name sin f hex Intel Hex format ROM initialization files variation name gb v A timing and resource estimation netlist for use in some third party synthesis tools variation name model m MATLAB m file describing a MATLAB bit accurate model Altera Corporation May 2008 MegaCore Version 8 0 2 7 NCO MegaCore Function User Guide MegaWizard Plug In Manager Flow Table 2 1 IP Toolbench Files Part 2 of 2 Filename Note 1 Note 2 variation name nativelink tcl Description A Tcl script that can be used to assign NativeLink simulation testbench settings to the Quartus II project variation name tb m variation name wave do MATLAB testbench file ModelSim Waveform file Notes to Table 2 1 1 Q variation name gt is a prefix variation name supplied automatically by IP Toolbench The entity name prefix is added automatically The VHDL code for each MegaCore instance is generated dyna
38. ion Generate time limited device programming files for designs that include megafunctions Program a device and verify your design in hardware You only need to purchase a license for the NCO MegaCore function when you are completely satisfied with its functionality and performance and want to take your design to production After you purchase a license you can request a license file from the Altera website at www altera com licensing and install it on your computer When you request a license file Altera emails you a license dat file If you do not have Internet access contact your local Altera representative D For more information on OpenCore Plus hardware evaluation refer to AN 320 OpenCore Plus Evaluation of Megafunctions OpenCore Plus Time Out Behavior OpenCore Plus hardware evaluation supports the following two operation modes Untethered the design runs for a limited time Tethered Trequires a connection between your board and the host computer If tethered mode is supported by all megafunctions in a design the device can operate for a longer time or indefinitely megafunctions in a device time out simultaneously when the most restrictive evaluation time is reached If there is more than one megafunction in a design a specific megafunction s time out behavior may be masked by the time out behavior of the other megafunctions The untethered timeout for the NCO MegaCore function is 1 hour th
39. ion of each MegaCore function The MegaCore IP Library Release Notes and Errata report any exceptions to this verification Altera does not verify compilation with MegaCore function versions older than one release MegaCore functions provide either full or preliminary support for target Altera device families as described below Full support means the MegaCore function meets all functional and timing requirements for the device family and may be used in production designs Preliminary support means the MegaCore function meets all functional requirements but may still be undergoing timing analysis for the device family it may be used in production designs with caution MegaCore Version 8 0 1 1 NCO MegaCore Function User Guide Features Table 1 2 shows the level of support offered by the NCO MegaCore function to each Altera device family Table 1 2 Device Family Support Arria GX Full Device Family Support Level Cyclone Full Cyclone II Full Cyclone III Full HardCopy II Full Stratix Full Stratix II Full Stratix GX Full Stratix Preliminary Stratix IV Preliminary Stratix GX Full Other device families No support Featu res The Altera NCO MegaCore function implements a numerically controlled oscillator and supports the following features 1 2 Supports 32 bit precision for angle and magnitude The source interface is compat
40. is pre selected by the value specified in the Quartus Il or DSP Builder software The HDL that is generated for your MegaCore function variation may be incorrect if you change the device family target in IP Toolbench Number of Channels 1 8 Default 1 Choose the number of channels when you want to implement a multi channel NCO CORDIC Implementation Parallel Serial When the CORDIC generation algorithm is selected on the Parameters page you can choose to use a parallel one output per clock cycle or serial one output per 18 clock cycles implementation Multiplier Based Architecture Logic Elements Dedicated Multipliers When the multiplier based algorithm is selected on the Parameters page you can choose whether to use logic elements or dedicated multipliers and choose the number of clock cycles per output Clock Cycles Per Output 1 2 Default 1 When the multiplier based algorithm is selected on the Parameters page you can choose 1 or 2 clock cycles per output Table 3 3 shows the parameters that are displayed in the Resource Estimate page Table 3 3 NCO MegaCore Function Resource Estimate Page Parameter Number of ALUTs LEs Displays the number of adaptive look up tables or logic elements Note 7 Number of Memory Bits Displays the number of memory bits Number of M9Ks M4Ks Displays the number of or M4K RAM blocks Note 2 Note
41. lgorithm refer to A Survey of CORDIC Algorithms for FPGAs see Reference 1 on page 4 14 In all methods the frequency at which the phase increment accumulates and the size of that input phase increment relative to the maximum size of the accumulator directly determines the normalized sinusoidal frequency see Equation 2 on page 4 3 When deciding which NCO implementation to use in programmable logic you should consider several parameters including the spectral purity frequency resolution performance throughput and required device resources Often you need to consider the trade offs between some or all of these parameters Spectral Purity Typically the spectral purity of an oscillator is measured by its signal to noise ratio SNR and its spurious free dynamic range SFDR The SNR of a digitally synthesized sinusoid is a ratio of the signal power relative to the unavoidable quantization noise inherent in its discrete valued representation SNR is a direct result of the finite precision with which NCO represents the output sine and cosine waveforms Increasing the output precision results in an increased SNR MegaCore Version 8 0 4 1 NCO MegaCore Function User Guide Numerically Controlled Oscillators 1 4 2 The following equation estimates the SNR of a given sinusoid with output precision b SNR 6b 1 8 dB Each additional bit of output precision leads to an additional 6 dB in SNR The SFDR of a digital sin
42. low signals are denoted by suffix n e g reset n Anything that must be typed exactly as it appears is shown in Courier type For example c qdesigns tutorial chiptrip gdf Also sections of an actual file such as a Report File references to parts of files for example the VHDL keyword BEGIN as well as logic function names for example TRI are shown in Courier 1 2 8 and Numbered steps are used in a list of items when the sequence of the items is a b C etc important such as the steps listed in a procedure Bullets are used a list of items when the sequence the items is not important v The checkmark indicates a procedure that consists of one step only gt The hand points to information that requires special attention A The caution calls attention to a condition that could damage the product or design CAUTION and should be read prior to starting or continuing with the procedure or process The warning calls attention to a condition that could cause injury to the user and WARNING should be read prior to starting or continuing the procedure or processes The angled arrow indicates you should press the Enter key ET The feet direct you to more information on a particular topic Altera Corporation May 2008 MegaCore Version 8 0 Info 3 NCO MegaCore Function User Guide Typographic Conventions Info 4 MegaCore Version 8 0 Altera Corporation NCO MegaCore Fu
43. ls refer to the Simulating Altera IP in Third Party Simulation Tools chapter in volume 3 of the Quartus II Handbook Simulating in Third Party Simulation Tools Using NativeLink You can perform a simulation in a third party simulation tool from within the Quartus II software using NativeLink The Tcl script file variation name nativelink tcl can be used to assign default NativeLink testbench settings to the Quartus II project To perform a simulation in the Quartus II software using NativeLink perform the following steps 1 Create a custom MegaCore function variation as described earlier in this chapter but ensure you specify your variation name to match the Quartus II project name 2 Check that the absolute path to your third party EDA tool is set in the Options page under the Tools menu in the Quartus II software 3 Onthe Processing menu point to Start and click Start Analysis amp Elaboration 4 Onthe Tools menu click Tcl scripts Select the Tcl script variation name nativelink tcl and click Run Check for a message confirming that the Tcl script was successfully loaded 5 Onthe Assignments menu click Settings expand EDA Tool Settings and select Simulation Select a simulator under Tool name then in NativeLink Settings select Compile test bench and click Test Benches Confirm that appropriate testbench settings have been applied to the Quartus II project 6 Onthe Tools menu point to EDA Simulation Tool an
44. lution F in IP Toolbench phase mod i P 1 0 Input Optional phase modulation input You can specify the modulator precision Pin IP Toolbench phi inc i A 1 0 Input Input phase increment You can specify the accumulator precision A in IP Toolbench reset n Input Active low reset fcos o M 1 0 Output Optional output cosine value when dual output is selected You can specify the magnitude precision M in IP Toolbench Altera Corporation May 2008 MegaCore Version 8 0 4 13 NCO MegaCore Function User Guide References fsin o M 1 0 Output Output sine value You can specify the magnitude precision M in IP Toolbench out valid Output Data valid signal Asserted by the MegaCore function when there is valid data to output References 4 14 Altera application notes white papers and user guides providing more detailed explanations of how to effectively design with MegaCore functions and the Quartus II software are available at the Altera web site www altera com Refer also to the following references 1 Andraka Ray A Survey of CORDIC Algorithms for FPGAs FPGA 98 Proceedings of the ACM SIGDA Sixth International Symposium on Field Programmable Gate Arrays MegaCore Version 8 0 Altera Corporation NCO MegaCore Function User Guide May 2008 N DTE RYA Appendix A Example Designs Exa mp le Example design 1 is a high precision dual output oscillator for use in an interme
45. mically when you click Finish so that the entity name gt is different for every instance It is generated from the variation name by appending st The generation report also lists the MegaCore function variation signals see Figure 2 6 D For a full description of the signals supported on external ports for your MegaCore function variation refer to Table 4 4 on page 4 13 Figure 2 6 Port Lists in the Generation Report Q Generation NCO Woe MegaCore Function Variation File Ports OUTPUT 18 OUTPUT 18 p eme MegaCore Function Generation Successful 12 2 8 NCO MegaCore Function User Guide May 2008 After you review the generation report click Exit to close IP Toolbench Then click Yes on the Quartus II IP Files prompt to add the qip file describing your custom MegaCore function variation to the current Quartus II project MegaCore Version 8 0 Altera Corporation Getting Started Altera Corporation May 2008 Simulate the Design To simulate your design use the IP functional simulation models generated by IP Toolbench The IP functional simulation model is either a vo or vho file depending on the output language you specified Compile the vo or vho file in your simulation environment to perform functional simulation of your custom variation of the MegaCore function For more information on IP functional simulation mode
46. nction User Guide May 2008
47. oidal samples at a rate of one sample for every two clock cycles following an initial latency of L clock cycles The exact value of L depends on the parameters that you set Figure 4 6 shows the timing diagram for a serial CORDIC NCO architecture Figure 4 6 Serial CORDIC Timing Diagram clk clken phi inc i reset n out valid fsin 0 E fcos 0 s Note that the sin 0 and fcos 0 values can change while out valid is low After the clock enable is asserted the oscillator outputs sinusoidal samples at a rate of one sample per N clock cycles where N is the magnitude precision set in the NCO MegaCore function Figure 4 6 shows the case where N 8 There is also an initial latency of L clock cycles the exact value of L depends on the parameters that you set Altera Corporation MegaCore Version 8 0 4 11 May 2008 NCO MegaCore Function User Guide Functional Description Table 4 3 shows typical latency values for the different architectures Table 4 3 Latency Values Latency 2 3 Architecture Variation Base Minimum Maximum Small ROM all 7 7 13 Large ROM all 4 4 10 Multiplier Based Throughput 1 Logic cells 11 11 17 Multiplier Based Throughput 1 Dedicated Special case 7 8 8 14 Multiplier Based Throughput 1 Dedicated Not special case 10 10 16 Multiplier Based Throughput 1 2 15 15 26 CORDIC Parallel 2N 4 20 4 74 5 CORDIC Serial CORDIC 2N
48. or applications in which the output frequency is tuned relative to a free running frequency for example in all digital phase lock loops You can also use the frequency modulation input to switch the output frequency directly for example to implement frequency shift keying FSK modulators like the quaternary FSK modulator in Example Design 2 on page A 3 4 8 MegaCore Version 8 0 Altera Corporation NCO MegaCore Function User Guide May 2008 Functional Description Altera Corporation May 2008 You can set the frequency modulation resolution input in the NCO MegaCore function The specified value must be less than or equal to the phase accumulator precision The NCO MegaCore function also provides an option to increase the modulator pipeline level however the effect of the increase on the performance of the NCO MegaCore function varies across NCO architectures and variations Phase Modulation You can use the NCO MegaCore function to add an optional phase modulator to your MegaCore function variation allowing dynamic phase shifting of the NCO output waveforms This option is particularly useful if you want an initial phase offset in the output sinusoid You can also use the option to implement efficient phase shift keying PSK modulators in which the input to the phase modulator varies according to a data stream You set the resolution and pipeline level of the phase modulator in the NCO MegaCore function The input resolution
49. rum graphically See Example Design 1 on page A 1 for an example using phase dithering and its effect on the spectrum of the output signal MegaCore Version 8 0 4 9 NCO MegaCore Function User Guide Functional Description Multi Channel NCOs The NCO MegaCore function allows you to implement multi channel NCOs This allows for multiple sinusoids of independent frequency and phase to be generated at a very low cost in additional resources The resulting waveforms have an output sample rate of fai M where M is the number of channels You can select 1 to 8 channels Multi channel implementations are available for all single cycle generation algorithms The input phase increment frequency modulation value and phase modulation input are input sequentially to the NCO with the input values corresponding to channel 0 first and channel M 1 last The inputs to channel 0 should be input on the rising clock edge immediately following the de assertion of the NCO reset On the output side the first output sample for channel 0 is output concurrent with the assertion of out valid and the remaining outputs for channels 1 to M 1 are output sequentially See Multi Channel NCO Timing Diagram on page 4 12 for details of how the data is provided to and received from a multi channel NCO If a multi channel implementation is selected the NCO MegaCore function generates VHDL and Verilog test benches that time division multiplex the inputs into
50. s all possible output values for a given angular and magnitude precision the generated waveform has the highest spectral purity for that parameter set assuming no dithering The large ROM architecture also uses the fewest logic elements LEs for a given set of precision parameters Small ROM Architecture If low LE usage and high output frequency are a high priority for your system use the small ROM architecture to reduce your internal memory usage In a small ROM architecture the device memory only stores 45 degrees of the sine and cosine waveforms other output values are derived from these values based on the position of the rotating phasor on the unit circle as shown in Table 4 1 and Table 4 2 Table 4 1 Derivation of Output Values Position in Unit Circle Range for Phase x sin x cos x 1 0 lt x lt 7 4 sin x cos x 2 4 lt x lt 1 2 4 sin r 2 x 3 2 lt lt 37 4 2 sin x 1 2 4 31 4 x n cos x x 5 lt X lt 51 4 6 57 4 lt lt 31 2 cos 37 2 x sin 37 2 x 7 2 lt x lt 71 4 cos x 37 2 3 7 2 8 77 4 lt X lt 2t sin 27 x 5 2 MegaCore Version 8 0 4 5 NCO MegaCore Function User Guide Functional Description Figure 4 2 Derivation of Output Values 1 5 0 5 0 5 Becaus
51. sed algorithm using logic elements or dedicated multipliers If you specify multiplier based and do not target Stratix device families the Quartus II software implements the NCO MegaCore function using logic elements Do not change the Target device family in the Implementation page The device family is automatically set to the value that was specified in the Quartus II or DSP Builder software and the generated HDL for your MegaCore function variation may be incorrect if this value is changed in IP Toolbench CAUTION 3 4 MegaCore Version 8 0 Altera Corporation NCO MegaCore Function User Guide May 2008 Parameter Settings Figure 3 4 Implementation Tab Multiplier Based Algorithm 6 Parameterize NCO 509 Parameters Implementation Resource Estimate Frequency Modulation Device Family Target Multiplier Based Architecture Stratix Ill Phase Modulation Ouputs C Phase Modulation Input Dual Output O Single Output HH Multi Channel NCO M Number of Channels NC Use Logic Elements Use Dedicated Multiplier s Clock Cycles Per Output 1 Frequency Domain Response Time Domain Response MEME ca 20 0 40 0 60 0 80 0 100 0 120 0 140 0 160 0 0 0 0 62500 126 1875 25 3 125 335 4375 50 Freauency x10 HI Cancel Altera Corporation May 2008 Click the Resource Estimate tab when you are finished setting
52. t these parameters you can graphically view the effects on the NCO MegaCore function in the Frequency Domain Response and Time Domain Response tabs See Figure 3 1 on page 3 2 The NCO MegaCore function generates the spectral plot shown in Figure 3 1 by computing a 2 048 point fast Fourier transform FFT of bit accurate time domain data Before performing the FFT IP Toolbench applies a Kaiser window of length 2 048 to the data You can zoom into the view by pressing the left mouse key on the plot drawing a box around the area of interest Right click the plot to restore the view to its full range Refer to Architectures on page 4 5 and Phase Dithering on page 4 9 for more information about these parameter options MegaCore Version 8 0 3 1 NCO MegaCore Function User Guide Setting Parameters Figure 3 1 Parameterize Tab Me Parameterize BAX Parameters Implementation Resource Estimate Generation Algorithm Precisions Phase Dithering Small ROM Phase Accumulator Precision 32 m Implement Phase Dithering Angular Resolution 116 v U 76 Dither Level Large ROM Magnitude Precision 18 v Min Max CORDIC Magnitude dB 0 20 0 40 0 60 0 80 0 100 0 120 0 140 0 160 0 0 0 9 Multiplier Based Frequency Domain Response Time Domain Response Generated Output Frequency Parameters Clock Rate 100 MHz v Desired Output Frequency 1 MHz v
53. tallation amp Licensing for Windows or Quartus II Installation amp Licensing for UNIX amp Linux Workstations Figure 1 3 shows the directory structure after you install the NCO MegaCore Function where path is the installation directory The default installation directory on Windows is c Naltera N80 or on Linux the default installation directory is opt altera 80 Figure 1 3 Directory Structure path Installation directory Jip Contains the MegaCore IP Library m Comma ip toolbench Contains common IP Toolbench files 1 7 Contains all of the NCO Compiler Files doc Contains all of the NCO Compiler Documentation iib Contains NCO Compiler encrypted source code and other support files f example_designs Contains example NCO Compiler design files M design1 Contains a dual output oscillator or example design design2 Contains a QFSK modulator example design OpenCore Plus Evaluation With Altera s free OpenCore Plus evaluation feature you can perform the following actions Simulate the behavior of a megafunction Altera MegaCore function or AMPP megafunction within your system W Verify the functionality of your design as well as evaluate its size and speed quickly and easily 1 6 MegaCore Version 8 0 Altera Corporation NCO MegaCore Function User Guide May 2008 About This MegaCore Funct
54. the implementation parameter options The NCO MegaCore function dynamically estimates the resource usage of your custom NCO MegaCore function variation based on the parameters specified See Figure 3 5 Arria GX Stratix Stratix GX Stratix and Stratix IV devices use adaptive look up tables ALUTS other devices use logic elements LEs MegaCore Version 8 0 3 5 NCO MegaCore Function User Guide Parameter Descriptions Figure 3 5 Resource Estimate Tab 3 Parameterize NCO Liles s Parameters Implementation Resource Estimate Resource Usage Estimate Number of ALUTs Number of Memory Bits Number of M9Ks Number of 9 bit DSP Elements Frequency Domain Response Time Domain Response 180 13824 Magnitude dB 0 20 0 40 0 60 0 80 0 100 0 120 0 140 0 160 0 0 0 0 62500 1 25 1 875 2 5 3 125 3 75 4375 Freayency 107 Hz canet 5 Click Finish when you are finished viewing the resource estimates Parameter This section describes the NCO MegaCore function parameters which a can be set in the user interface see Setting Parameters on page 3 1 Descriptions Table 3 1 shows the parameters that can be set in the Parameters page Table 3 1 NCO MegaCore Function Parameters Page Part 1 of 2 Parameter Generation Algorithm Small ROM Large ROM CORDIC Multiplier Based Value Description Choose the requir
55. tions on setting black box attributes for synthesis tools b Run the synthesis tool to produce an EDIF netlist file edf or a Verilog Quartus Mapping VQM file vqm for input to the Quartus II software c Add the EDIF or VOM file to your Quartus II project 2 Choose Start Compilation Processing menu in Quartus II software After a successful compilation you can program the targeted Altera device and verify the design in hardware Refer to Quartus II Help for instructions on compiling and programming your design MegaCore Version 8 0 Altera Corporation NCO MegaCore Function User Guide May 2008 N DTE RYA 3 Parameter Settings Setting Parameters Altera Corporation May 2008 This chapter gives an example of how to parameterize a NCO MegaCore function and describes the available parameters The Parameterize NCO pages provide the same options whether they have been opened from the DSP Builder or MegaWizard Plug In Manager flow For information about opening the parameterization pages refer to the Design Flows section in Chapter Design Flows gt user interface only allows you to select legal combinations of parameters and warns you of any invalid configurations To parameterize your NCO MegaCore function follow these steps 1 With the Parameters tab selected specify the generation algorithm precisions phase dithering and generated output frequency parameters As you adjus
56. uency to output frequency ratio and precision settings as shown in Figure 2 on page 2 At a dithering level of 5 the SFDR is approximately 111 95 dB which exceeds the specification MegaCore Version 8 0 A 1 NCO MegaCore Function User Guide Example Design 1 Figure A 1 Spectrum After Setting Angular amp Magnitude Precision After Setting Angular amp Magnitude Precision Frequency Domain of NCO Sin Output Magnitude dB Frequency Hz oat Figure A 2 Spectrum After the Addition of Dithering After Addition of Dithering Spectral Plot of NCO Sin Output Dither Level 5 20 Magnitude dB Frequency Hz x10 A 2 MegaCore Version 8 0 Altera Corporation NCO MegaCore Function User Guide May 2008 Example Designs Example Design 2 Altera Corporation May 2008 Example design 2 is a quaternary frequency shift keying OFSK modulator for use in a hypothetical transmitter design The design targets the Altera EP2S15F484C3 Stratix II device In this type of modulator the output frequency of the oscillator varies according to an input symbol stream the values of which map to a four symbol alphabet The top level design file is install path NipNnco example designs design2 design2 bdf The oscillator meets the following specifications SFDR 80dB Output Frequencies e f 576 MHz e f 192MHz e f 192MHz e f 5 76 MHz WB Output Sample Rate 220 MSPS
57. usoid is the power of the primary or desired spectral component relative to the power of its highest level harmonic component in the spectrum Harmonic components manifest themselves as spikes or spurs in the spectral representation of a digital sinusoid and occur at regular intervals and are also a direct consequence of finite precision However the effect of the spurs is often severe because they can cause substantial inter modulation products and undesirable replicas of the mixed signal in the spectrum leading to poor reconstruction of the signal at the receiver The direct effect of finite precision varies between architectures but the effect is augmented because due to resource usage constraints the NCO does not usually use the full accumulator precision in the polar to cartesian transformation You can mitigate truncation effects with phase dithering in which the truncated phase value is randomized by a sequence This process removes some of the periodicity in the phase reducing the spur magnitude in the sinusoidal spectrum by up to 12 dB The NCO MegaCore function s graphical spectral analysis allows you to view the effects as you change parameters without regenerating the IP Toolbench output files and re running simulation Refer to Setting Parameters on page 3 1 for information about how you can view the effects of changing the generation algorithm precision phase dithering and generated output frequency parameters Maximum O
58. ustom variations of megafunctions Which action do you want to perform Create a new custom megafunction variation 7 Edit an existing custom megafunction variation Copy an existing custom megafunction variation Copyright 1991 2008 Altera Corporation Cancel Bact Finish 3 Click Next and choose the NCO v8 0 from the Signal Generation section in the Installed Plug Ins tab Figure 2 2 Figure 2 2 Selecting the MegaCore Function MegaWizard Plug In Manager page 2a ix Which megafunction would you like to customize Select a megafunction from the list below Installed Plug Ins Altera SOPC Builder Arithmetic Communications gj DSP Error Detection Correction Filters Signal Generation NCO v7 2 NCO v8 0 J Transforms amp Video and Image Processing Gates mg 1 0 fi Interfaces JTAG accessible Extensions Memory Compiler a Storage Bi IP MegaStore Which device family will you be using Stratis 11 Which type of output file do you want to create C AHDL VHDL C Verilog HDL What name do you want for the output file Browse D mydesigns 80 nco_top Return to this page for another create operation Note To compile a project successfully in the Quartus Il software your design files must be in the project directory in the global user libraries specified in the Options dialog box Tools menu
59. utput Frequency The maximum frequency sinusoid that an NCO can generate is bounded by the Nyquist criterion to be half the operating clock frequency Additionally the throughput affects the maximum output frequency of the NCO If the NCO outputs a new set of sinusoidal values every clock cycle the maximum frequency is the Nyquist frequency If however the implementation requires additional clock cycles to compute the values the maximum frequency must be further divided by the number of cycles per output MegaCore Version 8 0 Altera Corporation NCO MegaCore Function User Guide May 2008 Functional Description Functional The NCO MegaCore function allows you to generate a variety of NCO x pm architectures You can create your custom NCO using an IP Toolbench Descri pti on driven interface that includes both time and frequency domain analysis tools The custom NCO outputs a sinusoidal waveform in two s complement representation The waveform for the generated sine wave is defined by the following equation k s nT Asin 270070 bas where e Tis the operating clock period e fois the unmodulated output frequency based on the input value frmis a frequency modulating parameter based on the input value fm py is derived from the phase modulation input value P and the number of bits used for this value by the equation P a wiatn prru is the internal dithering value
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