Home

DDR3 SDRAM Controller with ALTMEMPHY User Guide

1. PHY Command Outputs ac ck 2x Command Jes YXNOP YXacri NOP i 002 mem_ras_n mem_cas_n mem we n mem_cs_n 1 1 1 mem addr m yox te 000 i Jf f f mem_ba m mem_dq mem dqs i mu HM command interface is made up of the signals mem_ras_n mem_cas_n mem_we_n mem cs and mem odt The waveform in Figure 5 2 shows a NOP command followed by five back to back write commands The following sequence corresponds with the numbered items in Figure 5 2 1 The commands are asserted either on the rising edge of ac c1k 2x The ac clk 2x is derived from either mem clk 2 0 write clk 2 270 or the inverted variations of those two clocks for 180 and 90 phase shifts This depends on the setting of the address and command clock in the ALTMEMPHY parameter editor Refer to Address and Command Datapath on page 5 3 for illustrations of this clock in relation to the mem_clk_2x or write clk 2x signals 2 Alladdress and command signals except for mem cs ns mem cke and mem odt signals remain asserted on the bus for two clock cycles allowing sufficient time for the signals to settle 3 The mem cs n mem cke and mem odt signals are asserted during the second cycle of the address command phase B
2. 22 2 en 5 5 Clock Management rk hex deri bx ed P RP YU per PASE 5 5 Reset Management 5 7 Read Datapath isic cic Sig Re qa arbe rera ve bere age 5 8 Arria Il GX Devices eee eri er4 o GG RC E Pa REA RPG Rac dD a RR RTA 5 8 June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide iv Contents ALTMEMPHNY Signals 9 00520 erem eR EN De EEG Rad erred npe 5 10 PHY to Controller Interfaces 5 16 Using Custom Controller ieee ve ba Pr E eee HE PER CER als 5 24 Preliminary Steps ees cu NU a xS epe oS 5 24 D sign Considerations tr ee ee este pre e 5 24 Clocks and Resets 222222222924 GC a e Oe SELES Sea 5 24 Calibration Process Requirements 5 25 Other Local Interface Requirements 5 25 Address and Command Interfacing 5 25 Handshake Mechanism Between Read Commands and Read Data 5 25 Handshake Mechanism Between Write Commands and Write Data 5 26 Partial Writes 1
3. ALTMEMPHY Example External DLL Driver Pass or Memory 1 Devi Controller evice T Note to Figure 1 1 1 When you choose Instantiate DLL Externally delay locked loop DLL is instantiated outside the ALTMEMPHY megafunction The MegaWizard Plug In Manager generates an example top level file consisting of an example driver and your DDR3 SDRAM high performance controller custom variation The controller instantiates an instance of the ALTMEMPHY megafunction which in turn instantiates a phase locked loop PLL and DLL You can also instantiate the DLL outside the ALTMEMPHY megafunction to share the DLL between multiple instances of the ALTMEMPHY megafunction You cannot share a PLL between multiple instances of the ALTMEMPHY megafunction but you may share some of the PLL clock outputs between these multiple instances The example top level file is a fully functional design that you can simulate synthesize and use in hardware The example driver is a self test module that issues read and write commands to the controller and checks the read data to produce the pass or fail and test complete signals The ALTMEMPHY megafunction creates the datapath between the memory device and the memory controller The megafunction is available as a stand alone product or can be used in conjunction with the Altera high performance memory controller When using the ALTMEMPHY megafunction
4. 22 4 4 2 4 2 6 Specifying Parameters CERE E bap de dede dep aS 2 6 Generated Pies P 2 8 Chapter 3 Parameter Settings ALTMEMPHY Parameter Settings 3 1 Memory Settings er ned RUP RH EPI ER baden d ee 3 2 Using the Preset Editor to Create a Custom Memory Preset 3 3 Derating Memory Setup and Hold Timing 3 10 PEDBGSetUngs 235 d dee eee ed done ue a Rob Saee diui 3 11 Settings D EE 3 11 DDR3 SDRAM Controller with ALTMEMPHY Parameter Settings 3 12 Controller erreti e lavas tecto tse gode duo e o e tee d gn 3 13 Chapter 4 Compiling and Simulating Compiling the Design NR eese ee Pee e bb d pe eeu paetos eria 4 1 Simulating the Design i ecce Hee tette 4 4 Chapter 5 Functional Description ALTMEMPHY Block Description siete etre 5 2 Calibration orm er er EN oak UU T ERE P aan s ve ires 5 3 Address and Command Datapath 2 2 2 5 3 MGX Devices tre deca Pk hak ee RGA SSSA RSS E RH PAN xe aep 5 3 Clock and Reset Management
5. MEER ER 6 5 Automatic Power Down with Programmable Time Out 6 5 ODT Generatiori LOGIC a ee eitia ente ehe eleme GE Re 6 6 DDR3SDRAM b ame EPI Idee hoa ee bre PERS 6 6 ECC oos tener acts tti IL Lem SIL dM E m 6 7 Partial Writes ERO Oen pH E ERE b dig eer ee Ire LETS 6 8 Partial 5 5 e NR pape Eee a guts 6 9 External Interfaces 6 9 Clock andi Reset Interface e eerte Re ere e e done ee 6 10 Avalon ST Data Slave Interface 1 2 6 10 Controller PEPY Interface er ee eth ete e een cete date tee ede 6 10 Memory Side Band Signals 6 10 Self Refresh Low Power Interface 6 10 User Controller Refresh Interface 2 6 11 Configuration and Status Register CSR Interface 6 11 Top Level Signals 6 12 Sequence of Operations esee De hte e e need e EXORTU ea PU Re t bad e e end 6 18 Write Command VR e vado P epe tpe ced 6 18 Read Command ea dotate edu el tito den ee ted ed 6 19 Read Modify Wri
6. Ir I I AFI Command 2 0 Worm xc acr mI NOP afi dm 3 0 afi_dqs_burst 0 afi_dqs_burst 1 afi doing rd 1 0 Wo L 9 71 o s J afi rdata 31 0 00000000 afi rdata valid 1 0 M s I o l 3 AFI Memory Interface mem cke 1 0 nnuuuuuuuuuuuuuuuuuud mem ba 2 0 WT 0 Tite o mem_addr 13 0 0000 Y pory oo 1440 00 0000 148 0001 0000 mem cs 1 0 UU UU Mem Command 2 0 No RDN NOP mem_dgs uuu mem dm 720 o Ivo I Iw 00 mem odi 1 0 Y 910 05 eoueuuojieg uDIH 304 sweifeig 8 1934249 01 8 Chapter 8 Timing Diagrams 8 11 DDR3 High Performance Controller 11 The following sequence corresponds with the numbered items in Figure 8 5 1 The user logic requests the first read by asserting the local read req signal and the size and address for this read In this example the request is a burst of length of 2 to the local address 0x0000810 This local address is mapped to the following memory address in half rate mode mem row address 0x0001 mem col address 0x0010 2 0x0040 mem bank address 0x00 2 When the command queue is full the controller deasserts the 1ocal ready signal to indicate that the controller has not accepted the command The user logic must keep the read request size and address signal until the 1ocal ready signalis asserted again 3 Th
7. import port on the other PHY instance June 2011 Table 6 9 on page 6 14 shows the controller local interface signals Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 6 14 Chapter 6 Functional Description High Performance Controller Il Top Level Signals Description Table 6 9 Local Interface Signals Part 1 of 4 Signal Name local address Direction Input Description Memory address at which the burst should start By default the IP core maps local address to the bank interleaving scheme You can change the ordering via the Local to Memory Address Mapping option in the Controller Settings page The IP core sizes the width of this bus according to the following equations m Full rate controllers For one chip select width row bits bank bits column bits 1 For multiple chip selects width chip bits row bits bank bits column bits 1 If the bank address is 2 bits wide row is 13 bits wide and column is 10 bits wide the local address is 24 bits wide To map 1ocal address to bank row and column address local address is 24 hits wide local address 23 11 row address 12 0 local address 10 9 bank address 1 0 local address 8 0 column address 9 1 The IP core ignores the least significant bit LSB of the column address multiples of four on the memory side because the local data width i
8. The maximum DQS to DQ skew DQS to last DQ valid per group per access 10055 Positive DQS latching edge to associated clock edge External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide June 2011 Altera Corporation Chapter 3 Parameter Settings 3 9 ALTMEMPHY Parameter Settings Table 3 5 DDR3 SDRAM Timing Parameter Settings Part 2 of 2 Note 1 Parameter Name Range Units Description DQ and DM input hold time relative to 005 which has a derated value depending on the slew rate of the differential DQS and DQ DM signals Ensure that you are using the correct number and that the value entered is referenced to Vpge dc not Viu dc min or Vj dc max Refer to Derating Memory Setup and Hold Timing on page 3 10 for more information about how to derate this specification DQ and DM input setup time relative to DQS which has a derated value depending on the slew rate of the differential DQS signals and DQ DM signals Ensure that you are using the correct number and that the value entered is referenced to Vgge dc not Viu ac min or Vj ac max Refer to Derating Memory Setup and Hold Timing on page 3 10 for more information about how to derate this specification tpsu 0 1 0 5 tek DQS falling edge hold time from CK tpss 0 1 0 5 tek 005 falling edge to CK setup Address and control input hold time which has a derated value dependin
9. e bU c wd Pis 5 27 Chapter 6 Functional Description High Performance Controller Il Memory Controller Architecture 6 1 Ayalon ST Input Interface ete rr 6 2 Command Generator kd ears poen 6 2 Timing Bank Pool epe e Ret era e Cp ed epa etes ug etu s 6 3 Arpiter serrare 6 3 Arbitration Rules ie ete 6 3 Rank TimMer hit eRe hice 6 3 Read Data uere e alten PT bia 6 3 Write Data Butter 6 3 ECC BIOK DP 6 3 APL Intertac d ia C i baie 6 4 CSR Interface uos E 6 4 Controller Features Descriptions 6 4 Data Reordering ee tele cepe desee einen 6 4 Pre emptive Bank Management 6 4 Quasi 1T arid Quasi T id deu bd ecd 6 4 User Autoprecharge Commands 6 5 Address and Command Decoding Logic 6 5 Low Power LOgiC Wd epee o VOI de ead E tos 6 5 Us r Controlled Sel Refresh
10. Compiling and Simulating 4 5 Simulating the Design 57 If you are simulating your ALTMEMPHY based design with a Denali model Altera recommends that you use full calibration mode For more information about simulation refer to the Simulation section in volume 4 of the External Memory Interface Handbook June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 4 6 External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Chapter 4 Compiling and Simulating Simulating the Design June 2011 Altera Corporation ND SRYN 5 Functional Description ALTMEMPHY June 2011 The ALTMEMPHY megafunction creates the datapath between the memory device and the memory controller and user logic in various Altera devices The ALTMEMPHY megafunction GUI helps you configure multiple variations of a memory interface You can then connect the ALTMEMPHY megafunction variation with either a user designed controller or with the Altera high performance controller In addition the ALTMEMPHY megafunction and the Altera high performance controller are available for half rate DDR3 SDRAM interfaces If the ALTMEMPHY megafunction does not meet your requirements you can also create your own memory interface datapath using the ALTDLL and ALTDO DOS megafunctions available in the Quartus II software However you are then resp
11. Document Revision History Info 1 How to Contact Altera Info 1 Typographic Conventions see e metere eee ee en RC ed edere be eds Info 2 June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide vi External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide June 2011 Contents Altera Corporation 1 About This The Altera DDR3 SDRAM Controller with ALTMEMPHY IP provides simplified interfaces to industry standard DDR3 SDRAM The ALTMEMPHY megafunction is an interface between a memory controller and the memory devices and performs read and write operations to the memory The DDR3 SDRAM Controller with ALTMEMPHY IP works in conjunction with the Altera ALTMEMPHY megafunction The DDR3 SDRAM Controller with ALTMEMPHY IP and ALTMEMPHY megafunction support DDR3 SDRAM interfaces in half rate mode The DDR3 SDRAM Controller with ALTMEMPHY IP offers the high performance controller II HPC ID which provides high efficiency and advanced features Figure 1 1 on page 1 1 shows a system level diagram including the example top level file that the DDR3 SDRAM Controller with ALTMEMPHY IP creates for you Figure 1 1 System Level Diagram Example Top Level File
12. On the Project menu click Set as Top Level Entity Generated Files Table 2 3 shows the ALTMEMPHY generated files Table 2 3 ALTMEMPHY Generated Files Part 1 of 2 File Name Description Contains constants used in the interface This file is alt mem phy defines v always in Verilog HDL regardless of the language you chose in the MegaWizard Plug In Manager Lists the top level files created and ports used in the variation name html _ gt megafunction lt variation_name gt ppt Pin planner file for your ALTMEMPHY variation Quartus II IP file for your ALTMEMPHY variation lt variation_name gt qip containing the files associated with this megafunction Top level file of your ALTMEMPHY variation generated lt variation_name gt v vhd based on the language you chose in the MegaWizard Plug In Manager variation name vho Contains functional simulation model for VHDL only Includes a delay module for simulation This file is only variation name alt mem phy delay vhd generated if you choose VHDL as the language of your MegaWizard Plug In Manager output files Generated file that contains DQ DQS 1 0 atoms variation name alt mem phy dq dqs vhd or v interconnects and instance Arria GX devices only Specification file that generates the variation name mem phy dq 445 clearbox txt variation name alt mem phy dq 445 file using the clea
13. afi cs 13 AFI Command 2 afi dm 3 afi das afi das afi doing 19112 afi rdata 31 afi rdata Controller AFI f 2 B 4 Ini JAABBCCOD EEFF0011 AABBCCDD EEFF0011 AABBCCDD AFI Memory Interface ck mem ba 2 mem 20013 nj Mem Command Tem 05 mem dm mem 47 mem 041 1000 0000 1008 uuuuuuuuuuut Y vo NOI 5 3 0 E IM E E D 2 e 9 0 09 eoueuuoueg ubiH euaa sweifeig 8 193deu9 8 Chapter 8 Timing Diagrams DDR3 High Performance Controller 11 The following sequence corresponds with the numbered items in Figure 8 1 1 June 2011 Altera Corporation The user logic requests the first read by asserting the local_read_regq signal and the size and address for this read In this example the request is a burst of length of 2 to the local address 0x000000 This local address is mapped to t
14. alt mem ddrx cmd gen v Converts user requests to DRAM aware commands alt mem d rx csr v Contains configuration registers alt mem ddrx buffer v Contains buffer for local data alt mem ddrx buffer manager v Manages the allocation of buffers alt mem ddrx burst tracking v Tracks data received per local burst command alt mem ddrx dataid manager v Manages the IDs associated with data stored in buffer alt mem ddrx fifo v Contains the FIFO buffer to store local data to create a link is also used in rdata path to store the read address and error address alt mem du rx list v Tracks the DRAM commands associated with the data stored internally alt mem ddrx rdata path v Contains read data path logic alt mem ddrx wdata path v Contains write data path logic External Memory Interface Handbook Volume 3 Section II DDR3 SDRAM Controller with ALTMEMPHY IP User Guide June 2011 Altera Corporation Chapter 2 Getting Started Generated Files Table 2 5 Controller Generated Files Part 2 of 2 2 11 Filename alt_mem_ddrx_define iv Description Defines common parameters used in the RTL files alt mem ddrx ecc decoder v Instantiates appropriate width ECC decoder logic alt mem ddrx ecc decoder 32 syn v Contains synthesizable 32 bit version of ECC decoder alt mem ddrx ecc decoder 64 syn v Contains synthesiza
15. memek fififiwuuuwuvwuwwwuwuwwuwuwwwwwuwwuwuwuvwuuuuuwwwwwwuwvuwvuwuwvuwwuwwv mem 2 mem addi 13 1000 0000 Y 1000 0000 Y 1008 0000 1010 T mem cs nf LJ LI VI LJ LJ Mem Command 2 L NO WRI NOP WRI NOPI WR NOP WR mem 105 mem_dm ee mem 447 I 00 I 00 typogr epos pole joo 2 mem 04 910 05 eoueuuojieg uDIH 304 sweifeig 8 1934249 Chapter 8 Timing Diagrams DDR3 High Performance Controller 11 June 2011 The following sequence corresponds with the numbered items in Figure 8 2 1 Altera Corporation The user logic asserts the first write request to row 0 so that row 0 is open before the next transaction The user logic asserts a second local_write_req signal with size of 2 and address of 0 col 0 row 0 bank 0 chip 0 The local_ready signal is asserted along with the local_write_reg signal which indicates that the controller has accepted this request and the user logic can request another read or write in the following clock cycle If the 1ocal ready signal was not asserted the user logic must keep the write request size and address signals asserted until the 1ocal ready signal is registered high The controller issues the necessary memory command and address signals to the ALTMEMPHY megafunction for it to send to the memory device The controller asserts the afi_wdata_valid s
16. usr mode rdyto the memory controller which then asserts this signal to indicate that the memory interface is ready for use The controller still accepts read and write requests before local init done is asserted however it does not issue them to the memory until it is safe to do so This signal does not indicate that the calibration is successful local rdata Output Read data bus The width of 1ocal rdata is twice that of the memory data bus for a full rate controller four times the memory data bus for a half rate controller local rdata error Output Asserted if the current read data has an error This signal is only available if you turn on Enable Error Detection and Correction Logic The controller asserts this signal with the 1 1 rdata valid signal If the controller encounters double bit errors no correction is made and the controller asserts this signal local rdata valid Output Read data valid signal The 1 1 rdata valid signal indicates that valid data is present on the read data bus External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide June 2011 Altera Corporation Chapter 6 Functional Description High Performance Controller 11 6 17 Top Level Signals Description Table 6 9 Local Interface Signals Part 4 of 4 Signal Name Direction Description The local_ready signal indicates that the controller is ready
17. you can only perform timing analysis with one DQ bits per DOS bit 4or8 bits Defines the number of data DQ bits for each data strobe DQS pin Specifies whether you are using DM pins for write Drive DM pins from FPGA Yes or No operation Altera devices do not support DM pins with x4 mode Maximum memory frequency for CAS latency 5 0 Maximum memory frequency Tor acy on Specifies the frequency limits from the memory data Maximum memory frequency sheet per given CAS latency The ALTMEMPHY for CAS latency 7 0 80 700 MegaWizard Plug In Manager generates a warning if the operating frequency with your chosen CAS latency exceeds this number The lowest frequency supported by DDR3 SDRAM devices is 300 MHz Note to Table 3 3 1 The range values depend on the actual memory device used Table 3 4 DDR3 SDRAM Initialization Options Part 1 of 2 Parameter Name Range Units Description PM Sets the number of words read or written per Memory burst length 4 8 on the fly beats transaction Controls the order in which data is transferred between Sequential or memory and the FPGA during read transaction For Memory burst ordering Interleaved more information refer to the memory device datasheet Sets the mode register setting to disable Slow exit DLL precharge power down Fasi prd A enable Fast exit the memory DLL when CKE is disabled Enables the DLL in the memory device when set
18. 1 When you choose Instantiate DLL Externally DLL is instantiated outside the controller Before compiling a design with the ALTMEMPHY variation you must edit some project settings include the sdc file and make I O assignments I O assignments include I O standard pin location and other assignments such as termination and drive strength settings Some of these tasks are listed in the ALTMEMPHY Generation window To use the Quartus II software to compile the example top level file in the Quartus II software and perform post compilation timing analysis perform the following steps 1 Set up the TimeQuest timing analyzer On the Assignments menu click Timing Analysis Settings select Use TimeQuest Timing Analyzer during compilation and click OK b Add the Synopsys Design Constraints sdc file lt variation name gt _phy_ddr_timing sdc to your project On the Project menu click Add Remove Files in Project and browse to select the file c Add the sdc file for the example top level design lt variation name gt _example_top sdc to your project This file is only required if you are using the example as the top level design Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 4 2 Chapter 4 Compiling and Simulating Compiling the Design 2 You either use the lt variation_name gt _pin_assignments tcl or the lt variation_name gt ppf fi
19. 1 1 1 tl rdat lid 1 1 1 1 1 1 1 1 fi T T T T T T T T T T ctl rdoto ey Figure 5 13 Second Read Alignment Half Rate Design ctl rlat 9 1 2 3 4 5 6 7 8 9 cil cl ctl t t t t t ctl cs 1 19 1 1 1 1 1 1 li ctl doing read 10 01 1 1 1 1 1 1 1 1 1 mem dqs VJ 1 1 1 1 1 1 1 1 1 1 1 mem dq 1 1 Qoo 1 1 1 1 ctl_rdata_valid 10 01 rdata Handshake Mechanism Between Write Commands and Write Data In the AFI the ALTMEMPHY output ct1 wlat gives the number of ct1_clk cycles between the write command that is issued ct1 cs nasserted and ct1 dqs burst asserted The ct1_wlat signal considers the following actions to provide a single value in ct1 1 clock cycles m CAS write latency m Additive latency m Datapath latencies and relative phases Board layout m Address and command path latency and 17 register setting which is dynamically setup to take into account any leveling effects External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section 1 DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Chapter 5 Functional Description ALTMEMPHY 5 27 Using a Custom Controller June 2011 The ct1 wl
20. 6 7 summarizes the controller s external interfaces Table 6 7 Summary of Controller External Interfaces Part 1 of 2 Interface Name Display Name Type Clock and Reset Interface Description Clock and Reset Interface Clock and Reset Interface AFI 1 Clock and reset generated by UniPHY to the controller Avalon ST Data S lave Interface Command Channel Avalon ST Data Slave Interface Avalon ST 2 Address and command channel for read and write SCSD Write Data Channel Avalon ST Data Slave Interface Avalon ST 2 Write Data Channel SCMD Read Data Channel Avalon ST Data Slave Interface Avalon ST 2 Read data channel SCMD with read data error response Controller PHY Interface AFI 2 0 AFI Interface AFI 1 Interface between controller and PHY Memory Side B and Signals Self Refresh Low Power Interface Self Refresh Low Power Interface Avalon Control amp Status Interface 2 SDRAM specific signals to place memory into low power mode User Controller Refresh Interface User Controller Refresh Interface Avalon Control amp Status Interface 2 SDRAM specific signals to request memory refresh June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 6 12 Chapter 6 Functional Description High Performanc
21. Debug interface address dbg_cs Input Debug interface chip select dbg wr Input Debug interface write request dbg wr data Input Debug interface write data dbg rd Input Debug interface read request dbg rd data Input Debug interface read data dbg waitrequest Output Debug interface wait request External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide June 2011 Altera Corporation Chapter 6 Functional Description High Performance Controller 11 6 23 Register Maps Register Maps Table 6 15 shows the overall register mapping for the DDR3 SDRAM Controller with ALTMEMPHY Table 6 15 Register Map Address Description ALTMEMPHY Register Map 0x005 Mode register 0 1 0x006 Mode register 2 3 Controller Register Map 0x100 ALTMEMPHY status and control register 0x110 Controller status and configuration register 0x120 Memory address size register 0 0x121 Memory address size register 1 0x122 Memory address size register 2 0x123 Memory timing parameters register 0 0x124 Memory timing parameters register 1 0x125 Memory timing parameters register 2 0x126 Memory timing parameters register 3 0x130 ECC control register 0x131 ECC status register 0x132 ECC error address register ALTMEMPHY Register Map The ALTMEMPHY register map allows you to control the memory components mode register settings Table 6 16 shows the registe
22. Enable User Auto Refresh Controls option is turned on 1ocal refresh req becomes available and you are responsible for issuing sufficient refresh requests to meet the memory requirements This option allows complete control over when refreshes are issued to the memory including grouping together multiple refresh commands Refresh requests take priority over read and write requests unless the IP core is already processing the requests local refresh chip Input Controls which chip to issue the user refresh to The IP core uses this active high signal with 1ocal refresh req This signal is as wide as the memory chip select This signal asserts a high value to each bit that represents the refresh for the corresponding memory chip For example If 1ocal refresh chip signal is assigned with a value of 4 b0101 the controller refreshes the memory chips 0 and 2 and memory chips 1 and 3 are not refreshed local size Input Controls the number of beats in the requested read or write access to memory encoded as a binary number The IP core supports Avalon burst lengths from 1 to 64 The IP core derives the width of this signal based on the burst count that you specify in the Local Maximum Burst Count option With the derived width you specify a value ranging from 1 to the local maximum burst count specified local wdata Input Write data bus The width of 1ocal wdata is twice that of the memory data bus for a full rate cont
23. II DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Chapter 2 Getting Started 2 7 MegaWizard Plug In Manager Flow 3 Specify the parameters on all pages in the Parameter Settings tab lt For detailed explanation of the parameters refer to the Parameter Settings on page 3 1 4 Onthe EDA tab turn on Generate simulation model to generate an IP functional simulation model for the MegaCore function in the selected language An IP functional simulation model is a cycle accurate VHDL or Verilog HDL model produced by the Quartus II software A Use the simulation models only for simulation and not for synthesis or any other purposes Using these models for synthesis creates a nonfunctional design Some third party synthesis tools can use a netlist that contains only the structure of the MegaCore function but not detailed logic to optimize performance of the design that contains the MegaCore function If your synthesis tool supports this feature turn on Generate netlist When targeting a VHDL simulation model the MegaWizard Plug In Manager still generates the lt variation_name gt _alt_mem_phy v file for the Quartus II synthesis Do not use this file for simulation Use the lt variation_name gt vho file for simulation instead The ALTMEMPHY megafunction only supports functional simulation You cannot perform timing or gate level simulation when using the ALTMEMPHY megafunction 5 On the Summary tab select the fi
24. The LSB of these two becomes the first value the signal takes in the c1k domain You can seethatctl dqs burst has the necessary one mem 1 cycle lead on ct1 wdata valid The latency between ctl cs n being asserted and ct1 wdata valid going high is effectively ct1_wlat in this example two controller clock ctl cIk cycles This can be thought of in terms of relative memory clock mem c1k cycles in which case the latency is four mem 1 cycles Only the upper half is valid as the 1 wdata valid signal demonstrates there is ct1 wdata valid bit to two 8 bit words The write data bits go out on the bus in order least significant byte first So for a continuous burst of write data on the DQ pins the most significant half of write data is used which goes out on the bus last and is therefore contiguous with the following data The converse is true for the end of the burst Write data is spread across three controller clock ct1_c1k cycles but still only four memory clock mem c1k cycles However in relative memory clock cycles the latency is equivalent in the word aligned and word unaligned cases The 0504 here is residual from the previous clock cycle In the same way that only the upper half of the write data is used for the first beat of the write only the lower half of the write data is used in the last beat of the write These upper bits can be driven to any value in this alignment External Memory Interface Handbook V
25. This bus is half the width of the local read and write data busses m Memory data strobe signal which writes data into the DDR3 SDRAM and em_dqs Bidirectional Captures read data into the Altera device TE Bidirectional nM data strobe signal which with the mem signal improves em clk Bidirectional Clock for the memory device em clk n Bidirectional Inverted clock for the memory device em addr Output Memory address bus T Output sat signal generated by the PHY and sent to the em Output Memory bank address bus em cas n Output Memory column address strobe signal em Output Memory clock enable signals em cs n Output Memory chip select signals em dm Output Memory data mask signal which masks individual bytes during writes em odt Output Memory on die termination control signal em ras n Output Memory row address strobe signal em we n Output Memory write enable signal Active low signal that is asserted when a parity error occurs and stays parturien Sy Output asserted until the PHY is reset DDR3 SDRAM only June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section 1 DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 6 18 Table 6 10 Interface Signals Part 2 of 2 Chapter 6 Functional Description High Performance Controller Il Sequence of Operations Signal Name mem err out n 1 Direction Input Description Signal sent from the DIM
26. calibration and is dependant upon the relative delays in the address and command path and the write datapath in both the PHY and the external DDR SDRAM subsystem The controller must drive ctl_cs_n and then wait ct1_wlat two this example ct1_clks before driving ctl_wdata_valid 4 Observe the ordering of write data ct1 wdata Compare this to data on the mem signal In all waveforms a command record is added that combines the memory pins ras n cas n and into the current command that is issued This command is registered by the memory when chip select mem cs n is low The important commands in the presented waveforms are WR write ACT activate a S External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section II DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 5 21 Chapter 5 Functional Description ALTMEMPHY PHY to Controller Interfaces Figure 5 9 Word Aligned Reads ctl_cas_n o ctl_we_n ctl_doin lt N A E AEN AA EE E e L RL BE RB RE R e e Pe E e e 2 o e E LsbesebebmrzsbsbimseLbeesiscse e ra p SUR Ed S
27. driving the DO outputs For designs targeting other devices use only the DM pins if you require partial writes Assertthe ctl dqs burstand ctl wdata validsignals as for full write operations so that the DO and DOS pins are driven during partial writes Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 5 28 Chapter 5 Functional Description ALTMEMPHY Using a Custom Controller External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 6 Functional Description JN DTE RYAN High Performance Controller Il gt This chapter describes the High Performance Controller HPC II with advanced features introduced in version 11 0 for designs generated in the Quatus II software version 11 0 Designs created in earlier versions and regenerated in version 11 0 do not inherit the new advanced features for information on HPC II without the version 11 0 advanced features refer to the External Memory Interface Handbook for Quartus II version 10 1 available in the External Memory Interfaces section of the Altera Literature website The memory controller provides high memory bandwidth high clock rate performance and run time programmability The controller can reorder data to reduce row conflicts and bus turn around time by grouping reads and writes together allowing for efficien
28. equivalent As a result its phase leads that of the mem clk 2x by 90 ac_clk 2x C3 909 Full Rate Global Regional Address and command clock The ac_clk_2x clock is derived from either mem_clk_2x when you choose 0 or 180 phase shift or write 2 when you choose 90 or 270 phase shift Refer to Address and Command Datapath on page 5 3 for illustrations of the address and command clock relationship with the mem clk_2x Of write clk 2x signals n clk 2x C3 909 Full Rate Global Global Memory chip select clock n 2x clock is derived from ac_clk 2x resync clk 2x C4 Calibrated Full Rate Global Regional Clocks the resynchronization registers after the capture registers Its phase is adjusted to the center of the data valid window across all the DQS clocked DDIO groups External Memory Interface Handbook Volume 3 Section II DDR3 SDRAM Controller with ALTMEMPHY IP User Guide June 2011 Altera Corporation Chapter 5 Functional Description ALTMEMPHY Block Description Table 5 1 DDR3 SDRAM Clocking in Arria GX Devices Part 2 of 2 5 7 Clock Name 7 measure clk 2x Postscale Counter C5 Phase Degrees Calibrated Clock Rate Full Rate Clock Network Type All Quadra nts Global Any 3 Quadrants 2 Regional Notes This clock
29. groups should be used by assigning each DQS pin to the required pin The Quartus II Fitter then automatically places the respective DQ signals onto suitable DQ pins within each group To avoid no fit errors when you compile your design ensure that you place the mem_clk pins to the same edge as the mem dq and mem pins and set an appropriate I O standard for the non memory interfaces such as the clock source and the reset inputs when assigning pins in your design For example for DDR3 SDRAM select 1 5 V Also select in which bank or side of the device you want the Quartus II software to place them The x4 DIMM has the following mapping between DOS and DQ pins DOS 0 maps to DQ 3 0 DOS 1 maps to DQ 7 4 wm DOS 2 maps to DO 11 8 m DOS 3 maps to DQ 15 12 The DOS pin index in other x4 DIMM configurations typically increases sequentially with the DQ pin index DOS 0 DO 3 0 DOS 1 DO 7 4 DOS 2 DQ 11 8 Specify the output pin loading for all memory interface pins Select your required I O driver strength derived from your board simulation to ensure that you correctly drive each signal or ODT setting and do not suffer from overshoot or undershoot To compile the design on the Processing menu click Start Compilation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Chapter 4 Compiling and Simulating Simulating the Design After you have
30. half rate or DWIDTH RATIO 4 is supported to allow controllers to issue reads and writes that are aligned to either the half cycle of the half rate clock ctl rlat Output READ LAT WIDTH Contains the number of clock cycles between the assertion of ct1 doing the return of valid read data ct1 rdata This signal is unused by the Altera high performance controller Address and Command Interface MEM IF ROWADDR WIDTH ctl addr Input x DWIDTH RATIO 2 Row address from the controller ctl ba Input Bank address from the controller ctl_cke Input Clock enable from the controller ctl cs n Input 4 Chip select from the controller ctl odt Input On die termination control from the controller ctl_ras_n Input DWIDTH RATIO 2 Row address strobe signal from the controller June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section 1 DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 5 14 Table 5 3 AFI Signals Part 4 of 4 Chapter 5 Functional Description ALTMEMPHY ALTMEMPHY Signals Signal Name Type Width 7 Description ctl we n Input DWIDTH RATIO 2 Write enable ctl cas n Input DWIDTH RATIO 2 Column address strobe signal from the controller ctl rst n Input DWIDTH RATIO 2 Reset from the controller Calibration Control and Status Interface IF PAIR When as
31. is for VT tracking This free running clock measures relative phase shifts between the internal clock s and those being fed back through a mimic path As a result the ALTMEMPHY megafunction can track VT effects on the FPGA and compensate for the effects Note to Table 5 1 1 The 1 clock represents a frequency that is half of the memory clock frequency the 2x clock represents the memory clock frequency 2 The default clock network type is Global however you can specify a regional clock network to improve clock jitter if your design uses any three quadrants 3 For mem clk2x 4 Foraux full rate Reset Management Figure 5 3 shows the main features of the reset management block for the DDR3 SDRAM PHY You can use the p11 ref clk input to feed the optional reset request nedge detect and reset counter module However this requires the pll ref clksignal to use a global clock network resource June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 5 8 Chapter 5 Functional Description ALTMEMPHY Block Description There is a unique reset metastability protection circuit for the clock divider circuit because the phy_clk domain reset metastability protection registers have fan in from the soft_reset_n input so these registers cannot be used Figure 5 3 ALTMEMPHY Reset Management Block for Arria Il GX Devices seq pll start
32. legal values is 6 32 cycles 31 16 Reserved 0 Reserved for future use _ The refresh interval timing parameter The 15 0 ther Read write range of legal values is 780 6240 cycles 0x125 _ The refresh cycle timing parameter The 23 16 range of legal values is 12 88 cycles 31 24 Reserved 0 Reserved for future use This value must be set to match the memory 3 0 CAS latency to Read write CAS latency You must set this value in the 0x04 register map as well Additive latency setting The default value for these bits is set in the Memory additive CAS 7 4 Additive latency AL latency setting in the Preset Editor dialog box You must set this value in the 0x05 0x126 as well write latency setting You must set this BE HER wie lainey value in the 0x06 register map as well This value must be set to match the memory 15 12 Write recovery twp write recovery time twp You must set this value in the 0x04 register map as well 19 16 Burst Length Read write Value must match memory burst length 31 20 Reserved 0 Reserved for future use June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 6 28 Table 6 17 Controller Register Map Part 4 of 5 Chapter 6 Functional Description High Performance Controller Il Register Maps Address 0x130 Bit ENABLE_ECC Default Ac
33. memory address range 0x0 to 0x47 multiply the memory address by the width of the memory interface data bus in bytes Refer to Table 2 2 for more Avalon MM addresses Table 2 2 Avalon MM Addresses for Mode Interface Reset Vector Offset Exception Vector Offset 8 0x60 0x80 16 0 0 0 0 32 0x120 0x140 64 0x240 0x260 4 Click Finish 5 On the Component Library tab expand Interface Protocols and expand Serial 6 Select JTAG UART and click Add 7 Click Finish Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 2 6 Ls Chapter 2 Getting Started MegaWizard Plug In Manager Flow If there are warnings about overlapping addresses on the System menu click Auto Assign Base Addresses If you enable ECC and there are warnings about overlapping IRQs on the System menu click Auto Assign IRQs 8 For this example system ensure all the other modules are clocked on the altmemddr_sysclk to avoid any unnecessary clock domain crossing logic 9 Click Generate Ls To ensure that the external connections and memory interfaces are exported to the top level RTL file be careful not to accidentally rename or delete either of these interfaces in the Export column of the System Contents tab Among the files generated by Qsys is the Quartus II IP File qip This file contains information about a generated IP core or
34. of the read modify write process In this case the IP core increments the double bit error counter and issues an interrupt The IP core writes a new write word to the location of the error The ECC status register keeps track of the error information External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section II DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Chapter 6 Functional Description High Performance Controller 11 6 9 External Interfaces Figure 6 3 and Figure 6 4 show partial write operations for the controller for full and half rate configurations respectively Figure 6 3 Partial Write for the Controller Full Rate local address 0 Y 1 local_size 2 local be xi Y local wdata 01234567 89ABCDEF mem dm aY RX RY E f coy a9 mem dq Figure 6 4 Partial Write for the Controller Half Rate local address local_size local be Pp local_wdata 01234567 mem_dm ea Partial Bursts Devices that do not have the DM pins do not support partial bursts You must write a minimum or multiples of memory burst length equivalent words to the memory at the same time Figure 6 5 shows a partial burst operation for the controller Figure 6 5 Partial Burst for Controller local address local size 24 4 local be local_wdata 7 01234567 mem_
35. phase steps per cycle The text window at the bottom of the MegaWizard Plug In Manager displays information about the memory interface warnings and errors if you are trying to create something that is not supported The Finish button is disabled until you correct all the errors indicated in this window June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section 1 DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 3 2 Chapter 3 Parameter Settings ALTMEMPHY Parameter Settings The following sections describe the four tabs of the Parameter Settings page in more detail Memory Settings In the Memory Settings tab you can select a particular memory device for your system and choose the frequency of operation for the device Under General Settings you can choose the device family speed grade and clock information In the middle of the page left side you can filter the available memory device listed on the right side of the Memory Presets dialog box refer to Figure 3 1 If you cannot find the exact device that you are using choose a device that has the closest specifications then manually modify the parameters to match your actual device by clicking Modify parameters next to the Selected memory preset field Table 3 1 describes the General Settings available on the Memory Settings page of the ALTMEMPHY parameter editor Table 3 1 General Settings Parameter Name Description Targets d
36. refresh Determines the temperature range for self refresh You need to also use the optional auto self refresh option Memory self refresh range Extertd d when using this option The Altera controller currently does not support the extended temperature self refresh operation June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 3 8 Chapter 3 Parameter Settings ALTMEMPHY Parameter Settings Table 3 5 DDR3 SDRAM Timing Parameter Settings Part1of2 Note 1 Parameter Name Time to hold memory reset before beginning calibration 0 1000000 Units us Description Minimum time to hold the reset after a power cycle before issuing the MRS commands during the DDR3 SDRAM device initialization process tit 0 001 1000 us Minimum memory initialization time After reset the controller does not issue any commands to the memory during this period ns Minimum load mode register command period The controller waits for this period of time after issuing a load mode register command before issuing any other commands tunp is specified in ns in the DDR3 SDRAM high performance controller and in terms of tc cycles in Micron s device datasheet Convert to ns by multiplying the number of cycles specified in the datasheet times where is the memory operation frequency a
37. system In most cases the qip file contains all of the necessary assignments and information required to process the MegaCore function or system in the Quartus II compiler Generally a single qip file is generated for each Osys system However some more complex Qsys components generate a separate qip file In that case the system qip file references the component qip file 10 Compile your design refer to Compiling and Simulating on page 4 1 MegaWizard Plug In Manager Flow The MegaWizard Plug In Manager flow allows you to customize the DDR3 SDRAM Controller with ALTMEMPHY or the stand alone PHY with the ALTMEMPHY megafunction and manually integrate the function into your design Help For more information about the MegaWizard Plug In Manager refer to the Quartus II Specifying Parameters To specify parameters using the MegaWizard Plug In Manager flow perform the following steps 1 In the Quartus II software create a new Quartus II project with the New Project Wizard 2 On the Tools menu click MegaWizard Plug In Manager to start the MegaWizard Plug In Manager m DDR3 SDRAM Controller with ALTMEMPHY is in the Interfaces folder under the External Memory folder m The ALTMEMPHY megafunction is in the I O folder Ka The variation name must be a different name from the project name and the top level design entity name External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section
38. the steps listed in a procedure Bullets indicate a list of items when the sequence of the items is not important 57 The hand points to information that requires special attention A question mark directs you to a software help system with related information m The feet direct you to another document or website with related information CAUTION A caution calls attention to a condition or possible situation that can damage or destroy the product or your work WARNING A warning calls attention to a condition or possible situation that can cause you injury Lj The envelope links to the Email Subscription Management Center page of the Altera website where you can sign up to receive update notifications for Altera documents External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section II DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
39. to Yes You must always enable the DLL in the memory device Enable the DLL in the Yes or No _ as Altera does not guarantee any ALTMEMPHY memory devices Operation when the DLL is turned off All timings from the memory devices are invalid when the DLL is turned off RZQ in DDR3 SDRAM interfaces are set to 240 Sets ODT disable the on die termination ODT value to either 60 Q ODT Rtt nominal value RZQ 4 RZQ 2 W RZQ 4 120 RZQ 2 or 40 RZQ 6 Set this to RZQ 6 ODT disable if you are not planning to use ODT For a single ranked DIMM set this to RZQ 4 External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide June 2011 Altera Corporation Chapter 3 Parameter Settings ALTMEMPHY Parameter Settings Table 3 4 DDR3 SDRAM Initialization Options Part 2 of 2 3 7 Memory partial array self refresh BA 2 0 000 001 Eighth array BA 2 0 000 Three Quarters array BA 2 0 010 011 100 101 110 111 Parameter Name Range Units Description RZQ in DDR3 SDRAM interfaces are set to 240 Q Sets Dynamic ODT off the memory ODT value during write operations to 60 Q Dynamic ODT value RZQ 4 RZQ W RZQ 4 or 120 Q RZQ 2 As ALTMEMPHY only supports single rank DIMMs you do not need this option set to Dynamic ODT off RZQ in DDR3 SDRAM interfaces are set to 240 Q Sets the output driver impedance from the memory device Out
40. to accept request signals If controller asserts the local_ready signal in the clock cycle that it asserts a read or write request the controller accepts that request The controller deasserts the local_ready signal to indicate that it cannot accept any more requests The controller can buffer eight read or write requests after which the local_ready signal goes low Refresh request acknowledge which the controller asserts for one clock cycle every time it issues a refresh Even if you do not turn on Enable User Auto Refresh Controls 1ocal refresh still indicates to the local interface that the controller has just issued a refresh command Self refresh request acknowledge signal The controller asserts and deasserts this signal in response to the local_self_rfsh_reg signal Auto power down acknowledge signal The controller asserts this signal for one clock cycle every time auto power down is issued Interrupt signal from the ECC logic The controller asserts this signal when the ECC feature is turned on and the controller detects an error local_ready Output local refresh ack Output local self rfsh ack Output local power down ack Output ecc interrupt Output Table 6 10 shows the controller interface signals Table 6 10 Interface Signals Part 1 of 2 Signal Name Direction Description T Bidirectional Memory data bus
41. to data on the bus External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Altera Corporation June 2011 5 22 Chapter 5 Functional Description ALTMEMPHY PHY to Controller Interfaces Figure 5 10 and Figure 5 11 show spaced word unaligned writes and reads Figure 5 10 Word Unaligned Writes 10 1 ctl dqs burst 00 00 ctl wdata valid 00 10 11 0 10 11 01 00 wdata m Decore joooezoe patet RU am 00 we ctl_addr 020000 do Memory fF Interface fe he Be de i ETE IM NE mem clk command amn NA 1 2 3 4 5 Ea cd dd vs dt b vt Ly ctl ctl_wlat ctl cs n 11 P HE uma b 7 Hp amma E fl amm i am Notes to Figure 5 10 1 2 3 4 Alternative word unaligned chip select ct1 cs n As with word aligned writes ct1 burst is asserted one memory clock cycle before valid You can see ctl dqs burst is 11 the same cycle where ct1 wdata validis 10
42. to keep the controller in the memory full clock domain while allowing the local side to run at half the memory clock speed so that latency can be reduced Local interface clock frequency Value that depends on the memory clock frequency and controller data rate Local interface width Value that depends on the memory clock frequency and controller data rate When targeting a HardCopy device migration with performance improvement the ALTMEMPHY IP should target the mid speed grade to ensure that the PLL and the PHY sequencer settings match The compilation of the design can be executed in the faster speed grade External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Chapter 3 Parameter Settings 3 3 ALTMEMPHY Parameter Settings Table 3 2 describes the options available to filter the Memory Presets that are displayed This set of options is where you indicate whether you are creating a datapath for DDR3 SDRAM Table 3 2 Memory Presets List Parameter Name Memory type Description You can filter the type of memory to display for example DDR3 SDRAM Memory vendor You can filter the memory types by vendor JEDEC is also one of the options allowing you to choose the JEDEC specifications If your chosen vendor is not listed you can choose JEDEC for the DDR3 SDRAM interfaces Then pick a device that has similar specifications
43. to your chosen device and check the values of each parameter Make sure you change the each parameter value to match your device specifications Memory format You can filter the type of memory by format for example discrete devices or DIMM packages Maximum frequency You can filter the type of memory by the maximum operating frequency 1 Using the Preset Editor to Create a Custom Memory Preset Pick a device in the Memory Presets list that is closest or the same as the actual memory device that you are using Then click the Modify Parameters button to parameterize the following settings in the Preset Editor dialog box m Memory attributes These are the settings that determine your system s number of DQ DQ strobe DOS address and memory clock pins m Memory initialization options These settings are stored in the memory mode registers as part of the initialization process m Memory timing parameters These are the parameters that create and time constrain the PHY Even though the device you are using is listed in Memory Presets ensure that the settings in the Preset Editor dialog box are accurate as some parameters may have been updated in the memory device datasheets You can change the parameters with a white background to reflect your system You can also change the parameters with a gray background so the device parameters match the device you are using These parameters in gray background are c
44. use controllers with SOPC Builder refer to the ALTMEMPHY Design Tutorials section in volume 5 of the External Memory Interface Handbook For more information on the Quartus II software refer to the Quartus II Help Specifying Parameters To specify the parameters for the DDR3 SDRAM Controller with ALTMEMPHY IP using the SOPC Builder flow perform the following steps 1 In the Quartus II software create a new Quartus II project with the New Project Wizard 2 Onthe Tools menu click SOPC Builder 3 Fora new system specify the system name and language 4 Add DDR3 SDRAM Controller with ALTMEMPHY to your system from the System Contents tab gt The DDR3 SDRAM Controller with ALTMEMPHY is in the SDRAM folder under the Memories and Memory Controllers folder 5 Specify the required parameters on all pages in the Parameter Settings tab 57 To avoid simulation failure you must set Local to Memory Address Mapping to CHP BANK ROW COL if you select High Peformance Controller II for Controller Architecture For detailed explanation of the parameters refer to the Parameter Settings on page 3 1 External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section II DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Chapter 2 Getting Started SOPC Builder Flow June 2011 2 3 6 Click Finish to complete parameterizing the DDR3 SDRAM Controller with ALTMEMPRHY IP and add it to the system Comple
45. wdata ax cb xd Figure 5 7 Half Rate Write with Word Aligned Data LILI LIU UU L 00 10 11 00 ctl dgs burst ctl wdata valid 00 11 X 00 ctl wdata X ba X dc X After calibration process is complete the sequencer sends the write latency in number of clock cycles to the controller Figure 5 8 and Figure 5 9 show word aligned writes and reads In the following read and write examples the data is written to and read from the same address In each example ct1 rdata and ctl wdata are aligned with controller clock ct1_c1k cycles All the data in the bit vector is valid at once For comparison refer Figure 5 10 and Figure 5 11 that show the word unaligned writes and reads The ctl doing rd is represented as a half rate signal when passed into the PHY Therefore the lower half of this bit vector represents one memory clock cycle and the upper half the next memory clock cycle Figure 5 11 on page 5 23 shows separated word unaligned reads as an example of two ct1 doing rd bits are different Therefore for each x16 device at least two ct1 doing rd bits need to be driven and two ctl rdata valid bits need to be interpreted The AFI has the following conventions External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section II DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Chapter 5 Functional Description ALTMEMPHY 5 19 PHY to Controller Interfaces June 2011
46. write before scetarvad commit 31 24 Reserved 0 Reserved for future use June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 6 30 Chapter 6 Functional Description High Performance Controller II Register Maps External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide N DTE RYN 7 Latency Latency is defined using the local user side frequency and absolute time ns There are two types of latencies that exists while designing with memory controllers read and write latencies which have the following definitions m Read latency the amount of time it takes for the read data to appear at the local interface after initiating the read request m Write latency the amount of time it takes for the write data to appear at the memory interface after initiating the write request a gt Fora half rate controller the local side frequency is half of the memory interface frequency Altera defines read and write latencies in terms of the local interface clock frequency and by the absolute time for the memory controllers These latencies apply to supported device families with the half rate DDR3 high performance controller The latency defined in this section uses the following assumptions m The row is already open there is no extra bank management needed m The c
47. 0 Click Finish On the System Contents tab expand Interface Protocols and expand Serial Select JTAG UART and click Add Click Finish If there are warnings about overlapping addresses on the System menu click Auto Assign Base Addresses If you enable ECC and there are warnings about overlapping IRQs on the System menu click Auto Assign IRQs External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 2 4 Qsys Flow Chapter 2 Getting Started Qsys Flow 8 For this example system ensure all the other modules are clocked on the altmemddr_sysclk to avoid any unnecessary clock domain crossing logic 9 Click Generate La Among the files generated by SOPC Builder is the Quartus File qip This file contains information about a generated IP core or system In most cases the qip file contains all of the necessary assignments and information required to process the MegaCore function or system in the Quartus II compiler Generally a single qip file is generated for each SOPC Builder system However some more complex SOPC Builder components generate a separate qip file In that case the system qip file references the component qip file 10 Compile your design refer to Compiling and Simulating on page 4 1 The Qsys flow allows you to add the DDR3 SDRAM Controller with ALTMEMPHY directly to a new or existing Osys system You can also easily add
48. 0 of a memory clock cycle Data reads from the DIMM are performed for each phase position and a data valid window is located which is the set of resynchronization clock phase positions where data is successfully read The final resynchronization clock phase is set at the center of this range the center of the data valid window or CODVW This output is set to the current calculated value for the CODVW and represents how many phase steps were performed by the PLL to offset the resynchronization clock from the memory clock rsu codvw size Output The final centre of data valid window size rsu_codvw_size is the number of phases where data was successfully read in the calculation of the resynchronization clock centre of data valid window phase rsu_codvw_phase rsu_read_latency Output The rsu_read_latency output is then set to the read latency in phy clk cycles using the rsu_codvw_phase resynchronization clock phase If calibration is unsuccessful then this signal is undefined rsu no dvw err Output If the sequencer sweeps the resynchronization clock across every phase and does not see any valid data at any phase position then calibration fails and this output is set to 1 rsu grt one dvw err Output If the sequencer sweeps the resynchronization clock across every phase and sees multiple data valid windows this is indicative of unexpected read data random bit errors or an incorrectly config
49. 0 ps tis 65 1000 ps tRRD 2 06 64 ns June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 3 10 Chapter 3 Parameter Settings ALTMEMPHY Parameter Settings Derating Memory Setup and Hold Timing Because the base setup and hold time specifications from the memory device datasheet assume input slew rates that may not be true for Altera devices derate and update the following memory device specifications in the Preset Editor dialog box tps B B tH ts 57 For Arria GX devices you need not derate using the Preset Editor You only need to enter the parameters referenced to and the deration is done automatically when you enter the slew rate information on the Board Settings tab After derating the values you then need to normalize the derated value because Altera input and output timing specifications are referenced to When the memory device setup and hold time numbers are derated and normalized to update these values in the Preset Editor dialog box to ensure that your timing constraints are correct The following memory device specifications and update the Preset Editor dialog box with the derated value For example according to JEDEC 533 MHz DDR3 SDRAM has the following specifications assuming 1V ns DQ slew rate rising signal and 2V ns DQS DQSn slew rate m Base tps 2
50. 00 018 RO mem_dq 7 0 00 00 Mo 00 X 00 18 00 mem_odt 1 0 00 E 10 y 6 11 910 05 eoueuuojieg uDIH 304 sweifeig 8 1934249 1 8 Chapter 8 Timing Diagrams DDR3 High Performance Controller 11 June 2011 8 15 The following sequence corresponds with the numbered items in Figure 8 8 1 10 11 12 Altera Corporation The user logic requests the first write by asserting the 1ocal write reqsignal and the size and address for this write In this example the request is a burst length of 1 to a local address 0x000002 This local address is mapped to the following memory address in half rate mode mem row address 0x0000 mem col address 0x0002 2 0x0008 mem bank address 0x00 The user logic initiates the first read to the same address as the first write The request for the read is a burst length of 1 The controller continues to accept commands until the command queue is full When the command queue is full the controller deasserts the 1ocal ready signal The starting local address 0 000002 is mapped to the following memory address in half rate mode mem row address 0x0000 mem col address 0x0002 2 0x0008 mem bank address 0x00 The user logic asserts a second 1ocal write req signal with a size of 1 and address of 0x000004 The user logic asserts a second 1ocal read reqsignal with a size of 1 and addres
51. 00001 000003 0000001 y 0000003 0000005 local_size 4 0 2 local ready local_burstbegin local be 3 0 local write req local wdata 31 0 Controller AFI afi addi 27 0 ee vL f PLS VS VWF 1 0010004 0000000 0020008 0000000 1 030006 0000000 0040010 0000000 afi ba 5 0 afi cs n 0 A 8 I F J I F Command 2 0 wal NOP WR I wea NO WR afi dm 3 0 Lo I F afi_wlat 4 0 afi_dgs_burst 0 J afi_dgs_burst 1 N afi wdata 31 0 ABD EEFF0011 afi wdata valid 1 0 is 341 0 1 3 C3 1 9 1 3 I AFI Memory Interface mem cke 1 0 UUUUUU TUUU memck _ TUU LULU mem ba 2 0 200130 000 I 0000 00 00 00 I 00 10 LI Command 2 0 WR wa I J MP mem_dgs mem dir EE MFE 00 Docpepep 00 Moo FF EE 8 7 mem_da 7 0 mem 001 9 0 09 eoueuuouedg ubiH euaa sweifeig 8 193deug 8 8 Chapter 8 Timing Diagrams DDR3 High Performance Controller 11 June 2011 Th
52. 1 About This IP Unsupported Features Features Additive latency HPC II Support for arbitrary Avalon burst length Built in flexible memory burst adapter Configurable Local to Memory address mappings Optional run time configuration of size and mode register settings and memory timing Partial array self refresh PASR Support for industry standard DDR3 SDRAM devices Optional support for self refresh command lt lt lt 50555 Optional support for user controlled power down command Optional support for automatic power down command with programmable time out Optional support for auto precharge read and auto precharge write commands Optional support for user controller refresh Optional multiple controller clock sharing in SOPC Builder Flow Integrated error correction coding ECC function 72 bit Integrated ECC function 16 24 and 40 bit Support for partial word write with optional automatic error correction SOPC Builder ready amp Support for Plus evaluation IP functional simulation models for use in Altera supported VHDL and Verilog HDL simulator Notes to Table 1 3 1 HPC supports additive latency values greater or equal to 1 in clock cycle unit 2 This feature is not supported with DDR3 SDRAM with leveling Unsupported Features External Memory Interface Ha
53. 23 Reserved Reserved for future use 30 24 Reserved Reserved for future use 0x120 7 0 Column address width Read write The number of column address bits for the memory devices in your memory interface The range of legal values is 7 12 15 8 Row address width Read write The number of row address bits for the memory devices in your memory interface The range of legal values is 12 16 19 16 Bank address width Read write The number of bank address bits for the memory devices in your memory interface The range of legal values is 2 3 23 20 Chip select address width Read write The number of chip select address bits for the memory devices in your memory interface The range of legal values is 0 2 If there is only one single chip select in the memory interface set this bit to 0 31 24 Reserved Reserved for future use 0x121 31 0 Data width representation word Read only The number of DQS bits in the memory interface This bit can be used to derive the width of the memory interface by multiplying this value by the number of DQ pins per 00 pin typically 8 0x122 7 0 Chip select representation Read only The number of chip select in binary representation For example a design with 2 chip selects has the value of 00000011 31 8 Reserved Reserved for future use External Memory Interface Handboo
54. 5 m Base 100 m Vggg 0 175 V m Vygj dc 0 100 V m Vggg 0 175 V m Vggg 0 100 V The referenced setup and hold signals for a rising edge are tps tps delta tps Vrep slew_rate 25 0 175 200 tpH delta tpH Vy de Vrer slew_rate 100 0 100 200 ps If the output slew rate of the write data is different from 1V ns you have to first derate the tpg values then translate these AC DC level specs to specification For a 2V ns DQ slew rate rising signal and 2V ns DOS DOSn slew rate tps VREP Base tps delta tps Vrep slew_rate 25 88 87 5 200 5 tpH tpH delta tpH Vrep slew_rate 100 50 50 200 External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section II DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Chapter 3 Parameter Settings ALTMEMPHY Parameter Settings 3 11 For a 0 5V ns DQ slew rate rising signal 1V ns DQS DQSn slew rate tps Vggr Base tps ps delta tps Vggp slew rate 25 5 350 380 toy VREF Base delta toy Vngp slew rate 100 10 200 310 PHY Settings Click Next or the PHY Settings tab to set the options described in Table 3 6 T
55. External Memory Interface Handbook Volume 3 Section DDR3 SDRAM Controller with ALTMEMPHY User Guide RYAN 101 Innovation Drive San Jose CA 95134 www altera com EMI_DDR3_UG 3 0 Document last updated for Altera Complete Design Suite version Document publication date 11 0 June 2011 Li Subscribe 2011 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX are Reg U S Pat amp Tm Off and or trademarks of Altera Corporation in the U S and other countries All other trademarks and service marks are the property of their respective holders as described at www altera ccom common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or ic liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera Quality customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or 150 90012008 services NSAI Certified External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section Il DDR3 SDRAM Controller with ALT
56. I Command 2 0 afi dm 3 0 wlat 4 0 afi das 0500 afi das afi wdata 31 0 afi wdata valid 1 0 AFI Memory Interface mem cke mem clk mem ba 2 0 mem addi 13 0 mem cs n 0 Mem Command 2 0 mem 005 mem dm mem do 7 0 mem 0410 ru ru UJ External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section 1 DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Chapter 8 Timing Diagrams DDR3 High Performance Controller 11 June 2011 8 13 The following sequence corresponds with the numbered items in Figure 8 7 1 Altera Corporation The user logic asserts the first local write req signal with a size of 1 and address of 0x000000 The 1ocal ready signal is asserted along with the local write signal which indicates that the controller has accepted this request and the user logic can request another read or write in the following clock cycle If the 1ocal ready signal was not asserted the user logic must keep the write request size and address signals asserted until the 1ocal ready signal is registered high The local address 0x000000 is mapped to the foll
57. LTMEMPHY Parameter Settings The Memory Settings PHY Settings and Board Settings tabs provide the same options as in the ALTMEMPHY Parameter Settings page Figure 3 3 DDR3 SDRAM Controller with ALTMEMPHY Settings MegaWizard Plug In Manager DDR3 SDRAM Controller with ALTMEMPHY DDR3 SDRAM Controller with ALTMEMPH PHY Settings gt Board Settings gt Controller Architecture High Performance Controller Il 7 High Performance Controller Low Power Mode C Enable Self Refresh Controls _ Enable Auto Power Down Auto Power Down Cycles Efficiency C Enable User Auto Refresh Controls C Enable Auto Precharge Control Enable Reordering Starvation limit for each command 0 commands Local to Memory Address Mapping CHIP ROW BANK COL Command Queue Look Ahead Depth 4 Local Maximum Burst Count Reduce Controller Latency By Advanced Features C Enable Configuration and Status Register Interface C Enable Error Detection and Correction Logic Number of Banks to Track Multiple Controller Clock Sharing Local Interface Protocol I Info The PLL will be generated with Memory clock frequency 300 0 MHz and 32 phase steps per cycle Controller Settings gt This section describes parameters for the High Performance Controller HPC II with advanced features introduced in version 11 0 for designs generated in version 11 0 Designs cre
58. Level File Both the memory models display similar behaviors and have the same calibration time s The memory model lt variation name gt _test_component v vhd used in SOPC Builder designs is actually a variation of the full array memory model To ensure your simulation works in SOPC Builder use memory model with less than 512 Mbit capacity Example Driver The example driver is a self checking test pattern generator for the memory interface It uses a state machine to write and read from the memory to verify that the interface is operating correctly The example driver performs the following tests and loops back the tests indefinitely June 2011 Altera Corporation Sequential addressing writes and reads The state machine writes pseudo random data generated by a linear feedback shift register LFSR to a set of incrementing row bank and column addresses The state machine then resets the LFSR reads back the same set of addresses and compares the data it receives against the expected data You can adjust the length and pattern of the bursts that are written by changing the MAX_ROW MAX_BANK and MAX COL constants in the example driver source code and the entire memory space can be tested by adjusting these values You can skip this test by setting the test seq addr on signal to logic zero Incomplete write operation The state machine issues a series of write requests that are less than the maximum burst size supported by you
59. M to the PHY to indicate that a parity error has occured for a particular cycle DDR3 SDRAM only Notes to Table 6 10 1 This signal is for registered DIMMs only Table 6 11 shows the CSR interface signals Table 6 11 CSR Interface Signals Signal Name Direction Description csr addr Input Register map address The width of is 16 bits Byte enable signal which you use to mask off individual bytes during writes gerer Input csr be is active high csr_wdata Input Write data bus The width of is 32 bits Write request signal You cannot assert csr write reqandcsr read req csr write req Input signals at the same time ay Sand ze input Read request signal You cannot assert csr_read_req and red csr_write req signals at the same time csr_rdata Output Read data bus The width of csr_rdata is 32 bits Output Read data valid signal The csr_rdata_valid signal indicates that valid data is present on the read data bus The csr_waitrequest signal indicates that the HPC II is busy and not ready to accept request signals If the csr_waitrequest signal goes high in the csr_waitrequest Output clock cycle when a read or write request is asserted that request is not accepted If the csr_waitrequest signal goes low the HPC II is then ready to accept more requests Sequence of Operations This section explains how the various blo
60. MEMPHY IP User Guide N DTE SYN Contents Chapter 1 About This IP Release Informations create ee bbs eere eere 1 2 Device Family Support dide 1 2 Features Laake ve we lo eic de 1 3 Unsupp rted feats sare 1 4 MegaGCore Verification eene a eed ebbe ccrte 1 5 Resource E 1 5 System Requirements 1 2 1 5 Installation and Licensing ree eee dote fed ad esee utr eee deett eS 1 6 Free Evaluation 1 6 OpenCore Plus Time Out 1 7 Chapter 2 Getting Started BLOW EET 2 1 SOPC Builder rid teg ea ted est ceti 2 2 Specifying Parameters 4 2 site iad a de tera ioc pee decidi ed aa edo eoe ect s 2 2 Completing the SOPC Builder System 2 2 2 3 OS VS FLOW qe D 2 4 Specifying Parameters ee Sn walk ne te Rer edi ertet d eet pde e d urn 2 4 Completing the Osys System 2 5 MegaWizard Plug In Manager Flow
61. PHY IP User Guide 8 16 Chapter 8 Timing Diagrams DDR3 High Performance Controller 11 13 The controller returns the first read data to the user by asserting the local_rdata_valid signal when there is valid read data on the local_rdata bus If the ECC logic is disabled there is no delay between the afi_rdata and the local_rdata buses If there is ECC logic in the controller there is one or three clock cycles of delay between the afi rdata and local rdata buses External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section 1 DDR3 SDRAM Controller with ALTMEMPHY IP User Guide RA Additional Information This chapter provides additional information about the document and Altera Document Revision History The following table shows the revision history for this document Date Version Changes m Removed High Performance Controller information June 2011 30 m Updated High Performance Controller II information m Removed HardCopy Ill HardCopy IV E HardCopy IV GX Stratix and Stratix IV support December 2010 24 Updated for 10 1 m Added information for new GUI parameters Controller latency Enable reduced bank July 2010 20 tracking for area optimization and Number of banks to track u d m Removed information about IP Advisor This feature is removed from the DDR3 SDRAM IP support for version 10 0 February 2010 1 3 Corrected typos m Full support for Stratix IV devi
62. PHY Signals Table 5 3 AFI Signals Part 3 of 4 5 13 Signal Name ctl wlat Type Output Width 1 Description Required write latency between address command and write data that is issued to ALTMEMPHY controller local interface This signal is only valid when the ALTMEMPHY sequencer successfully completes calibration and does not change at any point during normal operation The legal range of values for this signal is 0 to 31 and the typical values are between 0 and ten 0 mostly for low CAS latency DDR memory types Read Data Interface ctl doing rd Input MEM IF DQS WIDTHx DWIDTH RATIO 2 Doing read input Indicates that the DDR3 SDRAM controller is currently performing a read operation The controller generates cc1 doing rdto the ALTMEMPHY megafunction The cti doing rd signal is asserted for one phy cycle for every read command it issues If there are two read commands 1 doing rd is asserted for two phy clk cycles The ct1 doing signal also enables the capture registers and generates the ctl mem rdata valid Signal The ctl doing signal should be issued at the same time the read command is sent to the ALTMEMPHY megafunction ctl rdata Output DWIDTH RATIO x MEM IF DWIDTH Read data from the PHY to the controller ctl rdata valid Output DWIDTH RATIO 2 Read data valid indicating valid read data on ctl rdata This signal is two bits wide as only
63. SDRAM is used the interface timing is identical for DDR3 devices An 8 bit interface with one chip select The data for one controller clock ct1_c1k cycle represents data for two memory clock mem 1 cycles half rate interface External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 5 20 Chapter 5 Functional Description ALTMEMPHY PHY to Controller Interfaces Figure 5 8 Word Aligned Writes als LAA AAA 2 ctl_wlat cil ras n ctl cas n ctl we n cll cs n ctl 005 burst ctl wdata valid Memory Interface i3 mem clk NE E xn p 77 command WR E AE Note 5 221 1 1 1 1 mem dqs U i J 1 Ji V mem_dq Notes to Figure 5 8 1 To show the even alignment of ct1 cs n expand the signal this convention applies for all other signals 2 The ctl_dgs_ burst must go high one memory clock cycle before ct1_wdata_valid Compare with the word unaligned case 3 The ctl_wdata_valid is asserted two ct1 wlat controller clock ct1_c1k cycles after chip select ct1_cs_n is asserted The ct1_wlat indicates the required write latency in the system The value is determined during
64. With the AFI high and low signals are combined in one signal so for a single chip select ctl_cs_n interface ct1 cs n 1 0 where location 0 appears on the memory bus on one 1 cycle and location 1 on the next mem 1 cycle This convention is maintained for all signals so for an 8 bit memory interface the write data ct1 wdata signalis ctl wdata 31 0 where the first data on the DQ pins is ctl_wdata 7 0 then ct1 wdata 15 8 then ctl _wdata 23 16 then ctl wdata 31 24 Word aligned and word unaligned reads and writes have the following definitions m Word aligned for the single chip select is active low in location 1 _1 ctl cs n 1 0 01 when a write occurs This alignment is the easiest alignment to design with m Word unaligned is the opposite so ct1 cs n 1 0 10 when a read or write occurs and the other control and data signals are distributed across consecutive ctl clk cycles The Altera high performance controller uses word aligned data only The timing analysis script does not support word unaligned reads and writes Spaced reads and writes have the following definitions m Spaced writes write commands separated by a gap of one controller clock ctl clk cycle m Spaced reads read commands separated by a gap of one controller clock ctl clk cycle Figure 5 8 through Figure 5 11 assume the following general points Altera Corporation The burst length is four A DDR2
65. afunction the number of clock cycles of read data it must expect for the first read The ALTMEMPHY megafunction uses the doing rd signal to enable its capture registers for the expected duration of memory burst The ALTMEMPHY megafunction issues the first read command to the memory and captures the read data from the memory The ALTMEMPHY megafunction returns the first data read to the controller after resynchronizing the data to the phy_clk domain by asserting the afi rdata validsignal when there is valid read data on the rdata bus The controller returns the first read data to the user by asserting the local rdata validsignal when there is valid read data on the local_rdata bus If the ECC logic is disabled there is no delay between the afi rdata and the local rdata buses If there is ECC logic in the controller there is one or three clock cycles of delay between the afi rdata and local rdata buses External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide BPIND 1951 dl AHdINIALLTV 191104109 NVHOS II 1011295 euinjoA eoeji91u Jeul9 X3 1106 eunr 012100109 Bally Half Rate Write Non Burst Aligned Address Figure 8 4 Half Rate Write Operation for HPC II Non Burst Aligned Address 3 4 1 1 2 Local Interface I I local address 25 0 00
66. and when released the calibration process begins again Other Local Interface Requirements The memory burst length for DDR3 SDRAM devices can be set at either four or eight but when using the Altera high performance controller only burst length eight is supported For a half rate controller the memory clock runs twice as fast as the clock provided to the local interface so data buses on the local interface are four times as wide as the memory data bus Address and Command Interfacing Address and command signals are automatically sized for 1T operation such that for full rate designs there is one input bit per pin for example one cs n input per chip select configured for half rate designs there are two If you require a more conservative 2T address and command scheme use a full rate design and drive the address command inputs for two clock cycles or in a half rate design drive both address command bits for a given pin identically Although the PHY inherently supports 1T addressing the high performance controller supports only 2T addressing so PHY timing analysis is performed assuming 27 address and command signals Handshake Mechanism Between Read Commands and Read Data When performing a read a high performance controller with the AFI asserts ctl doing read to indicate that a read command is requested and the byte lanes that it expects valid data to return on ALTMEMPHY uses ct1 doing read for the following actions m Co
67. are received the arbiter uses arbitration rules to determine the order in which to pass requests to the memory device Arbitration Rules The arbiter follows the following arbitration rules m If only one master is issuing a request grant that request immediately m If there are outstanding requests from two or more masters the arbiter applies the following tests in order Is there a read request If so the arbiter grants the read request ahead of any write requests b Ifneither of the above conditions apply the arbiter grants the oldest request first Rank Timer The rank timer maintains rank specific timing information and performs the following functions m Ensures that only four activates occur within a specified timing window m Manages the read to write and write to read bus turnaround time m Manages the time to activate delay between different banks Read Data Buffer The read data buffer receives data from the PHY and passes that data through the input interface to the master Write Data Buffer The write data buffer receives write data from the input interface and passes that data to the PHY upon approval of the write request ECC Block The error correcting code ECC block comprises an encoder and a decoder corrector which can detect and correct single bit errors and detect double bit errors The ECC block can remedy errors resulting from noise or other impairments during data transmission Alte
68. artial write which is effectively a read modify write event The partial write corrects the data at that address and writes it back Partial Writes The ECC logic supports partial writes Along with the address data and burst signals the Avalon MM interface also supports a signal vector 1ocal be that is responsible for byte enable Every bit of this signal vector represents a byte on the data bus Thus a logic low on any of these bits instructs the controller not to write to that particular byte resulting in a partial write The ECC code is calculated on all bytes of the data bus If any bytes are changed the IP core must recalculate the ECC code and write the new code back to the memory For partial writes the ECC logic performs the following steps 1 The ECC logic sends a read command to the partial write address 2 Upon receiving a return data from the memory for the particular address the ECC logic decodes the data checks for errors and then merges the corrected or correct dataword with the incoming information 3 The ECC logic issues a write to write back the updated data and the new ECC code The following corner cases can occur m single bit error during the read phase of the read modify write process In this case the IP core corrects the single bit error first increments the single bit error counter and then performs a partial write to this corrected decoded data word m A double bit error during the read phase
69. as a stand alone product use with either custom or third party controllers June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Release Information Chapter 1 About This IP Release Information Table 1 1 provides information about this release of the DDR3 SDRAM Controller with ALTMEMPHY IP Table 1 1 Release Information Item Description Version 11 0 Release Date May 2011 Ordering Codes IP HPMCII HPC II 00C2 DDR3 SDRAM Product IDs 00 0 ALTMEMPHY Megafunction Vendor ID 6AF7 Altera verifies that the current version of the Quartus II software compiles the previous version of each MegaCore function The MegaCore IP Library Release Notes and Errata report any exceptions to this verification Altera does not verify compilation with MegaCore function versions older than one release For information about issues on the DDR3 SDRAM high performance controller and the ALTMEMPHY megafunction in a particular Quartus II version refer to the Quartus II Software Release Notes Device Family Support The MegaCore function provides either final or preliminary support for target Altera device families m Final support means the core is verified with final timing models for this device family The core meets all functional and timing requirements for the device family and can be used in production designs m Preliminar
70. at signal is only valid when the calibration has been successfully completed by the ALTMEMPHY sequencer and does not change at any point during normal user mode operation Figure 5 14 shows the operation of ct1 wlat port Figure 5 14 Timing for ctl 045 burst ctl wdata valid Address and Command Half Rate Design ctl wlat 2 cil ctl_addr ctl_cs_n ctl_dqs_burst ctl_wdata_valid i_cola ees For a half rate design ctl cs nis 2 bits not 1 Also the ct1 dqs burst and ctl wdata valid waveforms indicate a half rate design This write results in a burst of 8 at the DDR Where ct1 cs nis driven 2 b01 the LSB 1 is the first value driven out of mem cs n and the MSB 0 follows on the next mem 1 Similarly for ctl dqs burst the LSB is driven out of mem first 0 then a 1 follows on the next clock cycle This sequence produces the continuous DOS pulse as required Finally the ctl bus is twice MEM IF ADDR WIDTH bits wide and so the address is concatenated to result in an address phase two mem 1 cycles wide Partial Writes As part of the DDR3 SDRAM memory specifications you have the option for partial write operations by asserting the DM pins for part of the write signal For designs targeting the Arria II devices deassert the ct1 wdata valid signal during partial writes when the write data is invalid to save power by not
71. ated in earlier versions and regenerated in version 11 0 do not inherit the new advanced features for information on parameters for HPC II without the version 11 0 advanced features refer to the External Memory Interface Handbook for Quartus II version 10 1 available in the External Memory Interfaces section of the Altera Literature website June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 3 14 Chapter 3 Parameter Settings DDR3 SDRAM Controller with ALTMEMPHY Parameter Settings Table 3 8 shows the options provided on the Controller Settings tab Table 3 8 Controller Settings Part 1 of 2 Parameter Description Controller architecture Specifies the controller architecture Turn on to enable the controller to allow you to have control on Enable self refresh controls when to place the external memory device in self refresh mode refer to User Controlled Self Refresh on page 6 5 Turn on to enable the controller to allow you to have control on when to place the external memory device in power down mode Turn on to enable the controller to automatically place the external memory device in power down mode after a specified number of idle controller clock cycles is observed in the controller You can Enable auto power down specify the number of idle cycles after which the controller powers down the memory in the Auto Power Down Cycles field refe
72. ation m Data demultiplexing and alignment As the DOS DOSn signal is not continuous the PHY also has postamble protection logic to ensure that any glitches on the DOS input signals at the end of the read postamble time do not cause erroneous data to be captured as a result of postamble glitches External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section II DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Chapter 5 Functional Description ALTMEMPHY 5 9 Block Description Figure 5 4 shows the order of the functions performed by the read datapath and the frequency at which the read data is handled Figure 5 4 0083 SDRAM Read Datapath in Arria GX Devices DDR SDR SDR HDR Data Demux and Alignment Data Capture IOE RAM Block DQS DQ n gt D Q D Q wr data 2n rd data 4n gt wr rd clk lt D Q FIFO of phy_clk_1x resync_clk_2x 10 Data Capture and Resynchronization The data capture and resynchronization registers for Arria II GX devices are implemented in the I O element IOE to achieve maximum performance Data capture and resynchronization is the process of capturing the read data DQ with the DQS DOQSn strobes and resynchronizing the captured data to an internal free running full rate clock supplied by the enhanced PLL The resynchronization clock is an intermediate clock whose phase shift i
73. bit bus notation for the single bit memory interface signals for example mem dqs rather than mem dgs 0 in the Tcl script you should change set single bit 0 to set single bit or External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section II DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Chapter 4 Compiling and Simulating 4 3 Compiling the Design June 2011 Altera Corporation Alternatively to change the pin names that do not match the design you can add a prefix to your pin names by performing the following steps a On the Assignments menu click Pin Planner b On the Edit menu click Create Import Megafunction c Select Import an existing custom megafunction and navigate to variation name gt ppf d Type the prefix you want to use in Instance name For example change mem_addr to corel_mem_addr Set the top level entity to the top level design a On the File menu click Open b Browse to your SOPC Builder system top level design or lt variation name gt _example_top if you are using MegaWizard Plug In Manager and click Open c On the Project menu click Set as Top Level Entity Assign the DQ and DQS pin locations a You should assign pin locations to the pins in your design so the Quartus II software can perform fitting and timing analysis correctly b Use either the Pin Planner or Assignment Editor to assign the clock source pin manually Also choose which DQS pin
74. ble 64 bit version of ECC decoder alt mem ddrx ecc encoder v Instantiates appropriate width ECC encoder logic alt mem ddrx ecc encoder 32 syn v Contains synthesizable 32 bit version of ECC decoder alt mem ddrx ecc encoder 64 syn v Contains synthesizable 64 bit version of ECC decoder alt mem ddrx ecc encoder decoder wrapper v Wrapper that instantiates all ECC logic alt mem ddrx input if v Contains local input interface logic alt mem ddrx mm st converter v Contains supporting logic for Avalon MM interface alt mem ddrx rank timer v Contains a timer associated with rank timing alt mem ddrx sideband v Contains supporting logic for user controlled refresh and precharge signals alt mem ddrx tbp v Contains command queue and associated logic for reordering features alt mem ddrx timing param v Contains timer logic associated with nonrank timing alt mem controller st top v Wrapper that instantiates all submodules amd configuration registers alt mem ddrx controller top v Wrapper that contains memory controller with Avalon MM interface alt mem d rx controller v Wrapper that instantiates all submodules June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 2 12 Chapter 2 Getting Started Generated Files External Mem
75. bration control and status interface Debug interface Table 5 2 Interface to the DDR3 SDRAM Devices Note 1 Signal Name Type Width 2 Description em addr Output EM IF ROWADDR WIDTH The memory row and column address bus em ba Output EM IF BANKADDR WIDTH The memory bank address bus em cas n Output 1 The memory column address strobe em_cke Output EM IF CS WIDTH The memory clock enable em clk Bidirectional IF CLK PAIR COUNT The memory clock positive edge clock 3 em clk n Bidirectional IF CLK PAIR COUNT The memory clock negative edge clock em cs n Output EM IF CS WIDTH The memory chip select signal em dm Output EM IF DM WIDTH The optional memory DM bus External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section II DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Chapter 5 Functional Description ALTMEMPHY 5 11 ALTMEMPHY Signals Table 5 2 Interface to the DDR3 SDRAM Devices Note 1 Signal Name Type Width 2 Description em dq Bidirectional MEM IF DWIDTH The memory bidirectional data bus M EM IF DWIDTH em 498 Bidirectional EM IF DQ PER DOS The memory bidirectional data strobe bus IF DWIDTH OE em dgs n Bidirectional EM IF DQ PER DOS The memory bidirectional data strobe bus em odt Output EM IF CS WIDTH The memory on d
76. buffer and determines the most efficient autoprecharge operation to perform reordering commands if necessary local self rfsh chip Input Controls which chip to issue the user refresh to The IP core uses this active high signal with local self rfsh req This signal is as wide as the memory chip select This signal asserts a high value to each bit that represents the refresh for the corresponding memory chip For example If 1ocal self rfsh chip signal is assigned with a value of 4 b0101 the controller refreshes the memory chips 0 and 2 and memory chips 1 and 3 are not refreshed local self rfsh req Input User control of the self refresh feature If you turn on Enable Self Refresh Controls you can request that the controller place the memory devices into a self refresh state by asserting this signal The controller places the memory in the self refresh state as soon as it can without violating the relevant timing parameters and responds by asserting local self rfsh You hold the memory in the self refresh state by keeping this signal asserted You can release the memory from the self refresh state at any time by deasserting local self rfsh reqand the controller responds by deasserting local self rfsh ack when it has successfully brought the memory out of the self refresh state local init done Output When the memory initialization training and calibration are complete the PHY sequencer asserts
77. ccess to the same bank is quicker This command is useful for applications that require fast random accesses Since the controller can reorder transactions for best efficiency when you assert the local_autopch_req signal the controller evaluates the current command and buffered commands to determine the best autoprecharge operation Address and Command Decoding Logic When the main state machine issues a command to the memory it asserts a set of internal signals The address and command decoding logic turns these signals into AFlI specific commands and address This block generates the following signals m Clockenable and reset signals afi cke afi rst n m Command and address signals afi cs n afi ba afi addr afi ras n afi cas n afi we n Low Power Logic s There are two types of low power logic the user controlled self refresh logic and automatic power down with programmable time out logic User Controlled Self Refresh When you assert the 1ocal self rfsh req signal the controller completes currently executing reads and writes and then interrupts the command queue and immediately places the memory into self refresh mode When the controller places the memory into self refresh mode it responds by asserting an acknowledge signal local self rfsh ack You can leave the memory in self refresh mode for as long as you choose To bring the memory out of self refresh mode you must deassert the request signal and the c
78. ccur CORDROP ERROR Read only Value is set to 1 when any controller scheduled autoconnections are dropped 7 3 Reserved Reserved for future use 15 8 SBE_COUNT Read only Reports the number of single bit errors that have occurred since the status register counters were last cleared 23 16 DBE_COUNT Read only Reports the number of double bit errors that have occurred since the status register counters were last cleared 31 24 CORDROP_COUNT Read only Reports the number of controller scheduled autocorrections dropped since the status register counters were last cleared 0x132 ERR_ADDR Read only The address of the most recent ECC error This address is a memory burst aligned local address External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide June 2011 Altera Corporation Chapter 6 Functional Description High Performance Controller 11 Register Maps Table 6 17 Controller Register Map Part 5 of 5 6 29 Address Bit Name Default Access Description The address of the most recent 0x133 31 0 CORDROP_ADDR 0 Read only autocorrection that was dropped This is a memory burst aligned local address 0 REORDER_DATA Read write 15 1 Reserved 0 Reserved for future use 0x134 4 Number of commands that can be served 23 16 STARVE LIMIT 0 Read
79. ces m Added information for Register Control Word parameters February 2010 1 2 m Added descriptions for mem ac parity mem_err_out_n and parity error n signals m Added timing diagrams for initialization and calibration stages for HPC November 2009 1 1 Minor corrections November 2009 1 0 First published How to Contact Altera To locate the most up to date information about Altera products refer to the June 2011 following table Contact 1 Contact Method Address Technical support Website www altera com support Website www altera com training Technical training Email custrain altera com Product literature Website www altera com literature Non technical support General Email nacomp altera com Software Licensing Email authorization altera com Note to Table 1 You can also contact your local Altera sales office or sales representative Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Info 2 Chapter Typographic Conventions Typographic Conventions The following table shows the typographic conventions this document uses Visual Cue Bold Type with Initial Capital Letters Indicate command names dialog box titles dialog box options and other GUI labels For example Save As dialog box For GUI elements capitalization matches the GUI bold type Indicates directory names pr
80. cess Read write Description When this bit equals 1 it enables the generation and checking of ECC This bit is only active if ECC was enabled during IP parameterization ENABLE_AUTO_CORR Read write When this bit equals 1 it enables auto correction when a single bit error is detected GEN_SBE Read write When this bit equals 1 it enables the deliberate insertion of single bit errors bit 0 in the data written to memory This bit is used only for testing purposes GEN_DBE Read write When this bit equals 1 it enables the deliberate insertion of double bit errors bits 0 and 1 in the data written to memory This bit is used only for testing purposes ENABLE INTR Read write When this bit equals 1 it enables the interrupt output MASK SBE INTR Read write When this bit equals 1 it masks the single bit error interrupt MASK DBE INTR Read write When this bit equals 1 it masks the double bit error interrupt CLEAR Read write When this bit equals 1 writing to this self clearing bit clears the interrupt signal and the error status and error address registers MASK CORDROP INTR Read write When this bit equals 1 the dropped autocorrection error interrupt is dropped Reserved Reserved for future use 0x131 SBE ERROR Read only Set to 1 when any single bit errors occur DBE ERROR Read only Set to 1 when any double bit errors o
81. cks pass information in common situations Write Command When a requesting master issues a write command together with write data the following events occur m The input interface accepts the write command and the write data m The input interface passes the write command to the command generator and the write data to the write data buffer m The command generator processes the command and sends it to the timing bank pool m Once all timing requirements are met and a write data ready notification has been received from the write data buffer the timing bank pool sends the command to the arbiter m Whenrank timing requirements are met the arbiter grants the command request from the timing bank pool and passes the write command to the AFI interface External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide June 2011 Altera Corporation Chapter 6 Functional Description High Performance Controller 11 6 19 Sequence of Operations The AFI interface receives the write command from the arbiter and requests the corresponding write data from the write data buffer The PHY receives the write command and the write data through the AFI interface Read Command When a requesting master issues a read command the following events occur The input interface accepts the read command The input interface passes the read command to the command generator The command generator
82. compiled the example top level file you can perform RTL simulation or program your targeted Altera device to verify the example top level file in hardware Simulating the Design During system generation SOPC Builder optionally generates a simulation model and testbench for the entire system which you can use to easily simulate your system in any of Altera s supported simulation tools The MegaWizard also generates a set of ModelSim Tel scripts and macros that you can use to compile the testbench IP functional simulation models and plain text RTL design files that describe your system in the ModelSim simulation software refer to Generated Files on page 2 8 For more information about simulating SOPC Builder systems refer to volume 4 of the Quartus II Handbook and AN 351 Simulating Nios II Embedded Processor Designs For more information about how to include your board simulation results in the Quartus II software and how to assign pins using pin planners refer to ALTMEMPHY Design Tutorials section in volume 5 of the External Memory Interface Handbook You have the following three simulation options m Skip calibration performs a static setup of the ALTMEMPHY megafunction to skip calibration and go straight into user mode Available for x4 and x8 DDR3 SDRAM Skip calibration simulation is supported for 300 MHz through 400 MHz There is no calibration in this simulation mode As no phase calibration is performed there must be
83. d by other system reset logic p Causes a complete reset of PHY but not the PLL used in the PHY June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 5 12 Table 5 3 AFI Signals Part 2 of 4 Chapter 5 Functional Description ALTMEMPHY ALTMEMPHY Signals Signal Name reset request n Type Output Width 1 Description Directly connected to the locked output of the PLL and is intended for optional use either by automated tools such as SOPC Builder or could be manually ANDed with any other system level signals and combined with any edge detect logic as required and then fed back to the g1obal reset ninput Reset request output that indicates when the PLL outputs are not locked Use this as a reset request input to any system level reset controller you may have This signal is always low while the PLL is locking but not locked and so any reset logic using it is advised to detect a reset request on a falling edge rather than by level detection ctl clk Output Half rate clock supplied to controller and system logic The same signal as the non AFl phy ctl reset n Output Reset output on ct1 clock domain Other Signals aux half rate clk Output In half rate designs a copy of the phy clk 1 signal that you can use in other parts of your design same as phy 1 port aux fu
84. d it in those states for the amount of time specified by the COUNTER VALUE signal You can vary this value to adjust the duration the memory is kept in the low power states This test is only available if your controller variation enables the low power mode option The example driver has four outputs that allow you to observe which tests are currently running and if the tests are passing The pass not fail pnf signal goes low once one or more errors occur and remains low The pass not fail per byte pnf per byte signal goes low when there is incorrect data in a byte but goes back high again once correct data is observed in the following byte The test status signal indicates the test that is currently running allowing you to determine which test has failed The test complete signal goes high for a single clock cycle at the end of the set of tests Table 6 13 shows the bit mapping for each test status Table 6 13 Test Status Bit Mapping Bit Test Sequential address test Incomplete write test Data mask pin test Address pin test Power down test Self refresh test a AJ ew mp o Auto precharge test Table 6 14 shows the ALTMEMPHY Debug interface signals which are located in lt variation_name gt _phy v vhd file Table 6 14 ALTMEMPHY Debug Interface Signals Signal Name Direction Description dbg Input Debug interface clock dbg_addr Input
85. data AFI PHY mem_dqs Sequencer DDR3 SDRAM June 2011 For half rate designs the address and command signals in the ALTMEMPHY megafunction are asserted for one 1 cycle 1T addressing such that there are two input bits per address and command pin in half rate designs If you require a more conservative 2T addressing drive both input bits of the address and command signal identically in half rate designs For DDR3 SDRAM with the AFI the read and write control signals are on a per DQS group basis The controller can calibrate and use a subset of the available DDR3 SDRAM devices For example the controller can calibrate and use two devices out of a 64 or 72 bit DIMM for better debugging mechanism Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 5 18 Chapter 5 Functional Description ALTMEMPHY PHY to Controller Interfaces For half rate designs the AFI allows the controller to issue reads and writes that are aligned to either half cycle of the half rate phy_clk which means that the datapaths can support multiple data alignments word unaligned and word aligned writes and reads Figure 5 6 and Figure 5 7 display the half rate write operation Figure 5 6 Half Rate Write with Word Unaligned Data 00 ctl_wdata_valid 10 11 01 00 ctl
86. delay inserted between ct1 doing rd and ctl rdata valid is spread over three controller clock cycles and the pointed to vector only the upper half of the ct1 is valid denoted by 1 rdata valid cycles the high bits in the sequence 10 11 0110 11 01 providing the required four memory clock cycles of assertion for ct1 doing rd for the two 4 beat reads in the full rate memory clock domain 011110 011110 The return pattern of ct1 rdata validis a delayed version of 1 doing ctl clk ctl rdata word unaligned read is in the previous controller clock ct1_c1k cycle In this example the doing rd signal is now spread over three controller clock ctl clk Altera Corporation clock 1 Similar to word aligned reads ct1 doing rdis asserted one memory clock cycle before chip select ct1 cs is asserted which for a Notes to Figure 5 11 3 The read data June 2011 2 5 24 Chapter 5 Functional Description ALTMEMPHY Using a Custom Controller Using a Custom Controller The ALTMEMPHY megafunction can be integrated with your own controller This section describes the interface requirement and the handshake mechanism for efficient read and write transactions Preliminary Steps Perform the following steps to generate the ALTMEMPHY megafunction 1 If you are creating a custom DDR3 SDRAM controller generate the Altera high performance controller targeting your chosen Altera and memory d
87. ditor displays an error on the bottom of the window if you choose more than one for DDR3 SDRAM interfaces Total Memory chip selects 1 2 4 or 8 bits Sets the number of chip selects in your memory interface The number of chip selects defines the depth of your memory You are limited to the range shown as the local side binary encodes the chip select address Memory interface DQ width 4 288 bits Defines the total number of DQ pins on the memory interface If you are interfacing with multiple devices multiply the number of devices with the number of DQ pins per device Even though the GUI allows you to choose 288 bit DQ width DDR3 SDRAM variations are only supported up to 80 bit width due to restrictions in the board layout which affects timing at higher data width Furthermore the interface data width is limited by the number of pins on the device For best performance have the whole interface on one side of the device Mirror addressing On multiple rank DDR3 SDRAM DIMMs address signals are routed differently to each rank referred to in the JEDEC specification as address mirroring Enter ranks with mirrored addresses in this field There is one bit per chip select For example for four chip selects enter 1011 to mirror the address on chip select 3 1 and 0 Memory vendor Elpida JEDEC Micron Samsung Hynix Nanya other Lists the name of the memory vendor for all supported memory standa
88. dm MR M o gt mem_dq External Interfaces This section discusses the interfaces between the controller and other external memory interface components June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 6 10 Chapter 6 Functional Description High Performance Controller II External Interfaces Clock and Reset Interface The clock and reset interface is part of the AFI interface The controller can have up to two clock domains which are synchronous to each other The controller operates with a single clock domain when there is no integrated half rate bridge and with two clock domains when there is an integrated half rate bridge The clocks are provided by ALTMEMPHY The main controller clock is a i clk and the optional half rate controller clock is afi_half_clk The main and half rate clocks must be synchronous and have a 2 1 frequency ratio The optional quarter rate controller clock is afi_quarter_clk which must also be synchronous and have a 4 1 frequency ratio Avalon ST Data Slave Interface The Avalon ST data slave interface consists of the following Avalon ST channels which together form a single data slave m The command channel which serves as command and address for both read and write operations m The write data channel which carries write data m Theread data channel which carries
89. dt 0 and mem_odt 2 mem_cs 1 mem_odt 1 and mem_odt 3 2 mem_odt 0 and mem odt 2 mem_cs 3 mem_odt 1 and mem odt 3 Table 6 6 shows which ODT signal is enabled for dual slot dual chip select per DIMM Table 6 6 ODT DDR3 SDRAM Dual Slot Dual Rank Per DIMM Read Read On ODT Enabled mem_cs 0 mem_odt 2 mem_cs 1 mem_odt 3 mem cs 2 mem odt 0 mem cs 3 mem odt 1 ECC The ECC logic comprises an encoder and a decoder corrector which can detect and correct single bit errors and detect double bit errors The ECC logic is available in two widths 64 72 bit and 32 40 bit The ECC logic has the following features Has Hamming code ECC logic that encodes every 64 32 16 or 8 bits of data into 72 40 24 or 16 bits of codeword Has a latency increase of one clock for both writes and reads For a 128 bit interface ECC is generated as one 64 bit data path with 8 bits of ECC path plus a second 64 bit data path with 8 bits of ECC path Detects and corrects all single bit errors Detects all double bit errors Counts the number of single bit and double bit errors Accepts partial writes which trigger a read modify write cycle for memory devices with DM pins Can inject single bit and double bit errors to trigger ECC correction for testing and debugging purposes Generates an interrupt signal when an error occurs La When u
90. e Controller Il Top Level Signals Description Table 6 7 Summary of Controller External Interfaces Part 2 of 2 Interface Name Display Name Type Description Configuration and Status Register CSR Interface Enables on the fly configuration of Avalon MM 2 memory timing parameters address widths and controller behaviour Configuration and Status CSR Register Interface Notes 1 For information about AFI signals refer to AFI Signals 2 For information about Avalon signals refer to Avalon Interface Specifications Top Level Signals Description Table 6 8 shows the clock and reset signals The suffix denotes active low signals Table 6 8 Clock and Reset Signals Part 1 of 2 Name Direction Description The asynchronous reset input to the controller The IP core derives all global reset n Input other reset signals from resynchronized versions of this signal This signal holds the PHY including the PLL in reset while low pll ref clk Input The reference clock input to PLL The system clock that the PHY provides to the user All user inputs to and outputs from the controller must be synchronous to this clock The reset signal that the PHY provides to the user The IP core asserts reset phy clk n Output reset phy clk nasynchronously and deasserts synchronously to phy clk clock domain An alternative clock that the PHY provides to the user This clock always runs at the sa
91. e Controller Latency Stages and Descriptions Latency Number Latency Stage Description local_read_req Or local_write_req signal assertion to ddr_cs_n Signal assertion T2 Command Output signal assertion to mem cs n Signal assertion Read command to DQ data from the memory or write command to DQ T1 Controller LS DISP data to the memory ALTMEMPHY T4 read data input Read data appearing on the local interface T2 Write data latency Write data appearing on the memory interface From Figure 7 1 the read latency in the high performance controller is made up of four components read latency controller latency T1 command output latency T2 CAS latency T3 PHY read data input latency T4 Similarly the write latency in the high performance controller is made up of three components write latency controller latency 1 write data latency T2 T3 External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section II DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Chapter 7 Latency 1 3 You can separate the controller and ALTMEMPHY read data input latency into latency that occurred in the I O element IOE and latency that occurred in the FPGA fabric gt The exact latency depends on your precise configuration You should obtain precise latency from simulation but this figure may vary in hardware because of the automatic calibration proce
92. e command to the timing bank pool the arbiter can then issue the write request to the PHY through the AFI interface When the PHY receives the write request it passes the data to the memory device External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 6 20 Chapter 6 Functional Description High Performance Controller Il Example Top Level File Example Top Level File The MegaWizard Plug In Manager helps you create an example top level file that shows you how to instantiate and connect the DDR3 SDRAM HPC II The example top level file consists of the DDR3 SDRAM HPC II some driver logic to issue read and write requests to the controller a PLL to create the necessary clocks and a DLL The example top level file is a working system that you can compile and use for both static timing checks and board tests Figure 6 6 shows the testbench and the example top level file Figure 6 6 Testbench and Example Top Level File pn 4 amp test complete 4 clock source Testbench Example Design Wizard Example Driver ag gt DDR3 SDRAM Controller l4 gt Generated Memory Model ALTMEMPHY Control DLL Logic p PLL Table 6 12 describes the files that are associated with the example top level file and the testbench Table 6 12 Example Top Level File and Testbenc
93. e following sequence corresponds with the numbered items in Figure 8 4 1 Altera Corporation The user logic asserts the first local write req signal with a size of 2 and address of 0x000001 The 1ocal ready signal is asserted along with the local write signal which indicates that the controller has accepted this request and the user logic can request another read or write in the following clock cycle If the 1ocal ready signal was not asserted the user logic must keep the write request size and address signals asserted until the 1ocal ready signal is registered high The local address 0x000001 is mapped to the following memory address in half rate mode mem row address 0x0000 mem col address 0x000001 2 0x000004 mem bank address 0x00 The user logic asserts the second local write req signal with a size of 2 and an address of 0x000003 The local address 0x000003 is mapped to the following memory address in half rate mode mem row address 0x0000 mem col address 0x000003 2 0x00000C mem bank address 0x00 The controller issues the necessary memory command and address signals to the ALTMEMPHY megafunction for it to send to the memory device The controller asserts the afi_wdata_valid signal to indicate to the ALTMEMPHY megafunction that valid write data and write data masks are present on the inputs to the ALTMEMPHY megafunction The controller asserts the afi 4 burst signals to control the ti
94. e is set to 0 15 13 Reserved 0 C Reserved for future use 16 DLL 0 Read write Not used by the controller but you can set 17 ODS 0 Read write and program into the memory device mode 18 RIT 0 Read write Tegister Additive latency setting The default value for these bits is set by the MegaWizard 21 19 AL Read write Additive Latency setting for your controller instance You must set this value in CSR interface register map 0x126 as well 22 RIT 0 Read write 2528 RTTAWL OCD 0 Read write Not used by the controller but you can set 26 DQS 0 Read write and program into the memory device mode 27 TDOS RDOS 0 Read write Teg ster 28 QOFF 0 Read write 31 29 Reserved 0 Reserved for future use External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide June 2011 Altera Corporation Chapter 6 Functional Description High Performance Controller 11 6 25 Register Maps Table 6 16 ALTMEMPHY Register Map Part 2 of 2 Address Bit Name Default Access Description 2 0 Reserved 0 Reserved for future use CAS write latency setting The default value for these bits is set by the MegaWizard CAS 5 3 CWL Read write Write Latency setting for your controller instance You must set this value in the CSR interface register map 0x126 as well 6 ASR 0 Read write Not used by the controller but you can set and program into the me
95. e user logic asserts a second 1ocal read signal with a size of 2 and address of 0x0000912 4 The controller issues the first read memory command and address signals to the ALTMEMPHY megafunction for it to send to the memory device 5 The ALTMEMPHY megafunction issues the read command to the memory and captures the read data from the memory Half Rate Write With Gaps Figure 8 6 Half Rate Write Operation for HPC II With Gaps phy clk Local Interface local_address 25 local size 4 local ready local burstbegin local be 3 local write req local wdata 31 I 800 T EFON 8000 Controller afi 840127 0000000 I I afi 1 F I I F afi cs n EFO T EFO AFI Command NOP gt sa 00 afi PALIT OT FFIEET lt afi lal afi dos bur afi dos bur afi wdata 31 afi wdata AFI Memory Interface mem cke 1 mem ck m i i 7 I X mem ba I X X X 5 mem 2 5 eR ao 11 mem CS Mem Command mem mem mem dq mem 00 le 5 25 eo 3 N i a 8 External Mem
96. ed to zero If you are using a DLL offset connect this DTH input to the o set ctrl out output of the d11 offset ctrl block Reference clock to feed to an externally instantiated DLL This clock dll reference clk Output 1 is typically from one of the PHY PLL outputs User Mode Calibration OCT Control Signals Em Input 14 OCT RS value port for use with ALT OCT megafunction if you want to use OCT with user mode calibration sek Bee vaide Input 14 OCT RT value port for use with ALT OCT megafunction if you want to zT use OCT with user mode calibration Debug Interface Signals Note 1 Note 2 dbg clk Input 1 Debug interface clock dbg reset n Input 1 Debug interface reset External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section II DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Chapter 5 Functional Description ALTMEMPHY ALTMEMPHY Signals Table 5 4 Other Interface Signals Part 2 of 2 5 15 Signal Name Type Width Description dbg addr Input ME Address input dgb wr Input 1 Write request dbg rd Input 1 Read request dbg cs Input 1 Chip select dbg wr data Input 32 Debug interface write data dbg rd data Output 32 Debug interface read data dbg waitrequest Output 1 Wait signal Calibration Interface Signals without leveling only rsu codvw phase Output The sequencer sweeps the phase of a resynchronization clock across 360 or 72
97. ee ae oe eee PS Posse caeci cim lt b b b g5 e e Pere us e e mc S s E 5 28 9 9 o 5 lt gt et o 5 e o 4 5 o E o mem clk mem cs n Notes to Figure 5 9 is asserted In the half rate cti domain this requirement manifests as the controller driving 11 as opposed to the 01 on ctl_doing rd 2 requires that ctl_doing_rdis driven for the duration of the read In this example it is driven to 11 for two half rate ctl_clks which equates For AFI 1 doing rd is required to be asserted one memory clock cycle before chip select ct1 cs n 1 to driving to 1 for the four memory clock cycles of this four beat burst The ctl rdata valid returns 15 cycles after ctl_doing_rd is asserted Returned is when the ctl rlat controller clock ct1 ctl rdata valid Signal is observed at the output of a register within the controller A controller can use the ct1_rlat value to determine when to register to returned data but this is unnecessary as the 1 rdata validis provided for the controller to use as an enable when registering 3 read data 4 Observe the alignment of returned read data with respect
98. elect per DIMM There is no ODT for reads Table 6 1 ODT DDR3 SDRAM Single Slot Single Chip select Per DIMM Write Write On mem_cs 0 ODT Enabled mem_odt 0 Table 6 2 shows which ODT signal is enabled for single slot dual chip select per DIMM There is no ODT for reads Table 6 2 ODT DDR3 SDRAM Single Slot Dual Chip select Per DIMM Write Write On ODT Enabled mem_cs 0 mem_odt 0 mem_cs 1 mem_odt 1 Table 6 3 shows which ODT signal is enabled for dual slot single chip select per DIMM Table 6 3 ODT DDR3 SDRAM Dual Slot Single Chip select Per DIMM Write Write On ODT Enabled mem_cs 0 mem_odt 0 and mem_odt 1 mem_cs 1 mem_odt 0 and mem_odt 1 Table 6 4 shows which ODT signal is enabled for dual slot single chip select DIMM Table 6 4 ODT DDR3 SDRAM Dual Slot Single Chip select Per DIMM Read Read On ODT Enabled mem_cs 0 mem_odt 1 mem_cs 1 mem_odt 0 External Memory Interface Handbook Volume 3 Section II DDR3 SDRAM Controller with ALTMEMPHY IP User Guide June 2011 Altera Corporation Chapter 6 Functional Description High Performance Controller 11 6 7 Controller Features Descriptions Table 6 5 shows which ODT signal is enabled for dual slot dual chip select per DIMM Table 6 5 ODT DDR3 SDRAM Dual Slot Dual Chip select Per DIMM Write Write On ODT Enabled mem_cs 0 mem_o
99. equential Operation for HPC Il 810 13 1 UUUUW UUU U FA UU WU UU VI Local Interface local address 25 0 0000002 0907004 110 local size 4 0 local ready local burstbegin local read req local rdata 31 0 MU 00000000 900000010 local_rdata_valid local be 3 0 local write req local wdata 31 0 1 00000008 00000010 77118 Controller AFI afi addr 27 0 0000000 002 0000000 afi ba 5 0 0000000 0020 2 0000000 afi cs n 3 0 VB I Command 2 0 T WRI rat NOP F NOP I afi dm 3 0 o wlat 4 0 afi wdata 31 0 00000000 afi doing rd 1 0 afi_wdata_valid 1 0 2191 afi das bursi 1 afi_dqs_burst 0 afi_rdata 31 0 00000000 00000000 10 afi_rdata_valid 1 0 I3 AFI Memory Interface mem cke 1 0 mem clk mem ba 2 0 mem addi 13 0 0000 0008 00 Jo008 0000 10010 0000 0010 mem cs 10 UJ Mem Command 2 0 WR I mem 105 I 2 NOP PUL mem_dm NOP I is ae 2 00
100. evice family for example Arria Il GX Table 1 2 page 1 3 shows supported device Device family families The device family selected here must match the device family selected on the MegaWizard page 2a Speed grade Selects a particular speed grade of the device for example 2 3 or 4 for the Arria Il GX device family PLL reference clock frequency Determines the clock frequency of the external input clock to the PLL Ensure that you use three decimal points if the frequency is not a round number for example 166 667 MHz or 100 MHz to avoid a functional simulation or a PLL locking problem Memory clock frequency Determines the memory interface clock frequency If you are operating a memory device below its maximum achievable frequency ensure that you enter the actual frequency of operation rather than the maximum frequency achievable by the memory device Also ensure that you use three decimal points if the frequency is not a round number for example 333 333 MHz or 400 MHz to avoid a functional simulation or a PLL locking issue Controller data rate Selects the data rate for the memory controller Sets the frequency of the controller to equal to either the memory interface frequency full rate or half of the memory interface frequency half rate The full rate option is not available for DDR3 SDRAM devices Enable half rate bridge This option is only available for HPC II full rate controller Turn on
101. evices 2 Compile and verify the timing This step is optional refer to Compiling and Simulating on page 4 1 3 If targeting a DDR3 SDRAM device simulate the high performance controller design so you can determine how to drive the PHY signals using your own controller 4 Integrate the top level ALTMEMPHY design with your controller If you started with the high performance controller the PHY variation name is controller gt phy v vhd Details about integrating your controller with Altera s ALTMEMPHY megafunction are described in the following sections 5 Compile and simulate the whole interface to ensure that you are driving the PHY properly and that your commands are recognized by the memory device Design Considerations This section discuss the important considerations for implementing your own controller with the ALTMEMPHY megafunction This section describes the design considerations for AFI variants Simulating the high performance controller is useful if you do not know how to drive the PHY signals Clocks and Resets The ALTMEMPHY megafunction automatically generates a PLL instance but you must still provide the reference clock input 11 ref clk with a clock of the frequency that you specified in the MegaWizard Plug In Manager An active low global reset input is also provided which you can deassert asynchronously The clock and reset management logic synchronizes this reset to the appropriate clock doma
102. f a request signal and an acknowledgement signal which allow you to determine when the controller issues refresh signals to the memory device This interface gives you increased control over worst case read latency and enables you to issue refresh bursts during idle periods This interface is clocked by afi When you assert a refresh request signal to instruct the controller to perform a refresh operation that request takes priority over any outstanding read or write requests that might be in the command queue Once the controller successfully issues a refresh command to the memory device the controller asserts the refresh acknowledge signal for one clock cycle If you want to send consecutive refresh commands you should keep the refresh request asserted which causes the controller to issue another refresh command and again assert the acknowledge signal for a one clock cycle You can perform up to nine consecutive refresh commands Configuration and Status Register CSR Interface The controller has a configuration and status register CSR interface that allows you to configure timing parameters address widths and the behavior of the controller The CSR interface is a 32 bit Avalon MM slave of fixed address width if you do not need this feature you can disable it to save area This interface is clocked csr_clk which is the same as afi 1 and is always synchronous relative to the main data slave interface Table
103. g on the slew rate of the CK and CK clocks and the address and command signals Ensure that you are using the correct number and that the value entered is referenced to yper dc not Viu dc min or Vj dc max Refer to Derating Memory Setup and Hold Timing on page 3 10 for more information about how to derate this specification Address and control input setup time which has a derated value depending on the slew rate of the CK and CK clocks and the address and command signals Ensure that you are using the correct number and that the value entered is referenced to Varr dc not Viy ac min or max Refer to Derating Memory Setup and Hold Timing on page 3 10 for more information about how to derate this specification tous 0 700 ps The maximum data hold skew factor 0 1 0 6 tek DQ output hold time The activate to activate time per device RAS to RAS delay timing parameter 7 69 256 ns The four activate window time per device 2 06 64 ns Read to precharge time Note to Table 3 5 1 See the memory device data sheet for the parameter range Some of the parameters may be listed in a clock cycle tc unit If the MegaWizard Plug In Manager requires you to enter the value in a time unit ps or ns convert the number by multiplying it with the clock period of your interface and not the maximum clock period listed in the memory data sheet tox 10 600 ps tps 10 600 ps tu 50 100
104. h 8 Memory burst length On the fly Memory burst ordering Sequential Enable the DLL in the memory devices Yes Memory CAS latency setting 5 0 DLL Precharge Power down Fast exit Output driver impedance ohm Memory Additive CAS latency setting Disabled cycles Memory Write CAS latency setting OAL 5 0 cycles Memory Partial Array Self Refresh Full Array Memory Auto Self Refresh Method Manual SR Refere Memory Self Refresh Range Normal Dynamic ODT WR value Dynamic ODT off The Advanced option shows the percentage of memory specification that is calibrated by the FPGA The percentage values are estimated by Altera based on the process variation External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section 1 DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Chapter 3 Parameter Settings ALTMEMPHY Parameter Settings 3 5 Table 3 3 through Table 3 5 describe the DDR3 SDRAM parameters available for memory attributes initialization options and timing parameters Table 3 3 DDR3 SDRAM Attributes Settings Part 1 of 2 Parameter Name Output clock pairs from FPGA Range 7 Units pairs Description Defines the number of differential clock pairs driven from the FPGA to the memory Memory clock pins use the signal splitter feature in Arria GX devices for differential signaling The ALTMEMPHY parameter e
105. h Files Filename Description variation name gt _example_top_tb v or vhd Testbench for the example top level file lt variation name gt _example_top v or vhd Example top level file lt variation name gt _mem_model v or vhd Associative array memory model variation name full mem model v or vhd Full array memory model variation name example driver v or vhd Example driver variation name or vhd Top level description of the custom MegaCore function variation name gt qip Contains Quartus project information for your MegaCore function variations There are two Altera generated memory models available associative array memory model and full array memory model The associative array memory model variation name mem model v allocates reduced set of memory addresses with a default depth of 2 048 or 2K address spaces This allocation allows for a larger memory array compilation and simulation which enables you to easily reconfigure the depth of the associate array The full array memory model variation name mem model full v allocates memory for all addresses accessible by the DDR cores This allocation makes it impossible to simulate large memory designs External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section 1 DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Chapter 6 Functional Description High Performance Controller 11 6 21 Example Top
106. haracteristics of the chosen memory device and changing them creates a new custom memory preset If you click Save As at the bottom left of the page and save the new settings in the quartus install dir NquartusNcommon ip altera altmemphy lib directory you can use this new memory preset in other Quartus II projects created in the same version of the software When you click Save the new memory preset appears at the bottom of the Memory Presets list in the Memory Settings tab If you save the new settings in a directory other than the default directory click Load Preset in the Memory Settings tab to load the settings into the Memory Presets list June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 3 4 Chapter 3 Parameter Settings ALTMEMPHY Parameter Settings Figure 3 2 shows the Preset Editor dialog box for a DDR3 SDRAM Figure 3 2 DDR3 SDRAM Preset Editor Preset Editor Memory preset Micron MT41J128M8BY 25 Parameter Categories All Parameters Memory Attributes Memory Initialization Options Memory Timing Parameters Shaded parameters represent the defining characteristics of this memory device Modifying any of the shaded parameters will result in the creation of a custom preset r Parameters Parameter Value Output clock pairs from FPGA 1 Total Memory chip selects 1 Total Memory interface DG widt
107. he options are available if they apply to the target Altera device Table 3 6 ALTMEMPHY PHY Settings Parameter Name Enable external access to reconfigure PLL prior to calibration Applicable Device Families HardCopy Il Description When enabling this option for HardCopy II devices the inputs to the ALTPLL RECONFIG megafunction are brought to the top level for debugging purposes This option allows you to reconfigure the PLL before calibration to adjust if necessary the phase of the memory clock mem 1 2x before the start of the calibration of the resynchronization clock on the read side The calibration of the resynchronization clock on the read side depends on the phase of the memory clock on the write side Instantiate DLL All supported device Use this option if you want to apply a non standard phase shift to the DQS capture clock The ALTMEMPHY DLL offsetting 1 0 can eternally then be connected to the external DLL and the Offset Control Block Adjusting the address and command phase can improve the address and command setup and hold margins at the memory Clock phase Arria Il GX device to compensate for the propagation delays that vary with different loadings You have a choice of 0 90 180 and 270 based on the rising and falling edge of the phy and write_clk signals Autocalibration simulation options All supported device families Choose between Full Ca
108. he following memory address in half rate mode mem_row_address 0x000000 mem_col_address 0x0000 mem bank address 0x00 The user logic initiates a second read to a different memory column within the same row The request for the second read is a burst length of 2 In this example the user logic continues to accept commands until the command queue is full When the command queue is full the controller deasserts the 1ocal ready signal The starting local address 0x000002 is mapped to the following memory address in half rate mode mem row address 0x0000 mem col address 0x0002 2 0x0008 I mem bank address 0x00 The controller issues the first read memory command and address signals to the ALTMEMPHY megafunction for it to send to the memory device The controller asserts the afi doing rd signal to indicate to the ALIMEMPHY megafunction the number of clock cycles of read data it must expect for the first read The ALTMEMPHY megafunction uses the doing rd signal to enable its capture registers for the expected duration of memory burst The ALTMEMPHY megafunction issues the first read command to the memory and captures the read data from the memory The ALTMEMPHY megafunction returns the first data read to the controller after resynchronizing the data to the phy_clk domain by asserting the afi rdata validsignal when there is valid read data on the afi rdata bus The controller returns the first read data to the
109. he reduction in the eye diagram on the hold side due to the ISI hold on the address and command signals Sets the total reduction in the eye diagram the setup side due to is the ISI on the DQ signals Delta DOS arrival time Sets the increase of variation on the range of arrival times of DQS due to ISI Max skew between Sets the largest skew or propagation delay on the DQ signals DIMMs devices between ranks Max skew within DQS group ns Sets the largest skew between the DQ pins in a DQS group Max skew between DQS groups ns Sets the largest skew between 00 signals in different 00 groups Sets the skew or propagation delay between the CK signal and the address and command signals The positive values represent the Addr command to CK skew ns address and command signals that are longer than the CK signals and the negative values represent the address and command signals that are shorter than the CK signals DDR3 SDRAM Controller with ALTMEMPHY Parameter Settings The Parameter Settings page in the DDR3 SDRAM Controller with ALTMEMPHY parameter editor Figure 3 3 allows you to parameterize the following settings m Memory Settings PHY Settings m Board Settings Controller Settings External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section 1 DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Chapter 3 Parameter Settings 3 13 DDR3 SDRAM Controller with A
110. iation name alt mem p hy ad Usage All ALTMEMPHY variations Description Generates the address and command structures All AlTMEMPHY variations Instantiates PLL DLL and reset logic pu lation nam alt mem Phy ALTMEMPHY variations Generates the DQ 00 DM and QVLD 1 0 pins variation name alt mem phy mi DDR3 SDRAM ALTMEMPHY Creates the VT tracking mechanism for DDR3 mic variation SDRAM PHYs Variation name alt mem phy oc DDR3 SDRAM ALTMEMPHY Generates the proper delay and duration for the edal variation when dynamic OCT is OCT sionals aoe ay enabled variation name alt mem phy po DDR3 SDRAM ALTMEMPHY Generates the postamble enable and disable stamble variations scheme for DDR3 PHYs June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 2 10 Chapter 2 Getting Started Generated Files Table 2 4 Modules in lt variation_name gt _alt_mem_phy v File Part 2 of 2 variation name al ad dp t mem phy re All ALTMEMPHY variations Description Takes read data from the 1 0 through a read path FIFO buffer to transition from the resyncronization clock to the PHY clock variation name al ata valid t mem phy rd DDR3 SDRAM ALTMEMPHY variations Generates read data valid signal to sequencer and contr
111. ie termination control signal em ras n Output 1 The memory row address strobe The memory reset signal This signal is derived Output 1 from the PHY s internal reset signal which is generated by gating the global reset soft reset and the PLL locked signal em we n Output 1 The memory write enable signal The address or command parity signal NL generated by the PHY and sent to the DIMM The active low signal that is asserted when a parity_error_n 4 Output 1 parity error occurs and stays asserted until the PHY is reset The signal sent from the DIMM to the PHY to indicate that a parity error has occured for a particular cycle mem err out n 4 Input Notes to Table 5 2 1 Connected to 1 0 pads 2 Referto Table 5 5 for parameter description 3 Output is for memory device and input path is fed back to ALTMEMPHY megafunction for VT tracking 4 This signal is for Registered DIMMs only Table 5 3 AFI Signals Part 1 of 4 Signal Name Type Width 7 Description Clocks and Resets pll ref clk Input 1 The reference clock input to the PHY PLL Active low global reset for PLL and all logic in the Inout 18 PHY A level set reset signal which causes 3 complete reset of the whole system The PLL may maintain some state information Edge detect reset input intended for SOPC Builder Inout 1 use or to be controlle
112. ignal to indicate to the ALTMEMPHY megafunction that valid write data and write data masks are present on the inputs to the ALTMEMPHY megafunction The controller asserts the afi burst signals to control the timing of the DOS signal that the ALTMEMPHY megafunction issues to the memory The ALTMEMPHY megafunction issues the write command and sends the write data and write DQS to the memory External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide BPIND 1951 dl AHdINIALLTV 191104109 NVHOS II 1011295 euinjoA eoeji91u Jeul9 X3 1106 eunr 012100109 Bally Half Rate Read Non Burst Aligned Address Figure 8 3 Half Rate Read Operation for HPC Burst Aligned Address i fa 8 6 U LP UU UUUUUUUUU UU UUUUUU UJ UUUUU UU UU UUUUUU UI Local Interface local address 25 0 local size 4 0 local ready local burstbegin local read req local rdata 31 0 local rdata valid local be 3 0 000 00001 00007 0005 AABBAABJEEF F001 erre vesccoo AABBAABHEEFFOOT EEFFOOTT LI VL I LA Vd 1 Controller AFI afi 27 0 10004 100000 20008 90000 37000 00000 40010 00000 50014 00000 afi ba 5 0 afi cs n 3 0 J 5IFIZgIFISIFIBIFTISIFISBI F AFI Command 2 0 NOP RD L
113. ins inside the ALTMEMPHY megafunction A clock output half the memory clock frequency for a half rate controller is provided and all inputs and outputs of the ALTMEMPHY megafunction are synchronous to this clock For AFIs this signal is called ct1 There is also an active low synchronous reset output signal provided ctl reset n This signal is synchronously de asserted with respect to the ct1_clk or phy clk clock domain and it can reset any additional user logic on that clock domain External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section 1 DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Chapter 5 Functional Description ALTMEMPHY 5 25 Using a Custom Controller Calibration Process Requirements When the global reset_nis released the ALTMEMPHY handles the initialization and calibration sequence automatically The sequencer calibrates memory interfaces by issuing reads to multiple ranks of DDR3 SDRAM multiple chip select Timing margins decrease as the number of ranks increases It is impractical to supply one dedicated resynchronization clock for each rank of memory as it consumes PLL resources for the relatively small benefit of improved timing margin When calibration is complete ct1 cal success goes high if successful ct1 cal fail goes high if calibration fails Calibration can be repeated by the controller using the soft reset nsignal which when asserted puts the sequencer into a reset state
114. k Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide June 2011 Altera Corporation Chapter 6 Functional Description High Performance Controller 11 Register Maps Table 6 17 Controller Register Map Part 3 of 5 6 27 Address Bit Name Default Access Description The activate to read or write a timing 3 0 trop Read write parameter The range of legal values is 2 11 cycles _ 44 activate to activate a timing parameter 74 tRRD Read wile range of legal values is 2 8 cycles __ The precharge to activate a timing parameter WB ikp Read write Thy range of legal values is 2 11 cycles 0x123 The mode register load time parameter This _ value is not used by the controller as the 1512 1 Read write controller derives the correct value from the memory type setting __ The activate to precharge timing parameter 23 16 tras Read write The range of legal values is 4 29 cycles _ 44 activate to activate a timing parameter 31 24 tre Read write The range of legal values is 8 40 cycles __ 44 write to read a timing parameter The 0 Read write range of legal values is 1 10 cycles _ The read to precharge a timing parameter 0x124 T4 Read write The range of legal values is 2 8 cycles L The four activate window timing parameter 15 8 traw Pead Wie range of
115. le to apply the I O assignments generated by the MegaWizard Plug In Manager Using the ppf file and the Pin Planner gives you the extra flexibility to add a prefix to your memory interface pin names You can edit the assignments either in the Assignment Editor or Pin Planner Use one of the following procedures to specify the I O standard assignments for pins m Ifyou havea single SDRAM interface and your top level pins have default naming shown in the example top level file run lt variation name gt _pin_assignments tcl or m If your design contains pin names that do not match the design edit the variation name gt _pin_assignments tcl file before you run the script To edit the tcl file perform the following steps a Open lt variation name gt _pin_assignments tcl file b Based on the flow you are using set the sopc_mode value to Yes or No SOPC Builder System flow if info exists sopc_mode set sopc_mode YES MegaWizard Plug In Manager flow if info exists sopc_mode set sopc mode NO c Type your preferred prefix in the pin prefix variable For example to add the prefix my mem do the following if info exists set prefix set pin prefix my mem After setting the prefix the pin names are expanded as shown in the following m SOPC Builder System flow my mem cs n from the your instance name MegaWizard Plug In Manager flow my mem cs n 0 La If your top level design does not use single
116. les you want to generate gray checkmark indicates a file that is automatically generated All other files are optional 6 Click Finish to generate the MegaCore function and supporting files A generation report appears 7 If you generate the MegaCore function instance in a Quartus II project you are prompted to add the qip files to the current Quartus II project When prompted to add the qip files to your project click Yes The addition of the qip files enables their visibility to Nativelink Nativelink requires the qip files to include libraries for simulation Ia file is generated by the parameter editor and contains information about the generated IP core In most cases the qip file contains all of the necessary assignments and information required to process the MegaCore function or system in the Quartus II compiler The parameter editor generates a single qip file for each MegaCore function 8 After you review the generation report click Exit to close the MegaWizard Plug In Manager June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 2 8 Chapter 2 Getting Started Generated Files 9 For the high performance controller set the lt variation name gt _example_top v or vhd file to be the project top level design file a On the File menu click Open b Browse to lt variation name gt _example_top and click Open c
117. libration long simulation time Quick Calibration or Skip Calibration For more information refer to the Simulation section in volume 4 of the External Memory Interface Handbook Board Settings Click Next or the Board Settings tab to set the options described in Table 3 7 The board settings parameters are set to model the board level effects in the timing analysis Table 3 7 ALTMEMPHY Board Settings Part 1 of 2 Parameter Name Units Number of slots discrete devices Description Sets the single rank or multi rank configuration CK CK slew rate differential V ns Sets the differential slew rate for the CK and signals Addr command slew rate V ns Sets the slew rate for the address and command signals DQ DQS slew rate differential V ns Sets the differential slew rate for the DQ and DQS signals June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 3 12 Table 3 7 ALTMEMPHY Board Settings Part 2 of 2 Chapter 3 Parameter Settings DDR3 SDRAM Controller with ALTMEMPHY Parameter Settings Parameter Name Units Description DQ slew rate V ns Sets the slew rate for the DQ signals Addr command eye reduction Sets the reduction the eye diagram the setup side due to the setup ISI on the address and command signals Addr command eye reduction n Sets t
118. limit Pre emptive Bank Management Data reordering allows the controller to issue bank management commands pre emptively based on the patterns of incoming commands consequently the desired page in memory can be already open when a command reaches the AFI interface Quasi 1T and Quasi 2T One controller clock cycle equals two memory clock cycles in a half rate interface and to four memory clock cycles in a quarter rate interface To fully utilize the command bandwidth the controlller can operate in Quasi 1T half rate and Quasi 2T quarter rate modes In Quasi 1T and Quasi 2T modes the controller issues two commands on every controller clock cycle The controller is constrained to issue a row command on the first clock phase and a column command on the second clock phase or vice versa Row commands include activate and precharge commands column commands include read and write commands External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section II DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Chapter 6 Functional Description High Performance Controller 11 6 5 Controller Features Descriptions User Autoprecharge Commands The autoprecharge read and autoprecharge write commands allow you to indicate to the memory device that this read or write command is the last access to the currently open row The memory device automatically closes or autoprecharges the page it is currently accessing so that the next a
119. ll rate clk Output In full rate designs a copy of the mem 2x signal that you can use in other parts of your design aux scan clk Output Low frequency scan clock supplied primarily to clock any user logic that interfaces to the PLL and DLL reconfiguration interfaces aux scan clk reset n Output This reset output asynchronously asserts drives low when global reset nis asserted and de assert drives high synchronous to aux scan clk When global reset niS de asserted It allows you to reset any external circuitry clocked by aux scan clk Write Data Interface ctl dqs burst Input MEM IF DQS WIDTHx DWIDTH RATIO 2 When asserted mem is driven The ctl dqs burst signal must be asserted before the ctl wdata valid signal and must be driven for the correct duration to generate a correctly timed mem signal ctl wdata valid Input MEM IF DQS WIDTHx DWIDTH RATIO 2 Write data valid Generates 1 and ctl dm output enables ctl wdata Input MEM IF DWIDTHx DWIDTH RATIO Write data input from the controller to the PHY to generate mem dq ctl dm Input MEM IF DM WIDTH x DWIDTH RATIO DM input from the controller to the PHY External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide June 2011 Altera Corporation Chapter 5 Functional Description ALTMEMPHY ALTMEM
120. low June 2011 2 5 To avoid simulation failure you must set Local to Memory Address Mapping to CHP BANK ROW COL if you select High Peformance Controller II for Controller Architecture For detailed explanation of the parameters refer to the Parameter Settings on page 3 1 6 Click Finish to complete parameterizing the DDR3 SDRAM Controller with ALTMEMPRHY IP and add it to the system Completing the Qsys System To complete the system perform the following steps 1 On the Component Library tab select Nios II Processor and click Add 2 On the Nios II Processor page in the Core Nios tab select altmemddr for Reset Vector and Exception Vector Change the Reset Vector Offset and the Exception Vector Offset to an Avalon address that is not written to by the ALTMEMPHY megafunction during its calibration process A CAUTION The ALTMEMPHY megafunction performs memory interface calibration every time it is reset and in doing so writes to a range of addresses If you want your memory contents to remain intact through a system reset you should avoid using these memory addresses This step is not necessary if you reload your SDRAM memory contents from flash every time you reset your system If you are upgrading your Nios system design from version 8 1 or previous ensure that you change the Reset Vector Offset and the Exception Vector Offset to AFI mode To calculate the Avalon MM address equivalent of the
121. me 3 June 2011 Altera Corporation Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Chapter 6 Functional Description High Performance Controller 11 6 13 Top Level Signals Description Table 6 8 Clock and Reset Signals Part 2 of 2 Name Direction Description Input for OCT Required signal for PHY to provide series termination calibration slave value Must be connected to a user instantiated OCT control block seriesterminationcontrol alt oct or another UniPHY instance that is set to OCT master mode Output for OCT master Unconnected PHY signal available for sharing with another PHY Input for OCT Required signal for PHY to provide series termination calibration slave value Must be connected to a user instantiated OCT control block parallelterminationcontrol alt_oct or another UniPHY instance that is set to OCT master mode Output for OCT master Unconnected PHY signal available for sharing with another PHY a Input for OCT Must connect to calibration resistor tied to GND on the appropriate master RDN pin on the device Refer to appropriate device handbook Input for OCT Must connect to calibration resistor tied to on the appropriate TUP master RUP pin on the device See appropriate device handbook Allows the use of DLL in another PHY instance in this PHY instance dqs delay ctrl import Input Connect the export port on the PHY instance with a DLL to the
122. me frequency as the external memory interface aux full rate clk Output In half rate designs this clock is twice the frequency of the phy and you can use it whenever you require a 2x clock In full rate designs the same PLL output as the phy signal drives this clock An alternative clock that the PHY provides to the user This clock always runs at half the frequency as the external memory interface In full rate designs this clock is half the frequency of the phy and aux half rate clk Output you can use it for example to clock the user side of a half rate bridge In half rate designs or if the Enable Half Rate Bridge option is turned on The same PLL output that drives the phy c1k signal drives this clock dll reference clk Output Reference clock to feed to an externally instantiated DLL Reset request output that indicates when the PLL outputs are not locked Use this signal as a reset request input to any system level reset request n Output reset controller you may have This signal is always low when the PLL is trying to lock and so any reset logic using Altera advises you detect a reset request on a falling edge rather than by level detection Edge detect reset input for SOPC Builder or for control by other soft reset n Input system reset logic Assert to cause a complete reset to the PHY but not to the PLL that the PHY uses phy clk Output External Memory Interface Handbook Volu
123. ming of the DOS signal that the ALTMEMPHY megafunction issues to the memory The ALTMEMPHY megafunction issues the write command and sends the write data and write DOS to the memory The controller generates another write because the first write is to a non aligned memory address 0x0004 The controller performs the second write burst at the memory address of 0x0008 External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide BPIND 1951 dl AHdINIALLTV 191104109 NVHOS II 1011295 euinjoA eoeji91u Jeul9 X3 1106 eunr 012100109 194 Half Rate Read With Gaps Figure 8 5 Half Rate Read Operation for HPC II With Gaps 1 2 3 5 phy ck 1 UUU Vf VT Local Interface local address 25 0 0008101 000912 0014 local size 4 0 local_ready local_burstbegin local_read_req local rdata 31 0 00000000 local_rdata_valid Eoo A local be 3 0 Controller AFI afi addr 27 0 0000000 00000510144 0 01 0000000 412104810004001 0000000 0000000 afi ba 5 0 V 0 Ja 0 o2 o rI afi_cs_n 3 0
124. mory device mode 7 SRT ET 0 Read write register 0x006 8 Reserved 0 Reserved for future use Not used by the controller but you can set 10 9 WR 0 Read write and program into the memory device mode register 15 11 Reserved 0 Reserved for future use 17 16 MPR RF 0 Read write Not used by the controller but you can set and program into the memory device mode 18 MPR 0 Read write register 0 31 19 Reserved Reserved for future use Controller Register Map The controller register map allows you to control the memory controller settings To access the controller register map connect the CSR interface signals using the Avalon MM protocol Table 6 17 shows the register map for the controller Table 6 17 Controller Register Map Part 1 of 5 Address Bit Name Default Access Description This bit reports the value of the ALTMEMPHY 0 CAL SUCCESS Read only ct1 cal success output Writing to this bit has no effect This bit reports the value of the ALTMEMPHY 1 CAL FAIL Read only ctl_cal_fail output Writing to this bit has no effect Writing a 1 to this bit asserts the ctl cal req signal to the ALTMEMPHY megafunction Writing a 0 to this bit 0x100 deaaserts the signal and the ALTMEMPHY megafunction will then initiate its calibration sequence You must not use this register during the ALTMEMPHY megafunction calibration You must wait until the CAL SUCCESS o
125. n NOP RD NOP RD RD NOP RD NOP afi dm 3 0 afi_dgs_burst 0 afi_dqs_burst 1 afi doing rd 1 0 0 137013 1013101300135 073 I afi_rdata 31 0 EEF FOON eco ves erre vano ARBAB afi rdata valid 1 0 0 3 10 0 0 2131013 AFI Memory Interface mem cke 1 0 mem clk mem ba 2 0 mem addi 13 0 0000 Joc ooo ooo 000 ooo Tot 000 Toota ooo 0 E mem cs Command 2 0 mem 05 mem di mem de 7 0 mem odt 1 0 480 302 eoueuuoneg ubiH euaa sweifeig 8 193deug 9 8 Chapter 8 Timing Diagrams DDR3 High Performance Controller 11 June 2011 The following sequence corresponds with the numbered items in Figure 8 3 1 Altera Corporation The user logic requests the first read by asserting 1ocal read req signal and the size and address for this read In this example the request is a burst of length of 2 to the local address 0x000001 This local address is mapped to the following memory address in half rate mode mem row address 0x0000 mem col address 0x0001 2 0x0004 mem bank address 0x00 The controller issues the first read memory command and address signals to the ALTMEMPHY megafunction for it to send to the memory device The controller asserts the afi doing rd signal to indicate to the ALIMEMPHY meg
126. nce The ALTPLL megafunction generates the different clock frequencies and relevant phases used within the ALTMEMPHY megafunction The available device families have different PLL capabilities The minimum PHY requirement is to have 16 phases of the highest frequency clock The PLL uses With No Compensation option to minimize jitter Changing the PLL compensation to a different operation mode may result in inaccurate timing results The input clock to the PLL does not have any other fan out to the PHY so you do not have to use a global clock resource for the path between the clock input pin to the PLL You must use the PLL located in the same device quadrant or side as the memory interface and the corresponding clock input pin for that PLL to ensure optimal performance and accurate timing results from the Quartus II software You must choose a PLL and PLL input clock pin that are located on the same side of the device as the memory interface to ensure minimal jitter Also ensure that the input clock to the PLL is stable before the PLL locks If not you must perform a manual PLL reset by driving the global_reset_n signal low and relock the PLL to ensure that the phase relationship between all PLL outputs is properly set gt If the design cascades PLLs the source upstream PLL should have low bandwidth setting and the destination downstream PLL should have a high bandwidth setting Adjacent PLLs cascading is recommended to reduce cl
127. nd not the memory device s tcp tras 8 200 ns Minimum active to precharge time The controller waits for this period of time after issuing an active command before issuing a precharge command to the same bank ns Minimum active to read write time The controller does not issue read or write commands to a bank during this period of time after issuing an active command ns Minimum precharge command period The controller does not access the bank for this period of time after issuing a precharge command REFI 1 65534 us Maximum interval between refresh commands The controller performs regular refresh at this interval unless user controlled refresh is turned on 14 1651 5 Minimum autorefresh command period The length of time the controller waits before doing anything else after issuing an auto refresh command twr ns Minimum write recovery time The controller waits for this period of time after the end of a write transaction before issuing a precharge command tek Minimum write to read command delay The controller waits for this period of time after the end of a write command before issuing a subsequent read command to the same bank This timing parameter is specified in clock cycles and the value is rounded off to the next integer ps DQ output access time toasck ps 00 output access time from CK CK signals 10050 ps
128. ndbook Volume 3 m Timing simulation disabled m Stratix and Stratix IV m DIMM support m Full rate interfaces Section II DDR3 SDRAM Controller with ALTMEMPHY IP User Guide The DDR3 SDRAM Controller with ALTMEMPHY IP does not support the following features and devices Partial burst and unaligned burst in ECC and non ECC mode when DM pins are June 2011 Altera Corporation Chapter 1 About This IP 1 5 MegaCore Verification MegaCore Verification Altera performs extensive random directed tests with functional test coverage using industry standard Denali models to ensure the functionality of the DDR3 SDRAM Controller with ALTMEMPHY IP Resource Utilization Table 1 4 shows the resource utilization data for the ALTMEMPHY megafunction and the DDR3 high performance controller II Table 1 4 Resource Utilization in Arria Il GX Devices Protocol wae Combinational Logic Mem M9K M144K Memor Bits ALUTS Registers ALUTs Blocks Blocks y Bits Controller 8 1 883 1 505 10 0 4 352 DDR3 16 1 893 1 505 10 4 0 8 704 Half rate 64 1 946 1 521 18 15 0 34 560 72 1 950 1 505 10 17 0 39 168 Controller PHY 8 3 389 2 760 12 4 0 4 672 DDR3 16 3 457 2 856 12 7 0 9 280 Half rate 64 3 793 3 696 20 24 0 36 672 72 3 878 3 818 12 26 0 41 536 System Requirements The DDR3 SDRAM Controller with ALTMEMPHY IP is a part of the MegaCore IP Library which is distrib
129. ne 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 5 10 Chapter 5 Functional Description ALTMEMPHY ALTMEMPHY Signals Read Data Alignment Data alignment is the process controlled by the sequencer to ensure the correct captured read data is present in the same half rate clock cycle at the output of the read data DPRAM Data alignment is implemented using memory blocks in the core of devices Postamble Protection A dedicated postamble register controls the gating of the shifted DOS signal that clocks the DQ input registers at the end of a read operation Any glitches on the DQS input signals at the end of the read postamble time do not cause erroneous data to be captured as a result of postamble glitches The postamble path is also calibrated to determine the correct clock cycle clock phase shift and delay chain settings ALTMEMPHY Signals This section describes the ALMEMPHY megafunction signals for DDR3 SDRAM variants Table 5 2 through Table 5 4 show the signals Signals with the prefix connect the PHY with the memory device ports with the prefix ct1 connect the PHY with the controller The signal lists include the following signal groups m I O interface to the SDRAM devices Clocks and resets External DLL signals User mode calibration OCT control Write data interface Read data interface Address and command interface Cali
130. no delays in the testbench The ALTMEMPHY megafunction is statically configured to provide the correct write and read latencies Skip calibration provides the fastest simulation time for DDR3 SDRAM interfaces Use the generated or vendor DDR3 SDRAM simulation models for this simulation option Skip calibration simulation between 300 MHz and 400 MHz supports CAS latency of 6 and a CAS write latency of 5 gt The additive latency must be disabled m Quick calibration performs a calibration on a single pin and chip select Available for x4 and x8 DDR3 SDRAM In quick calibration simulation mode the sequencer only does clock cycle calibration So there must be no delays DDR3 DIMM modeling for example in the testbench because no phase calibration is performed Quick calibration mode can be used between 300 MHz and 400 MHz Both the generated or vendor DDR3 SDRAM simulation models support burst length on the fly changes during the calibration sequence m Full calibration across all pins and chip selects This option allows for longer simulation time Available for x4 and x8 DDR3 SDRAM between 300 MHz and 400 MHz You cannot use the wizard generated memory model if you select Full Calibration You must use a memory vendor provided memory model that supports write leveling calibration External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section II DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Chapter 4
131. ntly open row when the burst reaches the end of the column On the other hand if your application has several masters that each use separate areas of memory choose the Chip Bank Row Column option This option allows you to use the top address bits to allocate a physical bank in the memory to each master The physical bank allocation avoids different masters accessing the same bank which is likely to cause inefficiency as the controller must then open and close rows in the same bank Enable auto precharge control Enable reordering Local to memory address mapping External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section II DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Chapter 3 Parameter Settings DDR3 SDRAM Controller with ALTMEMPHY Parameter Settings June 2011 3 15 Table 3 8 Controller Settings Part 2 of 2 Parameter Command queue look ahead depth Description Specifies a command queue look ahead depth value to control the number of read or write requests the look ahead bank management logic examines Local maximum burst count Specifies a burst count to configure the maximum Avalon burst count that the controller slave port accepts Reduce controller latency by Specifies in controller clock cycles a value by which to reduce the controller latency The default value is 0 but you have the option to choose 1 to enhance the latency performance of yo
132. ntrol of the postamble circuit m Generation of ct1 rdata valid m Dynamic termination Rt control timing The read latency ct1 rlat is advertised back to the controller This signal indicates how long it takes in ct1 clk clock cycles from assertion of ct1 doing read to valid read data returning on ct1 rdata The ctl rlat signal is only valid when calibration has successfully completed and never changes values during normal user mode Operation June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 5 26 Chapter 5 Functional Description ALTMEMPHY Using a Custom Controller The ALTMEMPHY provides a signal ct1_rdata_valid to indicate that the data on read data bus is valid The width of this signal varies between half rate and full rate designs to support the option to indicate that the read data is not word aligned Figure 5 12 and Figure 5 13 show these relationships Figure 5 12 Address and Command and Read Path Timing Full Rate Design ctl rlat 9 lt gt 1 2 3 4 5 6 7 8 9 ci odo t t t t t t t t t t t t t ctl cs n 1 1 1 1 1 1 1 1 1 1 1 1 1 ctl_doing_read i L Al i i i 1 1 1 1 1 1 1 906 ia mem dq 1 1 1 1 1 1 1 1 1 1 1 1
133. ock jitter Ta For more information about the VCO frequency range and the available phase shifts refer to the Clock Networks and PLLs chapter in the respective device family handbook June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 5 6 Chapter 5 Functional Description ALTMEMPHY Table 5 1 DDR3 SDRAM Clocking in Arria GX Devices Part 1 of 2 Block Description Table 5 1 shows the clock outputs that Arria II GX devices use Clock Name 1 phy clk 1x and aux half rate clk Postscale Counter C0 Phase Degrees 09 Clock Rate Half Rate Clock Network Type All Quadra nts Any 3 Quadrants 2 Global Global Notes The only clocks parameterizable for the ALTMEMPHY megafunction These clocks also feed into a divider circuit to provide the PLL scan_clk signal for reconfiguration that must be lower than 100 MHz mem clk 2x and aux full rate clk C1 09 Full Rate Regional 3 Global 4 Global This clock is for clocking DQS and as a reference clock for the memory devices mem clk 1x C2 09 Half Rate Global Regional This clock is for clocking DQS and as a reference clock for the memory devices write clk 2x C3 909 Full Rate Global Regional This clock is for clocking the data out of the DDR 1 0 0010 pins in advance of the DQS strobe or
134. oject names disk drive names file names file name extensions software utility names and GUI labels For example qdesigns directory D drive and chiptrip gdf file Italic Type with Initial Capital Letters Indicate document titles For example Stratix IV Design Guidelines italic type Indicates variables For example n 1 Variable names are enclosed in angle brackets For example file name and lt project name gt poft file Initial Capital Letters Indicate keyboard keys and menu names For example the Delete key and the Options menu Subheading Title Quotation marks indicate references to sections within a document and titles of Quartus 11 Help topics For example Typographic Conventions Courier type Indicates signal port register bit block and primitive names For example data1 tdi and input The suffix n denotes an active low signal For example resetn Indicates command line commands and anything that must be typed exactly as it appears For example c qdesigns tutorial chiptrip gdf Also indicates sections of an actual file such as a Report File references to parts of files for example the AHDL keyword SUBDESIGN and logic function names for example TRI An angled arrow instructs you to press the Enter key 1 2 3 and a b c and so on Numbered steps indicate a list of items when the sequence of the items is important such as
135. oller variation name al q wrapper mem pay se All ALTMEMPHY variations Generates sequencer for DDR3 SDRAM lt variation_name gt _al ite_dp t mem phy wr All ALTMEMPHY variations Generates the demultiplexing of data from half rate to full rate DDR data Table 2 5 shows the additional files generated by the high performance controller II that may be in your project directory Table 2 5 Controller Generated Files Part 1 of 2 Filename alt mem ddrx addr cmd v Description Decodes internal protocol related signals into memory address and command signals alt mem ddrx addr cmd wrap v A wrapper that instantiates the alt mem ddrx addr cmd v file alt mem ddrx ddr2 odt gen v Generates the on die termination ODT control signal for DDR2 memory interfaces alt mem ddrx ddr3 odt gen v Generates the on die termination ODT control signal for DDR3 memory interfaces alt mem ddrx odt gen v Wrapper that instantiates alt mem ddrx ddr2 odt gen v and alt mem ddrx ddr3 odt gen v This file also controls the ODT addressing scheme alt mem ddrx rdwr data tmg v Decodes internal data burst related signals to memory data signals alt mem d rx arbiter v Contains logic that determines which command to execute based on certain schemes alt mem ddrx burst gen v Converts internal DRAM aware commands to AFI signals
136. olume 3 June 2011 Altera Corporation Section II DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 5 23 os wn dk gt E gite eed es tes e Ds its ern hee ees T me e s Chapter 5 Functional Description ALTMEMPHY PHY to Controller Interfaces Figure 5 11 Word Unaligned Reads L LL FL FL WF i rap ic it specs s i e EL PE Spe tes ie nia ee ee pe eee LT M rn Sa 11 15 Ed Pheer alee eal or Tor om Pe he Role i ess o a Pepe epee Pee ss 5 zu 8 SEI uq Lr LL BF TSS PF ii a LE Er o o zu qd Li EFIE LP EF 341 o o T E c c c 5 o o 7 c 5 am T a 5 5 58 5 c 8 o c e 1 e oO c gt oO oO et o 9 I 5 29 E c 8 B 8 5 B 5 5 9 o o mi o 5 rdata bit vector is the number of controller ctl rlat External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide rd Advertised read latency cycles
137. onsible for every aspect of the interface including timing analysis and debugging This chapter describes the DDR3 SDRAM ALTMEMPHY megafunction which uses AFI as the interface between the PHY and the controller Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 5 2 Chapter 5 Functional Description ALTMEMPHY Block Description Block Description Figure 5 1 on page 5 2 shows the major blocks of the ALTMEMPHY megafunction and how it interfaces with the external memory device and the controller The ALTPLL megafunction is instantiated inside the ALTMEMPHY megafunction so that you do not need to generate the clock to any of the ALTMEMPHY blocks Figure 5 1 ALTMEMPHY Megafunction Interfacing with the Controller and the External Memory FPGA ALTMEMPHY Write Datapath Address and Command Memory t User Datapath Controller Logic External Memory Device Clock and Reset Management gt DLL PLL lt Read Datapath Sequencer The ALTMEMPHY megafunction comprises the following blocks Write datapath Address and command datapath Clock and reset management including DLL and PLL Sequencer for calibration Read datapath External Memory Interface Handbook Volume 3 June 2011 Altera C
138. ontroller is idle there is no queued transaction pending indicated by the local_ready signal asserted high m No refresh cycles occur before the transaction The latency for the high performance controller comprises many different stages of the memory interface June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 7 2 Chapter 7 Latency Figure 7 1 shows a typical memory interface read latency path showing read latency from the time a 1ocal read req assertion is detected by the controller up to data available to be read from the dual port RAM DPRAM module Figure 7 1 Typical Latency Path control doing rd FPGA Device Memory Device local read req PHY Latency T3 High Latency T2 includes CAS local addr Address Command Generation latency Controller mem cs n VO gt Latency T1 Lat T4 Read Datapath oe local_rdata Half Alignment and Capture rate Synchronization mem das mem_clk Resynchronization Shifted mem clk n Clock DQS Clock PLL PLL 0 or 180 phy_clk Table 7 1 shows the different stages that make up the whole read and write latency that Figure 7 1 shows Table 7 1 High Performanc
139. ontroller responds by deasserting the acknowledge signal when the memory is no longer in self refresh mode If a user controlled refresh request and a system generated refresh request occur at the same time the user controlled refresh takes priority the system generated refresh is processed only after the user controlled refresh request is completed Automatic Power Down with Programmable Time Out The controller automatically places the memory in power down mode to save power if the requested number of idle controller clock cycles is observed in the controller The Auto Power Down Cycles parameter on the Controller Settings tab allows you to specify a range between 1 to 65 535 idle controller clock cycles The counter for the programmable time out starts when there are no user read or write requests in the command queue Once the controller places the memory in power down mode it responds by asserting the acknowledge signal local_power_down_ack June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 6 6 ODT Generation Logic The on die termination ODT generation logic generates the necessary ODT signals for the controller based on the scheme that Altera recmmends DDR3 SDRAM Chapter 6 Functional Description High Performance Controller Il Controller Features Descriptions Table 6 1 shows which ODT signal is enabled for single slot single chip s
140. orporation Section II DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Chapter 5 Functional Description ALTMEMPHY 5 3 Block Description The major advantage of the ALTMEMPHY megafunction is that it supports an initial calibration sequence to remove process variations in both the Altera device and the memory device In Arria series devices the DDR3 SDRAM ALTMEMPHY calibration process centers the resynchronization clock phase into the middle of the captured data valid window to maximize the resynchronization setup and hold margin During the user operation the VT tracking mechanism eliminates the effects of VT variations on resynchronization timing margin Calibration The sequencer performs calibration to find the optimal clock phase for the memory interface For information about calibration refer to Chapter 3 of the Debugging section in volume 4 of the External Memory Interface Handbook Address and Command Datapath Ls This topic discusses the address and command datapath Arria Il GX Devices The address and command datapath is responsible for taking the address and command outputs from the controller and converting them from half rate clock to full rate clock Two types of addressing are possible m 1T full rate the duration of the address and command is a single memory clock cycle nem clk 2x Figure 5 2 This applies to all address and command signals in full rate designs or mem cs n mem cke and mem odt signal
141. ory Interface Handbook Volume 3 June 2011 Altera Corporation Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 8 12 Chapter 8 Timing Diagrams DDR3 High Performance Controller 11 The following sequence corresponds with the numbered items in Figure 8 6 1 The user logic asserts a local write req signal with a size of 2 and an address of 0x0000F1C The controller issues the necessary memory command and address signals to the ALTMEMPHY megafunction for it to send to the memory device The controller asserts the afi_wdata_valid signal to indicate to the ALTMEMPHY megafunction that valid write data and write data masks are present on the inputs to the ALTMEMPHY megafunction The controller asserts the afi burst signals to control the timing of the DOS signal that the ALTMEMPHY megafunction issues to the memory The ALTMEMPHY megafunction issues the write command and sends the write data and write DQS to the memory For transactions with a local size of two the local write reqand local ready signals must be high for two clock cycles so that all the write data can be transferred to the controller Half Rate Write Operation Merging Writes Figure 8 7 Write Operation for HPC II Merging Writes hy ck Local Interface local address 25 0 local size 4 0 local ready local burstbegin local be 3 0 write req local wdata 31 0 Controller AFI afi addi 27 0 afi ba 5 0 afi cs 3 0 AF
142. ory Interface Handbook Volume 3 June 2011 Altera Corporation Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 3 Parameter Settings ALTMEMPHY Parameter Settings The Parameter Settings page in the ALTMEMPHY parameter editor Figure 3 1 allows you to parameterize the following settings m Memory Settings m PHY Settings Board Settings Figure 3 1 ALTMEMPHY Parameter Settings Page MegaWizard Plug In Manager ALTMEMPHY x 4 ALTMEMPHY General Settings Device family Stratix Speed grade 4 PLL reference clock frequency MHz 10000 ps Memory clock frequency 200 MHz 5000 ps Controller data rate Half Enable Half Rate Bridge Local interface clock frequency 100 0 Local interface width Show in Memory Presets List __ Memory Presets Parameter Presets Memory type Micron MT4JTFB5464A Y 80B Memory vendor Micron 41 128 8 25 Memory format DDR2 SDRAM Micron MT41J255M8JE 25 Maximum memory frequen DDR3 SDRAM Micron MT8JTF12854A Y 80B Micron MTBJTF12884A Y 1G1 Micron MT18JBF25672PDY 1G4 Show All Load Preset Selected memory preset JEDEC DDR 400 128Mb x8 Modify parameters Description DDR SDRAM 200MHz 16MB 8 bits wide Discrete Device CAS 3 0 1 Chip Select I Info The PLL will be generated with Memory clock frequency 200 0 MHz and 48
143. ory interface MEM IF DQ PER DQS The number of mem 4411 pins per mem pin MEM IF CLK PAIR COUNT The number of mem clk mem n pairs in the interface PHY to Controller Interfaces The following section describes the typical modules that are connected to the ALTMEMPHY variation and the port name prefixes each module uses This section also describes using a custom controller This section describes the AFI The AFI standardizes and simplifies the interface between controller and PHY for all Altera memory designs thus allowing you to easily interchange your own controller code with Altera s high performance controller The AFI PHY includes an administration block that configures the memory for calibration and performs necessary mode registers accesses to configure the memory as required these calibration processes are different Figure 5 5 shows an overview of the connections between the PHY the controller and the memory device External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section II DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Chapter 5 Functional Description ALTMEMPHY PHY to Controller Interfaces Ka Altera recommends that you use the AFI for new designs Figure 5 5 AFI PHY Connections 5 17 Altera Device local_wdata AFI Controller 1 4 local_rdata ctl_addr ctl_cas_n ctl we n amp ctl r
144. other available components to quickly create a Qsys system with a DDR3 SDRAM controller such as the Nios II processor and scatter gather direct memory access SDMA controllers Qsys automatically creates the system interconnect logic and system simulation environment For more information about Osys refer to volume 1 of the Quartus II Handbook For more information about how to use controllers with Osys refer to the ALTMEMPHY Design Tutorials section in volume 6 of the External Memory Interface Handbook For more information on the Quartus II software refer to the Quartus II Help Specifying Parameters To specify the parameters for the DDR3 SDRAM Controller with ALTMEMPHY IP using the Osys flow perform the following steps 1 In the Quartus II software create a new Quartus II project with the New Project Wizard 2 On the Tools menu click Osys 3 Foranew system specify the system name and language 4 Add DDR3 SDRAM Controller with ALTMEMPHY to your system from the System Contents tab gt The DDR3 SDRAM Controller with ALTMEMPHY is in the SDRAM folder under the Memories and Memory Controllers folder 5 In the DDR3 SDRAM Controller with parameter editor specify the required parameters on all pages in the Parameter Settings tab External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section II DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Chapter 2 Getting Started Qsys F
145. owing memory address in half rate mode mem row address 0x0000 mem col address 0x0000 2 0x0000 mem bank address 0x00 The user logic asserts a second 1ocal write req signal with a size of 1 and address of 1 1ocal ready signal is asserted along with the 1ocal write req signal which indicates that the controller has accepted this request Since the second write request is to a sequential address same row same bank and column increment by 1 this write and the first write can be merged at the memory transaction The controller issues the necessary memory command and address signals to the ALTMEMPHY megafunction for it to send to the memory device The controller asserts the afi_wdata_valid signal to indicate to the ALTMEMPHY megafunction that valid write data and write data masks are present on the inputs to the ALTMEMPHY megafunction The controller asserts the afi burst signals to control the timing of the DOS signal that the ALTMEMPHY megafunction issues to the memory The ALTMEMPHY megafunction issues the write command and sends the write data and write DOS to the memory External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide BPIND 1951 dl AHdINIALLTV 191104109 NVHOS II 1011295 euinjoA eoeji91u Jeul9 X3 1106 eunr 012100109 Bally Write Read Write Read Operation Figure 8 8 Write Read S
146. phy v Contains all modules of the ALTMEMPHY variation except for the sequencer This file is always in Verilog HDL language regardless of the language you chose in the MegaWizard Plug In Manager The DDR3 SDRAM sequencer is included in the variation name mem phy seq vhd file variation name hb v cmp Black box file for your ALTMEMPHY variation depending whether you are using Verilog HDL or VHDL language variation name ddr pins tcl Contains procedures used in the variation name ddr timing sdc and variation name report timing tcl files variation name ddr timing sdc Contains timing constraints for your ALTMEMPHY variation variation name pin assignments tcl Contains 1 0 standard drive strength output enable grouping DQ DQS grouping and termination assignments for your ALTMEMPHY variation If your top level design pin names do not match the default pin names or a prefixed version edit the assignments in this file variation name report timing tcl Script that reports timing for your ALTMEMPHY variation during compilation Table 2 4 shows the modules that are instantiated in the variation name alt mem phy v vhd file A particular ALTMEMPHY variation may or may not use any of the modules depending on the memory standard that you specify Table 2 4 Modules in variation name alt mem phy vFile Part 1 of 2 dr cmd var
147. processes the command and sends it to the timing bank pool Once all timing requirements are met the timing bank pool sends the command to the arbiter When rank timing requirements are met the arbiter grants the command request from the timing bank pool and passes the read command to the AFI interface The AFI interface receives the read command from the arbiter and passes the command to the PHY The PHY receives the read command through the AFI interface and returns read data through the AFI interface The AFI interface passes the read data from the PHY to the read data buffer The read data buffer sends the read data to the master through the input interface Read Modify Write Command A read modify write command can occur when enabling ECC for partial write and for ECC correction commands When a read modify write command is issued the following events occur June 2011 Altera Corporation The command generator issues a read command to the timing bank pool The timing bank pool and arbiter passes the read command to the PHY through the AFI interface The PHY receives the read command reads data from the memory device and returns the read data through the AFI interface The read data received from the PHY passes to the ECC block The read data is processed by the write data buffer When the write data buffer issues a read modify write data ready notification to the command generator the command generator issues a writ
148. put driver impedance ine Some devices may not have RZQ 6 available as an option Be sure to check the memory device datasheet before choosing this option 5 0 6 0 7 0 8 0 Sets the delay clock cycles from the read command Memory CAS latency setting 9 0 10 0 cycles to the first output data from the memory Memory additive CAS latency Disable CL 1 cycles Allows you to add extra latency in addition to the CAS setting CL 2 y latency setting Memory write CAS latency Sets the delay in clock cycles from the write command setting CWL cycles to the first expected data to the memory Full array Half array BA 2 0 000 001 010 011 Quarter array Determine whether you want to self refresh only certain arrays instead of the full array According to the DDR3 SDRAM specification data located in the array beyond the specified address range are lost if self refresh is entered when you use this This option is not supported by the DDR3 SDRAM Controller with ALTMEMPHY IP so set to Full Array if you are using the Altera Half array controller BA 2 0 100 101 110 111 Quarter array BA 2 0 110 111 Eighth array BA 2 0 111 Manual SR Sets the auto self refresh method for the memory Memory auto self refresh reference SRT or device The DDR3 SDRAM Controller with ALTMEMPHY method ASR enable IP currently does not support the ASR option that you Optional need for extended temperature memory self
149. r CAL FAIL register shows a value of 1 2 CAL REQ 0 Read write 7 3 Reserved 0 Reserved for future use 13 8 Reserved 0 Reserved for future use 30 14 Reserved 0 Reserved for future use June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 6 26 Table 6 17 Controller Register Map Part 2 of 5 Chapter 6 Functional Description High Performance Controller Il Register Maps Address 0x110 Bit 15 0 AUTO PD CYCLES Default 0x0 Access Read write Description The number of idle clock cycles after which the controller should place the memory into power down mode The controller is considered to be idle if there are no commands in the command queue Setting this register to 0 disables the auto power down mode The default value of this register depends on the values set during the generation of the design Reserved Reserved for future use Reserved Reserved for future use Reserved Reserved for future use Reserved Reserved for future use 21 20 ADDR_ORDER 00 Read write 00 Chip row bank column 01 Chip bank row column 10 reserved for future use 11 Reserved for future use 22 REGDIMM Read write Setting this bit to 1 enables REGDIMM support in the controller 24
150. r 6 Functional Description High Performance Controller 11 6 15 Top Level Signals Description Table 6 9 Local Interface Signals Part 2 of 4 Signal Name local_burstbegin Direction Input Description The Avalon burst begin strobe which indicates the beginning of an Avalon burst Unlike all other Avalon MM signals the burst begin signal does not stay asserted if local_ready is deasserted For write transactions assert this signal at the beginning of each burst transfer and keep this signal high for one cycle per burst transfer even if the slave deasserts local_ready The IP core samples this signal at the rising edge of phy_clk when local write req is asserted After the slave deasserts the local_ready signal the master keeps all the write request signals asserted until local_ready signal becomes high again For read transactions assert this signal for one clock cycle when read request is asserted and 1ocal address from which the data should be read is given to the memory After the slave deasserts 1ocal ready waitrequest nin Avalon interface the master keeps all the read request signals asserted until 1 1 ready becomes high again local read req Input Read request signal You cannot assert read request and write request signals at the same time The controller must deassert reset phy clk n before you can assert 1 1 autopch req local refresh req Input User controlled refresh request If
151. r controller variation The addresses are then read back to ensure that the controller has issued the correct signals to the memory This test is only applicable in full rate mode when the local burst size is two You can skip this test by setting the test incomplete writes onsignalto logic zero Byte enable data mask pin operation The state machine issues two sets of write commands the first of which clears a range of addresses The second set of write commands has only one byte enable bit asserted The state machine then issues a read request to the same addresses and the data is verified This test checks if the data mask pins are operating correctly You can skip this test by setting the test dm pin onsignal to logic zero Address pin operation The example driver generates a series of write and read requests starting with an all zeros pattern a walking one pattern a walking zero pattern and ending with an all zeros pattern This test checks to make sure that all the individual address bits are operating correctly You can skip this test by setting the test addr pin on signal to logic zero External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 6 22 Chapter 6 Functional Description High Performance Controller Il m Low power mode operation Example Top Level File The example driver requests the controller to place the memory into power down and self refresh states and hol
152. r map for ALTMEMPHY To access the ALTMEMPHY register map connect the ALTMEMPHY Debug interface signals using the Avalon MM protocol After configuring the ALTMEMPRHY register map initialize a calibration request by setting bit 2 in the CSR register map address 0x100 for the mode register settings to take effect June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 6 24 Table 6 16 ALTMEMPHY Register Map Part 1 of 2 Chapter 6 Functional Description High Performance Controller Il Register Maps Address 0x005 Bit Name Default Access Description 2 0 Burst length 8 Read only This value is set to 8 3 BT 0 Read only This value is set to 0 CAS latency setting The default value for these bits is set by the MegaWizard CAS 6 4 CAS latency Read write Latency setting for your controller instance You must set this value in the CSR interface register map 0x126 as well 7 Reserved 0 Reserved for future use Not used by the controller but you can set 8 DLL 0 Read write and program into the memory device mode register Write recovery twp setting The default value for these bits is set by the MegaWizard Write Recovery setting for La I your controller instance You must set thi svalue in CSR interface register map 0x126 as well 12 PD 0 1 Read only This valu
153. r to Automatic Power Down with Programmable Time Out on page 6 5 Determines the desired number of idle controller clock cycles before the controller places the external memory device in a Enable power down controls Auto power down cycles power down mode The legal range is 1 to 65 535 The auto power down mode is disabled if you set the value to 0 clock cycles Enable user auto refresh Turn on to enable the controller to allow you to issue a single controls refresh Turn on to enable the auto precharge control on the controller top level Asserting the auto precharge control signal while requesting a read or write burst allows you to specify whether or not the controller should close auto precharge the current opened page at the end of the read or write burst Turn on to allow the controller to perform command and data reordering to achieve the highest efficency Starvation limit for each Specifies the number of commands that can be served before a command waiting command is served The legal range is from 1 to 63 Allows you to control the mapping between the address bits on the Avalon interface and the chip row bank and column bits on the memory interface If your application issues bursts that are greater than the column size of the memory device choose the Chip Row Bank Column option This option allows the controller to use its look ahead bank management feature to hide the effect of changing the curre
154. ra Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 6 4 Chapter 6 Functional Description High Performance Controller Il Controller Features Descriptions AFI Interface The AFI interface provides communication with the memory device through the physical layer logic PHY For more information about AFI signals refer to AFI Signals on page 5 11 CSR Interface The CSR interface provides communication with your system s internal control status registers Controller Features Descriptions The following sections describe main features of the memory controller Data Reordering The controller implements data reordering to maximize efficiency for read and write commands The controller can reorder read and write commands as necessary to mitigate bus turn around time and reduce conflict between rows Inter bank data reordering reorders commands going to different bank addresses Commands going to the same bank address are not reordered This reordering method implements simple hazard detection on the bank address level The controller implements logic to limit the length of time that a command can go unserved This logic is known as starvation control In starvation control a counter is incremented for every command served You can set a starvation limit to ensure that a waiting command is served immediately when the starvation counter reaches the specified
155. rbox flow Arria II GX devices only Quartus II IP file for the PLL that your ALTMEMPHY variation name alt mem phy pll qip variation uses that contains the files associated with this megafunction The PLL megafunction file for your ALTMEMPHY lt variation_name gt _alt_mem_phy_pll v vhd variation generated based on the language you chose in the MegaWizard Plug In Manager Black box file for the PLL used in your ALTMEMPHY variation Typically unused Contains the sequencer used during calibration This file is always in VHDL language regardless of the language you chose in the MegaWizard Plug In Manager A wrapper file for compilation only that calls the variation name alt mem phy seq wrapper v vhd sequencer file created based on the language you chose in the MegaWizard Plug In Manager variation name alt mem phy pll bb v cmp variation name phy seq vhd External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Chapter 2 Getting Started Generated Files Table 2 3 ALTMEMPHY Generated Files Part 2 of 2 2 9 File Name lt variation_name gt _alt_mem_phy_seq_wrapper vo vho Description A wrapper file for simulation only that calls the sequencer file created based on the language you chose in the MegaWizard Plug In Manager variation name alt mem
156. rds Memory format Discrete Device Arria II GX devices only support DDR3 SDRAM components without leveling for example Discrete Device memory format Maximum memory frequency See the memory device datasheet MHz Sets the maximum frequency supported by the memory Column address width 10 12 bits Defines the number of column address bits for your interface Row address width 12 16 bits Defines the number of row address bits for your interface If your DDR3 SDRAM device s row address bus is 12 bit wide set the row address width to 13 and set the 13 bit to logic level low or leave the 13 bit unconnected to the memory device in the top level file Bank address width bits Defines the number of bank address bits for your interface June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 3 6 Table 3 3 DDR3 SDRAM Attributes Settings Part 2 of 2 Chapter 3 Parameter Settings ALTMEMPHY Parameter Settings Maximum memory frequency for CAS latency 8 0 Maximum memory frequency for CAS latency 9 0 Maximum memory frequency for CAS latency 10 0 Parameter Name Range 7 Units Description Defines the number of chip selects on each device in your Chip selects per device 10r2 bits interface Currently calibration is done with all ranks but
157. read data m The write response channel which is an AXI protocol Te For information about the Avalon interface refer to Avalon Interface Specifications Controller PHY Interface The interface between the controller and the PHY is part of the AFI interface The controller assumes that the PHY performs all necessary calibration processes without any interaction with the controller For more information about AFI signals refer to AFI Signals on page 5 11 Memory Side Band Signals This section describes supported side band signals Self Refresh Low Power Interface The optional low power self refresh interface consists of a request signal and an acknowledgement signal which you can use to instruct the controller to place the memory device into self refresh mode This interface is clocked by afi clk When you assert the request signal the controller places the memory device into self refresh mode and asserts the acknowledge signal To bring the memory device out of self refresh mode you deassert the request signal the controller then deasserts the acknowledge signal when the memory device is no longer in self refresh mode External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section 1 DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Chapter 6 Functional Description High Performance Controller 11 6 11 User Controller Refresh Interface The optional user controlled refresh interface consists o
158. read data timing calculations Voltage and temperature VT tracking that guarantees maximum stable performance for DDR3 SDRAM interface Self contained datapath that makes connection to an Altera controller or a third party controller independent of the critical timing paths Easy to use parameter editor The ALTMEMPHY megafunction supports DDR3 SDRAM components without leveling supports DDR3 SDRAM components without leveling for Arria II GX devices using T topology for clock address and command bus m Supports multiple chip selects The DDR3 SDRAM PHY without leveling fy Ax is 400 MHz for single chip selects No support for data mask DM pins for x4 DDR3 SDRAM DIMMs or components so select No for Drive DM pins from FPGA when using x4 devices The ALTMEMPHY megafunction supports half rate DDR3 SDRAM interfaces only In addition Table 1 3 shows the features provided by the DDR3 SDRAM HPC and HPC II Table 1 3 DDR3 SDRAM HPC Features Part 1 of 2 Features HPC Half rate controller v Support for AFI ALTMEMPHY Support for Avalon Memory Mapped Avalon MM local interface v Support for Native local interface Configurable command look ahead bank management with in order reads and writes External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Table 1 3 DDR3 SDRAM Features Part 2 of 2 Chapter
159. reconfig reprogram request long pulse E phy_clk pSETQ 05 0 clk_div_reset_ams_n_r Pus Tpl reconfig_reset_ams_n cine Circuit F T ie v DSETg pSETQ reset n pSETQ DSETg clk_divider_reset_n ana pl lt gt clk_div_reset_ams_n ia reprogram_ pena I request ams i e bd dir pll_reconfig_reset_n phasestep locked 4 reset master ams resel_request_n 1 phaseupdown bal s pll_ref_clk D DSETQ ee clock 1 Optional global_reset_n reset gt reset requestn L 4 areset l edgedetectand aclive HIGH T 1 resetcounter 1 PLL gt 1 eae 1 1 1 1 soft_reset_n i global_or_soft_reset_n phy_internal_reset_n PHY resets 1 Reset Pipes 1 1 1 1 Uc NU Read Datapath This topic discusses the read datapath Arria 1 GX Devices The read datapath logic captures data sent by the memory device and subsequently aligns the data back to the system clock domain The read datapath for DDR3 SDRAM P consists of the following three main blocks m Data capture m Data resynchroniz
160. roller four times the memory data bus for a half rate controller local write req Input Write request signal You cannot assert read request and write request signal at the same time The controller must deassert reset phy n before you can assert local write req June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 6 16 Chapter 6 Functional Description High Performance Controller Il Top Level Signals Description Table 6 9 Local Interface Signals Part 3 of 4 Signal Name local_autopch_req Direction Input Description User control of autoprecharge If you turn on Enable Auto Precharge Control the local autopch req signal becomes available and you can request the controller to issue an autoprecharge write or autoprecharge read command These commands cause the memory to issue a precharge command to the current bank at the appropriate time without an explicit precharge command from the controller This feature is particularly useful if you know the current read or write is the last one you intend to issue to the currently open row The next time you need to use that bank the access could be quicker as the controller does not need to precharge the bank before activating the row you wish to access Upon receipt of the 1ocal autopch req signal the controller evaluates the pending commands in the command
161. s of 0x000004 The controller issues the necessary memory command and address signals to the ALTMEMPHY megafunction for it to send to the memory device The controller asserts the afi_wdata_valid signal to indicate to the ALTMEMPHY megafunction that valid write data and write data masks are present on the inputs to the ALTMEMPHY megafunction The controller asserts the afi burst signals to control the timing of the DOS signals that the ALTMEMPHY megafunction issues to the memory The controller issues the first read memory command and address signals to the ALTMEMPHY megafunction for it to send to the memory device The controller asserts the afi doing rd signal to indicate to the ALTMEMPHY megafunction the number of clock cycles of read data it must expect for the first read The ALTMEMPHY megafunction uses the doing rd signal to enable its capture registers for the expected duration of memory burst The ALTMEMPHY megafunction issues the write command and sends the write data and write DOS to the memory The ALTMEMPHY megafunction issues the first read command to the memory and captures the read data from the memory The ALTMEMPHY megafunction returns the first data read to the controller after resynchronizing the data to the phy_clk domain by asserting the afi_rdata_valid signal when there is valid read data on the afi_rdata bus External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEM
162. s determined during the calibration stage The captured data rdata p captured and rdata_n_captured is synchronized to the resynchronization clock resync clk 2x refer to Figure 5 4 For Arria II GX devices the ALTMEMPHY instances an ALTDO DOS megafunction that instantiates the required IOEs for all the DO and DOS pins Data Demultiplexing Data demultiplexing is the process of changing the SDR data into HDR data Data demultiplexing is required to bring the frequency of the resynchronized data down to the frequency of the system clock so that data from the external memory device can ultimately be brought into the FPGA controller clock domain Before data capture the data is DDR and n bit wide After data capture the data is SDR and 2n bit wide After data demuxing the data is HDR of width 4n bits wide The system clock frequency is half the frequency of the memory clock Demultiplexing is achieved using a dual port memory with a 2n bit wide write port operating on the resynchronization clock SDR and a 4n bit wide read port operating on the PHY clock HDR The basic principle of operation is that data is written to the memory at the SDR rate and read from the memory at the HDR rate while incrementing the read and write address pointers As the SDR and HDR clocks are generated the read and write pointers are continuously incremented by the same PLL and the 4n bit wide read data follows the 2n bit wide write data with a constant latency Ju
163. s in half rate designs m 2T half rate the duration of the address and command is two memory clock cycles For half rate designs the ALTMEMPHY megafunction supports only a burst size of four which means the burst size on the local interface is always set to 1 The size of the data is 4n bits wide on the local side and is n bits wide on the memory side To transfer all the 4n bits at the double data rate two memory clock cycles are required The new address and command can be issued to memory every two clock cycles This scheme applies to all address and command signals except for mem cs n mem and mem odt signals half rate mode Refer to Table 5 1 on page 5 6 to see the frequency relationship of mem 1 2x with the rest of the clocks June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Chapter 5 Functional Description ALTMEMPHY Block Description Figure 5 2 shows a 1T chip select signal mem cs n which is active low and disables the command in the memory device All commands are masked when the chip select signal is inactive The mem cs n signal is considered part of the command code Figure 5 2 Arria GX Address and Command Datapath
164. s twice that of the memory data bus width m Half rate controllers For one chip select width row bits bank bits column bits 2 For multiple chip selects width chip bits row bits bank bits column bits 2 If the bank address is 2 bits wide row is 13 bits wide and column is 10 bits wide the local address is 23 bits wide To map 1ocal address to bank row and column address local_address is 23 bits wide local_address 22 10 row address 12 0 local_address 9 8 bank address 1 0 local address 7 0 column address 9 2 The IP core ignores two LSBs of the column address on the memory side because the local data width is four times that of the memory data bus width local be Input Byte enable signal which you use to mask off individual bytes during writes local beis active high mem dm is active low To map 1ocal wdata and local be to mem dq and mem dm consider a full rate design with 32 bit 1ocal wdata and 16 bit dq Local lt 22334455 gt lt 667788AA gt lt BBCCDDEE gt Local be lt 1100 gt lt 0110 gt lt 1010 gt These values map to Mem dq lt 4455 gt lt 2233 gt lt 88AA gt lt 6677 gt lt DDEE gt lt BBCC gt Mem_dm lt 1 1 gt lt 0 0 gt lt 0 1 gt lt 1 0 gt lt 0 1 gt lt 0 1 gt External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide June 2011 Altera Corporation Chapte
165. serted 1 and mem 1 nare ctl mem clk disable Input COUNT disabled ctl_cal_success Output 1 A 1 indicates that calibration was successful ctl_cal fail Output 1 A 1 indicates that calibration has failed ser calte input 1 When asserted a new calibration sequence is ee req started Currently not supported ctl cal byte lane Input MEM IF DOS WIDTH x Indicates which DQS groups should be calibrated sel MEM CS WIDTH Not supported Note to Table 5 2 1 Referto Table 5 5 for parameter descriptions Table 5 4 Other Interface Signals Part 1 of 2 Signal Name Type Width Description External DLL Signals EDGE BEER Allows sharing DLL in this ALTMEMPHY instance with another dqs delay ctrl expor Output Wr ALTMEMPHY instance Connect the dqs delay ctrl export port t bm on the ALTMEMPHY instance with a DLL to the dqs delay ctrl import port on the other ALTMEMPHY instance DOS DELA Allows the use of DLL in another ALTMEMPHY instance in this dqs delay ctrl impor Input Mae up ALTMEMPHY instance Connect the dqs delay ctrl export port t i on the ALTMEMPHY instance with a DLL to the dqs delay ctrl import port on the other ALTMEMPHY instance Connects to the DQS delay logic when 911 import export is set Beau Ree 20 DELA 10 IMPORT Only connect if you are using a DLL offset which can gt Y Input Y WI otherwise be ti
166. sing ECC you must initialize memory before writing to it June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 6 8 Chapter 6 Functional Description High Performance Controller Il Controller Features Descriptions When single bit or double bit error occurs the ECC logic triggers the ecc interrupt signal to inform you that an ECC error has occurred When a single bit error occurs the ECC logic reads the error address and writes back the corrected data When a double bit error occurs the ECC logic does not do any error correction but it asserts theavl rdata errorsignalto indicate that the data is incorrect The 1 rdata error signal follows the same timing as the 1 rdata valid signal Enabling autocorrection allows the ECC logic to delay all controller pending activities until the correction completes You can disable autocorrection and schedule the correction manually when the controller is idle to ensure better system efficiency To manually correct ECC errors follow these steps 1 Whenan interrupt occurs read out the SBE ERROR register When a single bit error occurs the SBE ERROR register is equal to one 2 Read out the ERR ADDR register 3 Correct the single bit error by issuing a dummy write to the memory address stored in the ADDR register A dummy write is a write request with the local be signal zero that triggers a p
167. ss June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 7 4 Chapter 7 Latency External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide ANU 8 RYAN 8 Timing Diagrams This chapter details the timing diagrams for the DDR3 SDRAM high performance controller DDR3 High Performance Controller ll This section discusses the following timing diagrams for HPC II m Half Rate Read Burst Aligned Address Half Rate Write Burst Aligned Address Half Rate Read Non Burst Aligned Address Half Rate Write Non Burst Aligned Address Half Rate Read With Gaps Half Rate Write With Gaps Half Rate Write Operation Merging Writes Write Read Write Read Operation June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section 1 DDR3 SDRAM Controller with ALTMEMPHY IP User Guide BPIND 1951 dl AHdINIALLTV 191104109 NVHOS II 1011295 euinjoA eoeji91u Jeul9 X3 1106 eunr 012100109 219 Half Rate Read Burst Aligned Address Figure 8 1 Half Rate Read Operation for HPC II Burst Aligned Address phy ck Local Interface address 25 local local ready local burstbegin local read local_rdata 3t local_tdata_vali local 06 2 afi_addr 27 afi
168. t traffic patterns and reduced latency Memory Controller Architecture Figure 6 1 shows a high level block diagram of the overall memory interface architecture Figure 6 1 High Level Diagram of Memory Interface Architecture Memory Interface IP Memory Controller PHY Data Master Avalon MM or AXI Converter Avalon ST Interface AFI Interface AFI Interface External Memory CSR Interface CSR Master The memory interface consists of the memory controller logic block the physical PHY logic layer and their associated interfaces June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 6 2 Chapter 6 Functional Description High Performance Controller Il Memory Controller Architecture The memory controller logic block uses an Avalon Streaming Avalon ST interface as its native interface and communicates with the PHY layer by the Altera PHY Interface AFI The controller supports an Avalon Memory Mapped Avalon MM bus protocol Figure 6 2 shows a block diagram of the memory controller architecture Figure 6 2 Memory Controller Architecture Block Diagram Memory Controller Rank Timer __ Command Timing Bank 8 Generator Pool gt Arbiter n 2 8 Wri
169. te Command 6 19 Example Top Level Bie uude eR pe pt ete ed dede ed antes Als Sar 6 20 External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section 1 DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Contents Example Drive sess teret RR RR E b RE ER PER LER a rere duy 6 21 Register 6 23 ALTMEMPHY Register Map ERR RR EE E EET Resa E 6 23 Controller Register Map oii ass des i dba ha e dec deeded eee hari cera 6 25 Chapter 7 Latency Chapter 8 Timing Diagrams DDRS High Performance Controller re pe 8 1 Half Rate Read Burst Aligned Address 8 2 Half Rate Write Burst Aligned Address 8 4 Half Rate Read Non Burst Aligned Address 8 6 Half Rate Write Non Burst Aligned Address 8 8 Half Rate Read With Gaps tak crate conde Hee n e 8 10 Halt Rate Write With Ive proe oec Pee ne ed aden 8 11 Half Rate Write Operation Merging Writes 8 12 Write Read Write Read Operation 8 14 Additional Information
170. te Data Buffer z lt Read Data Buffer CSR Interface The following sections describe the blocks in Figure 6 2 Avalon ST Input Interface The Avalon ST interface serves as the entry point to the memory controller and provides communication with the requesting data masters T For information about the Avalon interface refer to Avalon Interface Specifications Command Generator The command generator accepts commands from the front end Avalon ST interface and from local ECC internal logic and provides those commands to the timing bank pool External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section II DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Chapter 6 Functional Description High Performance Controller 11 6 3 Memory Controller Architecture June 2011 Timing Bank Pool The timing bank pool is a parallel queue that works with the arbiter to enable data reordering The timing bank pool tracks incoming requests ensures that all timing requirements are met and upon receiving write data ready notification from the write data buffer passes the requests to the arbiter in an ordered and efficient manner Arbiter The arbiter determines the order in which requests are passed to the memory device When the arbiter receives a single request that request is passed immediately however when multiple requests
171. tem Optional Perform Yes Add Constraints Functional Simulation and Compile Design IP Complete Simulation Give Expected Results Debug Design June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 2 2 Chapter 2 Getting Started SOPC Builder Flow The SOPC Builder flow offers the following advantages m Generates simulation environment m Creates custom components and integrates them via the component wizard m Interconnects all components with the Avalon MM interface The MegaWizard Plug In Manager flow offers the following advantages m Allows you to design directly from the DDR3 SDRAM interface to peripheral device or devices m Achieves higher frequency operation SOPC Builder Flow The SOPC Builder flow allows you to add the DDR3 SDRAM Controller with ALTMEMPHY IP directly to a new or existing SOPC Builder system You can also easily add other available components to quickly create an SOPC Builder system with a DDR3 SDRAM controller such as the Nios II processor and scatter gather direct memory access SDMA controllers SOPC Builder automatically creates the system interconnect logic and system simulation environment St For more information about SOPC Builder refer to volume 4 of the Quartus II Handbook For more information about how to
172. terface protocol Specifies the local side interface between the user logic and the memory controller The Avalon MM interface allows you to easily connect to other Avalon MM peripherals The HPC II architecture supports only the Avalon MM interface Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 3 16 Chapter 3 Parameter Settings DDR3 SDRAM Controller with ALTMEMPHY Parameter Settings External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide BYA 4 Compiling and Simulating After setting the parameters for the MegaCore function you can now integrate the MegaCore function variation into your design and compile and simulate your design The following sections detail the steps you need to perform to compile and simulate your design Compiling the Design June 2011 Figure 4 1 shows the top level view of the Altera high performance controller design as an example of how your final design looks after you integrate the controller and the user logic Figure 4 1 High Performance Controller System Level Diagram Example Top Level File ALTMEMPHY 4 Example External gt High Driver Pass or Fail Memory DLL 1 Performance Device Controller PLL Note to Figure 4 1
173. ting the SOPC Builder System To complete the SOPC Builder system perform the following steps 1 In the System Contents tab select Nios II Processor and click Add 2 Onthe Nios II Processor page in the Core Nios II tab select altmemddr for Reset Vector and Exception Vector Change the Reset Vector Offset and the Exception Vector Offset to an Avalon address that is not written to by the ALTMEMPHY megafunction during its calibration process A CAUTION The ALTMEMPHY megafunction performs memory interface calibration every time it is reset and in doing so writes to a range of addresses If you want your memory contents to remain intact through a system reset you should avoid using these memory addresses This step is not necessary if you reload your SDRAM memory contents from flash every time you reset your system If you are upgrading your Nios system design from version 8 1 or previous ensure that you change the Reset Vector Offset and the Exception Vector Offset to AFI mode To calculate the Avalon MM address equivalent of the memory address range 0x0 to 0x47 multiply the memory address by the width of the memory interface data bus in bytes Refer to Table 2 1 for more Avalon MM addresses Table 2 1 Avalon MM Addresses for Mode DX ge OL Altera Corporation External gue Interface Reset Vector Offset Exception Vector Offset 8 0x60 0x80 16 0xAO0 0 0 32 0x120 0x140 64 0x240 0x26
174. uest a license file Altera emails you a license dat file If you do not have Internet access contact your local representative To use the DDR3 SDRAM HPC II contact your local sales representative to order a license Free Evaluation Altera s OpenCore Plus evaluation feature is only applicable to the DDR3 SDRAM HPC With the OpenCore Plus evaluation feature you can perform the following actions m Simulate the behavior of a megafunction Altera MegaCore function or AMPP M megafunction within your system m Verify the functionality of your design as well as evaluate its size and speed quickly and easily m Generate time limited device programming files for designs that include MegaCore functions m Program a device and verify your design in hardware You need to purchase a license for the megafunction only when you are completely satisfied with its functionality and performance and want to take your design to production External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section 1 DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Chapter 1 About This IP 1 7 Installation and Licensing OpenCore Plus Time Out Behavior OpenCore Plus hardware evaluation can support the following two modes of operation m Untethered the design runs for a limited time m Tethered requires a connection between your board and the host computer If tethered mode is supported by all megafunctions in a design the de
175. ur design at the expense of timing closure Enable configuration and status register interface Turn on to enable run time configuration and status retrieval of the memory controller Enabling this option adds an additional Avalon MM slave port to thememory controller top level that allows run time reconfiguration and status retrieving for memory timing parameters memory address size and mode register settings and controller features If the Error Detection and Correction Logic option is enabled the same slave port also allows you to control and retrieve the status of this logic Refer to Configuration and Status Register CSR Interface on page 6 11 Enable error detection and correction logic Turn on to enable error correction coding ECC for single bit error correction and double bit error detection Enable auto error correction Turn on to allow the controller to perform auto correction when the ECC logic detects a single bit error Alternatively you can turn off this option and schedule the error correction at a desired time for better system efficiency Multiple controller clock sharing This option is only available in SOPC Builder Flow Turn on to allow one controller to use the Avalon clock from another controller in the system that has a compatible PLL This option allows you to create SOPC Builder systems that have two or more memory controllers that are synchronous to your master logic Local in
176. ured PLL that must be resolved Calibration has failed and this output is set to 1 Notes to Table 5 4 1 The debug interface uses the simple Avalon MM interface protocol 2 These ports exist the Quartus II software even though the debug interface is for Altera s use only June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 5 16 Chapter 5 Functional Description ALTMEMPHY PHY to Controller Interfaces Table 5 5 shows the parameters that Table 5 2 through Table 5 4 refer to Table 5 5 Parameters Parameter Name DWIDTH RATIO Description The data width ratio from the local interface to the memory interface DWIDTH RATIO of 2 means full rate while DWIDTH RATIO of 4 means half rate LOCAL IF DWIDTH The width of the local data bus must be quadrupled for half rate and doubled for full rate IF DWIDTH The data width at the memory interface DWIDTH can have values that are multiples of MEM IF DQ PER DOS MEM IF DQS WIDTH The number of DQS pins in the interface MEM IF ROWADDR WIDTH The row address width of the memory device MEM IF BANKADDR WIDTH The bank address with the memory device MEM IF CS WIDTH The number of chip select pins in the interface The sequencer only calibrates one chip select pin MEM IF DM WIDTH The number of mem dm pins on the mem
177. user by asserting the local rdata validsignal when there is valid read data on the 1ocal rdata bus If the ECC logic is disabled there is no delay between the afi rdata and the local rdata buses If there is ECC logic in the controller there is one or three clock cycles of delay between the afi rdata and local rdata buses External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide BPIND 1951 dl AHdINIALLTV 191104109 NVHOS II 1011295 euinjoA eoeji91u Jeul9 X3 1106 eunr 012100109 Bally Half Rate Write Burst Aligned Address Figure 8 2 Half Rate Write Operation for HPC II Burst Aligned Address i LY W VL LY U UU U 1 Local Interface local_address 25 0000000 0000004 I 0000000 local size 4 02 local ready local burstbegin local be 3 local write req local wdata 31 Controller AFI afi addi 27 10001000 0000000 afi_ba 5 afi cs n 3 I F I F Command 2 Lact afi dm 3 F I afi wlat 4 0 afi dqs burst afi dqs bursi 1 afi wdata 31 EEFF001 F EEFF0011 AABBCCDD EEFFO011 afi wdata valid 1 3 0 AFI Memory Interface mem cke 1
178. uted with the Quartus II software and downloadable from the Altera website www altera com Ta For system requirements and installation instructions refer to Altera Software Installation amp Licensing June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 1 6 Chapter 1 About This IP Installation and Licensing Installation and Licensing Figure 1 2 shows the directory structure after you install the DDR3 SDRAM Controller with ALTMEMPHY IP where lt path gt is the installation directory The default installation directory on Windows is c altera lt version gt on Linux it is opt altera lt version gt Figure 1 2 Directory Structure C lt path gt Installation directory ip Contains the Altera MegaCore IP Library and third party IP cores Ll altera Contains the Altera MegaCore IP Library common Contains shared components L ddr3_high_pert Contains the DDR3 SDRAM Controller with ALTMEMPHY files SR lib Contains encypted lower level design files and other support files You need a license for the MegaCore function only when you are completely satisfied with its functionality and performance and want to take your design to production To use the DDR3 SDRAM HPC you can request a license file from the Altera web site at www altera com licensing and install it on your computer When you req
179. vice can operate for a longer time or indefinitely All megafunctions in a device time out simultaneously when the most restrictive evaluation time is reached If there is more than one megafunction in a design a specific megafunction s time out behavior may be masked by the time out behavior of the other megafunctions For MegaCore functions the untethered time out is 1 hour the tethered time out value is indefinite Your design stops working after the hardware evaluation time expires and the local ready output goes low June 2011 Altera Corporation External Memory Interface Handbook Volume 3 Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide 1 8 Chapter 1 About This IP Installation and Licensing External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section Il DDR3 SDRAM Controller with ALTMEMPHY IP User Guide BAN 2 Getting Started Design Flow You can implement the DDR3 SDRAM Controller with ALTMEMPHY IP using any of the following flows m SOPC Builder flow m Osysflow m MegaWizard Plug In Manager flow You can only instantiate the ALTMEMPHY megafunction using the MegaWizard Plug In Manager flow Figure 2 1 shows the stages for creating a system in the Quartus II software using the available flows Figure 2 1 Design Flow Select Design Flow Qsys or MegaWizard SOPC Builder pid Flow Specify Parameters Specify Parameters Complete SOPC Builder Sys
180. y asserting the chip select signal in alternative cycles back to back read or write commands can be issued 4 The address is incremented every other ac c1k 2x cycle gt Theac 2 clock is derived from either mem 1 2x when you choose 0 or 180 phase shift or write clk 2x when you choose 90 or 270 phase shift The address and command clock can be 0 90 180 or 270 from the system clock External Memory Interface Handbook Volume 3 June 2011 Altera Corporation Section II DDR3 SDRAM Controller with ALTMEMPHY IP User Guide Chapter 5 Functional Description ALTMEMPHY 5 5 Block Description Clock and Reset Management The clocking and reset block is responsible for clock generation reset management and phase shifting of clocks It also has control of clock network types that route the clocks which is handled in the variation name alt mem phy clk reset module in the variation name alt mem phy v vhd file Clock Management The clock management feature allows the ALTMEMPHY megafunction to work out the optimum phase during calibration and to track voltage and temperature variation relies on phase shifting the clocks relative to each other Certain clocks require phase shifting during the ALTMEMPHY megafunction Operation You can implement clock management circuitry using PLLs and DLLs The ALTMEMPHY MegaWizard Plug In Manager automatically generates an ALTPLL megafunction insta
181. y support means the core is verified with preliminary timing models for this device family The core meets all functional requirements but might still be undergoing timing analysis for the device family It can be used in production designs with caution m HardCopy Compilation means the core is verified with final timing models for the HardCopy device family The core meets all functional and timing requirements for the device family and can be used in production designs m HardCopy Companion means the core is verified with preliminary timing models for the HardCopy companion device The core meets all functional requirements but might still be undergoing timing analysis for HardCopy device family It can be used in production designs with caution External Memory Interface Handbook Volume 3 Section II DDR3 SDRAM Controller with ALTMEMPHY IP User Guide June 2011 Altera Corporation Chapter 1 About This IP Features Features June 2011 Altera Corporation Table 1 2 shows the level of support offered by the DDR3 SDRAM Controller with ALTMEMPHY IP to each of the Altera device families Table 1 2 Device Family Support Device Family Support Arria GX Final Other device families No support The ALTMEMPHY megafunction offers the following features Simple setup Support for the Altera PHY Interface AFI for DDR3 SDRAM on all supported devices Automated initial calibration eliminating complicated

DDR3 SDRAM Controller with ALTMEMPHY User Guide

Contents

Download Pdf Manuals

Related Search

Related Contents