Si86xxISO-EVB User's Guide
Contents
1. y QNO auo y avo E 25 9 1 Q 6 er 81 2 2 098 D gt 1 wy 9 8 881 8 8 xs y QNO 1 8 8 F ES 5 9 sa lt lt J lt lt fun 9 IL gt gt We F D QNO T f 8 B bm d i T i n va D gt gt gt w 7 1 5 8 6 ma lt lt RM wi 5 n a l g n 2 M 4 B 59 ERE S l 9 il ew Q s lt H o lt lt wi gt 1 gt agaz 5 5 A 1 gt 1 7B wai l SZ e i L ATA eed p g 21 2 1 4 le Ww f 5 als lt lt lt 7 JET 4 ue lt H 4 4 pow d nol i y Gan 1 1 QQA i 7 58 lt lt 1 lt lt 12 g8 lt H mali wi 1 lt 105 y QNO s los QNO S G l 1556 i 8 i S S LOI 1 T 9 8 g ISl 8 23 9981S Sl 8 DA12981S 1 9T nra vgssoas ih il x E dmi aw 010 60 o Rev 0 2 SILICON LABS Si86xxISO EVB UG 5 Bill of Materials Table 1 Si86xxISO Evaluation Board Bill of Materials2. lig 89 99 erii ex RE L AN I ke m NI e 4 4 n 4 5 B A i Ex 20 9 V 8 S 32 NOLLVIOSI l i 80 4 8 N V V lt 80 08 E 2 y 9 28 T m RI I 52 t M8 S pr ax G Han 5 eae b sl el J EEEE SI g G a G 5 G x ab EX P I 1 8 118 8 8 mig 88 iD o M 5 amp d z 8 8 A nd 2 A LL 20 4 5 aas kell lg 2 zaon W 7 L 1g 8 i meee LAUR SUO 83218 BA EE 2 5 5 g NOLLVIOSI 5 E NOLLVIOSI lee ecce o id lg 8 2 A A A LON 5 lg V V anov lt Mn 2 9 9 amp u igs ee Jal 58 ej XI ki KI 5 58 ine 2 ERGER ae IH LIII m 80 48 6 HDRIX4 6 Rev 0 2 SILICON LABS 5186 150 UG z JO 6 uonenje 3 051 98 5 9 aunbi4
3. Item Qty Ref Part Mfr Description Standoff Nylon 4 40 1 4 HEX 0 250 1 4 1 4 1902AK ND H542 ND Digikey HGT or EQ RoHS 23 1 0 uF X5R Ceramic 0805 16 2 12 1 12 PCC2249CT ND Digikey 10 OR EQ RoHS ue RES 1 SMT 0805 1 10 0 1 3 8 1 8 RR12P1 0KBCT ND Digikey OR EQ RoHS 4 2 11 12 S1011E 03 ND Digikev 5 HEADER 1 3 0 1 CTRS OR RoHS 5 2 Ji 2 S1011E 04 ND Digikev STAKE HEADER 1x4 0 1 CTRS OR EQ RoHS 6 2 J3 4 S1011E 05 ND Digikey STAKE HEADER 1x5 0 1 CTRS OR EQ RoHS 7 2 19 10 S1011E 06 ND Digikev 5 HEADER 1 6 0 1 CTRS OR EQ RoHS m STAKE HEADER 1X8 0 1 CTR GOLD 8 2 47 8 S2011E 08 ND Digikev OR EQ RoHS p STAKE HEADER 1X9 0 1 CTR GOLD 9 2 45 6 2011E 09 ND Digikey OR EQ RoHS IC 12 ISO 2 Ch 2 Bidirectional 1 7 MHz 10 1 U1 Si8600AD B IS Silicon Labs 5 kV SOL 16 RoHS IC 4 Ch 1 ISO 2 Bidirectional 11 1 U2 Si8605AD B IS Silicon Labs 2 Unidirectional 1 7 MHz 5 kV SOL 16 RoHS fa ISOpro Low Power 2 Channel Isolator 12 1 U6 Si8621BC B IS Silicon Labs 150 Mbps 3 75 kV 50 8 RoHS IC 5 Digital Isolator Low Power 13 1 U5 Si8655BA B IU Silicon Labs 5 Forward 150 Mbps 1 kV QSOP 16 RoHS IC 6 Channel Digital Isolator Low Power 14 1 U3 Si8663BD B IS Silicon Labs 3 Forward 3 Reverse 150 Mbps 5 SOL 16 RoHS IC 6 Channel Digital Isolator 3 Forward 3 15 1 04 Si8663EC
4. gt 1000 A m magnetic field immunity gt 30 kV us 4 kV HBM ESD immunity Si860x I C Compatible Bidirectional Isolators Bidirectional SDA and SCL 1 7 Mbps 35 mA open drain I O 3 to 5 5 V VDD supply range m Packaging and Isolation Rating Options WB SOIC 16 5 kV NB SOIC 16 3 75 kV NB SOIC 8 3 75 kV QSOP 16 1 kV RoHS compliant Rev 0 2 2 11 Copyright 2011 by Silicon Laboratories Si86xxISO EVB UG Si86xxISO EVB UG 2 Kit Contents The Si86xxISO Evaluation Kit contains the following items Si86xxISO based evaluation board Si86xxISO EVB shown in Figure 1 Si8600 Si8605 518621 518655 and 518663 CMOS digital isolators installed on the evaluation board SILICON LABS www silabs com isolation 1 C SMBus amp CMOS Digital Isolators 5 3 75 amp 1 kVrms ISOLATION RATING 2 Channel 2 Bidirectional 5 kVrms 1 7MHz I C 5 4 Chonnel e gt BDOUT 2 Bi 1 Fwd 1 Rev BDIN 1 5 kVrms 1 7MHz I C esera Si8605AD 6 Channel 3 Fwd 3 Rev 5 kVrms 150Mbps Digital 6 Channel 3 Fwd 3 Rev 3 75 kVrms 150Mbps Digital 5 Channel 5 Forward 1 kVrms 150Mbps Digital 2 Chonnel 1 Fwd 1 Rev 3 75 kVrms NI 150Mbps Digital o Si86xxISO EVB A Figure 1 Si86xxISO Evaluation Board Overview 4 e 2 Rev 0 2 ER SILICON LABS Si86xxlSO EVB UG 3 Hardware Overview and Setup Si86xxlSO evaluation board is populated
5. 2 illustrates the output A Pos 1 000 jus tins 4 10 12 27 Figure 3 500 kHz 5 V Peak Signal 4 Rev 0 2 SILICON LABS 5186 150 UG 3 2 12 Isolator Considerations After power 3 5 V has been supplied to the board connect a digital square wave input 5 Vpeak max with desired clock frequency up to 1 7 MHz to the desired input channel The Si8600 05 2 isolators have 1 pull up resistors already installed If these resistors are redundant with another board that is being used to evaluate the Si8600 05 the user should remove the redundant pull up resistors to accommodate adequate drive current for the test being performed Figure 4 illustrates Side B Pulling Up with Side A following for the Si8600 The Si8600 was powered from 3 V on both sides with a 100 kHz input test signal 4 10 11 04 l Figure 4 Side B Pulling Up Side A Following Note The test points in front of each device 1 mm spacing If desired the test points can be replaced with a 1 mm spacing terminal block to assist in evaluation Rev 0 2 5 SILICON LABS Si86xxISO EVB UG 4 Si86xxISO Evaluation Board Schematics
6. B IS1 Silicon Labs Reverse Low Power 150 Mbps 3 75 kV SO 16 RoHS Note All components on this BOM are lead free 8 Rev 0 2 SILICON LABS 5186 150 UG 6 Ordering Guide Table 2 Si86xxISO Evaluation Board Ordering Guide Ordering Part Number OPN Description Si86xxISO KIT Si86xx CMOS digital isolator evaluation board kit Rev 0 2 SILICON LABS Si86xxISO EVB UG DOCUMENT CHANGE LIST Revision 0 1 to Revision 0 2 m Updated BOM and schematics to reflect change from Rev A to Rev B silicon Rev 0 2 SILICON LABS 5186 150 UG NOTES SILICON LABS Rev 0 2 Si86xxISO EVB UG CONTACT INFORMATION Silicon Laboratories Inc 400 West Cesar Chavez Austin TX 78701 Tel 1 512 416 8500 Fax 1 512 416 9669 Toll Free 1 877 444 3032 Please visit the Silicon Labs Technical Support web page https www silabs com support pages contacttechnicalsupport aspx and register to submit a technical support request Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice Silicon Laboratories assumes no responsibility for errors and omissions and disclaims respo
7. with the following isolators Si8605 518621 518600 2 channel I C isolator 2 channel digital isolator 2 channel 12 isolator 2 channel digital isolator one forward one reverse 818455 5 channel digital isolator five forward Si8663 6 channel digital isolator three forward three reverse The board is designed to be powered from two separate supplies 2 5 5 5 V 500 mA that power all the isolators on the board VDD1 GND1 and VDD2 GND2 power the 5 kV isolators VDD3 GND3 and VDD4 GND4 power the 1 and 2 5 kV isolators Supplies as low as 2 5 V can be used If a user wants to evaluate an isolator other than the ones populated this can be accomplished by removing the footprint compatible device installed on the evaluation board and replacing it with the desired isolator device Figure 2 provides a silkscreen overview of the board 2 SILICON LABS www silabs com isolation 1 C SMBus amp CMOS Digital Isolators 5 3 75 amp 1 kVrms ISOLATION RATING 5 412 U6 SD Si8621BC SiB6xxISO EVB VDD 2 BSDA BSCL iL BSDA BDOUT BBIN 2 Bi 1 Fwd 1 Rev BSCL 2 17MHz i c GND2 2 Channel 2 2 Bidirectional 5 kVrms 1 7MHz I C 4 Channel 5 kVrms 6 Channel 3 Fwd 3 Rev 5 kVrms 150Mbps Digital 6 Channel 3 Fwd 3 Rev 3 75 kVrms 150Mbps Digital 5 Channel 5 Forward 1 kVrms 150Mbps Digital 2 Channel
8. 1 Fwd 1 Rev 3 75 kVrms 150Mbps Digital O Figure 2 Si86xxISO Evaluation Board Silkscreen SILICON LABS Rev 0 2 Si86xxISO EVB UG 3 1 Digital Isolator Considerations Si86xxISO evaluation board see Figure 1 provides a means of evaluating the Si861x 2x 3x 4x 5x 6x digital isolator families as well as the 518600 isolated family After power 2 5 5 V has been supplied to the board connect a digital input signal 5 Vpeak max with desired clock frequency up to 150 Mbps to the desired input channel To view the isolated channel s data transmission connect a scope probe to the output channel of interest There are various inputs and outputs on either side of the board depending on the device one chooses to evaluate as indicated by the silk screen The board can be used to measure propagation delay pulse width distortion channel channel matching pulse width skew and various other parameters The nominal output impedance of an isolator driver channel is approximately 50 40 which is a combination of the values of the on chip series termination resistor and the channel resistance of the output driver FET When driving loads where transmission line effects are a factor output pins should be terminated with 50 controlled impedance PCB traces Figure 3 illustrates the Si8621 transmitting a 500 kHz 3 Vpeak signal through the 518621 VDD1 and VDD2 were powered from 3 V Channel 1 illustrates the input and Channel
9. SILICON LABS Si86xxISO EVB UG Si86xxISO EVALUATION BOARD USER S GUIDE 1 Introduction Si86xxISO evaluation board allows designers to evaluate Silicon Lab s family of CMOS ultra low power isolators These isolators are CMOS devices employing RF coupler technology to transmit digital information across an isolation barrier Very high speed operation at low power levels is achieved These products are based on Silicon Laboratories proprietary RF isolation technology and offer shorter propagation delays lower power consumption improved noise immunity smaller installed size and more stable operation with temperature and age versus opto couplers The Si861x 2x 3x 4x 5x 6x include up to six unidirectional isolated channels permitting data transmission up to 150 Mbps The Si860x isolator series consists of single package galvanic isolation solutions for 2 SMBus and PMBus serial port applications For more information refer to the respective family data sheets summary of the benefits provided by the Silicon Laboratories Si86xx CMOS Digital Isolator family includes m Si86xx Digital Isolators 5 0 3 75 kV and 1 0 kV isolation ratings UL CSA and VDE certifications DC to 150 Mbps 2 5 to 5 5 V VDD supply range Fail safe operating mode s 40 to 125 C temperature range 10 ns max propagation delay lt 1 5 mA channel 1 Mbps lt 1 5 ns pulse width distortion Very low EMI Up to 50 V m electric field immunity
10. nsibility for any consequences resulting from the use of information included herein Additionally Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters Silicon Laboratories reserves the right to make changes without further notice Silicon Laboratories makes no warranty rep resentation or guarantee regarding the suitability of its products for any particular purpose nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation conse quential or incidental damages Silicon Laboratories products are not designed intended or authorized for use in applications intended to support or sustain life or for any other application in which the failure of the Silicon Laboratories product could create a situation where per sonal injury or death may occur Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap plication Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages 12 Rev 0 2 SIL ICON LABS
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