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Altera SoC Embedded Design Suite User Guide

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1. Trigger conditions 1 a Trigger in Pin Node Instance lt Hard Processor System HPS trigger out Pattern q High 4 gt Trigger out Pin l Instance v Hard Processor System HPS trigger in Hard Processor System HPS event gt Level Active High lt Latency delay 5 cycles Quartus SignalTap II GUI has the above depicted Trigger panel that controls cross triggering Getting Started Guides GJ Send Feedback Altera Corporation 5 44 Cross triggering Prerequisites e The Trigger In panel determines whether HPS can trigger FPGA Trigger In can be enabled and the Pattern can be selected with Don t care Low High Rising Edge for instance e The Trigger out panel determines whether FPGA can trigger HPS Trigger out can be enabled and the Level can be selected Active High and Active Low Note Changing some of the settings requires recompiling the FPGA design For this getting started scenario you will change only options that do not require recompilation The SignalTap II file that is provided with the Cyclone V GHRD has only the options that do not require compilation enabled to be edited If you recompile the design you can enable all options to be edited by selecting the Lock Mode to be Allow all changes Figure 5 48 SignalTap Lock Mode Lock mode sf Allow all changes Cross triggering Prerequisites This section pre
2. JTAG Chain Configuration JTAG ready Hardware USB Blaster l 1 1 3 3 Setup Devic 1 SOCVHPS 0x4BA00477 2 SCSEBAG oan acacia b gt Soe aes Ce eer 7 In SignalTap II under SOF Manager click the Browse button browse to the file lt SoC EDS Installation directory gt examples hardware cv_soc_devkit_ghrd output_files soc_system sof and click Open Figure 5 51 Browse Program Files JTAG Chain Configuration JTAG ready Hardware USB Blasterll 1 1 3 3 Setup Device 2 5CSEBA6 ES 5CSEM Scan Chain pans rei pae Z2 SOF Manager S LU arouse Program Fies i 8 In Signal Tap II under SOF Manager click the Program button to program the FPGA Figure 5 52 Program FPGA JTAG Chain Configuration JTAG ready x Hardware USB Blasterll 1 1 3 3 Setup Device 2 5CSEBA6 ES 5CSEM Scan Chain gt gt SOF Manager EN i Filmetene stem sof Program Device 9 After the FPGA is programmed the SignalTap II will be ready to acquire Getting Started Guides Altera Corporation CJ Send Feedback 5 46 FPGA Triggering HPS Example Figure 5 53 Signal Tap Ready to Acquire Quartus II 64 Bit SignalTap II Logic Analyzer cti_tapping stp File Edit View Processing Tools Help 3 H amp Instance Manager 9 E 2 Ready to acquire x JTAG Chain Co
3. Copy projects into workspace Working sets T Add project to working sets 5 Click Finish The project will be imported The project files will be displayed in the Project Explorer panel The following files are part of the project Getting Started Guides Altera Corporation CJ Send Feedback 5 14 Compiling the Sample Application Table 5 2 Project Files EEE EEE e hwlib c Sample application source code Altera SoCFPGA HardwareLib FPGA CV GNU Launcher file used to run debug the sample applica Debug launch tion from within Eclipse altera socfpga hosted ld Linker script debug hosted ds Debugger script use to load the sample application Makefile Makefile used to compile the sample application Compiling the Sample Application 1 To compile the application select the project in Project Explorer 2 Select Project gt Build Project 3 The project compiles and the Project Explorer shows the newly created hwlib axfexecutable file as shown in the above figure The Console dialog box shows the commands that were executed Figure 5 12 Project Compiled File Edit Source Refactor Navigate Search Project Run Window Help rie B S E G s Gia a ty v F Y Q Y g Q v g 7 v v Yv v RS Projec S2 a Strea Sr im o Out 8 Ma B amp ad An outline is not available ES Altera SoCFPGA HelloWorld Ba in Includes A hello c T s E Propert hello o arm le roperties B
4. The master boot record located at the first 512 bytes of the device memory contains partition address and size information The preloader and U boot images are stored in partitions of type 0xA2 Other images are stored in partition types according to the target file system format You can use the fdisk tool to set up and manage the master boot record When the fdisk tool partitions an SD MMC device the tool creates the master boot record at the first sector with partition address and size information for each partition on the SD MMC Padding The preloader image tool inserts a CRC checksum in the unused region of the image Padding fills the remaining unused regions The contents of the padded and unused regions of the image are undefined Related Information Booting and Configuration For more information refer to the Booting and Configuration appendix in volume 3 of the Arria V Device Handbook or the Cyclone V Device Handbook mkimage Tool The preloader verifies the mk image header appended to the boot image before the preloader loads the next stage boot image in the HPS booting process The next stage boot image is a U boot image an RTOS or a bare metal application HPS Preloader User Guide Altera Corporation CJ Send Feedback 8 18 mkimage Tool Options 2013 05 03 The preloader source files include the U boot utility mkimage tool The mkimage tool appends the mk image header to the next image Figure 8 6 mk image H
5. at runtime with debugging information stdout output from printf is directed to the UART You can view this debugging information by connecting a terminal program to the UART specified peripheral Altera Corporation HPS Preloader User Guide J Send Feedback 2013 05 03 BSP Settings 8 11 spl reset_ Boolean Refer to Table This setting forces the device to assert lt peripheral_name gt 8 7 spl reset_assert remain under reset state You can table for peripheral include multiple instances of names and values spl reset_ assert lt peripheral_ name gt to hold multiple peripherals in reset You must ensure the debugger does not read registers from these components spl warm_reset_ Boolean True This setting enables the reset handshake FPGA manager to perform handshake with the FPGA before asserting a warm reset spl warm_reset_ Boolean True This setting enables the reset handshake ETR manager to request that the Embedded Trace Router ETR stalls the Advanced eXtensible Interface AXI master and waits for the ETR to finish any outstanding AXI transactions before asserting a warm reset of the L3 interconnect or a debug reset of the ETR spl warm_reset_ Boolean True This setting enables the reset handshake SDRAM manager to request that the SDRAM controller puts the SDRAM device into self refresh mode before asserting warm reset spl boot FPGA_MAX_SIZE_ Hexadecimal 0x10000 This setting
6. tailor accordingly to meet their target system requirements The capabilities of the HWLIB are expected to evolve and expand over time particularly as common use case patterns become apparent from practical application in actual systems 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JN DTE RYA ISO 9001 2008 Registered 101 Innovation Drive San Jose CA 95134 9 2 Feature Description In general the HWLIB assumes to be part of the system software that is executing on the Hard Processor
7. Altera Corporation GJ Send Feedback 6 8 Debug Configuration Options Figure 6 7 Debug Configurations Connection Create manage and run configurations Configuration for connection type Bare Metal Debug is not valid Connection cannot be empty Ceaxler type filter text 4 fe C C Application C C Attach to Application fe C C Postmortem Debugg E C C Remote Application J DS 5 Debugger 2 SampleConfiguration Iron Python Run Iron Python unittest Java Applet G Java Application Ju JUnit g Jython run d Jython unittest Launch Group dj PyDev Django PyDev Google App Run 2 Python Run g Python unittest ral Remote Java Application mw Filter matched 19 of 19 items Name SampleConfiguration gt Connection Files 4 Debugger RTOS Awareness 6 Arguments P Environment 1 Select target Select the manufacturer board project type and debug operation to use Currently selected Altera Cyclon 4 Altera Arria V SoC 4 Cyclone V SoC Linux Application Debug Linux Kernel and or Device Driver Debug DTSL Options Configure trace or other target options Using default configuration options DS 5 Debugger will connect to a DSTREAM or RVI to debug a bare metal application Connections Bare Metal Debug Connection The following Target Types are available Bare Metal Debug select this to debug bare metal applications Linux Application Debug sele
8. Altera SoCFPGA HelloWorlc CDT Build Console Altera SoCFPGA HelloWorld Baremetal GNU altera socfpga hosted Id Y Lae A Ex mE m q ge C NEII 0 NE EIrro o hello axf arm none eabi a Taltera socfpga hosted ld hello o o hello axf map hello axf hello axf cbjdump arm none eabi objdump d hello axf gt hello axf objdump Makefile arm none eabi nm hello axf gt hello axf map semihost_setup ds A Build Finished Altera Corporation Getting Started Guides CJ Send Feedback Running the Sample Application Running the Sample Application 5 15 The bare metal sample application comes with a pre configured Eclipse Workspace Launcher that allows you to load run and debug the sample application The Workspace Launcher uses the Altera USB Blaster II board connection It uses a debugger script to load and run the Preloader to configure the HPS component and then loads the sample application To run the sample application perform the following steps 1 In the Eclipse IDE click Run gt Debug Configurations to open the Debug Configurations dialog box 2 In the Connection tab in the Debug Configurations dialog box ensure the selected target is Altera gt Cyclone V gt Bare Metal Debug gt Debug Cortex A9_0 via Altera USB Blaster 3 Under Connections tab click Browse to select the USB Blaster connection Figure 5 13 Debug Configurations 4 In the Select Debug H
9. Configurations DTSL Options Edit Create manage and run configurations Create edit or choose a configuration to launch a DS 5 debugging session re BS z z 5 B x B Name SampleConfiguration gt type filter text lt c Connection Files 2 Debugger RTOS Awareness 6 Arguments 2 Environment 1 fe C C Application fe C C Attach to Application fe C C Postmortem Debugge fe C C Remote Application J DS 5 Debugger 2 SampleConfiguration Cyclone V SoC Iron Python Run Bare Metal Debug Iron Python unittest Debug Cortex A9_0 via Altera USB Blaster Java Applet Debug Cortex A9 0 via DSTREAM RVI Select target Select the manufacturer board project type and debug operation to use Currently selected Altera Cyclone E Java Application Ju JUnit i Configure trace or other target options Using default configuration options g Jython run a Jython unittest Launch Group dij PyDev Django 23 PyDev Google App Run Bare Metal Debug Connection USB Blasterll on localhost USB 1 USB Blasterll USB 1 Python Run g Python unittest DS 5 Debugger will connect to an Altera USB Blaster to debug a bare metal application Connections 4 w Filter matched 19 of 19 items Cross Trigger Settings The Cross Trigger tab allows the configuration of the cross triggering option of the SoC FPGA The following options are available Enable FPGA gt HPS Cross Trigger for enabling triggers co
10. Ctri W Ctri Shift W Ctrl S Ctrl Shift S Ctrl P Alt Enter 3 C Project 3 C Project Project Convert to a C C Project Adds C C Nature Source Folder Folder amp Source File Header File File from Template Class Ctrl N F Tasks EJ Console E Properties Resource 3 Type the folder name in the Existing Code Location edit box and then click Finish Altera Corporation ARM DS 5 Altera Edition J Send Feedback Project Management 6 3 Figure 6 2 Import Existing Code window Import Existing Code Create a new Makefile project from existing code in that same directory Project Name sample_project Existing Code Location c sample_project Languages VIC C Toolchain for Indexer Settings ARM Compiler ARM Linux GCC GNUARM 4 Create a Makefile in that folder and define the rules required for compiling the code Make sure it has the all and the clean targets 5 Eclipse now offers the possibility of invoking the build process from the IDE ARM DS 5 Altera Edition Altera Corporation CJ Send Feedback 6 4 Debugging Figure 6 3 Eclipse IDE build process invoked File Edit Source Refactor Navigate Search Run Window Help ri in wi 6 Open Project e g j X Close Project M Streamlin b Build All DE Out 2 Ma _ B amp v Build Configurations 4 S Altera SoCFPGA Hardwa
11. Developer y y y y y ARM DS 5 Debugging ARM DS 5 V V V Tracing ARM DS 5 y y y Cross Triggering Hardware y y y Libraries Preloader y y y y Generator Flash y y y y Programmer Bare Metal y y y y Compiler Linux vV V Compiler Yocto Plugin V V Device Tree Generator This table lists typical tool usage but your actual requirements depend on your specific project and organization Hardware Engineer As a hardware engineer you typically design the FPGA hardware in Qsys You can use the ARM DS 5 Altera Edition s debugger to connect to the ARM cores and test the hardware A convenient feature of the DS 5 debugger is the soft IP register visibility using Cortex Microcontroller Software Interface Standard CMSIS Introduction to SoC Embedded Design Suite Altera Corporation GJ Send Feedback 1 4 Hardware Software Development Roles System View Description svd files With this feature the hardware you can easily read and modify the soft IP registers from the ARM side As a hardware engineer you might generate the Preloader for your hardware configuration The Preloader is a piece of software that configures the HPS component according to the hardware design As a hardware engineer you might also perform the board bring up You can use the ARM DS 5 debugger to verify that they can connect to the ARM and the board is working correctly These tasks require JT
12. NErIIU U oe arm none eabi g Taltera socfpga hosted 1ld hello o o hello axf map hello axf hello axf objdum arm none eabi objdump d hello axf gt hello axf objdump J p Makefile arm none eabi nm hello axf gt hello axf map semihost_setup ds B Ti Build Finished 3 The project compiles and the Project Explorer shows the newly created hwlib axfexecutable file as shown in the above figure The Console dialog box shows the commands that were executed Running the Sample Application Before running the sample application perform the following setup e Setup the board as described in Getting Started with Board Setup e Connect mini USB cable from DevKit board connector J37 to PC e Connect 19V power supply to the DevKit e Turn on the board using the PWR switch 1 Select Run gt Debug Configurations to access the launch configurations The sample project comes with a pre configured launcher that allows the application to be run on the board 2 In the Debug Configurations dialog box on the left panel select DS 5 Debugger gt Altera SoCFPGA HelloWorld Baremetal Debug The Target is already pre configured to be Altera gt Cyclone VSoC gt Bare Metal Debug gt Debug Cortex A9_ 0 via Altera USB Blaster 3 Click Browse to select the USB Blaster connection Altera Corporation Getting Started Guides CJ Send Feedback Running the Sample Application 5 9 Figure 5 6 Debug Configuration te x Ju
13. System HPS in privileged supervisor mode and in the secure state The anticipated HWLIB clients include e Bare Metal application developers e Custom preloader and boot loader software developers e Board support package developers e Diagnostic tool developers e Software driver developers e Debug agent developers e Board bring up engineers e Other developers requiring full access to SoC FPGA hardware capabilities Feature Description This section provides a description of the operational features and functional capabilities present in the HWLIB An overview and brief description of the HWLIB architecture is also presented The HWLIB is a software library architecturally comprised of two major functional components e SoC Abstraction Layer SoCAL e Hardware Manager HW Manager SoC Abstraction Layer SoCAL The SoC Abstraction Layer SoCAL presents the software API closest to the actual HPS hardware Its purpose is to provide a logical interface abstraction and decoupling layer to the physical devices and registers that comprise the hardware interface of the HPS The SoCAL provides the benefits of e A logical interface abstraction to the HPS physical devices and registers including the bit fields comprising them e A loosely coupled software interface to the underlying hardware that promotes software isolation from hardware changes in the system address map and device register bit field layouts Hardware Manager HW M
14. W No OS Support ala Submit e J hello c X egiin XN AM g mlel o OO 21 INCLUDING BUT NOT LIMITED TO PROCUREMENT OF SUBST 4 22 LOSS OF USE DATA OR PROFITS OR BUSINESS INTERRUPT E Appc X fi Target 9 Error gj 23 ON ANY THEORY OF LIABILITY WHETHER IN CONTRACT STR TG 24 INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY W G Ee GE 25 SOFTWARE EVEN IF ADVISED OF THE POSSIBILITY OF SUCH amp Linked LinuxAppDebug_Devkit 7 26 Preparing the debug session fa 27 28 include lt stdio h gt cd home root 29 export LD LIBRARY PATH home gt 30int main int argc char argv gdbserver 5000 home root hell 31 printf Hello SoC FPGA n Process home root hello created 32 return 0 Listening on port 5000 33 Debug session has been started co 34 E Remote debugging from host 137 57 C b Ca D inh Note At this stage all the usual debugging features of DS 5 can be used such as breakpoints view variables registers tracing and threads 9 Click the Continue green button or press F8 to run the application The hello message is printed on the Application Console Altera Corporation Getting Started Guides CJ Send Feedback Getting Started with Linux Kernel and Driver Debugging 5 31 Figure 5 33 Hello Message E AppC X E Target Error m Gl Ex BB amp Linked LinuxAppDebug_DevKit export LD LIBRARY PATH home gdbserver 5000 home root hell Process home r
15. application to the target board 5 Select the Registers view and maximize it It shows the Core Coprocessor VFP NEON and Peripheral Registers Under the Peripherals group the DS 5 displays both the HPS peripheral registers and the Soft IP registers The figure below shows some of the HPS modules with the EMAC one expanded Figure 5 18 Peripheral Registers 00 Variables e Breakpoints oo 23 Expressions fO Functions ye mk B Linked Altera SoCFPGA HardwareLib FPGA CV GNU Debug Name Value Size Access Xt a t amp Core GH amp CP15 E E VFP G NEON amp Peripherals gt acpidmap S cand D feo a GH amp canl amp clkmgr amp dap E dmanonsecure E dmasecure gt emacd emacO_gmacgrp_MAC_Configuration Ox 32 RAW H emac0_gmacgrp_MAC_Frame Filter x 008008 32 R W Peripherals Semac0 Semac0_gmacgrp_MAC_Configuration The MAC Configuration register establishes receive and transmit operating modes amp Hl 6 Put a breakpoint in the source code file named hwlib c at the line where the soft IP GPIO module data register is written to turn LEDs ON or OFF The breakpoint is added by simply double clicking to the left of the line number in the dialog box Getting Started Guides Altera Corporation CJ Send Feedback 5 20 Getting Started with Peripheral Register Visibility Figure 5 19 Breakpoint Added DS 5 Debug File Edit Source Refactor Navigate Search
16. can be accessed online on the documentation page of the ARM website www arm com and from Eclipse by navigating to Help gt Help Contents gt ARM DS 5 Documentation Starting Eclipse Eclipse is the IDE used by ARM DS 5 Altera Edition and it can be started from the Embedded Command Shell or from the windows file menu selection The advantage of starting Eclipse from the Embedded Command Shell is that all the utilities are added to the search path and they can be used directly from the makefiles without the full path 1 Atthe command line type eclipse amp to start Eclipse IDE used by ARM DS 5 Altera Edition See Embedded Command Shell section for more details about the shell 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service de
17. folder The rest of the Preloader settings are populated automatically Figure 5 2 Populated Options in the New BSP window Hardware Preloader settings directory ardware cv_soc_devkit_ghrd hps_isw_handoff soc_system_hps_0 os Software Preloader V Use default locations BSP target directory bedded examples hardware cv_soc_devkit_ghrd software spl_bsp BSP Settings File name ples hardware cv_soc_devkit_ghrd software spl_bsp settings bsp V Enable Settings File relative paths E Enable Additional Td script Additional Td script 6 Click OK to close the New BSP dialog box This will populate the BSP Editor dialog box with the default settings Altera Corporation Getting Started Guides J Send Feedback Getting Started with Preloader 5 5 Figure 5 3 Default Options in the BSP Editor window Operating system BSP target directory Settings a spl F BOOT_FROM_QSPI PRELOADER_TGZ CROSS_COMPILE BOOT FROM_RAM amp boot V BOOT_FROM_SDMMC BOOT_FROM_QSPI BOOT FROM SDMMC QSPI_NEXT_BOOT_IMAGE BOOT_FROM_RAM 0x60000 QSPI_NEXT_BOOT_IMAGE SDMMC_NEXT_BOOT_IMAG SDMMC_NEXT_BOOT_IMAGE Advanced 0x40000 m Information Problems Processing Finished initializing BSP components Total time taken 2 seconds Searching for BSP components with category os_software_element Initializing BSP components Finished initializing BSP c
18. force Flag to force decoding even if the input file is an unpadded image h help Display this help message and exit o output lt outfile gt Output file relative and absolute path supported v version lt num gt Header version to be created default to 0 Output Image Layout Base Address You should place the preloader image at 0x0 for NAND and QSPI flash The SD MMC flash has a MBR that points to a specific offset at the start of the partition The partition is of type 0xA2 a custom raw partition type without any file system The preloader image tool always places the output image at the start of the output binary file regardless of the target flash memory type The flash programming tool is responsible for placing the image at the desired location on the flash memory device Related Information Booting and Configuration For more information refer to the Booting and Configuration appendix in volume 3 of the Arria V Device Handbook or the Cyclone V Device Handbook Size A single preloader has a 60 KB image size You can store up to four preloader images in flash If the boot ROM does not find a valid preloader image at the first location it attempts to read an image from the next location 64 KB above the first To take advantage of this feature program four preloader images in flash at consecutive 64 KB intervals Altera Corporation HPS Preloader User Guide CJ Send Feedback 2013 05 03 Address Ali
19. h gt Writable Smart Insert 7 Click Continue green button or press F8 to run the application It displays the hello message in the Application Console Altera Corporation Getting Started Guides CJ Send Feedback Getting Started with the Hardware Library 5 11 Figure 5 9 Debugging Session window EDs Debug _ File Edit Source Refactor Navigate Search Project Run Window Help cy el a Be ag E aE MAIEN k Debug 83 RS Project A Remote hA Streaml 0 cx lt ojiva X 4 m K Gl Ex BE Sy yY RY 3 S v x aA PR ltera SoCFPGA HelloWorld Barer 3 SoCFPGA HelloWorld E WARNING TADIOO T OMRON 7 ermmm nn a aar sa om 7 r m Name R Altera Disconnect from Target pacu Debanappicii Execution stopped at ae fora ft n it In _exit no debug inf 5 amp Locals amp No Stack S xFFFF2F64 SVC amp File Statics curren Application exited witl amp amp Globals am r R Altera SoCFPGA HelloWorld Ba application exit code 0 No OS Support Command am woPthuM Sm Eelgeol eT x 9 App Cons 52 _ i Target Co O Error Log 1 int main int argc char argv Be BE Y printf Hello Tim n return B Linked Altera SoCFPGA HelloWorld Baremetal Debug Hello Tim p Writable Smart Insert 8 Click Disconnect from Target button to close the debugging session Getting Started with
20. of license to enter In this example select the radio button Enter a serial number or activation code to obtain a license to enter the choices listed below When done click Enter a ARM License Number for Subscription Edition b ARM License Activation Code for Web Edition and 30 Day Evaluation Figure 4 4 Add License Obtain a new license Select the type of license to create for this computer Enter a serial number or activation code to obtain a license Serial number LM01459 gt GD Use an existing license file or license server address Generate 30 day evaluation license Manually obtain a license via www arm com website 5 Click Next 6 In the Add License Choose Host ID dialog box select the Host ID Network Adapter MAC address to tie the license to If there are more than one option select the one you desire to lock the license to Click Next Figure 4 5 Add License Choose host ID Choose a host ID that the license will be locked to Choose a host ID that the license will be locked to It is recommended that you choose a host ID that represents a physical device on your computer If you choose a virtual device then your license will not work if the ID of the device changes in the future A Altera Corporation Licensing GJ Send Feedback Activating the License 4 5 7 In the Add License Developer account details dialog box enter an ARM developer Silve
21. of the desired core tracing options Altera Corporation ARM DS 5 Altera Edition J Send Feedback DTSL Options 6 17 Figure 6 18 DTSL Configuration Editor Cortex A9 Debug and Trace Services Layer DTSL Configuration Add edit or choose a DTSL configuration for file dts _config_script py class DSTREAM_DtsIScript B Name of configuration default Cross Trigger Trace Buffer Cortex A9 gt STM ETR ETF V Enable Cortex A9 core trace Enable Cortex A9 0 trace V Enable Cortex A9 1 trace PTM Triggers halt execution Enable PTM Timestamps Enable PTM Context IDs Context ID Size 32 bit C Cycle Accurate _ Trace capture range 0x0 OxFFFFFFFF Revert Apply The following Core Tracing Options are available e Enable Cortex A9 0 core trace check to enable tracing for core 0 e Enable Cortex A9 1 core trace check to enable tracing for core 1 e PTM Triggers halt execution check to cause the execution to halt when tracing e Enable PTM Timestamps check to enable time stamping Enable PMT Context IDs check to enable the context IDs to be traced e Context ID Size select 8 16 or 32bit context IDs Used only if Context IDs are enabled e Cycle Accurate check to create cycle accurate tracing e Trace capture range check to enable tracing only a certain address interval e Start Address End Address define the tracing address interval Used only if th
22. or press F9 The Debugger shows the captured trace information Getting Started Guides Altera Corporation CJ Send Feedback 5 40 Getting Started with Tracing Figure 5 44 DS 5 Debug 18 Disassembly Memory Modules Events Outline Trace 33 gt Ex O 4 M zeski amp Linked DebugLinux_DevKit swapper 0 Trace Properties Ranges update_sd Ib stats _ do div64 load_balance __aeabi_uidiv hrtimer_interrupt find_busiest_group __memzero timerqueue_add rcu_check_callbacks E E O B Q Q ktime_get Index Address Cycles Detail S 0x8000E8B0 MOV riz ir S 0x8000E8B4 LDM sp lr S 0x8000E8B8 MOV pc r12 del timer sync 0x00000014 S 0x80032668 MOV r3 sp S 0x8003266C BIC r2 r3 0x1fcO S 0x80032670 MOV r3 0 S 0x80032674 BIC r2 r2 0x3f S 0x80032678 MOVT r3 0x3ff C L J The tracing window shows e core instructions as they were executed e percentage occupied by each function e histogram with function allocation Related Information e ARM DS 5 Altera Edition on page 6 1 For more information refer to the ARM DS 5 Altera Edition section e Cyclone V Coresight Debug and Trace For more information about Tracing refer to the Coresight Debug and Trace section in volume 3 of the Cycone V Device Handbook e ARM DS 5 Documentation The ARM DS 5 Altera Edition reference material can be accessed online on the documentation page of
23. source code will be available in the folder lt SoC EDS installation directory gt embeddedsw socfpga sources linux socfpga Note if your computer connects to the Internet using a proxy you will need to use this command to tell the Git utility about the proxy git config global http proxy lt proxy_name gt Related Information Getting Started with Running Linux on page 5 2 For more information refer to the Getting Started with Running Linux section in this document Rocket Boards For more information about Linux and the latest source releases refer to the Rocketboards website Starting Eclipse via the Embedded Command Shell 1 Start an Embedded Command Shell by running lt SoC EDS installation directory gt embedded_command_ shell sh Start Eclipse by running the eclipse command from the Embedded Command Shell The Eclipse tool part of the ARM DS 5 AE prompts for the workspace folder to be used Accept the suggested folder and click OK The ARM DS 5 AE Welcome screen appears It can be used to access documentation tutorials and videos Debugging the Kernel This section presents how to create a Debug Configuration that is then used to debug the Linux kernel 1 2 3 Select Run gt Debug Configurations to open the Debug Configurations dialog box In the Debug Configurations dialog box right click DS 5 Debugger on the left panel and select New In the Debug Configurations dialog box perform the fo
24. stopped in the idle instruction Altera Corporation Getting Started Guides CJ Send Feedback Figure 5 36 Linux Kernel Stopped Debugging the Kernel 5 35 DS 5 Debug home radu altera 13 1 embedded embeddedsw socfpga sources linux socfpga o x File Edit Navigate Search Project Run Window Help a m ri D 4 s me a BP a R As o i Comm z E Histor Scripts o OB m R E OF 3 i 7I G Ex BB Sy y a B va a a amp Linked DebugLinux_Devkit Linked DebugLinux_DevKit add symbol file rats Name Vali j niente coll wx kernel_sunnart faya c E Locals REEE DebugLinux_ connected as File Statics current _ Unix Kemel Enabled Commana ame S proc v7 S amp a Di 3 AMe Mo H Ev ou 71 ENTRY cpu_v7_do idle a a Linked DebugLinux_Devkit lA lt Next instru 100 Address Opcode TAER gt ELAGFOOE cpu v7 eae O mmm E App Co W Target 5 Error L G Ex 6B amp Linked DebugLinux_DevKit Waiting Tor a pug server To Start acc 72 dsb WFI may enter a low po 73 wfi 74 mov pe Ur 75 ENDPROC cpu_v7_do idle 76 77 ENTRY cpu_v7_dcache clean area 78 ifndef TLB CAN READ FROM L1 CACHE 79 dcache_line_size r2 r3 801 mcr p15 0 r0 c7 c10 1 clean D en 8 add r0 r0 r2 82 subs Fi r1 r2 83 bhi 1b 84 dsb 85 endif 86 mov pc lr C
25. subscribe CG3 Send Feedback The Altera SoC Embedded Design Suite provides the tools needed to develop embedded software for Altera s SoC devices The Altera system on a chip SoC Embedded Design Suite EDS is a comprehensive tool suite for embedded software development on Altera SoC devices The Altera SoC EDS contains development tools utility programs run time software and application examples that enable firmware and application software development on the Altera SoC hardware platform Overview The Altera SoC EDS enables you to perform all required software development tasks targeting the Altera SoCs including Board bring up e Device driver development e Operating system OS porting e Bare metal application development and debugging e OS and Linux based application development and debugging e Debug systems running symmetric multiprocessing SMP e Debug software targeting soft IP residing on the FPGA portion of the device The major components of the SoC EDS include e ARM Development Studio 5 DS 5 Altera Edition Toolkit e Compiler tool chains e Bare metal GNU Compiler Collection GCC tool chain from Mentor Graphics e Linux GCC compiler tool chain from Linaro e Pre built Linux package including e Linux kernel executable e Linux kernel U boot image e Device tree blob e Secure Digital SD card image e Script to download Linux source code from the Git tree on the Rocketboards website www roc
26. the Hardware Library The SoC Hardware Libraries example program is part of the Altera SoC Embedded Design Suite EDS You can run the sample program on a Cyclone V SoC development kit board The example program demonstrates using the Hardware Library to programmatically configure the FPGA and exercise soft IP control from the hard processor system HPS HWLIB Sample Application Overview The Bare Metal sample application uses the HWLIB API to e Programmatically configure the FPGA from the HPS e Initialize and bring up the Advanced eXtensible Interface AXI bridge interfaces between the HPS and the FPGA e Exercise the FPGA soft IP parallel I O PIO core from the HPS to toggle the development board LEDs The sample application uses the development kit Golden System Reference Design GSRD FPGA configu ration The sample application uses the following files e FPGA configuration SRAM Object File sof e Preloader executable file for proper initialization of the GSRD HPS component Getting Started Guides Altera Corporation CJ Send Feedback 5 12 Starting the Eclipse IDE The sample application is built with a makefile that performs the following steps 1 Copies Hardware Libraries source code from installation folder to the current project folder 2 Compiles the example C source code files with the GNU Compiler Collection GCC tool chain from Mentor Graphics 3 Copies the sof file from the GSRD folder 4 Converts
27. the shell commands like arm none eabi gcc can be invoked directly When the Eclipse environment is started from the Embedded Command Shell it inherits the environment settings and it can call these compilation tools directly Alternatively the full path to the compilation tools can be used lt SoC EDS installation directory gt host_tools mentor gnu arm baremetal bin The bare metal compiler comes with full documentation located in the following folder lt SoC EDS installation directory gt host_tools mentor gnu arm baremetal share doc arm arm none eabi The documentation is offered in four different formats to accommodate various user preferences e Html files e Info files e Man pages e PDF files Among the provided documents are e Compiler manual e Assembler manual e Linker manual e Binutils manual GDB manual e Getting Started Guide e Libraries Manual Related Information Mentor Graphics For more information on the Sourcery CodeBench Lite Edition and for downloading the latest version of the tools if necessary refer to the Mentor Graphics website www mentor com 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their resp
28. to run and debug the application 1 Select Run gt Debug Configurations to open the Debug Configurations dialog box 2 Right click the DS 5 Debugger and click New to create a new debug configuration 3 Name the newly created debugger configuration LinuxAppDebug_DevKit by editing its name in the Connection tab 4 In the Connection tab select Altera Corporation Getting Started Guides J Send Feedback Running Sample Application 5 29 a For the Free Web Edition license select Generic gt gdb server gt Linux Application Debug gt Download and Debug Application b For the Subscription Edition or 30 day Evaluation Edition select Altera gt Cyclone 5 SoC gt Linux Application Debug gt Download and Debug Application 5 In the Connection tab select the newly created RSE connection and keep the default values Figure 5 30 Connection Settings Select target Select the manufacturer board project type and debug operation to use Curre v Altera b Aria V SoC v Cyclone V SoC gt Bare Metal Debug v Linux Application Debug Connect to already running gdbserver Download and debug application Connections A RSE connection 137 57 160 214 S Address Use RSE Host gdbserver TCP Port 5000 Use Extended Mode 6 Go to Files tab and set the Target Configuration parameters a Select the Application on host to download to be the hello executable file Use the Workspace browse
29. 4 n r Filter matched 19 of 19 items Apply Arguments The Arguments tab allows you to enter program arguments as text Figure 6 11 Debug Configurations Arguments Create manage and run configurations Connection Configuration for connection type Bare Metal Debug is not valid Connection cannot be empty Sax aR Name SampleConfiguration type filter text lion Files Debugger f RTOS Awareness Arguments gt MG Environment 2 E C C Application Program Arguments E C C Attach to Appli _ fe C C Postmortem Di fe C C Remote Applic a 3 DS 5 Debugger 2 SampleConfigurati Iron Python Run 2 Iron Python unittest 4 m r Apply Revert Filter matched 19 of 19 items Debug Environment The Environment tab allows you to enter environment variables for the program to be executed Altera Corporation ARM DS 5 Altera Edition I Send Feedback Debug Configuration Options 6 13 Figure 6 12 Debug Configurations Environment Create manage and run configurations Connection Configuration for connection type Bare Metal Debug is not valid Connection cannot be empty Bi B x E Fe Bf Name SampleConfiguration gt type filter text Files Debugger 3 RTOS Awareness t Arguments P Environment 2 E C C Application Target environment variables to set E C C Attach to Appli _ E C C Postmort
30. AG debugging which is enabled only in the Subscription Edition For more information see the Licensing section Bare Metal and RTOS Developer As either a bare metal or a RTOS developer you need JTAG debugging and low level visibility into the system Use the bare metal compiler to compile your code and the SoC Hardware Library to control the hardware in a convenient and consistent way Use the Flash Programmer to program the flash memory on the target board These tasks require JTAG debugging which is enabled only in the Subscription Edition For more information see the Licensing section Linux Kernel and Driver Developer As a Linux kernel or driver developer you use the same tools as the RTOS developers because you need low level access and visibility into the system However you use the Linux compiler instead of the bare metal compiler Youccan use the Yocto plugin to manage the project and the device tree generator to generate device trees These tasks require JTAG debugging which is enabled only in the Subscription Edition For more information see the Licensing section Linux Application Developer As a Linux application developer you write code that targets the Linux OS running on the board Because the OS provides drivers for all the hardware you do not need low level visibility over JTAG DS 5 offers a very detailed view of the OS showing informaton such as which threads are running and which drivers are loaded
31. Altera SoC Embedded Design Suite User Guide amp Subscribe ae 101 Innovation Drive N DPE 2Ya 2013 11 San Jose CA 95134 CJ Send Feedback a www altera com TOC 2 Altera SoC Embedded Design Suite User Guide Contents Introduction to SoC Embedded Design Suiite ccc sssssssssesesseescseessseeeees 1 1 OVVIE Wasin i E R R A bin ain RR 1 1 Device Pree Biman yeissesies civessiasavas ives sossvatiesssisocessesossdvedacus ceavbetodaciosiiandbedacueiscanapasvecvtstanchesveaneseontess 1 2 Hardware Software Development Roles ssssssssceseeeseeseneeessesessesecucsecucneeseseescseseseeseseeneaceneneessseeeeees 1 3 Hardware Software Development PLOW scsccs ccssscasercssesisnasscaussesasscosscessessescosssenttastzesassadasinesaesemdereusniess 1 5 Installing the Altera SoC Embedded Design Suite cssssssssseseseeeesseeeeees 2 1 Vins tall ete Foldet eeraa T AEE EE E i 2 1 Tastalling the SOC ED Sierrei Taa ia i AIARRA R E E EEA NE A 2 1 Installing the ARM DS 5 Altera Edition TOOK ius cocsssoisonsicssicniensnsnssntenshscnshd seahnvasdussinacnsoasassanasnsasopians 2 2 Installing USB Serial Driv fSsnsinsinnniriorirniiianine n aaa aa 2 2 Installing Altera USB Blaster Ii vers sessies sieriii rairs arsaa ceaphssGssnnsccaaiinucsiesseatisiacsivudasqacnidaduaanleandts 2 2 Bare Met l Coma pil OF oseccssusaosvsseveunses csantsutsnesensesyansecnenitantexccavavnstesosencavanoncetondens 3 1 TAC OTISING vs crscusecceebsececctscers A
32. BSP setting lt name gt get all No This option shows all the BSP settings values When using get a11 you should also use show names show names No This option only takes effect when used together with get lt name gt or get all When used with one of these options names and values of the BSP settings are shown side by side bsp generate files The bsp generate files tool generates the files and settings stored in BSP settings file as shown in the following examples Example 8 5 Generating Files After BSP Creation The following command creates a settings file based on the handoff folder then generates the Preloader source files based on those settings bsp create settings type spl bsp dir settings settings bsp preloader settings dir nps_isw_handoff lt hps_entity_name gt bsp generate files settings settings bsp bsp dir Example 8 6 Generating Files After BSP Updates bsp update settings settings settings bsp set spl debug SEMIHOSTING 1 bsp generate files settings settings bsp bsp dir Use the bsp generate files tool when BSP files need to be regenerated under one of the following conditions e bsp create settings creates the PSP but the bsp dir parameter was not specified so PSP files were not generated e bsp update settings updates the PSP but the bsp dir parameter was not specified so the files were not updated e You want to
33. C EDS section Installing Altera USB Blaster Drivers The SoC EDS installation includes Quartus II Programmer and Signal Tap II applications These applications connect to the board through an USB cable Linux machines can access the USB connection directly but dedicated drivers are required on a Windows host machine Altera Corporation Installing the Altera Soc Embedded Design Suite CJ Send Feedback Installing Altera USB Blaster Drivers 2 3 On Windows the drivers are in the lt Altera installation directory gt qprogrammer drivers directory Instruct Windows to install the drivers from that folder when the new hardware is detected Installing the Altera SoC Embedded Design Suite Altera Corporation CJ Send Feedback Bare Metal Compiler S subscribe J Send Feedback The bare metal compiler that is shipped with SoC EDS is the Mentor Sourcery CodeBench Lite Edition version 4 6 3 The compiler is a GCC based arm none eabi port That is it targets the ARM processor it assumes bare metal operation and it uses the standard ARM EABI conventions The bare metal compiler is installed as part of the SoCEDS installation in the following folder lt SoC EDS installation directory gt host_tools mentor gnu arm baremetal The Embedded Command Shell opened by running the script from the SoC EDS installation folder sets the correct environment PATH variables for the bare metal compilation tools to be invoked That is after starting
34. DS 5 Altera Edition section e ARM DS 5 Documentation The ARM DS 5 Altera Edition reference material can be accessed online on the documentation page of the ARM website www arm com and from Eclipse by navigating to Help gt Help Contents gt ARM DS 5 Documentation e Rocket Boards For more information about Linux refer to the Rocketboards website Getting Started Guides Altera Corporation CJ Send Feedback 5 32 Prerequisites Prerequisites 1 2 Make sure the desired Linux kernel version is already running on the board See the Getting Started with Running Linux section for instructions on how to rn the provided Linux binaries on the board Make sure the Linux kernel executable file is accessible on the host computer The kernel executable for the pre built Linux image is located at lt SoC EDS installation directory gt embeddedsw socfpga prebuilt_ images vmlinux Make sure the source code corresponding to the kernel running on the board are accessible on the host computer The sources for the pre built Linux image can be obtained by a Start Embedded Command Shell by running lt SoC EDS installation directory gt embedded_command_ shell sh b Run the following command cd lt SoC EDS installation directory gt embeddedsw socfpga sources c Run the following command git_clone sh The above commands will fetch the Linux kernel source code from the Git server on the Rocketboards website rocketboards org The
35. E of the subsequent boot image in QSPI Altera Corporation HPS Preloader User Guide CJ Send Feedback 2013 05 03 BSP Settings 8 9 spl boot SDMMC_NEXT_ BOOT_IMAGE Hexadecimal 0x40000 This setting specifies the location of the subsequent boot image in SD MMC spl boot WATCHDOG_ENABLE Boolean True This setting enables the watchdog during the preloader execution phase The watchdog remains enabled after the preloader exits spl boot CHECKSUM_NEXT_ IMAGE spl boot EXE_ON_FPGA Boolean Boolean True False This setting enables the preloader to validate the checksum in the subsequent boot image s header information This setting executes the preloader on the FPGA Select spl boot EXE_ON_FPGA when the preloader is configured to boot from the FPGA spl boot STATE_REG_ ENABLE Boolean True This setting enables writing the magic value to the INITSWSTATE register in the system manager when the preloader exists this indicates to the boot ROM that the preloader has run successfully spl boot BOOTROM_ HANDSHAKE_CFGIO Boolean True This setting enables handshake with boot ROM when configuring the IOCSR and pin multiplexing If spl boot BOOTROM_ HANDSHAKE_CFGIO is enabled and warm reset occurs when the preloader is configuring IOCSR and pin multiplexing the boot ROM will reconfigure IOCSR and pin multiplexing again This option is enabled by d
36. Edition Altera Corporation Q Send Feedback Embedded Command Shell S Subscribe C3 Send Feedback The Embedded Command Shell enables the user to invoke the SoC EDS tools without qualifying them with the full path That is commands like eclipse or bsp editor or arm none eabi gcc can be executed directly On Windows the Embedded Command Shell is started by running lt SoC EDS installation directory gt Embedded_Command_Shell bat On Linux the Embedded Command Shell is started from the Start menu or by running lt SoC EDS installation directory gt embedded_command_shell sh 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are ad
37. FPGA manager driver 5 alt_fpga_state_get Query the FPGA state 6 E E alt_fpga_control_enable Enable controlling the FPGA 7 alt_fpga_cfg_mode_get Query the configuration mode 8 alt_fpga_configure_ Configure the FPGA using the DMA dma 9 alt_bridge_init Initialize bridges socfpga_bridge_setup 10 alt_addr_space_remap Remap address space 11 socfpga_bridge_io N A Application accesses Soft IP directly 12 socfpga_bridge_ alt_bridge_uninit Deinitialize bridges cleanup Getting Started Guides Altera Corporation CJ Send Feedback 5 1 Getting Started with Peripheral Register Visibility Sequence Sample Application Used Hardware Libraries Description Function APIs alt_fpga_control_ Disable control of FPGA socfpga_fpga_cleanup disable 14 alt_fpga_uninit Close the FPGA driver 15 alt_dma_channel_free Deallocate the DMA channel socfpga_dma_cleanup 16 alt_dma_uninit Close the DMA driver Getting Started with Peripheral Register Visibility The ARM DS 5 Altera Edition allows you to specify the peripheral IP register descriptions using svd files The svd files are resulted from the hardware project compilation using ACDS The svd files contain the description of both HPS peripheral registers such as UART EMAC and timers and the Soft IP peripheral registers residing on FPGA side This section presents the necessary steps in order to view the HPS registers and the Soft IP registers using the Getting Started with Hardware
38. JUnit type filter text fe C C Application fe C C Attach to Applic fe C C Postmortem Det fe C C Remote Applicat DS 5 Debugger Iron Python Run Arria V SoC Iron Python unittest Cyclone V SoC E Java Applet Bare Metal Debug ive Apion 4 m Filter matched 19 of 19 items Create manage and run configurations Configuration for connection type Bare Metal Debug is not valid Connection cannot be empty 4 ai Name Altera SoCFPGA HelloWorld Baremetal Debug gt Be Connection gt I Files Zh Debugger f RTOS Awareness Arguments 2 Select target Select the manufacturer board project type and debug operation to use Currently selected Altera Cyc Debug Cortex A9_0 via DSTREAM RVI a Jython run Jython unittest DTSL Options Configure trace or other target options Using default configuration options Launch Group dj PyDev Django DS 5 Debugger will connect to an Altera USB Blaster to debug a bare metal application 43 PyDev Google App Run 2 Python Run g Python unittest ral Remote Java Applicatior Connections Bare Metal Debug Connection r Apply Debug 4 In the Select Debug Hardware dialog box select the desired USB Blaster and click OK Figure 5 7 Select Debug Hardware Getting Started Guides CJ Send Feedback I Select Debug He Details USB Blasterll on localh USB Blaster USB DJs smn Altera Corporation 5 10 Runnin
39. Library example Note The soft IP register descriptions are not generated for all soft IP cores Do not expect to have registers for all the cores they use on FPGA Some may have it some may not 1 Perform the steps described in the Getting Started with Hardware Library section up to and including configuring the USB Blaster connection 2 In the Eclipse IDE click Run gt Debug Configurations to open the Debug Configurations dialog box 3 In the Debug Configurations dialog box go to the Files panel and under the Files panel a Select Add peripheral description files from directory from the drop down box b Use the browse File System button to browse to the folder lt SoC EDS Folder gt examples hardware cv_soc_devkit_ghrd soc_system synthesis This is where the svd file generated by Quartus II is located Figure 5 17 Configue Peripheral Register Visibility lt i Connection lier Files Zh Debugger i OS Awareness Arguments B Environment Target Configuration Application on host to download File System Workspace Load symbols Files Add peripheral description files from directory m CAaltera 13 1 embedded examples hardware cv_soc_devkit_ghrd soc_system synthesis _ File System Workspace 4 m Altera Corporation Getting Started Guides J Send Feedback Getting Started with Peripheral Register Visibility 5 19 4 Click the Debug button to download the
40. OK 5 Click Finish The project is imported The project files are displayed in the Project Explorer panel The following files are part of the project Table 5 1 Project Files La ee ee hwlib c Sample application source code Altera SoCFPGA HelloWorld Baremetal GNU Launcher file used to run debug the sample applica Debug launch tion from within Eclipse altera socfpga hosted ld Linker script debug hosted ds Debugger script use to load the sample application Makefile Makefile used to compile the sample application Compiling the Sample Application The sample application is compiled using the Mentor bare metal GCC tool chain invoked by the Makefile 1 To compile the application select the project in Project Explorer Getting Started Guides CJ Send Feedback Altera Corporation 5 8 Running the Sample Application 2 Select Project gt Build Project Figure 5 5 Project Compiled File Edit Source Refactor Navigate Search Project Run Window Help mild Ni E E gv Gr Projec xs W Strea m A E out X Ma m a Te An outline is not available E Altera SoCFPGA HelloWorld Ba in Includes hello c Br Problems 4 Tasks Console 23 E Properties i hello o arm le 1 e as Altera SoCFPGA HelloWorlc CDT Build Console Altera SoCFPGA HelloWorld Baremetal GNU E gt altera socfpga hosted ld vt E RRA Ex A g hell m WS tr ICE prototypes C NErro C 70
41. Project Run Window Help ci S He Bg B Fee 3 Y gl Y i a v v J Debug 52 RS Project Wl Remot h See 0 E H Ws Sa m RIS a m B apra a B Q v y gt 3 D FF SoCFPGA HardwareLib FPG CFPGA HardwareLib F a aaa YW Altera SoCFPGA HardwareLib FP a Debug Breakpoint 3 at S 3 Cortex A9_0 1 stopped on E Continue F8 24 _on file hwlib c E6 Core E 1 r YW Altera SoCFPGA HardwareLib FPGA CV G connected To No OS Support Command aa Altera SoCFPGA HardwareLib FPGA CV GNU Debug launch wlib c 23 gt A O 91 http en wikipedia org wiki Gray_code 13 SF uint32_t gray i gt gt 1 i PJE G Ee BEY alt_write_word ALT LWFPGA_BASE ALT_LWFPGA_LED_OFFSET gray x al PGA HardwareLib printf INFO Gray code i x x gt x x unsigned int i _ for uint32_t j j lt bits j i m Smart Insert 7 Let the program run by clicking the green Continue button or by pressing F8 The code will stop at the breakpoint Note This ensures that when you try to access the soft IP registers they are already available If you try to access the soft IP registers before the FPGA is programmed or before the bridges are open the debugger generates a memory access abort and the debugging session fails 8 Maximize the Registers dialog box and expand the Peripherals register group 9 Scroll to the end of the list and expand the altera_avalon_pio_led_pio_s1 gro
42. W1 5 on the board This will trigger a Signal Tap II acquisition and stop Signal Tap II This will be indicated by the status changing back to Ready to acquire Note On the Data tab you will be able to see the change on the dipswitch signal Figure 5 59 Dipswitch Toggled log 2013 09 06 18 05 21 0 ipga led pio 3 msaa ow Tid inst data_out 1 i A Data z3 Setup Altera Corporation Getting Started Guides CJ Send Feedback HPS Triggering FPGA Example 5 49 11 Go back to the Eclipse debugger you will notice the execution has stopped When SignalTap II is triggered because of the dipswitch it sends the trigger to HPS which in turn stops the cores as instructed Related Information e Cross triggering Prerequisites on page 5 44 For more information refer to the Cross triggering Prerequisites section in this document e Enabling Cross triggering on HPS on page 5 41 For more information refer to the Enabling Cross triggering on HPS section in this document HPS Triggering FPGA Example This section presents an example on how stopping HPS execution in the debugger can trigger FPGA to perform a SignalTap II acquisition This can be useful for example if we want to see the state of some FPGA signals at the time the HPS is stopped in the debugger The required steps are to reproduce this scenario 1 Perform the steps from the Cross triggering Prerequisites section 2 Open the Debugger co
43. You can use the Yocto plugin to manage the application build These tasks do not require JTAG debugging You can perform them both in the Web and Subscription editions For more information see the Licensing section Related Information e Licensing on page 4 1 For more information refer to the Licensing section e Licensing on page 4 1 For more information about svd files refer to the Hardware Software Development Flow section Altera Corporation Introduction to SoC Embedded Design Suite CJ Send Feedback Hardware Software Development Flow 1 5 Hardware Software Development Flow This section presents an overview of the design flow and the handoff between hardware and software development The Altera hardware to software handoff utilities allow hardware and software teams to work independently and follow their respective familiar design flows Figure 1 1 Altera Hardware to Software Handoff Preloader Device Tree The following handoff files are created when the hardware project is compiled e Handoff folder contains information about how the HPS component is configured including things like which peripherals are enabled the pin muxing and IOCSR settings memory parameters etc e svd file contains descriptions of the HPS registers and of the soft IP registers on FPGA side e sopcinfo file contains a description of the whole system The handoff folder is used by the preloader generator to create
44. ads the application on the board through JTAG enables semi hosting using the provided script and runs the application until the PC reaches the main function At this stage all the debugging features of DS 5 can be used such as viewing and editing registers and variables looking at the disassembly code Figure 5 15 Application Downloaded DS 5 Debug Refactor wl S E gt Fl err he Debug 5 T Project A Remot z Stream Navigate Search Project Run ay H Rg va kA k DAML R Altera SoCFPGA HardwareLib FF lt Cortex A9_0 1 stopped on ba Continue F8 La 12 RF main cs3 premain 0x2C Re Altera SoCFPGA HardwareLib FPGA CV G connected No OS Support E Altera SoCFPGA HardwareLib FPGA CV GNU 313 314int main int argc char argv 315 316 317 318 319 320 ALT_STATUS_CODE status ALT_E_SUCCESS ALT_DMA CHANNEL_t channel if status ALT_E_SUCCESS m Smart Insert Altera Corporation Perv B Window Help ey Ge a mgs a Gl Ex bE Dy BY m wy fO F 7 SoCFPGA HardwareLib FPG CFPGA HardwareLib F Stack x 2253388 Heap x 2243388 Execution stopped apy In hwlib c j Name amp Locals argc H argv status m channel Command Pre ji 5 m S MBE o BaAxS HT 9Je coa oe Gl Ex BH era SoCFPGA HardwareLib FPGA C m Getting Started Guides CJ Send Feedback Running the Sa
45. ample erases the flash on the flash addresses where the input file input bin resides followed by a blank check using a cable M Example 10 6 quartus_hps c 1 o E This example erases the full chip using a cable M When no input file input bin is specified it will erase all the flash contents Example 10 7 quartus_hps c 1 o E a 0x100000 s 0x400000 This example erases specified memory contents of the flash For example 4 MB worth of memory content residing in the flash address starting at 1 MB are erased using a cable M Example 10 8 quartus_hps c 1 o X a 0x98679 s 56789 output bin This example examines 56789 bytes of data from the flash with a 0x98679 flash start address using a cable M Supported Memory Devices Table 10 2 QSPI Flash a a a a e Micron 0x18BA20 Micron 0x19BA20 1 256 Micron 0x20BA20 2 512 Micron 0x21BA20 4 1024 Micron 0x18BB20 1 128 Micron 0x19BB20 1 256 Micron 0x20BB20 2 512 Spansion 0x182001 1 128 Sector size of 64 KB Spansion 0x182001 1 128 Sector size of 256 KB Spansion 0x190201 1 256 Sector size of 64 KB HPS Flash Programmer User Guide Altera Corporation CJ Send Feedback 2013 05 03 10 6 Supported Memory Devices Spansion 0x190201 256 Sector size of 256 KB Spansion 0x200201 Table 10 3 ONFI Compliant NAND Flash Micron 0x2C 0x48 Micron 0x2C OxAl 8 Micron 0x2C OxF1 8 Altera Corporation HPS Flas
46. anager The Hardware Manager HW Manager component provides a group of functional APIs that address more complex configuration and operational control aspects of selected HPS resources The HW Manager functions have the following characteristics e Functions employ a combination of low level device operations provided by the SoCAL executed in a specific sequence to effect a desired operation e Functions may employ cross functional such as from different IP blocks device operations to implement a desired effect e Functions may have to satisfy specific timing constraints for the application of operations and validation of expected device responses e Functions provide a level of user protection and error diagnostics through parameter constraint and validation checks The HW Manager functions are implemented using elemental operations provided by the SoCAL API to implement more complex functional capabilities and services The HW Manager functions may also be Altera Corporation Hardware Library Overview CJ Send Feedback Hardware Library Reference Documentation 9 3 implemented by the compound application of other functions in the HW Manager API to build more complex operations for example software controlled configuration of the FPGA Hardware Library Reference Documentation Reference documentation for the SoCAL API and HW Manager API is distributed as part of the SoCEDS Toolkit This reference documentation is provided as on
47. anns 5 49 ARM DS 5 Altera EQUti OM viscscisicnsssnsensdsveteteiaasusietcvsnssestdieateiubcainwieiesivsaseed aus 6 1 Starting FEU Sc chetseses ccs sence cas e EKK RENEE EEE AER 6 1 Project Managements ssssscsscanisacdsieeniaiensuedsd AiaisesversediateodviesdAaastssSvossenssatendyisesesaaicnssasesvsnetensss sete dotenseoouseee 6 2 Deb pgingesninampini pe nia a E R a 6 4 Debug Configuration Op ionic ciciassigscciatiincduatsaitiaaegetiausiernwmsnmayenteiatasuceawcmuincnaves 6 7 DISL Option swiiisied EEEE E EAE 6 14 Embedded Command Shell coiiiscseiessscnccsecthaassssustocscdasssadsanwnihaunsasnssedaduatsoateanenisanss 7 1 HPS Preloader User Guid G cicsccissscacsscoicatosusthiocsenssnicactscsdectoaasaatocses Hinssacteedentossios 8 1 HPS Contig uration sonsaina A EN EEA E 8 1 Preloader Support Package Generator e sseseesesesessssesssstessreesstesnteesntesseressrerereteeseeesntererenressntesnressnresst 8 2 Altera Corporation TOC 4 Altera SoC Embedded Design Suite User Guide Elsi ware Handoff Piles oe siiscsicatasnicscicssechea acl ueseweceasietstadeaectasins tune ninnisin aano iea aaaeaii ka e iasa 8 3 Using the Preloader Support Package Generator GU Ia sivsswsccosscestncasvensscensiientoccasd cass aisb cass toruvssnss 8 3 Preloader Support Package Piles and Vold ers sssssisccsnssadnisnsrvesiencnscechoasssinssdusopilucsbasdvasontacnosssnovsss 8 4 Command Line Tools for the Preloader Support Package Generator 8 4 BSP Settingan ieesadbsubvuevea
48. ardware dialog box select the desired USB Blaster and click OK Getting Started Guides CJ Send Feedback Create manage and run configurations Sexl e type filter text E C C Application E C C Attach to Aj E C C Postmorten E C C Remote Ap Zk DS 5 Debugger 3h Altera SoCFPGF Iron Python Run Iron Python unittes E Java Applet J Java Application Ju JUnit g Jython run g Jython unittest Launch Group dj PyDev Django PyDev Google App Python Run Ed Python unittest eag Remote Java Applic 4 m Filter matched 19 of 19 it Name Altera SoCFPGA HardwareLib FPGA CV GNU Debug Fo Connection Files 234 Debugger OS Awareness 6 Arguments Select target Select the manufacturer board project type and debug opercted Altera Cyclone V SoC Bare Metal Debug Debug Cortex Altera Arria V SoC Cyclone V SoC Bare Metal Debug Debug Cortex A9_0 via Altera USB Blaster DTSL Options Configure trace or other target offiguration options DS 5 Debugger will connect to an Altera USB Blaster to debu Connections Bare Metal Debug Connection m Altera Corporation 5 16 Running the Sample Application Figure 5 14 Select USB Blaster ID Name USB Blasterl on localh USB Blasterll USB 1 5 Click the Debug button from the bottom of the Debug Configurations dialog box 6 Eclipse ask whether to switch to Debug Perspective Click Yes to accept it The debugger downlo
49. are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ISO 101 Innovation Drive San Jose CA 95134 Select the components to be installed Altera recommends that you install all components Click Next 9001 2008 Registered JA DTE RYAN 2 2 Installing the ARM DS 5 Altera Edition Toolkit 10 When the installation is complete turn on Launch DS 5 Installation to start the ARM DS 5 installation Click Finish Note On some Linux based machines you can install the SoC EDS with a setup GUI similar to the Windows based setup GUI Due to the variety of Linux distributions and package requirements not all Linux machines can use the setup GUI If the GUI is not available you use an equivalent command line process Download the Linux installation program from the SoC Embedded Design Suite page on the Altera website Re
50. art of SoC EDS Getting Started Guides Altera Corporation CJ Send Feedback 5 22 Configuring Linux Note This section uses a Linux host computer as can be seen from the screen shots and the issued commands However the scenario can also be run on a Windows machine although it is not usual for Linux development to be done on Windows Related Information e ARM DS 5 Altera Edition on page 6 1 For more information refer to the ARM DS 5 Altera Edition section e ARM DS 5 Documentation The ARM DS 5 Altera Edition reference material can be accessed online on the documentation page of the ARM website www arm com and from Eclipse by navigating to Help gt Help Contents gt ARM DS 5 Documentation e Rocket Boards For more information about Linux refer to the Rocketboards website Configuring Linux For this getting started scenario we need Linux to be running on the target board and be connected to the local network The local network has to have a DHCP server that will allocate an IP address to the board Eclipse needs an account with a password to be able to connect to the target board The root account does not have a password by default so one needs to be set up The required steps are 1 Setup the board as described in the Getting Started with Board Setup section and connect the HPS Ethernet Connector J2 to the local network 2 Start Linux on the target board as described in the Getting Started with Running Linux sec
51. ation can be one the following e None meaning the tracing is disabled e ETR using any memory buffer accessible by HPS e ETF using the 32KB on chip trace buffer e DSTREAM using the 4GB buffer located in the DSTREAM The DSTREAM option is available only if the Target connection is selected as DSTREAM in the Debug Configuration ARM DS 5 Altera Edition Altera Corporation CJ Send Feedback 6 16 DTSL Options Figure 6 16 DTSL Configuration Editor Trace Buffer Debug and Trace Services Layer DTSL Configuration Add edit or choose a DTSL configuration for file dts _config_script py class DSTREAM_DtslScript oP B 4 Name of configuration default Cross Trigger Trace Buffer gt Cortex A9 STM ETR ETF Trace capture method Timestamp frequency System Memory Trace Buffer ETR On Chip Trace Buffer ETF DSTREAM 4GB Trace Buffer The Trace Buffer tab provides the option of selecting the timestamp frequency Figure 6 17 DTSL Configuration Editor Trace Buffer Debug and Trace Services Layer DTSL Configuration Add edit or choose a DTSL configuration for file dtsl_config_script py class DSTREAM_DtsIScript BX Name of configuration default Cross Trigger Trace Buffer gt Cortex A9 STM ETR ETF Trace capture method None Timestamp frequency 25000000 Apply Cortex A9 Settings The Cortex A9 tab allows the selection
52. bastouupaeveauascodenuevcsbouceaebveberbosdeaenasbstvevessuees 8 8 Preloader Co conn yt th as ycsacss sy atlases obeys wtb a suc weaned E A RN ENEN OARE EE EEE 8 13 Configuring FPGA with Image from QSPI Plas iss cdsssiaswcsravanenicnss ests ionnosnsd qattderausnsincessioesentiviansianvieeave 8 13 Loading Next Image from FAT Partition on Sat sas utiass eessawanassnistanucendetuieniceses pins Sommedeaesoin 8 14 Preloader Image DOO sicsassscussucsssudsachsisnnsnoissavapsavsenlencideaswibesbanibeuidaceasbctnssissoadaalusashashaiQ acatanisesniesadsadiat 8 14 Operation of the Preloader Image TOI sssiccciieaientinieaiaianieduimausiumauscueienns 8 14 Tool MS assess echo upoad states oan EN AERE E NOARI 8 15 Output Image Tay OU tseics sk cass eskseats case i ea EE EE E EA E 8 16 pikimage i oases usin sens cp ceshncanseaancnabac esha aa taneavaoraeaa seemed ia NEAN V ENSANSE ania KaD ESSAU SEVENTIES AEE 8 17 mkimage TOO Optom sicsdiesacasiscvansanicissnaniuntsachinesyssssessssuccnsdinucinesassinnedantaaapsanelanmaisaanrasniaacsecverd 8 18 mkimage Tool Image Cred hanna scsccsasssscisiawaneenssecdtasencasa scaauccusisiavitsgucipeneaasouasenaseeiuomuoasaagesensess 8 19 Hardware Library OVerview isecicoscaciasetesinaciipaieactieettcueearaareeni renee 9 1 Feature DESCHIP HOM cass cesencssdascscocdecessesssen tes Cosvtescuedescasverodsssseshonssesbossevasshaeshasasveed obese DaT eiT RE GEKEER Ras 9 2 SoC Abstraction Layer SOCAL i ciceviaseruivisscsutiansseasrels
53. boot select BSEL pins during cold reset you do not need to specify the type of flash to program Using the Flash Programmer from the Command Line HPS Flash Programmer The HPS flash programmer utility can erase blank check program verify and examine the flash The utility accepts a Binary File with a required bin extension The HPS flash programmer command line syntax is quartus_hps lt options gt lt file bin gt Note The HPS flash programmer uses byte addressing Altera Corporation HPS Flash Programmer User Guide CJ Send Feedback 2013 05 03 HPS Flash Programmer 10 3 Table 10 1 HPS Flash Programmer Parameters cable This option specifies what download cable to use To obtain the list of programming cables run the command jtagconfig It will list the available cables like in the following example jtagconfig 1 USB Blaster USB 0 2 USB Blaster USB 1 3 USB Blaster USB 2 The c parameter can be the number of the programming cable or its name The following are valid examples for the above case c 1 c USB Blaster USB 2 device d Yes if thereare This option specifies the index of the HPS multiple HPS device The tool will automatically detect the devices in the chain and determine the position of the HPS chain device however if there are multiple HPS devices in the chain the targeted device index must be specified operation 0 Yes This option specifies the op
54. breakpoints software hardware Set trace points enable disable toggle oanp 9 Select Modules panel to view the currently loaded modules In the example below only the ipv6 module is loaded Altera Corporation Getting Started Guides J Send Feedback Getting Started with Tracing 5 37 Figure 5 38 Linux Kernel Modules O00 18 Disassem Memory Modules X gt Events Outline 7 E amp Vv amp Linked DebugLinux_DevkKit Name Symbols Address Type Host File R ipv6 no symbols S 0x7F000000 kernel module 10 Add breakpoints at the module loadandmodule unload functions As modules are loaded with insmod and removed with rmmod the DS 5 AE will reflect the changes Figure 5 39 Kernel Debugger Breakpoints 6 Vari Bre X gt ms Regi Exp fO Fun ml v amp Linked DebugLinux_DevKit S 0x8008C1E8 ftrace_module_notify_enter De M S 0x8008C1E8 ftrace_module_notify_enter De M S 0x800722D0 sys _init_module Debugger Inte M S 0x8007015C sys_delete_module Debugger amam D Getting Started with Tracing ARM DS 5 provides powerful tracing features allowing PTM and STM tracing It allows different tracing data destination types This section presents an example of Program Tracing using PTM and storing the tracing information in memory using ETF The tracing scenario presented here uses Linux kernel debugging as an example but any application can be traced in the same way As sho
55. button b Edit the Target download directory to be home root the root folder c Edit the Target working directory to be home root the root folder Getting Started Guides Altera Corporation GJ Send Feedback 5 30 Running Sample Application Figure 5 31 Target Configuration Target Configuration Application on host to download workspace _loc Altera SoCFPGA HelloWorld Linux GNU hello File System Workspace Load symbols Target download directory home root Target working directory home root 7 Click the Debug button A dialog window appears asking to switch to Debug perspective Click Yes 8 Eclipse downloads the application to the board and stops at main function entry Figure 5 32 Program Downloaded DS 5 Debug Altera SoCFPGA HelloWorld Linux GNU hello c Eclipse Platform File Edit Source Refactor Navigate Search Project Run Window Help rie B a EA a mla De XN Brr A Re Astr o Ccom x2 gt W Histor Script E 9 B m R SE OF TO A amp oo 7 A a v o a gt amp Linked LinuxAppDebug_DevKit 7 B Linked LinuxAppDebug_DevKit b S wait aj Name Ey e Continue F8 Execution stopped at breakpoint 1 amp Locals 24 v Active Threads a In hello c Sl argc g 0x000908 i hread 2455 annedd i een T gt amp argv LinuxAppDebug_Dev connected i gt File Statics current
56. ck Trace Buffer tab and select On Chip Trace Buffer ETF for the Trace capture method Figure 5 41 Trace Into ETF Cross Trigger Trace Buffer _Cortex A9 STM ETR ETF Trace capture method On Chip Trace Buffer ETF c Timestamp frequency 25000000 6 In the DTSL dialog box click the Cortex A9 tab and enable tracing for both cores Altera Corporation Getting Started Guides GJ Send Feedback Getting Started with Tracing 5 39 Figure 5 42 Enable PTM Tracing Cross Trigger Trace Buffer Cortex A9 STM ETR ETF M Enable Cortex A9 core trace Enable Cortex A9 0 trace Enable Cortex A9 1 trace PTM Triggers halt execution lv 0 K Enable PTM Timestamps Enable PTM Context IDs J Context ID Size 32 bit O Cycle Accurate C Trace capture range 7 In the ETF tab select the ETF to be enabled and a buffer size of 0x8000 to match the ETF size on the Cyclone V SoC which is 32 KB Figure 5 43 Configure ETF Cross Trigger Trace Buffer Cortex A9 STM ETR ETF W Configure the on chip trace buffer Size 0x8000 8 Click OK to exit the DSTL Configuration Editor 9 Start a debugging session by starting the Debug Linux_DevKit debug configuration The debugger stops the Linux kernel and configure tracing 10 Let the kernel run by clicking the Continue green button or pressing F8 11 After executing some commands from the Linux serial terminal click Interrupt button
57. cription Edition allow e JTAG based Bare Metal Debugging e JTAG based Linux Kernel and Driver Debugging e Linux Application Debugging over Ethernet Related Information SoC Embedded Design Suite To download the SoC EDS tools and obtain more information about licensing please refer to the SoC Embedded Design Suite page of the Altera website Getting the License Depending on the licensing option it is necessary to follow the steps detailed for each option to obtain the license Subscription Edition If you have purchased the SoC EDS Subscription Edition then you have already received an ARM license serial number This is a 15 digit alphanumeric string with two dashes in between You will need to use this number to activate your license in DS 5 as shown below Free Web Edition For the free SoC EDS Web Edition you will be able to use DS 5 perpetually to debug Linux applications over an Ethernet connection Please get your ARM license activation code from the SoC Embedded Design Suite download page on the Altera website and then activate your license in DS 5 as shown below 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective hold
58. ct this to debug Linux applications Linux Kernel and or Device Driver Debug select this to debug the Linux kernel and Linux device drivers For the Bare Metal Debug and Linux Kernel and or Device Driver Debug target types the following different scenarios are available Debug Cortex A9_0 via Altera USB Blaster Debug Cortex A9_0 via DSTREAM RVI Debug Cortex A9_1 via Altera USB Blaster Debug Cortex A9_1 via DSTREAM RVI Debug Cortex A9x2 SMP via Altera USB Blaster Debug Cortex A9x2 SMP via DSTREAM RVI Altera Corporation ARM DS 5 Altera Edition J Send Feedback Debug Configuration Options 6 9 For Linux Application Debug option the following different scenarios are available e Connect to already running GDB server e Download and debug application e Start gdbserver and debug target resident application The Connections panel allows the user to specify the connection to be used to communicate to the board Depending on the Target type and the selected scenario the Connections panel will look different e For Bare Metal Debug and Linux Kernel and or Device Driver Debug target types a Browse button appears and it allows the user to browse and select either the Altera USB Blaster or the DSTREAM instances e For the Linux Application Debug the Connection needs to be configured in the Remote System Explorer view File Options The Files tab allows the following settings to be configured e Application on host to download
59. d modify an existing preloader support package PSP project in the preloader support package generator click File gt Open and browse to an existing bsp file To create a new PSP project click File gt New BSP to open the New BSP dialog box The New BSP dialog box includes the following settings and parameters e Preloader settings directory the path to the hardware handoff files The generator inspects the handoff files to verify the validity of this path e Operating system and Version Not applicable to preloader generation e BSP target directory the destination folder for new BSP files created by the generator This document refers to the preloader BSP directory as lt bsp_directory gt The default directory name is spl_bsp You can modify the directory name e BSP settings file name the location and filename of the bsp file e Additional tcl scripting the location and filename of a tcl script for overriding the default BSP settings You can customize the PSP After creating or opening a bsp file access the Settings in the BSP Editor dialogue box The Settings are divided into Common and Advanced settings When you select a group of settings the controls for the selected settings appear on the right side of the dialogue box When you select a single setting the setting name description and value are displayed You can edit these settings in the BSP Editor dialogue box Click Generate to generate the preloader su
60. der 5 3 The steps are 6 Setup the board as described in Board Setup section Extract the SD card image from the archive lt SoC EDS installation directory gt embeddedsw socfpga prebuilt_images sd_card_linux_boot_image tar gz The file is named sd_card_linux_boot_image img The command tar xzf lt filename gt can be used from Embedded Command Shell to achieve this Write the SD card image to a micro SD card using the free tool Win32DiskImager from the Sourceforge Projects website sourceforge net on Windows or the dd utility on Linux Power up the board using the PWR switch Connect a serial terminal from the host PC to the serial port corresponding to the UART USB connection and use 115 200 baud no parity 1 stop bit no flow control settings After successful boot Linux will ask for the login name Enter root and click Enter Figure 5 1 Linux Booted radu sudo File Edit View Scrollback Bookmarks Settings Help INIT Entering runle Starting OpenBSD S done rting sy rting Li Stopping Boot radu sudo Related Information Rocket Boards For more information about the latest Linux version refer to the Rocketboards website Sourceforge Projects To obtain the free tool Win32DiskImager refer to the Projects section of the Sourceforge website Getting Started with Preloader This section presents an example of how to generate and compile the Preloader for the Cyclone V SoC Golden Hardware Refere
61. e e Precompiled preloader Embedded command shell allowing easy invocation of the included tools Yocto Eclipse plugin Quartus II Programmer and SignalTap II Note The Linux package included in SoC EDS is not an official release and is intended to be used only as an example Use the official Linux release described in the Golden System Reference Design GSRD User Manual available on the Rocketboards website www rocketboards org or a specific release from the Git trees located on the Gitweb page of the Rocketboards website www rocketboards org for development Note The SoC EDS was tested only with the Linux release that comes with it Newer Linux releases may not be fully compatible with this release of SoC EDS Note The Golden Hardware Reference Design included with SoC EDS is not an official release and is intended to be used only as an example For development purposes please use the official GHRD release described in the GSRD User Manual available on the Rocketboards website www rocketboards org Related Information Rocketboards website For more information about the GHRD releases and to obtain the official Linux and GHRD releases refer to the Rocketboards website Device Tree Binary There are two device tree binary DTB files delivered as part of SoC EDS lt SoC EDS Installation directory gt embeddedsw socfpga prebuilt_images socfpga_cyclone5 dtb This is a generic DTB file which does not have any dependency o
62. e FPGA gt HPS Cross Trigger C Enable HPS gt FPGA Cross Trigger Cross Trigger initialization The Cross Trigger interface can only be accessed if the system clocks have been initialized If the Cross Trigger interface is accessed prior to the clock initialization then the target may lock up The folllowing option should only be set if you are sure that the system clocks have been initialized prior to DS 5 connecting to the target system The system clocks are typically set up by running the Altera preloader script C Assume Cross Triggers can be accessed In order to allow FPGA cross triggers to trigger HPS you need to e Check the Enable FPGA gt HPS Cross Triggering check box e Check the Assume Cross Triggers can be accessed check box In order to allow HPS cross triggers to trigger FPGA you need to e Check the Enable HPS gt FPGA Cross Triggering check box e Check the Assume Cross Triggers can be accessed check box Note In order to enable bi directional triggering you can check all three checkboxes Altera Corporation Getting Started Guides CJ Send Feedback Enabling Cross triggering on FPGA 5 43 Enabling Cross triggering on FPGA For this getting started scenario we are using Quartus SignalTap II utility to control FPGA cross triggering Figure 5 47 SignalTap Cross Trigger Options Trigger Trigger flow control Sequential gt Trigger position Pre trigger position gt
63. e Running Linux needed for the scenarios that use Linux The guides presented in this chapter are intedned to be run on a Cyclone V SoC Development board Getting Started with Board Setup This section presents the necessary Altera Cyclone V Development Kit board settings in order to run Linux and the Getting Started examples External Connections e External 19V power supply connected to J22 DC Input e Mini USB cable connected from host PC to J37 Altera USB Blaster II connector This is used for connecting the host PC to the board for debugging purposes e Mini USB cable connected from host PC to J8 UART USB connector This is used for exporting the UART interface to the host PC e Ethernet cable from connector J3 to local network This is used if Linux network connectivity is desired 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assume
64. e Trace Capture Range is enabled STM Settings The STM tab allows you to configure the STM System Trace Macrocell ARM DS 5 Altera Edition os Send Feedback Altera Corporation 6 18 DTSL Options Figure 6 19 DTSL Configuration Editor STM Debug and Trace Services Layer DTSL Configuration Add edit or choose a DTSL configuration for file dts _config_script py class DSTREAM_DtslScript B Name of configuration default C Cross Trigger Trace Buffer Cortex A9 STM gt ETR ETF F Enable STM trace Only one option is available e Enable STM Trace check to enable STM tracing ETR Settings The ETR settings allow the configuration of the ETR Embedded Trace Router settings The Embedded Trace Router is used to direct the tracing information to a memory buffer accessible by HPS Figure 6 20 DTSL Configuration Editor ETR Debug and Trace Services Layer DTSL Configuration Add edit or choose a DTSL configuration for file dts _config_script py class DSTREAM_DtslScript AX Name of configuration default CE Cross Trigger Trace Buffer Cortex A9 STM ETR gt ETF V Configure the system memory trace buffer Start address 0x100000 Size 0x8000 Enable scatter gather mode Altera Corporation ARM DS 5 Altera Edition CJ Send Feedback DTSL Options 6 19 The following options are available e Configure the system memory trace buffer ch
65. e command from the Embedded Command Shell 2 The Eclipse tool part of ARM DS 5 AE prompts for the workspace folder to be used Use the suggested folder and click OK 3 The ARM DS 5 AE Welcome screen appears It is instructive and can be used to access documentation tutorials and videos Importing the Sample Application 1 In Eclipse select File gt Import The Import dialog box displays 2 In the Import dialog box select General gt Existing Projects into Workspace and click Next This will open the Import Projects dialog box Altera Corporation Getting Started Guides CJ Send Feedback Importing the Sample Application 5 13 Figure 5 10 Import Existing Project Select Create new projects from an archive file or directory Select an import source type filter text 4 amp General Archive File 3 Existing Projects into Workspace G File System E Preferences 3 In the Import Projects dialog box select the Select Archive File option 4 Click Browse then navigate to lt SoC EDS Location gt embedded examples software select the file Altera SoCFPGA HardwareLib FPGA CV GNU tar gz and click OK Figure 5 11 Select Imported File Import Projects Select a directory to search for existing Eclipse projects Select root directory Select archive file HardwareLib FPGA CV GNU tar gz Projects PGA CV GNU Altera SoCFPGA HardwareLib FPGA CV GNU
66. eader from mkimage Tools Next Stage Boot Image mkimage Signature Header The preloader reads the following information from mk image header ak WN Figure 8 7 mkimage Header Layout from mkimage Tools 0x0040 Image magic number determines if the image is a valid boot image Image data size the length of the boot image to be copied Data load address the entry point of the boot image Operating system determines if the image is a U boot image or another type of image Image name the name of the boot image 6 Image CRC the checksum value of the boot image 0x0030 0x0020 0x0010 0x0000 Image name Data load address Entry point Image CRC OS arch type compression Magic number Header CRC Timestamp Image data size 0x4 OxC OxD OxE OxF The mkimage tool source files are included with the preloader source files in lt bsp_directory gt uboot socfpga tools mkimage The mkimage tool compiles and generates during preloader compilation but you can alternatively create the mkimage tool by typingmake tools in lt bsp_directory gt To use the mkimage tool you can add lt bsp_directory gt uboot socfpga tools to the system PATH environment variable mk image invokes the mkimage tool and the he1p option provides the tool description and option information mkimage Tool Options The help option of the mkimage tool provides the tool description and option
67. eadovecbaptasabaspastuwess 5 24 Setting up Remote System Explorer ces cincersccgsvassanebinniatsearvnrtnesvaaidodvenigamadsiovens tens 5 25 Running Sample Applicat Osi cassy sels starcisncesecrarseasviasivianrarvoaaansay anni aamearmereuraneates 5 28 Getting Started with Linux Kernel and Driver Debuggings cscscsssassscsseenicsssvsasssusssssessosssasssosniancassosns 5 31 PHELEQUISILES Sa ninun E A E E E 5 32 Starting Eclipse via the Embedded Command Shell cssssssssssssssssorsssssssssssscnessssncssseesseeses 5 32 Debugging th Wet casi csearsantyalavcesncexsascisekacsasar est avessshantisc eames aired ARa 5 32 Getting Started With Tracing ssis iieiea esenaestnennndanhenanvansinaashaabvennereaame catamarans 5 37 Getting Started with Cross Triggering ee sseeesesressrressressrtrssreeesstessttesnteesntentesnttsntessntesteesrtrererererreret 5 41 Enabling Cross triggering on FIPS c ciccsisasssiksveaisniniesiarcadteacdshincnataieullaieoaneaninmunanuases 5 41 Enabling Cross triggering on FPGA siccaciesisicssuaciwvinacacesicccssinorasseocanelasonilasinsaanesaavinetuedviiiives 5 43 Cross triggering Prerequisites sissssscisedssssessscdavassavesssocers scateossocessssnsedacscupsbsssadgessaciessvederosacssscinats 5 44 FPGA Daren HPS ata aracistssaceasins seve secasvandienianveussnansiseroiessuaabotcmswassqabaneanapecaeuaiys 5 46 FIPS Triggering FPGA Baa pl ess sssiscasissiscssdessbcvssvssscuspanacespaanicpbenanvaichanssaessthedd ivacnokvdvansaniandpe
68. eck this if the ETR was selected as the trace destination on the Trace Buffer tab e Start Address Size define the trace buffer location in system memory and its size e Enable scatter gather mode used when the OS cannot guarantee a contiguous piece of physical memory The scatter gather table is setup by the operating system using a device driver and is read automatically by the ETR ETF Settings The ETF tab allows the configuration of the ETF Embedded Trace FIFO settings The Embedded Trace FIFO is a 32KB buffer residing on HPS that can be used to store tracing data to be retrieved by the debugger but also as an elastic buffer for the scenarios where the tracing data is stored in memory through ETR or on the external DSTREAM device using TPIU Figure 6 21 DTSL Configuration Editor ETF Debug and Trace Services Layer DTSL Configuration Add edit or choose a DTSL configuration for file dts _config_script py class DSTREAM_DtsIScript d Name of configuration default Cross Trigger Trace Buffer Cortex A9 STM ETR ETF 4 Configure the on chip trace buffer Size 0x1000 The following options are available e Configure the on chip trace buffer check this if ETF was selected as the trace destination on the Trace Buffer tab e Size define the ETF size By default it is set up to 0x1000 4KB but it can be set to 0x8000 32KB to match the actual buffer size ARM DS 5 Altera
69. ective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services 101 Innovation Drive San Jose CA 95134 ISO 9001 2008 Registered JA DTE RYAN Licensing S Subscribe C3 Send Feedback The SoC EDS is available with three different licensing options e Subscription Edition e Free Web Edition e 30 day Evaluation of Subscription Edition The only tool impacted by the selected licensing option is the ARM DS 5 Altera Edition All the other tools offer the same level of features in all licensing options This means the preloader generator bare metal compiler etc offer the same features no matter which licensing option is used The main difference between the licensing options consists in which types of debugging scenarios are enabled e Web Edition allows Linux Application Debugging over Ethernet e Subscription Edition and 30 day Evaluation of the Subs
70. efault HPS Preloader User Guide CJ Send Feedback Altera Corporation 8 10 BSP Settings 2013 05 03 spl boot WARMRST_SKI CFGIO Boolean True This setting enables the preloader to skip IOCSR and pin multiplexing configuration during warm reset spl boot WARMRST_SKIP_ CFGIO is only applicable if the boot ROM has skipped IOCSR and pin multiplexing configura tion spl debug DEBUG_MEM WRITE ORY_ Boolean False This setting enables the preloader to write debug information to memory for debugging useful when UART is not available The address is specified by spl debug DEBUG_ MEMORY_ADDR spl debug SEMIHOST NG Boolean False This setting enables semihosting support in the preloader for use with a debugger tool spl debug SEMIHOSTING is useful when UART is unavail able Refer to the ARM Infocenter for more information on semihosting spl debug HARDWARE_ DIAGNOSTIC Boolean False This setting enables hardware diagnostic support enabling hardware to read from and write to the SDRAM to ensure hardware is working the status is reported in the console spl debug SKIP_SDRA M Boolean False The preloader skips SDRAM initialization and calibration when this setting is enabled spl performance SER SURO Ral IAL Boolean True This setting enables UART print out support enabling preloader code to call printf
71. em Di fe C C Remote Applic 3 DS 5 Debugger 2 SampleConfigurati Iron Python Run Iron Python unittest 4 n b Filter matched 19 of 19 items Apply Variable Value Debug Event Viewer The Event Viewer allows you to enable and configure the event views for the STM System Trace Macrocell and ITM Instrumentation Trace Macrocell The SoC FPGA does not have an ITM so only STM can be enabled When STM Viewer is enabled the size of the trace depth is also configured Figure 6 13 Debug Configurations Event Viewer Create manage and run configurations Connection Configuration for connection type Bare Metal Debug is not valid Connection cannot be empty Geax B 7 Name SampleConfiguration type filter text Files Bs Debugger 3 RTOS Awareness Arguments I Environment amp Event Viewer ou E C C Applicatic ITM STM C C Attach to C C Postmortd Enable Event Viewer for STM events C C Remote A amp DS 5 Debugger j 1Mb 25 SampleConfic Iron Python Run a tenn Meth nitt 4 m r Filter matched 19 of 19 ite ARM DS 5 Altera Edition Altera Corporation CJ Send Feedback 6 14 DTSL Options DTSL Options The tracing options are configured from the DTSL Configuration window accessible from the Debug Configuration window by pressing the Edit button DTSL represents Debug and Trace Services Layer Figure 6 14 Debug
72. end Feedback Debug Configuration Options 6 7 Figure 6 6 Naming your Configuration Create manage and run configurations Debugger Debugging from a symbol but no symbol files defined in the Files tab r ga ey Cex E7 Name MEE gt type filter text lt 4 Connection Files B Debugger i RTOS Awareness 3 fe C C Application E C C Attach to Aj fe C C Postmorten E C C Remote Ap Z DS 5 Debugger 2 New_configurat Cyclone V SoC Iron Python Run Bare Metal Debug 2 Iron Python unittes Linux Application Debug E Java Applet Linux Kernel and or Device Driver Debuq Select target Select the manufacturer board project type and debug operation to use Cu 5 Java Application Ju JUnit 2 Jython run Te r Filter matched 19 of 19 items Debug Debug Configuration Options This section lists the Debug Configuration options which allows you to specify the desired debugging options for a project Refer to the DS 5 reference documentation for the complete details Refer to the Getting Started Guides for concrete examples on how to use the debugging features of ARM DS 5 Altera Edition Connection Options The Connection tab offers the following configurable options e Target specifies which target to use e DTSL Options specifies the Debugger and described in detail in another section e Connections specifies the way to connect to the target ARM DS 5 Altera Edition
73. endvnansdecbebsasseedsiaeatcadenallaaaibebeesseauseavedindeneucauinecntcciemuses 4 1 Getting the LICENSE ssenarisi isai EEEE EIA AER R EOE ERA 4 1 Activating the Lices seoniniiiiiiin isinna EEEN EN 4 2 Getting Started GU d S ssiiciiisissssscisciinenesdiiie creir anbar orias aosa tiecies iannis 5 1 Getting Start d with Board Seca pss sscesccssscichcsssvassatacnvavchse ctvaceupensnviasayeaeeciasouadeuonvetannsansucomasemomsenses 5 1 External Connections nsesnisnienanneni an aan e Gehosianes 5 1 Dip Switch SS UTI esha dooce lnec aare air ced tA PESTEN E EE ASETTAEN LA VREA ei S E ASAE 5 2 Jumper SEM SS i sissssscssce caststeevecessesbusssvics susseksuevorssivvenssadeistesevessacessverccobsesbsondectansedbvbestesusuesteieascvext 5 2 Getting Started with Running Vim ss sscsasapinisannseacecsssacauvausdsiudepeddapeasanuanacnssiilcadudusducel sacbusdaneapivbsneiaadnieas 5 2 Getting Started with Preloader airera iiinis riidesse re i aera DEE lesstusduld laucnssasassanudgpsasonisan 5 3 Getting Started with Bare Metal Debugging ese sssessssessrsessstessteesntessetessreruserenseeesnrersnresnresnrrsnrrssnresns 5 6 Starting th Eclipse IDEmnnanenunienann anaidai 5 6 Importing the Sample Application s sesesesessesesesssssssrssrrssstesstessntesntessrressreensrrsereresrreesreesrreessres 5 7 Compiling the Sample Application sesesesessesesssssssssrssrsssstesstessntrsntessrressrresrrrsereresrreesrtesrreessres 5 7 R n ing the Sample App GA M
74. ensure the BSP files are up to date HPS Preloader User Guide Altera Corporation CJ Send Feedback 8 8 BSP Settings 2013 05 03 Table 8 4 User Parameters bsp generate files a Rearea T Deaton settings lt settings file gt Yes This option specifies the path to an existing BSP settings file bsp dir lt bsp dir gt Yes This option specifies the path where the BSP files are generated BSP Settings The preloader support package generator includes BSP settings for the following command options Table 8 5 Command Options r bsp create settings set bsp update settings set get bsp query settings get all show names Table 8 6 Available BSP Settings spl PRELOADER_TGZ String SOCEDS_DEST_ ROOT This setting specifies the path to host_tools altera archive file containing the preloader uboot preloader source files socfpga tar gz spl1 CROSS_COMPILE String arm none eabi This setting specifies the cross compilation tool chain for use spl boot BOOT_FROM_QSPI Boolean False This setting loads the boot loader image from QSPI spl boot BOOT_FROM_SDMMC Boolean True This setting loads the subsequent boot image from Secure Digital MultiMediaCard SD MMC spl boot BOOT_FROM_RAM Boolean False This setting loads the subsequent boot image from RAM spl boot QSPI_NEXT_BOOT__ Hexadecimal 0x60000 This setting specifies the location IMAG
75. er Convert RBF file to an image file using the mkimage utility Program the image file to QSPI at the address CONFIG_SPL_FPGA_QSPI_ADDR which is defined in uboot socfpga include configs socfpga_common h Boot board HPS Preloader User Guide Altera Corporation CJ Send Feedback 2013 05 03 8 14 Loading Next Image from FAT Partition on SD Card Loading Next Image from FAT Partition on SD Card The Preloader has the ability to load the next boot stage image from a FAT partition on an SD card This is an alternative to putting the next boot image on the custom SD card partition with ID 0xA2 It is more convenient to write data to a FAT partition than a custom partition especially on a Windows host OS In order to use this feature the following steps need to be performed Configure the Preloader load the next boot stage from SD MMC Generate Preloader Compile Preloader to make sure all the source code is available LW N Modify file uboot socfpga include configs socfpga_common h to have the macro CONFIG_SPL_FAT_SUPPORT defined It is undefined by default 5 In the same file edit the following macros if necessary e define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 e define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME u boot img 6 Copy the next stage boot image on the SD card FAT partition 7 Boot board Preloader Image Tool The preloader image tool creates an Altera boot ROM compatible image of the preloader The to
76. er PY 2 SampleConfig Iron Python Run 2 Iron Python unite Run debug initialization debugger script ds py E Java Applet E O Java Application Ju JUnit g Jython run Fd Jython unittest Launch Group dij PyDev Django 2 PyDev Google Ap Ej Python Run g Python unittest eag Remote Java Appl Run control D Connect only Debug from entry point Debug from symbol main E Execute debugger commands Host working directory V Use default S workspace_loc Paths Source search directory v File System Workspace 4 m Filter matched 19 of 19 ite RTOS Awareness The RTOS Awareness tab allows you to enable Keil CMSIS RTOS RTX awareness for the debugger in case that specific RTOS is used ARM DS 5 Altera Edition Altera Corporation GJ Send Feedback 6 12 Debug Configuration Options Figure 6 10 Debug Configurations RTOS Awareness Create manage and run configurations Connection Configuration for connection type Bare Metal Debug is not valid Connection cannot be empty Bi B x E Fe Bf Name SampleConfiguration type filter text fm Files Debugger 3 RTOS Awareness 69 Arguments I Environment c C C Application lt a C C pride to Appi J Select RTOS awareness Non E C C Postmortem Di CMSIS RTOSRTX fe C C Remote Applic 3 DS 5 Debugger 2 SampleConfigurati Iron Python Run Iron Python unittest
77. eration to be performed The following operations are supported e I Read IDCODE of SOC device and discover Access Port e S Read Silicon ID of the flash e E Erase flash e B Blank check flash e P Program flash e V Verify flash e EB Erase and blank check flash e BP Program lt BlankCheck gt flash e PV Program and verify flash e BPV Program blank check and verify flash e X Examine flash Note The program begins with erasing the flash operation before programming the flash by default addr a Yes if the start This option specifies the start address of the address is not 0 operation to be performed HPS Flash Programmer User Guide Altera Corporation CJ Send Feedback 2013 05 03 10 4 HPS Flash Programmer Command Line Examples size This option specifies the number of bytes of data to be performed by the operation size is optional repeat These options should be used together The HPS BOOT flow supports up to four images where each image is identical and these options duplicate the operation data therefore you do not need eSW to create a large file containing duplicate images interval i repeat specifies the number of duplicate images for the operation to perform interval specifies the repeated address The default value is 64 kilobytes KB repeatand intervalare optional HPS Flash Programmer Command Line Examples Please run quartus_hps
78. ers as described at Be www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with egiste Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JN DTE RYA 101 Innovation Drive San Jose CA 95134 4 2 Activating the License Activating the License This section presents the steps required for activating the license in DS 5 Altera Edition by using the serial license number or activation code that were mentioned in the Getting the License section Note An active user account is required to activate the DS 5 Altera Edition license If you do not have an active user account it can be created on the ARM Self Service page available on the ARM website silver arm com 1 The first time the Eclipse IDE from the ARM DS 5 is run it notifies you that it requires a license Click the Open License Manager button Figure 4 1 No License Found ARMDS 5 is license managed but there are no registered licenses Use the ARM L
79. erty of their respective holders as described at ISO www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with 9001 2008 Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes Registered no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JN DTE RYA 101 Innovation Drive San Jose CA 95134 2013 05 03 10 2 How the HPS Flash Programmer Works How the HPS Flash Programmer Works The HPS flash programmer is divided into a host and a target The host portion runs on your computer and sends flash programming files and programming instructions over a download cable to the target The target portion is the HPS in the SoC The target accepts the programming data flash content and required information about the target flash memory device sent by the host The target writes the data to the flash memory device Figure 10 1 HPS Flash Programmer Host Computer Flash Download Cable e g USB Blaster The HPS flash programmer determines the type of flash to program by sampling the
80. executable file as shown in the figure below The Console dialog box shows the commands that were executed Altera Corporation Getting Started Guides CJ Send Feedback Setting up Remote System Explorer 5 25 Figure 5 23 Project Compiled C C Eclipse Platform File Edit Source Refactor Navigate Search Project Run Window ri a iv Gi fy G K amp s Ga Ov eg Proje ste 70 Alom o gt e Vv An outline is not a available v SAltera SoCFPGA HelloWorl b 3 Binaries E Problems Tasks El Console 2 E Properties a b ig Includes CDT Build Console Altera SoCFPGA HelloWorld Linux GNU gt hello c l amp aaa ee re s hello arm le make att a gt aj hello o arm le arm lLinux gnueabihf gcc g 00 Werror Wall c gt helioma hello c o hello o S map arm Linux gnueabihf gcc g 00 Werror Wall hello o Makefile 0 hello cc m 5 arm Linux gnueabihf nm hello gt hello map Altera SOCFPGA H d Linux GNU hello Setting up Remote System Explorer The ARM DS 5 AE can run and debug programs directly on the target with the help of the Remote System Explorer RSE Before this feature can be used the RSE needs to be configured to connect to the target board running Linux 1 In your Eclipse workspace select Window gt Open Perspective gt Other This will open the Open Perspective dialog box 2 In the Open Perspective dialog box click t
81. g Debug server started successfully l gt p v ze gt 7 To view the running threads maximize the top left panel It shows Active Threads with the two currently executing threads Also the All Threads can be expanded to show all threads in the system Getting Started Guides CJ Send Feedback Altera Corporation 5 36 Debugging the Kernel Figure 5 37 Linux Threads 7 Debug Control 53 amp Project Explorer 4 Remote Systems e B Ma esi 7 Debughinux Devkitcomected O fP v Active Threads v swapper 0 2 stopped PID 0 was running cpu_v7_do idle 0x8 gt swapper 1 3 stopped PID 0 was running v All Threads gt amp swapper 0O 2 stopped PID 0 was running gt swapper 1 3 stopped PID 0 was running gt a kthreadd 4 PID 2 gt a ksoftirqd O 5 PID 3 gt X kworker 0 0 6 PID 4 gt kworker 0 0H 7 PID 5 gt X kworker u 0 8 PID 6 gt a kworker u 0H 9 PID 7 gt migration O 10 PID 8 gt rcu_bh 11 PID 9 gt rcu_sched 12 PID 10 amp DebugLinux_DevKit connected Linux Kernel Enabled s 8 Minimize the Debug Control panel and maximize the Functions panel from top right All of the functions in the kernel are displayed The Functions panel supports the following operations for each function Run up to the function Set PC to function Locate in source code memory disassembly Set
82. g the Sample Application 5 Click the Debug button from the bottom of the Debug Configurations dialog box 6 Eclipse ask whether to switch to Debug Perspective Click Yes to accept it The debugger downloads the application on the board through JTAG enables semi hosting using the provided script and runs the application until the PC reaches the main function At this stage all the debugging features of DS 5 can be used viewing and editing registers and variables looking at the disassembly code Figure 5 8 Program Downloaded ZDSs Debug Refactor Navigate Search Project Run Window Help rye ela ay Bp E me v Rly 7 J Debug X Project A Remote w Streamli m L X al X 4 m G8 x el or all a a ARS ae k Altera SoCFPGA HelloWorld Baret Continue Fa pnnected Itcra SoCFPGA HelloWorld Bare SoCFPGA HelloWorld F Cortex A9_0 1 Perper oes FTOR CRECI PO Nune Semihosting stack heaf amp amp Locals al __cs3_premain 0x2C Stack x 000000 argc __cs3_start_c 0x140 Heap xFFFF3FB amp argv 4 a r z p R Altera SoCFPGA HelloWorld Baremetal Debug connected File Statics cu _ m e FeLi No OS Support Command Pre Submit m MiBje szo eTe 1 8 B App Co X N i Target Error Lo m 10 int main int argc char argv Linked Altera SoCFPGA HelloWorld Baremetal Debu 11 printf Hello Tim n return 8 include lt stdio
83. gnment 8 17 Related Information Booting and Configuration For information about how the boot ROM loads preloader images see Boot ROM Flow in theBooting and Configuration appendix in volume 3 of the Arria V Device Handbook or the Cyclone V Device Handbook Address Alignment Every preloader image aligns to a 64 KB boundary at offsets 0x0 0x10000 0x20000 and 0x30000 except for the NAND flash Version 0 of the boot ROM assumes that all preloader images in flash memory align to 64 KB boundaries except in the case of NAND flash If the preloader images are stored in NAND flash with an erasable block size larger than 64 KB preloader images are aligned to the block size The preloader image tool is unaware of the target flash memory type If you do not specify the block size the default is 64 KB NAND Flash Each preloader image occupies an integer number of blocks A block is the smallest entity that can be erased so updates to a particular boot image does not impact the other images The size of a single preloader image sizing is either 64 KB or the NAND flash block size whichever is larger For example if a NAND block is 32 KB or 64 KB a single preloader image size is 64 KB if a NAND block is 128 KB a single preloader image size is 128 KB Serial NOR Flash Each QSPI boot image occupies an integer number of sectors unless subsector erase is supported this ensures that updating one image does not affect other images SD MMC
84. h Programmer User Guide CJ Send Feedback Linux Compiler 1 1 S subscribe J Send Feedback The Linux compiler that is shipped with SoCEDS is the Linaro Linux compiler version 4 7 3 The compiler is a GCC based arm linux gnueabihf port That is it target the ARM processor it assumes the target platform is running Linux and it uses the GNU EABI HF conventions The Linux compiler is installed as part of the ARM DS 5 Altera Edition which is installed as part of SoCEDS The compilation tools are located in the following folder lt SoC EDS installation directory gt ds 5 bin The Linux compiler comes with full documentation located in the following folder lt SoC EDS installation directory gt ds 5 documents gcc The documents are provided as HTML files Some of the provided documents are e Compiler manual e Assembler manual e Linker manual e Binutils manual GDB manual e Getting Started Guide Related Information Linaro For more information about the Linux compiler and for downloading the latest version of the tools if necessary refer to the download page at the Linaro website www linaro org 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service mark
85. he Remote System Explorer and click OK 3 In the Remote System Explorer view right click Local and select New gt Connection This will open the New Connection wizard Note Clicking the sign achieves the same result Getting Started Guides Altera Corporation CJ Send Feedback 5 26 Setting up Remote System Explorer Figure 5 24 Create New Connection Remote Sy amp Team 70 e a els gt Define a connection to remote system gt 4 Local Files Y Local Shells 4 In the first page of the New Connection wizard named Remote System Type view select SSH only and click Next Figure 5 25 New Connection window New Connection Select Remote System Type Connection for SSH access to remote systems System type type filter text v amp General ta FTP Only A Linux Local unix UN X amp Windows 5 Enter the IP address of the board in the Host Name field Click Finish to create the connection Altera Corporation Getting Started Guides GJ Send Feedback Setting up Remote System Explorer 5 27 Figure 5 26 Enter Target IP Address New Connection Remote SSH Only System Connection Define connection information Parent profile radu linux o Host name 137 57 160 214 v Connection name 137 57 160 214 Description M Verify host name lt Back i Next gt Cancel 6 In
86. he external SDRAM Loads the next image in the boot process typically stored in a flash device such as the NAND flash memory Secure Digital MultiMediaCard SD MMC flash memory or the quad serial peripheral interface QSPI flash memory 5 Jumps to the next loaded boot image hw nN Preloader Support Package Generator The preloader support package generator provides you with an easy safe and reliable way to customize the preloader The preloader image tool creates an Altera boot ROM compatible image of the preloader The preloader support package generator creates a customized preloader support package with preloader generic source files and board specific SoC FPGA files The generator consolidates required hardware settings and your inputs to create the preloader support package The support package files include a makefile to create the preloader image you can download the preloader image to a flash device or FPGA RAM The preloader support package generator allows you to perform the following tasks e Create a new preloader support package e Report preloader support package settings e Modify preloader support package settings e Generate preloader support package files Figure 8 2 Preloader Support Package Generator Flow User Inputs Qsys Qsys Settings J e g Pin Multiplexer Generate User Inputs Quartus gt Hardware Quartus Settings Handoff File
87. help to obtain information about usage You can also run quartus_hps help lt option gt to obtain more details about each option For example quartus_hps help 0 Example 10 1 quartus_hps c 1 o P input bin This example programs the input file input bin into the flash starting at flash address 0 using a cable M Example 10 2 quartus_hps c 1 o PV a 1024 s 500 input bin This example programs the first 500 bytes of the input file input bin into the flash starting at flash address 1024 followed by a verification using a cable M Example 10 3 quartus_hps c 1 o PV a 0x400 s 500 input bin This example programs the first 500 bytes of the input file input bin into the flash starting at flash address 1024 followed by a verification using a cable M Without the prefix Ox for the flash address the tool assumes it is decimal With the prefix 0x the tool assumes it is hexadecimal Example 10 4 quartus_hps c 1 o BPV t 2 i 0x100000 input bin This example programs the input file input bin into the flash using a cable M The operation repeats itself twice at every 1 megabyte MB of the flash address Before the program operation the tool ensures the flash is blank After the program operation the tool verifies the data programmed Altera Corporation HPS Flash Programmer User Guide CJ Send Feedback 2013 05 03 F Supported Memory Devices 10 5 Example 10 5 quartus_hps c 1 o EB input bin This ex
88. henever it performs an acquisition Figure 5 55 Enable Trigger Out to HPS Pin Instance v Hard Processor System HPS trigger in Hard Processor System HPS event Level Active High gt Latency delay 5 cycles 6 In Signal Tap II configure the Trigger in to be disabled by setting its pattern to Don t Care In this scenario we do not want the HPS to trigger FPGA Figure 5 56 Disable SignalTap Trigger in Pin Node D Instance 4 gt Hard Processor System HPS trigger out Pattern Don t Care gt Getting Started Guides Altera Corporation CJ Send Feedback 5 48 FPGA Triggering HPS Example 7 In Eclipse debugger let the Linux kernel continue running by pressing the green Continue button or pressing F8 8 In SignalTap II press the Run Analysis button to arm Signal Tap Figure 5 57 Run Analysis Instance Manager Pa 6 4 28 Ready to acquire Instance StatusfRun Analysis 87 Memory 102 Small NA Medium NA auto Not running 337 cells 10240 bits NA 9 SignalTap II will run the analysis and wait for the trigger from the dipswitch Figure 5 58 Acquisition in Progress Instance Manager a UCC POTTS Instance Status LEs 587 Memory 102 Small NA Medium NA auto_ Waiting for 587 cells 10240 bits NA 10 Change the state of the FPGA Dipswitch 0 S
89. ia V Device Handbook Getting Started with Bare Metal Debugging The ARM DS 5 Altera Edition provides very powerful bare metal debugging capabilities This section presents running the ARM DS 5 Altera Edition for the first time importing compiling and running the Hello World bare metal example application provided as part of SoC EDS Sample Application Overview The provided sample application prints a Hello message on the debugger console by using semihosting This way no pins are used and all communication happens through JTAG The application is located in the 64 KB On Chip RAM and therefore does not require the SDRAM memory on the board to be configured Due to its simplicity and the fact that does not require pins or external resources to be configured this application can be run on any board supporting the SoC device Note Make sure that Linux or another OS is not running on the board prior to doing this example An OS can interfere with the feature of downloading and debugging bare metal applications Note The screen snapshots and commands presented in this section were created using the Windows version of SoCEDS but the example can be run in a very similar way on a Linux host PC Related Information e ARM DS 5 Altera Edition on page 6 1 For more information refer to the ARM DS 5 Altera Edition section e ARM DS 5 Documentation The ARM DS 5 Altera Edition reference material can be accessed online on the documen
90. icense Manager to obtain and add licenses You can open the ARM License Manager at any time from the Eclipse Help menu Ignore Open License Manager 2 Ifatany time itis required to change the license select Help gt ARM License Manager to open the License Manager Altera Corporation Licensing GJ Send Feedback Activating the License 4 3 Figure 4 2 Accessing ARM License Manager ith File Edit Source Refactor Navigate Search Project Run Window mi O Qv HEAO Help Contents v Gr amp v E7 v i Welcome z z ng BP Search Ww Streamlin Dynamic Help Key Assist Ctrl Shift L Tips and Tricks Cheat Sheets Check for Updates Install New Software El Problem 2 ARM License Manager 0 items ARM Extras Description About ARM DS 5 About Eclipse Platform 0 items selected 3 The License Manager View and edit licenses dialog box opens and shows that a license is not available Click the Add License button Figure 4 3 ARM License Manager Licensing GJ Send Feedback View and edit licenses Add or delete licenses below Select a license to view more information about it Add License Delete License Select the toolkit that you intend to use No toolkits available Altera Corporation 4 4 Activating the License 4 In the Add License Obtain a new licenses dialog box select the type
91. ifies the path to the handoff files lt preloader settings dir gt bsp dir lt bsp dir gt No This option specifies the path where the BSP files are generated When this option is specified bsp create settings generates the BSP files after the settings file has been created Altera recommends that you specify this parameter with bsp create settings set lt name gt lt value gt No This option sets the BSP setting lt name gt to the value lt value gt Refer to BSP Settings for a complete list of available setting names and descriptions Related Information BSP Settings For a complete list of available setting names and descriptions refer toBSP Settings bsp query settings The bsp query settings tool queries the settings stored in BSP settings file as shown in the following example Setting values are sent to courier Example 8 4 Querying a PSP The following command will retrieve all the settings from settings bsp and displays the setting names and values bsp query settings settings settings bsp get all show names Altera Corporation HPS Preloader User Guide CJ Send Feedback 2013 05 03 bsp generate files 8 7 Table 8 3 User Parameters bsp query settings Prion rece scion settings lt settings file gt Yes This option specifies the path to an existing BSP settings file get lt name gt No This option instructs bsp query settings to return the value of the
92. information mkimage Usage mkimage 1 image 1 gt list image header information mkimage x A arch O os T type C comp a addr e ep n name d data_file data_file image A gt set architecture to arch O gt set operating system to os T gt set image type to type C gt set compression type comp a gt set load address to addr hex gt set entry point to ep hex Altera Corporation HPS Preloader User Guide CJ Send Feedback 2013 05 03 g mkimage Tool Image Creation 8 19 n gt set image name to name d gt use image data from datafile x gt set XIP execute in place mkimage D dtc_options f fit image its fit image mkimage V gt print version information and exit mkimage Tool Image Creation Example 8 7 Creating a U boot Image mkimage A arm T firmware C none 0O u boot a 0x08000040 e 0 n U Boot 2011 12 for SOCFGPA board d u boot bin u boot img Example 8 8 Creating a Bare metal Application Image mkimage A arm 0O u boot T standalone C none a 0x02100000 e 0 n baremetal image d hello_world bin hello_world img HPS Preloader User Guide Altera Corporation GJ Send Feedback Hardware Library Overview S subscribe _ Send Feedback The Altera SoC FPGA Hardware Library HWLIB was created to address the needs of low level software programmers who require full access to the configuration a
93. installation directory gt to denote the location where Altera tools are installed e lt SoC EDS installation directory gt to denote the location where SoC EDS is installed Installing the SoC EDS Perform the following steps to install the SoC EDS Tool Suite in a Windows based system 1 Download the latest installation program from the SoC Embedded Design Suite page of the Altera website Run the installer to open the Installing SoC Embedded Design Suite EDS dialog box Click Next to start the Setup Wizard Accept the license agreement Click Next Soe ws installed the Quartus II software Altera recommends you accept the default SoC EDS installation Accept the default installation directory or browse to another installation directory If you have previously directory to allow the Quartus II software and the SoC EDS Tool Suite to operate together Click Next The installer displays a summary of the installation Click Next to start the installation process The installer displays the installation progress ewe PNna The installer displays a separate dialog box with the progress of the component installation 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks
94. ion 3 Single or quad image decoding If an error is found during the make image process the tool stops and reports the error Possible error conditions include e The input image size is equal to or less than 80 bytes e The input image size is equal to or greater than 60 kilobytes KB mkpimage invokes the preloader image tool invoking the tool with the he1p option provides a tool description and tool usage and option information gt mkpimage help mkpimage version 13 1 build 154 2013 Altera Corporation Description This tool creates an Altera BootROM compatible image of Second HPS Preloader User Guide Altera Corporation CJ Send Feedback 2013 05 03 8 16 Output Image Layout Stage Boot Loader SSBL The input and output files are in binary format It can also decode and check the validity of previously generated image Usage Create quad image mkpimage option s o lt outfile gt lt infile gt lt infile gt lt infile gt lt infile gt Create single image mkpimage option s o lt outfile gt lt infile gt Decode single quad image mkpimage d a lt num gt lt infile gt Options a alignment lt num gt Address alignment in kilobytes valid value starts from 64 128 256 etc default to 64 override if the NAND flash has a larger block size d decode Flag to decode the header information from input file and display it f
95. kernel executable b Specify the symbols file Note This tab also shows the soft IP peripheral registers as described in ARM DS 5 AE soft IP Register Visibility section 5 Click on the Debugger and perform the following steps a Select option Connect Only for Run Control b Check Execute debugger commands check box c Add the debugger commands to stop cores and load image symbols for the Linux executable as shown in the following figure d Add the path to the Linux source files on the host machine to allow the debugger to locate them Getting Started Guides Altera Corporation CJ Send Feedback 5 34 Debugging the Kernel Figure 5 35 Debugger Settings Run control Connect only Debug from entry point Debug from symbol O Run target initialization debugger script ds py O Run debug initialization debugger script ds py Execute debugger commands interrupt A add symbol file nome radu altera 13 1 embedded embeddedsw socfpga prebuilt_images vmlinux Host working directory Use default Paths Source search directory home radu altera 13 1 embedded embeddedsw socfpga sources linux socfpgal File System Workspace 6 Click the Debug button The debugger connects to the board stops the cores as instructed and loads the kernel symbols It determines where the cores are stopped and highlights it in the source code The following figure shows the debugger
96. ketboards org The script downloads the sources corresponding to the pre built Linux package e SoC Hardware Library HWLIB 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at ISO www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with 9001 2008 Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes Registered no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JN DTE RYA 101 Innovation Drive San Jose CA 95134 1 2 Device Tree Binary Hardware to software interface utilities e Preloader generator e Device tree generator Sample applications Golden Hardware Reference Design GHRD including e FPGA hardware project e FPGA hardware SOF fil
97. lated Information SoC Embedded Design Suite For more information refer to the SoC Embedded Design Suite page on the Altera website Installing the ARM DS 5 Altera Edition Toolkit The ARM DS 5 Altera Edition Toolkit installer is started as the last step of the SoC EDS installation process 1 A Welcome message is displayed Click Next 2 Accept the license agreement Click Next 3 Accept the default installation path to ensure proper interoperability between SoC EDS and ARM DS 5 AE Click Next Click Install to start the installation process A progress bar is displayed A separate driver installation window is opened Click Next Accept the driver installation and Click Install Drivers are installed successfully Click Finish ARM DS 5 AE installation is completed Click Finish SONA uM Bb Installing USB Serial Drivers The Altera SoC development boards have dedicated devices that convert the RS232 to USB The host machine requires dedicated drivers to use this feature Recent Linux distributions already have the necessary drivers included The Windows version of the SoC EDS Installer comes with the necessary driver package in lt SoC EDS installation directory gt drivers ftdi CDM20830_Setup exe Run CDM20830_Setup exe Windows will install the drivers automatically when the USB cable is inserted Related Information Installing the SoC EDS on page 2 1 For more information refer to the Installing the So
98. line HTML accessible from any web browser The locations of the online SoC FPGA Hardware Library HWLIB Reference Documentation are e SoC Abstraction Layer SoCAL API Reference Documentation lt SoC EDS installation directory gt ip altera hps altera_hps doc socal html index html e Hardware Manager HW Manager API Reference Documentation lt SoC EDS installation directory gt ip altera hps altera_hps doc hwmgr html index html Hardware Library Overview Altera Corporation GJ Send Feedback HPS Flash Programmer User Guide 1 0 2013 05 03 C lt Subscribe GJ Send Feedback The Altera Quartus II software and Quartus II Programmer include the hardware processor system HPS flash programmer Hardware designs such as HPS incorporate flash memory on the board to store FPGA configuration data or HPS program data The HPS flash programmer programs the data into a flash memory device connected to an Altera SoC The programmer sends file contents over an Altera download cable such as the USB Blaster II to the HPS and instructs the HPS to write the data to the flash memory The HPS flash programmer programs the following content types to flash memory e HPS software executable files Many systems use flash memory to store non volatile program code or firmware HPS systems can boot from flash memory Note The HPS Flash Programmer is mainly intended to be used for programming the Preloader Image to QSPI or NAND Flash Due to the low
99. llowing a Rename the configuration to DebugLinux_DevKit using the Name edit box Altera Corporation Getting Started Guides CJ Send Feedback Debugging the Kernel 5 33 b Select the Target to be Altera gt CycloneVSoC gt Linux Kernel and or Device Driver Debug gt Debug Cortex A9x2 SMP via Altera USB Blaster c Click the Browse button near the Connection edit box and select the desired USB Blaster instance Figure 5 34 Configure Connection lt gt Connection gt Files Debugger OS Awareness Arguments F Environment Select target Select the manufacturer board project type and debug operation to use Currently selected Altera Cyclone V SoC Linux Kernel and or Device Driver Debug Debug Cortex A9x2 SMP via Altera U a Vv cycione v sou gt Bare Metal Debug Linux Application Debug v Linux Kernel and or Device Driver Debug Debug Cortex A9_0 via Altera USB Blaster Debug Cortex A9_0 via DSTREAM RVI Debug Cortex A9_1 via Altera USB Blaster Debug Cortex A9_1 via DSTREAM RVI Debug Cortex A9x2 SMP via Altera USB Blaster DTSL Options Edit Configure trace or other target options Using default configuration options DS 5 Debugger will connect to an Altera USB Blaster to debug a SMP Linux kernel Connections Connection USB Blasteril on localhost 1 1 3 USB Blasteril 1 1 3 Linux Kernel Debug 4 Click the Files tab a Specify the Linux
100. ming from FPGA to HPS e Enable HPS gt FPGA Cross Trigger for enabling triggers coming from HPS to FPGA e Assume Cross Triggers can be accessed the user needs to select this option as a confirmation that the Preloader was already loaded so the DS 5 can access the cross triggering interface Altera Corporation ARM DS 5 Altera Edition J Send Feedback DTSL Options 6 15 Figure 6 15 DTSL Configuration Editor Cross Trigger Debug and Trace Services Layer DTSL Configuration Add edit or choose a DTSL configuration for file dts _config_script py class DSTREAM_DtsIScript B X Name of configuration default CE Cross Trigger gt Trace Buffer Cortex A9 STM ETR ETF Z Enable FPGA gt HPS Cross Trigger Z Enable HPS gt FPGA Cross Trigger Cross Trigger initialization The Cross Trigger interface can only be accessed if the system clocks have been initialized If the Cross Trigger interface is accessed prior to the clock initialization then the target may lock up The folllowing option should only be set if you are sure that the system clocks have been initialized prior to DS 5 connecting to the target system The system clocks are typically set up by running the Altera preloader script Assume Cross Triggers can be accessed Apply Trace Buffer Settings The Trace Buffer tab allows the selection of the destination of the trace information As mentioned in the introduction the destin
101. mple Application 5 17 7 Click Continue green button or press F8 to run the application It displays a log of activities it performs in the Application Console Figure 5 16 Application Completed 53 Target Console 9 Error Log amp fa ie BBY amp Linked Altera SoCFPGA HardwareLib FPGA CV GNU Debug 7 INFO INFO INFO INFO INFO INFO INFO INFO INFO INFO INFO INFO INFO INFO INFO INFO INFO RESULT Example com Gray Gray Gray Gray Gray Gray Gray Gray Gray Gray Gray Gray Gray LEDs code i x3 gt x2 0010 code i x4 gt x6 0110 code i x5 gt x7 111 code i x6 gt x5 0101 code i x7 gt x4 0100 code i x8 gt xc 1100 code i x9 gt xd 1101 code i xa gt xf 1111 code i xb gt xe 1110 code i xc gt xa 1010 code i xd gt xb 1011 code i xe gt x9 1001 code i xf gt x8 1000 should have blinked Cleanup of Bridge 2 Cleanup of FPGA Cleaning up DMA System leted successfully 8 Click Disconnect from Target button to close the debugging session Sequence Sample Application Used Hardware Libraries Description Function APIs alt_dma_init Init DMA module driver 2 alt_dma_channel_ Allocate DMA channel socfpga_dma_setup alloc_any 3 alt_dma_channel_ Check state of DMA channel state_get 4 alt_fpga_init Init
102. n soft IP FPGA programming and bridge releasing are not required before Linux starts running using this DTB This bare bones DTB is intended for customers interested in bringing up a new board or just wanting to simplify their boot flow until they get to the Linux prompt If what is being developed or debugged does not involve the FPGA it s better to remove the FPGA complexities lt SoC EDS Installation directory gt examples hardware cv_soc_devkit_ghrd soc_system dtb This DTB is based on Golden Hardware Reference Design GHRD design which is part of the GSRD Golden System Reference Design As the GHRD does contain soft IPs this DTB will notify Linux to load the soft IPs drivers Therefore the FPGA needs to be programmed and the bridges released before booting Linux Altera Corporation Introduction to SoC Embedded Design Suite CJ Send Feedback Hardware Software Development Roles 1 3 Related Information Rocketboards website For more information about the GSRD refer to the Rocketboards website Hardware Software Development Roles Depending on your role in hardware or software development you need a different subset of the SoC EDS toolkit The following table lists some typical engineering development roles and indicates which tools each role typically requires Table 1 1 Hardware Software Development Roles Tool Hardware Bare Metal RTOS Developer Linux Kernel and Linux Application Engineer Developer Driver Developer
103. nce Design GHRD that is provided with SoC EDS The Preloader is an essential tool for SoC software It performs the low level initialization brings up SDRAM memory loads the next boot stage from flash to SDRAM and executes it The Preloader is already delivered as part of the GHRD in the lt SoC EDS installation directory gt examples hardware cv_soc_devkit_ghrd software preloader folder Getting Started Guides Altera Corporation CJ Send Feedback 5 4 Getting Started with Preloader In this example you will re create the Preloader in the folder lt SoC EDS installation directory gt examples hardware cv_soc_devkit_ghrd software spl_bsp The screen snapshots presented in this section were created using the Windows version of SoC EDS but the example can be run in a very similar way on a Linux host PC The steps to create the Preloader are 1 Start an Embedded Command Shell by executing lt SoC EDS installation directory gt Embedded_Command_ Shell bat 2 Run the command bsp editor The BSP Editor dialog box appears Note The tool that generates a preloader support package is the BSP Editor also used to generate BSPs for other Altera products 3 Select File gt New BSP The New BSP dialog opens 4 Clickthe button to browse for the Preloader settings directory in the New BSP dialog box 5 Browse lt SoCEDS folder gt examples hardware cv_soc_devkit_ghrd hps_isw_handoff soc_system_hps_0 for the hardware handoff
104. nd control facilities of SoC FPGA hardware An additional purpose of the HWLIB is to mitigate the complexities of managing the operation of a sophisticated multi core application processor and its integration with hardened IP peripheral blocks and programmable logic in a SoC architecture Figure 9 1 HW Library SoC FPGA Hardware Hardware Library Within the context of the SoC HW SW ecosystem the HWLIB is capable of supporting software development in conjunction with full featured operating systems or standalone bare metal programming environments The relationship of the HWLIB within a complete SoC HW SW environment is illustrated in the above figure The HWLIB provides a symbolic register abstraction layer known as the SoCAL that enables direct access and control of HPS device registers within the address space This layer is a necessary enabler for several key stakeholders boot loader developers driver developers board support package developers debug agent developers board bring up engineers requiring a precise degree of access and control of the hardware resources The HWLIB also deploys a set of Hardware Manager HW Manager APIs that provides more complex functionality and drivers for higher level use case scenarios The HWLIB has been developed as a source code distribution The intent of this model is to provide a useful set of out of the box functionality and to serve as a source code reference implementation that a user can
105. nfiguration JTAG ready x Instance Status LEs 587 g 587 cells Memory 102 Small NA Medium NA 10240 bits NA Hardware USB Blasterll 1 1 3 3 A Setup Device 2 SCSEBAG ES SCSEM gt Scan Chain gt gt SOF Manager amp a files soc_system sof trigger 2013 09 06 17 49 21 0 Lock mode amp Allow trigger ct signal Configuration x Node Data Enable Trigger Enable Jager Conditio Type Alias Name i fpga_dipsw_pio 0 4 fpga_dipsw_pio 1 fpga_dipsw_pio 2 fpga_dipsw_pio 3 g fpga_led_pio 0 X X xX fpga_led_piof1 fpga_led_pio 2 fpga_led_pio 3 inst data_out 0 inst data_out 1 A Data z3 Setup amp auto_signaltap_O Related Information 10 10 p z Ei Trigger a Trigger flow control Trigger position Pre trigger position o o o Trigger conditions 0 00 00 00 Getting Started with Running Linux on page 5 2 For more information refer to the Getting Started with Running Linux section in this document FPGA Triggering HPS Example This section presents an example on how FPGA can trigger HPS to stop the execution This can be useful if you want to see what the HPS is doing at the moment the trigger comes from FPGA The required steps are to reproduce this scenario are 1 Perform the steps from the Cross triggering Prerequisite
106. nfiguration and edit DTSL options to enable FPGA cross triggering HPS as shown in the Enabling Cross triggering on HPS section a Un check the Enable FPGA gt HPS Cross Triggering check box b Check the Enable HPS gt FPGA Cross Triggering check box if checked c Check the Assume Cross Triggers can be accessed check box 3 Start the debug session by clicking Debug in the Debug Configuration dialog box The debugger will stop the Linux kernel and display the current HPS state 4 In Signal Tap II make sure all trigger signals are disabled by setting their condition to Don t care Figure 5 60 Trigger Signals Disabled trigger 2013 09 06 17 49 21 0 Lock mode amp Allow trigger cc Node Data Enable Trigger Enable Jager Condit Type Name 10 10 1v ZS k fpga_dipsw_pio 0 fpga_dipsw_pio 1 fpga_dipsw_pio 2 fpga_dipsw_pio 3 fpga_led_pio 0 fpga_led_pio 1 fpga_led_pio 2 fpga_led_pio 3 inst data_out 0 inst data_out 1 5 In Signal Tap II configure the Trigger in to be sensitive to both edges so that the SignalTap II sends the trigger to HPS whenever it performs an acquisition Getting Started Guides Altera Corporation CJ Send Feedback 5 50 HPS Triggering FPGA Example Figure 5 61 Configure Trigger in J Pin Node ls Instance 4 gt Hard Processor System HPS trigger out Pattern X Either Edge 4 gt 6 In Eclipsedebugger let the Linux kernel c
107. ol can also decode the header of previously generated images The preloader image tool makes the following assumptions 1 The input file format is raw binary You must use the ob jcopy utility provided with the GNU Compiler Collection GCC tool chain from the Mentor Graphics website www mentor com to convert other file formats such as Executable and Linking Format File elf Hexadecimal Intel Format File hex or S Record File srec to a binary format The output file format is binary 2 The preloader image tool always creates the output image at the beginning of the binary file If the image must be programmed at a specific base address you must supply the address information to the flash programming tool 3 The output file contains only preloader images Other images such as Linux SRAM Object File sof and user data are programmed separately using a flash programming tool or related utilities in the U boot on the target system Related Information Mentor Graphics For more information about the GNU Compiler Collection GCC toolchain refer to the Mentor Graphics website Operation of the Preloader Image Tool The preloader image tool runs on a host machine The tool generates the header and CRC checksum and inserts them into the final preloader image with the preloader program image and preloader exception vector For certain flash memory tools the position of the preloader images must be aligned to a specific block
108. omponents Total time taken 2 seconds Searching for BSP components with category os_software_element m aj 7 Click Generate in the BSP Editor dialog box to generate the Preloader files 8 Click Fxit in the BSP Editor dialog box to exit the application 9 In the Embedded Command Shell execute the following commands e cd lt SoC EDS installation directory gt examples hardware cv_soc_devkit_ghrd software spl_bsp e make 10 The Preloader is ready to be used in the above folder Some of the more relevant files that are created preloader mkpimage bin Preloader with the proper header to be loaded by BootROM uboot socfpga spl u boot spl Preloader ELF file to be used for debugging purposes uboot socfpga tools mkimage exe Utility to add the header needed by the Preloader to recognize the next boot stage Related Information e Preloader For more information about the Preloader refer to the Preloader section Getting Started Guides Altera Corporation GJ Send Feedback 5 6 Getting Started with Bare Metal Debugging e Booting and Configuration For more information about Booting and Configuration with regards to Preloader refer to the Booting and Configuration appendix in volume 3 of the Cyclone V Device Handbook Booting and Configuration For more information about Booting and Configuration with regards to Preloader refer to the Booting and Configuration appendix in volume 3 of the Arr
109. ontinue running by pressing the green Continue button or pressing F8 7 In SignalTap II press the Run Analysis button to arm Signal Tap Figure 5 62 Run Analysis Instance Manager Pa 6 4 j8 Ready to acquire x Instance Status Run Analysis p87 Memory 102 Small NA Medium NA auto Not running 37 cells 10240 bits NA 8 SignalTap II will run the analysis and wait for the trigger from HPS Figure 5 63 Acquisition in Progress instance Manager x TT O Instance Status LEs 587 Memory 102 Small NA Medium NA auto_ Waiting for 587 cells 10240 bits NA 9 In Eclipse debugger click the Interrupt button or press F9 This will stop the cores and send the trigger to FPGA 10 SignalTap II will detect the trigger from HPS perform an acquisition and stop This will be indicated by the status changing back to Ready to acquire Related Information e ARM DS 5 Altera Edition on page 6 1 For more information refer to the ARM DS 5 Altera Edition section Altera Corporation Getting Started Guides CJ Send Feedback HPS Triggering FPGA Example 5 51 e Cyclone V Coresight Debug and Trace For more information about Tracing refer to the Coresight Debug and Trace section in volume 3 of the Cycone V Device Handbook ARM DS 5 Documentation The ARM DS 5 Altera Edition reference material can be accessed online on the documentation page of the ARM website ww
110. oot hello created Listening on port 5000 Debug session has been started co Remote debugging from host 137 57 Hello SoC FPGA Child exited with status 0 Getting Started with Linux Kernel and Driver Debugging The ARM DS 5 Altera Edition provides very powerful Linux Kernel and Driver debugging capabilities This section presents an example on of how to debug the Linux kernel and drivers using DS 5 The software engineers can use the dedicated Linux debugging features presented in this section together with the basic debugging features such as viewing registers inspecting variables and setting breakpoints Note In the scenario presented here the Linux kernel is already running on the board but it can also be downloaded through the debugger Note This scenario uses the pre built Linux images and Linux source code included in the SoC EDS These are examples only use the latest sources from the Rocketboards website www rocketboards org for development Note This section uses a Linux host computer as can be seen from the screenshots and the issued commands However the scenario can also be run on a Windows machine although it is not usual for Linux development to be done on Windows Note The paths presented in this section assume the default installation paths were used Adjust accordingly if non standard location is used Related Information e ARM DS 5 Altera Edition on page 6 1 For more information refer to the ARM
111. ordance with 9001 2008 Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes Registered no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JN DTE RYA 101 Innovation Drive San Jose CA 95134
112. pga with the user specified cross compiler specified in the BSP settings and stores the generated preloader binary files in lt bsp directory gt uboot socfpga spl Converts the preloader binary file to a preloader image lt bsp directory gt preloader mkpimage bin with the mkpimage tool The mkpimage tool is part of the preloader image tool It inserts the correct header information and creates an Altera boot ROM compatible image of the preloader You can run the make utility in the command shell to compile the preloader in the BSP directory The makefile contains the following targets make all compiles the preloader make clean deletes preloader mkpimage bin from lt bsp_directory gt make clean all deletes lt bsp directory gt including the source files in the directory Configuring FPGA with Image from QSPI Flash The Preloader has the ability to configure the FPGA by using a configuration file stored in QSPI Flash In order to use this feature the following steps need to be performed 1 A WwW CNA UW Configure the Preloader load the next boot stage from QSPI Next boot stage image has to reside in QSPI Flash in this case Generate Preloader Compile Preloader to make sure all the source code is available Modify file uboot socfpga include configs socfpga_common h to have the macro CONFIG_SPL_FPGA_LOAD defined It is undefined by default Recompile Preloader Convert SOF file to RBF using Quartus Programm
113. pport package Click Exit to exit the preloader support package generator Using tcl Scripts Instead of using the default settings you can create a tcl script file tcl to define custom settings during BSP creation HPS Preloader User Guide Altera Corporation CJ Send Feedback 2013 05 03 8 4 Preloader Support Package Files and Folders set_setting is the only available tcl command Refer to BSP Settings for a list of available settings Example 8 1 Valid tcl Scripting Commands for Changing BSP Settings The following commands are used to set parameters n the BSP setings file set_setting spl boot set_setting spl boot BOOT_FROM_QOSPI true OSPI_NEXT_BOOT_IMAGE 0x50000 Preloader Support Package Files and Folders The files and folders created with the preloader support package are stored in the location you specified in BSP target directory in the New BSP dialog box Figure 8 3 PSP Directory bsp_directory og settings bsp Makefile Le generated The BSP files include e settings bsp the settings file containing all BSP settings e Makefile the makefile to create the preloader image for more information refer to Preloader Compilation e generated this folder contains files generated from the hardware handoff files from the Qsys system integration tool Command Line Tools for the Preloader Support Package Generato
114. pse the soft IP register group to avoid the debugger accessing them on the next debugging session before they are accessible 14 Click Disconnect from Target button to close the debugging session Note Do not try to access the soft IP registers before the FPGA is programmed or before the bridges are open Otherwise the debugger will generate a memory access abort and the debugging session will fail This includes having any soft IP registers groups expanded in the Registers dialog box The debugger will try to access them in order to refresh the view and it will generate a memory access abort if they are not accessible Always collapse the soft IP register view after usage if there is any chance they will not be available to the debugger Related Information e Getting Started with the Hardware Library on page 5 11 For more information refer to the Getting Started with the Hardware Library section e ARM DS 5 Documentation The ARM DS 5 Altera Edition reference material can be accessed online on the documentation page of the ARM website www arm com and from Eclipse by navigating to Help gt Help Contents gt ARM DS 5 Documentation Getting Started with Linux Application Debugging The ARM DS 5 Altera Edition provides very powerful Linux application debugging capabilities This section presents running the ARM DS 5 Altera Edition for the first time importing compiling and running the Hello World Linux example application provided as p
115. r The BSP command line tools can be invoked from the embedded command shell and provide all the features available in the preloader support package generator e The bsp create settings tool creates a new BSP settings file e The bsp update settings tool updates an existing BSP settings file e The bsp query settings tool reports the setting values in an existing BSP settings file e The bsp generate files tool generates a BSP from the BSP settings file Note Help for each tool is available from the embedded command shell To display help type the following command lt name of tool gt help bsp create settings The bsp create settings tool creates a new PSP settings file with default settings You have the option to modify the BSP settings or generate the PSP files as shown in the following example Altera Corporation HPS Preloader User Guide CJ Send Feedback 2013 05 03 bsp update settings 8 5 Example 8 2 Creating a New PSP Settings File bsp create settings type spl bsp dir settings settings bsp preloader settings dir hps_isw_handoff lt hps_entity_name gt Table 8 1 User Parameters bsp create settings SD type lt bsp type gt Yes This option specifies the type of BSP spl is the only allowed PSP type for a SoC EDS PSP settings lt settilngs iile gt Yes This option specifies the path to a BSP settings file The file is created with default settings Altera recommends that
116. r account If you do not have an account it can be created easily by clicking the provided link After entering the account information Click Finish Figure 4 6 Add License Developer account details Enter the ARM developer Silver account details Enter account details GB Paltera com Forgot password Click here to reset your password Don t have an account Click here to create one TE Get a Note The License Manager needs to be able to connect to the Internet in order to activate the license If you do not have an Internet connection you will need to write down your Ethernet MAC address and generate the license directly from the ARM Self Service web page on the ARM website silver arm com then select the Already have a license option in the License Manger Note Only the Subscription Edition with an associated license number can be activated this way The Web Edition and Evaluation edition are based on activation codes and these codes cannot be used on the ARM Self Service web page on the ARM website silver arm com They need to be entered directly in the License Manager which means an Internet connection is a requirement for licensing The ARM License Manager uses the Eclipse settings to connect to the Internet The default Eclipse settings is to use the system wide configuration for accessing the Internet In case the License Manager cannot connect to the Internet you can try to change the Proxy se
117. reLib GNU Emine Includes Build Working Set hwib c E Altera SoCFPGA HardwareLib GN J Build Automatically altera socfpga hosted ld B debug hosted ds Make Target Makefile An outline is not available Properties ER Problems 53 Tasks g eae E Properties p 0 items a Description Resource 6 Ifthe compilation tools issue errors Eclipse parses and formats them for you Debugging ARM DS 5 AE offers you a variety of debugging features The settings for a debugging session are stored in a Debug Configuration The Debug Configurations window is accessible from the Run gt Debug Configurations menu Altera Corporation ARM DS 5 Altera Edition J Send Feedback Figure 6 4 Accessing Debug Configurations Debugging 6 5 File Edit Source B S Er Sgr l 97 W Streamline Data B i 4 cS Altera SoCFPGA HelloWorld Baremetal GNU hello c hello o arm le Altera SoCFPGA HelloWorld Baremetal Debug lau altera socfpga hosted Id hello axf hello axf map hello axf objdump Makefile B semihost_setup ds g iS Altera SoCFPGA HelloWorld Baremetal GN Refactor Navigate Search Project Window Help Set Next Statement Q Run Debug Run History Run As Ctrl Alt R Ctrl F11 Run Configurations Debug History Debug As Debug Configurations Toggle Breakpoint Ct
118. reference material can be accessed online on the documentation page of the ARM website www arm com and from Eclipse by navigating to Help gt Help Contents gt ARM DS 5 Documentation Enabling Cross triggering on HPS 1 Cross triggering can be enabled in the DTSL dialog box which can be accessed from the Connection tab of the Debug Configuration Getting Started Guides Altera Corporation CJ Send Feedback 5 42 Enabling Cross triggering on HPS Figure 5 45 se Connection far Files 4 Debugger i OS Awareness Arguments PS Environment 7 Select the manufacturer board project type and debug operation to use Currently selected Altera Cyclone V SoC Linux Kernel and or Device Driver Debug Debug Cortex A9x2 SMP via Altera L SS a v Linux Kernel and or Device Driver Debug Debug Cortex A9_0 via Altera USB Blaster Debug Cortex A9_0 via DSTREAM RVI Debug Cortex A9_1 via Altera USB Blaster Debug Cortex A9_1 via DSTREAM RVI Nahin Cartav AQv CMD wis NCTREAMIRAVI Debug Cortex A9x2 SMP via Altera USB Blaster DS 5 Debugger will connect to an Altera USB Blaster to debug a SMP Linux kernel DTSL Options Configure trace or other target options Using default configuration options 2 The Cross Trigger tab of the DTSL Configuration Editor allows Cross trigger configuration Figure 5 46 HPS Cross Trigger Configuration Cross Trigger gt Trace Buffer Cortex A9 STM ETR ETF O Enabl
119. rl Shift B Toggle Line Breakpoint Toggle Method Breakpoint Toggle Watchpoint W Skip All Breakpoints Remove All Breakpoints Breakpoint Types Manage Python Exception Breakpoints Q External Tools A Debug Configuration is created in the Debug Configurations window by selecting DS 5 Debugger as the type of configuration in the left panel and then right click and select the New menu option ARM DS 5 Altera Edition GJ Send Feedback Altera Corporation 6 6 Debugging Figure 6 5 Creating a Debug Configuration Create manage and run configurations Create edit or choose a configuration to launch a DS 5 debugging session CY p Configure launch settings from this dialog type filter text Press the New button to create a configuration of the selected type E C C Application B Press the Duplicate button to copy the selected configuration E C C Attach to Ap E C C Postmortem E C C Remote App _ DS 5 Debug Press the Delete button to remove the selected configuration 2 Iron Pythor Duplicate E Java Applet Delete launch perspective settings from the Perspectives preference page D Java Application Ju JUnit 2 Jython run 2 Jython unittest m Filter matched 18 of 18 items Deb The Eclipse IDE assigns a default name to the configuration which can then be edited by you Altera Corporation ARM DS 5 Altera Edition CJ S
120. s Name SampleConfiguration ior Files Bs Debugger ey RTOS Awareness Arguments B Environment G3 Event Viewer aor Target Configuration Application on host to download File System Workspace _ Load symbols Files Load symbols from file Add peripheral description files from directory 4 gt Apply Revert Debug The Debugger tab offers the following configurable options e Run Control Options Option to connect only debug from entry point or debug from user defined symbol Option to run user specified target initialization script Option to run user specified debug initialization script Option to execute user defined debugger commands e Host working directory used by semihosting e Paths allows you to enter multiple paths for the debugger to search for sources Paths can be added with button and removed with button Altera Corporation ARM DS 5 Altera Edition J Send Feedback Debug Configuration Options 6 11 Figure 6 9 Debug Configurations Debugger Create manage and run configurations Connection Configuration for connection type Bare Metal Debug is not valid Connection cannot be empty Geax Anez Name SampleConfiguration gt type filter text Files Z Debugger E RTOS Awareness Arguments Environment EJ Event Viewer 1 fe C C Applicatio fe C C Attach to 4 fe C C Postmorte fe C C Remote Aj 3 DS 5 Debugg
121. s e g Pin Assignments User Inputs pp Preloader Preloader support Support package settings Package Generator Generate Preloader Preloader Source Support Code Package Make Preloader Image Altera Corporation HPS Preloader User Guide CJ Send Feedback 2013 05 03 Hardware Handoff Files 8 3 Hardware Handoff Files Use the Qsys system integration tool in the Quartus II software to generate a set of handoff files containing the hardware information required by the preloader The handoff files from the Qsys compilation are located in the lt quartus project directory gt hps_isw_handoff lt hps entity name gt directory where hps entity name is the HPS component name in Qsys Note You must update the hardware handoff files and regenerate the preloader support package each time a hardeare change impacts the HPS such as after pin multiplexing or pin assignment Using the Preloader Support Package Generator GUI You must perform the following steps to use the preloader support package generator GUI bsp editor 1 6 7 Start an embedded command shell as follows e Ona Windows based system run the batch file lt SoC EDS installation directory gt Embedded_Command_Shell bat e Ona Linux based system run the shell script lt SoC EDS installation directory gt embedded_command_shell sh Run the bsp editor command in the embedded command shell to launch the preloader support package generator To open an
122. s no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JN DTE RYA ISO 9001 2008 Registered 101 Innovation Drive San Jose CA 95134 5 2 Dip Switch Settings Dip Switch Settings e SW1 all switches OFF e SW2 all switches OFF e SW3 ON OFF OFF OFF ON ON This selects the proper FPGA configuration option MSEL e SW4 OFF OFF ON ON This selects both HPS and FPGA to be in the JTAG scan chain Jumper Settings J5 9V Open J6 JTAG_HPS_SEL Shorted J8 JTAG_SEL Shorted J9 UART Signals Open J13 OSC1_CLK_SEL Shorted J15 JTAG_MIC_SEL Open J26 CLKSELO 2 3 Shorted J27 CLKSEL1 2 3 Shorted J28 BOOTSELO 2 3 Shorted J29 BOOTSEL1 2 3 Shorted J30 BOOTSEL2 1 2 Shorted J31 SPI_I2C Open Getting Started with Running Linux This section presents how to run the provided Linux image on the board to be able to run the Getting Started sections related to Linux Note The provided Linux image is an example only use the latest version from the Rocketboards website www rocketboards org for your development Altera Corporation Getting Started Guides GJ Send Feedback Getting Started with Preloa
123. s are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JN DTE RYA ISO 9001 2008 Registered 101 Innovation Drive San Jose CA 95134 Yocto Plugin 1 2 S Subscribe C3 Send Feedback The Yocto Linux Source Package available on the Yocto Project website www yoctoproject org allows the entire Linux software stack Kernel drivers device tree root file system targeting the SoC to be built in a very simple and convenient way The Yocto Eclipse plugin fulfills the need of the application developers to be able to target the Linux software stack without requiring them to learn the details on how to build the system This enables the developers to focus on what they know best developing applications The Yocto Eclipse plugin is installed on top of the ARM DS 5 Altera Edition Documentation on how to install and
124. s section 2 Open the Debugger configuration and edit DTSL options to enable FPGA cross triggering HPS as shown in the Enabling Cross triggering on HPS section a Check the Enable FPGA gt HPS Cross Triggering check box b Un check the Enable HPS gt FPGA Cross Triggering check box if checked c Check the Assume Cross Triggers can be accessed check box 3 Start the debug session by clicking Debug in the Debug Configuration dialog box The debugger will stop the Linux kernel and display the current HPS state 4 In Signal Tap II configure a trigger on the fpga_dispw_pio 0 signal to trigger at any edge by right clicking the corresponding cell in the Trigger Condition column Altera Corporation Getting Started Guides J Send Feedback FPGA Triggering HPS Example 5 47 Figure 5 54 Trigger on Dip Switch trigger 2013 09 06 17 49 21 0 Lock mode amp Allow trigger cc Node Bata Enable Trigger Enable Jager Conti Type aias Name EAE fpga_dipsw_pio 0 Don t Care fpga_dipsw_pioft tpga_dipsw_pioj2 2 Low tpga_dipsw_pioj3 Falling Edge al fpga_led_pio 0 Rising Edge fpga_led_pioft er ces fpga_led_pio 2 T High poa ea poe Ss inst data_out 0 inst data_out 1 gia sedaauk Pg 5 In Signal Tap II configure the Trigger out to be sent to HPS so that the SignalTap II sends the trigger to HPS w
125. sc svasdsvasicasssngsns abv dapvnaccnusnsovsasecncce enina 5 8 Getting Started with the Hardware Library csciiciiwncssinieasncessveasssasocsetossnstasaverseavagerwaianwacnsunssnavaecsenes 5 11 Altera Corporation Altera SoC Embedded Design Suite User Guide TOC 3 HWLIB Sample Application Overview ccsssssssssssececesssesesecssesesesesececseseseeeeecseseseeeeeseseeeeees 5 11 Statting th Edips MOE casas coneayetincencnasaiOvaatices ican eased asian etd essasi vieii E TOASA 5 12 Importing the Sample Application sse sssseseseessesessesesssrsssressressnresntesstrrsntressrresrreesreeesreesnreesnees 5 12 Compiling the Sample Application se sssseseseesssesssessesrssssssstessstesntesntresnrrssrrresreeesrreesreesreeeseees 5 14 Running the Sample Applicationsssaneneninnininniesininnnunaniananinn 5 15 Getting Started with Peripheral Register Visibility cisscsusssioisseassesastssatschssbcapessendindecludscessincesisaravdishonss 5 18 Getting Started with Linux Application DeDU gett g sssisssicssvansescanscadiacnercate qaviaswenustcaneeianssnesviseenensecnese 5 21 OR EA OR MIs A RE EEEa cen EEEE AE S DEERE SEERE ava Senda stage 5 22 Starting Eclipse via the Embedded Command Shell cesses ces eseeseseesesessesssseesseeseseeses 5 22 Importing the Sample Applicat Onissiscscicscasasexssnsvatavesavcasoveattvonnctsansasuseqasuanastasendsenmoassouvaaevedess 5 23 Compiling the Sample App cans sicccsussaslsausssecsaices witssosd nenssdeane lvasaae habsi
126. scribed herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services 101 Innovation Drive San Jose CA 95134 ISO 9001 2008 Registered JA DTE RYAN 6 2 Project Management 2 On Windows Eclipse can be started by selecting Start gt All Programs gt ARM DS 5 gt Eclipse for DS 5 On different Linux machines shortcuts may be created for starting Eclipse in a similar manner Project Management ARM DS 5 Altera Edition enables convenient project management using makefiles The sample projects that are provided with SoC EDS use makefiles to manage the build process In order to allow Eclipse to manage a makefile based project a project needs to be created 1 Create a folder on the disk For example we have created the folder c sample_project 2 Create the project by selecting File gt New gt Makefile Project with Existing Code Figure 6 1 Creating a Project with Existing Code Edit Source Refactor Navigate Search Project Run Window Help Alt Shift N gt c Makefile Project with Existing Code New Open Fil Close Close Al Save Save As Save All Revert Move le Rename Refresh Convert Line Delimiters To Print Switch Workspace Restart Import Export Properti Exit g es 0 items selected
127. se CA 95134 Device Tree Generator 1 3 S Subscribe CG3 Send Feedback A Device Tree is a data structure that describes the underlying hardware to an operating system primarily Linux By passing this data structure to the OS kernel a single OS binary may be able to support many variations of hardware This flexibility is particularly important when the hardware includes an FPGA The Device Tree Generator tool is part of Altera SoC EDS and is used to create device trees for SoC systems that contain FPGA designs created using Qsys The generated Device Tree describes the HPS peripherals selected FPGA Soft IP and also peripherals that are board dependent Related Information e Altera Wiki For more information about DTG refer to the Altera Wiki website e Device Tree Generator User Guide For more details refer to the Device Tree Generator User Guide located on the Device Tree Generator Documentation page on the Rocketboards website 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at ISO www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in acc
128. sents the preparation steps that are required in order to perform the cross triggering scenarios We boot the HPS start Signal Tap II and program the FPGA Note Any debugging scenario on HPS can be running as long as it uses a JTAG connection It does not necessarily have to be Linux It could be a bare metal program for example 1 Boot the board using the Linux SD card as shown in the Getting Started with Running Linux section 2 Connect USB cable from the USB Blaster II connection to the host PC 3 Open the Quartus SignalTap II program by running the command lt SoC EDS installation directory gt qprogrammer bin quartus_stpw This assumes you have accepted the default settings when installing SoC EDS 4 In Signal Tap II select File gt Open browse to lt SoC EDS Installation directory gt examples hardware cv_ soc_devkit_ghrd cti_tapping stp and click Open 5 In Signal Tap II on the JTAG Chain Configuration gt Hardware select the USB Blaster II Instance Figure 5 49 Select USB Blaster II Instance JTAG Chain Configuration device is selected x Hardware Please Select Setup USB Blasterll 1 1 3 3 Device Scan Chain amp Wj Files soc_system sof gt gt SOF Manager 6 In SignalTap II on the JTAG Chain Configuration gt Device select the FPGA device Altera Corporation Getting Started Guides I Send Feedback Cross triggering Prerequisites 5 45 Figure 5 50 Select FPGA device
129. size the preloader image tool generates any padding data that may be required Altera Corporation HPS Preloader User Guide CJ Send Feedback Tool Usage 8 15 The preloader image tool optionally decodes and validates header information when given a pre generated preloader image Figure 8 4 Basic Operation of the Preloader Image Tool Padding CRC Checksum Preloader Program CRC Checksum Preloader Program Empty Header Preloader Exception Vector Header Preloader Exception Vector 0x0000 As illustrated the binary preloader image is an input to the preloader image tool The compiler leaves an empty space between the preloader exception vector and the program The preloader image tool overwrites this empty region with header information and calculates a checksum for the whole image When necessary the preloader image tool appends the padding data to the output image The header includes e Validation word e Version field set to 0x0 e Flags field set to 0x0 e Program length measured by the number of 32 bit words in the preloader program e 16 bit checksum of the header contents 0x40 0x49 Figure 8 5 Header Format Simple Checksum Reserved 0x0 Program Length Flags Version Validation Word 0x31305341 0x48 0x44 0x40 Tool Usage The preloader image tool has three usage models 1 Single image creation 2 Quad image creat
130. specifies the maximum code text and rodata size that can fit within the FPGA If the code build is bigger than the specified size a build error is triggered spl boot FPGA_DATA_BASE Hexadecimal Oxffff0000 This setting specifies the base location for the data region data bss heap and stack when execute on FPGA is enabled text and rodata are default memory sections defined by the linker tool in the GCC tool chain data and bss are default memory sections defined by the linker tool in the GCC tool chain HPS Preloader User Guide Altera Corporation CJ Send Feedback 2013 05 03 8 12 BSP Settings spl boot FPGA_DATA_MAX__ Hexadecimal 0x10000 This setting specifies the SIZE maximum data data bss heap and stack size that can fit within FPGA If the code build is bigger than the specified size a build error is triggered spl debug DEBUG_MEMORY__ Hexadecimal Oxfffffd00 This setting specifies the base ADDR address for storing preloader debug information enabled with the sp1 debug DEBUG_ MEMORY_WRITE setting spl debug DEBUG_MEMORY__ Hexadecimal 0x200 This setting specifies the SIZE maximum size used for storing preloader debug information unique_80 unique_80_Connect_42_table_950CF11383D54E11A719D728E572F211 lists the available variations of the sp1 reset_assert lt peripheral_name gt setting with their default values Refer to unique_80 unique_80_Connec
131. speed of operation it is not recommended to be used for programming large files e FPGA configuration data At system power up the FPGA configuration controller on the board or HPS reads FPGA configuration data from the flash memory to program the FPGA The configuration controller or HPS may be able to choose between multiple FPGA configuration files stored in flash memory e Other arbitrary data files The HPS flash programmer programs a binary file to any location in a flash memory for any purpose For example a HPS program can use this data as a coefficient table or a sine lookup table The HPS flash programmer programs the following memory types e Quad serial peripheral interface QSPI Flash e ONFI Open NAND Flash Interface compliant NAND Flash HPS Flash Programmer Command Line Utilities You can run the HPS flash programmer directly from the command line For the Quartus II software the HPS flash programmer is located in lt Altera installation directory gt quartus bin For the Quartus II Programmer the HPS flash programmer is located in lt Altera installation directory gt qprogrammer bin 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the prop
132. t source type filter text 4 amp General Archive File E Existing Projects into Workspace G File System E Preferences 3 In the Import Projects dialog box select the Select Archive File option 4 Click Browse then navigate to lt SoC EDS installation directory gt embedded examples software select the file Altera SoCFPGA HelloWorld Baremetal GNU tar gz and click OK Getting Started Guides Altera Corporation CJ Send Feedback 5 24 Compiling the Sample Application Figure 5 22 Select Imported File Import Projects Select a directory to search for existing Eclipse projects Select root directory Select archive file HelloWorld Baremetal GNU tar gz Projects remetal GNU Altera SoCFPGA HelloWorld Baremetal GNU Copy projects into workspace Working sets E Add project to working sets Working sets Select Ne gt 5 Click Finish The project is imported The project files are displayed in the Project Explorer panel The following files are part of the project Table 5 3 Project Files SS a ieee ed hello c Sample application source code Makefile Makefile used to compile the sample application Compiling the Sample Application 1 To compile the application select the project in Project Explorer 2 Select Project gt Build Project 3 The project compiles and the Project Explorer shows the newly created hello
133. t_42_table_3B1A66707E3946F4B4FAAC146A63D9BB for a general description of the spl reset_assert lt peripheral_name gt setting Table 8 7 spl reset_assert lt peripheral_name gt BSP Setting Default Value spl reset_assert DMA False spl reset_assert FPGA_DMAO True spl reset_assert FPGA_DMA1 True spl reset_assert FPGA_DMA2 True spl reset_assert FPGA_DMA3 True spl reset_assert FPGA_DMA4 True spl reset_assert FPGA_DMA5 True spl reset_assert FPGA_DMA6 True spl reset_assert FPGA_DMA7 True spl reset_assert GPIOO0O False spl reset_assert GPIO1l False spl reset_assert GPIO2 False spl reset_assert L4WD1 False spl reset_assert OSC1TIMER1 False spl reset_assert SDR False Altera Corporation HPS Preloader User Guide J Send Feedback 2013 05 03 Preloader Compilation 8 13 BSP Setting Default Value spl reset_assert SPTIMERO False spl reset_assert SPTIMER1 False Preloader Compilation The makefile created by the PSP generator compiles the preloader sources and generates a preloader image The makefile performs the following tasks Copies the generic preloader source code into lt bsp_directory gt uboot socfpga Copies the generated BSP files and hardware handoff files to the source directory in lt bsp_directory gt uboot socfpga board altera socfpga_ lt device gt Configures the compiler tools to target an SoC FPGA Compiles the source files in lt bsp directory gt uboot socf
134. tation page of the ARM website www arm com and from Eclipse by navigating to Help gt Help Contents gt ARM DS 5 Documentation Starting the Eclipse IDE 1 Select Start Menu gt Programs gt ARM DS 5 gt Eclipse for DS 5 to start Eclipse Alternatively you can run eclipse command from the Embedded Command Shell 2 The Eclipse tool part of ARM DS 5 AE prompts for the workspace folder to be used Use the suggested folder and click OK 3 The ARM DS 5 AE Welcome screen appears It is instructive and can be used to access documentation tutorials and videos Altera Corporation Getting Started Guides CJ Send Feedback Importing the Sample Application Importing the Sample Application 5 7 1 In Eclipse select File gt Import The Import dialog box displays 2 In the Import dialog box select General gt Existing Projects into Workspace and click Next This will open the Import Projects dialog box Figure 5 4 Import Existing Project Select an import source type filter text Create new projects from an archive file or directory 4 General Archive File E Existing Projects into Workspace G File System E Preferences Finish 3 In the Import Projects dialog box select the Select Archive File option 4 Click Browse then navigate to lt SoC EDS installation directory gt embedded examples software select the file Altera SoCFPGA HelloWorld Linux GNU tar gz and click
135. the sof file to a compressed Raw Binary File rbf format with the quartus_cpf utility available in the Altera Complete Design Suite or the Quartus II software programmer 5 Converts the rbf to an equivalent Executable and Linking Format File elf object file with the GCC objcopy utility 6 Links the example program and the FPGA configuration resource object files into the HWLIB example executable file A debugger script performs the following steps to help execute the sample application 1 Loads the preloader image and places a breakpoint at the end of the image 2 Runs the preloader image until it reaches the breakpoint this properly configures the HPS component according to the GSRD 3 Loads the HWLIB sample application Related Information e Hardware Library Overview on page 9 1 For more information refer to the Hardware Libs Overview section in this document e Mentor Code Sourcery For more information about the Sourcery CodeBench Lite Edition including ARM GCC IDE refer to the Embedded Software page on the Mentor Graphics website e ARM DS 5 Documentation The ARM DS 5 Altera Edition reference material can be accessed online on the documentation page of the ARM website www arm com and from Eclipse by navigating to Help gt Help Contents gt ARM DS 5 Documentation Starting the Eclipse IDE 1 Select Start Menu gt Programs gt ARM DS 5 gt Eclipse for DS 5 to start Eclipse Alternatively you can run eclips
136. the ARM website www arm com and from Eclipse by navigating to Help gt Help Contents gt ARM DS 5 Documentation e Rocket Boards For more information about Linux refer to the Rocketboards website Altera Corporation Getting Started Guides CJ Send Feedback Getting Started with Cross Triggering 5 41 Getting Started with Cross Triggering The Altera SoC offers powerful cross triggering capability between the HPS and the FPGA fabric The HPS can trigger the FPGA and also the FPGA can trigger the HPS ARM has updated the DS 5 tool specifically for Altera to enable this SoC capability to be easily used This section presents an example of how cross triggering can be used The Golden Hardware Reference Design GHRD contains the necessary instrumentation to be able to use Quartus Signal Tap II tool to demonstrate cross triggering The Quartus Signal Tap II utility is an optional component of the SoC EDS installation and is selected by default Related Information e ARM DS 5 Documentation The ARM DS 5 Altera Edition reference material can be accessed online on the documentation page of the ARM website www arm com and from Eclipse by navigating to Help gt Help Contents gt ARM DS 5 Documentation e Cyclone V Coresight Debug and Trace For more information about Cross Triggering refer to the Coresight Debug and Trace section in volume 3 of the Cycone V Device Handbook e ARM DS 5 Documentation The ARM DS 5 Altera Edition
137. the Cyclone V Device Handbook HPS Configuration The preloader performs the following steps to configure the HPS and load the next image in the boot process 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at ISO www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with 9001 2008 Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes Registered no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JAN D E RYA 101 Innovation Drive San Jose CA 95134 8 2 Preloader Support Package Generator ict Configures the HPS pins I O configuration shift register IOCSR and pin multiplexing Configures the HPS phase locked loops PLLs and clocking Configures t
138. the Preloader The svd file contains the description of the registers of the HPS peripheral registers and registers for soft IP components in the FPGA portion of the SoC This file is used by the ARM DS 5 Debugger to allow these registers to be inspected and modified by the user SOPC Information sopcinfo file containing a description of the entire system is used by the Device Tree Generator to create the Device Tree used by the Linux kernel Note The soft IP register descriptions are not generated for all soft IP cores Related Information e HPS Preloader User Guide on page 8 1 For more information refer to the HPS Preloader User Guide e Device Tree Generator on page 13 1 For more information refer to the Device Tree Generator section Introduction to SoC Embedded Design Suite Altera Corporation CJ Send Feedback Installing the Altera SoC Embedded Design Suite S Subscribe Cj Send Feedback You must install the Altera SoC Embedded Design Suite EDS and the ARM Development Studio 5 DS 5 Altera Edition Toolkit to run the SoC EDS on an Altera SoC hardware platform Installation Folders The default installation folder for SoC EDS is e c altera 13 1 embedded on Windows e altera 13 1 embedded on Linux The default installation folder for Quartus Programmer is e c altera 13 1 qprogrammer on Windows e altera 13 1 qprogrammer on Linux Throughout this document the following are used e lt Altera
139. the Remote Systems panel click the Target IP gt Sftp Files gt Root This opens a dialog box to enter the username and password Figure 5 27 Browse Target wRe za Ta CO 7 8 Zj v Ef Local gt 78 Local Files f Local Shells v Ek 137 57 160 214 v 4 Sftp Files gt gt My Home FX Ssh Shells Ssh Terminals ae gt 7 Enter root as the username and the password you have selected in the Configuring Linux section Check the Save User ID and Save password check boxes Click OK Getting Started Guides Altera Corporation CJ Send Feedback 5 28 Running Sample Application Figure 5 28 Target Username and Password Enter Password System type SSH Only Host name 137 57 160 214 User ID root Password optional Save user ID W Save password Cancel OK 8 Eclipse asks for confirmation of authenticity of the board Click Yes 9 Remote System Explorer shows the files on the DevKit board on the left panel Figure 5 29 Target Files wij Remote Syste X Team 7E v 2 3 gt v f 137 57 160 214 v 4 Sftp Files gt p My Home v Root v amp tin v boot B vmlinux 3 9 0 zimage B zZimage 3 9 0 gt dev gt etc nan w ey ER Running Sample Application At this stage we have a compiled Linux application and a properly configured Remote Systems Connection This section shows how to create a Debugger Configuration and use it
140. the file name of the application to be downloaded to the target It can be entered directly in the edit box or it can be browsed for in the Workspace or on the File System e Files contains a set of files A file can be added to the set using the button and files can be removed from the set using the button Each file can be one of the following two types e Load symbols from file the debugger uses that file to load symbols from it e Add peripheral description files from directory the debugger to load peripheral register descriptions from the SVD files stored in that directory The SVD file is a result of the compilation of the hardware project ARM DS 5 Altera Edition Altera Corporation CJ Send Feedback 6 10 Debug Configuration Options Figure 6 8 Debug Configurations File options Debug Configu Create manage and run configurations Connection Configuration for connection type Bare Metal Debug is not valid Connection cannot be empty Mi a x Ep type filter text 4 fe C C Applicatio fe C C Attach to 4 fe C C Postmorte E C C Remote Aj 3 DS 5 Debugger 2 SampleConfig Iron Python Run Iron Python unitte E Java Applet 5 Java Application Ju JUnit g Jython run g Jython unittest Launch Group dij PyDev Django 2 PyDev Google Ap 2 Python Run g Python unittest eag Remote Java Appl m Filter matched 19 of 19 ite O Debugger Option
141. tion 3 On the Linux console run the command ifconfig to determine the IP address of the board 4 On the Linux console change the root password by running the passwd command Ignore the warnings about a weak password Related Information e Getting Started with Board Setup on page 5 1 For more information refer to the Getting Started with Board Setup section e Getting Started with Running Linux on page 5 2 For more information refer to the Getting Started with Running Linux section Starting Eclipse via the Embedded Command Shell 1 Start an Embedded Command Shell by running lt SoC EDS installation directory gt embedded_command shell sh 2 Start Eclipse by running the eclipse command from the Embedded Command Shell 3 The Eclipse tool part of the ARM DS 5 AE prompts for the workspace folder to be used Accept the suggested folder and click OK 4 The ARM DS 5 AE Welcome screen appears It can be used to access documentation tutorials and videos Altera Corporation Getting Started Guides CJ Send Feedback Importing the Sample Application 5 23 Importing the Sample Application 1 In Eclipse select File gt Import The Import dialog box displays 2 In the Import dialog box select General gt Existing Projects into Workspace and click Next This will open the Import Projects dialog box Figure 5 21 Import Existing Project Select Create new projects from an archive file or directory Select an impor
142. ttings by going to Window gt Preferences gt General gt Network Connections 8 After a few moments the ARM DS 5 will activate the license and display it in the License Manager Click Close Licensing Altera Corporation CJ Send Feedback 4 6 Activating the License Figure 4 7 ARM License Manager View and edit licenses Add or delete licenses below Select a license to view more information about it 7 LM01459 gt CD ic Add License This license is stored in C Users ED AppData Roaming ARM DS 5 licenses directory Which is referenced from ARMLMD_LICENSE_FILE environment variable Select the toolkit that you intend to use Related Information ARM Self Service For more information about creating user accounts refer to the ARM website silver arm com Altera Corporation Licensing CJ Send Feedback Getting Started Guides X Subscribe C3 Send Feedback This chapter presents a series of getting started guides aimed at enabling you to quickly get accustomed to doing the basic SoC software development tasks The following items are covered e Preloader e Bare Metal debugging e SoC Hardware library HWLIB e Peripheral register visibility e Linux application debugging e Linux Kernel and driver debugging e Tracing e Cross Triggering The following additional topics are covered to support the above scenarios e Board setup needed for all the scenarios
143. up It corresponds to the soft IP GPIO module that controls the FPGA LEDs on the board 10 Expand the DATA register This register contains the values that are driven on the GPIO pins to control the LEDs Altera Corporation Getting Started Guides CJ Send Feedback Getting Started with Linux Application Debugging 5 21 Figure 5 20 Soft IP Registers 00 Variables Breakpoints 0 Registers 3 xy Expressions fO Functions wv Oe S Linked Altera SoCFPGA HardwareLib FPGA CV GNU Debug lt i Name Value Size Access H S uartd T H S uartl amp usb0 H amp usbl gt altera_avalon_sysid_sysid_qsys_control_slave amp altera_avalon_pio_led_pio_sl altera_avalon_pio_led_pio_sl_DATA x 0000008 32 R W data 32 R W altera_avalon_pio_led_pio_sl_DIRECTION xeee0 088 32 R W He a SPeripherals altera_avalon_pio_led_pio_s1 altera_avalon_pio_led_pio_s1_DATA data alti Reads Data value currently on PIO inputs Writes New value to drive on PIO outputs altera_avalon_pio_led_pio_sl_SET_BIT rite only 32 WO altera_avalon_pio_led_pio_sl_CLEAR_BITS rite only 32 WO amp altera_avalon_pio_dipsw_pio_sl S altera_avalon_pio_button_pio_sl 11 You can resume the code several times by pressing F8 and you will see how the DATA register changes and the HPS LEDs on the board are lighted accordingly 12 You can also change the DATA register manually and see the LEDs being lighted accordingly 13 Colla
144. use the Yocto Plugin is located on the Rocketboards website www rocketboards org Related Information e Yocto Project For more information about the Yocto Linux source project refer to the Yocto Project website http www yoctoproject org e Yocto Eclipse Plugin For more information about the Yocto Eclipse Plugin refer to the Rocketboards website http www rocketboards org 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at Be www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with caret egiste Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JN DTE RYA 101 Innovation Drive San Jo
145. valvinnasetatantaeecrmeraioueiaeiabivane 9 2 Hardware Manager HW Manager icsissassascasssssniosasadenssedetersarascsnsassvesandsarabaticsranseegecatuataoanebssasiis 9 2 Hardware Library Reference Tic ute nati Oi sin ised caastcscinasastasdvistioenestatenatabinsblasnnaiandtenannsiassseatianns 9 3 HPS Flash Programmer User Gude sivsacicvosssisectansectvcocssvsecsasss casvouivsseewiesarssvenens 10 1 HPS Flash Programmer Command Line Utilities ajiisisessssasesitsovsssvesacsasanessvassassnesscarsssvosvsdeanasatsveassvess 10 1 How the HPS Flash Programmer W Ores cs cosssspsctossnsnetantsaitnaiaiseaesvinsternivcas tenivenirianvanvanianm ators 10 2 Using the Flash Programmer from the Command Line cccesesesessessesseeseeseeseesessesseesesensseesees 10 2 HPS Flash Propane r eyscsdsscicpscnaseascasapedicvsdiacd insanspacosp iaiia ii sann ai aaea kak E 10 2 HPS Flash Programmer Command Line Exammpless ssiisssosiesssssssasessssisorastsesssssnaeosassesssssnoscsaese 10 4 S ppotted Memory DEVICES vissri iiivsrsi issira innti ititira ENNEN E NEN VANERISET AEREN 10 5 Lin x Comipilet ssesssissisoissossesrresreinesesisssreeesessstanee res rasio sdso Kesekso prasote neso seis vissies 11 1 Yocto PWG iihijccesscccscarsessstonevacoeusoassatcangece papeeiataayaete sioner eames 12 1 Device Tree Generators iiissssssscsecrwantssreessinessuosnscsuneedantvevansassuousensceuenadantienianssnis 13 1 Altera Corporation Introduction to SoC Embedded Design Suite S
146. vised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JN DTE RYA ISO 9001 2008 Registered 101 Innovation Drive San Jose CA 95134 HPS Preloader User Guide 2013 05 03 C9 Subscribe GJ Send Feedback There are four stages of the hard processor system HPS booting process the preloader is the second stage Figure 8 1 Typical Boot Flow Boot ROM y Preloader v Boot Loader a Operating System The Preloader configures the HPS component based on the information from the handoff folder initializes the SDRAM and then loads the next stage of the boot process into SDRAM and passes control to it The preloader can directly load your final application for Bare Metal applications and simple RTOSes Typically a boot ROM loads the preloader from a flash device into the on chip RAM and executes the preloader The preloader can also be executed directly from the FPGAmemory Related Information e Arria V Device Handbook Booting and Configuration For more information about the four stages of the HPS booting process refer to the Booting and Configuration appendix in volume 3 of the Arria V Device Handbook e Cyclone V Device Handbook Booting and Configuration For more information about the four stages of the HPS booting process refer to the Booting and Configuration appendix in volume 3 of
147. w arm com and from Eclipse by navigating to Help gt Help Contents gt ARM DS 5 Documentation e Rocket Boards For more information about Linux refer to the Rocketboards website Getting Started Guides Altera Corporation CJ Send Feedback ARM DS 5 Altera Edition S Subscribe C3 Send Feedback The ARM DS 5 Altera Edition is based on the ARM Development Studio 5 DS 5 Toolkit and is a device specific exclusive offering from Altera The ARM DS 5 Altera Edition is a powerful Eclipse based comprehensive Integrated Development Environment Some of the most important provided features are e File editing supporting syntax highlighting and source code indexing e Build support based on makefiles e Bare metal debugging e Linux application debugging e Linux kernel and driver debugging e Multicore debugging e Access to HPS peripheral registers e Access to FPGA soft IP peripheral registers e Tracing of program execution through PTM e Tracing of system events through STM e Cross triggering between HPS and FPGA e Connecting to the target using Altera USB Blaster II The ARM DS 5 Altera Edition is a complex tool with a vast amount of features and options The Altera SoC EDS User Guide only describes some of the most common features and options and provides getting started scenarios to allow you to start being productive quickly Related Information ARM DS 5 Documentation The ARM DS 5 Altera Edition reference material
148. wn the tracing can be selected to show current core a particular core or follow the currently executing thread The following steps are necessary in order to enable PTM tracing 1 Execute the steps described in the Getting Started with Linux Kernel and Driver Debugging section to perform Linux kernel debugging 2 Select Run gt Debug Configurations and select the Debug Linux_DevKit configuration created at the previous step Getting Started Guides Altera Corporation CJ Send Feedback 5 38 Getting Started with Tracing 3 Select the Connection tab 4 Click the Edit DTSL Options button Figure 5 40 Edit DTSL Options Button lt i Connection D Files 4 Debugger ii OS Awareness Arguments PS Environment Select the manufacturer board project type and debug operation to use Currently selected Altera Cyclone V SoC Linux Kernel and or Device Driver Debug Debug Cortex A9x2 SMP via Altera L eo v Linux Kernel and or Device Driver Debug Debug Cortex A9_0 via Altera USB Blaster Debug Cortex A9_0 via DSTREAM RVI Debug Cortex A9_1 via Altera USB Blaster Debug Cortex A9_1 via DSTREAM RVI Debug Cortex A9x2 SMP via Altera USB Blaster Nahin Cartav AQv CMD wis NCTREAMIAVI DTSL Options Configure trace or other target options Using default configuration options DS 5 Debugger will connect to an Altera USB Blaster to debug a SMP Linux kernel 5 In the DTSL windowDTSL dialog box cli
149. you name the BSP settings file settings bsp preloader settings dir No This option specifies the path to the hardware lt preloader settings dir gt handoff files bsp dir lt bsp dir gt No This option specifies the path where the BSP files are generated When specified bsp create settings generates the files after the settings file has been created Altera recommends that you always specify this parameter with bsp create settings set lt name gt lt value gt No This option sets the BSP setting lt name gt to the value lt value gt Refer to BSP Settings for a complete list of available setting names and descriptions Related Information BSP Settings For a complete list of available setting names and descriptions refer toBSP Settings bsp update settings The bsp update settings tool updates the settings stored in the BSP settings file as shown in the following example HPS Preloader User Guide Altera Corporation GJ Send Feedback 8 6 bsp query settings 2013 05 03 Example 8 3 Updating a PSP The following command changes the value of a parameter inside the file settings bsp bsp update settings settings settings bsp set spl debug SEMIHOSTING 1 Table 8 2 User Parameters bsp update settings ET D eea settings lt settings file gt Yes This option specifies the path to an existing BSP settings file to update prelGader scttings oir No This option spec

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