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ADS8568EVM-PDK User Guide (Rev. A)

1. t ADC Bypass BVDD BVDD BVDD BVDD C40 C35 CM C33 ca BVDD RI4 R3 C46 F 0 1uF 0 1uF 0 1uF ko L ig 1 Ik E B c A0 2 ra Al E __13 C42 _ 4 EN as t 46 REF A 1 2 BVDD CH B0 5 AD EST SN74AHC138 BI CH 40 so Rere 33 REF STBY ADC Data Bus Lan Depo 2 JPIS DBUDCIN 22 DODI 4 12 AGND B 3L DC D2 6 3 DB3 DCIN_A 30 DC D3 s 55 m L 29 DC D4 49 10 49 R56 63 REF c DBS SEL CD De DS i 12 anm t 0 REF C DB6 SEL B DC DG i3 14 re DB7 26 DC D7 15 16 1516 10k Do Z cH Do DBS DCEN DC D8 is 1516 L 5 AGND DB9SDI 22 DC D9 i9 gt as Di CH DI DBIOSCIK 2AL DC D10 7 2 2192 C45 10uF DBII REFBUFEN 20 DODII 33 x 6 REF D 7812500 2 25 26 Parallel Control REF D DBI3SDO B 8 27 28 HVDD A ki 7814600 C L DC D14 29 30 HVSS
2. Item Quantity Designator Description Manufacturer Part Number 30 2 L1 L2 Power inductors 5 3 pH 1 90 A Sumida CDRH5D28NP 5R3NC 31 1 Q1 MOSFET P channel 20 V 3 7 A SOT23 3 Vishay Siliconix SI2323DS T1 E3 R1 R4 R5 R7 R14 R17 R18 R27 32 24 R31 R35 R40 R44 R60 R61 R64 R67 Resistor 1 kO 1 10 W 196 0603 SMD Yageo RCO603FR 071KL R70 R73 R76 R79 R82 33 10 R10 R13 R15 R16 R19 R20 R41 R45 Resistor 10 O 1 10 W 196 0603 SMD Yageo RCO603FR 0710RL E 35 5 R36 R55 R58 Resistor 10 kQ 1 10 W 1 0603 SMD Yageo RCO603FR 0710KL 36 2 R24 R25 Resistor 2 1 10 W 1 0603 SMD Yageo RCO603FR 072KL 37 1 R37 Resistor 1 O 1 10 W 196 0603 SMD Yageo RC0603FR 071RL 38 1 R46 Resistor 130 kQ 1 10 W 1 0603 SMD Yageo RC0603FR 07130KL R47 R48 R54 R62 R63 R65 R66 R68 39 20 R69 R71 R72 R74 R75 R77 R78 R80 Resistor 0 Q 1 10 W 0603 SMD Yageo RCO0603JR 070RL R81 R83 R84 R86 40 1 R49 Resistor 1 MO 1 10 W 196 0603 SMD Yageo RC0603FR 071ML 41 1 R50 Resistor 90 9 1 10 W 1 0603 SMD Yageo RC0603FR 0790K9L 42 1 R51 Resistor 100 O 1 10 W 196 0603 SMD Yageo RC0603FR 07100RL 43 1 R52 Resistor 1 50 MQ 1 10 W 1 0603 Yageo RC0603FR 071M5L 44 2 R53 R87 Resistor 51 1 kQ 1 10 W 1 0603 SMD Yageo RCO60SFR 0751K1L 45 1 R59 49 9 1 10 W 1 0603 SMD Yageo RC0603FR 0749R9L 46 6 TP1 TP3 TP6 TP8 TP11 Test point PC mini 0 040 D red Keystone 50
3. 1 Changed entire uu u aa Saya 1 NOTE Page numbers for previous revisions may differ from page numbers in the current version Revision History 21 SBAU193A July 2011 Revised February 2012 Submit Documentation Feedback Copyright O 2011 2012 Texas Instruments Incorporated Evaluation Board Kit Important Notice Texas Instruments provides the enclosed product s under the following conditions This evaluation board kit is intended for use for ENGINEERING DEVELOPMENT DEMONSTRATION OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end product fit for general consumer use Persons handling the product s must have electronics training and observe good engineering practice standards As such the goods being provided are not intended to be complete in terms of required design marketing and or manufacturing related protective considerations including product safety and environmental measures typically found in end products that incorporate such semiconductor components or circuit boards This evaluation board kit does not fall within the scope of the European Union directives regarding electromagnetic compatibility restricted substances RoHS recycling WEEE FCC CE or UL and therefore may not meet the technical requirements of these directives or other related directives Should this evaluation board kit not meet the specifications indicated in the User s Guide the boar
4. RIO A 0 luF 100 Mi 2200pF VOP R66 As ex R78 lt OPA2211AD 0 L 0 L OP VOP 39pF 3 3 R21 NI R5 lk 109 R39 e R20 BO R4l 100 DO R67 2 7 C65 208 R NI 8 XI 7T cie R79 EU 2200 2200 6 ar OPA2211AD ES L 71718 NI ce R81 OPA2211AID 71920 0 NI Analog Input 0 VOP E C27 Op Amp Bypass lk C51 R29 NI RI Rae 52 BE O 1uF R45 100 BI R70 ik 6 B1 VOP R22 NI 71 0 s i R42 220008 cut frn 8 OPA2211AD 2200pF NI Op Amp Bypass 0 m OP voP OF 686 VOP HVINT T 70 HVINT VIN 433VD ABA v VD pvpp 35VA T B T m R25 VA AVDD kr 1 2 E 2k FB4 FBS 7 cs 9 10 cul Di e E 4 OF Figure 13 ADS85x8EVM Schematic 1 SBAU193A July 2011 February 2012 ADS8568EVM PDK 19 Submit Documentation Feedback Copyright O 2011 2012 Texas Instruments Incorporated Bill of Materials Layout and Schematic 5 INSTRUMENTS www ti com
5. Submit Documentation Feedback Copyright O 2011 2012 Texas Instruments Incorporated l TEXAS INSTRUMENTS www ti com Using the ADS8568EVM PDK Plug In in ADCPro 4 4 1 Using the ADS8568EVM PDK Plug In in ADCPro Using the ADS8568EVM PDK Plug in The ADS8568EVM PDK plug in for ADCPro provides control over all settings of the ADS8568 in parallel interface mode The ADS8568EVM PDK plug in may be used in Hardware mode or Software mode The user can adjust the ADS8568EVM settings when not acquiring data During acquisition all controls are disabled and settings may not be changed When a setting is changed on the ADS8568EVM plug in the setting immediately updates on the board Settings on the ADS8568EVM correspond to settings described in the ADS8568 product data sheet Operation in Hardware Mode For proper operation in hardware mode the user selects Hardware mode by clicking on the Mode panel Jumper JP16 must be shunted or closed refer to Figure 3 The channel range is adjusted in hardware mode by setting jumper JP18 shunt 2 3 4 Vae range is selected shunt 1 2 2x range is selected For proper operation the user must also ensure that the channel range in ADCPro matches the hardware settings When using the internal reference the user must verify that jumper JP12 is open JP21 must be open to enable the internal reference If the onboard REF5025 2 5 V reference is desired JP21 must be shunted to disable th
6. 36 DBIS SDO_D 16 31 32 10 48 t RI6 RANGEXCIK BVDD 10 L 5 i Bs C57 C58 C38 CAI 8 5 56 REFIO 10k JP18 HOLD z R55 10uF 10uF 0 1uF 66 Hwsw 4l BVDD one 2 ae 8 PARSER amp 8 L Ra ma 499 HOLD n HVDD GHVNT x 10k 5 4 sviN pvp cnl cat _ R87 4 7uF 51 1k AVDD U7 R49 150p L t Ds IM 2 1 C50 we 29 20 0 9 3 6 1 R50 10uF pur i3 4 0 01uE 1 7 e 90 9k i F5025 Ql t 1 lope DRHSDOSNP SR3NC 4 Rag C55 Ep323DS FPP 224 9 6 2 0 22 1 lt 130k HVSS VREF amr 5 i ed 15 0 TOs NN oun y 6 Emas zz 13 1 a gaeaeg ON levin C68 12 e 4JuH 4 7uH 4 7uF 7 TPS65131RGE END DRHSD28NP 5R3NC ER R85 NI 4 R86 0 Figure 14 ADS85x8EVM Schematic 2 20 ADS8568EVM PDK Copyright O 2011 2012 Texas Instruments Incorporated SBAU193A July 2011 Revised February 2012 Submit Documentation Feedback TEXAS INSTRUMENTS www ti com Revision History Revision History Changes from Original July 2011 to A Revision Page Changed document title to ADS8568EVM PDK
7. JP21 Open Internal ADC reference enabled JP22 Closed Selects parallel interface mode JP23 Short 1 2 14 V onboard supply on 2 2 ADS8568EVM PDK Kit Operation To prepare to evaluate the ADS8568 with the ADS8568EVM PDK complete the following steps 1 Verify the jumpers on the ADS8568EVM are as shown in Figure 2 note that these settings are the factory configured settings for the EVM 2 Using the MMB1 Motherboard User s Guide SLAU372 verify the MMB1 jumpers are in the default position and install the ADCPro and ADS8568EVM plug in software Complete hardware connections and driver installation as part of the MMB1 Motherboard User s Guide SLAU372 3 Plug the ADS8568EVM into the MMB1 The female portion of 42 J3 J4 and J5 on the EVM align with the respective male connectors J6 J7 J13 and J14 of the MMB1 4 Connect the included ac adapter to the MMB1 Do not misalign the pins when plugging the ADS8568EVM into the MMB1 Check the pin alignment of J2 J3 J4 and J5 carefully before applying power to the ADS8568EVM PDK CAUTION SBAU193A July 2011 Revised February 2012 Submit Documentation Feedback ADS8568EVM PDK 5 Copyright O 2011 2012 Texas Instruments Incorporated TEXAS INSTRUMENTS Quick Reference www ti com 3 3 1 3 2 3 3 3 4 6 Quick Reference Analog Input Eight of the analog input sources channels 0 to 7 can be applied directly to heade
8. O Supply The buffer supply of the ADS8568EVM PDK is provided through connector J3 Connector J3 has 3 3 V and 5 V digital supply defined on pins 9 and 10 respectively Jumper JP4 on the EVM allows the user to select the default 5 5 V or 3 3 V for the device BV source This voltage is also applied to the remaining digital circuitry on the EVM Figure 7 shows jumper JP4 configured for the 3 3 VD buffer supply 5VD 3 3VD 10 0 1uF Figure 7 Voltage Selection SBAU193A July 2011 Revised February 2012 ADS8568EVM PDK 13 Submit Documentation Feedback Copyright 2011 2012 Texas Instruments Incorporated Bill of Materials Layout and Schematic 5 4 Digital Controls J4 and J5 The digital inputs and outputs of the EVM are provided through connectors J4 and J5 The ADS8568EVM PDK plug in supports the parallel interface of operation 5 4 1 Parallel Control Connector J4 TEXAS INSTRUMENTS www ti com Connector J4 contains parallel control signals such as write enable and read enable Four address lines are also provided to allow the stacking of multiple ADS8568EVMs The signals applied to this connector are routed through U7 when the device is set up in the parallel interface mode of operation JP22 closed Table 5 describes the control lines found on J4 Table 5 Connector J4 Parallel Control Pin Number Signal Description J4 1 DC_CNTL G2A input to address de
9. Revised February 2012 ADS8568bEVM PDK 11 Submit Documentation Feedback Copyright O 2011 2012 Texas Instruments Incorporated TEXAS INSTRUMENTS ADS8568EVM Hardware Details www ti com 5 3 5 3 1 12 Power Supplies The ADS8568EVM PDK is configured at the factory with an on board bipolar analog input 14 5 V switching supply EHV a 5 V AVpp analog supply and either a 5 BV or 3 3 Vpp supply For ADS8568EVM stand alone operation power sources can be applied through connector J3 on the board Table 3 shows the various supply connections on connector J3 Table 3 Connector J3 Power Supply Inputs Signal Pin Number Signal VA Connects to HVDD VA Connects to HVSS 5 VA Connects to AVpp Unused DGND AGND Unused Unused 3 3 V optional BVpp 10 5 V optional BVpp Ocio A N Bipolar Analog Input Supplies The board is configured from the factory with a 14 5 V switching supply to generate the HV analog bipolar input 14 5 V supply The onboard 14 5 V is generated via the TPS65131 positive and negative dc to dc converter The user could also provide power to the HV supplies and onboard buffers from a well regulated external linear supply that has current limiting capabilities The HVDD and HVSS supplies to the ADS8568 can be selected through jumpers JP19 and JP20 The supplies to the OPA2211 buffers can be selected through jumpers JP10 and JP11 If the user desires to use the e
10. is granted under any patent right or other intellectual property right of TI covering or relating to any machine process or combination in which such TI products or services might be or are used FCC Warning This evaluation board kit is intended for use for ENGINEERING DEVELOPMENT DEMONSTRATION OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end product fit for general consumer use It generates uses and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules which are designed to provide reasonable protection against radio frequency interference Operation of this equipment in other environments may cause interference with radio communications in which case the user at his own expense will be required to take whatever measures may be required to correct this interference EVM Warnings and Restrictions It is important to operate this EVM within the input voltage range of 15 V to 15 V and the output voltage range of 3 3 V to 5 5 V Exceeding the specified input range may cause unexpected operation and or irreversible damage to the EVM If there are questions concerning the input range please contact a TI field representative prior to connecting the input power Applying loads outside of the specified output range may result in unintended operation and or possible permanent damage to the EVM Please consult the EVM User s Guide
11. prior to connecting any load to the EVM output If there is uncertainty as to the load specification please contact a TI field representative During normal operation some circuit components may have case temperatures greater than 85 C The EVM is designed to operate properly with certain components above 85 C as long as the input and output ranges are maintained These components include but are not limited to linear regulators switching transistors pass transistors and current sense resistors These types of devices can be identified using the EVM schematic located in the EVM User s Guide When placing measurement probes near these devices during operation please be aware that these devices may be very warm to the touch Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright O 2012 Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications app
12. 00 47 6 TP4 TP5 TP7 TP9 TP10 TP12 Test point PC mini 0 040 D black Keystone 5001 48 4 U1 U5 U6 U8 IC op amp precision DL LNLP 8 SOIC T OPA2211AIDDA 49 1 U2 IC 3 8 line decodr demux 16 SOIC T SN74AHC138D so DU 51 1 U4 IC op amp GP R R 38 MHz SGL 8 MSOP T OPA350EA 250 52 1 U7 IC precision VREF 2 5 V LN LD MSOP T REF5025AIDGKT 53 1 U9 IC converting DC DC pos neg 24 QFN T TPS65131RGER 54 6 N A 0 100 shunt black shunts 3M 969102 0000 DA 55 13 N A 2 mm shunt Samtec 2SN BK G 16 ADS8568EVM PDK Copyright 2011 2012 Texas Instruments Incorporated SBAU193A July 2011 Revised February 2012 Submit Documentation Feedback TEXAS INSTRUMENTS www ti com Bill of Materials Layout and Schematic 62 Layout through show the PCB layout of the ADS8568EVM not to scale Installed Device 58568 8528 ADS85x8EVM Rev Parallel Data 3 ie 8 Mr iene oe ae 6521094 PWB Rev B Ld eem 190000000 Parallel Control E cans Brem CAC E E E z s amr s nita MIS eee wees Figure 10 ADS85
13. 011 Revised February 2012 Submit Documentation Feedback Copyright O 2011 2012 Texas Instruments Incorporated TEXAS INSTRUMENTS www ti com Bill of Materials Layout and Schematic Table 7 Bill of Materials Item Quantity Designator Description Manufacturer Part Number 1 1 N A Printed wiring board Tl 6521094 2 8 C1 C18 C19 C25 C27 C63 C66 Murata GRM1885C1H390JA01D C2 C3 C11 C15 C22 C24 C32 C36 S 3 25 C38 C41 C46 C48 C50 C52 C59 C81 Capacitor ceramic 0 1 HF 7 50 V 10 Murata GRM188R71H104KA93D C86 4 0 C4 C7 C8 C10 C17 C20 C64 C67 Not installed C5 C6 C9 C12 C14 C42 C45 C53 C57 Capacitor ceramic 10 uF X5R 16 V 20 5 13 C58 C61 0805 TDK C2012X5R1C106M 6 8 C13 C16 C28 C31 C62 C65 Murata GRM1885C1H222JA01D 7 5 C21 C23 C49 C54 C85 Taiyo Yuden GMK107BJ105KA T 8 1 C37 oo ceramic 0 47 pF TO V 10 Murata GRM188R61A474KA61D 9 2 C55 C60 Taiyo Yuden JMK212BJ226KG T 10 1 C68 C69 Capacitor ceramic 4 7 uF 25 V X5R 0805 Murata GRM21BR61E475KA12L 11 2 C70 C72 capacitor ceramic 0 01 X7R 50 V 10 Murata GRM188R71H103KA01D 12 2 C71 C83 Capacitor ceramic 150 pF 50 V COG 0603 TDK C1608C0G1H151J 13 8 C73 C80 TDK C3216X7R1E475K 14 1 C82 Capacitor ceramic 0 22 uF 16 V X7R 10 TDK C1608X7R1C224K 15 2 D1 D2 LED 565nm green dif
14. 10 based MMB1 motherboard that can be used with ADCPro to quickly evaluate the device This manual covers the operation of the ADS8568 device referred to as the ADS8568EVM and the ADS8568E VM PDK Throughout this document the abbreviation EVM and the term evaluation module are synonymous with the ADS8568EVM Related Documentation from Texas Instruments The related documents listed in Table 1 are available for download through the Texas Instruments web site at www ti com Table 1 Related Documents Device Literature Number ADS8568 SBAS543 OPA2211 5805377 TPS65131 SLVS493 REF5025 SBOS410 SN74LVC1G17D SCES351 SBAU193A July 2011 Revised February 2012 ADS8568bEVM PDK 3 Submit Documentation Feedback Copyright O 2011 2012 Texas Instruments Incorporated QuickStart 2 QuickStart This section provides a QuickStart guide to quickly get up and running using ADCPro 2 1 Default Jumper Settings TEXAS INSTRUMENTS www ti com A silkscreen detailing the default jumper settings is shown in Figure 2 Table 2 explains the configuration for these jumpers 4 ADS8568EVM PDK ADS85x8EVM Rev Deron 8 ai 6521094 m m m ang EINE 9 09 mm um du d a da C T E WW oy s Texas I NSTRUMENTS Fi
15. 68EVM Internal GND Layer 1 Figure 11 ADS8568EVM Internal Layer 2 SBAU193A July 2011 Revised February 2012 ADS8568EVM PDK 17 Copyright 2011 2012 Texas Instruments Incorporated Bill of Materials Layout and Schematic 63 Schematic Figure 13 and Figure 14 show complete schematics for the ADS8568EVM 18 ADS8568EVM PDK 4 Figure 12 ADS8568EVM Silkscreen Bottom Layer INSTRUMENTS www ti com SBAU193A July 2011 Revised February 2012 Copyright 2011 2012 Texas Instruments Incorporated Submit Documentation Feedback TEXAS INSTRUMENTS www ti com Bill of Materials Layout and Schematic 5792 Note 39pF Components marked NI Op Amp Bypass ex are NOT installed m NI R4 dk luF 10 0 R6l E 2s psf RU co P m mat Cos m R62 3 02 mw 2 t 220097 2211 E d NI E 0 VOP VOP __ 23 ag
16. R AN E 12 4 Analog Bipolar Input Supply Jumpers eee eee eee eee nnn II Inm emen mn ehe n nen 12 5 GonnectorJ4 Parallel Controls uu uuu maak mua aec 14 6 Connector J5 Parallel Interface Data Ouput 14 7 5 15 ADS8568EVM PDK SBAU193A July 2011 Revised February 2012 Submit Documentation Feedback Copyright O 2011 2012 Texas Instruments Incorporated l TEXAS INSTRUMENTS www ti com EVM Overview 1 1 1 1 2 EVM Overview The ADS8568EVM is an evaluation module EVM built to the TI Modular EVM System specification It can be connected to any of the modular EVM system interface cards available from Texas Instruments The ADS8568EVM is available as a stand alone printed circuit board PCB or as part of the ADS8568EVM PDK which includes an MMB1 motherboard and software As a stand alone PCB the ADS8568EVM is useful for prototyping designs and firmware ADS8568EVM Features Contains all support circuitry needed for the ADS8568 Voltage reference options internal reference onboard REF5025 or external reference Analog input bipolar voltage supply options onboard 14 5 V HV analog supplies or external supply inputs Compatible with the TI Modular EVM System The ADS8568EVM PDK includes the ADS8568EVM and an Opal Kelly XEM30
17. coder U3 default low by pull down resistor Rss J4 3 DC AWE Active low write enable input to ADS8568 used with CS to write to the configuration register Active low read enable input to ADS8568 used with CS to read from the J4 5 ARE parallel data bus J4 7 DC_A0 3 line to 8 line address decoder input A J4 9 DC_A2 3 line to 8 line address decoder input B J4 11 DC_A3 3 line to 8 line address decoder input C 3 line to 8 line address decoder input G1 must be high to enable address line J4 13 decoder J4 15 DC_A3 No connection CONVST_A B C D inputs when shunt jumpers are placed in the respective DC TOUT default states on JP9 as described in Table 2 Interrupt source to host processor connects directly to pin 18 BUSY of the J4 19 DC_INTa ADS8568 J4 2 through 44 20 DGND These pins are connected to digital ground even 5 4 2 Parallel Data Connector J5 Connector J5 contains parallel interface output data lines Table 6 lists the parallel data output found in connector J5 Table 6 Connector J5 Parallel Interface Data Ouput Pin Number Signal Description 16 bit parallel data bus used when writing to or reading from the ADS8568 in J5 1 through J5 31 odd DCD 15 0 parallel mode 44 3 DGND These pins are connected to digital ground 6 Bill of Materials Layout and Schematic 6 1 Bill of Materials Table 7 lists the ADS8568EVM bill of materials 14 ADS8568EVM PDK SBAU193A July 2
18. d kit may be returned within 30 days from the date of delivery for a full refund THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES EXPRESSED IMPLIED OR STATUTORY INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE The user assumes all responsibility and liability for proper and safe handling of the goods Further the user indemnifies TI from all claims arising from the handling or use of the goods Due to the open construction of the product it is the user s responsibility to take any and all appropriate precautions with regard to electrostatic discharge EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES TI currently deals with a variety of customers for products and therefore our arrangement with the user is not exclusive TI assumes no liability for applications assistance customer product design software performance or infringement of patents or services described herein Please read the User s Guide and specifically the Warnings and Restrictions notice in the User s Guide prior to handling the product This notice contains important safety information about temperatures and voltages For additional information on TI s environmental and or safety programs please contact the TI application engineer or visit www ti com esh No license
19. e internal reference and the user must switch to Software mode The user may input the desired sampling rate on the Data Rate panel The data rate is limited by the ADS8568EVM plug in software to a maximum of 400 kSPS The conversion results are available on connector J5 SBAU193A July 2011 Revised February 2012 ADS8568EVM PDK 7 Submit Documentation Feedback Copyright 2011 2012 Texas Instruments Incorporated TEXAS INSTRUMENTS Using the ADS8568EVM PDK Plug In in ADCPro www ti com ADS85X8EVM 3 400 000kHz Figure 3 Operation in Hardware Mode 8 ADS8568EVM PDK SBAU193A July 2011 Revised February 2012 Submit Documentation Feedback Copyright 2011 2012 Texas Instruments Incorporated TEXAS INSTRUMENTS www ti com Using the ADS8568EVM PDK Plug In in ADCPro 4 1 2 Operation in Software Mode For proper operation in software mode the user selects Software mode by clicking on the Mode panel Jumper JP16 must be open as shown in Figure SSXSEVM Figure 4 Operation in Software Mode When using the internal reference the user must verify that jumper JP12 is open and select Internal in the Vref Source control The Internal Reference Buffers must be enabled by selecting the appropriate panel The user may choose either the 2 5 V or 3 0 V internal Vier In addition the user may program the DAC to adjust the voltage reference by placing the code value as determined by Equation 1 in the Vref DAC panel pro
20. es Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agree that they are solely responsible for all legal regulatory and safety related requirements concerning their products and any use of TI products in such safety critical applications notwithstanding any applications related information or support that may be provided by TI Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications TI products are neither designed nor intended for
21. f 0603 SMD Lumex SML LX0603GW TR 16 2 D3 D4 MBRM120 Schottky 1 A 20 V PowerMite On Semi MBRM120ET3G 17 5 FB1 FB5 Ferrite chip 600 Q 500 mA 0805 TDK MMZ2012R601A 18 1 J1 Connector SMA jack straight PCB Amphenol 132134 19 1 J1 Connector SMA jack straight PCB Emerson 142 0701 201 20 2 J2 J4 Top 10 pin dual row SM header 20 posible Samtec TSM 110 01 T DV P 21 2 J2 J4 Bottom 10 pin dual row SM header 20 posible Samtec SSW 110 22 F D VS K 22 1 J3 Top 5 pin dual row SM header 10 posible Samtec TSM 105 01 T DV P 23 1 J3 Bottom 5 pin dual row SM header 10 posible Samtec SSW 105 22 F D VS K 24 1 J5 Top 16 pin dual row SM header 32 posible Samtec TSM 116 01 T DV P 25 1 J5 Bottom 16 pin dual row SM header 32 posible Samtec SSW 116 22 F D VS K JP1 JP2 JP4 JP8 JP10 JP11 JP13 JP14 9 26 15 JP18 JP20 JP23 3 pin 2 mm header Samtec TMM 103 01 T S 27 1 3 pin dual row header 6 posible Samtec TSW 103 07 T D 28 1 JP9 4 pin triple row header 12 posible Samtec TSW 104 07 T T 29 6 JP12 JP15 JP17 JP21 JP22 2 pin 0 1 inch header Samtec TSW 102 07 T S SBAU193A July 2011 Revised February 2012 Submit Documentation Feedback Copyright O 2011 2012 Texas Instruments Incorporated ADS8568EVM PDK 15 Bill of Materials Layout and Schematic Table 7 Bill of Materials continued TEXAS INSTRUMENTS www ti com
22. gure 2 ADS8568EVM Default Jumper Settings Copyright 2011 2012 Texas Instruments Incorporated Parallel Data 000001101001 Parallel Control LLL SBAU193A July 2011 Revised February 2012 Submit Documentation Feedback TEXAS INSTRUMENTS www ti com QuickStart Table 2 Default Jumper Configuration Default Position Switch Description Number JP1 Short 2 3 Selects the buffered AO input configuration JP2 Short 2 3 Selects the buffered A1 input configuration JP3 Open Sets CS low with R17 JP4 Short 1 2 Selects 5 VD as the BVDD voltage JP5 Short 2 3 Selects the buffered CO input configuration JP6 Short 2 3 Selects the buffered BO input configuration JP7 Short 2 3 Selects the buffered B1 input configuration JP8 Short 2 3 Selects the buffered C1 input configuration JP9 Short 1 2 4 5 7 8 and 10 11 Conversion start to J4 17 DCTOUT JP10 Short 1 2 Selects HVINT for the VOP AMP supply JP11 Short 1 2 Selects HVINT for the AMP supply JP12 Open External reference not connected to REFIO JP13 Short 2 3 Selects the buffered DO input configuration JP14 Short 2 3 Selects the buffered D1 input configuration JP15 Open Disables auto sleep mode JP16 Closed Selects hardware mode JP17 Open Disables RESET JP18 Short 2 3 Selects the 4 VREF range JP19 Short 1 2 Selects HVINT for the HVDD ADC supply JP20 Short 1 2 Selects HVINT for the HVSS ADC supply
23. ily interface with multiple control platforms Dual row header socket combinations at J2 J3 J4 and J5 allow connection to external circuitry for evaluation and debug Analog Input Circuit The circuit at the analog input of the ADS8568EVM board consists of four independent OPA2211 dual operational amplifiers The OPA2211 dual op amps may be powered from an onboard 14 5 V analog supply or from an external supply The amplifiers are configured as inverting unity gain buffers by default The OPA2211 buffer input circuit is shown in Figure 5 This circuit is used in all eight input channels Jumper JPx can be used to bypass the input buffer circuit VOP Figure 5 Analog Input Schematic ADS8568EVM PDK SBAU193A July 2011 Revised February 2012 Submit Documentation Feedback Copyright O 2011 2012 Texas Instruments Incorporated 13 TEXAS INSTRUMENTS www ti com ADS8568EVM Hardware Details 5 2 058568 Internal Reference EVM Onboard Reference The ADS8568 has an internal programmable 2 5 V or 3 V internal reference Alternatively the user can select the onboard 2 5 V reference REF5025 U7 When the device is set up in hardware mode JP16 closed the internal fixed 2 5 V reference is enabled through the REFEN pin JP21 open Refer to Figure 6 for the jumper location The channel range is adjusted in hardware mode by the JP18 settings JP18 shunt 2 3 4 range selected JP18 shunt 1 2 2 range
24. j Users Guide TE 5 SBAUT193A July 2011 Revised February 2012 INSTRUMENTS ADS8568E VM PDK Figure 1 ADS8568EVM PDK This user s guide describes the characteristics operation and use of the ADS8568EVM by itself and as part of the ADS8568EVM PDK This evaluation module EVM is an evaluation platform for the ADS8568 a 16 bit eight channel simultaneous sampling bipolar input analog to digital converter ADC The ADS8568EVM allows evaluation of all aspects of the ADS8568 device This document includes an EVM QuickStart hardware and software details bill of materials and schematic ADCPro is a trademark of Texas Instruments Incorporated All other trademarks are the property of their respective owners SBAU193A July 2011 February 2012 ADS8568EVM PDK 1 Submit Documentation Feedback Copyright 2011 2012 Texas Instruments Incorporated 2 13 TEXAS INSTRUMENTS www ti com Contents 1 EVM OVERVIEW 3 2 QUICK STANT EE 4 3 QUICK Qua qa aaa suq 6 4 Using the ADS8568EVM PDK Plug In in ADCPro 7 5 ADS8568EVM Hardware Details 10 6 Bill of Materials Layout and 14 List
25. licable at the time of sale in accordance with 5 standard warranty Testing and other quality control techniques are used to the extent Tl deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using Tl components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notic
26. nversion results are available through connector J5 Power Supply The analog portion of the ADS8568 requires an analog 5 V supply and a bipolar input supply The 5 V analog voltage supply can be generated by the ac adapter or by applying the 5 VA to the connector of the MMB1 board The ADS8568EVM is configured at the factory with the onboard 14 5 V bipolar supply The user can also select to apply the bipolar supply to the VA connectors on the MMB1 board Please refer to the Power Supplies section of the ADS8568EVM Hardware Details for more information CAUTION Do not exceed the 18 VDC bipolar Input supply limit Damage to the op amps and the ADS8568 can occur if this limit is exceeded Voltage Reference The ADS8568 has an internal 2 5 V to 3 V programmable reference Alternatively the user can select the onboard 2 5 V reference REF5025 U7 The device is set up by default in hardware mode JP16 closed with the internal 2 5 V reference enabled JP21 open Refer to the ADS8568 Internal Reference and EVM Onboard Reference section of the ADS8568EVM Hardware Details for more information CAUTION If the REF5025 2 5 V onboard reference is required the internal reference must be disabled by first shorting JP21 and afterwards installing JP12 Ensure JP12 is open whenever the internal reference is enabled to avoid potential damage to the ADS8568 device ADS8568EVM PDK SBAU193A July 2011 Revised February 2012
27. of Figures 1 ADSS568EVM PDK m 1 2 ADS8568EVM Default Jumper Settings 4 3 Operation im Hardware usa 8 4 Operation in Sotware 9 5 Analog Input 10 6 Jumpers JP16 JP18 JP212 22 a 11 7 BV inp Voltage Selection ya au aaa awaqa Naa yaa yawa wiway saa yw 13 8 ADS8568EVNM Silk sereen Layer NEMUS 17 9 ADS8568EVM TOD 17 10 ADSS8568EVME Internal GND Layer 1 ro Det nit Tera ce 17 11 ADS8568EVM Internal Layer 2 uuu sasawa renean MS 17 12 ADS8568EVM Silkscreen Bottom Layer 17 13 ADS85x8EVM Schematic T 19 14 ADS85x8EVM Schematic EU n UE 20 List of Tables 1 a ERKENNEN AE 3 2 Default JUMpPer GOMIQUIALION Rem 5 3 Connector J8 Power Supply Inputs ise entre epa nns EUM K
28. r J2 of the ADS8568EVM top side or through the analog IO J3 connector on the MMB1 board Each analog input signal can be configured to connect to the ADS8568 through the OPA2211 inverting unity gain buffers default condition JPx jumpered pins 2 to 3 or directly to the ADS8568 device Refer to the Analog Input Circuit section of the ADS8568EVM Hardware Details for more information about the analog input circuit By default the device is set up with the 2 5 V internal reference the 4 range selected corresponding to 10 V range Digital Control There is a variety of control lines associated with the ADS8568EVM that are user accessible through various jumpers The ADS8568 may output the conversion results using a serial or parallel interface The ADS8568EVM may be set in parallel or serial mode through jumper JP22 and may be configured in hardware or software control mode through jumper JP16 The operating mode of the device determines which connector pins on connectors J4 and J5 are used to control the converter operation and timing and which pins on the connector output the digital results NOTE The ADS8568EVM PDK kit with ADCPro supports the parallel interface mode of operation under hardware mode or software mode control By factory default the ADS8568EVM PDK is configured to operate with the parallel interface JP22 shunt under hardware control JP16 shunt When using the ADS8568EVM PDK kit the parallel interface co
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30. selected NOTE The device is configured at the factory in hardware mode with a 2 5 V reference and a 4x range The Operation in Hardware Mode section provides more detailed information about the hardware mode of operation When the device is set up in software mode JP16 open the user can select either the internal 2 5 V or 3 0 V programmable reference and choose either the 4 or 2 range through the software panel on the ADS8568EVM Plug In If the onboard REF5025 2 5 V reference is desired the internal reference must first be disabled in hardware mode J21 must be shunted to disable the reference The ADS8568EVM provides an onboard 2 5 V reference via U7 To use the REF5025 reference a shunt jumper must be placed on JP12 Test points TP8 and TP9 are provided to allow the user to monitor the reference voltage either internal or the REF5025 and may also be used to connect a user provided reference voltage in the range of 0 5 V to 3 025 V ADS85x8EVM Rev B sl TE iF mmm 16 0000001111 Parallel Data d d on css mij aves mua 6521094 ral ong HH Par m ia um Wa x d IT T ase fat s 5 da nir me I NSTRUMENTS 000001110101 Parallel Control Figure 6 Jumpers JP16 JP18 JP21 and JP22 SBAU193A July 2011
31. use in military aerospace applications or environments unless the TI products are specifically designated by TI as military grade or enhanced plastic Only products designated by TI as military grade meet military specifications Buyers acknowledge and agree that any such use of TI products which TI has not designated as military grade is solely at the Buyer s risk and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by as compliant with ISO TS 16949 requirements Buyers acknowledge and agree that if they use any non designated products in automotive applications TI will not be responsible for any failure to meet such requirements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Audio www ti com audio Automotive and Transportation www ti com automotive Amplifiers amplifier ti com Communications and Telecom www ti com communications Data Converters dataconverter ti com Computers and Peripherals www ti com computers DLP Products www dlp com Consumer Electronics www ti com consumer apps DSP dsp ti com Energy and Lighting www ti com energy Clocks and Timers www ti com clocks Industrial www ti com industrial Interface inte
32. vided Range x Code 1 1024 1 SBAU193A July 2011 Revised February 2012 ADS8568EVM PDK 9 Copyright 2011 2012 Texas Instruments Incorporated TEXAS INSTRUMENTS ADS8568EVM Hardware Details www ti com 5 1 10 Code is the decimal value of the DAC register content To ensure proper performance the DAC output voltage should not be programmed below 0 5 V If the external reference is desired the user must disable the internal reference first by selecting External The user may either install jumper J12 to connect the onboard 2 5 V REF5025 reference or connect an external reference The allowed external reference range is from 0 5 V to 3 025 V The user must input the reference voltage in the External Vref Source panel provided in the screen in order for ADCPro to display the conversion results properly When the device is operating in software mode the channel range is adjusted for each channel pair by selecting either 4 or 2 in the Channel Input Range panel Each device channel pair except channel pair A which is the master channel pair and is always active can be individually switched off using the Powerdown panel provided The user may input the desired sampling rate on the Data Rate panel The data rate is limited by the ADS8568EVM plug in software to a maximum of 400 kSPS The conversion results are available on connector J5 ADS8568EVM Hardware Details The ADS8568EVM is designed to eas
33. xternal linear supply the switching power supply may be disabled by placing jumper JP23 to the OFF position Ensure all power is off before manipulating the power supply jumpers Table 4 describes the bipolar input supply jumpers Table 4 Analog Bipolar Input Supply Jumpers Pin Number Default Position Switch Description 1 2 On board HVINT to OPA2211 buffers 2 3 External supply to OPA221 1buffers 1 2 On board HVINT to OPA2211 buffers 2 3 External HV supply to OPA221 1 buffers 1 2 On board HVINT to HVDD supply on ADS8568 2 3 External HV to HVDD supply on ADS8568 1 2 On board HVINT to HVDD supply on ADS8568 2 3 External HV to HVDD supply on ADS8568 JP10 Short 1 2 JP11 Short 1 2 JP19 Short 1 2 JP20 Short 1 2 CAUTION Do not exceed the 18 VDC bipolar input supply limit Damage to the op amps and the ADS8568 can occur if this limit is exceeded ADS8568EVM PDK SBAU193A July 2011 Revised February 2012 Submit Documentation Feedback Copyright O 2011 2012 Texas Instruments Incorporated TEXAS INSTRUMENTS www ti com ADS8568EVM Hardware Details 5 3 2 Analog 5 V Supply The ADS8568EVM board requires an independent 5 V supply to power the analog portion of the DUT the external reference and the external reference buffer This voltage is applied through J3 pin 3 and is denoted as AVDD This supply can be monitored at test point TP3 5 3 3 Digital Power Buffer I

ADS8568EVM-PDK User Guide (Rev. A)

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