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GreenPAK Designer User Guide

1. Silego Technology Inc 04 20 2015 109 www silego com N SILEGO PA GreenPAK1 4 Designer 4 02 Remove Point Removes selected point Double clicking on the point will also remove it Data panel Turns on off the data table User can remove change values for selected point or add new point between two existing points Figure 10 33 Import Points 48 Import points Insert points here 50 7 1 26 100 4 10 5 300 0 405 1 Options Decimal separator Column separator Row separator point zal tab A auta line Feed mo m User can insert points from another application and set separators options Decimal separator point comma Column separator auto tab it other Row separator auto line feed tab t other Figure 10 34 Data Panel Min T 7 34 ms T 1000 00 ms Max T 452191 50 ms Available points 65 x aoo tiw 0 00 5 Put EJ Period Put the point Cursor Silego Technology Inc www silego com 04 20 2015 110 SN SILEGO NR GreenPAK1 4 Designer 4 02 Figure 10 35 Cursor i Custom signal Wizard RNA x gt Clear A Add Point A Add Peak Continuous Ramp p Remove Point Data panel 7 Import points Close Data X Value Y Value 00 00 00 00 300 00 1000 00 500 00 600 00 700 00 00 00 100 00 400 00 1 0 00 ms 0 00 V 2 12777ms 241 974 3 328 79ms 2 26v 4 43270ms 2 10v
2. Mode Normal Invert signal mode Umax Umin max min voltage level T1 T2 T3 T4 duration of trapezoid If T3 1 signal is a triangle If T32 1 T2 2 or T4 2 signal is a saw Silego Technology Inc www silego com 04 20 2015 104 S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 Figure 10 27 Duration of Trapezoid LE Signal Wizard Options Ln z mn u 8 Generator PIN 11 Trapeze Tr gt a r S Shown period Auto Start point 0 00 ms E Stop point 1000 05 ms Fa Global linkage Linked v Repeat Cydic Se Repeat count 2 ad Prestart state Low gt Prestart delay 0 00 ms r End state Prestart state Output type High Z Pause type Laststate gt Type Trapeze Triangle S Mode Normal v Umax 408v L Umin 0 00 V r gt Z ES 250 00 ms Ka 0 50 z 2 0 50 T2 250 00 ms S ae 0 00 0 00 pp i 250 00 ms Ka lt r lt T un un un T4 250 00 ms ka S S S 8 ms Ka e e e Auto Apply kJ Apply All Start Pause Stop Auto Min 0 00 e Max 0 25 r 9 Silego Technology Inc www silego com 04 20 2015 105 SI LEGO GreenPAK GreenPAK1 4 Designer 4 02 Figure 10 28 Logic pattern 7 F Options Pre start state Low Pre start delay 0 00 ms End state Pre star
3. VDD Key 197 LED TP2 pu Pe ON N wpp me TPS Internal YDD External VDD Expansion Connector TPS TP10 TP12 TP14 Pie TP18 TP20 OFF TP TPS GNO Bi TPIS TPIZ i aa E Start Gers top Gens CEE LED s Emulation Nic EC INV PIN20 oo ETE Test Mode LED TP19 Nic EG Read INY PINI9 LED TP18 Nic EC i PINIS ncs oO LED TP17 Nic EC Frogram IM muli PINI7 j __ lt lt lt _ lt lt lt v LED TP16 E Nic EC INV PIN16 LED TP15 Nic EC is PINIS HEFN Md LED TP14 Nic EC INV PINI NIC EC INV l PIN13 KZ LED TP12 a nic EC INY PIN12 j Chip P N S Board Hy In figure 10 1 one can see the GreenPAK IC with stimulus areas and expansion connectors which are connected to pins There are 2 panels with buttons in the top left and top right corners which provide the emulation process Silego Technology Inc 04 20 2015 90 www silego com SS SILEGO PA GreenPAK1 4 Designer 4 02 Stimulus Areas are used to configure input connections Use the context menu to manage them Figure 10 2 Context Menu LED Enabled LED Inverted Connect Ea Expansion Connector MIC YDD GND Pull Up Pull Gown Button Logic generator 10 1 Types of Areas Fixed Inputs Figure 10 3 10 7 Figure 10 3 N C not connected Figure 10 4 Set to VDD Figure 10 5 Set to GND
4. Edit Rotate Left rotate a selected block counterclockwise Rotate Right rotate a selected block clockwise Flip Horizontal horizontal reflection of a selected block Flip Vertical vertical reflection of a selected block Align Horizontal horizontal alignment of selected blocks Align Vertical vertical alignment of selected blocks Set Label creating a text label for selected blocks Erase Label erasing text labels near selected blocks Set Wire enable wire creating mode Erase Wire enable wire erase mode lt o lt Zoom in increase the work area scale Zoom out decrease the work area scale Fit work area tune scale to show all blocks visible in project Zoom 1 1 set default scale Pan mode enable Full screen mode switch to full screen mode Properties show hide Properties panel NVM Viewer show hide NVM bits viewer Components show hide Green PAK blocks list e Rules Checker Output Tools in GreenPAK 1 Designer e Emulation this tool is included for convenient project testing e Programmer start GreenPAK Programmer with the current project exported e Rules Checker checks current design for correct settings Silego Technology Inc www silego com 04 20 2015 10 9 LEGO GreenPAK GreenPAK1 4 Designer 4 02 Tools in GreenPAK 2 Designer e Emulator this tool is included for convenient project testing e Mini Emulator this t
5. Phase Custom phase Amplitude Zero offset 50 Period 0 00 Frequency Data Modify Jane oo mees an start Pause sto auto Mn oo0 Elwen 025 Ell KATE ms Silego Technology Inc www silego com 04 20 2015 13 e 8 2 3 Logic Generator SILEGO GreenPAK GreenPAK1 4 Designer 4 02 Figure 8 20 Logic Generator Logic generator is used for generating the logic pulses Options Generator Shown period Start point Stop point Global linkage Repeat Repeat count Prestart state Prestart delay End state Output type Pause type T Figure 8 21 Edit Button Allows User to Configure The Signal y Signal Wizard General PIN 2 Logic Seque Auto 0 00 ms Zb 4h ab gt Cyclic Low 0 00 ms Prestart state Push Pull Last state O 0 o O ap P Logic Generator Settings Normal Level 1 500 00 ms High 2 500 00 ms Low 3 500 00 ms High 4 500 00 ms Low 5 500 00 ms High 6 500 00 ms Low boo 4 gt ab 49 Insert Remowe Count Auto Apply Configuration options Mode Repeat T Level Insert Remove Count 2850 07 2400 06 2550 06 2700 07 2250 06 1800 05 1950 05
6. Figure 3 17 Labeled connections A gt Available options for wire context menu Convert to labeled connection Available options for label context menu Convert to wired connection Rename network Remove connection 3 4 2 Set Erase Label Using Set Erase Label the user can add delete text label The Set Label tool adds a text label to the selected component or without connecting them to the specific component The user can Attach label to component or Detach label s from component s If no component is selected then the user can select a component from the list offered by the Set Label tool The user can also choose text color If the selected component already has a label Set Label tool can edit label text If the user selects more than one component it is possible to change the text color without changing text in all components at once If the user changes the text while more than one component is selected it will be changed on all selected components at once as well Erase Label deletes text label Figure 3 17 Add Label Ose JE Silego Technology Inc www silego com 04 20 2015 20 9 LEGO GreenPAK GreenPAK1 4 Designer 4 02 Qu ko 3 5 Specifying the Pinout 3 5 1 Port Connections Pin blocks can be connected just like any other blocks using the Wiring Tool 3 5 2 Port Drive Modes GreenPAK 1 chip has five PGIO PIN3 4 6 7 8 and one GPI PIN2 pin components These components
7. Figure 8 6 Pull Up Figure 8 7 Pull Down LED s Figure 8 8 8 9 Figure 8 8 Inverted Buffered LED Inverted Buffered LED Pull Up Inverted Buffered LED Pull Down Silego Technology Inc www silego com 04 20 2015 65 SILEGO GreenPAK GreenPAK1 4 Designer 4 02 lt ko Figure 8 9 Buffered LED Buffered LED Pull Up Buffered LED Pull Down Configurable Input Figure 8 10 Figure 8 10 Configurable Button die The default connection can be set to either Upper connection or Bottom connection Click your mouse over the key to change the value User can configure each connection to VDD GND High Z or Pull Up Down Figure 8 11 Default Key Connection Upper connection Bottom connection To Upper connection Key mode F To Bottom connection Set Push hot key NMC Upper connection GND High Z Pull Down Bottom connection b Default key connection Default key connection Key mode d Key mode Set Push hot key d Set Push hot key b Silego Technology Inc www silego com 04 20 2015 66 SN SILEGO PA GreenPAK1 4 Designer 4 02 The switch has 2 modes Latched or Unlatched which can be configured from the context menu Figure 8 12 Key Mode Upper connection Bottom connection Default key connection z Set Push hot key Unlatched RIF User can assign Hot
8. 2 03 V 100 00 400 01 1000 04 1100 04 1200 05 1300 05 1400 05 1500 06 1600 06 1700 06 1900 07 2000 07 Period EIS ms 400 01 700 03 300 0 100 00 Frequency 1200 05 1600 06 1800 07 1900 07 1100 04 1400 05 1500 06 a ken E Min 0 00 Max Sine settings Repeat One shot Cyclic Custom repeat option Phase Custom 0 Pi 2 Pi 3Pi 2 pO Custom phase show phase in a radian Amplitude amplitude Zero offset zero offset Period period Freguency shows freguency Data change signal using Custom Signal Wizard Silego Technology Inc www silego com 04 20 2015 103 SILEGO GreenPAK GreenPAK1 4 Designer 4 02 Figure 10 26 Trapezoid Triangle Sawtooth E Signal Wizard Options General Generator PIN 11 Trapeze Tr A E 1000 05 100 01 1 500 03 Shown period Auto Start point 0 00 ms ES Stop point 1000 05 ms Global linkage Linked zil Repeat Cydic Repeat count 3 Prestart state Low Prestart delay End state Prestart state Output type High z Fause type Laststate ZS Signal Generator Settings Trapeze Triangle 5 Normal T 4 08 V 0 00 v ES 250 00 ms ES 250 00 ms a 250 00 ms a 250 00 ms E Auto Apply kej Apply A Start Pause Stop auto Min 0 00 max 0 5 F Trapeze Settings
9. 5 446 32ms S o 02 6 504 25ms 2 0 00V 7 608 18ms 4 1 66v 8 650 77ms S 0 56 9 706 98ms e 174v 10 764 90ms 10 534 11 841 58ms 1 89 ue Ja Er Er ul J LE JLE JL E JEE JL i2 s9508ms o s8v ote r t tr t D r Le P 9 a gt a gt ab ab ab ab ab IGI ap ap a KIE ap 13 1 s 2 75 V ms 200 00 300 00 900 00 1000 00 500 00 600 00 700 00 800 00 100 00 400 00 Min T 7 34 ms T 1000 00 ms Max T 452191 50 ms Available points 68 X 300 00 E 2 00 H Put 3 10 2 6 VDD Power Signal Generator Figure 10 36 VDD Power Signal Generator Simple signal generator for VDD with its own options Silego Technology Inc www silego com 04 20 2015 111 SS SILEGO PA GreenPAK1 4 Designer 4 02 10 3 Expansion Connector User can connect disconnect I O pads of GreenPAK with the expansion connector on the board Figure 10 37 Expansion Connector 10 4 Control panel Figure 10 38 Control Panel Emulation The current project will be loaded to the chip but not programmed and will be ready for test on the emulation board Also user can change any configuration during the emulation process In the case when Power key and VDD key on the Expansion connector are turned off a warning message will pop up figure 10 39 Figure 10 39
10. Max 1850 00 S gt Silego Technology Inc www silego com 04 20 2015 99 S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 10 2 3 Logic Generator Figure 10 20 Logic Generator TP2 Key W Logic gener ator PIN2 Logic generator is used for generating the logic pulses Figure 10 21 Edit button allows configuring the signal it Signal Wizard Generator PIN 2 Logic Seque Shown period Auto 14 Start point 0 00 ms Stop point 3 e s Global linkage Repeat Cyclic Repeat count 2 Prestart state Low Prestart delay 0 00 ms End state Prestart state Output type Push Pull 4b 4 gt ep ip Pause type Last state Normal T Level 1 500 00 ms High 2 500 00 ms Low 3 500 00 ms High 4 500 00 ms Low 5 500 00 ms High 6 500 00 ms Low 4b 4b 4 a lt lt 4 4 Insert Remove Count Y Auto Apply Configuration options Mode Repeat T Level Insert Remove Count 2850 07 2400 06 2550 06 2700 07 2250 06 1500 04 1800 05 1950 05 2100 05 150 00 1050 03 2 00 i i i i i i 2 00 1 50 i i i i i 1 50 1 00 i i i i i 1 00 0 50 i i i i i i i 0 50 150 00 300 01 900 02 1050 03 1500 04 1950 05 2100 05 24
11. Output type High Z Pause type Last state Type Custom signal Set Signal Apply 0 00 150 00 300 01 1500 04 1650 04 1800 05 1950 05 1050 03 ms 3000 08 31 2100 05 2550 06 2700 07 Min 0 00 gt Max 1000 00 Custom Signal Settings Repeat One shot Cyclic Custom repeat option Data Set Signal change signal using Custom Signal Wizard Silego Technology Inc www silego com 04 20 2015 107 S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 10 2 5 Custom Signal Wizard Figure 10 30 Drawing Signal Arbitrary waveform CH Custom signal Wizard AX x FED Se Clear Add Point M Add Peak Continuous Ramp ar Remove Point Data panel d Import points Data X Value Y Value 200 00 300 00 700 00 800 00 900 00 1000 00 500 00 600 00 100 00 400 00 1 0 00 ms 3 20 V 2 40 07 ms 3 14 V 3 101 05 ms 3 18 V 4 153 30 ms 3 10 V 5 205 58 ms 2 96 V amp 235 20 ms 2 42 V 7 242 15 ms 2 18 V 8 259 97 ms 1 84 Y 9 318 82 ms 0 48 V 10 398 95 ms 1 50 V rj ir Jor OH CC 11 416 37 ms 2 19 Y 12 466 90 ms 2 85 Y 13 574 93 ms 3 22 V 14 738 68 ms 3 18 Y 15 803 12 ms 2 58 Y 200 00 00 00 500 00 600 00 700 00 00 00 900 00 1000 00 ms 100 00 400 00 16 832 7
12. 0 00 v PA 8 366 27ms 2 0 42V Sa 9 412 27ms S 2 74 V ie JL 10 483 82ms s 0 00 Le j 11 603 07 ms El 0 01 v Giele a Jegen eem 12 630 32 ms 2 1 53 SA 13 676 32 ms i 0 01 v SEA 14 839 76 ms I 0 01 v Sra S S 8 15 839 86ms t 1 06 v ae le JL 8 3 R 16 877 34 ms e 123v BED 17 89428ms S 2 81 e _ 7 Min T 1000 00 ms T 1000 00 ms Max T 393210 00 ms Available points 59 X 0 00 0 00 ie Put 3 au 933 56 Aa T Xi z tJ m an nea 12 me IZI 1 u aj al Figure 10 32 Continuous Ramp r P ma E Custom signal Wizard ole gt k Clear A Add Point Add Peak Continuous Ramp Jr Remove Point Data panel ry Import points Close x O mu O O CH Data E x Value Value E T 1 0 00 ms 0 00 Gel 4 00 dui s 2 185 69ms 1 64V sel 3 349 23ms gt 1 92V sed 4 432 71ms 210v sed 5 446 34ms S 0 01 GEJE 6 504 26ms F 0 00Y Se j 7 608 18ms f 1 66 asta 8 650 77 ms 2 0 57 y SEJE 9 706 98ms S 1 75 Se JL 10 764 91ms lossy Sit 11 841 57ms S 1894 12 896 08ms 0 88V sed 13 1000 00 ms 2 75 V S Min T 7 34 ms T 1000 00ms gt Max T 452191 50 ms Available points 68 X 0 00 2 Y 0 00 2 Put 3 E emgeet v
13. 10 117 0 ms__ 2 205V B 11 1300ms 215v EJ 12 1430 ms__ 2 2 24 V F 13 156 0 ms__ 2 2 34 V ES 14 1690ms gt 231 V m 15 1820ms 7 215V E 16 1950ms gt 201 v F c 17 2080ms Lv F 18 2210 ms__ 1 87 V EG 0 00 19 2240 ms i80V 20 2470ms S 1 75 V ES ms 21 260 0ms l170v 22 2720ms 7 165V E gt 23 2860ms Lev E T 1000 ms B Points 78 X 0 0 ms m Y 0 00 V F Put Se 24 2990ms 7 1 57 EG ae T P 950 00 600 00 700 00 750 00 900 00 550 00 250 00 100 00 450 00 500 00 100 00 150 00 200 00 650 00 Sos m ln E W hM FP 4k 3k AN AH AE d AF AM AE dL A EAU I ane D ane T ane D ane Ai ane Ai ane i ane ii 700 00 750 00 800 00 900 00 H 600 00 Li Li LILI 00 350 00 200 00 500 00 450 00 400 00 250 00 100 00 150 00 350 00 1000 00 A A dik Toolbar Clear clear data Peak Ramp Continuous Ramp ddaw modes Data panel turn on off the data table Silego Technology Inc www silego com 04 20 2015 50 S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 Figure 7 27 Peak EB Custom signal Wizard Clear A Peak r Ramp r1 Continuous Ramp f Data panel Data panel 800 00 LI D 95 10 A Value Y Value 0 0 ms 0 00 v ES 13 0 ms lt 0 00 v F 26 0 ms loov s 39 0 ms lt 0 00 v F 520 ms zlocov FE 650ms locov FF 78 0 ms lt 0 00 v
14. 6 6 6 e ee 6 e 2 e 1 02 Y OO Ia a on Uu Toolbar Clear Clear data Add Point Add Peak Continuous draw mode Ramp Remove Point Data panel turn on off the data table Close Close window with current signal Silego Technology Inc www silego com 04 20 2015 82 SILEGO Figure 8 32 Peak GreenPAK GreenPAK1 4 Designer 4 02 K A KE Custom signal Wizard J EJ Clear Add Point Ne Add Peak ri Continuous Ramp Remove Point a Datapanel Close ES 5 Data 3 j 3 3 3 3 X Value Y Value m de si S mi E is s ke d 1 0 00 ms 0 00 Y EN 2 27 26 ms 2 0 00 v Pr 3 42 59 ms e 1 17 y Giele 4 7836ms oev Hee 5 126 06 ms 0 00 y E Fm 6 156 73 ms 189v SENA 7 245 32 ms fed 0 00 v SEJ 8 36627ms 2 0 42V Giele 9 412 27ms z7v a 10 483 82 ms i 0 00 v ra a 11 603 07ms Heloo SEJE 12 630 32ms 1 53V SEJE 13 676 32 ms H 0 01 v EE GAME SIME 14 839 76 ms loo1v sec z E 2 8 g 8 8 8 8 8 15 839 86 ms E 1 06 v 2 LE 17 894 28 ms 281V SENA Min T 1000 00 ms T 1000 00 ms Max T 393210 00 ms Available points 59 X 0 00 ly 0 00 i Put 3 18 933 56 ms gt 1
15. Counter Control Data reg 750 737 Properties EN Mode Delay Range 1 16383 Delay time 0 1400 ms Formula Edge select Both e Clock source RC OSC Freq Silego Technology Inc www silego com 04 20 2015 143 S SILEGO o GreenPAK1 4 Designer 4 02 Programmable Delay Edge Detector reg lt 966 965 gt reg lt 968 967 gt Delay Value Selection Edge Mode Selection From Connection Matrix Output lt 74 gt gt Programmable d IN OUT Delay To Connection Matrix Input lt 44 gt reg lt 969 gt Delayed Edge Detector Output Silego Technology Inc www silego com 04 20 2015 144 N SILEGO GreenPAK1 4 Designer 4 02 INV 0 INV 1 Gate INV 0 Gate gt From Connection Matrix Output lt 90 gt To Connection Matrix Input lt 59 gt Silego Technology Inc www silego com 04 20 2015 145 S SILEGO Deglitch Filter GreenPAK GreenPAK1 4 Designer 4 02 a Filter_0 From Connection Matrix Output lt 21 gt 5 To Connection Matrix Input lt 42 gt gt R Filter_1 From Connection Matrix Output lt 22 gt C To Connection Matrix Input 61 gt gt reg lt 962 gt Properties Information Delay VDD Delay 1 8 V 200 ns 33 V 78 ns 55 V 53 ns Silego Technology Inc www silego com 04 20 2015 146 N SILEGO GreenPAK1 4 Designer 4 02 VREF Block Diagram External VDD 21 V 55V reg lt 981 gt ext vref acm
16. Note These buttons can only be controlled by generators with an installed Global Linkage flag Silego Technology Inc www silego com 04 20 2015 68 S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 8 2 1 General Options in a Signal Wizard Mode Figure 8 16 General Option General Generator PIN 3 Sine Shown period 200 00 500 00 600 00 700 00 900 00 1000 00 100 00 gt 400 00 Start point Stop point Global linkage Linked Repeat Cydic dert JPE e e e e 2 50 Repeat count i EEE EE ZE R enden 2 00 Prestart state jo 2 1000 R 2 5 0 ae eee End state Prestart state 0 50 Output type Pause type 0 00 High z Last state Signal Generator Settings Type Sine w Phase Custom phase 0 00 rad Amplitude 2 03 V g zero offset 2 03 V Period 1000 00 ms ES Frequency UC Hz Data Modify L 850 00 1000 00 100 00 500 00 All Start Fause Stop w Auto Apply ka Apply Generator generator selector Shown period Auto Custom 1T 2T 3T 4T set the period of a current generator to be displayed Global linkage Linked Unlinked if generator is linked it will be controlled by buttons Start Stop and Pause on the Emulator Repeat One shot Cyclic Custom repeat option Prestart state Low Start point VO High Z state before start Presta
17. Shown period Start point 0 ms Stop point 2000 ms Type Repeat Phase 0 Custom phase 0 00 rad Amplitude 1 67V Zero offset 1 67V Period ems JJ CH Lg Oh E Lg Cp 4 im a 00 a eM A B TIM O A Frequency 0 50 Hz moe O O O 4 4 4 O bo GT amp bi mi NN d Oh c Tmax scale Oh P JA 700 18 800 20 900 23 1000 25 1800 45 1900 48 2000 50 1000 Silego Technology Inc www silego com 04 20 2015 99 S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 The user can manually change the scale Figure 7 34 Manually Changing Scale EH Signal Wizard jj Options na 8 8 S E 8 8 Rg 7 8 2 Generator PIN 7 Sine v 1 in in D m E E Shown period Auto gt Start point O ms Ka a Stop point 2000 ms EZ Repeat Cydic ER Phase 0 gt Custom phase 0 00 rad Lei Amplitude 1 67V Zero offset 1 67 V zi S Period 2000 ms a 0 00 Frequency 0 50 Hz 3 02 2 69 2 0 1 68 w Auto Apply bJ Apply 1 34 Stat Pause Stop 0 00 600 00 950 00 nie ms 850 00 900 00 700 00 750 00 800 00 100 00 300 00 350 00 400 00 450 00 500 00 550 00 1000 00 Silego Technology Inc www silego com 04 20 2015 56 S SILEG
18. 2700 07 2850 07 z Min 0 00 i Max 1 Custom Signal Settings Repeat One shot Cyclic Custom repeat option Data Set Signal change signal using Custom Signal Wizard Silego Technology Inc www silego com 04 20 2015 81 S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 8 2 6 Custom Signal Wizard Figure 8 31 Drawing Signal Arbitrary waveform FB Custom signal Wizard JEg x Pa TAT Clear A Add Point M Add Peak TF Continuous Ramp dar Remove Point lt Datapanel Close Data X Value Y Value 300 00 900 00 1000 00 100 00 200 00 400 00 500 00 600 00 700 00 800 00 1 0 00 ms 3 20 V 2 40 07 ms 3 14 V 3 101 05 ms 3 18 V 4 153 30 ms 3 10 V 5 205 58 ms 2 96 V rj irj CHC amp 235 20 ms 2 42 V 7 242 15 ms 2 18 V 8 259 97 ms 1 84 V 9 318 82 ms 0 48 V 10 398 95 ms 1 50 V 11 416 37 ms 2 19 Y 12 466 90 ms 2 85 Y 0 50 13 574 93 ms 3 22 Y 0 25 14 738 68 ms 3 18 Y 15 803 12 ms 2 58 Y 300 00 500 00 600 00 700 00 800 00 900 00 1000 00 ms 200 00 400 00 100 00 16 832 75 ms 1 92 V YO ww 17 852 53 ms 18 918 12 Min T 14 39 ms T 1000 00 ms E Max T 412870 50 ms Available points 62 X 0 00 E Y 0 00 E Put 9 STE 1 31 se 6 e 2 e e se
19. ACMP3 From ACMPO s MUX output Selectable Gain From ACMP2 s MUX output L S Vref To Connection Matrix input lt 18 gt PIN15 aio en reg lt 563p AG PIN15_aio_en ON after if reg lt 913 912 gt 11 then 1 otherwi 0 100 us Delay PIN14 ACMA PIN12 ACMP1 M i m v reg lt 556 552 gt Properties x 1uA pullup on A input Mone w Hysteresis Disable ca Silego Technology Inc www silego com 04 20 2015 141 SS SILEGO en GreenPAK1 4 Designer 4 02 Counters Delay Generators CNT DLYO 4 5 6 reg 713 Delay IN gt reg 716 714 From Connection Matrix Output 15 Delay IN CNT ext cik Delay out Matrix Input 13 CNT DLYO Counter end Counter Control Data reg lt 730 717 gt Properties x Mode Delay A ama PI Range 1 16383 Delay time 0 1400 ms Formula Edge select pop SI Clock From RC OSC Clock source RC OSC Freg Silego Technology Inc www silego com 04 20 2015 142 N SILEGO GreenPAK1 4 Designer 4 02 Counters Delay Generators CNT DLY1 reg 733 PJ Delay_IN From Connection Matrix Output lt 16 gt Reset_IN Delay_out To Connection Matrix Input lt 14 gt reg 736 734 RC Osc 4 RC Osc 12 RC Osc 24 RC Osc 64 ext clock from CM Out lt 17 gt CNT DLY1 Counter end Count end out x 1
20. Alti Denn D Apply Silego Technology Inc www silego com 04 20 2015 131 SS SILEGO en GreenPAK1 4 Designer 4 02 Properties e Type Mode nSET nRESET option Initial O output polarity Nan inverted Q gt Silego Technology Inc www silego com 04 20 2015 132 SS SILEGO KN GreenPAK1 4 Designer 4 02 3 Bit LUT or Pipe Delay Macrocell reg lt 670 663 gt U rom Connection Matrix Output lt 60 gt O onnectio Matrix Output lt 61 gt To Connection Matrix input lt 32 gt 3 bit LUT8 our To Connection Matrix Input lt 41 gt rom Connection Matrix Output lt 60 gt gt ic N 16Flip flop Block CLK reg lt 666 663 gt To Connection Matrix Input lt 32 gt Silego Technology Inc www silego com 04 20 2015 133 SS SILEGO en GreenPAK1 4 Designer 4 02 Properties 3 bit LUT8 Pipe Delay Type LUT IN IN2 IN INO 0 00 0 Ge 0 O 0 1 ad 0 0 1 0 0 0 1 1 0 1 0 0 ad 0 1 0 1 Ze 0 11 1110 zaj D 1 1 1 a 1 0 0 0 1 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Properties 3 bit LUT Pipe Delay Type Pipe Delay OUTO PD num OUT1 PD num OUT output polarity Detailed Info Silego Technology Inc www silego com 04 20 2015 134 SILEGO GreenPAK GreenPAK1 4 Designer 4 02 lt ko 4 Bit LUT o
21. Figure 10 6 Pull Up Figure 10 7 Pull Down Silego Technology Inc www silego com 04 20 2015 91 SS SILEGO NR GreenPAK1 4 Designer 4 02 LED s Figure 10 8 10 9 Figure 10 8 Inverted Buffered LED Inverted Buffered LED Pull Up Inverted Buffered LED Pull Down Figure 10 9 Buffered LED Buffered LED Pull Up Buffered LED Pull Down Configurable Input Figure 10 10 Figure 10 10 Configurable Button The default connection can be set to either Upper connection or Bottom connection Click your mouse over the key U or B to change the value The user can configure each connection to VDD GND High Z or Pull Up Down Figure 10 11 Default Key Connection Upper connection Buttom connection Default connection To Upper connection Latch mode lt To Bottom connection b Set Push hot key LED Enabled LED Inverted Connect to Expansion Connec o Nic VDD GND Pull Up Pull Down Button Logic gene s Signal gene Silego Technology Inc www silego com 04 20 2015 92 GreenPAK GreenPAK1 4 Designer 4 02 Upper connection x OND HIZ Pull Dawn Default connection je SES Default connection Latch mode Latch mode Set Push hot key Sek Push hat key The switch has 2 modes Latched Unlatched which can be configured from the context menu or click your mouse over the key L to change the value Figure 10 12 Key Mode Upper connection Buttom connection Default
22. From matrix PIN 2 Combinatorial Logic 2 bit LUTO Reset Disable Bypass Edge active Edge detect mode Rising edge Information 18V 33V 50V min max min max min max V OH 1 660 2 100 2 900 V OL 0415 0 810 2 200 LOL 0 340 1 836 2 745 For more information please refer to the datasheet CNT3 DLY3 FSM1 en Detailed Special components Info te ply anc Show all Hide all Legend box Rules checker output Time Event Rule 22 39 13 G Fail PIN 5 OE is not connected OE from PIN 5 is not connected So output is configured as Push Pull 223913 YY Warning PIN 3 Incorrect Mode option PIN 3 has incorrect mode Mode option should be set as Analog In 223913 lt P Warning PIN 5 Resistor value is not Floating Floating resistor value is recommended for Push Pull mode to lower power consumption 22 39 13 gt Warning A CMPO output not connected Block s output is not connected to a circuit 22 39 13 Note POR ckeck Power Supply Control mode One of the analog blocks is turned on Check POR Power Supply Control mode settings for correct setting Checking is done with 1 fails 3 warnings and 1 notes In order to check the design click the Rules Checker button on the tool bar in Tools menu Rules Checker Window can be called by clicking Rules checker output in View menu Rules checker output consists of three parts l Event shows message type Fail Warning Note 2
23. PIN 8 PIN 9 PIN 10 Logic gates INVO Combinatorial Logic 2 bit LUTO 2 bit LUT1 2 bit LUT2 2 bit LUT3 3 bit LUTO 3 bit LUT1 3 bit LUT2 3 bit LUT3 3 bit LUT4 3 bit LUTS 3 bit LUT6 3 bit LUT7 DFF Latches DFF LATCHO A XJXIXIAIXIAIXJXIXIXIX Matrix 1 a Matrix 1 VO PADs VDD PIN 12 PIN 13 PIN 14 PIN 15 PIN 16 GND PIN 17 PIN 18 PIN 19 PIN 20 Logic gates INV1 z Combinatorial Logic 2 bit LUT4 2 bit LUTS 2 bit LUT6 2 bit LUT7 3 bit LUT8 3 bit LUT9 3 bit LUT10 3 bit LUT11 3 bit LUT12 3 bit LUT13 3 bit LUT14 3 bit LUT15 4 bit LUT1 i DFF Latches xi KR RR KRK KJK o lli v IH Show all Hide all Legend box Silego Technology Inc 04 20 2015 www silego com 9 LEGO GreenPAK GreenPAK1 4 Designer 4 02 Qu ko 3 1 1 Main Menu Main menu contains controls described below File New start new or open existing project from GPAK Launcher Open open existing project in GP Designer Clear clear project and select revision for specified chip Open in current open existing project for specified chip Save save current project Save as save current project in specified location Import NVM bits load configuration bits from text file Export NVM bits save configuration bits to text file Print start Print Editor referring item 4 Project Information Examples open examples directory Exit program close GPD
24. PW Pwr Dowr CIk inver Out range Reg 0 0 Reg 1 0 Reg 2 0 in EH HE 9 E minx sel HO mink sel di shared pa DCI PW Pwr Dowr CIK inver Out range mix Reg 0 0 e Reg 1 0 snare 5d Reg 2 0 in mink sel 0 p 4 a rm Silego Technology Inc 04 20 2015 30 www silego com SILEGO GreenPAK GreenPAK1 4 Designer 4 02 The user can add to the working area the custom figures including rectangle rounded rectangle ellipse etc Figure 5 7 Custom Figure The user can also customize the main paint parameters Figure 5 8 Paint Parameters 8 Drawing Settings Pen Width 3 EX Pen Style Dash v Pen Color black z Brush Style cross z transparent R turquoise violet wheat white You can see a small preview window which includes a painted rectangle with user parameters Silego Technology Inc www silego com 04 20 2015 31 SS SILEGO PA GreenPAK1 4 Designer 4 02 When the user adds a figure to the working area one can customize the figure size by dragging black points on the corners and sides The user can view it only by moving the mouse pointer up to the figure Figure 5 9 Work Area PIM 3 Mode Digital in est infout Resistor Pull Down Resistor value 300K O out Wu NU pM emque PIN 4 Mode Digital in ee A TT Resistor Pull Down Resistor value 300K Ope
25. Start Generators Stop Generators Test mode LETTET T Test mode button is used for turning on off the test mode Figure 7 40 Test mode Button Start Generators Stop Generators nek Start Generators Stop Generators Silego Technology Inc www silego com 04 20 2015 60 S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 Test mode can be used for connecting or disconnecting a chips I O pads to stimulus areas configured by the user The representation of test mode is illustrated below Emulation process can be started with the Start emulation button and will be indicated with the white logo in GreenPAK Figure 7 41 Start Emulation EH GreenPAK 1 Emulatio Emulation Test mode config Start emulation Default Stop emulation Programming Log TUN IN 7 14 32 47 Initialization Step 1 Nj 14 32 47 IO manager initialization 14 32 47 IO manager Connecting to interrupt channels PIN 8 a PIN 7 14 32 47 IO manager state changed STARTING PIN 6 14 32 47 IO manager state changed GND RUNNING 14 32 47 IO manager successfully started GreenPAK 14 32 47 Initialization succeeded ONO ENI 14 32 47 Initialization Step 2 a gt gt gt gt m 14 32 47 IOHID checker initialization IN 6 14 32 47 IOHID checker Connecting to interrupt channels 14 32 47 IOHID checke
26. aeg Reg 1 0 Vref Bandgap pga od Reg 2 0 selector Pwr Down inf Force Disable ouf vref analog ext clk 1 w In mosi Pwr Dowr je mix lk inver B 19979 out range S2P s2ph ech ix Reg 0 0 76 Mode S2P 58 Self Reg 1 0 shared g sclk Bi Reg 2 0 3 ALA J Silego Technology Inc www silego com 04 20 2015 28 SN SILEGO NR GreenPAK1 4 Designer 4 02 Figure 5 3 Preview Window TE Print Editor BAX File Edit View 2 a lt A A m X Lu Print Preview Save image Snapshot Rotate Left Rotate Right Flip Horizontal Flip vertical Add Text AddRect Add Ellipse Graphics settings LJO PADs DC Combinatorial Logic DFF Latches PW Y Analog Comparators Digital Comparators Y Counters Delays w Special components In Pwr Dowr mix lk inver se 0 Out range mix Reg 0 0 Se Reg 1 0 shared od Reg 2 0 ul Tul CUu a e o a CD D O O U o z zi op z 3 e k lt o tb D lt un o EN CU o D o Q a D g 0X HIE EH pua a BuIS 3pow 195 TI o ke o o o a o ied DCI PM tie Pwr Dowr mir lt Clk inver capture SES Out range er Reg 0 0 ser Reg 1 0 _ shared bi Reg 2 0 par a NEU CU MA User can move lines and points to correct odd angled appearance
27. d My Computer My Recent My Network Places Documents Desktop GEN WN rwd My Documents wr DEIER LU My Computer ka LZ My Network File name project Places Save as type PDF file pdf z poi m S Silego Technology Inc www silego com 04 20 2015 36 SS SILEGO PA GreenPAK1 4 Designer 4 02 6 Rules Checker This tool allows checking current project errors for example incorrect block connections or settings Rules Checker has three types of messages rai this message is generated when there is a significant error in design that will not work under any conditions lt P Warning this message is generated when one or more blocks may contain incorrect connections or settings in the design This does not mean that there is an error It only notifies the user to check the connections or settings of the blocks Note this message is generated to remind the user to check for correct settings Figure 6 1 Rules Checker Output Bowen AC III I IG a a A 2 ieee File Edit View Tools Help lw a A A cz Fs e Dl x x x A A lt Rn s i L New Open Save Print SetWire Erase Wire Rotate Left Rotate Right i i i j Setlabel Erase Label Rules Checker Mini Emulator Emulator Lock NVM Properties Components Datasheets Examples 1x push pull Resistor value 300K Initial state Output floating OE
28. 0 00ms End state Pre start state 4 4b Qp at Output type High Z Pause type Last state 4 Signal Generator Settings Type Sine 5 00 4 5 i i 4 50 Phase o 4 0 9 NUN C UNI cuc ETE dia 3 50 Custom phase 0 00 rad ga 3 00 i i i i i i i i i r 2 50 te Tmaxscale 0 1000 1 0a Dna plenu FA 2 00 1 50 1 00 0 50 0 00 TP6 PING Amplitude v l amp 2 75 V Zero offset 2 95 V Period 1 000 00 ms 0 00 Frequency 1 00 Hz ms c 700 00 750 00 800 00 900 00 950 00 1000 00 100 00 150 00 450 00 500 00 550 00 600 00 6 Data Modify Auto Apply ee Apply Al Start Pause Min 0 00 B Max 1 Silego Technology Inc www silego com 04 20 2015 97 SI LEGO GreenPAK GreenPAK1 4 Designer 4 02 Figure 10 18 User Can Change the Scale Manually Lo w Zeg yL qui 0 00 General BU DU 40 00 E 03 ra aL EZ Ls n iC ber 12 1110 00 647 50 740 1295 148 18 Generator PIN 3 Sine ROG AUD AUN QS ME TC MN M zoo oo z vo o o oa a Start point 0 00 ms ia m a sinp paii 3 00 ES A AO A A REM w Global linkage PEU its l i 3 ee S M ee R Repeat exu cu ccm c cau use AI fiM 1 00 2 3 2 3 2 S E a 3 2 S Prestart state Low eae We ES oe RE ee ee rr
29. 2100 05 150 00 1050 03 1500 04 1 50 1 50 1 00 1 00 0 50 0 50 nnno We ms 150 00 600 0 900 02 1050 0 1200 03 1350 03 1500 04 1650 04 1800 05 2100 05 2250 06 1950 05 2400 06 2550 06 2700 07 2850 07 3000 08 Start Pause Auto min 0 00 2 Max 1 Normal lnvert One shot Cyclic Custom signal mode repeat option sets duration of level insert pulse to the entered position remove pulse from the entered position pulses count Silego Technology Inc 04 20 2015 www silego com 74 S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 8 2 4 Clock Generator Figure 8 22 Clock Generator A high frequency logic generator which generates a 12 MHz frequency signal can be connected to any pin Each Clock generator should be connected to its pattern collection of generators settings There are 6 total patterns LO L1 L2 for the left side of pins PIN 2 3 4 5 6 and RO R1 R2 for the right side PIN 8 9 10 11 12 All the patterns have inter independent settings and can be used by a random quantity of Clock generators connected up to the pins on the corresponding side Connections configuration is indicated in the generator s name connected to pin For instance a Clock generator which is connected to pin 2 and LO pattern will have a CLO index Clock Left Pattern number 0 Configuration Options Pattern number Pattern LO L1 L2 RO R1 R2 c
30. F 910ms loov E 1040ms loov 10 117 0 ms Z 0 00 v F 11 1300ms Z 159V FE 5 900 00 55 600 00 65 500 00 5 350 75 l 1 1 E ET Bd ILI 0 00 DO dk sh 350 00 l EEIEIEE 900 00 75 5 600 00 5 400 l em QUIL 1 6 WD D sJ M Ln BR Uu N HH dj ak Sk db Clear A Peak r R amp r1 Continuous Ramp Data panel Data FOO UU d Ld 800 00 a LI OK 300 00 200 00 1 L 1 1 600 00 X Value Y Value 0 0 ms lt 0 00 v F 13 0 ms J 0 00 v E 26 0 ms 0 00 v Fa 39 0 ms 1 0 00 v ES 52 0 ms 0 00 v FA 65 0 ms IE 0 00 v E 78 0 ms EI 0 00 v Fa 91 0 ms 0 00 v Fa 104 0 ms Z 0 00 v 10 1170ms oov X E T 1000 ms Points 78 X 0 0 ms F Y 0 00 v F Put ki 11 1300ms__ E 0 00 v EE 5 AE EN E 450 00 a 550 00 65 HA 75 a 5 dH dl ib ik CO Jd ik 1 E 1 E 900 00 600 00 35 400 450 00 50 00 600 00 100 55 i 78 D 5 6 L g 1 o Oo Ch Ln E W Ep Ji dk AF 4r ih Silego Technology Inc www silego com 04 20 2015 51 SI LEGO GreenPAK GreenPAK1 4 Designer 4 02 Figure 7 29 Continuous Ramp LE Custom signal Wizard Data panel 800 00 900 00 1000 010 600 00 750 00 X Value Y Value 0 0 ms s 0 07 v F i30ms loz36v E 260ms osv s 330ms zlogv G 520ms Lv E 65 0 ms s 1 56 v ES 7 amp 0 ms Z 18
31. Figure 5 4 Work sheet pwr down inp ch 1 inp ch 2 ADC Mode Single end out clk inn Gain 0 5 Vref VEG 1 796 v par data Reference DAC Mormal feedback ser data 2 ch select pga ext vref pwr down PWM ext clk Output mode P output gut duty cycle nar 0 99 6 outp ex c Delay1 Dead band time 8 ns Counter data 1 i outn Force Power on Disabled Input Enabled Edge select Both Silego Technology Inc www silego com 04 20 2015 29 S SILEGO 5 1 Working Area Working area can be zoomed in or zoomed out User can add a text label to the schematics using the text tool Figure 5 5 Text Label Change Font Edit Remove 4 Rect b vide a Xe GreenPAK GreenPAK1 4 Designer 4 02 Figure 5 6 View with Text Label E Print Editor Sex File Edit Yiew t Save image Ga Ca A m Add Text Add Rect Add Ellipse E A Rotate Left Rotate Right Flip Horizontal m Print Led a Preview Snapshot Flip vertical oDue PIED A Lo Jndul ures Jed Some text UMOCJ Md 401283 8S debpueg Ja 1I G 0X UIED EH pue e Buls 3POIN 488 e qesiq 92104 jno qui mos capture S2P Mode S2P ncsb selk par Graphics settings W U gt z Y 1 0 PADs Combinatorial Logic DFF Latches Analog Comparators Digital Comparators Counters Delays Y Special components ine DCI
32. Key for Push action The assigned key will simulate mouse click over the key Figure 8 13 Choosing Hot Key Upper connection Bottom connection L GND Default key connection Key mode Set Push hot key 4 KEY 1 KEY 2 N C KEY 3 Set To VDD KEY 4 Set To GND KEY 5 Pull Up KEY 5 Pull Down KEY 7 KEY 8 Set Configurable Button KEY 9 Logic generator KEY U Clock generator Custom rawr ceHinac Fr k The user can assign the same hot key to multiple Switches allowing a single hot key the ability to change the key values of all the Switches at once Silego Technology Inc www silego com 04 20 2015 67 SS SILEGO PA GreenPAK1 4 Designer 4 02 8 2 Generators To each chip there can be connected 3 types of generators Signal generator Logic generator and Clock generator Figure 8 14 Choosing Generators N C Set To VDD Set To GMD Pull Up Pull Down Set Configurable Button Signal generator Logic generator Expansion ci Clock generator LED Copy settings to Exchange settings with b Each generator has its own settings For the settings window to appear press the Edit button co On the left the options table is divided into 2 groups 1 General applied to all types of generators and 2 Special for each generator To start the generators use the buttons below the Emulator Figure 8 15 Managing Buttons Start Pause Stop Generators Generators Generators
33. S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 Figure 7 20 Trapeze Trapezoid Generator PIN 6 Trapeze Iri v Shown period Auto v Start point 0 ms Stop point Type Trapeze Mode Normal Repeat Cydic Loop count 1 OG O ly Trapeze settings Mode Normal Invert signal mode Repeat One shot Cyclic repeat option Umax Umin max min voltage level T1 T2 T3 T4 duration of trapeze Figure 7 21 Duration of Trapeze Trapezoid 00 ms Silego Technology Inc www silego com 04 20 2015 46 GreenPAK GreenPAK1 4 Designer 4 02 S SILEGO DO 058 I l I l 1 I I I l 1 I l I I 1 I I I I 1 I I I Dao OOF a a OSE a GER LILI DS ipo CH n E E rT om iD KC ama A od A A ri Figure 7 22 If T3 1 Signal is a Triangle 9 NId www silego com 00 gas a6 tt ITI Do n Do aar UO OS Figure 7 23 If T3 1 and T2 2 or T4 2 Signal is a Sawtooth Silego Technology Inc 04 20 2015 47 S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 Figure 7 24 Sine 100 05 600 30 800 40 Start point O ms Stop point 1000 ms 0 00 rad _1 67 V 1 67 V 1000 ms 1 00 Hz 100 05 smo L
34. Silego devices GreenPAK Universal Dev Board 1 ID 0x203 In use GreenPAK Universal Dev Board 1 ID 0x209 Blink Selected board blinks to notify its selection Refresh button Refresh button updates chip information in bottom right corner of the Emulator Silego Technology Inc www silego com 04 20 2015 114 SS SILEGO en GreenPAK1 4 Designer 4 02 Socket Test This feature allows testing the socket connectors to ensure that it works properly and doesn t have influence on emulation or reading programming processes Figure 10 44 Socket Test Results GreenPAK Universal Board O Default Oe M GreenPAK Universal Dev Board 1 ID 0x203 In use Blink S Silego Technology Inc www silego com 04 20 2015 115 SN SILEGO en GreenPAK1 4 Designer 4 02 11 Designing Overview 11 1 SLG4672x Properties Interpretation Pin2 90 kQ pull up en m E E 900 kQ o LL C Nc E 1 QW OO CD UO floating 01 10 kQ 10 100 kQ 11 1 MO Non Schmitt Trigger Input 01 Digital In with Schmitt Tigger smt_en 1 10 Low Voltage Digital In mode Iv en 1 11 analog IO mode Digital In Low Voltage Input D Input Mode 1 0 00 Digital In without Schmitt Trigger wosmt en 1 Analog IO Silego Technology Inc www silego com 04 20 2015 116 SN SILEGO en GreenPAK1 4 Designer 4 02 Properties Ed EEE KN I
35. Trapezoid Triangle Saw E Signal Wizard Options General Generator PIN 11 Trapeze Tr A E 1000 05 100 01 1 500 03 Shown period Auto Start point 0 00 ms ES Stop point 1000 05 ms Global linkage Linked zil Repeat Cydic Repeat count 3 Prestart state Low Prestart delay End state Prestart state Output type High z Fause type Laststate ZS Signal Generator Settings Trapeze Triangle 5 Normal T 4 08 V 0 00 v ES 250 00 ms ES 250 00 ms a 250 00 ms a 250 00 ms E Auto Apply kej Apply A Start Pause Stop auto Min 0 00 max 0 5 F Trapeze Settings Mode Normal Invert signal mode Umax Umin max min voltage level T1 T2 T3 T4 duration of trapeze If T3 1 signal is a triangle If T32 1 T2 20r T4 2 signal is a sawtooth Silego Technology Inc www silego com 04 20 2015 19 S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 Figure 8 29 Duration of Trapeze Trapezoid LE Signal Wizard Options Ln z mn u 8 Generator PIN 11 Trapeze Tr gt a r S Shown period Auto Start point 0 00 ms E Stop point 1000 05 ms Fa Global linkage Linked v Repeat Cydic Se Repeat count 2 ad Prestart sta
36. Y Value 300 00 500 00 600 00 700 00 800 00 900 00 1000 00 200 00 400 00 100 00 1 0 00 ms 0 00 V 2 12777ms A 1 97 3 328 79ms 2 26v 4 432 70ms 2 0v 5 446 32ms El oozy 6 50425ms S o 00 7 608 18ms S 166v 8 650 77ms X 2 D 56V 9 706 98ms 2l1 74v 10 764 90ms 0 53V 11 841 58ms 2 1 s9v PEER HH eJ De je Ij C 12 896 08ms el 0 88 v ap ab ab ab ab ab ab ab ab a a gt a gt ap 2 75 V 200 00 00 00 700 00 800 00 900 00 1000 00 500 00 600 00 100 00 400 00 Min T 7 34 ms T 1000 00 ms E Max T 452191 50 ms Available points 68 X 300 00 is Y 2 00 Si Put 3 8 2 7 VDD Power Signal Generator Figure 8 36 VDD Power Signal Generator Simple signal generator for VDD with its own options Silego Technology Inc www silego com 04 20 2015 84 SS SILEGO en GreenPAK1 4 Designer 4 02 8 3 Expansion Connector User can connect disconnect I O pads of GreenPAK with the expansion connector on the board Figure 8 37 Expansion Connector Expansion connector 8 4 Control Panel Figure 8 38 Control Panel Emulation The current project will be loaded to the chip but not programmed and will be ready for the test on the emulation board The user can also change any configuration during the emulat
37. and complete control over the routing and configuration options GreenPAK Designer will be used as a general name for GreenPAK 1 Designer GreenPAK 2 Designer GreenPAK 3 Designer and GreenPAK 4 Designer GreenPAK Designer has an integrated programming tool that allows you to program configured design into your GreenPAK chip With this tool you can also read an already programmed chip and export its data to the Designer Designer will generate a project which has the same configuration as chip To start working with GreenPAK Designer please take the following steps Download and install GreenPAK Designer software Select what components you need Interconnect and configure components Specify the pinout Test your design with the Emulation Tool or Mini Emulation tool for GreenPAK 2 chip Use GreenPAK 1 4 development kit with GreenPAK 1 4 Programmer GreenPAK 1 4 Emulation Tool or GreenPAK 1 Mini Emulation Tool to program your project into GreenPAK 1 GreenPAK 2 GreenPAK 3 and GreenPAK 4 chip You can find your kit on Silego s webstore 1 2 System requirements PC System Configuration Minimum System Requirements for Silego GreenPAK Designer CPU 1800MHz oystem Memory RAM 512MB Graphics Card 128MB Free Hard Disk Space 100MB Operating System Windows XP Vista 7 8 x86 x64 MAC OS X v10 5 or Ubuntu 12 04 Silego Technology Inc www silego com 04 20 2015 5 9 LEGO GreenPAK GreenPAK1 4 Desig
38. can be configured to work in the following modes Digital in with Schmitt trigger Digital in without Schmitt trigger Low voltage digital in Analog I O _ 1x push pull _ 2x push pull _ 1x open drain _ 2x open drain GreenPAK 2 chip has nine PGIO PIN3 4 5 6 8 9 10 11 12 and one GPI PIN2 pin components These components can be configured to work in the following modes _ Digital in with Schmitt trigger _ Digital in without Schmitt trigger _ Low voltage digital in Analog I O _ 1x push pull _ 2x push pull _ 1x open drain _ 2x open drain _ Analog in and open drain out GreenPAK 3 4 chip has seventeen PGIO PIN3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 and one GPI PIN2 pin components These components can be configured to work in the following modes Digital in with Schmitt trigger Digital in without Schmitt trigger Low voltage digital in _ 1x push pull _ 2x push pull _ 1x open drain NMOS 2x open drain NMOS _4x open drain NMOS _ 1x open drain PMOS _ 2x open drain PMOS 1x 3 State Output _ 2x 3 State Output _ Analog input _ Analog output Also Pull Up Pull Down resistors are configurable To configure the pin component open its parameters to set a desired mode and pull up pull down resistor I O pin components have input IN output OUT and output Silego T
39. cause changes in other blocks Component settings are available at component Properties panel Figure 3 8 which appears after double clicking on the component Properties panel consists of three parts Properties Connections and Information Properties section contains all settings of a selected component Connections section allows you to configure connections that couldn t be made using wiring tool Information section contains short information about parameters of selected component After making changes in Properties panel click the Apply button to save changes If you do not click the Apply button and select another block a save changes message box will appear Figure 3 8 Properties Panel Properties x 1uA pullup on A in t U Y Hysteresis Disable 4 4 Low bandwidth Enable 4 IN gain Disable Connections IN source PIN 13 4 4 IN source 50 mV Set power control settings T zd kel Apply Reset settings to default Reset connections to default Cancel Reset connections and or settings to default this option allows to reset NVM bits components properties wire connections from to component Silego Technology Inc www silego com 04 20 2015 17 SN SILEGO mE GreenPAK1 4 Designer 4 02 3 4 Specifying Interconnections You can interconnect chip components to achieve the necessary functionality To make a connection please select Set wire sw on the Wire toolbar or fr
40. connection atch mode Ei lt Not latched Set Push hot key Latched LED Enabled LED Inverted Connect to Expansion Congiector Nic VDD GND Pull Up Pull Down Button Silego Technology Inc www silego com 04 20 2015 93 SS SILEGO PA GreenPAK1 4 Designer 4 02 User can assign Hot Key for Push action The assigned key will simulate mouse click over the key Figure 10 13 Choosing Hot Key Upper connection Buttom connection Default connection Latch mode Set Push hotkey kt Custom key LED Enabled Key Q LED Inverted Key W Key E Y Key pi Nic Key T Key Y Key U Key T Pull Up Key O Pull Down Key P Connect to Expansion Connector VDD GND Button Key A Key S Key D Key F Key G Key H Key J Key K Key LU Key Logic generator User can assign the same hot key to other Switches which allows changing the key values of all the Switches with the same hot key at once Silego Technology Inc www silego com 04 20 2015 94 S SILEGO 10 2 Generators GreenPAK GreenPAK1 4 Designer 4 02 To each chip there can be connected 2 types of generators Logic generator or Signal generator Figure 10 14 Choosing Generators LED Enabled LED Inverted Connect ta Expansion Connector MIC WDD GND Pull Up Pull Down Button Logic generator Signal generator Each generator has its own settings For the settings wi
41. more than one generator at the same time Figure 8 25 Sets Start Pause Hot Key Start generator Pause generator L Stop generator Properties lt Global linkage Pause type Set Start Pause hot key gt N C Y KEY 2 Set To VDD Set To GND Pull Up Pull Down Set Configurable Button Signal generator Logic generator Clock aenerator Silego Technology Inc www silego com 04 20 2015 76 S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 Signal Generator Settings Type Const voltage level Sine User Defined type of waveform Constant Value U voltage level Figure 8 26 Constant Value 100 01 500 04 50 04 600 05 50 00 Generator PIN 3 Constant Vo g 55 Shown period Auto Start point 0 00 ms Stop point 1000 08 ms Global linkage Linked 0 50 T nan SE E 0 00 0 00 Repeat Cydic Repeat count 2 Prestart state Law Prestart delay 0 00 ms F End state Prestart state CYWAIN DE High Z 4 00 p d i 5 E z q r 5 5 B g E 4 00 3 5n icem areca A RE ATENE eee eae FETH 2 EN PES DOE Last state JF ue ee EH ae T V mmm Son SE Ee DEEN 2 00 i Dr es i i i E um ca I i 2 00 V a 000 0 ee VET O O O
42. the blocks The Help button on the property panel of each block provides the same information about the current block Figure 3 20 Help Window File Edit View Tools Options Help ds yy Vd Bb X BIN New Open Save Print Set Wire Erase Wire Set Label Erase Label Rules Checker Emulator Project Settings Project Info Properties an DA 1 2 rn 4 Ty 1 FARS Designer V4 U1 T T r gt 4 8 e Components NVM Viewer Datasheet Examples User Guides A Rotate Left 7 Rotate Right Flip Horizontal Flip Vertical Align Horizontal Align Vertical GreenPAK3 Reference SLG46721V Project settings PIN GreenPAK3 Reference SLG46721V ms LUT Look up Table LUT DFF LATCHes Detailed information Y PIN 15 PIN 17 S Y PIN 18 Logic xe cui Y PIN 19 LUT CNT DLY Highly Versatile Macro Cells Y PIN 20 Programmable Delay Edge Detector Read Back Protection Read Lock Logic gates Additional Logic Functions 1 8 V 596 to 5 V 10 Supply INVO ACMP Analog Comparator 1 8 V 5 to 3 3 V 1096 Supply when using the 2MHz internal OSC INVi Voltage Reference VREF Operating Temperature Range 40 C to 85 C Combinatorial Logic Power on reset POR RoHS Compliant Halogen Free 2 bit LUT4 RC Oscillator RC OSC 20 pin STOEN 2 x 3 x 0 55 mm 0 4 mm pitch i tions x Personal Computers and Servers cade PC Peripherals 3 bit LUT5 Consumer Electronics 3 bit LUT6
43. 0 950 00 10 Silego Technology Inc www silego com 04 20 2015 53 S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 7 3 General Options in a Signal Wizard Mode Figure 7 32 General Options 100 05 600 30 Generator PIN 7 Sine Shown period Auto Start point O ms L qp Stop point 1000 ms Custom phase 0 00 rad f sm Amplitude 1 67V Pb AE o gt e 1 01 Zero offset 1 67 V 0 67 0 34 Period 1000 ms 0 00 3 36 Frequency 1 00 Hz 3 02 2 69 Data Modify 2 35 2 01 Xd a a ae a make mines Gre 1 34 Auto Apply J Apply Se 0 0 67 Start J Pause Stop 0 34 0 00 100 05 150 08 600 30 Auto Min 0 gt Max 1000 KG General Settings Generator generator selector Shown period Auto Custom 1T 2T 3T AT set the period of a current generator to be displayed Start point start point generating signal Stop point stop point generating signal Silego Technology Inc www silego com 04 20 2015 o4 S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 7 4 Period Modes AUTO Mode All generators with AUTO option have one scale this scale MAX period of all generators with AUTO option Figure 7 33 Auto Mode 2000 50 100 10 1000 25 1600 40
44. 0 SLG46116 SLG46117 SLG46620 e Whats New page with information about current projects and chips application e Recovery Files page with restored files after crash or freeze Files was saved with Autosave feature in predetermined time intervals New Project starts new project for selected chip revision or double click with left mouse button on selected chip revision icon Open Project opens existing project automatically selects chip revision Close close GreenPAK Designer launcher Silego Technology Inc www silego com 04 20 2015 7 SN SILEGO en GreenPAK1 4 Designer 4 02 3 GreenPAK Designer This section describes GreenPAK Designer application and its features 3 1 GreenPAK Designer Interface Overview GreenPAK Designer consists of main menu toolbar main work area output window properties panel and components list see Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 1 GreenPAK 1 User Interface E A GreenPAK 1 Designer v1 04 46 nm m ma AAA EN Soe in L a e Properties Components Datasheets Examples User Guides File Edit View Tools Help a Bx Y B a A lt WW amp 3 New Open Save Print Set Wire Erase Wire Rotate Left Rotate Right Flip Horisontal Flip Vertical Set Label Erase Label Rules checker Programmer Emulator Components List x 1 0 PADs Mode Digital in without Sd v Resistor Pull Down Resistor value 3
45. 00 06 2850 07 rre ims 2550 06 2700 07 3000 08 1650 04 1800 05 2 lt Start Pause e Auto Normal Invert signal mode One shot Cyclic Custom repeat option sets duration of level insert pulse to the entered position remove pulse from the entered position pulse count Silego Technology Inc 04 20 2015 www silego com 100 SS SILEGO PA GreenPAK1 4 Designer 4 02 10 2 4 Signal Analog Generator Figure 10 22 Signal Generator Signal generator is used to generate analog signals Constant Voltage level Sine Trapeze Trapezoid Logic pattern and User defined Logic and signal generators can be started paused stopped using orange buttons or through the context menu The user can also assign the hot keys for start pause More than one generator can use the same hot button to start pause at once This is how to start more than one generator at the same time Figure 10 23 Sets Start Pause Hot Key gt tart Edit Global linkage Custom key lt Key Oo Key W Key E Key R Key T Key Y Key U Key T Key O Key P Connect to Expansion Connector Signal generator Key A Key S Key D Key F Key G Key H Key J Key K Kev L Key Silego Technology Inc www silego com 04 20 2015 101 S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 Signal Generator Settings Type Const voltage level Trapeze Logic pa
46. 00K 4 ab 4P OE None Combinatorial Logic 2 bit LUTO 2 bit LUT1 3 bit LUTO 3 bit LUT1 tel DFF LATCH 1 DFF LATCH 2 Analog Comparators A 0 Show All Hide All Legend box Silego Technology Inc www silego com 04 20 2015 8 SILEGO GreenPAK1 4 GreenPAK Designer 4 02 Figure 3 2 GreenPAK 2 3 User Interface m SLG46721 GreenPAK 3 Designer v3 00 01 File Edit View Tools Help BAe v a a 8 i x EWIE j m 9 New Open Save Print Set Wire Erase Wire Rotate Left Rotate Right Flip Horisontal Flip Vertical Set Label Erase Label Rules Checker Emulator Project Settings Properties Components Datasheets Examples User Guides Properties PIN 3 I Oselection Digital Input Input made pi talin without Sc Output mode Mons a OE 1 Resistor Pull Down H Resistor value 1M gt Information Electrical Specifications 164 3 34 SDV min max minfmax min max VIH 1 100 1 780J 2 640 VIL 0 690 Jan 1 840 de j z af de Em f ud p i LEM a mum Components List E3 Components 1 0 PADs VDD PIN 2 PIN 3 PIN 4 PIN 5 PIN 6 PIN 7 PIN 8 PIN 9 PIN 10 GND PIN 12 PIN 13 PIN 14 PIN 15 PIN 16 PIN 17 PIN 18 PIN 19 PIN 20 Logic gates INVO INV1 Combinatorial Logic 2 bit LUT4 2 bit LUTS 3 bit LUTO 3 bit LUT1 3 bit LUT4 3 bit LUTS 3 bit LUT6 3 bit LUT 3 b
47. 2 Period Frequency 0 34 0 00 ms amp Auto Min 0 max 45 B 3 Silego Technology Inc www silego com 04 20 2015 58 SS SILEGO PA GreenPAK1 4 Designer 4 02 7 9 Expansion Connector User can connect disconnect I O pads of GreenPAK with the expansion connector on the board Figure 7 37 Expansion Connector E E U Expansion connector 7 6 Control Panel Emulation Start emulation load project to the chip and start the emulation Stop emulation stop the emulation Test Mode Configuration The user can save current configuration of a test mode to the project file Programming Read Program chip with the current project using the emulation board Figure 7 38 Emulation Programming Emulation Test mode config Start emulation Default Stop emulation Save Delete Programming Read chip Program Silego Technology Inc www silego com 04 20 2015 59 S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 7 7 Test Mode and Emulation Process Figure 7 39 Test Mode 1 1 em em emm emm emm el ko m mz u sz u 1 T VDD 3 3V l PIN sz mm 1 I PIN z PIN s En GreenPAK 1 LT T sm mw m em em emm oe el Expansion connector
48. 20 GreenPAK GreenPAK1 4 Designer 4 02 Non Schmitt Trigger Input Low Voltage Input o 900 kQ OD LL Res sel 1 0 00 floating 01 10 ko 10 100 kQ 11 1 MQ www silego com N SILEGO mE GreenPAK1 4 Designer 4 02 Properties Silego Technology Inc www silego com 04 20 2015 121 S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 Register OE IO Structure with Super Driver for Pins 10 12 Mode 2 0 000 Digital In without Schmitt Trigger wosmt en 1 001 Digital In with Schmitt Trigger smt en 1 010 Low Voltage Digital In mode Iv en 1 011 analog IO mode 100 push pull mode pp en 1 101 NMOS open drain mode odn en 1 110 PMOS open drain mode odp en 1 111 analog IO and NMOS open drain mode odn en 1 and AIO en 1 Non Schmitt Trigger Input Low Voltage Input Analog IO 4 Digital Out O N A S1 4 N OC S0 10 kQ Floating g 5 00 floating 01 10 ko Silego Technology Inc www silego com 04 20 2015 122 N SILEGO mE GreenPAK1 4 Designer 4 02 Silego Technology Inc www silego com 04 20 2015 123 N SILEGO mE GreenPAK1 4 Designer 4 02 2 Bit LUT reg lt 590 587 gt From Connection Matrix Output lt 70 gt i To Connection Matrix Input 37 2 bit LUT4 our From Connection Matrix Output lt 71 gt Silego Technology Inc www silego com 04 20 2015 124 N SILEGO mE GreenP
49. 4 Lo R 3 m lt E 49 User Guides Rotate Left RotateRight Flip Horisontal Flip Vertical Set Label Erase Label Rules Checker Mini Emulator Emulator Lock NVM Properties Components Datasheets E Legend box e Silego web site e Software and documentation B Live Support Skype L Datasheets Combinatorial Logic Updater ee 2 bit LUTO About this program No updates are available You are using the latest version A CMP1 Digital Comparators PWM DCMPO PWMO DCMP 1 PWM1 DCMP2 PWM2 Counters Delays CNTO DLYO CNT1 DLY1 Y2 FSMO CNT3 DLY3 FSM1 Special components ADC P DLY Pipe delay POR S2P VREF Show all Hide all Legend box 2 You can also find the latest GPD version at Software amp Docs page of Silego web site For the best user experience keep your GreenPAK Designer up to date Feel free to email suggested updates to the developer to improve this program Please refer to About this program section of Help menu Silego Technology Inc www silego com 04 20 2015 23 SS SILEGO NR GreenPAK1 4 Designer 4 02 3 9 Help Window To view information about a specific block select the block and click Help from the Help menu or press the F1 button A window will list the information about each block short info Press the detailed info button for more detailed information Figure 3 20 If you don t select any block you will be shown the information about all
50. 46400V Rev B GreenPAK2 2 SL G46400V GreenPAK2 2 What s New WB SLG46200V GreenPAK1 Datasheet Product page Get samples Contact us STOFN 20 Description The SLG46721V provides a small low power component for commonly used mixed signal functions The user creates their circuit design by programming the one time Non volatile Memory NVM to configure the interconnect logic the I O Pins and the macro cells of the SLG46721V This highly versatile device allows a wide variety of mixed signal functions to be designed within a very small low power single integrated circuit The macro cells in the device include the following Four Analog Comparators ACMP Two Voltage References Vref Nine Combinatorial Look Up Tables LUTs Two 2 bit LUTs Seven 3 bit LUTs Nine Combination Function Macrocells Four Selectable DFF Latch or 2 bit LUTs Two Selectable DFF Latch or 3 bit LUTs One Selectable Pipe Delay or 3 bit LUT Datasheets Two Selectable CNT DLY or 4 bit LUTs Five Counter Delay Generators CNT DLY One 14 bit delay counter Examples e Nna 14 hit dalau rnuntar with avtarnal clack racat User Guide New S Open Close GreenPAK Designer launcher e Welcome welcome page with short information and tips for new users e Develop on this page user can select chip revision to start new project for required revision SLG46200 SLG46400 SLG46400 Rev B SLG46721 SLG46722 SLG46110 SLG4612
51. 5 ms 1 92 V 17 852 53 ms 1 31 Y WUJWUJU 1 02 Y CEA bab ab ab ab ab ab ab ap ap ab ab ap a aD ab ab ab a Hele o db db db db fe sb ub b e 18 918 12 ms Min T 14 39 ms T 1000 00 ms Max T 412870 50 ms Available points 62 X 0 00 Zigeionm 2 Put 3 non v Toolbar Clear clear data Add Point Add Peak Continuous draw mode Ramp Remove Point Data panel turn on off the data table Import points copy points from another application Close close window with current signal Silego Technology Inc www silego com 04 20 2015 108 SILEGO Figure 10 31 Peak GreenPAK GreenPAK1 4 Designer 4 02 r FB Custom signal Wizard 11654 g E Clear A Add Point A Add Peak Continuous Ramp dar Remove Point Data panel ry Import points Close x O gt O O O O O co Data lt gs 3 a kko Yel A bet i Ke m D a w a 1 0 00 ms 0 00 Y Gel S 4 00 2 27 26 ms Al 0 00 v E eg T 3 42 59 ms 2A 117v ie e Jm 4 78 36 ms 0 02 area 5 126 06ms 0 00Y Glace 6 156 73 ms 11 89v SEA 7 245 32 ms
52. 7V F 910ms 216ev E 9 1040ms 2 246V ka 10 1170ms S 2 75 v 11 130 0 ms__ 2 3 06 V EJ 950 00 Ak dk 4 dh 0 34 0 00 dh dh dh ms 650 00 b 700 00 750 00 500 00 300 00 950 00 r gt 200 00 600 00 AM A dk dh Peak the point Cursor Silego Technology Inc www silego com 04 20 2015 02 S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 Figure 7 31 Cursor LE Custom signal Wizard rA Ramp f continuous Ramp f Data panel Data panel UU LILI 00 DR 50 10 150 300 00 40 200 00 350 00 500 00 700 00 550 00 600 00 750 00 650 00 900 00 950 00 450 650 X Value Y Value 0 0 ms 0 07 v FE 130ms z o3ev SI 26 0 ms 0 67 v m 390ms zlogv SI 52 0 ms 11 26 v 650 ms 2 1 56v E 780ms igzv A 91 0 ms s 216 v FE 1040 ms 2 46 vV F 10 117 0 ms___ 2 2 75 v F 11 1300ms_ 2 306v 12 1430ms l336v 13 156 0ms 236v 14 1690 ms 3 36 V 15 182 0 ms___ 2 3 36 V 16 1950ms_ 7 336V l 17 208 0 ms 1 3 36 v 18 221 0 ms___ 21 3 36 v m 19 2340ms 1 3 36 V n 1000ms __ gt Points 78 x 0 0ms w ooov Put 20 2470ms Sl336w Isi Ill LAB jl E l dh Ak db dk A dk o D cl M A W M PFP dk dr AN AF k n nn L E 5 B E 5 S E E i E 600 00 800 00 900 00 100 00 150 00 ee pm 45 5 M 55 65 700 00 750 00 850 0
53. 97 Y eJ LJ _ 10 n22 A2 me leal ou Ed n he Figure 8 33 Continuous Ramp r HE Custom signal Wizard m Ok Clear A Add Point M Add Peak r1 Continuous Ramp E Remove Point L Data panel Close 700 00 600 00 4 4 v Min T 7 34 ms T 1000 00 ms gt Max T 452191 50 ms Available points 68 xX 0 00 Fa Y 0 00 Put Remove Point Removes selected point Double clicking on the point can also remove it Silego Technology Inc 04 20 2015 83 O O O co co O Data i e in m 1 0 00 ms 0 00 Y Sts 2 185 69ms ZIL gele 3 349 23 ms 211192 Y SO 4 43271ms 2 210v SON 5 44634ms 4 0 01 SON 6 50426ms 9 0 00 H j 7 608 18 ms 21 1 66 V SEJE 8 650 77ms Sieg CE 9 706 98ms 24 1 75 SI 10 764 91ms Sien lel 11 841 57ms 1 89V CEP i2 s9508ms S 0 88 v CE 13 1000 00 ms 2 75 VW r 4 www silego com S SILEGO o GreenPAK1 4 Designer 4 02 Figure 8 34 Data Panel Min T 7 34 ms T 1000 00 ms Max T 452191 50 ms Available points 65 X 0 00 B Y Put y Period Put the point Cursor Figure 8 35 Cursor i Custom signal Wizard Ex EEUU ce 4 VEA Clear A Add Point A Add Peak Continuous Ramp j Remove Point Data panel Close Data X Value
54. A 213 221118 1 AAA 22 E PO PU CO ER En TRY 22 at A PA 22 SR ele ee ERT E 23 JA ul CR Y NOON FF A OE IDE THUR FFYN DT RE O ELE en 24 4 GreenPAK Programmer 4 1 GreenPAK Programmer TEE 25 sie iss eoa E ee mmt 25 ed seized tT UE mem 25 us ARS A ome Emm 26 OFE a gin RE A EI o e E PO RI a RE A Y NF 26 9 Print Function Mr E 30 EE EE 34 A nn RR NHY YF anaes FYD WY O N eR cR 37 7 GreenPAK 1 Emulation Board ok DES JOANNA emi A A Pee Om 39 Silego Technology Inc www silego com 04 20 2015 3 S SI LEGO GreenPAK M GreenPAK1 4 Designer 4 02 dE E T sais sc estrone EE 43 KA EE SNE E e Kn 43 7 2 2 Signal Analog o E 44 7 2 3 User defined IONS BOE eee eee nen eee A a esd ee eee med FFF 49 7 3 General Option iti Signal Wizard eet 54 KE leie as NER T Tr 55 ED A args ces SERA pts Emm 59 PASE life An VE E EA E EEE EEPE A OT E E T 59 7 7 Test Mode and Emulation TODO uso uat dado PHD AAA EA A KSERO cian 60 8 GreenPAK 2 Emulation Board ENK CNN IE UT MT EET S 64 pos DEE 68 8 2 1 General Option in Signal Wizard MIDES ss ne ci Cd SN Gal Ao 69 Du FEHOS MOOD EE 70 5 24 Ner E o pM TUNER 74 0234 a A EE 75 Oaea ma Aag Genera EE 76 5 276 la a e Mt rrr N 82 8 2 7 VDD Power ole er SINR NIME EE EE TERT 84 DI e a o EE 85 A EE 85 9 GreenPAK 2 Min Emulation POD GRA AA AE EE R A ee 89 10 GreenPAK 3 4 Emulation Board US EN S Eel C T Z E 220 2060454 1280002 TE kdo 91 A A TEENS 95 10 2 1 Genera
55. AK1 4 Designer 4 02 Properties IN IN2 IN INO 0 0 0 1 e 0 0 1 0 0 1 1 e 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 v 1 0 1 1 0 1 z 1 0 1 1 e 1 1 1 1 0 1 gt 1 1 1 0 1 1 1 1 Standard gates gt alto Defined by user T Alei Ses KA Apply Silego Technology Inc www silego com 04 20 2015 125 S SILEGO o GreenPAK1 4 Designer 4 02 3 Bit LUT reg 606 599 From Connection Matrix Output lt 35 From Connectio gt Matrix Output 36 SS From Connectio b Matrix Output 37 To Connection Matrix Input lt 24 gt N1 3 bit LUTO our Silego Technology Inc www silego com 04 20 2015 126 N SILEGO GreenPAK1 4 Designer 4 02 Properties x IN3 IN IN INO OUT 0 0 o oo l 0 1 0 1 0 0 1 1 0 1 0 1 1 0 1 1 0 1 1 1 1 0 0 1 0 0 1 1 0 1 1 0 1 1 1 1 0 1 1 0 1 1 1 1 0 1 1 1 1 Standard gates Defined by user MO Detailed y ge Silego Technology Inc www silego com 04 20 2015 127 SN SILEGO en GreenPAK1 4 Designer 4 02 2 Bit LUT or D Flip Flop Macrocells From Connection Matrix Output lt 63 gt 2 bit LUTO our To Connection Matrix Input lt 33 gt 4 bits NVM reg lt 574 571 gt DFF4 p OUT gt clk 1 bit NVM 8 reg lt 595 gt From Connection Matrix Output lt 62 gt Silego Technology Inc www silego com 04 20 2015 128 SS SILEG
56. Data Communications Equipment 3 bit LUT7 Handheld and Portable Electronics 3 bit LUT9 The GreenPAK3 SLG46721 is Silego s third generation GreenPAK product and is a one time programmable Mixed Signal Array coming in a small 2 mm x 3 mm X ma n TDFN 20 package A The GreenPAK3 operates at a 1 8V to 5V voltage range and provides a small low power component for commonly used mixed signal functions AOP2 Users create their circuit design by programming Non Volatile Memory NVM to configure interconnect logic I O PINs and macrocells of the SLG46721 This T pap highly versatile device allows a wide variety of mixed signal functions to be designed within a single very small low power integrated circuit POR Combination Function components 2 bit LUTO DFF LATCH4 2 bit LUT1 DFF LATCHS 2 bit LUT2 DFF LATCH6 2 bit LUT3 DFF LATCH7 3 bit LUT2 DFF LATCH2 zal 3 bit LUT3 DFF LATCH3 3 bit LUT8 Pipe Delay v Show all Hide all Legend box Silego Technology Inc www silego com 04 20 2015 24 9 LEGO GreenPAK GreenPAK1 4 Designer 4 02 A ko 4 GreenPAK Programmer 4 1 GreenPAK Programmer Overview GreenPAK Programmer provides user with a possibility to program a configured design to PAK chip quickly It can be started from Designer software or from the Windows main menu To start Programmer from GreenPAK Designer use the Tool bar main menu button or press F10 on the keyboard Programmer starts with an adv
57. Export save data to text file Import load data from text file Open in new Designer s window open current bit sequence in new Designer s window Figure 10 40 NVM Data Project data Loaded file Current project Pattern ID E Lock NYM Index Value Comment false false false false false false false false OJ oon W N O false false false false false false false false Flm Reload from current project Clear Export Import Open in new Designer s window Use current project s sequence For Programming and Emulation process Use this sequence For Programming and Emulation process Chip Details Show details about chip and board Silego Technology Inc www silego com 04 20 2015 113 9 LEGO GreenPAK GreenPAK1 4 Designer 4 02 lt ko Save settings Save current configuration of a test mode to the project file Figure 10 41 Save Settings dialog Log Show log LED control User can turn on off leds on GreenPAK emulation board Test mode configuration Save current configuration of a test mode to the project file Delete selected configuration Import new configuration s from project file s Figure 10 42 Test Mode Configuration Support for multiple devices This feature allows user to connect few supported hardware boards and select specific one for performing the operations Figure 10 43 Multiple
58. H R H B H H M M B i 0 d 100 01 450 03 100 04 I E 4 600 05 800 06 E 44 1000 08 Auto Min 0 00 F Max 1000 00 Silego Technology Inc www silego com 04 20 2015 TT GreenPAK GreenPAK1 4 Designer 4 02 S SILEGO Figure 8 27 Sine EB Signal Wizard Start point Stop point Global linkage Repeat Repeat count Prestart state Prestart delay End state Output type Pause type Custom phase Amplitude Zero offset Linked Cydic Low 0 00 ms Prestart state High Z Last state 0 0 00 rad 2 03 V 2 03 V 100 00 400 01 1000 04 1100 04 1200 05 1300 05 1400 05 1500 06 1600 06 1700 06 1900 07 2000 07 Period EIS ms 400 01 700 03 300 0 100 00 Frequency 1200 05 1600 06 1800 07 1900 07 1100 04 1400 05 1500 06 a ken E Min 0 00 Max Sine Settings Repeat One shot Cyclic Custom repeat option Phase Custom 0 Pi 2 Pi 3Pi 2 pO Custom phase show phase in a radian Amplitude amplitude Zero offset Zero offset Period period Frequency shows frequency Data change signal using Custom Signal Wizard Silego Technology Inc www silego com 04 20 2015 78 SILEGO GreenPAK GreenPAK1 4 Designer 4 02 Figure 8 28
59. Incorrect Power Configuration No power source is connected to the chip A The internal power source will be connected automatically Test mode Test mode is used for connecting or disconnecting the chips I O pads to stimulus areas configured by user Also a user can check the programmed chip using the test mode without emulation In order to do this one only needs to turn on the test mode and power key The test mode can work without power on the chip User will control the Power key manually Read Read chip using emulation board Silego Technology Inc www silego com 04 20 2015 112 SILEGO GreenPAK GreenPAK1 4 Designer 4 02 Qu ko Program Program chip with the current project NVM Data The table of bits Pattern ID gives an ID 1 255 to the project The ID will be put in the chip after programming and also will be read back while in chip reading operation Lock NVM blocks NVM reading A programmed project becomes unavailable for chip reading The chip is still available for emulation Use current project s sequence for Programming end Emulation process user can choose to use current project s sequence for programing and emulation process Use this sequence for Programming end Emulation process user can choose current sequence for programming and emulation process Reload from current project user can load bit sequence from current project Clear sets all bits to false
60. K 1 Designer e Rules Checker e Programmer e Emulator Tools in GreenPAK 2 Designer e Rules Checker e Mini Emulator e Emulator e Lock NVM Tools in GreenPAK 3 4 Designer e Rules Checker e Emulator e Project Settings e Project Info Panel switcher e Properties e Components e NVM Viewer e Datasheets e Examples e User Guides Navigation e Zoom slider adjust scale Zoom 1 1 Fit work area Full screen mode Pan mode Show item hint 3 1 3 Work Area Work area contains all blocks available in GreenPAK chip and their connections In GreenPAK 4 Designer SLG46620 chip work area consist of 2 matrices MatrixO and Matrix1 Figure 3 4 The components of each matrix can be interconnected through 10 input and 10 output ports Matrices window placement define buttons LI YH Matrix O full screen Matrix 1 full screen Vertical placement 2 matrices Horizontal placement 2 matrices One of matrices in separate window or monitor Silego Technology Inc www silego com 04 20 2015 12 SS SILEGO PA GreenPAK1 4 Designer 4 02 Figure 3 4 Two matrices of GreenPAK 4 Designer IET A aaa c ISLG46620V GreenPAK4 Designer v 4 01 9 3 4 m Components NVM Viewer Datasheet Examples User Guides File Edit View Tools Options Help New Open Save Print Set Wire Erase Wire SetLabel Erase Label Rules Checker Emulator Project Settings
61. O GreenPAK GreenPAK1 4 Designer 4 02 CUSTOM Mode Figure 7 35 Set Custom Period 200 00 300 00 350 00 500 00 550 00 600 00 650 00 700 00 750 00 800 00 850 00 900 00 950 00 100 00 150 00 100 00 450 00 IT 1000 00 200 00 00 00 600 00 700 00 750 00 800 00 900 00 1000 00 550 00 450 00 500 00 400 00 150 00 Custom phase 0 00 rad Amplitude 167V 100 00 2750 00 3000 00 3500 00 3750 00 4000 00 4250 00 4500 00 5000 00 2000 00 2500 00 1500 00 1750 00 750 00 Zero offset 1 67V Period 2000 ms Frequency 0 50 Hz Data 750 00 750 00 4000 00 1750 00 2000 00 3000 00 500 00 1000 00 1750 00 Max 1000 The user can set a custom period to be displayed for any generator Note Analog generators connected to PIN7 and PING start generation 0 5ms later than those connected to PIN4 and PIN6 This delay is displayed on the graphs in a Signal Wizard when the AUTO mode is ON Silego Technology Inc www silego com 04 20 2015 of S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 Figure 7 36 The Delay of Analog Generator f 4 0 34 Custom phase 0 00 rad m B 0 00 Amplitude 1 67 y Z u LF c c c c c c c c c c c c c c c c c c fe Te Zero offset 1 67V 5 3 0
62. O en GreenPAK1 4 Designer 4 02 Properties x 2 bit LUTO DFF LATCH A Type um IN IM2 INL INO OUT 0 A 0 0 A 0 1 0 A 1 g 0 1 1 1 0 0 0 O 1 0 1 JU a 0 1 1 g 0 0 1 1 1 10 1 O 0 0 1 0 1 0 1 O 1 0 0 1 1 1 0 1 1 0 0 0 1 1 O 1 0 1 1 1 o 0 1 1 1 1 JU l Mat er wm Defined by user w Altoi Detailed gs Info e Apply Properties 2 bit LUTO DFF LATCH A Type DFF LATCH Mode nSET nRESET option Initial polarity Q output polarity Silego Technology Inc www silego com 04 20 2015 129 SN SILEGO en GreenPAK1 4 Designer 4 02 3 Bit LUT or D Flip Flop with Set Reset Macrocells From Connection IN2 Matrix Output 43 j INT 3 bit LUT2 ovr LET From Connection To Connection Matrix lt Matrix Output lt 42 gt gt Input 26 gt 4 8 bits NVM reg lt 622 615 gt D From Connection D FE2 Matrix Output lt 41 gt nRST nSET Bim gt cik reg lt 671 gt Silego Technology Inc www silego com 04 20 2015 130 N SILEGO GreenPAK1 4 Designer 4 02 EJ Properties Type LUT IN IN2 INL INO OUT 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 1 1 U 1 1 0 0 10 1 1 0 1 0 1 1 1 0 0 1 1 1 1 0 Standard gates Man Defined by user
63. O selection Digital Input e Input mode OE 0 OE 1 None Resistor PulDown Pull Down ren Silego Technology Inc www silego com 04 20 2015 117 S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 Matrix OE IO Structure for Pins 3 5 7 9 13 14 16 18 19 Input Mode 1 0 00 Digital In without Schmitt Trigger wosmt en 1 01 Digital In with Schmitt Trigger smt en 1 10 Low Voltage Digital In mode Iv en 1 11 analog IO mode Output Mode 1 0 00 1x push pull mode pp1x_en 1 01 2x push pull mode pp2x_en 1 pp1x_en 1 10 1x NMOS open drain mode od1x_en 1 11 2x NMOS open drain mode od2x_en 1 od1x_en 1 Non Schmitt Trigger Input C 900 kQ Res_sel 1 0 00 floating 01 10 kQ 10 100 kQ 11 1 MQ Silego Technology Inc www silego com 04 20 2015 118 GreenPAK GreenPAK1 4 Designer 4 02 Silego Technology Inc www silego com 04 20 2015 119 S SILEGO Register OE IO Structure for Pins 4 6 8 15 17 20 Mode 2 0 000 Digital In without Schmitt Trigger wosmt en 1 OE 0 001 Digital In with Schmitt Trigger smt en lt 1 OE 0 010 Low Voltage Digital In mode lv en 1 OE 0 011 analog IO mode 100 push pull mode pp en 1 OE 1 101 NMOS open drain mode odn en lt 1 OE 1 110 PMOS open drain mode odp en 1 OE 1 111 analog IO and NMOS open drain mode odn en lt 1 and AIO en Silego Technology Inc 04 20 2015 1
64. Project Info Properties A Rotate Left 7 Rotate Right Flip Horizontal Flip Vertical T Align Horizontal Align Vertical Matrix 1 t Components List x E a Components Matrix 0 Y BG E DACO w DACI osc Pip Pipe DelayO z Combination Function components v 4 bit LUTO PGEN WS Ctrl 14 bit CNTO DLYO Ports o 900 o o o o o o ooo o o oe oo oc 2 2 bit 2 b l LUTS o o 000 0 000 000 o 000 000 00 o o o lt lt 927979 mud IS 222 o d 4 33 Er ZE 000 900 9 o o o o o o o o o o S s o o 3 3 3 3 3 b 3 3 b l l o o o o o o o o A a 3 E E 3 L L amp 88 voc SS o o o 900 gt o 909000 o lt OD a i i oo oo oo 000 o o o o o o o ooo o o 44 NN oc EE 55 aun A oo oo m m o 4 w c 5 o o 4 w i E KR e 3 D o D o Ei o o oo g o o Ie n DFF Latches LS aS LS EE 0 1 v JH Show all Hide al Legend box Three types of components connection Connectivity matrix connections green user can connect any output to any input through wiring tool Settings defined connections orange these connections are predefined and depend on block settings Buses wide orange line buses also depend on block settings All buses are 8 bit wide All blocks can be moved using mouse or keyboa
65. Rule information about the message 3 Note recommendations on how to correct the error or error explanation Silego Technology Inc www silego com 04 20 2015 37 S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 T GreenPAK 1 Emulation Board Figure 7 1 The Main Screen Emulation Start emulation Stop emulation Read chip Program Log 14 32 47 GreenPAK Emulation Tool started 14 32 47 Updated from current project 14 32 47 Test mode is disabled 14 32 47 Device is not connected 14 32 47 Initialization Step 1 14 32 47 IO manager initialization 14 32 47 IO manager Connecting to interrupt channels 14 32 47 IO manager state changed STARTING 14 32 47 IO manager state changed RUNNING 14 32 47 IO manager successfully started 14 32 47 Initialization succeeded 14 32 47 Initialization Step 2 14 32 47 IOHID checker initialization 14 32 47 IOHID checker Connecting to interrupt EET channels Em r 14 32 47 IOHID checker state changed O Z Z STARTING 14 32 47 IOHID checker state changed Expansion connector RUNNING 14 32 47 IOHID checker successfully started 14 32 47 Initialization succeeded 14 32 47 Test mode is disabled 14 32 48 Input stream Callback received 14 32 48 Input stream Callback received Start Generators Stop Generators m L 3 A Z Device is not connected Figure 7 1 displa
66. SILEGO GreenPAK GreenPAK1 4 Designer 4 02 Qu ko GreenPAK Designer User Guide Silego Technology Corporate Headquarters 1515 Wyatt Drive Santa Clara CA 95054 USA Phone 408 327 8800 http www silego com Silego Technology Inc www silego com 04 20 2015 1 9 LEGO GreenPAK GreenPAK1 4 Designer 4 02 Qu ko Copyrights Copyright 2010 2015 Silego Technology The information contained herein is subject to change without notice Silego Technology assumes no responsibility for the use of any circuitry other than circuitry embodied in a Silego product Nor does it convey or imply any license under patent or other rights Silego products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Silego Furthermore Silego does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Silego products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Silego against all charges GreenPAK Designer GreenPAK Programmer and GreenPAK are trademarks of Silego Technology All other trademarks or registered trademarks referenced herein are property of the respective corporations Any Sour
67. Tool ausi Emulation Test mode Read Programi n NWM Data Power Signal generator PIN 11 Key P nic Save settings Please connect device to USB port GreenPAK 2 3 s T elei i EE ajaja m mimm Expansion connector mI r Fd Fra A E F GRIES E as d Start Pause Stop Generators Generators Generators Board HWIFW rev NID Chip rev M D Default Save settings Delete Figure 8 1 displays the GreenPAK IC with dotted areas and expansion connectors which are connected to pins The right bottom corner displays revision information Silego Technology Inc www silego com 04 20 2015 63 SS SILEGO en GreenPAK1 4 Designer 4 02 Dotted areas are used to configure input connections Use the context menu to manage them Figure 8 2 Context Menu NC Set To VDD Set To GND Pull Up Pull Down Set Configurable Button Signal generator Logic generator Clock generator LED d Copy settings to d Exchange settings with b Copy settings to allows the copy settings from the current area to another connection Exchange settings with exchange settings of the current area with another connection 8 1 Types of Areas Fixed Inputs figure 8 3 8 7 Figure 8 3 N C not connected Figure 8 4 Set to VDD Silego Technology Inc www silego com 04 20 2015 64 S SILEGO o GreenPAK1 4 Designer 4 02 Figure 8 5 Set to GND
68. Types Figure 3 13 Green Line Green lines in GreenPAK Designer software tools are used to mark manual wires Using them you can manually connect necessary blocks to operate in the desired way You can connect block output to multiple inputs but wiring of different outputs to one input is impossible Figure 3 14 Orange Line Orange lines are used to mark the internal functional bounds of the chip blocks They do not have the impact on chip operation until the proper function is used These lines can t be erased Figure 3 15 Bold Orange Line Bold orange lines like the orange lines mark the internal bounds The difference is that the bold orange lines mark 8 bit parallel data buses These lines also cannot be erased They do not have an impact on chip operation until the proper function is used and the proper option is set Figure 3 16 Light Green Line Light green lines are used to mark the shared connections Their behavior is the same as the green lines Silego Technology Inc www silego com 04 20 2015 19 SN SILEGO PA GreenPAK1 4 Designer 4 02 Replacing wires by labels This option converts wired connection to 2 labels for output and input pins and back Figure 3 17 Name of the label will be generated automatically NETx where x random number If output was connected to few inputs all of them should have the same name For changing the connection type use the context menu of the block line or label NET
69. al Size Project Data Edit Data Zoom In Zoom Out Silego Technology Inc www silego com 04 20 2015 34 S SILEGO GreenPAK M GreenPAK1 4 Designer 4 02 Main Actions The user can Choose orientation of the diagram on a paper landscape or portrait Fit the diagram to a page or keep the real size e Fit to center e Zoom in or zoom out e Choose the size or type of paper Figure 5 12 Page Setup Print Preview DHZ EET S z Source Asroraruseckui EbI OD x Orientation Left 2 38 Right 4 15 Top 5 55 Bottom 3 95 Cancel Printer fo Portrait Landscape Silego Technology Inc www silego com 04 20 2015 35 S SILEGO GreenPAK M GreenPAK1 4 Designer 4 02 The user can add an editable data frame using the data frame tool Figure 5 13 Data Frame Tool Edit project info kiki Title Project Mame File Mame project1 gpp Author Ostap Company Siegol Revision 1 02 Date 04 26 2011 rE in PIN 6 Mode Digtal in Resistor Pull Down SZ in out Resistor value 300K out OE Disabled Project Name Date 04 26 2011 Rew 1 02 Size project app Ostap Silego Technology The user can save the finished diagram into a PDF file or print it out Figure 5 14 Save to PDF Print Preview Dl 2 7 WW LI SEs Ie Save File Save in 8 Desktop lt BE My Documents
70. anced interface shown on Figure 4 1 Figure 4 1 GreenPAK Programmer Window gt GreenPAK1 Programmer Tool Read chip Program 17 28 04 GreenPAK Programmer started 17 28 04 Updated From current project 17 28 04 Device is not connected Loaded file Current project Index Value Comment true true w true w true w true w true true true true w true False O CO MME mM no re false false false false true w true w true w true w true 4 Device is nat connected 4 2 Selecting Sequence File When you start GPP from the GPD tool bar gt or the main menu it automatically imports a bit seguence from the current project so you can easily program the chip Also you can select another file seguence by pressing the Import button 4 3 Programming Chip To program da evice please follow the next steps Insert PAK chip into the socket Connect programmer hardware to USB If you insert it for the first time please wait until programmer installation is complete Next you will see the message Device is connected in the status bar Start GreenPAK Programmer Select file sequence if required Press Program button Silego Technology Inc www silego com 04 20 2015 25 SILEGO GreenPAK GreenPAK1 4 Designer 4 02 Qu ko After programming is complete you will see a Programming successful message If you see another message please
71. ce Code software and or firmware is owned by Silego Technology Silego and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Silego hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Silego Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Silego integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Silego Disclaimer SILEGO MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Silego reserves the right to make changes without further notice to the materials described herein Silego does not assume any liability arising out of the application or use of any product or circuit described herein Silego does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Silego product in a life supp
72. de selected selected Co Pin colors during connection Open for connection Temporarily dosed for connection Used for hard wired connection Connection is not allowed Wire colors Normal connection Shared connection Hard wired connection Labeled connection colors Normal connection normal highlighted Shared connection normal highlighted Hard wired connection normal highlighted Combined connection normal highlighted Labeled connection colors during connection Open for connection normal highlighted Temporary dosed for connection normal highlighted Used for hard wired connection normal highlighted Connection is not allowed normal highlighted Pin tip colors Open for connection E Connection limit is reached Temporarily closed for connection Used for hard wired connection External 1 0 Silego Technology Inc www silego com 04 20 2015 22 N SILEGO GreenPAK1 4 Designer 4 02 3 8 Updating GreenPAK Designer There are two ways of updating the GreenPAK Designer 1 When updates are available this information will be displayed The user will get a chance to either download a new version using the Update or the Not now to delay the renewal until the next program start After the download is finished an opened folder with installer will appear Figure 3 19 Updating GreenPAK Designer HE GreenPAK 2 Designer v1 02 24 Pas File Edit View Tools s s MA Help m e A do
73. e 7 42 Using Test Mode Without Emulation Emulation Start emulation Stop emulation channels 14 32 47 IO manager state changed STARTING PIN 8 14 32 47 IO manager state changed PIN 7 RUNNING 14 32 47 IO manager successfully started PIN 6 14 32 47 Initialization succeeded cy 14 32 47 Initialization Step 2 14 32 47 IOHID checker initialization GreenPAK 14 32 47 IOHID checker Connecting to interrupt channels 14 32 47 IOHID checker state changed STARTING 14 32 47 IOHID checker state changed RUNNING 1111 11 14 32 47 IOHID checker successfully started 14 32 47 Initialization succeeded a 14 32 47 Test mode is disabled Zale ss i ez 14 32 48 Input stream Callback received l 14 32 48 Input stream Callback received Expansion connector 14 36 17 Test mode is disabled 14 37 29 Device is connected 14 37 29 Reset board Start Generators Stop Generators 14 39 01 Test mode is enabled 14 39 05 Reset board 14 39 05 Test mode is disabled 14 39 47 Test mode is enabled 14 39 55 Reset board 14 39 55 Test mode is disabled 14 40 30 Test mode is enabled 6 Device is connected Silego Technology Inc www silego com 04 20 2015 62 S SILEGO o GreenPAK1 4 Designer 4 02 8 GreenPAK 2 Emulation Board Figure 8 1 The Main Screen Oe B gt o A ge a 2 SL x E GreenPAK 2 Emulation
74. e Linked Unlinked if generator is linked it will be controlled by buttons Start Stop and Pause on the Emulator Repeat One shot Cyclic Custom repeat option Prestart state Low Start point VO High Z state before start Prestart delay delay before start End state Keep last state Prestart state pin state after generation Output type High Z Strong Drive Open Drain Drives High type of output Open Drain Drives Low Resistive Pull Up Resistive Pull Down Resistive Pull Up Down Pause type Last state Low High High Z state when it is paused Silego Technology Inc www silego com 04 20 2015 96 w SILEGO GreenPAK GreenPAK1 4 Designer 4 02 10 2 2 Period Modes AUTO Mode All generators with AUTO option have one scale this scale MAX period of all generators with AUTO option Figure 10 17 One Scale for All Generators 48 Signal Wizard Options General 100 00 150 00 200 00 300 00 700 00 800 00 1000 00 950 00 600 00 750 00 900 00 400 00 450 00 500 00 550 00 SEN nn 250 00 Generator TP6 PING Sine M 5 00 i i i i i i i i i i i i i i i i i i i 5 00 4 00 4 00 3 50 3 50 3 00 x Hu u a 2 50 2 50 2 00 2 00 1 50 1 50 1 00 1 00 0 50 0 50 Start point 0 00 ms Stop point a v a E m VDD PIN1 Global linkage ined 4 Repeat Cyclic Repeat count Pre start state Low Pre start delay
75. echnology Inc www silego com 04 20 2015 21 S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 enable OE pins These pins are one way directed so you need to configure the pin component and connect the proper pin OUT pin is an output signal from the pin component It corresponds to the signal from the input buffer IN pin is an input to the pin component It accepts a signal from internal components Output Enable OE signal defines the Push pull buffer state Low OE signal switches buffer to Hi Z state High OE signal enables Push pull buffer regardless of selected component operating mode It could be used for applications where bidirectional pins are needed 3 6 Navigation A Zoom Out A buttons ES or Zoom 1 1 A To navigate through project workspace use the View menu or toolbar Use Zoom In or slider to zoom workspace If you want to see all project components click on Fit work area To navigate through work area you can use Pan mode D To enable block s hint press Show item hints button A hint box pops up next to the item when the mouse moves over the block 3 7 Legend Box Legend box shows the color scheme of GreenPAK designer After clicking Details this box displays The user can open this window by clicking Legend box button in Help menu Figure 3 18 Legend Box View Block colors WI Block on de selected selected Block off de selected selected m I O PAD de selected selected m I O Port
76. ee Ww GSR SZ Type C SE we ev IAB EE EE AOS EA p mi pone m EN EE of gu p ae A ua Spon a Mm 2 50 R za E 1 E A eee D 7 EE ME m a e I R TEE FAR d FM ONA c k Zero offset 2 03 V H Period 1000 00 ms E Frequency Data Modify 5 ms 740 00 825 00 180 00 8 Y Auto Apply B Apply Al Start Pause Stop Min 0 00 gt Max E 9 button turns on off the mouse coordinates in the timing diagrams Silego Technology Inc www silego com 04 20 2015 98 S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 CUSTOM Mode Figure 10 19 Choosing Period Options H 00 50 1110 00 202 1480 00 0 00 un ou O HEET 0 00 Cydic Repeat count 2 Prestart state Low Prestart delay 0 00 ms End state Prestart state Output type High Z Pause type Last state 50 1110 00 1387 50 1480 00 1572 0 00 0 0 5 00 00 00 2975 100 00 2800 00 75 0 700 00 1050 0t 1575 1750 00 35 14 5 O M A vi M an e 0 00 rad J R de ee MM OA 2 03 V 2 03 V d bb pad MM LA QU pb 1000 00 ms d d lt gt C 0 00 00 00 1 00 Hz 0 00 5 00 75 00 275 800 00 75 00 10 262 lara aa 2975 3150 0 3325 1750 00 350 875 00 1050 00 15
77. esigner 4 02 9 GreenPAK 2 Mini Emulation Board Figure 9 1 The Main Screen Se GreenP AK Mini Emulator Tool 18 38 05 Device is not connected 18 38 05 Test mode is disabled z X E E ES d PIM2 PIM3 PI 16 wv 48 d Internal power source Program VOD Power 3 29 V EECH Emulation Test mode Ramp time 5 ms EJ w External power source Read Loaded file Current project Pattern ID 1 H Lock N M Index Value Comment E False False False False False False False False 1 2 3 4 5 6 7 8 False False False False False False False False False False k Clear Import Export Reload From current project Open as new project A Device is not connected Chip revision MID Board HWIFW revision MID VDD Power defines the voltage level set on the GreenPAK Internal power source when the Test mode is ON Ramp time time of voltage increases from 0 V to the level specified in the VDD Power while turning the Test mode ON Pattern ID gives an ID 1 255 to the project The ID will be put in the chip after programming and also will be read while chip reading Lock NVM blocks NVM reading A programmed project becomes unavailable for chip reading The chip is still available for emulation User can connect disconnect I O pads of GreenPAK 2 with the expansion connector on the board using PIN2 PIN3 PIN4 latches The Test mode button is used for turning
78. esigner 4 02 Qu ko A Example projects In the GreenPAK Designer Help menu you can find a link to the Examples directory There you can find fully configured examples which can help get your projects completed more quickly Each example has documentation that contains diagrams and descriptions Silego Technology Inc www silego com 04 20 2015 150
79. eslie F P Sine settings Repeat One shot Cyclic repeat option Phase Custom 0 Pi 2 Pi 3Pi 2 pO Amplitude amplitude Zero offset zero offset Period period Data change signal using Custom Signal Wizard Custom phase show phase in radian Freguency show freguency Silego Technology Inc www silego com 04 20 2015 48 S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 7 2 3 User Defined Generator Figure 7 25 User Defined Waveform TE Signal Wizard 100 05 800 40 1000 50 600 30 Start point 0 ms Stop point 1000 ms Loop count Data U 0 O O Lu O a Ow li A OI a OJOS OAN O LJ e ymy NJ Pd III O lu O Mie O UL b 100 05 Min 0 H Max 1000 User Defined Waveform Settings Repeat One shot Cyclic repeat option Data change signal using Custom Signal Wizard Silego Technology Inc www silego com 04 20 2015 49 S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 Figure 7 26 Custom Signal Wizard Arbitrary waveform TI Custom signal Wizard Clear K Peak nm FT Continuous Ramp Data panel Data panel 00 00 350 00 1000 00 HO DU LLL LJALA X Value Y Value a 0 0 ms s 152v ES 130ms s 154V Ri 260ms gt 159V E 39 0 ms 11 62 v F 520 ms Elev 650ms 7 175V E 780ms zlimv E 910ms S La7V 9 1040 ms Lsv a
80. ile format 3 2 2 Lock NVM Window Figure 3 5 NVM Options Lock NVM blocks NVM reading A programmed project becomes unavailable for chip reading Though chip is still applicable for the emulation Pattern ID gives an ID 1 255 to the project The ID will be put in the chip after programming and also will be read back during chip reading operation Silego Technology Inc www silego com 04 20 2015 15 9 LEGO GreenPAK GreenPAK1 4 Designer 4 02 A w 3 2 3 Project Settings Window Figure 3 6 General Project Settings KE General project settings VD directly to analog blocks use for YDD lt 1 9 Regulator and Charge Pump automatic ON OFF use For dynamical 1 71 lt YDD lt 5 5V range Regulator auto ON OFF and Charge Pump always OFF use For 3 0V lt YDD lt 5 54 General project options Regulator auto ON OFF and Charge Pump always ON use for 1 71 lt YDD lt 3 0 General Lock NVM Power Supply Control mode Regulator and Charge Pump a EN GPIO quick charge Disable v Cancel GPIO quick charge this option will temporarily enable 2k resistor for 1us duration in parallel to internal pull up downs during power on before reset signal is released to internal blocks For example this option should be used to ensure the internal pull up rise time is fast enough to be detected as high level during power on Otherwise a rising edge with weak i
81. ing DFF Latches Y Analog Comparators Y Digital Comparators Counters Delays Y Special components Fh RE ET REI T Ti PIN 10 Mode Digital in without Schmitt trigger ex Res Pull Down infout Res val 300K Init state Output floating 0 8 0 0000 a FT T LAJA Silego Technology Inc www silego com 04 20 2015 27 S SILEGO o GreenPAK1 4 Designer 4 02 The Main Actions User can hide or display any component using the Components list on the right Each component in the work area is selectable and movable Any component can be rotated or flipped Note print editor settings will be saved before print editor s window is closed It allows the user to repair previous state during next opening Le Ces H You can load previous print editor state or reset all blocks Do you want to load previous print editor state m Discard x Cancel Figure 5 2 Preview Window TE Print Editor Cuy File Edit View a a AS ZA lt K A o Y Print Preview Save image Snapshot Rotate Left Rotate Right Flip Horizontal Flip Vertical Add Text AddRect Add Ellipse Graphics settings DD Y 1 0 PAD n DC aliis Logic i 7 Po dmm a nalo omparators in PW W hak lC FSC e l Pwr Down 3 Special components m rx Mode Single end gata Gren CIK inver Gain x0 5 pai ge Ra Go Gain input 0 1 V data si Reg d 0 DD range
82. ion process In case when Power key and VDD key on the Expansion connector are turned off there will pop up a warning message figure 8 39 Figure 8 39 Incorrect Power Configuration ii Incorrect power config atio No power source is connected to the chip A The internal power source will be connected automatically X Cancel Silego Technology Inc www silego com 04 20 2015 85 9 LEGO GreenPAK GreenPAK1 4 Designer 4 02 Qu ko Test Mode The test mode is used to connect or disconnect chip s I O pads to stimulus areas configured by the user The user can also check the programmed chip using the test mode without emulation In order to do this one only needs to turn on the test mode and power key The test mode can work without power on the chip User will control the Power key manually Read Read chip using emulation board Program Program chip with the current project NVM Data The table of bits Pattern ID gives an ID 1 255 to the project The ID will be put into the chip after programming and also will be read during chip reading operation Lock NVM blocks NVM reading A programmed project becomes unavailable for chip reading However the chip is still available for emulation Use current project s sequence for Programming end Emulation process user can choose to use current project s sequence for programing and emulation process Use this sequence for Programmi
83. it LUT9 Analog Comparators A CMPO A CMP1 A CMP2 A CMP3 Counters Delays 14 bit CNTO DLYO 14 bit CNT1 DLY1 8 bit CNT4 DLY4 8 bit CNTS DLYS 8 bit CNT6 DLY6 Special components FILTER 0 FILTER 1 RC OSC P DLY VREFO VREF1 POR Combination Function components 2 bit LUTO DFF LATCH 4 2 bit LUT1 DFF LATCH 5 2 bit LUT2 DFF LATCH 6 2 bit LUT3 DFF LATCH 7 3 bit LUT2 DFF LATCH 2 3 bit LUT3 DFF LATCH 3 3 bit LUT8 Pipe Delay Abt LUTO CNT2 DLY2 4 bit LUT1 CNT3 DLY3 KIKKRI IA IATA IA IA IA Show All Hide All Legend box Figure 3 3 GreenPAK 4 User Interface File Edit View Tools Options Help ls A y New Open Save Print Set Wire Erase Wire SetLabel Erase Label Rotate Left Rotate Right Flip Horizontal Flip Vertical m Align Horizontal Properties Matrix 0 PIN 2 1 0 selection PIN not used t Input mode OE 0 Output mode OE 1 a v 4 Resistor 4 Resistor value PIN 2 Reset Disable t Bypass High active T Edge detect vm a mode Information Electrical Specifications 18V 3 3 V 5 0 V min max min max min max SLG46620V GreenPAK4 Designer v 4 01 2 A N HE a Q Project Settings Project Info Properties Components NVM Viewer Datasheet Examples User Guides x Matrix 1 t Components List x Components Matrix 0 gt Matrix 0 VO PADs VDD PIN 2 PIN 3 PIN 4 PIN 5 PIN 6 GND PIN 7
84. izard Window GreenPAK GreenPAK1 4 Designer 4 02 i8 Signal Wizard Options Generator PIN 6 Logic Sequel gt Shown period Auto Start point Stop point 1 000 ms Mode Normal Repeat Cyclic T1 T2 1 100 0 ms H 200 0ms 2 300 0 ms SI 400 0ms Insert Remove Count Auto Apply Apply Start Pause Stop e Auto Configuration Options Mode Repeat T1 T2 Values Table Insert Remove Count Silego Technology Inc 04 20 2015 100 00 N 100 00 ft 1080 SA Normal Invert One shot Cyclic 43 400 00 400 00 500 00 500 00 EE ZU OU Z QU UU E N Sis Re ZU OU FUU UU signal mode repeat option 900 00 900 00 1000 00 1000 00 sets of pulses T1 low duration T2 high duration of one pulse insert pulse to the entered position remove pulse from the entered position pulses count www silego com S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 7 2 2 Signal Analog Generator Signal generator is used to generate analog signals Constant Voltage level Saw Triangle Trapeze Trapezoid Sine User defined Logic and signal generators can be started paused stopped using orange buttons or through the context menu The user can also assign hot keys for start pause Several generators can use the same hot key to start pause at
85. l Option in Signal Wizard Modes ana 96 10 2 2 Period PICOS Si AA MM Se DM aiU E REED 97 e ere 100 POZA OGONA Analog Generat EE 101 ke GN re e E Nome 108 10 2 6 VDO Power A A UM EDDU ERE o 111 1032 Expansion ONE RR TOT 112 Eeer 112 11 Designing Overview 11 1 SLG46721 Properties Interoretaton aaa 116 a PROJECTS area A O A io wini AFR ED ME Tu CAD FEE 150 Silego Technology Inc www silego com 04 20 2015 4 9 LEGO GreenPAK GreenPAK1 4 Designer 4 02 Qu ko 1 Introduction This document describes the installation and usage of Silego GreenPAK Designer software This software can be used as a stand alone application for the firmware development and for GreenPAK chips programming If the information in this guide is not sufficient to resolve issues experienced with GreenPAK Designer refer to the resources listed under the Support section Features that are common for GreenPAK 1 Designer GreenPAK 2 Designer GreenPAK 3 Designer and GreenPAK 4 Designer are described in chapters with a GreenPAK Designer general name The differences are described in separate chapters 1 1 Application Overview Each GreenPAK Designer GreenPAK 1 Designer GreenPAK 2 Designer GreenPAK 3 Designer and GreenPAK 4 Designer is a full featured integrated development environment IDE that allows you to specify exactly how you want the device to be configured This provides you direct access to all GreenPAK device features
86. n drain x2 Disabled Out i i Silego Technology Inc www silego com 04 20 2015 32 S SI LEGO GreenPAK M GreenPAK1 4 Designer 4 02 The user can save a composed diagram into a graphics file or directly send it to the printer Figure 5 10 Save diagram 7 Print Editor File Edit View m O RA Sa A OO Save File Save in 8 Desktop z e ES Fe My Documents 4 Y My Computer E My Recent My Network Places Documents d Desktop My Documents wy a My Computer o O a a 5 a 3 i co e ap a Amp indio Wd epour dino 969 66 960 m a My Network File name roject Places Save as type Image file pna Cancel y dino mno pwr down inp ch 1 inp ch 2 ADC Mode Single end out clk ser data inn Gain 0 5 Vref VEG 1 796 w par data Reference DAC Mormal 2 ch select fasdhack pga ext vref ext clk Silego Technology Inc www silego com 04 20 2015 33 S SILEGO GreenPAK M GreenPAK1 4 Designer 4 02 5 2 Preview Window Preview window shows the composed and ready to print diagram In this window the user cannot change the position of the components or the other elements in the diagram The user can only choose the advanced settings for printing or saving to the file Figure 5 11 Preview Window 8 8D j EB BTA A m Print SavePDF Save Image Page Setup Portrait Landscape To Center Re
87. ndow to appear press the Edit button EX On the left you can see the options table divided into 2 groups 1 General applied to all types of generators 2 Special for each generator For them to start up use the buttons below the Emulator m 10 15 puis Buttons Note these buttons can be controlled only by generators with an installed Global Linkage flag Sz Silego Technology Inc 04 20 2015 95 www silego com S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 10 2 1 General Options in a Signal Wizard Mode Figure 10 16 General Option General Generator PIN 3 Sine Shown period 1000 00 100 00 200 00 500 00 600 00 700 00 900 00 gt 400 00 Start point Stop point Global linkage Linked a o z go m EL Repeat count EEE EE dene A A R EA 2 00 Prestart state A SR Pana O 1 50 r w Prestart state DD 95 gt So Z l Output type 0 00 Pause type High z Last state Signal Generator Settings Type Sine w Phase Custom phase 0 00 rad Amplitude 2 03 V g Zero offset 2 03 V Period 1000 00 ms ES Frequency 00 Hz Data Modify L 850 00 1000 00 100 00 500 00 All Start Fause Stop w Auto Apply ka Apply Generator generator selector Shown period Auto Custom 1T 2T 3T 4T set the period of a current generator to be displayed Global linkag
88. ner 4 02 lt ko 1 3 Support Free support for GreenPAK Programmer is available online at http www silego com ASSES siegousa silegochinese silegoeurope silegojapan At facebook Silego Technology For software updates please go to the Software amp Docs page on our website You can find all these resources in the Help menu of GreenPAK Designer 1 4 Acronyms These are the acronyms used in the User Guide Table 1 1 Acronyms GreenPAK Designer GreenPAK Programmer GPD GPP Integrated Circuit E SB Universal Serial Bus General Purpose Input Output General Purpose Input NMOS N channel MOSFET metal oxide semiconductor field effect transistor PMOS P channel MOSFET metal oxide semiconductor field effect transistor O U Silego Technology Inc www silego com 04 20 2015 6 S SI LEGO GreenPAK M GreenPAK1 4 Designer 4 02 2 GreenPAK Designer Launcher This section describes GreenPAK Designer launcher application and its features Figure 2 1 GreenPAK Designer Launcher User Interface EJ GreenPAK Designer v 3 00 24 x MIB SLG46721V Part Number E Size mm Vdd V GPIO Power Switch Max LUT ACMP SE SLG46110V GreenPAK3 16x16 18 to 5 0 2 NE SLG46116V GreenPAK3 1 6 x 2 5 1 8 to 5 0 Soft start P FET w o Discharge 2 Wm SLG46117V GreenPAK3 1 6 x 2 5 1 8 to 5 0 Soft start P FET w Discharge 2 J SLG46120V GreenPAK3 16x16 2 SLG46721V GreenPAK3 4 WE SLG46722V GreenPAK3 s SLG
89. ng end Emulation process user can choose current sequence for programming and emulation process Reload from current project user can load bit sequence from current project Clear sets all bits in false Export save data to text file Import load data from text file Open in new Designer s window open current bit sequence in new Designer s window Figure 8 40 NVM Data a Project data m E Loaded file Current project Pattern ID 1 a Lock N M Index Value Comment false e false false false false false false false false false aon oon A W N rs false false false false false false Reload from current project Clear Export Import Open in new Designer s window Use current project s sequence for Programming and Emulation process Use this sequence for Programming and Emulation process Silego Technology Inc www silego com 04 20 2015 86 9 LEGO GreenPAK GreenPAK1 4 Designer 4 02 lt ko Save Settings Save current configuration of a test mode to the project file Fi gure 8 41 Save Set caption Project x Enter configuration s caption Log Show log Figure 8 42 Test Mode Configuration Default Save settings Delete S User can save current configuration of a test mode to the project file Figure 8 42 Silego Technology Inc www silego com 04 20 2015 87 SN SILEGO PA GreenPAK1 4 D
90. nternal pull up can be quite slow and miss detection as a high level because of too slow of risetime Figure 3 7 Project Settings FE General project settings General Lock NYM NYM Options Lock NYM Disable Pattern ID Cancel Lock NVM blocks NVM reading A programmed project becomes unavailable for chip reading The chip is still applicable for emulation Pattern ID gives an ID 1 255 to the project The ID will be put in the chip after programming and also will be read while chip reading operates Silego Technology Inc www silego com 04 20 2015 16 9 LEGO GreenPAK GreenPAK1 4 Designer 4 02 lt ko 3 3 Configuring Chip Components 3 3 1 Placing Components When you open GreenPAK Designer it will start with a blank project A blank project contains pins and blocks which cannot be hidden Components can be moved rotated flipped and aligned In order to move a component simply drag it where you want by clicking the left mouse button To rotate flip align component select it and press E A A lt S uy the Rotate Flip Align buttons Rotate Left Rotate Right Flip Horizontal Flip Vertical Align Horizontal Align Vertical on the toolbar Or select Rotate Flip Align in the main menu 3 3 2 Setting Chip Components Parameters Each chip component has different parameters Some components have parameters that are shared with other components Changes in one block
91. ocks You cannot hide blocks that are connected by any type of lines In the GreenPAK chip there are connections which are beyond the connectivity matrix They are controlled by settings of proper components and cannot be fully disconnected That s why there are some blocks that cannot be hidden Hidden blocks retain their configuration For this reason be sure to configure hidden components properly You can show hide selected blocks by using the check un check feature on the list In order to show a group of blocks double click on the check box of the desired group In order to hide a group use a single click There are two buttons at the bottom of the components list Show all shows all blocks and Hide all hides all blocks which are not connected to a circuit Also user can use filter to find required components Also user can drag amp drop any component from Component List to the workarea to the right place 3 1 6 Color Scheme Components Mode Description Normal Selected Turned on Turned off wm UO PAD Components Pin Tips Color Value User can connect wire to this pin Pin has already been connected and there cannot be any other connections to this pin Inner connection user cannot connect wire to this pin a User can connect wire to this pin only after changing component option External I O Pin I O from chip Silego Technology Inc ww
92. om the main menu Next click the first and second pins that you want to connect After selecting the first pin GPD highlights allowed connections in green If you click the first pin and then decide to exit line creating mode press Esc or the right mouse button Figure 3 9 Also you can manually correct the created wires You can move horizontal lines up and down vertical lines left and right Figure 3 10 Figure 3 10 You can move points on the wire Figure 3 11 Figure 3 11 In order to create additional points on the line use the double click Figure 3 12 Figure 3 12 Only the green color pins can be connected Using Wire Creating tool Some components have pins that are not allowed to be connected using wiring tool Connections between such pins orange dotted line and violet pin color and buses can be made only by changing settings in Connections section of the Properties panel of Silego Technology Inc www silego com 04 20 2015 18 SN SILEGO PA GreenPAK1 4 Designer 4 02 proper components In this case violet pins can change color to green and user can connect them using wiring tool Orange wires will be automatically generated Orange wires also can be modified by user Input pins without connections are considered to be tied to ground gt In order to delete wire please select Erase wire at the Wire tool bar and click on the selected wire Only green wires can be deleted 3 4 1 Wire
93. on off the test mode Silego Technology Inc www silego com 04 20 2015 88 9 LEGO GreenPAK GreenPAK1 4 Designer 4 02 Qu ko The Emulation button turns on off the Emulation mode In Emulation mode the Test mode will be automatically turned on Thus the current project will be loaded to the chip but not programmed and will be ready for test on the emulation board The user can change any configuration during the emulation process The user can also check the programmed chip using test mode without emulation In order to do this one only needs to turn on the test mode and power key A Program button is used for writing NVM to chip A Read button is used for reading NVM from chip A Clear button resets all values to false Export Import buttons are used for saving opening NVM in txt format Reload from current project updates NVM from current project Open as a new project creates a new project in GreenPAK Designer with current NVM configuration Below the mini emulator window there is the information about device chip revision and board hardware freeware revision Silego Technology Inc www silego com 04 20 2015 89 S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 10 GreenPAK 3 4 Emulation Board Figure 10 1 The Main Screen 8 GreenPAK Universal Board Pec T M NVM Data Signal generator PINI Je Revision Irfo ESZ Save settings Nic Leg
94. once This is the right way to start more than one generator at the same time Figure 7 17 Start Pause Hot Key Start generator Pause generator Stop generator Properties Set Start Pause hot key b M C Set To VDD Set To GND Pull Up Pull Down I Set Button E SENE Logic generator Silego Technology Inc www silego com 04 20 2015 44 S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 The Start Generators and Stop Generators buttons can also be used in this way Figure 7 18 Start Generators and Stop Generators Signal Generator settings Type Const voltage level Trapeze Sine User Defined type of waveform Constant value U voltage level Figure 7 19 Generators Settings UTE signal Wizard Generator PIN 7 Constant Vo Shown period Auto Start point ms 50 00 200 00 ui 300 00 500 00 550 00 600 00 700 00 900 00 400 00 100 00 Stop pomt 1000 ms n y L 364m EL Li LO ee pma J La a A CT C3 GET az La JH f CO LALO PIO C3 m os JH a DD EE cnt Lu Ka ele a O 1 6 1 3 1 0 O O 2001 QQ 0 00 300 00 750 00 550 00 600 00 700 00 800 00 900 00 500 00 350 00 400 00 100 00 25 1000 00 Min 0 max 1000 gt gt Silego Technology Inc www silego com 04 20 2015 45
95. onnect to pattern Frequency generator frequency Duty cycle In percent duration of high signal in percentage Figure 8 23 Clock Generator View 3000 08 1500 04 1800 05 Start point Stop point Global linkage Li Repeat Repeat count 2 Prestart state Low Prestart delay 0 00 ms alb gt End state None Output type Strong Drive Pause type None Pattern num Pattern LO dk 4 Frequency 12 MHz Duty cycle 50 1050 0 1500 04 100 05 2400 06 Auto Min Ion E Silego Technology Inc www silego com 04 20 2015 15 S SILEGO o GreenPAK1 4 Designer 4 02 Start and Stop buttons can be used to start and stop a current generator A Pause button used for generator pause start at the same time makes the Clock generator key connect disconnect If All flag is enabled the buttons do the same as buttons in the emulator 8 2 5 Signal Analog Generator Figure 8 24 Signal Generator Signal generator is used to generate analog signals Constant Voltage level Sine Trapeze Trapezoid User defined Logic signal and clock generators can be started paused stopped using orange buttons or through the context menu The user can also assign the hot keys for start pause Several generators can use the same hot button to start pause at once This is how to start
96. onnection Matrix Input 10 External WDD 1 71 V 5 5 V HE ODDO e m Properties x dh 1uA pullup on input meee EE conto ose gt Mone Silego Technology Inc www silego com 04 20 2015 138 SS SILEGO PA GreenPAK1 4 Designer 4 02 ACMP1 Block Diagram reg lt 812 811 gt ibias Hysteresis Selection Selectable 7 L S ref 7 PIN10 aio en ON after if reg lt 883 882 gt 11 then 1 Wi 100 us Delay External VIDD PIN10 ACMP1 To Connection Matrix Input lt 11 gt From ACMPO s MUX output PIN10 aio en reg lt 570 gt reg PIN12 ACMP From ej vi Vla D lt n Properties aid nm None Silego Technology Inc www silego com 04 20 2015 139 N SILEGO mE GreenPAK1 4 Designer 4 02 ACMP2 Block Diagram reg 827 to ACMP3 s MUX input reg lt 824 823 gt Hysteresis Selection Selectable ZL M PIN13 aio en ON after if reg lt 899 898 gt 11 8 reg 100 us Delay lt 473 468 gt 000000 then 1 otherwise C PIN13 ACMP1 To Connection Matrix Input 12 From AC PIN14 ACMP PIN12 ACMP1 MIA i EJ amp 4 b Y reg lt 822 818 gt Properties Silego Technology Inc www silego com 04 20 2015 140 SS SILEGO mE GreenPAK1 4 Designer 4 02 ACMP3 Block Diagram reg lt 558 557 gt ibias Hysteresis Selection PIN15
97. ool is included for convenient project testing e Rules Checker checks current design for correct settings Tools in GreenPAK 3 4 Designer e Emulator this tool is included for convenient project testing e Rules Checker checks current design for correct settings Options e Settings default projects folder autosave toolbars position recovery shortcuts and update options L u O Help show help window User guide open User guide directory Legend box show the legend box in the right bottom Silego web site open Silego official web site Software and documentation open Software amp Dock web page Support page FAQ web page Facebook Silego technology Facebook page Silego TV Silego technology You Tube channel Examples open examples directory Datasheets open documentation directory Updater open GreenPAK product page About this program show information about GPD versions modification 3 1 2 Tool bars Toolbar provides a quick access to frequently used functions There are 7 tool bars File e New e Open e Save e Print Wire e Set wire e Erase Wire Item editor e Rotate Left e Rotate Right e Flip Horizontal e Flip Vertical e Align Horizontal e Align Vertical Silego Technology Inc www silego com 04 20 2015 11 9 LEGO GreenPAK GreenPAK1 4 Designer 4 02 Qu ko e Set Label e Erase Label Tools in GreenPA
98. ort systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Silego against all charges Use may be limited by and subject to the applicable Silego software license agreement Silego Technology Inc www silego com 04 20 2015 2 S SI LEGO GreenPAK M GreenPAK1 4 Designer 4 02 Contents 1 Introduction Aedo eau REI NE ERN 5 a OH ag gp Ge Gd A ING dd wnn OR OO 5 A Tc 6 pP oris 1 lt EU EE Umm 6 2 eu PAK Designer ESUNICTIBE uice ci usi imas RNA RC Y cu quu End nip OE DNE peri 7 3 GreenPAK Designer 3 1 GreenPAK Designer OVerViEW a e e O o o Oz a AA 8 em mb miu a mnm 10 SNC erte Bab ROWNO RR A 11 SWINE SII A c E 12 3 14 nn TE TO FFF FFO ES ME NEM 14 A e TA 14 A nn RE HR RR A NF Ma 14 5 i e A EI HR A 15 eU se le Le ExiStIng Re Se resemaaironee ccna E RR OO RR NF I DR 18 SAA Ee a PO M IIO 222420020 24h a 3044 40200911 AA Goci O NY A 15 32 3 Project Settings VMN FF a jana HR NN HN RT catedra 16 3 3 Configuring Chip Ea ga sei MEE D RH HR CY ii AR FT FFF FEW FY 17 3 3 1 ee eeler 17 3 3 2 Setting Chip Components Parameters cccccccccececeececseeecececeeeceeeesseceescecegeeseeseeceeseeseeseeeeeaes 17 3 4 Specifying Interco neGClo sS adna Fu UF wa 1A OWE is 18 SE Ze i i a TERNI 19 co CE PI beni inus bose zi FFF FRYN EN HT NF Y YNN FED P G MO MN DN mE 20 3 5 BU ME PINOUE e A e tem 21 so TT 21 3 0 2 PON BU NIONE A EN EE 21 OS
99. pO Pin Pin19 aio en ext vref acmp1 Vref Out 1 Pin19 Pin12 De ee req lt 994 992 gt CMP2_VREF VDD reg 556 552 lo Pin18 aio en Vref Out 2 Pin18 reg lt 997 995 gt Y reg lt 983 gt VDD 2 reg lt 998 gt Vref Out_1 is floating in case of reg lt 994 992 gt 111 amp reg lt 982 gt 0 Vref Out_2 is floating in case of reg lt 997 995 gt 111 amp reg lt 983 gt 0 Properties x a P Disable aj ti pa i ES Disable Source selector Donc A CMPO m f H 50 mV A CMP1 f H 50 mV Silego Technology Inc www silego com 04 20 2015 147 GreenPAK GreenPAK1 4 Designer 4 02 Silego Technology Inc www silego com 04 20 2015 148 S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 RC OSC Block Diagram Internal RCO reg lt 566 565 gt reg lt 708 gt 0 25 kHz 1 2 MHz i DIV 1 2 4 8 L To Connection Matrix Input lt 45 gt Pin 20 Ext Clock First Stage Divider Ext Clk Sel reg zz To Connection Matrix Input lt 46 gt 112 1 24 64 To Connection Matrix Input lt 47 gt Inn reg lt 711 710 gt To Connection Matrix Input lt 48 gt To Connection Matrix Input lt 49 gt Second Stage Divider Properties x SS L Clock selector nca 25 00 kHz W REY Clock 1 d KA CLOCK 8 3 Silego Technology Inc www silego com 04 20 2015 149 9 LEGO GreenPAK GreenPAK1 4 D
100. r 8 Bit Counter Delay Macrocells From Connection Matrix Output 30 4 IN3 Y 4 bit LUTO From Connection Matrix Output lt 29 gt A IN2 SA OUT To Connection Matrix Input lt 22 gt 16 bits NVM reg lt 688 673 gt DLY n CNT Reset From Connection Matrix Output lt 27 gt CNT DLY2 our clk 1 bit NVM reg lt 705 gt Silego Technology Inc www silego com 04 20 2015 135 GreenPAK GreenPAK1 4 Designer 4 02 Properties Type LUT IN NZ INI INO 0 0 0 zai 0 0 zal 0 o 1 zal 0 o 1 zal 0 1 o0 zal 0 1 0 zal 0 1 1 0 1 1 zal 1 0 0 zal 1 0 1 0 1 zal 1 0 1 1 1 0 zal 1 1 0 zal 1 1 1 zal 1 1 1 zal Standard gates Defined by user x Silego Technology Inc www silego com 04 20 2015 136 S SILEGO o GreenPAK1 4 Designer 4 02 Properties Clock From RC OSC Clock source RC OSC Freq Og je m Silego Technology Inc www silego com 04 20 2015 137 SN SILEGO PA GreenPAK1 4 Designer 4 02 ACMPO Block Diagram to ACMP1 ACMP2 ACMP3 s MUX input reg lt 804 gt reg lt 801 800 gt ibias Hysteresis Selection uu Selectable V L S L PIN6 aio en reg 569 reg 78 Y PIN6 aio en ON after if reg lt 855 854 gt 11 then 1 otherwis 0 100 us Delay PIN7 M N DIN Internal Vref reals Extemal VDD TV 55V PIN6 ACMPO To C
101. r Can Change the Scale Manually Lo w Zeg yL qui 0 00 General BU DU 40 00 E 03 ra aL EZ Ls n iC ber 12 1110 00 647 50 740 1295 148 18 Generator PIN 3 Sine ROG AUD AUN QS ME TC MN M zoo oo z vo o o oa a Start point 0 00 ms ia m a sinp paii 3 00 ES A AO A A REM w Global linkage PEU its l i 3 ee S M ee R Repeat exu cu ccm c cau use AI fiM 1 00 2 3 2 3 2 S E a 3 2 S Prestart state Low eae We ES oe RE ee ee rr ee Ww GSR SZ Type C SE we ev IAB EE EE AOS EA p mi pone m EN EE of gu p ae A ua Spon a Mm 2 50 R za E 1 E A eee D 7 EE ME m a e I R TEE FAR d FM ONA c k Zero offset 2 03 V H Period 1000 00 ms E Frequency Data Modify 5 ms 740 00 825 00 180 00 8 Y Auto Apply B Apply Al Start Pause Stop Min 0 00 gt Max E button turns on off the mouse coordinates on the timing diagrams Silego Technology Inc www silego com 04 20 2015 71 S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 CUSTOM Mode Figure 8 19 Choosing Period Options P adj 41 IC zd 832 50 1480 00 1665 00 740 00 1017 50 1110 00 b 4 gt Repeat count Prestart state pe 4 Prestart delay 0 00 ms End state Prestart state Output type High Z Pause type Las
102. r state changed STARTING CAE r 14 32 47 IOHID checker state changed C x em Ri 7 UNNING raa ina 14 32 47 IOHID checker successfully started 14 32 47 Initialization succeeded Expansion connector 14 32 47 Test mode is disabled 14 32 48 Input stream Callback received IDEA CER Sud 2 2 E 14 32 48 Input stream Callback received Start Generators Stop Generators 14 36 17 Test mode is di A O A 14 37 29 Device is connected 14 37 29 Reset board 14 39 01 Test mode is enabled 14 39 05 Reset board 14 39 05 Test mode is disabled 14 39 47 Test mode is enabled Device is connected In the emulation mode the test mode will be automatically turned on The current project will be loaded but not programmed to the chip and will be ready for test on the emulation board The user can change any configuration during the emulation process Note Power turns on when Emulation goes on The Power key must be turned on in emulation mode to send power to the chip otherwise the emulation will not work Power turns off when Emulation goes off Silego Technology Inc www silego com 04 20 2015 61 S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 The user can check the programmed chip using the test mode without emulation In order to do this turn on the test mode and the Power key The test mode can work without power on the chip The user will control the Power key manually Figur
103. rd Ctrl Arrow Keys or Alt Arrow Keys and rotated You can move a few blocks at the same time by using multiple select option Rotation flipping and alignment is also available for more than one block at a time Silego Technology Inc www silego com 04 20 2015 13 9 LEGO GreenPAK GreenPAK1 4 Designer 4 02 A ko 3 1 4 Properties Panel Properties panel contains all settings available for selected chip component The panel is divided in two partitions Properties and Connections Properties division contains settings and parameters that could be specified for a selected block Connection division contains settings which control the predefined connections to the selected block Last division could not be present in some blocks Some parameters and settings are common for a few blocks There are 2 types of controlling elements Edit Box and Drop List To change settings in Drop List you can click and select action or place the mouse pointer over selected list and scroll by mouse wheel To enter value into the Edit Box you can use keyboard mouse scroll or buttons at the right After finishing all configurations press Apply button to confirm changes If you want to discard changes you can press Reset button EI left from the Apply button or select another block 3 1 5 Components List The Components list is an instrument that contains all blocks available in chip It provides user with the possibility to show hide unused bl
104. refer to one of resources from the Support section 4 4 Read Chip For chip reading press the Read chip button Alternatively you can create a new file sequence manually 4 5 Exporting Data to GPD Using the GPP tool you can read an already programmed chip and export the data to GreenPAK Designer Designer generates a project which has the same configuration as the chip Components will be connected and configured but their placement will be the same as in a blank project The exported project will be created in the new window To export chip data to the GPD press Read chip to read data and press Open as new project afterward Silego Technology Inc www silego com 04 20 2015 26 SN SILEGO en GreenPAK1 4 Designer 4 02 5 Print Function Print Function component consists of two main parts Editable working area where the user can customize positions view of components and lines connecting them Preview window where the user can set up the print preferences Editable working area shows all components which where used in the design Figure 5 1 Print Editor LI Print Editor ole File Edit View o S A AJA Y Print Preview Save image Snapshot Rotate Left Rotate Right Flip Horizontal Flip vertical Add Text AddRect Add Ellipse Graphics settings 1 0 PADs Combinatorial Logic Mode Digital in without Schmitt trigger ex Res Pull Down m inout Res val 300K Init state Output float
105. rt delay delay before start End state Keep last state Prestart state pin state after generation Output type High Z Strong Drive Open Drain Drives High type of output Open Drain Drives Low Resistive Pull Up Resistive Pull Down Resistive Pull Up Down Pause type Last state Low High High Z hold state when it is paused Silego Technology Inc www silego com 04 20 2015 69 SILEGO GreenPAK GreenPAK1 4 Designer 4 02 8 2 2 Period Modes AUTO Mode All generators with AUTO option have one scale this scale MAX period of all generators with AUTO option Figure 8 17 One Scale for All Generators Generator Shown period ll Start point Stop point Global linkage Repeat Repeat count Prestart state Prestart delay End state Output type Pause type General PIN 3 Sine 0 00 ms Linked Cydic 2 Low 0 00 ms Prestart state High Z Last state Signal Generator Settings Type Phase Custom phase Amplitude Zero offset Period Frequency Data Auto Apply Silego Technology Inc 04 20 2015 Sine 10 0 00 rad 2 03V 2 03V 1000 00 ms i 1 00 Hz Modify Tmax scale 0 1000 08 Pause 70 www silego com SI LEGO GreenPAK GreenPAK1 4 Designer 4 02 Figure 8 18 Use
106. t connection can be set to either Upper connection or Bottom connection Figure 7 12 Default Key Connection Upper connection Bottom connection Default key connection Key mode Set Push hot key Upper connection Bottom connection Default key connection Key mode Set Push hot key To Upper connection 4 To Bottom connection Upper connection Bottom connection 4 GND High Z Pull Down Default key connection Set Push hot key User can configure each connection VDD GND High Z or Pull Up Down are available Silego Technology Inc 04 20 2015 www silego com 41 S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 User can assign Hot Key for Push action The assigned key will simulate mouse click over the key User can assign the same hot key to other Switches which will allow changing the key values of all the Switches with the same hot key at once Figure 7 13 Figure 7 13 Set Hot Keys Start generator Pause generator Stop generator Properties Set Start Pause hot key b N C Set Io VDD Set To GND Pull Up Pull Down Set Configurable Button Logic generator Copy settings to Exchange settings with Silego Technology Inc 04 20 2015 V 3ND GreenP AK Expansion connector www silego com 42 S SILEGO 7 2 Generators 7 2 1 Logic Generator Figure 7 14 Logic Generator Figure 7 15 Signal W
107. t state 4b Ak 4 1202 50 1295 00 1480 00 1572 50 1665 00 1850 00 740 00 1110 00 1225 00 2275 00 3150 00 Saken 3500 00 700 00 4 1050 00 4 1400 00 4 1575 00 2100 00 4 2450 00 00 00 4 2975 00 4 2800 00 0 Custom phase 0 00 rad Amplitude 2 03 V 2 03 V Period 1000 00 ms Frequency 1 00 Hz 350 00 1050 00 1575 00 1750 00 2100 00 2275 00 2450 00 3150 00 0 0 Max 1850 00 5 User can set a custom period to be displayed for any generator Note Logic and clock generators have a 75 mks delay before start The signal generator connected to PIN 8 or 9 has delay 25 mks before start In case it is connected to PIN 1 VDD or 11 the delay is 50 mks before start This delay is displayed on the graphs in Signal Wizard when the AUTO mode is ON Silego Technology Inc www silego com 04 20 2015 12 SI LEGO GreenPAK GreenPAK1 4 Designer 4 02 Figure 8 20 Start Delay WB Signal Wizard General Generator VOD Sine Shown period Auto Start point o00ms a Stop point 0 45ms H Global linkage Unlinked Repeat Cydic Repeat count E Prestart state Start point vo gt Prestart delay o 00ms sf End state Keep last state W 0 50 0 00 Output type High z Pause type Laststate Signal Generator Settings 4 00 3 50 Type Sine
108. t state Output type High Z Aki 4 4 4 4 2400 40 Pause type Last state Signal Generator Settings 4 Type Logic pattern 4 Mode Normal Levels adjustment Umax 5001 2 mV Standard dp Umin 0 0 mv E 1 500 00ms LI Umax 2 500 00 ms Umin 3 500 00 ms Umax 4 500 00 ms Umin 5 500 00 ms Umax 6 500 00 ms Umin 4 4b 4b o o o Insert dde Remove 4 4 Levels count Data Tolerance 7 mV Auto Apply ke E Min 0 00 ms Configuration options Mode Normal Invert signal mode Repeat One shot Cyclic Custom repeat option T Level sets duration of level Insert insert pulse to the entered position Remove remove pulse from the entered position Count pulse count Silego Technology Inc www silego com 04 20 2015 106 S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 Figure 10 29 Custom Signal Arbitrary waveform 700 07 2100 05 50 06 2550 06 3000 08 2400 06 1800 05 1950 05 PP dL JU UD 150 00 1050 03 1500 04 kk Start point Stop point Global linkage Linked Repeat Repeat count 2 Prestart state Low Prestart delay 0 00 ms End state Prestart state
109. te Low gt Prestart delay 0 00 ms r End state Prestart state Output type High Z Pause type Laststate gt Type Trapeze Triangle S Mode Normal v Umax 408v L Umin 0 00 V r gt Z ES 250 00 ms Ka 0 50 z 2 0 50 T2 250 00 ms S ae 0 00 0 00 pp i 250 00 ms Ka lt r lt T un un un T4 250 00 ms ka S S S 8 ms Ka e e e Auto Apply kJ Apply All Start Pause Stop Auto Min 0 00 e Max 0 25 r 9 Silego Technology Inc www silego com 04 20 2015 80 S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 Figure 8 30 Custom Signal JU Signal Wizard B50 07 000 08 2700 07 2550 06 2100 05 2250 06 2400 06 1800 05 1950 05 150 00 1050 0 1500 04 Shown period Start point 0 00 ms Stop point Global linkage Linked Repeat Repeat count 2 Prestart state Low Prestart delay 0 00 ms End state Prestart state Output type High Z Pause type Last state 4 00 3 50 i F 2 00 z 2 z 2 50 as k L j 7 c eg gt na Y e a 7 00 Y UU Go B Ww JU 1 00 n 0 50 i O0 start S 3000 08 3T 0 00 p 1050 03 1500 04 1800 05 2100 05 f ms 1200 03 1650 04 1950 05 600 02 750 02 900 02 150 00 450 01 2400 06
110. ttern Sine Custom type of waveform Constant value U voltage level Figure 10 24 Constant Value 100 01 500 04 50 04 600 05 50 00 Generator PIN 3 Constant Vo g 55 Shown period Auto Start point 0 00 ms Stop point 1000 08 ms Global linkage Linked 0 50 0 0 0 A A a S E E B A 8 a 5 S E A A a S S E 0 0 0 Repeat Cydic Repeat count 2 Prestart state Law Prestart delay 0 00 ms F End state Prestart state CYWAIN DE High Z 4 00 p d i 5 E z q r 5 5 B g E 4 00 3 5n icem areca A RE ATENE eee eae FETH 2 EN PES DOE Last state JF ue ee EH ae T V mmm Son SE Ee DEEN 2 00 i Dr es i i i E um ca I i 2 00 V a 000 0 ee VET 0 O O H R H B H H M M B i i o 100 01 450 03 100 04 I E 4 600 05 800 06 E 44 1000 08 Auto Min 0 00 we Max 1000 00 Silego Technology Inc www silego com 04 20 2015 102 GreenPAK GreenPAK1 4 Designer 4 02 S SILEGO Figure 10 25 Sine EB Signal Wizard Start point Stop point Global linkage Repeat Repeat count Prestart state Prestart delay End state Output type Pause type Custom phase Amplitude Zero offset Linked Cydic Low 0 00 ms Prestart state High Z Last state 0 0 00 rad 2 03 V
111. w silego com 04 20 2015 14 9 LEGO GreenPAK GreenPAK1 4 Designer 4 02 lt ka 3 2 Creating a Project To create a new GreenPAK Designer project go to File gt New or click the New icon on the toolbar While creating new project in GreenPAK 2 3 Designer please choose chip revision for current project Figure 3 4 Set Chip Revision IB Set chip revision Fl set chip revision E GreenPAK 3 SLG46721 chip more detail GreenPAK 3 51646721 chip more detail Select GreenPAK 3 chip revision Select GreenPAK 3 chip revision SLG46721 SLG46721 _ SLG46722 A new project will be created in current window and all unsaved changes will be lost Also you can start a new GreenPAK Designer copy and it will be loaded with the blank project By default the project is configured for minimal power consumption and some components are disabled All disabled components are darker and colored in red after selection GreenPAK 1 project uses gpp gp1 file extension GreenPAK 2 4 projects use gp2 gp3 gp4 file extension It contains information about position rotation flipping and configuration of chip blocks all wire connections and bit file seguence settings of test mode etc Interface settings will not be saved in the Project file 3 2 1 Updating Existing Projects If you load an existing project created by a previous version of GreenPAK Designer and want to save changes it will be saved in the updated f
112. ys the GreenPAK IC with 6 dotted areas and expansion connectors which are connected to pins Silego Technology Inc www silego com 04 20 2015 38 SS SILEGO en GreenPAK1 4 Designer 4 02 Dotted areas are used to configure input connections Use the context menu to manage them N C Set To VDD Set To GND Pull Up Pull Down Set Configurable Button Powered LED Ground LED Voltage divider Signal generator Logic generator Copy settings to d Exchange settings with b 7 1 Types of Areas Non Configurable Inputs Figure 7 3 7 9 Figure 7 3 N C not connected gure 7 4 Set to VDD I EA AA AY AAA aaa Set to VDD Set to GND Silego Technology Inc www silego com 04 20 2015 39 SS SILEGO en GreenPAK1 4 Designer 4 02 Ligure 7 6 Pull Configurable Inputs 7 10 configurable Button A A vm vm ie Y z Sm SM S ee ee ee m J In the above mode you can switch between VDD and GND Click your mouse over the key to change the value The switch has 2 modes Latched Unlatched default which can be configured from the context menu Silego Technology Inc www silego com 04 20 2015 40 S SILEGO GreenPAK GreenPAK1 4 Designer 4 02 Figure 7 11 Key Mode Upper connection Bottom connection Default key connection Set Push hot key N C 4 Latched Unlatched The defaul

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