TB-FMCH-HDMI2 Hardware User Manual
Contents
1. LVCMOS25 RX 1_P29 signal FPGA to FMC R9 LA33_N LVCMOS25 Unused CLK2_M2C_P LVCMOS25 Unused CLK3_M2C_P LVCMOS25 Unused LVCMOS25 Unused HA01 CC LVCMOS25 Unused HA02 P LVCMOS25 Unused HA03 P LVCMOS25 Unused 04 P LVCMOS25 Unused 5 P Rev 1 01 LVCMOS25 Unused TOKYO ELECTRON DEVICE LIMITED inreviun Pin Name 2 Description HA06 P LVCMOS25 Unused HAO7_P LVCMOS25 Unused HA08 P LVCMOS25 Unused 09 LVCMOS25 Unused HA10 P LVCMOS25 Unused HA11_P LVCMOS25 Unused HA12_P LVCMOS25 Unused HA13_P LVCMOS25 Unused HA14_P LVCMOS25 Unused HA15_P LVCMOS25 Unused HA16_P LVCMOS25 Unused HA17_P_CC LVCMOS25 Unused HA18_P LVCMOS25 Unused HA19_P LVCMOS25 Unused HA20_P LVCMOS25 Unused HA21_P LVCMOS25 Unused HA22_P LVCMOS25 Unused HA23_P LVCMOS25 Unused CLK2 2 LVCMOS25 Unused CLK3 M2C N LVCMOS25 Unused 00 LVCMOS25 Unused LVCMOS25 Unused 02 LVCMOS25 Unused LVCMOS25 Unused 04 LVCMOS25 Unused 05 LVCMOS25 Unused 06 LVCMOS25 Unused HAO7_N LVCMOS25 Unused HAO8_N LVCMOS25 Unused 09 LVCMOS25 Unused 10 LVCMOS25 Unused LVCMOS22. 50 Figure 7 2 TB FMCH HDMI2 TX Default Settings component side 52 Figure 8 1 Usage Example 54 Table 2 1 ROM Yata nti tidie dd 8 Table 4 1 HDMI Connector receiving side 14 Table 4 2 SCL SDA Jumper Setting 4 1020 ANGEN NANA 14 Table 4 3 1 lt 15 Table 4 4 Connector Pin Assignment 16 Table4 5 JIAG cm 18 Table 4 6 LED Status rd nne ner ecards seed deba d Ene 19 Table E Er a ba 19 Table 4 8 FPGA Pin 20 Table 5 1 HDMI Connector transmit side 33 Table 5 2 JP3 Jumper Setting ite bote A 34 Table 5 3 FMC Connector Pin Assignment 35 Table 5 4 JTAG 37 Jable 5 5 LED Status 38 Table 5 6 Switch 220 02 38 Table 5 7 FPGA Pin 39 Table 6 1 DDC Jumper Setting NOrmal 48 Table 6 2 DDC Jumper Set
3. Rev 1 01 TOKYO ELECTRON DEVICE LIMITED 52 inreviun Table 7 4 TB FMCH HDMI2 TX Default Switch Settings DSW RSW o Silk No Default Setting Function S1 1 OFF ADV7511 Config ROM selection S1 2 OFF S1 3 OFF S1 4 OFF 51 5 OFF Unused 51 6 OFF Unused S1 7 OFF Unused 51 8 ROM Select Signal ON DSW OFF RSW 52 ADV7511 Config ROM selection 1 2 3 4 5 6 7 8 1 01 TOKYO ELECTRON DEVICE LIMITED 53 inreviun 8 Usage Example Figure 8 1 shows a usage example Be careful about the jumper setting of the TB 6S LX150T IMG2 main board If the image is not output push the S3 of the TB FMCH HDMI2 RX or TB FMCH HDMI2 TX for only a short period of time El TB FMCH HDMI2 RX Pi 3 SE TB 6S LX150T IMG2 E x it T TB FMCH HDMI2 RX connects to CN4 TB FMCH HDMI2 RX are initial setting JPG JP7 5 6 Short JP1 1 2 Short Figure 8 1 Usage Example Table 8 1 Setting Example Silk No Setting Function Bank3 voltage setting 2 5V 3 3V FMC LPC2VADUJ voltage setting 2 5V 3 3V none Two jumpers must be always the same Bank0 voltage setting 2 5V 3 3V FMC LPC1 VADJ voltage setting 2 5V 3 3V Two jumpers must be always the same Note The bold characters are the setting in the usage example Rev 1 01 TOK
4. 48 6 2 DDC Connection Through 49 Default Switch Setting 50 Usage s jo 54 Rev 1 01 TOKYO ELECTRON DEVICE LIMITED 3 inreviun List of Figures Figure 3 1 FMC Connector Pin 9 Figure 4 1 TB FMCH HDMI2 RX Block 10 Figure 4 2 External View of TB FMCH HDMI2 RX component side 11 Figure 4 3 External View of TB FMCH HDMI2 RX solder side 11 Figure 4 4 TB FMCH HDMI2 RX Board 12 Figure 4 5 TB FMCH HDMI2 RX Power Supply 13 Figure 4 6 FPGA Output Data nnoo 27 Figure 5 1 TB FMCH HDMI2 TX Block 29 Figure 5 2 TB FMCH HDMI2 TX component side 30 Figure 5 3 TB FMCH HDMI2 TX solder 30 Figure 5 4 TB FMCH HDMI2 TX Board 31 Figure 5 5 TB FMCH HDMI2 TX Power Supply 32 Figure 5 6 FPGA Input Data Timing 46 Figure 6 1 DDC Connection Structure 48 Figure 6 2 DDC Connection Structure 49 Figure 7 1 TB FMCH HDMI2 RX Default Switch Settings component side
5. TX 1_SPDIF LVCMOS33 TX 1 SPDIF Digital Audio FPGA to TX TX 1_MCLK LVCMOS33 TX 1 Audio Master Clock FPGA to TX TXHT 1250 LVCMOS33 TX 1 125 Audio signal 0 FPGA to TX TXHT 1251 LVCMOS33 TX 1 125 Audio signal 1 FPGA to TX TXHT 1252 LVCMOS33 TX 1 125 Audio signal 2 FPGA to TX TXHT 1253 LVCMOS33 TX 1 125 Audio signal 3 FPGA to TX TX 1_SCLK LVCMOS33 TX 1 Audio serial clock FPGA to TX TX 1_LRCLK LVCMOS33 TX 1 LRCLK signal FPGA to TX TX 1_HPD_IO LVCMOS33 TX 1 hot plug control FPGA to TX TX 1_PD LVCMOS33 TX 1 power down FPGA to TX TX 1_INT LVCMOS33 TX 1 interrupt TX to FPGA TX 1_SCL O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O LVCMOS33 TX 1 serial clock FPGA to TX TX 1_SDA LVCMOS33 TX 1 serial data FPGA to from TX RSWO LVCMOS33 Rotary switch 0 RSW1 Rev 1 01 LVCMOS33 Rotary switch 1 TOKYO ELECTRON DEVICE LIMITED 44 inreviun Pin Name o Spec Description RSW2 LVCMOS33 Rotary switch 2 RSW3 LVCMOS33 Rotary switch 3 DSWO LVCMOS33 DIP switch O DSW1 LVCMOS33 DIP switch 1 DSW2 LVCMOS33 DIP switch 2 DSW3 LVCMOS33 DIP switch 3 DSW4 LVCMOS33 DIP switch 4 DSW5 LVCMOS33 DIP swi
6. 04 P LVCMOS25 RXHO P1 signal FPGA to FMC B1 05 LVCMOS25 P2 signal FPGA to FMC B2 LAO6 P LVCMOS25 signal FPGA to FMC B3 LAO7 P LVCMOS25 signal FPGA to FMC B4 08 P LVCMOS25 RXH0 P5 signal FPGA to FMC B5 09 LVCMOS25 P6 signal FPGA to FMC B6 LA10 P LVCMOS25 signal FPGA to FMC B7 LA11 P LVCMOS25 P8 signal FPGA to FMC B8 LA12 P LVCMOS25 P9 signal FPGA to FMC B9 LA13 P LVCMOS25 RX 0_P10 signal FPGA to FMC G0 14 LVCMOS25 P11 signal FPGA to FMC 91 LA15 LVCMOS25 RXHO P12 signal FPGA to FMC G2 LA16_P LVCMOS25 RX 0_P13 signal FPGA to FMC G3 LA17 P CC LVCMOS25 RX 0_P14 signal FPGA to FMC G4 LA18_P_CC LVCMOS25 RX 0_P15 signal FPGA to FMC G5 LA19 P LVCMOS25 RX 0_P16 signal FPGA to FMC G6 LA20_P LVCMOS25 RX 0_P17 signal FPGA to FMC G7 LA21_P LVCMOS25 RX 0_P18 signal FPGA to FMC G8 LA22 P LVCMOS25 RXHO P19 signal FPGA to FMC G9 LA23 P LVCMOS25 RX 0_P20 signal FPGA to FMC RO LA24 P LVCMOS25 RX 0_P21 signal FPGA to FMC R1 LA25 P LVCMOS25 RX 0_P22 signal FPGA to FMC R2 LA26_P LVCMOS25 RX 0_P23 signal
7. GND LAO3 N LAO4 P 07 06 8 GND LA04_N GND 06 HAO8_N LA08_P GND HA11_P GND GND LAO8 LA07_P HA11_N HA10_P HA12 P GND 07 GND 12 LA12 GND HA14 P GND GND LA12_N LA11_P HA14_N 17 CC HA15 P GND LA11_N GND HA17_N_CC HA15_N LA16 P GND HA18 P GND GND LA16 LA15 P 18 21 19 GND LA15_N GND HA21_N 19 LA20 P GND HA22 P GND GND LA20 LA19 P 22 HA23 02 GND 19 GND HA23_N 02 LA22 P GND HBO1 P GND GND LA22 LA21 HBO1_N 00 HB04 P GND LA21 N GND HBOO N CC 04 LA25 P GND P GND GND LA25 LA24 P 07 06 08 GND 424 GND 06 CC 08 LA29 P GND HB11_P GND GND LA29 LA28 P HB11_N HB10_P HB12 P GND LA28 N GND HB10 N HB12 N LA31 P GND HB15 P GND GND LA31 N LA30 P HB15 N HB14 P HB16 P GND LA30 N GND HB14 N HB16 N LA33 P GND HB18 P GND GND LA33 N LA32 P HB18 N HB17 P CC HB20 P GND LA32 N GND HB17
8. RXH 1282 LVCMOS33 RX 1 125 Audio Signal 2 RX to FPGA RXH 1253 LVCMOS33 RX 1 125 Audio Signal 3 RX to FPGA RX 1_LRCLK LVCMOS33 RX 1 LRCLK Signal RX to FPGA RX 1_SCL LVCMOS33 RX 1 2 Serial Clock FPGA to RX RX 1_SDA LVCMOS33 RX 1 I2C Serial Data RX to from FPGA RX 1_INT1 LVCMOS33 RX 1 Interrupt Input 1 RX to FPGA RX 1_RESETN LVCMOS33 RX 1 Reset FPGA to RX RX 1_CSN LVCMOS33 RX 1 CS Output FPGA to RX RX 1_CEC LVCMOS33 RX 1 Signal RX to from FPGA RX 1_DDCA_SCL_F LVCMOS33 RX 1 DDC Serial Clock RX to FPGA RX 1_DDCA_SDA_F LVCMOS33 RX 1 DDC Serial Data RX lt gt FPGA RX 1_HPD_IO LVCMOS33 RX 1 Hot Plug Control FPGA to RX RX 1_DET1 LVCMOS33 RX 1 Detect Signal RX to FPGA RSWO LVCMOS33 Rotary Switch 0 RSW1 LVCMOS33 Rotary Switch 1 RSW2 LVCMOS33 Rotary Switch 2 RSW3 LVCMOS33 Rotary Switch 3 DSWO LVCMOS33 DIP Switch 0 DSW1 Rev 1 01 LVCMOS33 DIP Switch 1 TOKYO ELECTRON DEVICE LIMITED 25 inreviun o Pin Name DSW2 DSW3 DSW4 DSW5 DSW6 DSW7 LEDO LED1 LED2 LED3 LED4 LED5 LED6 LED7 Spec Description LVCMOS33 DIP Switch 2 LVCMOS33 Switch 3 LVCMOS33 Switch 4 LVCMOS33 Switch 5 LVCMOS33 Switch 6 LVCMOS33 Switch 7 LVCMOS33 LEDO LVCMOS33
9. 23 LVCMOS25 Unused TX 0_D35 LVCMOS33 TX 0 Video data 35 FPGA to TX TXH0 D34 LVCMOS33 TX 0 Video data 34 FPGA to TX TXH0 D33 LVCMOS33 TX 0 Video data 33 FPGA to TX TX 0_D32 LVCMOS33 TX 0 Video data 32 FPGA to TX TX 0_D31 LVCMOS33 TX 0 Video data 31 FPGA to TX TX 0_D30 LVCMOS33 TX 0_D29 LVCMOS33 TX 0 Video data 29 FPGA to TX TX 0_D28 LVCMOS33 TX 0 Video data 30 FPGA to TX TX 0 Video data 28 FPGA to TX TX 0_D27 LVCMOS33 TX 0 Video data 27 FPGA to TX TX 0_D26 LVCMOS33 TX 0 Video data 26 FPGA to TX TX 0_D25 LVCMOS33 TX 0 Video data 25 FPGA to TX TX 0_D24 LVCMOS33 TX 0 Video data 24 FPGA to TX TX 0_D23 LVCMOS33 TX 0 Video data 23 FPGA to TX TX 0_D22 LVCMOS33 TX 0 Video data 22 FPGA to TX TX 0_D21 LVCMOS33 TX 0 Video data 21 FPGA to TX TX 0_D20 LVCMOS33 TX 0 Video data 20 FPGA to TX TX 0_D19 LVCMOS33 TX 0 Video data 19 FPGA to TX TX 0_D18 LVCMOS33 TX 0_D17 LVCMOS33 TX 0 Video data 17 FPGA to TX TX 0_D16 LVCMOS33 TX 0 Video data 16 FPGA to TX TX 0_D15 LVCMOS33 TX 0 Video data 15 FPGA to TX TXHO_D14 LVCMOS33 TX 0 Video data 14 FPGA to TX TXH0 D13 LVCMOS33 TX 0 Video data 18 FPGA to TX TX 0 Video data 13 FPGA to TX TX 0_D12 LVCMOS
10. 90 LA14 LVCMOS25 D11 Signal FMC to FPGA G1 LA15 P LVCMOS25 TX 0_D12 Signal FMC to FPGA G2 LA16 P LVCMOS25 TX 0_D13 Signal FMC to FPGA G3 LA17_P_CC LVCMOS25 TX 0_D14 Signal FMC to FPGA G4 LA18_P_CC LVCMOS25 TX 0_D15 Signal FMC to FPGA G5 LA19 LVCMOS25 TX 0_D16 Signal FMC to FPGA G6 LA20 P LVCMOS25 TX 0_D17 Signal FMC to FPGA G7 LA21 P LVCMOS25 TX 0_D18 Signal FMC to FPGA G8 LA22 P LVCMOS25 TX 0_D19 Signal FMC to FPGA G9 LA23 LVCMOS25 TX 0_D20 Signal FMC to FPGA RO LA24 P LVCMOS25 TX 0_D21 Signal FMC to FPGA R1 LA25 P LVCMOS25 TX 0_D22 Signal FMC to FPGA R2 LA26 LVCMOS25 TX 0_D23 Signal FMC to FPGA R3 LA27 P LVCMOS25 TX 0_D24 Signal FMC to FPGA R4 LA28 LVCMOS25 TX 0_D25 Signal FMC to FPGA RS LA29 P LVCMOS25 TX 0_D26 Signal FMC to FPGA R6 LA30 P LVCMOS25 TX 0_D27 Signal FMC to FPGA R7 LA31_P LVCMOS25 TX 0_D28 Signal FMC to FPGA R8 LA32 P LVCMOS25 TX 0_D29 Signal FMC to FPGA R9 LA33 P LVCMOS25 Unused CLKO M2C N LVCMOS25 TX DCLK Signal FMC to FPGA CLK1 M2C N Rev 1 01 LVCMOS25 Unused TOKYO ELECTRON DEVIC
11. GND DP2 C9M P GND LA23 N 05 P GND DP2 C9M N GND GND 05 DP2 P GND LA27 P LA26 P GND DP2 2 GND 27 LA26 N 09 GND DP2 8 GND GND 09 GND DP2 C8M GND TCK GND DP3 C2M P GND SCL TDI HB13 P DP3 C2M N GND SDA TDO HB13 N GND DP2 C7M P GND 3 3VAUX GND GND DP2 C7M N GND TMS 19 DP4 P GND GAO TRST HB19_N DP4 2 GND 12V GA1 GND GND DP2_C6M_P GND 3 3V HB21 GND DP2 6 12V GND HB21_N DP5_C2M_P GND GND 3 3V GND DP5 2 GND 3 3V GND VADJ GND Rev 1 01 RESO GND 3 3V TOKYO ELECTRON DEVICE LIMITED GND 16 inreviun F row G row H row J row K row PG_M2C GND VREF A M2C GND VREF B M2C GND CLK1 M2C P PRSNT M2C L CLK3 M2C P GND GND CLK1 M2C N GND CLK3 M2C N GND HAO0 P CC GND CLKO M2C P GND CLK2 M2C P 00 CC GND CLKO GND CLK2 M2C N GND 00 P GND GND GND LA00 CC 02 P 2 P 04 GND 02 GND 2 04 LA03 P GND 07 P GND
12. Unused HA12 P LVCMOS25 Unused HA13 P LVCMOS25 Unused HA14 P LVCMOS25 Unused HA15 P LVCMOS25 Unused HA16 P LVCMOS25 Unused HA17 CC LVCMOS25 Unused HA18 P LVCMOS25 Unused HA19 P LVCMOS25 Unused HA20 P LVCMOS25 Unused HA21 P LVCMOS25 Unused HA22 P LVCMOS25 Unused HA23 P LVCMOS25 Unused CLK2 M2C N LVCMOS25 Unused CLK3 M2C N LVCMOS25 Unused 00 CC LVCMOS25 Unused 01 CC LVCMOS25 Unused 02 LVCMOS25 Unused LVCMOS25 Unused 04 LVCMOS25 Unused 05 LVCMOS25 Unused 06 LVCMOS25 Unused 07 LVCMOS25 Unused 08 LVCMOS25 Unused 09 LVCMOS25 Unused 10 LVCMOS25 Unused HA11 LVCMOS25 Unused 12 LVCMOS25 Unused 13 LVCMOS25 Unused 14 LVCMOS25 Unused HA15_N LVCMOS25 Unused HA16_N LVCMOS25 Unused HA17 CC LVCMOS25 Unused HA18 LVCMOS25 Unused 19 LVCMOS25 Unused HA20 N LVCMOS25 Unused HA21_N Rev 1 01 LVCMOS25 Unused TOKYO ELECTRON DEVICE LIMITED inreviun Pin Name Spec Description 22 LVCMOS25 Unused
13. LVCMOS33 RX 0 Video data 21 RX to FPGA RX 0_P20 LVCMOS33 RX 0 Video data 20 RX to FPGA RX 0_P19 LVCMOS33 RX 0 Video data 19 RX to FPGA RX 0_P18 LVCMOS33 gt 1 gt ae RX 0 Video data 18 RX to FPGA RXHO P17 LVCMOS33 RX 0 Video data 17 RX to FPGA RXHO P16 LVCMOS33 RXH0 15 LVCMOS33 gt RX 0 Video data 15 RX to FPGA RXHO P14 LVCMOS33 RX 0 Video data 14 RX to FPGA RXHO P13 LVCMOS33 RX 0 Video data 16 RX to FPGA RX 0 Video data 13 RX to FPGA RXHO P12 LVCMOS33 RX 0 Video data 12 RX to FPGA RXHO P11 LVCMOS33 RX 0 Video data 11 RX to FPGA RX 0_P10 LVCMOS33 YS RX 0 Video data 10 RX to FPGA RX 0_P9 LVCMOS33 RX 0 Video data 9 RX to FPGA RXH0 LVCMOS33 RX 0 Video data 8 RX to FPGA RXH0 P7 LVCMOS33 RX 0 Video data 7 RX to FPGA RX 0_P6 LVCMOS33 RX 0 Video data 6 RX to FPGA RXHO P5 LVCMOS33 RX 0 Video data 5 RX to FPGA RX 0_P4 LVCMOS33 RX 0 Video data 4 RX to FPGA RX 0_P3 LVCMOS33 RX 0 Video data 3 RX to FPGA RX 0_P2 LVCMOS33 RX 0 Video data 2 RX to FPGA RXHO P1 LVCMOS33 RX 0 Video data 1 RX to FPGA RXHO PO LVCMOS33 RX 0 Video data 0 RX to FPGA RXHO DE LVCMOS33 RX 0 data enable
14. MONITOR DDC 5V DDC GND HOTPLUG DET DDC SCL DDC SCL Figure 6 2 DDC Connection Structure Through To select DDC connection Through connect RX board J4 and TX board J1 or RX board J2 and TX board J3 using an attached cable Rev 1 01 TOKYO ELECTRON DEVICE LIMITED 49 inreviun 7 Default Switch Setting Figure 7 1 shows default TB FMCH HDMI2 RX switch settings portions enclosed by dotted lines JP7 JP12 10 JP11 en JP1 LUD JP17 JP15 JP13 Figure 7 1 TB FMCH HDMI2 RX Default Switch Settings component side Table 7 1 TB FMCH HDMI2 RX Default Settings JP pin Silk No Initial Setting Function SCLO 1 2 HDMI 2 3 FPGA SDAO 1 2 HDMI 2 3 FPGA DDCO 5 1 2 Normal 2 3 Through DDCO HPD 1 2 Normal 2 3 Through DDCO SDA 1 2 Normal 2 3 Through DDCO SCL 1 2 Normal 2 3 Through DDCO GND 1 2 Normal 2 3 Through 1 2 3 4 5 6 7 8 SCL1 1 2 HDMI 2 3 FPGA SDA1 1 2 HDMI 2 3 FPGA DDC1_5V 1 2 Normal 2 3 Through DDC1_HPD 1 2 Normal 2 3 Through DDC1 SDA 1 2 Normal 2 3 Through DDC1 SCL 1 2 Normal 2
15. Otherwise the product may be damaged B Disclaimer This product is HDMI interface for Xilinx FPGA evaluation boards Tokyo Electron Device Limited assumes no responsibility for any damages resulting from the use of this product for purposes other than those stated Even if the product is used properly Tokyo Electron Device Limited assumes no responsibility for any damages caused by 1 Earthquake thunder natural disaster or fire resulting from the use beyond our responsibility acts by a third party or other accidents the customer s willful or accidental misuse or use under other abnormal conditions 2 Secondary impact arising from use of this product or its unusable state business interruption or others 3 Use of this product against the instructions given in this manual 4 Malfunctions due to connection to other devices Tokyo Electron Device Limited assumes no responsibility or liability for 1 Erasure or corruption of data arising from use of this product 2 Any consequences or other abnormalities arising from use of this product or 3 Damage of this product not due to our responsibility or failure due to modification This product has been developed by assuming its use for research testing or evaluation It is not authorized for use in any system or application that reguires high reliability Repair of this product is carried out by replacing it on a chargeable basis not repairing the faulty devices How
16. RX to FPGA RXHO LLC LVCMOS33 RX 0 LLC signal RX to FPGA RX 0_SCLK LVCMOS33 RX 0 Audio serial clock RX to FPGA RX 0_MCLKOUT LVCMOS33 RX 0 Audio master clock RX to FPGA Rev 1 01 TOKYO ELECTRON DEVICE LIMITED 23 inreviun Pin Name Description SYSCLK P LVCMOS33 System Clock 27 2 RX 0_HSYNC LVCMOS33 RX 0 HSYNC RX to FPGA RX 0_VSYNC LVCMOS33 RX 0 VSYNC RX to FPGA RX 0_SPDIF LVCMOS33 RX 0 SPDIF Digital Audio RX to FPGA RX 0_12S0 LVCMOS33 RX 0 125 Audio Signal 0 RX to FPGA RX 0_12S1 LVCMOS33 RX 0 125 Audio Signal 1 RX to FPGA 0 1252 LVCMOS33 RX 0 125 Audio Signal 2 RX to FPGA 0 1253 LVCMOS33 RX 0 125 Audio Signal 3 RX to FPGA RX 0_LRCLK LVCMOS33 RX 0 LRCLK Signal RX to FPGA RX 0_SCL LVCMOS33 RX 0 2 Serial Clock FPGA to RX RX 0_SDA LVCMOS33 RX 0 2 Serial Data RX to from FPGA RXFO INT1 LVCMOS33 RX 0 Interrupt Input 1 RX to FPGA RX 0_RESETN LVCMOS33 RX 0 Reset FPGA to RX RX 0_CSN LVCMOS33 RX 0 CS Output FPGA to RX RX 0_CEC LVCMOS33 RX 0 CEC Signal RX to from FPGA RX 0 DDCA LVCMOS33 RX 0 DDC Serial Clock RX to FPGA RX 0 DDCA SDA LVCMOS33 RX 0 DDC Serial Data RX to from FPGA 0 LVCMOS33 RX 0 Hot Plug Control FPGA to RX DET1 LVCMOS33 RX 0 Detect Signal RX to FPGA FPGA_SRSTN LVCMOS33
17. 0_DSD2 LVCMOS33 TX 0 DSD Audio data 2 FPGA to TX TX 0_DSD3 LVCMOS33 TX 0 DSD Audio data 3 FPGA to TX TX 0_DSD4 LVCMOS33 TX 0 DSD Audio data 4 FPGA to TX TX 0_DSD5 LVCMOS33 TX 0 DSD Audio data 5 FPGA to TX TX40 DSD LVCMOS33 TX 0 DSD clock FPGA to TX TX 0_SPDIF LVCMOS33 TX 0 SPDIF Digital Audio FPGA to TX TX 0_MCLK LVCMOS33 TX 0 Audio Master Clock FPGA to TX TXHO 1250 LVCMOS33 125 Audio Signal 0 FPGA to TX TXHO 1251 LVCMOS33 125 Audio Signal 1 FPGA to TX TXHO 1282 LVCMOS33 TXHO 1253 LVCMOS33 125 Audio Signal FPGA to TX TX 0_SCLK LVCMOS33 TX 0 125 Audio Signal 2 FPGA to TX TX 0 Audio Serial Clock FPGA to TX TX 0_LRCLK LVCMOS33 TX 0 LRCLK Signal FPGA to TX LVCMOS33 TX 0 Hot Plug Control FPGA to TX TX 0 PD LVCMOS33 TX 0 Power Down FPGA to TX TXH0 INT LVCMOS33 TXHO Interrupt TX to FPGA TX 0_SCL Ol 1010101J01010 J0 10 10 10 0 0 0 0 0 O0 0 O LVCMOS33 TX 0 Serial Clock FPGA to TX TX 0_SDA LVCMOS33 TX 0 Serial Data FPGA to TX FPGA SRSTN LVCMOS33 FPGA Reset TX 1_D35 LVCMOS33 TX 1 Video data 35 FPGA to TX TX 1_D34 LVCMOS33 TX 1 Video data 34 FPGA to TX TX 1_D33 LVCMOS33 TX 1_D32 LVCMOS33 TX 1 Video da
18. 2 DDC Jumper Setting Through TB FMCH HDMI2 RX TB FMCH HDMI2 TX Jumper JP6 SCLO Setting Open Jumper Setting JP7 SDAO Open JP8 DDCO_5V 1 2 short Normal JP7 DDCO 5V 1 2 short Normal JP9 DDCO HPD 1 2 short Normal JP8 DDCO HPD 1 2 short Normal JP10 DDCO SDA 2 3 short Through JP4 DDCO SDA 2 3 short Through JP11 DDCO SCL 2 3 short Through JP5 DDCO SCL 2 3 short Through JP12 DDCO GND 2 3 short Through JP6 DDCO GND 2 3 short Through JP3 SCL1 Open JP4 SDA1 Open JP13 DDC1 5V 1 2 short Normal JP12 DDC1 5V 1 2 short Normal JP14 DDC1 HPD 1 2 short Normal JP13 DDC1 HPD 1 2 short Normal JP15 DDC1 SDA 2 3 short Through JP9 DDC1 SDA 2 3 short Through JP16 DDC1 SCL 2 3 short Through JP10 DDC1 SCL 2 3 short Through JP17 DDC1 GND 2 3 short Through TB FMCH HDMI2 RX JP11 DDC1_GND 2 3 short Through TB FMCH HDMI2 TX SCL SG DDC SDA 5V HDMI DDC GND HOTPLUG DET DDC SCL EEPROM DEC DDC SCL F DDC SDA DDC Cable DDC SCL
19. 24 inreviun Pin Name Spec Description RX 1_P13 LVCMOS33 RX 1 Video Data 13 RX to FPGA RX 1_P12 LVCMOS33 RX 1 Video Data 12 RX to FPGA RX 1_P11 LVCMOS33 RX 1 Video Data 11 RX to FPGA RX 1_P10 LVCMOS33 RX 1 Video Data 10 RX to FPGA RX 1_P9 LVCMOS33 RX 1 Video Data 9 RX to FPGA RX 1_P8 LVCMOS33 RX 1 Video Data 8 RX to FPGA RX 1_P7 LVCMOS33 RX 1 Video Data 7 RX to FPGA RX 1_P6 LVCMOS33 RX 1 Video Data 6 RX to FPGA RX 1_P5 LVCMOS33 RX 1 Video Data 5 RX to FPGA RX 1_P4 LVCMOS33 RX 1 Video Data 4 RX to FPGA RX 1_P3 LVCMOS33 RX 1 Video Data 3 RX to FPGA RX 1_P2 LVCMOS33 RX 1 Video Data 2 RX to FPGA RX 1_P1 LVCMOS33 RX 1 Video Data 1 RX to FPGA 1_ LVCMOS33 RX 1 Video Data 0 RX to FPGA RX 1_DE LVCMOS33 RX 1 Data Enable RX to FPGA RX 1_LLC LVCMOS33 RX 1 LLC Signal RX to FPGA RX 1_SCLK LVCMOS33 RX 1 Audio Serial Clock RX to FPGA RX 1_MCLKOUT LVCMOS33 RX 1 Audio Master Clock RX to FPGA RX 1_HSYNC LVCMOS33 RX 1 HSYNC RX to FPGA RX 1_VSYNC LVCMOS33 RX 1 VSYNC RX to FPGA RX 1_SPDIF LVCMOS33 RX 1 SPDIF Digital Audio RX to FPGA RX 1_12S0 LVCMOS33 RX 1 125 Audio Signal 0 RX to FPGA RXH 1251 LVCMOS33 RX 1 125 Audio Signal 1 RX to FPGA
20. LED1 LVCMOS33 LED2 LVCMOS33 LED3 LVCMOS33 LED4 LVCMOS33 LED5 LVCMOS33 LED6 LVCMOS33 LED7 Rev 1 01 TOKYO ELECTRON DEVICE LIMITED 26 inreviun 4 11 FPGA Output Data Phase Figure 4 6 shows the output data phase of FPGA on TB FMCH HDMI2 RX FPGA to FMC data is output at the falling edge of the video clock The data should be latched at the rising edge on the main board side FPGA gt FMC HDMIRX CLK VSYNC HSYNC Output data are synchronous with down edge of HDMIRX_CLK Figure 4 6 FPGA Output Data Timing Rev 1 01 TOKYO ELECTRON DEVICE LIMITED inreviun 4 12 Image Size 4 12 1 2D Image Size TB FMCH HDMI2 RX supports HDMI1 4 compliant primary format and part of secondary format 1080p 60Hz Supported image size 640x480p 59 94 60Hz 1280x720p 59 94 60Hz 1920x1080i 59 94 60Hz 720x480p 59 94 60Hz 720 1440 x480i 59 94 60Hz 1280x720 50Hz 1920x1080i 50Hz 720x576p 50Hz 720 1440 x576i 50Hz 1920x1080p 59 94 60Hz 1920x1080p 50Hz 4 12 2 3D Image Size TB FMCH HDMI2 RX supports HDMI1 4 compliant primary format Supported image size 1280x720p 59 94 60Hz Frame Packing Side by Side Half Top and Bottom 1280x720p 50Hz Frame Packing Side by Side Half Top and Bottom 1280x720p 23 98 24Hz Frame Packing 1280x720p 23 97 30Hz Frame Packing 1920x1080i 59 94 60Hz Frame Packing
21. Output 3 12bit Output 1 53 Rev 1 01 TOKYO ELECTRON DEVICE LIMITED FPGA reconfig long push 3 seconds FPGA reset short push 38 inreviun 5 10 FPGA Pin Assignment Table 5 7 shows the FPGA pin assignment In case of 8 bit signal format active bits are assigned to MSB 8 bit of each RGB pin of FMC LSB 2 bit are always 2100 in 8 bit signal format Table 5 7 FPGA Pin Assignment Pin Name Spec Description CLKO M2C P LVCMOS25 TX 0_DCLK Signal FMC to FPGA CLK1 M2C P LVCMOS25 Unused LA00_P_CC LVCMOS25 TX 0_VSYNC Signal FMC to FPGA LAO1 P CC LVCMOS25 TX 0_HSYNC Signal FMC to FPGA LAO2 LVCMOS25 TX 0_DE Signal FMC to FPGA LAO3 P LVCMOS25 TXH0 DO Signal to FPGA BO LA04_P LVCMOS25 TX 0_D1 Signal FMC to FPGA B1 LA05_P LVCMOS25 TX 0_D2 Signal FMC to FPGA B2 LAO6 LVCMOS25 TX 0_D3 Signal FMC to FPGA B3 LA07_P LVCMOS25 TX 0_D4 Signal FMC to FPGA B4 LA08 LVCMOS25 TX 0_D5 Signal FMC to FPGA B5 09 P LVCMOS25 TX 0_D6 Signal FMC to FPGA B6 LA10 P LVCMOS25 TX 0_D7 Signal FMC to FPGA B7 LA11_P LVCMOS25 TX 0_D8 Signal FMC to FPGA B8 LA12 P LVCMOS25 TX 0_D9 Signal FMC to FPGA B9 LA13_P LVCMOS25 TX 0_D10 Signal FMC to FPGA
22. P FMC Connector Samtec s ASP 134488 01 HDMI Connector common Molex s 5002541927 Power Supply common Jumper switch selection The RX board has an EEPROM for Display Data Channel hereafter referred to as DDC and allows setting the AnalogDevices s ADV7612BSWZ P board operation via jumpers GND___ DPOC2MN __ M2C P LPC Connector LPC Connector Figure 3 1 FMC Connector Pin Layout Rev 1 01 TOKYO ELECTRON DEVICE LIMITED inreviun 4 TB FMCH HDMI2 RX 4 1 Block Diagram Figure 4 1 shows the TB FMCH HDMI2 RX block diagram The FMC HPC connector is mounted on the solder side of the board FMC HPC FPGA DECHO HDMI 0 RX RX 0_P 35 0 0 0 0 2 RX 0_VS HS DE RX 0_DDCA SCL LA 33 00 P N RXHO LLC RX 0_D
23. Side by Side Half 1920x1080i 50Hz Frame Packing Side by Side Half 1920x1080p 23 98 24Hz Frame Packing Side by Side Half Top and Bottom 1920x1080p 29 97 30Hz Frame Packing Top and Bottom 1920x1080p 59 94 60Hz Top and Bottom 1920x1080p 250Hz Top and Bottom Rev 1 01 TOKYO ELECTRON DEVICE LIMITED 28 inreviun 5 TB FMCH HDMI2 TX 5 1 Block Diagram Figure 5 1 shows a TB FMCH HDMI2 TX block diagram The FMC HPC connector is mounted on the solder side of the board ENCHO HDMI 0 TX TX 0_DI35 0 TXHO 0 2 0 VS HS DE TX 0 SCL LA 33 00 P N TX 0 SDA HA 23 00 P N TXHO DSD 5 0 CECHO CLK 3 0 M2C P N TX 0_DSDCLK TX 0_SPDIF HEACHO MCLK me TO SISO 500254 1927 TXH0 SCLK TXHOLROLK 8 DDOO SCL 0 PD DDCOSDA CLK TXHOINT
24. handled incorrectly N Caution Indicates the possibility of injury or physical damage in connection with houses or household goods if the product is handled incorrectly The following graphical symbols are used to indicate and classify precautions in this manual Examples Turn off the power switch X Do not disassemble the product Do not attempt this Rev 1 01 TOKYO ELECTRON DEVICE LIMITED 5 inreviun In the event of a failure disconnect the power supply If the product is used as is a fire or electric shock may occur Disconnect the power supply immediately and contact our sales personnel for repair If an unpleasant smell or smoking occurs disconnect the power supply If the product is used as is a fire or electric shock may occur Disconnect the power supply immediately After verifying that no smoking is observed contact our sales personnel for repair Do not disassemble repair or modify the product Otherwise a fire or electric shock may occur due to a short circuit or heat generation For inspection modification or repair contact our sales personnel Do not touch a cooling fan As a cooling fan rotates in high speed do not put your hand close to it Otherwise it may cause injury to persons Never touch a rotating cooling fan Do not place the product on unstable locations Otherwise it may drop or fall resulting
25. 03EDCB VCC_2 5V 15 PEST ET gt i _ FPGA VCCIO 261mA 663 1 6575W LTC3026EMSE VCC 1 8V0 e 7511 19 XCFIGVCCINT 10mA 1 LTC3026EMSE VCC 1 8V1 Figure 5 5 TB FMCH HDMI2 TX Power Supply Structure Rev 1 01 TOKYO ELECTRON DEVICE LIMITED 32 inreviun 5 5 HDMI Transmitter The HDMI connector uses MOLEX s 5002541927 The HDMI transmitter uses Analog Devices s ADV7511KSTZ P The following device is used for ESD protection ESD protection Semtech s RCLAMP0524 and RCLAMP0504 Table 5 1 shows the HDMI connector pin assignment Table 5 1 HDMI Connector transmit side Name Description TMDS DATA2 TMDS Transmit Data 2 TMDS SHLD2 TMDS Transmit Data 2 Shield TMDS DATA2 TMDS Transmit Data 2 TMDS DATA1 TMDS Transmit Data 1 TMDS SHLD1 TMDS Transmit Data 1 Shield TMDS DATA1 TMDS Transmit Data 1 TMDS DATAO TMDS Transmit Data 0 TMDS SHLDO TMDS Transmit Data 0 Shield TMDS DATAO TMDS Transmit Data 0 TMDS CLK TMDS Transmit Clock TMDS CLK SHLD TMDS Transmit Clock Shield TMDS CLK TMDS Transmit Clock CEC CEC Signal UTILITY HEAC HEAC Signal DDC_SCL DDC Serial Clock DDC_SDA DDC Serial Data DDC CEC GND DDC CEC Ground DDC 5V 5V HPD HEAC Rev 1 01 Hot Plug Detection HEAC Signal TOKYO
26. 3 Through DDC1 GND 1 2 Normal 2 3 Through 12VIN SEL 1 2 FMC connector 2 3 External power source Rev 1 01 TOKYO ELECTRON DEVICE LIMITED 50 inreviun Table 7 2 TB FMCH HDMI2 RX Default Setting DSW RSW o Silk No Default Setting Function S1 1 OFF ADV7612 Config ROM selection S1 2 OFF S1 3 OFF S1 4 OFF 51 5 OFF Unused 51 6 OFF Unused S1 7 OFF Unused 51 8 ROM Select Signal ON DSW OFF RSW 52 ADV7612 Config ROM selection 1 2 3 4 5 6 7 8 1 01 TOKYO ELECTRON DEVICE LIMITED N evu Figure 7 2 shows TB FMCH HDMI2 TX default switch settings portions enclosed by dotted lines JP8 JP5 JP4 JP6 JP7 y JP3 ue FR ert m JP12 JP13 10 JP9 JP11 Figure 7 2 TB FMCH HDMI2 TX Default Settings component side Table 7 3 TB FMCH2 TX Default Settings JP Pin Silk No Initial Setting Function DDCO 5V 1 2 Normal 2 3 Through DDCO HPD 1 2 Normal 2 3 Through DDCO SDA 1 2 Normal 2 3 Through DDCO SCL 1 2 Normal 2 3 Through GND 1 2 Normal 2 3 Through DDC1 5V 1 2 Normal 2 3 Through DDC1 HPD 1 2 Normal 2 3 Through DDC1 SDA 1 2 Normal 2 3 Through DDC1 SCL 1 2 Normal 2 3 Through DDC1 GND 1 2 Normal 2 3 Through 12VIN SEL 1 2 FMC connector 2 3 External power source 1 2 3 4 5 6 7 8 9
27. 33 TX 0 Video data 12 FPGA to TX TX 0_D11 LVCMOS33 TX 0 Video data 11 FPGA to TX TX 0_D10 LVCMOS33 TX 0 Video data 10 FPGA to TX TX 0_D9 LVCMOS33 TX 0 Video data 9 FPGA to TX TX 0_D8 LVCMOS33 TX 0 Video data 8 FPGA to TX TXHO D7 LVCMOS33 TX 0 Video data 7 FPGA to TX TX 0_D6 LVCMOS33 TX 0 Video data 6 FPGA to TX TXHO LVCMOS33 TX 0 Video data 5 FPGA to TX TX 0_D4 LVCMOS33 TXHO D3 LVCMOS33 TX 0 Video data FPGA to TX TX 0_D2 LVCMOS33 TX 0 Video data 2 FPGA to TX TXHO DA LVCMOS33 TX 0 Video data 1 FPGA to TX TX40 DO LVCMOS33 TX 0 Video data 0 FPGA to TX TX 0_DCLK LVCMOS33 TX 0 Video data 4 FPGA to TX TX 0 DCLK signal FPGA to TX SYSCLK P LVCMOS33 System clock 27MHz TXHO DE LVCMOS33 TX 0 data enable FPGA to TX TX 0_HSYNC LVCMOS33 TX 0 HSYNC FPGA to TX Rev 1 01 TOKYO ELECTRON DEVICE LIMITED 42 Pin Name o Spec Description inreviun TXHO VSYNC LVCMOS33 TX 0 VSYNC FPGA to TX TXHO DSDO LVCMOS33 TX 0 DSD Audio data 0 FPGA to TX TX 0_DSD1 LVCMOS33 TX 0 DSD Audio data 1 FPGA to TX TX
28. 5 Unused 12 LVCMOS25 Unused HA13 LVCMOS25 Unused 14 LVCMOS25 Unused 15 LVCMOS25 Unused 16 LVCMOS25 Unused HA17 CC LVCMOS25 Unused 18 LVCMOS25 Unused 19 LVCMOS25 Unused HA20 N LVCMOS25 Unused 21 LVCMOS25 Unused Rev 1 01 TOKYO ELECTRON DEVICE LIMITED 22 Pin Name Spec Description inreviun HA22 N LVCMOS25 Unused HA23 LVCMOS25 Unused RX 0_P35 LVCMOS33 RX 0 Video data 35 RX to FPGA RX 0_P34 LVCMOS33 RX 0 Video data 34 RX to FPGA RX 0_P33 LVCMOS33 RX 0 Video data 33 RX to FPGA RX 0_P32 LVCMOS33 LX gt gt gt RX 0 Video data 32 RX to FPGA RXHO_P31 LVCMOS33 RX 0 Video data 31 RX to FPGA RX 0_P30 LVCMOS33 RX 0 Video data 30 RX to FPGA RX 0_P29 LVCMOS33 RX 0 Video data 29 RX to FPGA RX 0_P28 LVCMOS33 RX 0 Video data 28 RX to FPGA RX 0_P27 LVCMOS33 RX 0 Video data 27 RX to FPGA RX 0_P26 LVCMOS33 RX 0 Video data 26 RX to FPGA RX 0_P25 LVCMOS33 RX 0 Video data 25 RX to FPGA RX 0_P24 LVCMOS33 RX 0 Video data 24 RX to FPGA RX 0_P23 LVCMOS33 RX 0 Video data 23 RX to FPGA RX 0_P22 LVCMOS33 RX 0 Video data 22 RX to FPGA RX 0_P21
29. 5 3 TB FMCH HDMI2 TX solder side Rev 1 01 TOKYO ELECTRON DEVICE LIMITED 30 inreviun 5 3 Board Specification Figure 5 4 shows the TB FMCH HDMI2 TX board specification External Dimensions W 160mm H 69mm Number of Layers 8 Layers Board Thickness 1 6 mm Material FR 4 FPGA Xilinx s XC6SLX45 3FGG484C FMC Connector Samtec s ASP 134488 01 HDMI Connector Molex s 5002541927 000 000 000 Ore fF SSRIS 5176 m 522 5 ar LUO EE COTTE 2 4 N 3 1 Figure 5 4 TB FMCH HDMI2 TX Board Dimensions Rev 1 01 TOKYO ELECTRON DEVICE LIMITED 31 inreviun 5 4 Power Supply to the Board Figure 5 5 shows the TB FMCH HDMI2 TX power supply structure VCC_12V_IN LT3503EDCB VCC_5V i ADG702 0 001mAx2 0 002mA i ire ae 134mA 0 671W LT3568EDD VOC 12V gt FPGA VCCINT 503mA 349mA oe cool LT3503EDCB VOC 3 3V clc C DERE FPGA VCAUX 68mA FPGA_VCCIO 311mA ADV7511 0 3mA x2 0 6mA I gt _ 1 437mA KC3225A 6mA 18mA 1 442 LTC1326 0 04mA I XCF16 VCCIO 40mA Br Se ERE LT35
30. 7 06 08 GND 424 GND 06 CC 08 LA29 P GND HB11_P GND GND LA29 LA28 P HB11_N HB10_P HB12 P GND LA28 N GND HB10 N HB12 N LA31 P GND HB15 P GND GND LA31 N LA30 P HB15 N HB14 P HB16 P GND LA30 N GND HB14 N HB16 N LA33 P GND HB18 P GND GND LA33 N LA32 P HB18 N HB17 P CC HB20 P GND LA32 N GND HB17 CC 20 GND VIO B M2C GND VADJ Rev 1 01 GND VADJ GND TOKYO ELECTRON DEVICE LIMITED VIO B M2C 36 inreviun 5 7 Other Interfaces The board also provides the following interfaces 5 7 1 JTAG Interface The board has a JTAG connector FPGA configuration JTAG Connector Molex s 87832 1420 Table 5 4 JTAG Connector Signal Name 5 7 2 General Purpose Clock Interface The board has a general purpose clock on FPGA 27MHz crystal oscillator KC5032C027 0000C30EOO Kyocera Rev 1 01 TOKYO ELECTRON DEVICE LIMITED inreviun 5 8 LED Status Table 5 5 shows the onboard LED function Circuit Silk Table 5 5 LED Status Purpose Description DS3 LEDO General purpose LEDO TX0 I2C config state Off CFG done On CFG active DS4 LED1 General purpose LED1 TX0 I2C read back Off Error O
31. 8 Signal FMC to FPGA G8 LA22 LVCMOS25 TX 1_D19 Signal FMC to FPGA G9 LA23 N LVCMOS25 TX 1_D20 Signal FMC to FPGA RO LA24 LVCMOS25 TX 1_D21 Signal FMC to FPGA R1 LA25 LVCMOS25 TX 1_D22 Signal FMC to FPGA R2 LA26 LVCMOS25 TX 1_D23 Signal FMC to FPGA R3 LA27_N LVCMOS25 TX 1_D24 Signal FMC to FPGA R4 LA28 N LVCMOS25 TX 1_D25 Signal FMC to FPGA RS LA29 LVCMOS25 TX 1_D26 Signal FMC to FPGA R6 LA30_N LVCMOS25 TX 1_D27 Signal FMC to FPGA R7 LA31_N LVCMOS25 TX 1_D28 Signal FMC to FPGA R8 LA32_N LVCMOS25 TX 1_D29 Signal FMC to FPGA R9 LA33_N LVCMOS25 Unused CLK2 M2C P LVCMOS25 Unused CLK3 M2C P LVCMOS25 Unused LVCMOS25 Unused HA01 CC LVCMOS25 Unused 2 P LVCMOS25 Unused 525 Unused 04 P LVCMOS25 Unused 05 Rev 1 01 LVCMOS25 Unused TOKYO ELECTRON DEVICE LIMITED 40 Pin Name Spec inreviun Description _ LVCMOS25 Unused 07 P LVCMOS25 Unused 08 LVCMOS25 Unused 09 LVCMOS25 Unused HA10 P LVCMOS25 Unused HA11 LVCMOS25
32. A to FMC B7 LA11_N LVCMOS25 RX 1_P8 signal FPGA to FMC B8 LA12 N LVCMOS25 RX 1_P9 signal FPGA to FMC B9 LA13 N LVCMOS25 RX 1_P10 signal FPGA to FMC 90 LA14 N LVCMOS25 RX 1_P11 signal FPGA to FMC G1 LA15 N LVCMOS25 RX 1_P12 signal FPGA to FMC G2 LA16_N LVCMOS25 RX 1_P13 signal FPGA to FMC G3 LA17_N_CC LVCMOS25 RX 1_P14 signal FPGA to FMC G4 LA18 N CC LVCMOS25 RX 1_P15 signal FPGA to FMC G5 LA19 N LVCMOS25 RX 1_P16 signal FPGA to FMC G6 LA20_N LVCMOS25 RX 1_P17 signal FPGA to FMC G7 LA21 N LVCMOS25 RX 1_P18 signal FPGA to FMC G8 LA22 LVCMOS25 RX 1_P19 signal FPGA to FMC G9 LA23 N LVCMOS25 RX 1_P20 signal FPGA to FMC RO LA24 N LVCMOS25 RX 1_P21 signal FPGA to FMC R1 LA25 LVCMOS25 RX 1_P22 signal FPGA to FMC R2 LA26 LVCMOS25 RX 1_P23 signal FPGA to FMC R3 LA27_N LVCMOS25 RX 1_P24 signal FPGA to FMC R4 LA28_N LVCMOS25 RX 1_P25 signal FPGA to FMC RS LA29 LVCMOS25 RX 1_P26 signal FPGA to FMC R6 LA30_N LVCMOS25 RX 1_P27 signal FPGA to FMC R7 LA31_N LVCMOS25 RX 1_P28 signal FPGA to FMC R8 LA32_N
33. CC 20 GND VIO B M2C GND VADJ Rev 1 01 GND VADJ GND TOKYO ELECTRON DEVICE LIMITED VIO B M2C 17 inreviun 4 7 Other Interfaces The board also has the following interfaces 4 7 1 EEPROM Interface I2C interface used to control the EEPROM from the FPGA EEPROM device 24LCS22A SN Micro Chip 4 7 2 JTAG Interface JTAG connector for FPGA configuration JTAG connector 87832 1420 Molex Table 4 5 JTAG Connector 4 7 3 General Purpose Clock Interface General purpose clock for FPGA 27MHz crystal oscillator KC5032C027 0000C30E00 Kyocera Rev 1 01 TOKYO ELECTRON DEVICE LIMITED inreviun 4 8 LED Status Table 4 6 shows the onboard LEDs Table 4 6 LED Status Circuit Silk Purpose Description DS1 LEDO General purpose LEDO RX0 I2C config state Off CFG done On CFG active DS2 LED1 General purposeLED1 RX0 I2C read back Off Error On No error DS3 LED2 General purposeLED2 RX1 I2C config state Off CFG done On CFG active DS4 LED3 General purposeLED3 RX1 I2C read back Off Error On No error DS5 LED4 General purposeLED4 Unused On DS6 LED5 General purposeLED5 RX0 Input video image clock monitor Flashing Clock Off No clock DS7 LED6 General purposeLED6 RX1 Input video image clock monitor Flashing Clock Off No clock DS8 LED7 General purposeLED7 System reset monitor On Reset
34. CLK T 8 255057 SYSCLKP TX 0 SCL SDA era KC5032027000 ADVIBII KC5032C12 000 3 DDOO GND 5 TX 0 HPD IO DDOD ASP 134488 01 5 41 LED 7 0 ENCH HDMI 1 TX 7 TX D 35 0 TX 1_C TX 0 0 2 P dit DSW 7 0 TX 1_VS HS DE TX 1_DDCA SCL 77 TX 1_CLK 1 SDA D RSW 3 TX 1_DSD 5 0 CECHI m 7 TX 1_DSDCLK JTAG TX 1_SPDIF HEAC 1 FPGA TCK TMS TDI TDO a HPD 1 500254 1927 PROM TX 1_SCLK FPGA D 7 0 TX 1_LRCLK 3 DDOFESOE FPGA DONE TX 1_PD DDOTSDA FPGAJNITB TXiH INT T 8 Doy FPGA PROGB TX 1_SCL SDA FPGA CCLK ADVIBII KC5032C12 000 8 DDOTGND gt XCF16PFSG48C 3 5561 T SHLDI 9 XC6SLX45 3FGG484C Figure 5 1 TB FMCH HDMI2 TX Block Diagram Main Function 1 HDMI Transmit FPGA to ADV7511 FMC Connector Interface FMC HPC to FPGA JTAG Interface General purpose Clock Interface 27MHz General purpose Switch General purpose LED DDC Connection Normal Through 1 01 TOKYO ELECTRON DEVICE LIMITED 29 TB FMCH HDMI2 Hardware User Manual 5 2 External View of the Board Figures 5 2 and 5 3 show the external view of the TB FMCH HDMI2 TX board L tira 1189 TEN FPGA HDMI Transmitter HDMI Connector Figure 5 2 TB FMCH HDMI2 TX component side are mine I OE n T Swans E 3 Em nis LJ I O o O O 9 og KON Figure
35. DCA SDA HA 23 00 P N RX 0 12S 3 0 CECHO CLK 3 0 M2C P N RX 0_SPDIF DETO RX 0_SCLK HPD 0 RX 0_LRCLK RX 0_MCLKOUT 500254 1927 a 8 DDOO SCL RX 0 INT1 CSN 8 DDOO SDA CLK 0 RESETN t 3 SYSCLK P 28 6363MHz 3 5560 RX80 8 LDDOO GND KC5032C27 000 RX 0_DET1 5 RX40 HPD IO LDDO0 ASP 134488 01 2 RX 0_DDCA_SDA F TIT 5 EEPROM 0 RX 0_DDCA SCL F a LED 7 0 241 522 DECH HDMI 1 RX DSW 7 0 RX 1_P 35 0 RX 1_C 0 2 RX 1_VS HS DE RX 1_DDCA SCL RX 1_LLC RX 1_DDCA SDA 2 RSW 3 0 RX 1 12S 3 0 CECH 4 W RX 1_SPDIF DETI RX 1_SCLK HPD 1 RX 1_LRCLK JTAG RX 1_MCLKOUT 500254 1927 FPGA TCK TMS TDI TDO 8 DDOI SOL RX 1_INT1 CSN 1 8 DDGUSDA 87832 1420 FPGA D 7 0 RX 1_RESETN 0 T 8 SV FPGA DONE 28 6363MHz 3 DDCiHPD FPGA INITB ADV7612 8 5561 546 FPGA PROGB RX 1 DETI 5 FPGA COLK RX 1_HPD IO 3 0001 XCF16PFSG48C RX 1_DDCA SDA F 77 EEPROM 1 RX 1_DDCA SCL_F 241 522 XC6SLX45 3FGG484C Figure 4 1 TB FMCH HDMI2 RX Block Diagram Main Functions 1 HDMI receive function ADV7612 gt FPGA FMC connector interface FPGA gt FMC HPC connector EEPROM interface JTAG interface General purpose clock interface 27 2 General purpose switch General purpose LED DDC connection Normal Through 2 3 4 5 6 7 8 1 01 TOKYO ELECTRON DEVICE LIMITED TB FMCH HDMI2 Hardware
36. E LIMITED 39 Pin Name Spec Description inreviun 00 LVCMOS25 TX 1_VSYNC Signal FMC to FPGA LAO1 CC LVCMOS25 TX 1_HSYNC Signal FMC to FPGA 02 LVCMOS25 TX 1_DE Signal FMC to FPGA LA03_N LVCMOS25 TX 1_DO Signal FMC to FPGA BO LAO4 LVCMOS25 TX 1_D1 Signal FMC to FPGA B1 05 LVCMOS25 TX 1_D2 Signal FMC to FPGA B2 LA06 LVCMOS25 TX 1_D3 Signal FMC to FPGA B3 LAO7 LVCMOS25 TX 1_D4 Signal FMC to FPGA B4 LAO8 LVCMOS25 TX 1_D5 Signal FMC to FPGA B5 09 LVCMOS25 TX 1_D6 Signal FMC to FPGA B6 LA10_N LVCMOS25 TX 1_D7 Signal FMC to FPGA B7 LA11_N LVCMOS25 TX 1_D8 Signal FMC to FPGA B8 LA12 N LVCMOS25 TX 1_D9 Signal FMC to FPGA B9 LA13 N LVCMOS25 TX 1_D10 Signal FMC to FPGA G0 LA14 N LVCMOS25 TX 1_D11 Signal FMC to FPGA G1 LA15 N LVCMOS25 TX 1_D12 Signal FMC to FPGA G2 LA16_N LVCMOS25 TX 1_D13 Signal FMC to FPGA G3 LA17_N_CC LVCMOS25 TX 1_D14 Signal FMC to FPGA G4 LA18 N CC LVCMOS25 TX 1_D15 Signal FMC to FPGA G5 LA19 N LVCMOS25 TX 1_D16 Signal FMC to FPGA G6 LA20 N LVCMOS25 TX 1_D17 Signal FMC to FPGA G7 LA21 N LVCMOS25 TX 1_D1
37. ELECTRON DEVICE LIMITED 33 inreviun 5 6 FMC Connector The FMC connector connecting to the High Pin Count uses SAMTEC s ASP 134488 01 Power to the TB FMCH HDMI2 TX is supplied from 12V on the main board An external power source can also be used Table 5 2 shows JP3 jumper setting for power supply Table 5 2 JP3 Jumper Setting Purpose Silk Jumper Setting FMC Connector 12VIN SEL JP3 1 2 short External Power Source 12VIN SEL JP3 2 3 short The following test pin is used to connect an external power Source TP14 12VIN Rev 1 01 TOKYO ELECTRON DEVICE LIMITED 34 inreviun A row Table 5 3 shows the FMC connector pin assignment Table 5 3 FMC Connector Pin Assignment B row C row D row E row GND RES1 GND PG_C2M GND DP1 M2C P GND DPO C2M P GND HA01 P M2C GND DPO C2M N GND HAO1 CC GND DP9 M2C P GND GBTCLKO M2C P GND GND DP9 M2C N GND GBTCLKO M2C N GND DP2 M2C P GND DPO M2C P GND 5 P DP2 M2C N GND DPO M2C N GND 5 GND DP8 M2C P GND LAO1 GND GND DP8 M2C GND LA01_N_CC 09 DP3 M2C P GND LA06_P GND 09 DP3 2 GND 06 05 P GND GND DP7 M2C P GND 05 HA13 P GND DP7 M2C N GND GND HA13 N DP4 M2C
38. FPGA Reset RX 1_ P35 LVCMOS33 RX 1 Video Data 35 RX to FPGA RX 1_P34 LVCMOS33 RX 1 Video Data 34 RX to FPGA RX 1_P33 LVCMOS33 RX 1 Video Data 33 RX to FPGA RX 1_P32 LVCMOS33 RX 1 Video Data 32 RX to FPGA RX 1_P31 LVCMOS33 RX 1 Video Data 31 RX to FPGA RX 1_P30 LVCMOS33 RX 1 Video Data 30 RX to FPGA RX 1_P29 LVCMOS33 RX 1 Video Data 29 RX to FPGA RX 1_P28 LVCMOS33 1_ 27 LVCMOS33 RX 1 Video Data 27 RX to FPGA RX 1_P26 LVCMOS33 RX 1 Video Data 28 RX to FPGA RX 1 Video Data 26 RX to FPGA RX 1_ P25 LVCMOS33 RX 1 Video Data 25 RX to FPGA RX 1_P24 LVCMOS33 RX 1 Video Data 24 RX to FPGA RX 1_P23 LVCMOS33 RX 1 Video Data 23 RX to FPGA RX 1_P22 LVCMOS33 RX 1 Video Data 22 RX to FPGA RX 1_P21 LVCMOS33 RX 1 Video Data 21 RX to FPGA RX 1_P20 LVCMOS33 RX 1 Video Data 20 RX to FPGA RX 1_P19 LVCMOS33 RX 1 Video Data 19 RX to FPGA RX 1_P18 LVCMOS33 RX 1 Video Data 18 RX to FPGA RX 1_P17 LVCMOS33 RX 1 Video Data 17 RX to FPGA RX 1_P16 LVCMOS33 RX 1 Video Data 16 RX to FPGA RX 1_P15 LVCMOS33 RX 1 Video Data 15 RX to FPGA RX 1_P14 Rev 1 01 LVCMOS33 RX 1 Video Data 14 RX to FPGA TOKYO ELECTRON DEVICE LIMITED
39. FPGA to FMC R3 LA27_P LVCMOS25 RX 0_P24 signal FPGA to FMC R4 LA28_P LVCMOS25 RX 0_P25 signal FPGA to FMC RS LA29 P LVCMOS25 RX 0_P26 signal FPGA to FMC R6 LA30_P LVCMOS25 RX 0_P27 signal FPGA to FMC R7 LA31_P LVCMOS25 RX 0_P28 signal FPGA to FMC R8 LA32_P O LVCMOS25 LL LL RX 0_P29 signal FPGA to FMC R9 LA33_P LVCMOS25 Unused LVCMOS25 Unused CLKO_M2C_N CLK1_M2C_N LVCMOS25 TOKYO ELECTRON DEVICE LIMITED 20 Unused Rev 1 01 inreviun Pin Name o Spec Description LAO0 CC LVCMOS25 RX 1_VSYNC signal FPGA to FMC LAO1 N CC LVCMOS25 RX 1_HSYNC signal FPGA to FMC 02 LVCMOS25 RX 1_DE signal FPGA to FMC LA03_N LVCMOS25 RX 1_PO signal FPGA to FMC BO LA04_N LVCMOS25 RX 1_P1 signal FPGA to FMC B1 05 LVCMOS25 RX 1_P2 signal FPGA to FMC B2 LA06 LVCMOS25 RX 1_P3 signal FPGA to FMC B3 LAO7 LVCMOS25 RX 1_P4 signal FPGA to FMC B4 LAO8 LVCMOS25 RX 1_P5 signal FPGA to FMC B5 09 LVCMOS25 RX 1_P6 signal FPGA to FMC B6 LA10_N LVCMOS25 RX 1_P7 signal FPG
40. G_M2C GND VREF A M2C GND VREF B M2C GND CLK1 M2C P PRSNT M2C L CLK3 M2C P GND GND CLK1 M2C N GND CLK3 M2C N GND HAO0 P CC GND CLKO M2C P GND CLK2 M2C P 00 CC GND CLKO GND CLK2 M2C N GND 00 P GND GND GND LA00 CC 02 P 2 P 04 GND 02 GND 2 04 LA03 P GND 07 P GND GND LAO3 N LAO4 P 07 06 8 GND LA04_N GND 06 HAO8_N LA08_P GND HA11_P GND GND LAO8 LA07_P HA11_N HA10_P HA12 P GND 07 GND 12 LA12 GND HA14 P GND GND LA12_N LA11_P HA14_N 17 CC HA15 P GND LA11_N GND HA17_N_CC HA15_N LA16 P GND HA18 P GND GND LA16 LA15 P 18 21 19 GND LA15_N GND HA21_N 19 LA20 P GND HA22 P GND GND LA20 LA19 P 22 HA23 02 GND 19 GND HA23_N 02 LA22 P GND HBO1 P GND GND LA22 LA21 HBO1_N 00 HB04 P GND LA21 N GND HBOO N CC 04 LA25 P GND P GND GND LA25 LA24 P 0
41. OS33 TX 1_D11 LVCMOS33 TX 1 Video data 11 FPGA to TX TX 1_D10 LVCMOS33 TX 1 Video data 12 FPGA to TX TX 1 Video data 10 FPGA to TX TX 1_D9 LVCMOS33 TX 1 Video data 9 FPGA to TX TX 1_D8 LVCMOS33 TX 1 Video data 8 FPGA to TX TX 1_D7 LVCMOS33 TX 1 Video data 7 FPGA to TX TX 1_D6 LVCMOS33 TX 1 Video data 6 FPGA to TX TX 1_D5 LVCMOS33 TX 1 Video data 5 FPGA to TX TX 1_D4 LVCMOS33 TX 1_D3 LVCMOS33 TX 1 Video data 3 FPGA to TX TX 1_D2 LVCMOS33 TX 1 Video data 2 FPGA to TX TX41_D1 LVCMOS33 TX 1 Video data 1 FPGA to TX DO LVCMOS33 TX 1 Video data 0 FPGA to TX TX 1_DCLK LVCMOS33 TX 1 Video data 4 FPGA to TX TX 1 DCLK signal FPGA to TX TX 1_DE LVCMOS33 TX 1 data enable FPGA to TX TX 1_HSYNC LVCMOS33 TX 1 HSYNC FPGA to TX TX 1_VSYNC LVCMOS33 TX 1 VSYNC FPGA to TX TX 1_DSDO LVCMOS33 TX 1 DSD Audio data 0 FPGA to TX TX 1_DSD1 LVCMOS33 TX 1 DSD Audio data 1 FPGA to TX TX 1_DSD2 LVCMOS33 TX 1 DSD Audio data 2 FPGA to TX TX 1_DSD3 LVCMOS33 TX 1 DSD Audio data 3 FPGA to TX TX 1_DSD4 LVCMOS33 TX 1 DSD Audio data 4 FPGA to TX TX 1_DSD5 LVCMOS33 TX 1 DSD Audio data 5 FPGA to TX TX 1_DSD_CLK LVCMOS33 TX 1 DSD clock FPGA to TX
42. P GND LA10 P LAO9 P GND DP4 M2C GND LA10 N 09 HA16 P GND DP6 M2C P GND GND HA16 N GND DP6 M2C N GND LA13 P GND DP5 M2C P GND LA14 P LA13 N HA20 P DP5 M2C GND 14 GND 20 GND GBTCLK1 M2C P GND LA17 P CC GND GND GBTCLK1 M2C GND LA17 CC P DP1 C2M P GND LA18 P CC GND HB03 DP1 C2M N GND LA18 N CC LA23 P GND GND DP2 C9M P GND LA23 N 05 P GND DP2 C9M N GND GND 05 DP2 P GND LA27 P LA26 P GND DP2 2 GND 27 LA26 N 09 GND DP2 8 GND GND 09 GND DP2 C8M GND TCK GND DP3 C2M P GND SCL TDI HB13 P DP3 C2M N GND SDA TDO HB13 N GND DP2 C7M P GND 3 3VAUX GND GND DP2 C7M N GND TMS 19 DP4 P GND GAO TRST HB19_N DP4 2 GND 12V GA1 GND GND DP2_C6M_P GND 3 3V HB21 GND DP2 6 12V GND HB21_N DP5_C2M_P GND GND 3 3V GND DP5 2 GND 3 3V GND VADJ GND Rev 1 01 RESO GND 3 3V TOKYO ELECTRON DEVICE LIMITED GND 35 inreviun F row G row H row J row K row P
43. T3503EDCB VCC 3 3V GE es de I FPGA VCAUX FPGA VOCIO 20mA e ADW7612 3125mA x2 625mA 3 750mA 225 GmA 2 475W LTC1326 0 04mA NC782125 0 02mA x2 0 04mA XCF16 VCCIO 40mA LT3503EDCB VCC_2 5V I FPGA VCCIO 261mA _ ee 1170mA 2 926W LTC3026EMSE VCC 1 8V0 ADV7612 449mA XCFI6VCCINT 10MA LTC3026EMSE VCC 1 8V1 Figure 4 5 TB FMCH HDMI2 RX Power Supply Structure Rev 1 01 TOKYO ELECTRON DEVICE LIMITED inreviun 4 5 HDMI Receiver HDMI Connector uses 5002541927 MOLEX HDMI Receiver uses an ADV7612BSWZ P Analog Devices The following device is used as ESD protection ESD protection RCLAMP0524 and RCLAMP0504 Semtech Table 4 1 shows the HDMI connector pin assignments Table 4 1 HDMI Connector receiving side Name Description TMDS receive data 2 TMDS receive data 2 shield TMDS receive data 2 TMDS receive data 1 TMDS receive data 1 shield TMDS receive data 1 TMDS receive data 0 TMDS receive data 0 shield TMDS receive data 0 TMDS receive clock TMDS receive clock shield TMDS DATA2 TMDS SHLD2 TMDS DATA2 TMDS DATA1 TMDS SHLD1 TMDS DATA1 TMDS DATAO TMDS SHLDO TMDS DATAO TMDS CLK TMDS CLK SHLD TMDS CLK TMDS receive clock CEC CEC signal RESERVED Reserved DDC_SCL DDC seri
44. User Manual 4 2 External View of the Board Figures 4 2 and 4 3 show the external view of the TB FMCH HDMI2 RX board RoHS am TII ME 916161412 FPGA HDMI Receiver HDMI Connector Figure 4 2 External View of TB FMCH HDMI2 RX component side ICT ai m c mme mde LA c FMC HPC Figure 4 3 External View of TB FMCH HDMI2 RX solder side Rev 1 01 TOKYO ELECTRON DEVICE LIMITED 11 inreviun 4 3 Board Specification The following shows TB FMCH HDMI2 RX board specifications External Dimensions W 160mm x H 69mm Number of Layers 8 layers Board Thickness 1 6 mm Material FR 4 FPGA Xilinx s XC6SLX45 3FGG484C FMC Connector Samtec s ASP 134488 01 HDMI Connector Molex s 5002541927 9 55 Fo 999 906 e N arti Ve 5 ues DI 6 uu 2 gt rime mm _ para mm E epu Figure 4 4 TB FMCH HDMI2 RX Board Dimensions Rev 1 01 TOKYO ELECTRON DEVICE LIMITED 12 inreviun 4 4 Supplying Power to the Board Figure 4 5 shows a TB FMCH HDMI2 RX power supply structure 12V IN LT3503EDCB VCC_5V 2ALCS22A 3mAx2 6m Wn cecal 135mA 0 677W LT3568EDD 12V FPGA VOCINT 485mA 562mA l L
45. YO ELECTRON DEVICE LIMITED 54 inreviun m TOKYO ELECTRON DEVICE PLD Solution Division URL http www inrevium jp eng x fpga board E mail psd support teldevice co jp HEAD Guarter Yokohama East Sguare 1 4 Kinko cho Kanagawa ku Yokohama City Kanagawa Japan 221 0056 TEL 81 45 443 4016 FAX 81 45 443 4058 Rev 1 01 TOKYO ELECTRON DEVICE LIMITED 55
46. aaa naa ru e A Mg 20 4 11 FPGA Output Data Phase raranananannnannnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnne 27 4 12 Image inna 28 4121 2DIMag SZ6 e e ee d dra dread 28 412 2 SD Image SIZE unna a tibl det ta e al 28 TB FMGH HDMI2 TX eere ae a a 29 5 1 Block Diagram Y RF Y FAR 29 5 2 External View of the Board ese 30 5 3 Board 31 5 4 Power Supply to the Board i 32 5 5 ADMI Trans 33 5 6 a 34 5 7 Other 37 5 7 1 JTAG Interface dun ERR Ree 37 5 7 2 General Purpose Clock 37 5 8 LED Status cirio 38 5 9 Control Function 38 5 10 39 511 FPGA Input Data Phase ree a sda idee 46 5 12 Image SZO ER 47 5 12 1 29 Image arenaene 47 5 122 3D IMAGESIZE eee ee Loa ela 47 DDC Connection Normal Through 48 6 1 DDC Connection Normal
47. active Off Reset released DS10 HPDO hot plug display On Connected state DS9 HPD1 RX1 hot plug display On Connected state DS11 DONE Config display Config done DS12 12VLED 12V display 12V active 4 9 Control Function Table 4 7 shows the onboard switch function Table 4 7 Switches o Circuit Function S1 1 ADV7612 config ROM selection 51 2 Should set all On 51 3 51 4 51 5 51 6 Unused S1 7 Unused 51 8 ROM selection signal On DSW enable Off RSW enable 52 ADV7612 config ROM selection set to 0 53 FPGA reconfig long push 3 seconds FPGA reset short push AJOIN gt Rev 1 01 TOKYO ELECTRON DEVICE LIMITED inreviun 4 10 FPGA Pin Assignment Table 4 8 shows the FPGA pin assignment In case of 8 bit signal format active bits are assigned to MSB 8 bit of each RGB pin of FMC LSB 2 bit are always 2 b00 8 bit signal format Pin Name Table 4 8 FPGA Pin Assignment Spec Description CLKO M2C P LVCMOS25 RXHO LLC signal FPGA to FMC CLK1_M2C_P LVCMOS25 RX 1_LLC signal FPGA to FMC LA00_P_CC LVCMOS25 RX 0_VSYNC signal FPGA to FMC LAO1 P CC LVCMOS25 HSYNC signal FPGA to FMC LAO2 P LVCMOS25 RXH0 DE signal FPGA to FMC LAO3 P LVCMOS25 PO signal FPGA to FMC BO
48. age size 1280x720p 59 94 60Hz Frame Packing Side by Side Half Top and Bottom 1280x720p 50Hz Frame Packing Side by Side Half Top and Bottom 1280x720p 23 98 24Hz Frame Packing 1280x720p 23 97 30Hz Frame Packing 1920x1080i 59 94 60Hz Frame Packing Side by Side Half 1920x1080i 50Hz Frame Packing Side by Side Half 1920x1080p 23 98 24Hz Frame Packing Side by Side Half Top and Bottom 1920x1080p 29 97 30Hz Frame Packing Top and Bottom 1920x1080p 59 94 60Hz Top and Bottom 1920x1080p 50Hz Top and Bottom Rev 1 01 TOKYO ELECTRON DEVICE LIMITED inreviun 6 DDC Connection Normal Through Two types of DDC connections are supported 6 1 DDC Connection Normal Table 6 1 shows DDC connection jumper setting Normal and Figure 6 1 shows DDC connection structure Table 6 1 DDC Jumper Setting Normal TB FMCH HDMI2 RX TB FMCH HDMI2 TX Jumper JP6 SCLO Setting 1 2 short Normal Jumper Setting JP7 SDAO 1 2 short Normal JP8 DDCO 5V 1 2 short Normal JP7 DDCO 5V 1 2 short Normal JP9 DDCO 1 2 short Normal JP8 DDCO 1 2 short Normal JP10 DDCO SDA 1 2 short Normal JP4 DDCO SDA 1 2 short Normal JP11 DDCO SCL 1 2 short Normal JP5 DDCO SCL 1 2 short Normal JP12 DDCO GND 1 2 short Normal JP6 DDCO GND 1 2 short Normal JP3 SCL1 1 2 short Normal JP4 SDA1 1 2 short N
49. al clock DDC_SDA DDC serial data DDC CEC GND DDC CEC ground DDC 5V 5V power supply HOTPLUG DET Hot plug detection The receiver has an EEPROM 24LCS22A SN Micro Chip This EEPROM is used to store EDID data The SCL signal can be switched by JP6 JP3 and the SDA signal using JP7 JP4 Note At factory default settings EEPROM stores temporary data to enable output of image data from an image output device The ID used in the data is a dummy ID for evaluation purposes So do not use it for actual products Table 4 2 SCL SDA Jumper Setting Purpose Silk Setting DDC connection Normal JP6 SCLO JP7 SDAO JP3 SCL1 JP4 SDA1 JP6 1 2 short JP3 1 2 short JP7 1 2 short JP4 1 2 short Rev 1 01 connection Through DDC JP6 SCLO JP7 SDAO JP3 SCL1 JP4 SDA1 JP6 2 3 short JP3 2 3 short TOKYO ELECTRON DEVICE LIMITED JP7 2 3 short JP4 2 3 short inreviun 4 6 Connector FMC connector High Pin Count connecting to the main board uses ASP 134488 01 Power to the TB FMCH HDMI2 RX is supplied from a 12V on the main board An external power source can also be used Table 4 3 shows JP1 jumper setting for power supply Table 4 3 JP1 Jumper Setting Purpose Silk Setting FMC connector 12VIN SEL JP1 1 2 short External power supply 12VIN SEL JP1 2 3 short To connect an exter
50. ever non chargeable replacement is offered for initial failure if such notification is received within two weeks after delivery of the product The specification of this product is subject to change without prior notice The product is subject to discontinuation without prior notice Rev 1 01 TOKYO ELECTRON DEVICE LIMITED 7 inreviun 1 Related Documents and Board Accessories All documents relating to this board can be downloaded from our website Club X Accessories Interboard spacers and screws Interboard jumper cable 2 Overview The TB FMCH HDMI2 comes either with AnalogDevices s HDMI Receiver ADV7612BSWZ P or HDMI Transmitter ADV7511KSTZ P Collectively there are called TB FMCH HDMI2 This document specifically describes these optional boards in the RX and TX sections respectively Each board has two independent receivers transmitters and is designed for high resolution support It uses Samtec s FMC connector and Molex s HDMI connector for connection with a platform board having High Pin Count connectors This User Manual is refer to Initial ROM files TB FMCH HDMI2 boards need to download following ROM files Table 2 1 ROM data Board name FPGA ROM data TB FMCH HDMI2 RX rx_fpga_top mcs TB FMCH HDMI2 TX tx_fpga_top mcs Rev 1 01 TOKYO ELECTRON DEVICE LIMITED 8 inreviun 3 Feature HDMI Devices Receiver AnalogDevices s ADV7612BSWZ P Transmitter AnalogDevices s ADV7511KSTZ
51. in injury to persons or failure If the product is dropped or damaged do not use it as is Otherwise a fire or electric shock may occur Do not touch the product with a metallic object Otherwise a fire or electric shock may occur Do not place the product in dusty or humid locations or where water may splash Otherwise a fire or electric shock may occur Do not get the product wet or touch it with a wet hand Otherwise the product may break down or it may cause a fire smoking or electric shock oo oooo o Do not touch a connector on the product gold plated portion Otherwise the surface of a connector may be contaminated with sweat or skin oil resulting in contact failure of a connector or it may cause a malfunction fire or electric shock due to static electricity Rev 1 01 TOKYO ELECTRON DEVICE LIMITED 6 inreviun Do not use or place the product in the following locations Humid and dusty locations Q Airless locations such as closet bookshelf Locations which receive oily smoke or steam Locations exposed to direct sunlight Locations close to heating equipment Closed inside of a car where the temperature becomes high Staticky locations Locations close to water or chemicals Otherwise a fire electric shock accident or deformation may occur due to a short circuit or heat generation Q Do not place heavy things on the product
52. inreviun TB FMCH HDMI2 Hardware User Manual Rev 1 01 Rev 1 01 TOKYO ELECTRON DEVICE LIMITED 1 inreviun Revision History Version Date Description Publisher Rev 1 00 2011 02 01 Initial release Yoshioka Rev 1 01 2011 03 29 Modified Figure4 2 4 3 5 2 5 3 Yoshioka Rev 1 01 TOKYO ELECTRON DEVICE LIMITED 2 inreviun 5 6 7 8 Table of Contents Related Documents and Board Accessories nnne 8 NENNE 8 HUE 9 TB FMCH HDMI2 RX 10 4 1 Block T 10 4 2 External View of the Board i 11 4 3 Board Specification 12 4 4 Supplying Power to the Board iaia ra 13 4 5 HDMI 14 4 6 15 4 7 Other 18 4 7 1 EEPROM Interface tete tetro tete mx 18 4 7 2 pM 18 4 7 3 General Purpose Clock Interface 18 4 8 LED Status dida eh d i EN add i 19 4 9 Control sve 19 4 10 FPGA Pir Assignment tt a Pd ea naa gana
53. n No error DS5 LED2 General purpose LED2 TX1 I2C config state Off CFG done On CFG active DS6 LED3 General purpose LED3 TX1 I2C read back Off Error On No error DS7 LED4 General purpose LED4 Unused On DS8 LED5 General purpose LED5 input video image clock monitor Flashing Active clock Off No clock DS9 LED6 General purpose LED6 TX1 input video image clock monitor Flashing Active clock Off No clock DS10 LED7 General purpose LED7 System Reset Monitor On Reset active Off Reset release DS1 HPDO hot plug display On Connected state DS2 HPD1 TX1 hot plug display On Connected state DS11 DONE Config display Config complete DS12 5 9 12VLED Control Function 12V display Table 5 6 shows the onboard switch function o Circuit 12V active Table 5 6 Switch Function Description S1 1 S1 2 8bit Output S1 3 S1 4 ADV7511 config ROM selection 81 1 OFF 51 2 61 3 ON 51 4 ON 10bit Output 51 1 51 2 51 3 OFF 51 4 ON 12bit Output 51 1 ON 51 2 OFF 51 3 51 4 51 5 Unused 51 6 Unused S1 7 Unused MD a RR ws gt 1 8 On Selection of ROM select signal DSW enable Off RSW enable 52 ADV7511 config ROM selection 8bit Output 2 10bit
54. nal power source use the following test pin TP14 12VIN Rev 1 01 TOKYO ELECTRON DEVICE LIMITED inreviun A row Table 4 4 shows the FMC connector pin assignment Table 4 4 FMC Connector Pin Assignment B row C row D row E row GND RES1 GND PG_C2M GND DP1 M2C P GND DPO C2M P GND HA01 P M2C GND DPO C2M N GND HAO1 CC GND DP9 M2C P GND GBTCLKO M2C P GND GND DP9 M2C N GND GBTCLKO M2C N GND DP2 M2C P GND DPO M2C P GND 5 P DP2 M2C N GND DPO M2C N GND 5 GND DP8 M2C P GND LAO1 GND GND DP8 M2C GND LA01_N_CC 09 DP3 M2C P GND LA06_P GND 09 DP3 2 GND 06 05 P GND GND DP7 M2C P GND 05 HA13 P GND DP7 M2C N GND GND HA13 N DP4 M2C P GND LA10 P LAO9 P GND DP4 M2C GND LA10 N 09 HA16 P GND DP6 M2C P GND GND HA16 N GND DP6 M2C N GND LA13 P GND DP5 M2C P GND LA14 P LA13 N HA20 P DP5 M2C GND 14 GND 20 GND GBTCLK1 M2C P GND LA17 P CC GND GND GBTCLK1 M2C GND LA17 CC P DP1 C2M P GND LA18 P CC GND HB03 DP1 C2M N GND LA18 N CC LA23 P GND
55. ormal JP13 DDC1 5V 1 2 short Normal JP12 DDC1 5 1 2 short Normal JP14 DDC1 1 2 short Normal JP13 DDC1 HPD 1 2 short Normal JP15 DDC1 SDA 1 2 short Normal JP9 DDC1 SDA 1 2 short Normal JP16 DDC1 SCL 1 2 short Normal JP10 DDC1 SCL 1 2 short Normal JP17 DDC1 GND 1 2 short Normal TB FMCH HDMI2 RX JP11 DDC1_GND DDC_SCL SG DDC SDA DDC 5V DDC GND HDMI HOTPLUG DET DDC SOL DDC SCA EEPROM DET DEC DDC GND AE DDC GND DET RE 1 2 short Normal TB FMCH HDMI2 TX DDC SCL DDC SDA DDC 5V MONITOR DDC GND HDMI HOTPLUG DET DDC SCL Figure 6 1 DDC Connection Structure Normal TOKYO ELECTRON DEVICE LIMITED Rev 1 01 inreviun 6 2 Table 6 2 shows DDC connection jumper setting Through and Figure 6 2 shows DDC connection structure Through DDC Connection Through Table 6
56. ta 33 FPGA to TX TX 1 Video data 32 FPGA to TX TX 1_D31 LVCMOS33 TX 1 Video data 31 FPGA to TX TX 1_D30 LVCMOS33 TX 1 Video data 30 FPGA to TX TX 1_D29 LVCMOS33 TX 1 Video data 29 FPGA to TX TX 1_D28 LVCMOS33 TX 1 Video data 28 FPGA to TX TX 1_D27 LVCMOS33 TX 1 Video data 27 FPGA to TX TX 1_D26 LVCMOS33 TX 1 Video data 26 FPGA to TX TX 1_D25 LVCMOS33 TX 1_D24 LVCMOS33 TX 1 Video data 24 FPGA to TX TX 1_D23 LVCMOS33 TX 1 Video data 25 FPGA to TX TX 1 Video data 23 FPGA to TX TX 1_D22 LVCMOS33 TX 1 Video data 22 FPGA to TX TX 1_D21 LVCMOS33 TX 1 Video data 21 FPGA to TX TX 1_D20 LVCMOS33 TX 1 Video data 20 FPGA to TX TX 1_D19 LVCMOS33 TX 1 Video data 19 FPGA to TX TX 1_D18 LVCMOS33 TX 1 Video data 18 FPGA to TX TX 1_D17 LVCMOS33 TX 1 Video data 17 FPGA to TX TX 1_D16 Rev 1 01 LVCMOS33 TX 1 Video data 16 FPGA to TX TOKYO ELECTRON DEVICE LIMITED 43 Pin Name Spec Description inreviun TX 1_D15 LVCMOS33 TX 1 Video data 15 FPGA to TX TX 1_D14 LVCMOS33 TX 1 Video data 14 FPGA to TX TX 1_D13 LVCMOS33 TX 1 Video data 13 FPGA to TX TX 1_D12 LVCM
57. tch 5 DSW6 LVCMOS33 DIP switch 6 DSW7 LVCMOS33 DIP switch 7 LEDO LVCMOS33 LEDO LED1 LVCMOS33 LED1 LED2 LVCMOS33 LED2 LED3 LVCMOS33 LED3 LED4 LVCMOS33 LED4 LED5 LVCMOS33 LED5 LED6 LVCMOS33 LED6 LED7 Rev 1 01 LVCMOS33 LED7 TOKYO ELECTRON DEVICE LIMITED inreviun 5 11 FPGA Input Data Phase Figure 5 6 shows the input data phase of the FPGA on the TB FMCH HDMI2 TX connector to FPGA data is captured by the FPGA at the rising edge of a video clock Data from the main board is transferred at the falling edge of a video clock gt HDMITX VSYNC HSYNC DE DATA ES SE SS ae tl Output data are synchronous with down edge of HDMITX_CLK Figure 5 6 FPGA Input Data Timing Rev 1 01 TOKYO ELECTRON DEVICE LIMITED 46 inreviun 5 12 Image Size 5 12 1 2D Image Size TB FMCH HDMI2 TX supports HDMI1 4 compliant primary format and part of secondary format 1080p 60Hz Supported image size 640x480p 59 94 60Hz 1280x720p 59 94 60Hz 1920x1080i 59 94 60Hz 720x480p 59 94 60Hz 720 1440 x480i 59 94 60Hz 1280x720 50Hz 1920x1080i 50Hz 720x576p 50Hz 720 1440 x576i amp 50Hz 1920x1080p 59 94 60Hz 1920x1080p 50Hz 5 12 2 3D Image Size TB FMCH HDMI2 RX supports HDMI1 4 compliant primary format Supported im
58. ting 49 Table 7 1 TB FMCH HDMI2 RX Default Settings JP 50 Table 7 2 TB FMCH HDMI2 RX Default Setting DSW RSW 51 Table 7 3 TB FMCH2 TX Default Settings JP 2 52 Table 7 4 TB FMCH HDMI2 TX Default Switch Settings 53 Table 8 1 Setting 54 Rev 1 01 TOKYO ELECTRON DEVICE LIMITED 4 inreviun Introduction Thank you for purchasing the TB FMCH HDMI2 RX TB FMCH HDMI2 TX boards Before using the product be sure to carefully read this user manual and fully understand how to correctly use the product First read through this manual then always keep it handy SAFETY PRECAUTIONS Observe the precautions listed below to prevent injuries to you or other personnel or damage to property Before using the product read these safety precautions carefully to assure correct use e These precautions contain serious safety instructions that must be observed After reading through this manual be sure to always keep it handy The following conventions are used to indicate the possibility of injury damage and classify precautions if the product is handled incorrectly N Danger Indicates the high possibility of serious injury or death if the product is handled incorrectly N Warning Indicates the possibility of serious injury or death if the product is
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