EVBUM2073 - NB4N441MNGEVB Evaluation Board User's Manual
Contents
1. 20 LOCKED Output _____ CMOS TTL PLL Locked Indicator 21 OE Input H CMOS TTL Synchronous Output Enable Active HIGH The Enable is synchronous to the p output clock to eliminate the possibility of runt pulses on the CLKOUT outputs a EN DfeensrGekoupa 7 p cour Output eck Oui m vec Susy _ Board Pins Input Clock An SMA connector J1 board trace to Serial Pins NB4N441 SCLOCK SDATA and CLK XTAL1 device pin contains a gap placed on the board SLOAD pins have board traces connected to SMA trace at the crystal pin J5 This board trace and connector connectors J10 J9 and J7 for external control There are no are open and not connected to the crystal pin and has no 50 Q termination resistors on these nodes If signal sources impedance affect on the crystal pin A short must bridge this requiring output termination are needed to drive SCLOCK gap to connect the INPUT CLOCK SMA to the device SDATA and SLOAD a 50 2 resistor can be added from the CLK XTAL1 pin A 50 Q termination resistor may be added board trace at the SMA conductor to SMA ground from the board trace from CLK to SMAGND at the SMA Output Enable The Output Enable function is carried connector or install a 50 Q resistor in place of C6 out manually with the switch SW1 or externally via SMA SWA 6 and 7 are the M N and P SELECT2. gt 22 5 C5 XTAL2 gt 4 88 01 XTALI CLK 4 441 GND NC10 C6 VCC g VCC 0 mazg These components as close to Q 8 5 E clock driver as possible 9 Zz D 59 E o Y2 27MHz XTAL This crystal is an HC49 leaded crystal that plugs into the two pin headers next to the clock driver 4 Figure 4 Input Clock and Crystal 81 XTAL1 CLK GND U1 NB4N441 SLOAD SEL2 SLOAD SEL2 SDATA SEL1 SCLK SELO SDATA SEL1 SCLOCK SELO Note SELx Signals Have In ternal 75k Pulldowns 2 4 SLD S2 2 4 SDAT S1 2 4 SCLK SO Figure 5 SDI Inputs http onsemi com 8 NB4N441MNGEVB U1 OE NB4N441 LOCKED GND SLOAD SEL2 SDATA SEL1 SCLK SEL1 2 GND 3 3V_LED Note OE Signal Has an Internal 37 5k Pullup R6 200Q 1 16W OUTPUT ENABLED D3 LED_GRN N e Q2 BSS138W a CLKOUT_OE OUTPUT ENABLE SW SPDT OUTPUT DISABLE Figure 6 Output Enable http onsemi com 9 NB4N441MNGEVB 22 CLKOUT_L CLKOUT U1 NB4N441 OE 20 PLLLOCKED LOCKED LOCKED DEN GND om e lt o0 t x a oddo 3 3V_LED 3 3V_LED 17 Q8 R2 Place LED s Near 2002 LOCKED Connector 1 16W D1 D2 PLL Not LOCKED PLL LED_GRN LED_RED LOCKED N a e Q1 BSS138W a Figure 7 Output LOCKED Not LOCKED Inputs to
3. Digikey 5 C23 EMI LTST C190GKT LED GRN E D3 D1 160 1183 1 ND Digikey EJ LTST_C190EKT LED_ORN D4 D5 D6 D7 160 1182 1 ND Digikey 4 mE LTST C190AKT D8 D9 D10 D11 D13 160 1180 1 ND Digikey A 11 AAA D14 D16 D17 D19 D20 D21 LTST_C190GKT LED_GRN eon 015 018 160 1183 1 ND Digikey s LTST C190YKT LED YLW Lite On D26 D27 D28 160 1184 1 ND Digikey 15 142 0701 801 SMA Johnson J1 42 44 J7 J8 J9 J10 J502 ND Digikey Components J11 16 0673 0 15 01 30 02 10 0673 Mill Max 43 5 2 0 142 0701 801 Johnson J502 ND Digikey Components 142 0701 801 2 J502 ND Digikey Components 571 0500 RED BANANA JACK eltron 150 039 Farnell Newark 571 0700 BANANA JACK eltron 571 0100 BLK BANANA JACK 10 89 1081 CDRH74 102MC 382811 5 0 1 Shunt EN 382811 5 0 1 Shunt AMP Tyco 28 1895 314 40 Hex Standoff Keystone 3 4 x1 4 PMS 440 0025 PH 50 000 00306 24 LD QFN GCI Flex M amp M Specialties Socket 150 043 150 040 WM6808 ND E 308 1197 1 ND M1 M2 M3 M4 A26229 ND A26229 ND M6 M7 M8 M9 1895K ND M10 M11 M12 M13 H342 ND 50 000 00306 Q1 Q2 Q3 Q4 Q5 Q6 BSS138WDICT ND BSS138WDICT ND R1 R2 R6 R12 R13 P220GCT ND R14 R15 http onsemi com 15 Farnell Newark Farnell Newark Digikey Digikey Digikey Digikey Digikey Digikey Digikey Digikey Mouser Digikey Item Mfg Part ERJ 3GEYJ753V NB4N441MNGEVB Description Manufacturer Reference Vendor Part Vendor R7
4. LED PLD indicates power is applied to the PLD LED on 3 Insure J3 external CLOCK line from J1 is open not LOADED DRIVEN or shorted 4 Insure SW5 LEFT CUSTOM 441 RIGHT STANDARD 442 select is set to the LEFT bypassing SW2 SEL 3 0 Note LED will light for CUSTOM FREQUENCIES 5 Set SW4 SW6 and SW7 rocker switches to desired P M and N programming values UP 0 LOGIC LOW LED indicator OFF DOWN 1 LOGIC HIGH LED indicator ON 6 Load program values by depressing momentary switch SWS or send a pulse signal 125 ns min through J13 SMA connector when installed with OFFSET LVCMOS LVTTL LEVELS of 2 0 V HIGH and 1 3 V LOW B External SDI 1 See datasheet DC Table AC Table as well as Figures 5 and 6 2 To use the SDI serial data input port generate and input SCLOCK SDATA and SLOAD signals with OFFSET LVCMOS LVTTL LEVELS of 2 0 V HIGH and 1 3 V LOW The SCLOCK signal will sample the information presented on SDATA line Values are loaded and indexed into a 18 bit shift register The register shifts once per rising edge of the SCLOCK input The serial input SDATA bits must each meet setup and http onsemi com 3 NB4N441MNGEVB hold timing to the respective SCLOCK rising edge as specified in the AC Characteristics section of the datasheet document The MOST Significant Bit MSB P4 is indexed in first followed by P3 P2 P1 N2 N1 NO M9 through the LEAST Significant Bit LSB MO in
5. PLD R7 75k gt SEL3 4 Inputs to Clock Driver or Driven by External gt SEL2 4 Source Through SMA Connectors 3 3V_LED gt SELT 4 cm 3 3 LED 2009 PBSSI88W ________ _ _ 0 b 6l oc Q6 BSS138W IA SS A Q6 BSS138W A J18 O R20 0 gt 53 1 4 PS e EA 0 SDAT S1 11 4 SCLK SO 1 4 Figure 8 Inputs to PLD http onsemi com 10 NB4N441MNGEVB 3 3V_LED 3 3V_LED A 5 a fe ue MEE S oz NE Lc e g gt eee lt 85 E uer LEM IL cR MEM x EXIGERE TP LEX LCD LU o 4 Dg LO EZZ mw A SS Ss Figure 9 Switches and LED http onsemi com 11 NB4N441MNGEVB 3 3V_LED gt PLD_OEn 4 3 3V_LED DNI SW SPST On Board Serial Enabled Use Custom Frequencies 3 3V_LED 1 D15 LED_GRN x LED GRN Q7 BSS138W 1 Use Standard Protocols SW SPST Figure 10 Output Enable http onsemi com 12 NB4N441MNGEVB 3 3V_LED nad 6 8 5 SNC 2 SEL3 7 mom e 53 1 2 2 SEL2 5 810 92 5 SDAT SLD S2 1 2 2 SEL1 SDAT S1 7 0 SDAT S1 1 2 2 SELO
6. R8 R9 R10 P75KGCT ND Digikey Qty ERJ 3GEYOROOV Panasonic R20 R21 R22 R23 PO OGCT ND Digikey ERJ 3GEYJ154V Panasonic R25 R26 R27 R28 R2 P150KGCT ND Digikey 9 R30 R31 R32 R33 R 34 R35 R36 R37 R38 R39 R40 R41 R42 R56 41 ERJ 3GEYJ221V 2002 Panasonic R43 R44 R46 R47 R4 9 R50 R51 R52 R53 R 54 R55 R57 R58 R59 R60 R61 R62 R63 R64 R65 P220GCT ND Digikey 20 42 ERJ 3GEYJ102V Panasonic R70 R71 R72 R74 P1 0KGCT ND Digikey 4 ERJ 3GEYJ472V P4 7KGCT ND Digikey EN CC mem GN E EN E qm CG _ MON AC foo sm CE oem E e e f oo fom o foe f e o E AR e wm es fo CC quem E we CN CN CGE uem E A Te CUIR NUM 5 s mme CN e EA Ls E m el BOE Panasonic 300 6143 1 ND Digikey 300 6050 ND Digikey 300 7232 1 ND Digikey 58 HC49US27 000MABJ 27MHz XTAL CSX750FBC4 000000MTR 4MHz Oscillator http onsemi com 16 L1 L2 L3 L4 NB4N441MNGEVB LAMINATION STACK Signal SMAGND Vcc DUTGND DUTGND and Signal LAMINATION DIAGRAM Layer Layer Copper Dielectric Layer Trace Number Name Thickness Thickness Material Width 1 TOP 1 2 OZ MAGND 1 OZ 2 S LLLLLLLLLLLLLLLL LLL PNS 22 PETER 22 lt lt MS 72 TGND 1 2 OZ FINISHED PCB THICKNESS TO BE 0 64 0 003 ASSEMBLY NOTES Notes Unles
7. Semiconductor Website www onsemi com Literature Distribution Center for ON Semiconductor USA Canada P O Box 5163 Denver Colorado 80217 USA Europe Middle East and Africa Technical Support Order Literature http www onsemi com orderlit Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Phone 421 33 790 2910 VP Fax 303 675 2176 800 344 3867 Toll Free USA Canada Japan Customer Focus Center For additional information please contact your local Email orderlit onsemi com Phone 81 3 5817 1050 Sales Representative EVBUM2073 D
8. gt SCLK SO e G scLk so 1 2 8 STDn 3 3V_LED B 8 P3 12 43 Spare2 66 DNI 8 2 gt 18 na AS 8 P1 gt 19 Spare1 R67 DNI 8 PO R 20 3 21 3 8 R68 R69 8 DNI DNI 8 Me B M5 4 3 3 gt B M2 n V V 3 M1 y 3 3V_LED 3 EPM7032AETC44 4 35 R72 3 3V_LED 7 B PLD_TCK TCK 26 9 8 PLD_OEn 381 PLD_OEn 32PLD TDO TY L A 1 El 3 3V_LED 7 TMS Jj ds seb RCFGn E o J13 RCFG EXT 1 5 8 o9 106 RECONFIGURE 6 2 39 R74 SMA 3 e tk JTAG HEADER SW MOM PB SPDT 3 3V_LED 3 3 LED V Y 113 4 VDD 2 GND OUT 3 CLK4MHz 40 V 4MHz Oscillator Figure 11 PLD http onsemi com 13 NB4N441MNGEVB 3 3V 3 3V Caps near power connector J15 2 Place resistor under inductor 43 3V L1 so only one be installed 3 3PLL 1 Red Banana Jack J16 2 C10 cu SMAGND 22uF O 01uF7T O 1pF 2 2 biz YLW Banana Jack ae ES 1 8W J17 2 Caps near Clock Driver DUTGND 3 3V Place one cap by each Clock Pin 3 1 Driver VCC or GND Pin BLK Banana Jack 3 3V LED M6 3444 40 Hex Standoff 3 4 x1 4 C15 C16 C17 C18 M7 0 01uF 0 01uF 0 01uF 0 01uF 4 40 Hex Standoff 3 4 x1 4 M8 C24 25 C26 C27 4 40 Hex Standoff 3 4 x1 0 01uF M9 3144 40 Hex Standoff 3 4 x1 4 M10 34 40 Phillips Panhead 1 4 Zn Plated
9. 0 005 in 596 per linear inch Front to back registration to be within 0 003 in True position tolerance shall be determined by a minimum anular ring of 0 005 in Plated holes shall not be rough or irregular so as to hinder proper solder wicking Soldermask Green LPI BO Apply Legend SILKSCREEN to both sides using a nonconductive white Epoxy based ink per artwork No board shop logo on board Each PCB shall be serialized in legend in the area shown as follow 0005 1 1 Sequential Number assigned per panel Panel Number assigned per log Year and Week Testing 15 Final Electrical Test shall be preformed provided 356 netlist The PCB shall have a verification stamp Connectivity to be verified against IPC format net list A TDR report for each layer shall be provided by vendor at time of shipment NB4N441MNGEVB ON Semiconductor and Q are registered trademarks of Semiconductor Components Industries LLC SCILLC SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provide
10. DIP switches connector J11 and observing the OUTPUT CLOCK amp JP1 is an LED power supply jumper provided to disable the OUTPUT CLOCK CLKOUT pins LED s and their current Disabling the LEDs will allow PLL LOCKED There are two convenient PLL indicator measuring only the device power supply current LEDs green for when the device is PLL LOCKED and red Output CLOCK and Output CLOCK The outputs for PLL not LOCKED have equal length board traces with SMA connectors J2 amp LED PLD Power The LED and PLD power can be J4 Use matched cables to connect the outputs to an disabled by leaving JP1 open or removing shunt from JP1 oscilloscope or frequency counter Alternative connection pads are supplied for installation of a Thevenin termination scheme http onsemi com 6 NB4N441MNGEVB APPENDIX 2 SCHEMATICS 3 3PLL 3 3V 3 3V R76 R79 DNI DNI SG2 SG3 Note No Stubs Between o Solder Gap Solder Gap CLKOUT and CLKOUT_L and amp Solder Gaps 9 28 CLKOUT OUTPUT CLOCK 22 CLKOUT_L i CLKOUT OUTPUT CLOCK NB4N441 2 OE reer 564 505 LOCKED Solder Gap Solder Gap uds Note CLKOUT and 939 0 GND CLKOUT_L Traces Should be nog 5 E x Equal Length 9209 R77 R78 DNI DNI 3 Figure 3 Outputs http onsemi com 7 NB4N441MNGEVB 3 3V No Stub Between Crystal and Solder Gap 1 CLK_IN 561 INPUT CLOCK SMA Solder Gap m pe
11. JP1 LED PLD indicates power is applied to the PLD LED on 3 Insure J3 external CLOCK line from J1 is open not LOADED DRIVEN or shorted 4 Insure SW5 LEFT CUSTOM 441 RIGHT STANDARD 442 select is set to the LEFT bypassing SW2 SEL 3 0 Note LED will light for CUSTOM FREQUENCIES 5 Set SW4 SW6 and SW7 rocker switches to desired P M and N programming values UP 0 LOGIC LOW LED indicator OFF DOWN 1 LOGIC HIGH LED indicator ON 6 Load program values by depressing momentary switch SWS or send a pulse signal through J13 SMA connector when installed with standard LVTTL LVCMOS levels B External SDI 1 See datasheet DC Table AC Table as well as Figures 5 and 6 2 To use the SDI serial data input port generate and input SCLOCK SDATA and SLOAD signals with standard LVTTL LVCMOS levels The SCLOCK signal will sample the information presented on SDATA line Values are loaded and indexed into a 18 bit shift register The register shifts once per rising edge of the SCLOCK input The serial input SDATA bits must each meet setup and hold http onsemi com 4 NB4N441MNGEVB timing to the respective SCLOCK rising edge as specified in the AC Characteristics section of the datasheet document The MOST Significant Bit MSB P4 is indexed in first followed by P3 P2 P1 N2 N1 NO M9 through the LEAST Significant Bit LSB MO indexed in last A Pulse on the SLOAD pin after the SHIFT register is fu
12. Machine Screw 3 3V 3 3V LED M5 TP1 TP2 TP4 5 JP1 0 1 Shunt 84 40 Phillips Panhead 1 4 1 T Jumper allows user to isolate T Zn P C19 C20 C21 C22 C23 0 1uF Place one cap by each PLD and OSC VCC Pin ated Machine Screw Header2x1 clock driver for power estimation 00000000 M12 4 4 40 Phillips Panhead 1 4 X uet Zn Plated Machine Screw Mounding Mounding Mounding Mounding Three Power Planes M13 Hole Hole Hole Hole T Voc 43 3V 4 40 Phillips Panhead 1 4 SMAGND 1 3V Zn Plated Machine Screw V DUTGND GND PCB Notes 1 Use GETEK Board Material 2 Board Impedance 50 Q Figure 12 Power and Hardware http onsemi com 14 NB4N441MNGEVB APPENDIX 3 BILL OF MATERIALS LAMINATION STACKUP AND ASSEMBLY NOTES LED_AMB D12 LED_ORN 160 1182 1 ND E lt 2 Sumida yco 4 40 Phillips Panhead 1 4 Zn plated Machine Screw Building Fasteners Mfg Part Description Manufacturer Reference Vendor Part Vendor 1 C1 C2 R3 C3 R4 C4 R 19 5 C5 C6 R45 R48 R66 R67 R68 R69 R76 R77 R78 R79 T494D226K016AS 22uF 07 011 012 399 1782 1 ND Digikey HEN C0603C103K5RACTU 0 01uF Kemet C8 C10 013 C15 C16 399 1091 1 ND Digikey C17 C18 C24 C25 C26 C27 C28 HO ECJ 1VB1C104K 0 1uF 9 14 PCC1762CT ND Digikey EA 5 ECJ 1VB1C104K 0 1uF Panasonic C19 C20 C21 C22 PCC1762CT ND
13. NB4N441MNGEVB NB4N441MNGEVB Evaluation Board User s Manual Device Name NB4N441MN Description The NB4N441MNG is a precision clock PLL based synthesizer which generates select differential LVPECL clock output frequencies from 12 5 MHz to 425 MHz A Serial Peripheral Interface SPI is used to configure the device to produce output frequencies from a single 27 MHz crystal input reference by programming three internal registers P pre scale PLL Feedback Divider and Output Divider using a three line LVTTL LVCMOS Serial Data Interface SDI consisting of a SERIAL DATA SDATA input a SERIAL CLOCK SCLOCK input and a SERIAL LOAD SLOAD The NB4N441MNGEVB Evaluation board is designed to provide a flexible and convenient platform to quickly program evaluate and verify the performance and operation of the NB4N441MNG device under test With the device removed this NB4N441MNGEVB Evaluation board is designed accept a 24 LD QFN GCI socket M amp M Specialties Inc 1 800 892 8760 www mmspec com Dwg No 50 000 00306 to permit use as an insertion test fixture FRONT ON Semiconductor hitp onsemi com EVAL BOARD USER S MANUAL Board Features e On board 27 MHz crystal source or input external clock source SMA e On board serial data loader with 16 bit DIP switches or externally serial program through SMA connectors e PLL In Lock LED status indicator e 3 3 split power supply operation banana j
14. ack and anvil supply connectors for SMAGND and DUTGND e LVPECL differential output signals via SMA connectors with provision for termination resistors Contents Description Board Features Board Layout Map Test and Measurement Setup Procedures Appendix 1 Device Information Appendix 2 Schematics Appendix 3 Bill Of Materials Lamination Stackup BACK Figure 1 NB4N441MNGEVB Evaluation Board Semiconductor Components Industries LLC 2012 February 2012 Rev 1 Publication Order Number EVBUM2073 D NB4N441MNGEVB BOARD LAYOUT MAP SW1 OUTPUT EN SMAGND CC DUTGND DEVICEUN D3 OUTPUT THEVENIN PARALLEL DER TEST EN LED RESISTOR PADS Unpopulated J12 JUMPERS J2CLK out out J1 INPUT CLK J11 OUTPUT EN 1 8 PLL LOCKED J7 SLOAD min E PLL LOCKED LED J9 SDATA ANH HHH PLL not LOCKED LED J10 SCLOCK LED for LEDS and PLD PWR j SW5 switch R P 4 0 M 9 0 2 0 EL 3 0 NOT ED US SW8 RECONFIG LED for Standard Protocols LED for CUSTOM FREQUENCIES URE FRONT SMAGND 27 MHz DUTGND VCC Crystal Through Hole of INPUT CLOCK trace J5 BACK Figure 2 Board Layout Map http onsemi com 2 NB4N441MNGEVB TEST AND MEASUREMENT SETUP AND PROCEDURE Step 1 Equipment or equivalent 1 2 3 4 5 Agilent Signal Generator 33250 for CLK input Tektronix TDS8000 Oscilloscop
15. d in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT American Technical Support 800 282 9855 Toll Free ON
16. dexed in last A Pulse on the SLOAD pin after the SHIFT register is fully indexed 18 clocks will load and latch the data values for the internal P M and N registers The SLOAD pulse Low to HIGH rising edge transition transfers the data from the SHIFT register to the LATCH register The SLOAD Pulse HIGH to LOW transition will lock the new data values into the LATCH register 5 Output Enable ON Switch SW1 DOWN or externally HIGH through J11 offset LVCMOS LVTTL of 2 0V HIGH and 1 3 V LOW to enable the output after setup LED D3 indicator will be ON to indicate an enabled output real time high impedance input scope will not require an external trigger connection 5 XTAL CLK Input Determine if the onboard crystal or an external signal reference will be used Onboard Crystal signal source is default ready for use NOTE If an external clock reference is used then dismount crystal and connect a clock signal 10 MHz 50 MHz with standard LVTTL LVCMOS into INPUT CLOCK 31 Also short from the bottom side through hole trace of INPUT CLOCK to J5 not J3 Do not drive XTAL2 Termination of the signal generator may be needed with 50 Q to SMA ground Program SDI The P M and N internal registers may be programmed by A the onboard PLD or B by using the three line LVTTL LVCMOS Serial Data Interface SDI consisting of a SERIAL DATA SDATA input a SERIAL CLOCK SCLOCK input and a SERIAL LOAD SLOAD as fo
17. e or Frequency Counter Agilent 6624A DC Power Supply Digital Voltmeter Matched high speed cables with SMA connectors Step 2 Lab Setup Procedure for Split Supplies into LOW impedance 50 Q equipment or probes 1 ER 97 109 Output Enable OFF Switch SW1 UP or externally LOW through J11 offset LVCMOS LVTTL of 2 0 V HIGH and 1 3 V LOW to disable the output during setup LED D3 indicator will be off to indicate disabled output Supplies Connect a split power supply to the evaluation board for 3 3 V operation as follows RED banana jack or clip anvil at 2 0 SMAGND YELLOW banana jack or clip anvil at 0 V DUTGND BLACK banana jack or clip anvil 1 3 V Output Connect LVPECL Output CLOCK and Output CLOCK outputs to the oscilloscope with matched cables NOTE The readings of the output voltage levels will be offset by 1 3 V from standard LVPECL levels With this split supply the device outputs will be parallel terminated by the oscilloscope or frequency counter input module s internal 50 to GND impedance See the data sheet Figure 10 where SMAGND 20V 20 V OSCILLOSCOPE GND An alternative thevenin parallel termination scheme can been accommodated by using the unpopulated Resistor Pads R76 R77 R78 and R79 provided on the OUTPUT CLOCK and OUTPUT CLOCK lines near the SMA connectors See AND8020 for additional details Do not use both thevenin parallel term
18. ination scheme and LOW IMPEDANCE 50 termination schemes on the same output at the same time double termination Trigger Ensure the oscilloscope trigger input is properly setup and adjusted and has a 50 Q termination to ground The board does not provide 50 Q source termination resistors Two possible oscilloscope trigger methods might be connector from CLKOUT to the trigger of the scope Use CLKOUT directly to the trigger XTAL CLK Input Determine if the onboard crystal or an external signal reference will be used Onboard Crystal signal source 27 MHz is default ready for use NOTE If an external clock reference is used then dismount the crystal and connect a clock signal 10 MHz 50 MHz 3 3 Vpp amplitude with LEVELS OFFSET 1 3 V as 42 0 V HIGH and 1 3 V LOW into CLK XTAL1 J1 Also short from the bottom side through hole trace of INPUT CLOCK to J5 not J3 Do not drive XTAL2 Termination of the signal generator may be needed with 50 Q to SMA ground 4 Program SDI The P M and N internal registers may be programmed by A the onboard PLD or B by using the three line 3 3 Vpp amplitude offset LVTTL LVCMOS Serial Data Interface SDI consisting of a SERIAL DATA SDATA input a SERIAL CLOCK SCLOCK input and a SERIAL LOAD SLOAD as follows A Onboard PLD 1 Insure all 4 of the J12 441 CONFIG jumpers are all installed connecting the PLD output to the Device 2 Insure JP1
19. llows A Onboard PLD ALTERNATE STEP 2 LAB SET UP PROCEDURE FOR 1 Insure all 4 of the J12 441 CONFIG jumpers SINGLE SUPPLY INTO HIGH IMPEDANCE PROBES are all installed connecting the PLD output to 1 Output Enable OFF Switch SW1 UP or the Device externally LOW through J11 standard LVCMOS LVTTL of 2 0V HIGH and 0 8 V LOW to disable the output during setup LED D3 indicator will be off to indicate disabled output Supplies Connect a single power supply to the evaluation board for 3 3 V operation as follows VCC RED banana jack or clip anvil at 3 3 SMAGND YELLOW banana jack or clip anvil at 0 V DUTGND BLACK banana jack or clip anvil OV Output Connect LVPECL OUTPUT CLOCK and OUTPUT CLOCK outputs to the oscilloscope with matched cables The device outputs will require proper termination A thevenin parallel termination scheme can be accomplished by populating Resistor Pads R76 R77 R78 and R79 provided on the OUTPUT CLOCK and OUTPUT CLOCK lines near the SMA connectors Install 127 Ohm resistors R77 at SG4 and R78 at 565 Install 83 Ohm resistors R76 at SG2 and R79 at SG2 See AND8020 for additional details Use HIGH IMPEDANCE FET Probes or equipment only Do not use LOW IMPEDANCE 50 equipment or probes when using thevenin parallel termination or the signal will be double terminated Trigger Ensure the oscilloscope trigger input is setup and adjusted properly A self triggered 2 Insure
20. lly indexed 18 clocks will load and latch the data values for the internal P M and N registers The SLOAD pulse Low to HIGH rising edge transition transfers the data from the SHIFT register to the LATCH register The SLOAD Pulse HIGH to LOW transition will lock the new data values into the LATCH register 7 Output Enable ON Switch SW1 DOWN or externally HIGH through J11 to enable the output after setup LED D3 indicator will be ON to indicate an enabled output http onsemi com 5 NB4N441MNGEVB APPENDIX 1 DEVICE AND BOARD INFORMATION SEE CURRENT DATASHEET DEVICE PINS ME yo Default Type ew sew O gatve Power Greaney 2 w s voor Pit fe s w s amo se ____ 7 PAZ wu cwsaOeiiaorimere Onsamut 8 mut Grystal Oscistorimerace Cnsalimwiortxema Cock pu s ew sw ww eem ves sew x wc suey JeWePmeSuny _ CI MOST CMOS TTL NOST HOSTEL TTL A DT IN E ETE
21. s Otherwise Specified Material 1 2 GETEK Laminate Epoxy Polyphenylene Oxide Resin Type NEMA FR 4 IPC L 1088 04 See Layer Table Inner Layers 1 02 Copper clad Outer Layers 1 2 oz Copper Foil Plated to 1 1 2 oz finished Refer to Stacking Diagram for Finished Board Thickness Tooling Finish 6 3 4 5 Photo etch circuitry per artwork drill locations controlled by drill file drl fabrication print The dielectric thickness of the controlled impedance layers is for reference only Final acceptance shall be determined by these layer pairs having a characteristic impedance of 52 5 10 The vendor can make width adjustments on only the critical conductor widths of 0 0005 All other adjustments must have prior approval from Baldwin Tech Layer Grouping 1 2 Finished conductor width to be 0 012 Plating Specification Electrodeposited hard gold plate Type 1 99 7 min gold Grade C Knoop Hardness 130 200 Class 1 50 100 micro inches thick in accordance with MIL G 4520C and ANSI IPC A 6000 Section 4 0 surface placing acceptability requirements Class 3 50 100 http onsemi com 13 14 16 thick over electrodeposited nickel plate in accordance with ANSI IPC A 6000 Section 4 0 Class 3 200 600 micro inches thick Drill sizes are finished Plated through holes to have a minimum barrel plating of 0 0008 in Board twist and warp not to exceed
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