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16-Bit RISC Microcontroller User's Manual

1. 4 3 MUL uOP and DIV of ALU function uOP for 8 bits operation need both 8 cycles for 16 bits operation need both 16 cycles 4 4 All jumps calls ret and loopXX instructions required to fetch the next instruction for the destination address Unconditional Fetch uOP will need 9 cycles Pipeline stages for unconditional fetch Fetch gt Decoded gt EA gt secs Idle gt TO gt T1 gt Fetch uOP n xt uOP Fetch Decode EA Acces Access Access T35WB pO UIRueseee will be flushed These 9 cycles caused branch penalty IDecode following stages New uOP Note op r operand read stage EA Calculate Effective Address stage Idle Bus Idle stage TO T3 Bus TO T3 stage Access Access data from cache memory stage RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 95 R D C RISC DSP Controller R8822 23 DC Characteristics 23 1 Absolute Maximum Rating Symbol Rating Commercial Unit Note T inal Volt ith R tt Vis Es oltage with Respectto 9 5 v 05 V
2. E Ee x lt Zlolo Z e mw o ga Ele Sls B o 2 8 az Ee ve m gE 2 2 SSS e LI Ez Dn ARE Alala S Zio Final Version 1 6 RDC Semiconductor Co January 5 2004 Subject to change without notice 105 R D C i RISC DSP Controller R8822 DRAM Read Cycle with No Wait State No Description MIN MAX Unit 1 CLKOUTA low to A Address Valid 0 12 ns 2 Data setup time 5 ns 3 Data hold time 2 ns 4 CLKOUTA high to Row address valid 0 12 ns 5 CLKOUTA low to Column address valid 0 12 ns 6 CLKOUTA low to RAS active 3 12 ns 7 CLKOUTA high to RAS inactive 3 12 ns 8 CLKOUTA high to CAS active 3 12 ns 9 CLKOUTA low to CAS inactive 3 12 ns 10 CLKOUTA low to RD active 0 12 ns 11 CLKOUTA low to RD inactive 0 12 ns RDC Semiconductor Co Subject to change without notice 106 Final Version 1 6 January 5 2004 RDC Rez a ao 2 B t u t CLKOUTA 1 T LT LE T LIT tT L1 LI o Kes DRAM Read Cycle with Wait States No Description MIN MAX Unit 1 CLKOUTA low to A Address Valid 0 12 ns 2 Data setup time 5 ns 3 Data hold time 2 ns 4 CLKOUTA high to Row address valid 0 12 ns 5 CLKOUTA low to Column address valid 0 12 ns 6 CLKOUTA low to RAS active 3 12 ns 7 CLKOUTA high to RAS inactive 3 12 ns 8 CLKOUTA high to CAS acti
3. A19 A0 aooco c0000 20000 0 101fc 2211 2211 DMA 1 The source synchronized transfer is not followed immediately by another DMA transfer No Description MIN MAX Unit j DRQ is confirmed time 3 ns RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 101 RDC swen o o o o R882 CLKOUTA DMA 2 The source synchronized transfer is followed immediately by another DMA transfer No Description MIN MAX Unit 1 DRQ is confirmed time 2 0 ns RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 102 R D C li RISC DSP Controller R8822 CLKOUTA No Description MIN MAX Unit 1 HOLD setup time 5 0 ns 2 HLDA Valid Delay 0 15 ns 3 HOLD hold time 2 0 ns 4 HLDA Valid Delay 0 15 ns RDC Semiconductor Co Subject to change without notice 103 Final Version 1 6 January 5 2004 R D C li RISC DSP Controller CLKOUTA R8822 ARDY Timing No Description MIN MAX Unit 1 ARDY Resolution Transition setup time 3 0 ns ARDY active hold time 5 0 ns RDC Semiconductor Co Subject to change without notice 104 Final Version 1 6 January 5 2004 R8822 R D C li RISC DSP Controller CLKOUTA o E E gt a oc Qo
4. T4 CLKOUTA TW R8822 RDC Semiconductor Co Subject to change without notice 99 Final Version 1 6 January 5 2004 R D C i RISC DSP Controller No Description MIN MAX Unit 1 CLKOUTA high to A Address Valid 0 12 ns 2 A address valid to WR low 1 5T 9 ns 3 S6 active delay 0 15 ns 4 S6 inactive delay 0 15 ns 5 AD address Valid Delay 0 12 ns 6 Address Hold ns 7 ALE active delay 0 12 ns 8 ALE width T 10 ns 9 ALE inactive delay 0 12 ns 10 Address valid after ALE inactive 1 2T 5 ns 1 WR active delay 0 12 ns 12 WR pulse width 2T 10 ns 13 WR inactive delay 0 12 ns 14 WHB WLB active delay 0 15 ns 15 WHB WLB inactive delay 0 15 ns 16 BHE active delay 0 15 ns 17 BHE inactive delay 0 15 ns 18 CLKOUTA high to UCS LCS valid 0 15 ns 19 UCS LCS inactive delay 0 15 ns 20 PCS MCS active delay 0 15 ns 21 PCS MCS inactive delay 0 15 ns 22 DEN active delay 0 15 ns 23 DEN inactive delay 0 15 ns 24 DTR active delay 0 15 ns 25 DTR inactive delay 0 15 ns 26 Status active delay 0 15 ns 27 Status inactive delay 0 15 ns 28 UZI active delay 0 15 ns 29 UZI inactive delay 0 15 ns R8822 RDC Semiconductor Co Subject to change without notice 100 Final Version 1 6 January 5 2004 RDC swen o o R882 Tl T2 T3 T4 TL T2 T3 T4 TL CLKOUTA
5. Memory and I O Space 512K Bytes 512K Bytes A19 1 D15 8 HE Physical Data Bus Models RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 RDC 0 R882 12 2 Data Bus The memory address space data bus is physically implemented by dividing the address space into two banks of up to 512k bytes One bank connects to the lower half of the data bus and contains the even addressed bytes A0 0 the other bank connects to the upper half of the data bus and contains odd addressed bytes A0 1 AO and BHE determine whether one bank or both banks participate in the data transfer 12 3 Wait States Wait states extend the data phase of the bus cycle The ARDY or SRDY input with low level will be inserted wait states in If R2 bit 0 the user can also insert wait states by programming the internal chip select registers The R2 bit of UMCS offset 0AOh default is low so either ARDY or SRDY should be in ready state with pull high resistors when at power on reset or external reset The wait state counter value is decided by the R3 Rland RO bits in each chip select register There are five groups of R3 R1 and RO bits in the registers offset AOh A2h A4h A6h and A8h Each group is independent R2 bit in control registers e N Bus EU JU Ready Wait State Falling CLKOUTA gt Edge Counter Rising Bus Ready is active High Edge eR2 bitin UMCS default is 0 so
6. 0000h 15 14 13 12 11 10 9 8 7 4 3 2 1 0 Bit 15 13 DMA DMA Control Field These bits configure the serial ports in use with DMA transfers ODE o MODD c TM R DMA control bits Bit 15 bit 14 bit 13 b Receive Transmit 0 0 0 NoDMA No DMA 0 0 1 DMAO0 DMA 1 RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 80 RDC swam 4 0 R882 0 1 0 DNE Les DMA 0 0 1 1 N A ss N A 1 0 0 i DMA0 xe No DMA 1 0 1 sx DMAI se No DMA 1 1 0 NoDMA DMA 0 1 1 1 NoDMA du DMA 1 Bit 12 RSIE Receive Status Interrupt Enable An exception occurring during data reception or error detection will generate an interrupt Set 1 Enable the serial port 0 to generate an interrupt request Bit 11 BRK Send Break Set this bit to 1 the TXD pin is always driven low Long Break The TXD is driven low for greater than 2M 3 bit times Short break The TXD is driven low for greater than M bit times M start bit data bits number parity bit stop bit Bit 10 TB8 Transmit Bit 8 This bit is transmitted as ninth data bit in mode 2 and mode 3 This bit is cleared after every transmission Bit 9 FC Flow Control Enable Set 1 Enable the hardware flow control for serial port 0 Set 0 Disable the hardware flow control for serial port 0 Bit 8 TXIE Transmitter Ready Interrupt Enable When the Transmit Holding Register is empty the THRE bit in St
7. Bit 8 TF Trace Flag Set to enable single step mode for debugging cleared to disable the single step mode If an application program sets the TF flag with POPF or IRET instruction a debug exception is generated after the instruction The CPU automatically generates an interrupt after each instruction that follows the POPF or IRET instruction Bit 7 SF Sign Flag If this flag is set the high order bit of the result of an operation will be 1 indicating the state of being negative Bit 6 ZF Zero Flag If this flag is set the result of the operation will be zero Bit 5 Reserved Bit 4 AF Auxiliary Flag If this flag is set there will be a carry from the low nibble to the high one or a borrow from the high nibble to the low nibble of the AL general purpose registers It is used in BCD operation Bit 3 Reserved Bit 2 PF Parity Flag This flag will be set if the result of low order 8 bit operation has even parity Bit 1 Reserved Bit 0 CF Carry Flag If CF is set there will be a carry out or a borrow into the high order bit of the instruction result RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 26 RDC swan o o o o R882 8 4 Address Generation The Execution Unit generates a 20 bit physical address to Bus Interface Unit by the Address Generation Memory is organized in sets of segments Each segment contains a 16 bit value Memory is addressed with a two component address that
8. eese eee ente eee etna tn nota 16 Timer Control Unif iere sto tita Rocha PP Y PP SHE SE eR ea eP ko uerus 16 1 Timer Counter Unit Output Mode ssssssssss 17 Watchdog Timer usceessoeeekver eet ta neo nucon ao ern nen pausa utin 18 Asynchronous Serial Ports e eeeeeeeeeeeeee 18 1 Serial Port Flow Corto renta titan beat 18 1 1 SDCEJDTBPEIOUDCOL 32er s Cet tos taut os I8 1 2 CTS KTR Protocol ineo d ure ee ner iis 18 2 DMA Transfer to from a Serial Port Function RDC Semiconductor Co Subject to change without notice Final Version 1 6 January 5 2004 RDC sses 23100 0 R882 18 3 The Asynchronous Mode Description eese nennen nennen enne 80 19 ILS E IIT EE 85 19 1 PIO Multi Function Pin List Table cae t etr e tenete e tie eter Mans qe etu eis 85 20 DURA wen Ie ETT 89 20 1 Programmable Read Write Cycle Time esee enne enne 89 20 2 Programmable Refresh Control sus oen ye n eae inv rene en dene em d dle ad 90 21 Instruction Set OPCodes and Clock Cycles eere eere eren 91 22 R8822 Execution Timings unen retos thee EE YES En eub escaderaabietesevedssavadsvesvacess 95 23 DiC Characters PLE RTT 96 23 1 Absolute Maximum Rating su one deter atten Lees rotiecie bs tol erbe iai 96 232 Recommended DC Operating Conditions soie n ebay p a dd en nds 96 23 3 DG Electrical C
9. 42 ud Bi directional I O with a 50 K internal pull up resistor 12mA TTL output 44 HLDA 4mA CMOS output 54 INT2 INTA0 PIO31 Bi directional I O with an enabled disabled 10 K internal 52 INT4 PIO30 pull up resistor when functions as PIO For normal function the 10k pull up resistor is disabled 8mA TTL output TTL Schmitt Trigger input Bi directional I O with a 10 K internal pull up resistor 53 INT3 INTA1 IRQ 8mA TTL output TTL Schmitt Trigger input R8822 RDC Semiconductor Co Subject to change without notice 17 Final Version 1 6 January 5 2004 R D C i RISC DSP Controller R8822 PQFP Pin NO Pin Name Characteristics 57 cs nam 2 RA TTL output ui a 10 K internal pull up resistor TTL Schmitt Trigger input T DEN PIOS 48 DT R PIO4 oe PCSO PIO16 65 PCSI PIO17 i PCg CTSI ENRX PIO18 62 PCS RTSI RTRI PIO19 n PCS5 A1 PIO3 59 PCH A2 PIO2 M MCSO0 PIO14 i MCS UCAS IPIOTS Bi directional I O with an enabled disabled 10 K internal MCS2 LCAS PIO24 pull up resistor when functions as PIO For normal 69 MCS3 RASI PIO25 function the 10k pull up resistor is disabled 97 UZI PIO26 8mA TTL output 96 S6 CLKDIV2 PIO29 75 TMRINO PIO11 72 TMRINI PIOO 77 DRQO INTS PIO12 76 DRQ1 INT6 PIO13 98 TXDI PIO27 99 RXDI PIO28 100 CTS0 ENRX0 PIO21 3 RTSO RTRO PIO20 RDC Semiconductor Co Subject to change without notice 18 Final Version 1 6 January 5 2004 RDC 0 0 R8
10. Bit 15 IREQ Interrupt Request Set 1 if an interrupt is pending The S4 S0 field contains valid data Bit 14 5 Reserved Bit 4 0 S4 S0 Poll Status Indicate the interrupt type of the highest priority pending interrupt Poll Register Offset 24h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I I I I IREQ Reserved S4 S0 Master Mode When the Poll register is read the current interrupt is acknowledged and the next interrupt takes its place in the Poll register Bit 15 IREQ Interrupt Request Set 1 if an interrupt is pending The S4 SO field contains valid data Bit 14 5 Reserved Bit 4 0 S4 S0 Poll Status Indicate the interrupt type of the highest priority pending interrupt RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 61 RDC swen o R882 End of Interrupt Register Offset 22h Reset Value 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 iid Master Mode Bit 15 NSPEC Non Specific EOI Set 1 indicates non specific EOI NSPEC Set 0 indicates the specific EOI interrupt type in S4 SO Bit 14 5 Reserved Bit 4 0 S4 S0 Source EOI Type Specify the EOI type of the interrupt that is currently being processed Note We suggest the specific EOI is the most secure method to use for resetting In Service bit Specific End of Interrupt Register Offset 22h Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 o ololj
11. Enable Watchdog Timer Set 0 Disable Watchdog Timer Bit 14 WRST Watchdog Reset Set 1 WDT generates a system reset when WDT timeout count is reached Set 0 WDT generates an NMI interrupt when WDT timeout count is reached if the NMIFLAG bit is 0 If the NMIFLAG bit is 1 the WDT will generate a system reset when timeout Bit 13 RSTFLAG Reset Flag When watchdog timer reset event occurs this bit will be set to 1 by hardware This bit will be cleared by any keyed sequence write to this register or external reset This bit is 0 after an external reset or 1 after a watchdog timer reset Bit 12 NMIFLAG NMI Flag After WDT generates an NMI interrupt this bit will be set to 1 by H W This bit will be cleared by any keyed sequence write to this register Bit 11 8 Reserved Bit 7 0 COUNT Timeout Count The COUNT setting determines the duration of the watchdog timer timeout interval a The duration equation Duration 5 Epon b The Exponent of the COUNT setting Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Exponent 0 0 0 0 0 0 0 0 N A Frequency X X X X X X X gt X 10 RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 76 R D C li RISC DSP Controller k xX X x x x 1 0 x x x xX x 1 0 0 x x x x 1 0 0 0 x x x 1 0 0 0 0 x x 1 0 0 0 0 0 x 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 c Watchdog timer Duration reference table 20 2
12. Watchdog Timer Control Register 76 58 Timer 1 Count Register 74 E4 Refresh Counter Register 90 56 Timer 0 Mode Control Register 71 E2 Refresh Reload Value Counter Register 90 54 Timer 0 Maxcount Compare B Register 73 DA DMA I Control Register 67 52 Timer 0 Maxcount Compare A Register 73 D8 DMA 1 Transfer Count Register 67 50 Timer 0 Count Register 73 D6 DMA I Destination Address High Register 67 46 Power Down Configuration Register 32 D4 DMA I Destination Address Low Register 68 44 Serial Port 0 interrupt control register 50 D2 DMA I Source Address High Register 68 42 Serial port 1 interrupt control register 50 DO DMA I Source Address Low Register 68 40 INTA4 Control Register 51 CA DMA 0 Control Register 64 3E INT3 Control Register 51 C8 DMA 0 Transfer Count Register 66 3C JINT2 Control Register 52 C6 DMA 0 Destination Address High Register 66 3A INTI Control Register 53 C4 DMA 0 Destination Address Low Register 66 38 INTO Control Register 53 C2 DMA 0 Source Address High Register 66 36 DMA 1 INT6 Interrupt Control Register 54 CO DMA 0 Source Address Low Register 67 34 DMA 0 INTS Interrupt Control Register 55 A8 PCS and MCS Auxiliary Register 43 32 Timer Interrupt Control Register 56 A6 Midrange Memory Chip Select Register 42 30 Interrupt Status Register 56 A4 Peripheral Chip Select Register 44 2E Interrupt Request Register 57 A2 Low Memory Chip Select Register 41 2C__ Interrupt In service Register 58 AO Upper Memory Chip Sel
13. the end of the DMA cycle And no DMA acknowledge is provided since the chip selects MCSx and PCSx can be programmed to be active for a given block of memory or I O space and the DMA source and destination address registers can be programmed to point to the same given block DMA transfer can be either source or destination synchronized and it can also be unsynchronized The Source Synchronized Transfer figure shows the typical source synchronized transfer which provides the source device at least three clock cycles from the time it is acknowledged to de assert its DRQ line RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 68 RD COM swen o o R882 Fetch Cycle Fetch Cycle T1 T2 T3 T4 T1 T2 T3 T4 CLKOUTA DRQ Casel DRQ Case2 NOTES Case1 Current source synchronized transfer will not be immediately followed by another DMA transfer Case Current source synchronized transfer will be immediately followed by antoher DMA transfer Source Synchronized Transfers The Destination Synchronized Transfer figure shows the typical destination synchronized transfer which differs from a source synchronized transfer in which two idle states are added to the end of the deposit cycle The two idle states extend the DMA cycle to allow the destination device to de assert its DRQ pin four clocks before the end of the cycle If the two idle states were not inserted the destination device would not
14. BHE ADO0 or AO Types of Bus Cycle 0 0 Word transfer 0 1 High byte transfer D15 D8 4 BHE ADEN Output Input 1 0 Low byte transfer D7 D0 1 1 Refresh The address portion of the AD bus can be enabled or disabled by DA bit in the LMCS and UMCS register during LCS or UCS bus cycle access if BHE ADEN is held high during power on reset No external pull up resistor is required because the BHE ADEN has an internal weak pull up resistor The AD bus always drives both address and data during LCS or UCS bus cycle access if the BHE ADEN pin is with an external pull low resistor during reset Write Strobe This pin indicates that the data on the bus is to 5 pd Output be written into a memory or an I O device WR is active during T2 T3 and Tw of any write cycle and floats during a bus hold or reset Read Strobe It s an active low signal which indicates that the 6 RD Output micro controller is performing a memory or I O read cycle RD floats during a bus hold or reset Address latch enable Active high This pin indicates that an address output on the AD bus Address is guaranteed to be valid on the trailing edge of ALE This pin is tri stated during ONCE mode and is never floating during a bus hold or reset Asynchronous ready This pin performs the microcontroller that the address memory space or I O device will complete a data transfer The ARDY pin accepts a rising edge that 1s asynchronous to CLKOUTA and is active high The fal
15. ENRXO signal is enabled Transmit data for asynchronous serial port 1 This pin transmits 98 TXDI PIO27 Output Input asynchronous serial data from the UART of the micro controllers 99 RXDI PIO28 Input Output Receive data for asynchronous serial port 1 This pin receives p asynchronous serial data Ready to send Ready to Receive signal for asynchronous serial port 1 When the RTSI bit in the AUXCON register is set and 62 PCS3 RTSI RTRI PIO18 Output Input the FC bit in the serial port 1 control register is set the RTSI signal is enabled Otherwise when the RTSI bit is cleared and the FC bit is set the RTRI signal is enabled RDC Semiconductor Co Subject to change without notice Final Version 1 6 January 5 2004 10 RDC 24 0 0 R882 Clear to send Enable Receiver Request signal for asynchronous serial port 1 When the ENRXI bit in the AUXCON register is cleared and the FC bit in the serial port 1 control register is set the CTSI signal is enabled Otherwise when the ENRXI bit is set and the FC bit 1s set the ENRXI signal is enabled Bus Interface Bus high enable address enable During a memory access the BHE and ADO or AO encodings indicate what types of the bus cycle BHE is asserted during T1 and keeps the asserted to T3 and Tw This pin is floating during a bus hold 63 PCS2 CTSI ENRXI PIO19 Input Output and reset BHE and ADO or AO Encodings
16. For internal PDATA B dec pull down Normal Data In O un normal function PIO pin Operation Diagram 19 1 PIO Multi Function Pin List Table PIO No Pin No PQFP Multi Function Reset status PIO internal resistor 0 72 TMRINI Input with 10k pull up 1 73 TMROUTI Input with 10k pull down 2 59 PCS6 A2 Input with 10k pull up 3 60 PCS5 A1 Input with 10k pull up 4 48 DT R Normal operation Input with 10k pull up 5 49 DEN Normal operation Input with 10k pull up 6 46 SRDY Normal operation Input with 10k pull down 7 22 A17 MA8 Normal operation Input with 10k pull up 8 20 A18 Normal operation Input with 10k pull up 9 19 A19 Normal operation Input with 10k pull up 10 74 TMROUTO Input with 10k pull down 11 75 TMRINO Input with 10k pull up 12 77 DRQO INTS Input with 10k pull up 13 76 DRQI INT6 Input with 10k pull up 14 50 MCSO Input with 10k pull up 15 51 MCSI UCAS Input with 10k pull up 16 66 PCSO Input with 10k pull up RDC Semiconductor Co Subject to change without notice 85 Final Version 1 6 January 5 2004 R8822 RDC RISC DSP Controller 17 65 PCSI Input with 10k pull up 18 63 PCS2 CTSI ENRX Input with 10k pull up 19 62 PCS3 RTSI RTRI Input with 10k pull up 20 3 RTSO RTRO Input with 10k pull up 21 100 CTSO ENRXO Input with 10k pull up 22 2 TXDO Input with 10k pull down 23 1 RXDO Input with 10k pull down 24 68 MCS2 LCAS Input with 10k pull up 25 69 MCS3
17. REQ I t t nterrup INT5 e Control Logic DMA1 Interrupt REQ inte K 16 Bit Int2 LE me LLL EOI Register INT4 In Service Asynchronous Serial Port 0 Acknowledge Register Asynchronous Serial Port 1 16 Bit Acknowledge to DMA Timer Serial port Unit Internal Address Data Bus Interrupt Control Unit Block Diagram 14 1 Master Mode and Slave Mode The interrupt controller can be programmed as a master or slave mode to program FEh 14 The master mode has two connections Fully Nested Mode connection or Cascade Mode connection RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 46 R D C li RISC DSP Controller Interrupt Source Interrupt Source Interrupt Source Interrupt Source Interrupt Source Interrupt Source Interrupt Source Fully Nested Mode Connections R8822 8259 INTA CAS3 CASO CAS3 CASO 8259 CAS3 CASO INT INTA CAS3 CASO Cascade Mode Connection INTO cade Address Dccode INTAO R8822 Slave Mode Connection Interrupt 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Interrupt Interrupt 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 t Interrup Sources Sources Sources Sources RDC Semiconductor Co Subject to change without notice 47 Final Version 1 6 January 5 2004 RDC swan o o R882 14 2 Interrupt Vector Type and Priority The
18. Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T l I Reserved erki mm RB8 RDR rare FER OER PER reur HS0 Res These bit definitions are the same as those of Register 82h Serial Port 1 Transmit Register Offset 14h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T I I T I T T T Reserved TDATA These bit definitions are the same as those of Register 84h Serial Port 1 Receive Register Offset 16h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 These bit definitions are the same as those of Register 86h Offset 18h Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I I I I I I I I I I I I I BAVDDIV Serial Port 1 Baud Rate Divisor Register These bit definitions are the same as those of Register 88h RDC Semiconductor Co Final Version 1 6 January 5 2004 Subject to change without notice 84 R D C 2 RISC DSP Controller 19 PIO Unit R8822 R8822 provides 32 programmable I O signals which are multi functional pins with other normal function signals Software is used to program the registers 7Ah 78h 76h 74h 72h and 70h to configure these multi functional pins for PIO or normal function For internal pull up v PIO PIO Mode Direction 1 Normal Function 1 3 J Pin PIO Data In Out 4 D OR r Read a
19. Ta Ambient Temperature 0 70 C 23 2 Recommended DC Operating Conditions Symbol Parameter Min Typ Max Unit Vcc Supply Voltage 4 75 5 2 25 V GND Ground 0 0 0 V Vih Input High Voltage Note 1 2 0 Vec 0 5 V Vihl Input High Voltage RST 3 Vce 0 5 V Vih2 Input High Voltage X1 3 Vec 0 5 V Vil Input Low voltage 0 5 0 0 8 V Note 1 The RST and XI pins are not included 23 3 DC Electrical Characteristics Symbol Parameter Test Condition Min Max Unit Vcc V max Ili Input Leakage Current Vin GND to Vmax 10 10 uA ae Input Leakage Current Vcc V max Ni with 10K pull R With Pull R10K enable Vin GNDtoVmax 79 400 vA o Input Leakage Current Vcc V max Ti Gath 90K pull E oss Pall R SOK Vin GND to Vmax 120 e e Vec V max Ilo Output Leakage Current Vin GND to Vmax 10 10 uA Iol 6mA VOL Output Low Voltage Vec Vmin 0 4 V Ioh 6mA VOH Output High Voltage Vec V min 2 4 V f Vcc 5 25V Icc Max Operating Current 40MHz 180 mA Note 2 Vmax 5 25V Vmin 4 75V Symbol Parameter Min Max Unit Note Fun Max operation clock frequency of u 40 Mhz Vect 5 commercial RDC Semiconductor Co Subject to change without notice 96 Final Version 1 6 January 5 2004 R D C 2 RISC DSP Controller 24 AC Characteristics R8822 BHE ucs LCs PCSx MCSx T1 READ CYCLE T2 T3 TA CLKOUTA TW RDC Semiconduc
20. an internal 10K pull down resistor 16 CLKOUTA 17 CLKOUTB 8mA 3 State CMOS output 9 TA Bi directional I O with a 50 K internal pull up resistor S2 BWSEL 4mA TTL output 10 S1 A 4mA 3 State CMOS output 11 SO 43 WLB 6 RD 12mA 3 State CMOS output 5 WR 19 A19 PIO9 Bi directional I O with an enabled disabled 10K sis 20 A18 PIO8 pull up resistors when functions as PIO For norma 22 A17 MA8 PIO7 function the 10k pull up resistor is disabled 16mA TTL output RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 16 R D C i RISC DSP Controller ers Pin Name Characteristics 23 A16 24 A15 MA7 25 A14 26 A13 MA6 27 A12 28 A11 MA5 29 A10 2 a1 16mA 3 State CMOS output 32 A7 MA3 33 A6 34 A5 MA2 35 A4 36 A3 MA1 37 A2 39 Al MAO 40 AO 78 ADO 80 ADI 82 AD2 84 AD3 86 AD4 88 ADS 91 AD6 94 AD7 Bi directional I O 79 AD8 16mA TTL output 81 AD9 83 AD10 85 ADII 87 AD12 90 AD13 93 AD14 95 ADI5 7 ALE Bi directional I O with a 50K internal pull down resistor 4mA TTL output 46 SRDY PIO6 Bi directional I O with an enabled disabled 10K internal 74 TMROUTO PIO10 pull down resistor when functions as PIO For normal 73 TMROUTI PIOI function the 10k pull down resistor is disabled 2 TXDO0 PIO22 8mA TTL output 1 RXD0 PIO23 ____ Bi directional I O with a 50 K internal pull up resistor 4 BHE ADEN 4mA TTL output
21. and large data structures The ES register is initialized to 0000H ss Stack Segment x O Extra Segment SEGMENT REGISTERS 8 3 Instruction Pointer and Status Flags Registers IP Instruction Pointer The IP is a 16 bit register and it contains the offset of the next instruction to be fetched The IP register cannot be directly accessed by software and 1s updated by the Bus Interface Unit It can be changed saved or restored as a result of program execution The IP register is initialized to 0000H and the CS IP starting execution address is at OFFFFOH RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 25 RDC a Processor Status Flags Registers FLAGS Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 These flags reflect the status after the Execution Unit is executed Bit 15 12 Reserved Bit 11 OF Overflow Flag If an arithmetic overflow occurs this flag will be set Bit 10 DF Direction Flag If this flag is set the string instructions are in the process of incrementing addresses If DF is cleared the string instructions are in the process of decrementing addresses Refer to the STD and CLD instructions for setting and clearing the DF flag Bit 9 IF Interrupt Enable Flag Refer to the STI and CLI instructions for setting and clearing the IF flag Set 1 The CPU enables the maskable interrupt request Set 0 The CPU disables the maskable interrupt request
22. be programmed to 0000b RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 RDC swan o o o o R882 DMA1 Destination Address Low Register Offset D4h DMA1 Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DDA15 DDAO Bit 15 0 DDA15 DDAO Low DMA 1 Destination Address These bits are mapped to A15 AO during a DMA transfer The value of DDA19 DDA0O will be incremented or decremented by 2 after each DMA transfer DMA1 Source Address High Register Offset D2h DMA1 Reset Value 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 Bit 15 4 Reserved Bit 3 0 DSA19 DSA16 High DMA 1 Source Address These bits are mapped to A19 A16 during a DMA transfer when the source address is in memory space or I O space If the source address is in I O space 64Kbytes these bits must be programmed to 0000b DMA1 Source Address Low Register Offset DOh DMA1 Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DSA15 DSAO Bit 15 0 DSA15 DSA0 Low DMA 1 Source Address These bits are mapped to A15 AO during a DMA transfer The value of DSA19 DSA0O will be incremented or decremented by 2 after each DMA transfer 15 2 External Requests External DMA requests are asserted on the DRQ pins The DRQ pins are sampled on the falling edge of CLKOUTA It takes a minimum of four clocks before the DMA cycle is initiated by the Bus Interface The DMA request is cleared four clocks before
23. change without notice 34 RDC 4B 12 Bus Interface Unit The bus interface unit drives address data status and control information to define a bus cycle The bus A19 A0 are non multiplexed memory or I O addresses The AD15 ADO are multiplexed addresses and data bus for memory or I O accessing The S2 S are encoded to indicate the bus status which is described in the Pin Description table page 12 The Basic Application System Block page 19 and Read Write Timing Diagram page 21 describe the basic bus operations When the DRAM controller is enabled AD15 ADO will perform the DRAM data bus during microcontroller accessing DRAM And the MA8 MAO are multiplexed with Address bus 12 4 X Memory and I O Interface The memory space consists of 1M bytes 512k 16 bit port and the I O space consists of 64k bytes 32k 16 bit port Memory devices exchange information with the CPU during memory read memory write and instruction fetch bus cycles I O read and I O write bus cycles use a separate I O address space Only IN OUT instruction can access I O address space and information must be transferred between the peripheral device and the AX register The first 256 bytes of I O space can be accessed directly by the I O instructions The entire 64k bytes I O address space can be accessed indirectly through the DX register I O instructions always force address A19 A16 to low level FFFFFH Memory 1M Bytes Space OFFFFH A 64K Bytes Space
24. cycles for each instruction The timings given are based on the following assumptions 1 The opcode along with data or displacement required for execution has been prefetched and resides in the instruction queue at the time needed 2 No wait states or bus HOLDs occur 3 All word data are located on even address boundaries 4 One RISC micro operation uOP maps one cycle according to the pipeline stages described below except the following case Pipeline Stages for single micro operation one cycle Fetch gt Decode gt jop_1 gt ALU gt WB For ALU function uOP Fetch gt Decode gt EA Access gt WB For Memory function uOP 4 1 Memory read uOP need 6 cycles for bus Pipeline stages for Memory read uOP 6 cycles Fetch gt Decode 2 EA gt Access gt Idle gt TO gt T1 gt T2 gt T3 BN n Cycle ui 4 2 Memory push uOP need 1 cycle if it has no previous Memory push uOP and 5 cycles if it has previous Memory push or Memory Write uOP Pipeline stages for Memory push uOP after Memory push uOP another 5 cycles Fetch gt Decode gt EA amp eces gt Idle T0 9 T1 WB 1 Memory push uOP 2 uOP Fetch gt Decode 2 EA 2 Acces gt Acces Idle T1 r2 gt T3 gt WB
25. each non used peripheral clock by programming the Disable Peripheral Clock Register Power Down This CPU can enter power down mode stop clock when the Power Down Configuration Register is programmed during the CPU running in full speed mode or power save mode The CPU will be waked up when each one of the external INTO INT1 INT2 INT3 and INT4 pins is active high and the CPU operating clock will go back to full speed mode if the INT is serviced the interrupt flag is enabled If the interrupt flag is disabled then the CPU will be waked up by the INT the operating clock will go back to the previous operating clock state and the CPU will execute the next program counter instruction There is 19 bit counter time waiting the crystal clock stable when the CPU wakes up from stop clock mode RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 30 RDC swam 4B Power Save Control Register Offset FOh Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSEN 0 0 CBF CBD CAF CAD 0 0 0 F2 FA FO MCSBIT Bit 15 PSEN Enable Power save Mode This bit is cleared by hardware when an external interrupt occurs This bit will not change when software interrupts INT instruction and exceptions occur Set 1 enable power save mode and divide the internal operating clock by the value in F2 F0 Bit14 MCSBIT MCSO0 control bit Set 0 M
26. fs re e r Bit 15 9 BA19 BA13 Base Address The BA19 BA13 correspond to bits 19 13 of the 1M bytes 20 bits programmable base address of the MCS chip select block The bits 12 to 0 of the base address are always 0 The base address can be set to any integer multiple of the size of the memory block size selected in these bits For example if the midrange block is 32Kbytes only the bits BA19 to BA15 can be programmed So the block address could be located at 20000h or 38000h but not in 22000h The base address of the MCS chip select can be set to 00000h only if the LCS chip select is not active And the MCS chip select address range is not allowed to overlap the LCS chip select address range The MCS chip select address range also is not allowed to overlap the UCS chip select address range Bit 8 3 Reserved Bit 2 R2 Ready Mode This bit is configured to enable disable the wait states inserted for the MCS chip selects The R1 andRO bits of this register determine the number of wait states to be inserted RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 42 RDC CBD Set 1 external ready 1s ignored Set 0 external ready is required Bit 1 0 R1 R0 Wait State value The R1 and RO determine the number of wait states inserted into an MCS access R1 RO 1 1 3 wait states 1 0 2 wait states 0 1 1 wait state 0 0 0 wait state PCS and MCS Auxiliary R
27. hold or reset 24 A15 MA7 25 Al4 MA8 MAO0 DRAM address interface The MA bus is 26 A13 MA6 multiplexed with A bus When accessing DRAM the bus 27 A12 performs row or column address otherwise the bus performs 28 A1I MAS Address bus 2 35 4 Output Input 31 A8 32 A7 MA3 33 A6 34 A5 MA2 35 A4 36 A3 MAI 37 A2 39 A1 MAO 40 AO The multiplexed address and data bus for memory or I O accessing The address is present during the t1 clock phase and the data bus phase is in t2 t4 cycle 78 80 82 84 8 ADO AD7 The address phase of the AD bus can be disabled when the p BHE ADEN pin is with an external pull low resistor during 79 81 83 85 8 ADS ADIS Input Output reset Keer 7 90 The AD bus is in high impedance state during a bus hold or 93 95 reset conditions and this bus is also used to load system configuration information with pull up or pull low resistors into the RESCON register when the reset input goes from low to high Write high byte This pin indicates the high byte data AD15 AD8 on the bus is to be written to a memory or I O 42 WHB Output device WHB isthe logic OR of BHE and WR This pin is floating during reset or bus hold conditions Final Version 1 6 January 5 2004 RDC Semiconductor Co Subject to change without notice 12 R D C RISC DSP Controller R8822 43 WLB Output Write low byte This pin indicates the low byte data AD7 ADO on the bus is to be written to a memory or I O device WLB
28. is granted the interrupt controller uses the interrupt type to access a vector from the interrupt vector table If the external INT is active level triggered to request the interrupt controller service and the INT pins must be held till the microcontroller enters the interrupt service routine There is no interrupt acknowledged output when running in fully nested mode so the PIO pins should be used to simulate the interrupt acknowledged pin if necessary 14 4 Interrupt Acknowledge The processor requires the interrupt type as an index into the interrupt table An internal or external controller can provide the interrupt type The internal interrupt controller provides the interrupt type to processor without external bus cycles generation When an external interrupt controller is providing the interrupt type the processor generates two acknowledged bus cycles and the interrupt type is written to the AD15 ADO lines by the external interrupt controller RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 48 RDC swen o R882 Tl T2 T3 TA T1 T2 T3 T4 CLKOUTA ADDRESS 19 0 S6 AD15 ADO BHE INTAO INTA1 DEN DT R NJ e INTR ACK INTERRUPT ACKNOWLEDGE CYCLE CASECADE OR SLAVE MODE 14 5 Programming the Registers Software is used to program the registers Master mode 44h 42h 40h 3Eh 3Ch 3Ah 38h
29. m 3 8 register with accumulator 10010 reg 3 XTAL Translate byte to AL 11010111 10 IN Input from fixed port 1110010w port 12 variable port 1110110w 12 OUT Output from fixed port 1110010w port 12 variable port 1110110w 12 LEA Load EA to register 10001101 mod reg r m 1 LDS Load pointer to DS 11000101 mod reg r m mod 11 14 LES Load pointer to ES 11000100 mod reg r m modz 11 14 ENTER Build stack frame 11001000 data low data high L L 0 7 L 1 11 L gt 1 11 10 L 1 LEAVE Tear down stack frame 11001001 7 LAHF Load AH with flags 10011111 2 SAHF Store AH into flags 10011110 2 PUSHF Push flags 10011100 2 POPF Pop flags 10011101 11 ARITHMETIC INSTRUCTIONS ADD Add reg memory with register to either 000000dw mod reg r m 1 7 immediate to register memory 100000sw mod 000 r m data data if sw 01 1 8 RDC Semiconductor Co Subject to change without notice 91 Final Version 1 6 January 5 2004 R8822 R D C i RISC DSP Controller immediate to accumulator 0000010w data data if w 1 1 Function Format Clocks Notes ADC Add with carry reg memory with reg
30. or odd addresses and two bus cycles are necessary reads from sources and writes to destinations Adder Control Logic for each data transfer 20 bit Adder Subtractor CAH 4 Channel 0 TDRQ DAH 4 Channel 1 Timer 2 Request DROO C8h Transfer Counter Channel 0 PEN C2h COh Source Address Channel 0 Request PNE DMA Arbitration DRO1 C6h C4h Destination Address Channel 0 Logic Control g Serial Port0 D8h Transfer Counter Channel 1 Logic Serial Port1 D2h D0h Source Address Channel 1 D6h D4h Destination Address Channel 1 Interrupt Request CAh 8 Channel 0 INT DAh 8 Channel 1 Channel Control Register0 CAh Channel Control Register1 DAh 16 bit Internal Address Data Bus DMA Unit Block 15 1 DMA Operation Every DMA transfer consists of two bus cycles see figure of Typical DMA Transfer and the two bus cycles cannot be separated by a bus hold request a refresh request or another DMA request The registers CAh C8h C6h C4h C2h COh DAh D8h D6h D4h D2h and DOh are used to configure and operate the two DMA channels RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 63 RDC o o o R882 et eaa i i EN RUN T pan m A19 AO0 fddresq Addresf aors ano 7 see Y esee D el aac Bl Typical DMA Trarsfer DMAO Conirol Register Offset CAh DMAO Reset Value 14 11 1 8 7 0 15 13 12
31. pending Bit 3 2 D1 I6 D0 I5 DMA Channel or INT Interrupt Request Set 1 The corresponding DMA channel or INT has an interrupt pending Bit 1 Reserved Bit 0 TMR Timer Interrupt Request Set 1 The timer control unit has an interrupt pending RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 57 RDC 8B Interrupt Request Register Offset 2Eh Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Slave Mode The Interrupt Request register is a read only register For internal interrupts D1 I6 D0 I5 TMR2 TMRI and TMRO the corresponding bit is set to 1 when the device requests an interrupt The bit is reset during the internally generated interrupt acknowledge Bit 15 6 Reserved Bit 5 4 TMR2 TMR1 Timer2 Timerl Interrupt Request Set 1 Indicates the state of any interrupt requests form the associated timer Bit 3 2 D1 16 D0 15 DMA Channel or INT Interrupt Request Set 1 Indicates the corresponding DMA channel or INT has an interrupt pending Bit 1 Reserved Bit 0 TMRO Timer 0 Interrupt Request Set 1 Indicates the state of an interrupt request from Timer 0 Interrupt In Service Register Offset 2Ch Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Master Mode The bits in the INSERV register are set by the interrupt controller when the interrupt 1s taken Each bit in the register 1s cleared by writing the corresponding interrupt type to t
32. the source address is in memory space or I O space If the source address is in I O space 64Kbytes these bits must be programmed to 0000b RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 66 RD COM swen o o R882 DMAO Source Address Low Register Offset COh DMAO Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DSA15 DSAO Bit 15 0 DSA15 DSA0 Low DMA 0 Source Address These bits are mapped to A15 AO during a DMA transfer The value of DSA19 DSAO will be incremented or decremented by 2 after each DMA transfer DMA1 Conirol Register Offset DAh DMA1 Reset Value 14 11 1 15 13 12 0 9 8 7 6 5 4 3 2 1 0 smo ro wr svwr svwo e frora exr cuo sr aw The definitions of Bit 15 0 for DMA1 are the same as those of Bit 15 0 of register CAh for DMAO DMA1 Transfer Count Register Offset D8h DMA1 Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC15 TCO Bit 15 0 TC15 TCO DMA 1 transfer Count The value of this register is decremented by 1 after each transfer DMA1 Destination Address High Register Offset D6h DMA1 Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 15 4 Reserved Bit 3 0 DDA19 DDA16 High DMA 1 Destination Address These bits are mapped to A19 A16 during a DMA transfer when the destination address is in memory space or I O space If the destination address is in I O space 64K bytes these bits must
33. the state of input pins with weakly pulled up or pulled down will be latched and each pin will perform the individual function The AD15 AD0 will be latched into the register F6h UCS ONCEI and LCS ONCE0 RASO will enter ONCE mode All of the pins will float except X1 and X2 when they are with pull low resistors The input clock will be divided by 2 when S6 CLKDIV2 is with a pull low resistor The AD15 ADO bus will drive both of the address and data regardless of the DA bit setting during UCS and LCS cyclesif BHE ADEN is with a pull low resistor CLKOUTA nin ae float input i e 0 flat float 5 Hii float LETY float float Reset Status RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 33 RDC swen o o R882 Offset F6h Reset Value AD15 ADO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset Configuration Register Bit 15 0 RC Reset Configuration ADI5 ADO The AD15 to ADO must be with weakly pulled up or pulled down resistors to correspond to the contents when ADI5 ADO are latched into this register during the RST pin goes from low to high The value of the reset configuration register provides the system information when this register is read by software This register is read only and the contents remain valid until next processor reset Final Version 1 6 RDC Semiconductor Co January 5 2004 Subject to
34. will be set Bit 1 HS0 Handshake Signal 0 This bit is read only This bit reflects the inverted value of the external CTSO pin Bit 0 Reserved Serial Port 0 Transmit Register Offset 84h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 15 8 Reserved Bit 7 0 TDATA Transmit Data This register is written by software with data to be transmitted on the serial port 0 Serial Port 0 Receive Register Offset 86h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 15 8 Reserved Bit 7 0 RDATA Received DATA The RDR bit should be read as 1 before the RDATA register is read to avoid reading invalid data Serial Port 0 Baud Rate Divisor Register Offset 88h Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I I I I I I I I I I I BAUDDIV Bit 15 0 BAUDDIV Baud Rate Divisor The general formula for baud rate divisor is Baud Rate Microprocessor Clock 16 x BAUDDIV For example when the Microprocessor clock is 22 1184MHz and the BAUDDIV 12 Decimal the baud rate of serial port is 115 2k RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 RDC swen o o o R882 Offset 10h Reset Value 0000h 4 3 2 1 0 15 14 13 12 11 10 9 8 7 These bit definitions are the same as those of Register 80h Serial Port 1 Control Register MODE gt MODD c 1 R Serial Port 1 Status Register Offset 12h
35. word 26 memory byte 23 memory word 31 IDIV Integer divide signed 1111011w mod 111 r m register byte 18 register word 26 memory byte 23 memory word 31 AAS ASCII adjust for subtraction 00111111 3 DAS Decimal adjust for subtraction 00101111 2 AAA ASCII adjust for addition 00110111 3 DAA Decimal adjust for addition 00100111 2 AAD ASCII adjust for divide 11010101 00001010 14 AAM ASCII adjust for multiply 11010100 00001010 15 CBW Corrvert byte to word 10011000 2 CWD Convert word to double word 10011001 2 RDC Semiconductor Co Subject to change without notice 92 Final Version 1 6 January 5 2004 R D C RISC DSP Controller R8822 Function Format Clocks Notes BIT MANIPULATION INSTRUCTUIONS NOT z Invert register memory 1111011w mod 010 r m 1 7 AND And reg memory and register to either 001000dw mod reg r m 1 7 immediate to register memory 1000000w mod 100 r m data data if w 1 1 8 immediate to accumulator 0010010w data data if w 1 1 OR Or reg memory and register to either 000010dw mod reg r m 1 7 immediate to register memory 1000000w mod 001 r m data data if w 1 1 8 immediate to accumulator 0000110w data data if w 1 1 XOR Exclusive or reg memory and register to either 001100dw mod reg r m 1
36. 0 9 6 5 4 3 2 1 bwiojonec omc ewo soec swe rc wr svv swo e frora exr cna sr aw Bit 15 DM IO Destination Address Space Select Set 1 The destination address is in memory space Set 0 The destination address is in I O space Bit 14 DDEC Destination Decrement Set 1 The destination address 1s automatically decremented after each transfer The B W bit 0 bit determines the decremented value which is by 1 or 2 When both of the DDEC and DINC bits are set to 1 the address remains constant Set 0 Disable the decrement function Bit 13 DINC Destination Increment Set 1 The destination address 1s automatically incremented after each transfer The B W bit 0 bit determines the incremented value which is by 1 or 2 Set 0 Disable the increment function Bit 12 SM IO Source Address Space Select Set 1 The Source address is in memory space Set 0 The Source address is in I O space Bit 11 SDEC Source Decrement Set 1 The Source address is automatically decremented after each transfer The B W bit 0 bit determines the decremented value which is by 1 or 2 When both of the SDEC and SINC RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 64 RDC 8B bits are set to 1 the address remains constant Set 0 Disable the decrement function Bit 10 SINC Source Increment Set 1 The Source address is automatically incremented after each transfer The B W bit 0 bit determin
37. 1 22 23 24 25 26 Frequency Exponent 10 20 21 22 23 24 25 26 20 MHz Slus 52ms 104 ms 209 ms 419 ms 838ms 1167s 3 35s 25 MHz 40us 41 ms 83 ms 167 ms 335ms 671ms_ 1 34s 2 68s 33 MHz 30us 31ms 62ms 125 ms 251 ms 503ms 1 00s 2 01s 40 MHz 25us 26ms 52ms 104ms 209ms 419ms 838 ms 1 67 s R8822 RDC Semiconductor Co Subject to change without notice 77 Final Version 1 6 January 5 2004 RDC 0 R882 18 Asynchronous Serial Ports R8822 has two asynchronous serial ports which provide the TXD and RXD pins for the fully duplexed bi directional data transfer and with handshaking signals CTS ENRX RTS and RTR The serial ports support 9 bit 8 bit or 7 bit data transfer odd parity even parity or no parity 1 stop bit Error detection DMA transfers through the serial port Multi drop protocol 9 bit support Double buffers for transmit and receive The receive transmit clock is based on the microprocessor clock The serial port can be used in power saved mode but the transfer rate must be adjusted to correctly reflect the new internal operating frequency Software is used to program the registers 80h 82h 84h 86h and 88h for port 0 10h 12h 14h 16h and18h for port 1 to configure the asynchronous serial ports Internal Address Data Bus 16 bit Transmit Receive Data Register 84h 14h Data Reg
38. 15 4 Reserved Bit 3 MSK Mask Set 1 Mask the interrupt source of the DMA 1 controller Set 0 Enable the DMA 1 controller interrupt Bit 2 0 PR Interrupt Priority These bit settings for priority selection are the same as those of bit 2 0 of Register 44h RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 RDC o o R882 DMA 1 INT6 Interrupt Control Register Offset 36h Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Lojoro ojo ojo o o ojo usk ere prs rn Slave Mode reset value is 0000h Bit 15 4 Reserved Bit 3 MSK Mask Set 1 Mask the interrupt source of the DMA 1 controller Set 0 Enable the DMA 1 controller interrupt Bit 2 0 PR Interrupt Priority These bit settings for priority selection are the same as those of bit 2 0 of Register 44h DMA O INT5 Interrupt Control Register Offset 34h Reset Value 000Fh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 polo fofo ofo o o o oe o Jase pre par pr Master Mode Bit 15 4 Reserved Bit 3 MSK Mask Set 1 Mask the interrupt source of the DMA 0 controller Set 0 Enable the DMA 0 controller interrupt Bit 2 0 PR Interrupt Priority These bit settings for priority selection are the same as those of bit 2 0 of Register 44h DMA O INT5 Interrupt Control Register Offset 34h Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Ee ojeoro ojojo o ojo o o usere rat pro Slave Mode Bit 15 4 Rese
39. 1orida 0soa zx 22A C an IX vecoia Svoi zSoW GND szoia rsvH ESOWN 1 os ano 1 IS isa C Tasma zs oord INIWNL amy TOId TLNOWNL C a a1 OTOId OLNOMWL Il au IIOId ONIWNL uM TOId 9INI TOud 1 Nuav sHg8 ZIOId SLNI o0Ouad 1 ozora ouru 0oslu o a N m ut N o oo o o a N m bl N o mol oo o n a a a n a a a a ad N N N N N N E S HU UU UUU UU UU UU O O nu0 q e 4 e q e i g un o 8 7 a D s i o q a S 4249828828282862295222988282822323 H H H H H HHAH aanmanmas mO m a NRSV g eB EGE EE en g B Z B a U B N n o E n U Subject to change without notice RDC Semiconductor Co R D C li RISC DSP Controller 3 3 R8822 PQFP amp LQFP Pin Out Table R8822 Pin name LQFP Pin No PQFP Pin No Pin name LQFP Pin No PQFP Pin No ADO 1 78 A11 MA5 51 28 ADS 2 79 A10 52 29 ADI 3 80 A9 MA4 53 30 AD9 4 81 A8 54 31 AD2 5 82 A7 MA3 55 32 ADIO 6 83 A6 56 33 AD3 7 84 A5 MA2 57 34 ADII 8 85 A4 58 35 AD4 9 86 A3 MAI 59 36 ADI2 10 87 A2 60 37 ADS 11 88 VCC 6l 38 GND 12 89 A1 MAQ0 62 39 ADI3 13 90 A0 63 40 AD6 14 91 GND 64 41 VCC 15 92 WHB 65 42 ADI4 16 93 WLB 66 43 AD7 17 94 HLDA 67 44 ADI5 18 95 HOLD 68 45 S6 CLK DIV PIO29 19 96 SRDY PIO6 69 46 UZI PIO26 20 97 NMI 70 47 TXDI PI
40. 3 A6 A5 MA2 A3 MA1 NMI DT R PIO4 DEN PIO5 49 MCSO PIO14 50 R8822 DRQO INT5 PIO12 DRQ1 INT6 PIO13 TMRINO PIO11 TMROUTO PIO10 TMROUT1 PIO1 TMRIN1 PIOO RST GND MCS3 RAS1 PIO25 MCS2 LCAS P1O24 vcc PCSO PIO16 PCS1 PIO17 GND PCSZ CTSI ENRX1 PIO18 PCS3 RTS1 RTR1 PIO19 vcc PCS5 A1 PIO3 PCS6 A2 P102 LCS ONCEO RASO UCS ONCE1 INTO INT1 SELECT INT2 INTAO PIO31 INT3 INTA1 IRQ INT4 PIO30 MCS1 UCAS PIO15 RDC Semiconductor Co Subject to change without notice Final Version 1 6 January 5 2004 R8822 71 DT R P104 70 NMI 74 MCS1 UCAS PIO15 73 McSso P1014 72 DEN PIO5 66 WLB 75 __ INT4 PI030 69 7 SRDY PIO6 68 HOLD 65 WHB 62 A1 MAO 61 vcc 59 A3 MA1 58 A4 55 A7 MA3 64 GND 63 ao 60 1 a2 57 A5 MA2 56 A6 54 as 53 A9 MA4 52 A10 51 A11 MA5 67 HLDA Final Version 1 6 January 5 2004 R D C li RISC DSP Controller OuI IVINI INI ziv TEOId OWLNI ZINI 1 9vW tIV LOWISS ILNI viv ouNI 1 LVW SIV IXoNO SOn 91v osvsu 0uoNo soi1 Loria 8VW LTIV zoia zv 9soa 22A tora 1v ssod C 1 8014 8T 22A 1 eora eiv eroId Iuru ISLlN ESOd ana 8TOId IXuNS ISL2 2SOd 1 amp Lnoxio ano 1 1 vinoxTo Lioria Isoa 1 994 9
41. 36h 34h 32h 30h 2Eh 2Ch 2Ah 28h 26h 24h 22h Slave Mode 3Ah 38h 36h 34h 32h 30h 2Eh 2Ch 2Ah 28h 22h 20h to define the interrupt controller operation RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 49 RDC o o o O R882 Serial Port 0 Interrupt Control Register Offset 44h Reset Value 001Fh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 present Lt si e em ero Master Mode Bit 15 4 Reserved Bit 3 MSK Mask Set 1 Mask the interrupt source of the asynchronous serial port 0 Set 0 Enable the serial port 0 interrupt Bit 2 0 PR2 PRO Priority These bits determine the priority of the serial port related to the other interrupt signals The priority selection PR2 PRI PRO Priority 0 0 0 0 High 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 41 0 6 1 1 1 7 Low Serial Port 1 Interrupt Control Register Offset 42h Reset Value 000Fh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 peers sc ero Master Mode Bit 15 4 Reserved Bit 3 MSK Mask Set 1 Mask the interrupt source of the asynchronous serial port 1 Set 0 Enable the serial port interrupt Bit 2 0 PR2 PRO Priority These bits determine the priority of the serial port related to the other interrupt signals The priority selection RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 50 RDC swe
42. 5 Modify Oscillator Characteristics F15 2002 05 08 Modify Wait State Description F16 2004 01 05 Modify DC Characteristics and add Thermal Characteristics R8822 RDC Semiconductor Co Subject to change without notice 114 Final Version 1 6 January 5 2004
43. 7 immediate to register memory 1000000w mod 110 r m data data if w 1 1 8 immediate to accumulator 0011010w data data if w 1 1 TEST And function to flags no result register memory and register 1000010w mod reg r m 1 7 immediate data and register memory 1111011w mod 000 r m data data if w 1 1 8 immediate data and accumulator 1010100w data data if w 1 1 Sifts Rotates register memory by 1 1101000w mod TTT r m 2 8 register memory by CL 1101001w mod TTT r m 1 n 7 n register memory by Count 1100000w mod TTT r m count 1 n 7 n STRING MANIPULATION INSTRUCTIONS MOVS Move byte word 1010010w 13 INS Input byte word from DX port 0110110w 13 OUTS Output byte word to DX port 0110111w 13 CMPS z Compare byte word 1010011w 18 SCAS Scan byte word 101011w 13 LODS Load byte word to AL AX 1010110w 13 STOS Store byte word from AL AX 1010101w 7 Repeated by count in CX MOVS z Move byte word 11110010 1010010w 4 9n INS Input byte word from DX port 11110010 0110110w 5 9n OUTS Output byte word to DX port 11110010 0110111w 549n CMPS z Compare byte word 1111011z 1010011w 4 18n SCAS Scan byte word 1111001z 1010111w 4 13n LODS Load byte word to AL AX 11110010 0101001w 3 9n STOS Store byte word from AL AX 11110100 0101001w 4 3n PROGRAM TRANSFER INSTRUCTIONS Conditional Transfers junpif JE JZ equal zero 01110100 disp 1 9 JL JNGE less not greater or equal 01111100 disp 1 9 JLE JNG less or equal not greater 01111110 disp 1 9 JC J
44. 7 PCS3 Base Address 768 Base Address 1023 PCSS BaseAddress 1280 Base Address 1535 PCS6 Base Address 1536 Base Address 1791 Bit 6 4 Reserved Bit 3 R3 Bit 1 0 R1 RO Wait State Value The R3 R1 and RO determine the number of wait states inserted into a PCS3 PCSO access R3 RI RO Wait States 0 0 0 0 0 0 1 0 1 0 2 0 i 3 1 0 0 5 1 0 1 7 1 1 0 9 l 1 1 15 RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 44 RDC swan o o o o R882 Bit 2 R2 Ready Mode This bit is configured to enable disable the wait states inserted for the PCS3 PCS0 chip selects The R3 R1 and RO bits determine the number of wait state to be inserted Set 1 external ready is ignored Set 0 external ready is required RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 45 RDC 4B 14 Interrupt Controller Unit There are 16 interrupt requests source connected to the controller 7 maskable interrupt pins INTO INT6 2 non maskable interrupts NMI pin and WDT 7 internal unit request sources Timer 0 1 and 2 DMA 0 and 1 Asynchronous serial port 0 and 1 Master Slave Mode Select FEH 14 Timer0 1 2 Interrupt REQ Timer0 REQ INTO K Timerl REQ INTL Timer2 REQ Interrupt Type Unit Watchdog Timer Execation f J NMI Interrupt REQ DMAO Interrupt
45. 82 5 Basic Application System Block Flash ROM BASIC APPLICATION SYSTEM BLOCK A Flash ROM High Byte Low Byte Converter Timer0 1 INTx DMA PIO BASIC APPLICATION SYSTEM BLOCK B RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 19 R D C li RISC DSP Controller Flash ROM byte word access selection byte access with a 330ohm pull low resistor Level Converter RS232 Level Converter 100K luF BASIC APPLICATION SYSTEM BLOCK C S2 BWSEL Serial port0 R8822 Serial portl Timer0 1 INTx DMA TM R8822 Flash ROM Data 16 or 8 Address WE OE CE EDO FP DRAM Data 16 MAO MA8 amp RAS 256Kx16 Peripheral Data 16 or 8 Address RDC Semiconductor Co Subject to change without notice 20 Final Version 1 6 January 5 2004 RDC 4B 6 Read Write Timing Diagram T1 T2 T3 T4 CLKOUTA TW A19 A0 DRESS AD15 ADO BHE UCS LCS PCSx MCSx DEN UZI READ CYCLE RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 21 R D C i RISC DSP Controller A19 A0 S6 AD15 ADO WHB WLB BHE UCS LCS PCSx MCSx DEN UZI T1 T2 WRITE CYCLE T3 T4 CLKOUTA TW R8822 RDC Semiconductor Co Subje
46. B JNAE carry below not above or equal 01110010 disp 1 9 JBE JNA below or equal not above 01110110 disp 1 9 JP JPE parity parity even 01111010 disp 1 9 JO overflow 01110000 disp 1 9 JS sign 01111000 disp 1 9 JNE JNZ not equal not zero 01110101 disp 1 9 JNL JGE not less greater or equal 01111101 disp 1 9 JNLE JG not less or equal greater 01111111 disp 1 9 JNC JNB JAE not carry not below 01110011 disp 1 9 above or equal JNBE JA not below or equal above 01110111 disp 1 9 JNP JPO not parity parity odd 01111011 disp 1 9 JNO not overflow 01110001 disp 1 9 RDC Semiconductor Co Subject to change without notice 93 Final Version 1 6 January 5 2004 RDC ena R8822 JNS not sign 01111001 disp 1 9 Function Format Clocks Notes Unconditional Transfers CALL Call procedure direct within segment 11101000 disp low disp high 11 reg memory indirect within segment 11111111 mod 010 r m 12 17 indirect intersegment 11111111 mod 011 r m mod 11 25 direct intersegment 10011010 segment offset 18 selector RET Retum from procedure within segment 11000011 16 within segment adding immed to SP 11000010 data low data high 16 intersegment 11001011 23 instersegment adding immed to SP 1001010 data low data high 23 JMP
47. B within 7 days after the dry pack is opened If the IC is out of dry pack more than 7 days it should be burned in oven 125 C gt 12 hours before mounted on PCB RDC Semiconductor Co Subject to change without notice 111 Final Version 1 6 January 5 2004 RDC sees RB 26 Package Information 26 1 POFP a ma YP co j E o m 2 1 f J N w ks bom c RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 112 R D C li RISC DSP Controller 262 LQFP 16 00 0 10 14 00 0 10 0 127 TYP 1 60 MAX A A o o ad a o o o o o o e a n IN HY v gt gt lt 0 50 TYP 0 2240 05 wan Sealing Plane A 0 076 MAX A wn o o o lt a Wd A N o o lt gt 0 60 0 15 1 9 1 00 REF o UNIT mm R8822 RDC Semiconductor Co Subject to change without notice 113 Final Version 1 6 January 5 2004 R D C i RISC DSP Controller 27 Revision History Rev Date History P10 2000 7 31 Preliminary Version F11 2001 5 17 Final Version 1 1 Formal release F12 2001 8 10 Modify Wait State Description Page 30 F13 2001 11 29 DC Characteristics F14 2001 12 2
48. CPU is required CLKOUTA CLKOUTA external ready at power on reset The wait state counter value is located at Wait state block Diagram coru regtiss CIP ssc unit ARDY 12 4 Bus Hold When the bus hold is requested HOLD pin and active high by another bus master the microprocessor will issue a HLDA in response to a HOLD request at the end of T4 or Ti When the microprocessor is in hold status HLDA is high the ADI5 AD0 A19 A0 WR RD DEN SI S0 S6 BHE DT R WHB and WLB are floating and the UCS LCS PCS6 PCSS MCS3 MCSO and PCS3 PCSO will be driven high After HOLD is detected as being low the microprocessor will lower the HLDA RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 36 RD COM swen o n o R882 Case 1 Ti Ti Ti Ti Case 2 T3 T4 Ti Ti CLKOUTA HOLD HLDA AD15 ADO aaa Floating i A19 A0 DEN DT R 2 S0 ELTE ileatiag a SS BUS HOLD ENTER WAVEFORM RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 37 RDC swen 0 R882 Case 1 Ti Ti Ti Ti T1 Case 2 Ti Ti Ti T4 T1 woa 1T LI LIT HLDA AD15 ADO Floating A19 A0 rieetias MEM NE DEN P Tii Des a Floating lix WR Floating duce DER e Floating eee S2 S0 r
49. CSO operates normally Set 1 MCSO is active over the entire MCSx range Bit13 12 Reserved Bit 11 CBF CLKOUTB Output Frequency selection Set 1 CLKOUTB output frequency is the same as crystal input frequency Set 0 CLKOUTB output frequency is from the clock divisor which frequency is the same as that of microprocessor internal clock Bit 10 CBD CLKOUTB Drive Disable Set 1 Disable the CLKOUTB This pin will be three stated Set 0 Enable the CLKOUTB Bit 9 CAF CLKOUTA Output Frequency selection Set 1 CLKOUTA output frequency is the same as crystal input frequency Set 0 CLKOUTA output frequency is from the clock divisor which frequency is the same as that of microprocessor internal clock Bit 8 CAD CLKOUTA Drive Disable Set 1 Disable the CLKOUTA This pin will be three stated Set 0 Enable the CLKOUTA Bit 7 3 Reserved Bit 2 0 F2 F0 Clock Divisor Select F2 Fl F0 Divider Factor 0 0 0 Divided by 1 0 0 Divided by 2 0 J 0 Divided by 4 0 1 1 Divided by 8 1 0 0 Divided by 16 1 0 1 Divided by 32 1 1 0 Divided by 64 l 1 1 Divided by 128 RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 31 RDC swen o o R882 Disable Peripheral Clock Register Offset FAh Reset Value 0000h 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 UART DMA Timer IntCIk Clk Clk Clk Reserved Bit 15 Int Clk Set 1 to stop the Interru
50. O input signal from low to high rising edge trigger Set 0 Low input holds the timer 0 Count Register 50h value High input enables the counting which counts internal events The definition of setting the EXT RTG 0 0 Timer counts the internal events if the TMRINO pin remains high 0 1 Timer counts the internal events count register reset on every rising transition on the TMRINO pin 1 x TMRINO pin input acts as clock source and timer0 count register is incremented by one every external clock Bit 3 P Pre scaler Bit This bit and EXT bit 56h 2 define the timer0 clock source The definition of setting the EXT P 0 0 Timer0 Count Register is incremented by one every four internal processor clock 0 1 Timer count register is incremented by one which is pre scaled by timer 2 1 x TMRINO pin input acts as clock source and Timer0 Count Register is incremented by one every external clock Bit 2 EXT External Clock Bit Set 1 Timer0 clock source from external Set 0 Timer clock source from internal Bit 1 ALT Alternate Compare Bit This bit controls whether the timer runs in single or dual maximum count mode Set 1 Specify dual maximum count mode In this mode the timer counts to Maxcount Compare A and resets the count register to 0 Then the timer counts to Maxcount Compare B resets the count register to 0 again and starts over with Maxcount Compare A Set 0 Specify single maximum count mode In t
51. O input without pull up pull down PIO Data 0 Register Offset 74h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PDATA 15 0 Bit 15 0 PDATA15 PDATAO PIO Data Bus These bits PDATA15 PDATAO are mapped to PIO15 PIOO which indicate the driven level when the PIO pin is as an output or reflect the external level when the PIO pin is as an input PIO Direction 0 Register Offset 72h Reset Value FCOFh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I I I PDIR 15 0 Bit 15 0 PDIR 15 PDIRO PIO Direction Register Set 1 Configure the PIO pin as an input Set 0 Configure the PIO pin as an output or as normal pin function RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 87 R D C li RISC DSP Controller PIO Mode 0 Register Offset 70h Reset Value 0000h 3 2 1 0 I PMODE 15 0 Bit 15 0 PMODE15 PMODED0 PIO Mode Bit R8822 RDC Semiconductor Co Subject to change without notice 88 Final Version 1 6 January 5 2004 RDC swam 4 0 R882 20 DRAM Controller The R8822 supports 16 bit EDO or FP DRAM control interface The supporting types are 256k 16 128k 16 64k 16 or 32k 16 The DRAM control pins are multiplexed pins which have been described in the Pin Configuration The Basic System Application Block Diagram shows the connection between the microcontroller and DRAM The DRAM controller supports two b
52. O27 21 98 DT R PIO4 71 48 RXDI PIO28 22 99 DEN PIO5 72 49 CTS0 ENRXO PIO21 23 100 MCSO PIO14 73 50 RXDO0 PIO23 24 1 MCSI UCAS PIOI5 74 51 TXDO0 PIO22 25 2 INT4 PIO30 75 52 RTSO RTRO PIO20 26 3 INT3 INTA 1 IRQ 76 53 BHE ADEN 27 4 INT2 INTAO PIO31 TT 54 WR 28 5 INTI SELECT 78 2 RD 29 6 INTO 79 56 ALE 30 F UCS ONCE 1 80 57 ARDY 31 8 LCS ONCE0 RASO 81 58 S2 BWSEL 32 9 PCS6 A2 P102 82 59 S1 33 10 PCS5 A1 PIO3 83 60 S0 34 11 VCC 84 31 GND 35 12 PCS3 RTSI RTRI PIO19 85 62 XI 36 13 PCS2 CTSI ENRXI PIO18 86 63 X2 37 14 GND 87 64 VCC 38 15 PCSI PIO17 88 65 CLKOUTA 39 16 PCSO PIO16 89 66 CLKOUTB 40 17 VCC 90 67 GND 41 18 MCS2 LCAS PIO24 91 68 A19 PIO9 42 19 MCS3 RASI P1025 92 69 A18 PIO8 43 20 GND 93 70 VCC 44 21 RST 94 71 A17 MA8 PIO7 45 22 TMRI NI PI O0 95 72 A16 46 23 TMROUTI PI O1 96 73 A15 MA7 47 24 TMROUTO PI O10 97 74 A14 48 25 TMRI NO PI O11 98 75 A13 MA6 49 26 DRQI INT6 PI O13 99 76 A12 50 27 DRQO INTS PI O12 100 77 RDC Semiconductor Co Subject to change without notice Final Version 1 6 January 5 2004 R D C 2 RISC DSP Controller R8822 4 Pin Description Pin No mbol T Description PQFP Symbo ype escriptio 15 21 38 61 VCC Trout System power 5 volt power supply 67 92 p 12 18 41 64 System ground 70 89 GND Input Reset input When RST is asserted the CPU immediately 71 RST Input terminates all operations cle
53. Offset 2Ah Reset Value 0007h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Lojoo o o ojo o o ojojo nnn Master Mode Determine the minimum priority level at which maskable interrupts can generate an interrupt Bit 15 3 Reserved Bit 2 0 PRM2 PRMO Priority Field Mask Determine the minimum priority that is required in order for a maskable interrupt source to generate an interrupt Priority PR2 PRO High 0 000 1 001 2 010 3 011 4 100 5 101 6 110 Low 7 111 RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 59 RDC o O R882 Priority Mask Register Offset 2Ah Reset Value 0007h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Ee o o o ojojo ojo ojo o jmnvjnw n Slave Mode Determine the minimum priority level at which maskable interrupts can generate an interrupt Bit 15 3 Reserved Bit 2 0 PRM2 PRM6O Priority Field Mask Determine the minimum priority that is required in order for a maskable interrupt source to generate an interrupt Priority PR2 PRO High 0 000 1 001 2 010 3 011 4 100 5 101 6 110 Low 7 111 Interrupt Mask Register Offset 28h Reset Value 07FDh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Master Mode Bit 15 11 Reserved Bit 10 SPO Serial Port 0 Interrupt Mask The state of the mask bit of the asynchronous serial port 0 interrupt Bit 9 SP1 Serial Port 1 I
54. Oils eda iecit tl Ran pt d desi pde dite uten UR ae nada 27 9 Peripheral Control Block Registers eee ee e eee esee eee eene eere eee en setae etae 28 10 Power Save amp Power DOW uova EI IYVERVREKERENE REM NE ERROR MR DURER UP EYE REV V REY EN UKR 30 11 l m 33 12 Bus Interface HII Meer 35 12 1 Memory and VO Interface c ssed oe uH NERUE US EUN DU E RM DU UU ted 35 RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 R D C ii RISC DSP Controller 12 2 Data ris tends 12 3 Wait State Smoren deum E du De UNE dades 12 4 Bus Hold rede es date diene Aa nein cane cuta tds 12 5 B Wide st eho boas as ee nA EI a E 13 Chip Select Unit m 13 1 UGS apa UN INA So S waged Dita eget tute E E E ied 132 LOS RS 13 3 MESE eie eet ep ene a een SNe eee 13 4 PSK 14 Interrupt Controller Unit eee 14 1 Master Mode and Slave Modes et ed eitis 14 2 Interrupt Vector Type and Priority sss 14 3 Interrupt Requests aces et eie abs te dacit e tpe tu tei Oba 14 4 Interrupt Acknowledge aee eese rn etos 14 5 Programming the Repisterg ue eet EE Co e te 15 DMA Unit PT 15 1 DMA Operation aat qi eed Dre t p Qa ns 15 2 bxterual Requests eese eee hi e r ato dents 15 3 Serial Port DMA Transfer
55. RASI Input with 10k pull up 26 97 UZI Input with 10k pull up 27 98 TXDI Input with 10k pull up 28 99 RXDI Input with 10k pull up 29 96 S6 CLKDI Input with 10k pull up 30 52 INT4 Input with 10k pull up 31 54 INT2 Input with 10k pull up PIO Data 1 Register Offset 7Ah Reset Value 4 3 2 1 0 I I I PDATA 31 16 Bit 15 0 PDATA31 PDATA16 PIO Data Bits These bits PDATA31 PDATA16 are mapped to PIO31 PIO16 which indicate the driven level when the PIO pin is as an output or reflect the external level when the PIO pin is as an input PIO Direction 1 Register Offset 78h Reset Value FFFFh 4 3 2 1 0 I PDIR 31 16 Bit 15 0 PDIR 31 PDIR16 PIO Direction Register Set 1 Configure the PIO pin as an input Set 0 Configure the PIO pin as an output or as normal pin function RDC Semiconductor Co Subject to change without notice 86 Final Version 1 6 January 5 2004 RDC swen o o o R882 PIO Mode 1 Register Offset 76h Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PMODE 31 16 Bit 15 0 PMODE31 PMODE16 PIO Mode Bit The definitions of the PIO pins are configured by the combination of PIO Mode and PIO Direction The PIO pins are programmed individually The definitions PIO Mode PIO Direction for the PIO pin function 0 0 Normal operation 0 1 PIO input with pull up pull down 1 0 PIO output 1 1 PI
56. RDC sses 0 10 1 R882 R8822 16 Bit RISC Microcontroller User s Manual R DC RISC DSP Controller RDC Semiconductor Co Ltd http www rde com tw Tel 886 3 666 2866 Fax 886 3 563 1498 RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 RD CE rrr 20 1 3 1 R882 Contents 1a dT ee 5 2 OG WRIT 6 3 Pin Configuration M 7 3 1 POPP ee e ne ene E E UE EM E 7 3 2 EE E E E E E A E ee 8 3 3 R8822 POFP amp LQFP Pin Out Table iui cousin iR RR aX Ota a M dessa MeL or dq 9 Az Pin DeSCrip tn M 10 4 1 R8822 WO Characteristics of Each PI nip en pU RD bna p e TR Cd bp ot a E eda 16 5 Basic Application System BIOCK sessi trexreo tok ta RENS RE pYRUENS Eo YS NS EXNX SERERE RNV ESRE RIS S KR VN 0 19 6 Read Write Timing Diagram ecce eee ee ee eee eene esten seen eee en e tete e eas teen e eaae een ae 21 7 Crystal Characterisl6 8 nescia ec tes FI SK GRIDIE UA UAR OK AE RNRUIA TREAT MOQURUR RR EXER ENDE NIRE 23 8 EXPCUDUDCD HIE ooo ass paces eas NE EHEREEEERIG INED Po SEP LAE EDU ROAD ERU HEN anes 24 8 1 Ge er l Ress ES o Gassen Sos Hte DG desi e php DEN E Ep Res ERRE 24 8 2 S gment R giSt rS RB TETTE EEE ESERE EON SEEEN EESTE 25 8 3 Instruction Pointer and Status Flags Registers sese 25 8 4 Address CIE TALI
57. Unconditional jump short long 11101011 disp low 9 9 direct within segment 11101001 disp low disp high 9 reg memory indirect within segment 11111111 mod 100 r m 11 16 indirect intersegment 11111111 mod 101 r m mod 11 18 direct intersegment 11101010 segment offset 11 selector Iteration Control LOOP Loop CX times 11100010 disp 7 16 LOOPZ LOOPE Loop while zero equal 11100001 disp 7 16 LOOPNZ LOOPNE Loop while not zero equal 11100000 disp 7 16 JCXZ Jump if CX zero 11100011 disp 7 15 Interrupt INT Interrupt Type specified 11001101 type 41 Type 3 11001100 41 INTO Interrupt on overflow 11001110 43 4 BOUND Detect value out of range 01100010 mod reg r m 21 60 IRET Interrupt return 11001111 31 PROCESSOR CONTROL INSTRUCTIONS CLC clear carry 11111000 2 CMC Complement carry 11110101 2 STC Set carry 11111001 2 CLD Clear direction 11111100 2 STD Set direction 11111101 2 CLI Clear interrupt 11111010 5 STI Set interrupt 11111011 5 HLT Halt 11110100 1 WAIT Wait 10011011 1 LOCK Bus lock prefix 11110000 1 ESC Math coprocessor escape 11011MMM mod PPP r m 1 NOP No operation 10010000 1 SEGMENT OVERRIDE PREFIX CS 00101110 2 SS 00110110 2 DS 00111110 2 ES 00100110 2 RDC Semiconductor Co Subject to change without notice 94 Final Version 1 6 January 5 2004 RDC swam BD 22 R8822 Execution Timings The above instruction timings represent the minimum execution time in clock
58. ank 1 is 3 wait states It should program the wait state bits for bank 0 after the CPU is reset RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 89 RDC swan o R882 20 2 Programmable Refresh Control The DRAM controller provides Self refresh or CAS before RAS refresh control The hardware will auto stop the self refresh operation when the controller accesses the DRAM data during the DRAM in self refresh mode During a refresh cycle the AD bus will drive the address to FFFFFh and the UCS signal will not assert The CPU will enter idle state during a refresh cycle and the idle clock cycle is 7 clocks If two banks of DRAM are being used in a system both banks will be refreshed at the same time The reload counter E2h should be set more than 12h Users should base on the system clock to configure the reload value the normal refresh rate on a DRAM is 15 6us It will start the refresh counter when the EN bit bit 15 of E4h is enabled Referenced wait states amp refresh counter value System clock DRAM Speed Wait States Refresh Cycle Refresh Reload clocks Counter Value 25 MHz 70ns 0 7 186h 33MHz 70ns 1 7 203h 60ns 0 7 203h 40MHz 70ns 2 7 270h 60ns 1 7 270h 50ns 0 7 270h 40ns 0 7 270h Refresh Reload Value Counter Register Offset E2h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 o RC14 RC0 Bit 15 Reserved Bit 14 0 RC14 RCO Refres
59. anks and dual CAS signals supports high byte signal UCAS andlow byte signal LCAS operating mode access When bit 6 of LMCS A2h register is set to 1 bank 0 will be enabled then all the bit definitions of A2h are for bank 0 of the DRAM controller Bit 6 of UMCS AOh is set to 1 then bank 1 is enabled and all bit definitions of AOh are for bank 1 of DRAM controller The memory space of bank 0 is from 00000h to 7FFFFh and the DRAM memory block size is programmable Users can program register A2h LMCS to select memory block size 64k 128k 256k or 512k bytes The memory space of bank 1 is from 80000h to FFFFFh Users can configure register AOh UMCS to select the memory block size to be 64k 128k 256k or 512k bytes The address mapping of MA8 MAO amp Row Column signals DRAM Address Row Address Mapping Column Address Mapping MAO A1 Al A2 MA1 A3 A3 A4 MA2 A5 A5 A6 MA3 A7 A7 A8 MA4 A9 A9 A10 MAS A11 All A12 MA6 A13 A13 Al4 MA7 A15 AI5 AI6 MAS AIT7 A17 A18 BANKO RASO Pin58 UCAS Pin51 LCAS Pin68 WE Pin5 OE Pin6 BANK RASI Pin69 UCAS Pin51 LCAS Pin68 WE Pin5 OE Pin6 The pin numbers are for PQFP configuration 20 1 Programmable Read Write Cycle Time The DRAM Controller read write cycle depends on the external wait state signal ARDY or SRDY and bit 0 and bit 1 of registers AOh and A2h The default wait state of b
60. ars the internal registers amp logic and transfers the address to the reset address FFFFOh 13 XI Input Input to the oscillator amplifier 14 X2 Output Output from the inverting oscillator amplifier Clock output A The CLKOUTA operation is the same as 16 CLKOUTA Output crystal input frequency X1 CLKOUTA remains active during reset and bus hold conditions Clock output B The CLKOUTB operation is the same as 17 CLKOUTB Output crystal input frequency X1 CLKOUTB remains active during reset and bus hold conditions Asynchronous Serial Port Interface Receive data for asynchronous serial port 0 This pin receives l perl pre Cunt asynchronous serial data Transmit data for asynchronous serial port 0 This pin transmits 2 TXDO0 PIO22 Output Input asynchronous serial data from the UART of the micro controllers Ready to send Ready to Receive signal for asynchronous serial port 0 When the RTSO bit in the AUXCON register is set and 3 RTSO RTRO PIO20 Output Input the FC bit in the serial port 0 control register is set the RTSO signal is enabled Otherwise when the RTSO bit is cleared and the FC bit is set the RTRO signal is enabled Clear to send Enable Receiver Request signal for asynchronous serial port 0 When the ENRXO bit in the AUXCON register is 100 CTS0 ENRXO0 PIO21 Input Output cleared and the FC bit in the serial port 0 control register is set the CTSO signal is enabled Otherwise when the ENRXO bit is set and the FC bit is set the
61. asserted low the microcontroller receives data When DT R is asserted high the microcontroller writes data to the data bus 49 DENPIOS5 Output Input Data enable This pin is provided as a data bus transceiver output enable DEN is asserted during memory and I O accesses DEN is driven high when DT R changes states It is floating during bus hold or reset conditions 96 S6 CLKDIV2 PIO29 Output Input Bus cycle status bit6 clock divided by 2 For the S6 feature this pin is set to low to indicate a microcontroller initiated bus cycle or high to indicate a DMA initiated bus cycle during T2 T3 Tw and T4 For CLKDIV2 feature The internal clock of microcontroller is the external clock divided by 2 CLKOUTA CLKOUTB X1 2 if this pin held low during power on reset The pin is sampled on the rising edge of RST 97 UZI PIO26 Output Input Upper zero indication This pin is the logical OR of the inverted A19 A16 It is asserted in the T1 and is held throughout the cycle Chip Select Unit Interface 50 51 68 69 MCSO0 PIO14 MCSI UCAS PIO15 MCS2 LCAS PIO24 MCS3 RASI PIO25 Output Input Midrange memory chip selects For MCS feature these pins are active low when the MMCS register is enabled to access a memory The address ranges are programmable MCS3 MCSO are held high during bus holds RDC Semiconductor Co Subject to change without notice Final V
62. atus Register is set an interrupt will occur Set 1 Enable the Interrupt Set 0 Disable the interrupt Bit 7 RXIE Receive Data Ready Interrupt Enable When the receiver buffer contains valid data the RDR bit in Status Register is set it will generate an interrupt Set 1 Enable the Interrupt Set 0 Disable the interrupt Bit 6 TMODE Transmit Mode Set 1 Enable the TX machines Set 0 Disable the TX machines Bit 5 RMODE Receive Mode Set 1 Enable the RX machines Set 0 Disable the RX machines Bit 4 EVN Even Parity This bit is valid only when the PE bit is set Set 1 the even parity checking is enforced even number of 1s in frame RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 81 RDC 0 0 R882 Set 0 odd parity checking is enforced odd number of 1s in frame Bit 3 PE Parity Enable Set 1 Enable the parity checking Set 0 Disable the parity checking Bit 2 0 MODE Mode of Operation bit 2 bit 1 bit 0 MODE Data Bits Parity Bits Stop Bits 0 0 1 Mode 1 Tor 8 1 or 0 1 0 1 0 Mode 2 9 N A 1 0 1 1 Mode 3 8 or 9 1 or 0 1 1 0 0 Mode 4 7 N A 1 Serial Port 0 Status Register Offset 82h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I Reserved BRK1 BRKO RB8 RDR THRE FER OER PER TEMT HSO Res The Serial Port 0 Status Register provides information about the
63. cial Execution nous Serial ats HLDA lt Unit Logic Unit Portl S6 CLEDIV2 lt gt Adder L RXD1 UZI lt gt BSF Ya A19 A0 MA8 MAO v Vine ADi5 ADO Wy V_ wie ALE WR BHE ADEN RDC Semiconductor Co Subject to change without notice Final Version 1 6 January 5 2004 R D C 2 RISC DSP Controller 3 Pin Configuration 3 1 POFP RXD0 PIO23 TXD0 P1IO22 RTSO RTR0 PIO20 BHE ADEN WR RD ALE ARDY S2 BWSEL X2 VCC CLKOUTA CLKOUTB GND A19 PIO9 A18 PIO8 vee A17 MA8 PIO7 A16 A15 MA7 A14 A13 MA6 A12 A11 MA5 A10 A9 MA4 100 1 CTS0 ENRX0 PIO21 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 97 L1 UZI PIO26 96 S6 CLKDIV2 P1029 95 AD15 99 RXD1 PIO28 98 TXD1 PIO27 94 AD7 93 AD14 92 vec 91 AD6 90 AD13 89 1 GND ss AD5 87 L 1 AD12 86 AD4 85 AD11 84 AD3 83 1 AD10 82 AD2 81 AD9 R8822 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 47 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 46 48 A4 A2 vec A1 MAO AO GND WHB WLB HLDA HOLD SRDY PIO6 A8 A7 MA
64. consists of a 16 bit segment and 16 bit offset The Physical Address Generation figure describes how the logical address is transferred to the physical address Shift left 4 bits Segment Base Logical Address Offset Physical Address TO Memory Physical Address Generation RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 27 R D C 2 RISC DSP Controller 9 Peripheral Control Block Registers R8822 The peripheral control block can be mapped into either memory or I O space by programming the FEh register And it starts at FFOOh in I O space when the microprocessor is reset The following table is the definitions of all the peripheral Control Block Registers and the detailed descriptions will be arranged on the related Block Unit E Register Name Page aS Register Name Page FE Peripheral Control Block Relocation Register 29 66 Timer 2 Mode Control Register 74 FA Disable Peripheral Clock Register 32 62 Timer 2 Maxcount Compare A Register 75 F6 Reset Configuration Register 34 60 Timer 2 Count Register 75 F4 Processor Release Level Register 29 SE Timer 1 Mode Control Register 73 F2 Auxiliary Configuration Register 39 5C Timer 1 Maxcount Compare B Register 74 F0 Power Save Control Register 31 5A Timer 1 Maxcount Compare A Register 74 E6
65. ct to change without notice 22 Final Version 1 6 January 5 2004 R D C 2 RISC DSP Controller T Crystal Characteristics For fundamental mode crystal Reference values Frequency 10 8288MHz 19 66MHz 30MHz 33MHz 40MHz Rf None None None None None Cl 10Pf 10Pf None None None C2 10Pf 10Pf 10Pf 10Pf 10Pf C3 None None None None None L None None None None None For third overtone mode crystal Reference values Frequency 22 1184MHz 28 322MHz 33 177MHz 40MHz Rf 1M 1 5M 1 5M 1 5M Cl 15Pf 15Pf 15Pf 15Pf C2 30Pf 30Pf 30Pf 30Pf C3 None 220Pf 220Pf 220Pf L None 10uL 4 7uL 2 7uL R8822 Final Version 1 6 January 5 2004 RDC Semiconductor Co Subject to change without notice 23 RDC 0 R882 8 Execution Unit 8 1 General Registers The R8822 has eight 16 bit general registers And the AX BX CX and DX can be subdivided into two 8 bit registers AH AL BH BL CH CL DH and DL The functions of these registers are described as follows AX Word Divide Word Multiply Word I O operation AL Byte Divide Byte Multiply Byte I O Decimal Arithmetic Translate operation AH Byte Divide Byte Multiply operation BX Translate operation CX Loops String operation CL Variable Shift and Rotate operation DX Word Divide Word Multiply Indirect I O operation SP Stack operations POP POPA POPF PUSH PUSHA PUSHF BP Genera
66. current status of the serial port 0 Bit 15 11 Reserved Bit 10 BRK1 Long Break Detected This bit should be reset by software When a long break is detected this bit will be set high Bit 9 BRKO Short Break Detected This bit should be reset by software When a short break is detected this bit will be set high Bit 8 RB8 Received Bit 8 This bit should be reset by software This bit contains the ninth data bit received in mode 2 and mode 3 Bit 7 RDR Received Data Ready Read only The Received Data Register contains valid data This bit is set high and can only be reset by reading the Serial Port 0 Receive Register Bit 6 THRE Transmit Hold Register Empty Read only When the Transmit Hold Register is ready to accept data this bit will be set This bit will be reset when data is written to the Transmit Hold Register Bit 5 FER Framing Error detected This bit should be reset by software This bit is set when a framing error is detected Bit 4 OER Overrun Error Detected This bit should be reset by software This bit is set when an overrun error is detected Bit 3 PER Parity Error Detected This bit should be reset by software This bit is set when a parity error for mode 1 and mode 3 is detected Bit 2 TEMT Transmitter Empty This bit is read only RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 82 RDC recone 50 O R882 When the Transmit Shift Register is empty this bit
67. d Set 0 external ready is required Bit 1 0 R1 R0 Wait State value The R1 and RO determine the number of wait states inserted into a PCS5 PCS6 access RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 43 RDC swen o o o R882 R1 RO 1 1 3 wait states 1 0 2 wait states 0 1 1 wait state 0 0 0 wait state 13 4 PCSx In order to define these pins the peripheral or memory chip selects are programmed through A4h and A8h register The base address memory block can be located anywhere within the 1M byte memory space exclusive of the areas associated with the UCS LCS and MCS chip selects If the chip selects are mapped to I O space the access range is 64k bytes PCS6 PCS5 can be configured from 0 wait state to 3 wait states PCS3 PCSO can be configured from 0 wait state to 15 wait states Peripheral Chip Select Register Offset A4h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 15 7 BA19 BA11 Base Address BA19 BA11 correspond to bit 19 11 of the 1M byte 20 bits programmable base address of the PCS chip select block When the PCS chip selects are mapped to I O space BA19 BA16 must be written to 0000b because the I O address bus is only 64K bytes 16 bits wide PCSx address range PCSO Base Address Base Address 255 PCSI Base Address 256 Base Address 511 PCS2 Base Address 512 Base Address 76
68. e Bit 15 8 Reserved Bit 7 ETM Edge trigger mode enable When this bit is set to 1 and bit 4 set to 0 an interrupt is triggered by an edge which goes from low to high The low to high edge will be latched one level till this interrupt is serviced Bit 6 SFNM Special Fully Nested Mode Set 1 Enable the special fully nested mode of INT1 Bit 5 C Cascade Mode Set this bit to 1 to enable the cascade mode for INT1 or INTO Bit 4 LTM Level Triggered Mode Set 1 An interrupt is triggered by high active level Set 0 An interrupt is triggered by the low to high edge Bit 3 MSK Mask Set 1 Mask the interrupt source of INTI Set 0 Enable the INTI interrupt Bit 2 0 PR Interrupt Priority These bit settings for priority selection are the same as those of bit 2 0 of Register 44h INT1 Control Register Offset 3Ah Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 presen e Slave Mode This register is for timer 2 interrupt control reset value is 0000h Bit 15 4 Reserved Bit 3 MSK Mask Set 1 Mask the interrupt source of Timer 2 Set 0 Enable the Timer 2 interrupt Bit 2 0 PR Interrupt Priority These bit settings for priority selection are the same as those of bit 2 0 of Register 44h INTO Control Register Offset 38h Reset Value 000Fh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 presen erm sen o ima us ene ens Pro RDC Semiconductor Co Final Version 1 6 Subject to change without notice Jan
69. ect Register 40 2A Priority Mask Register 59 88 Serial Port 0 Baud Rate Divisor Register 83 28 interrupt Mask Register 60 86 Serial Port 0 Receive Register 83 26 Poll Status Register 61 84 Serial Port 0 Transmit Register 83 24 Poll Register 61 82 Serial Port 0 Status Register 82 22 _ End of Interrupt Register 62 80 Serial Port 0 Control Register 80 20 interrupt Vector Register 62 7A PIO Data 1 Register 86 18 Serial port 1 baud rate divisor 84 78 PIO Direction 1 Register 86 16 Serial port 1 receive register 84 76 PIO Mode 1 Register 87 14 Serial port 1 transmit register 84 74 PIO Data 0 Register 87 12 Serial port 1 status register 84 72 PIO Direction 0 Register 87 10 Serial port 1 control register 84 70 PIO Mode 0 Register 88 RDC Semiconductor Co Subject to change without notice 28 Final Version 1 6 January 5 2004 RDC swen o o o o O R882 Peripheral Control Block Relocation Register Offset FEh Reset Value 20FFh 15 14 1 11 10 9 8 7 6 5 4 3 2 1 0 es 3 12 The peripheral control block is mapped into either memory or I O space by programming this register When the other chip selects PCSx or MCSx are programmed to zero wait state and ignore the external ready the PCSx or MCSx can overlap the control block Bit 15 Reserved Bit 14 S M Slave Master Configures the interrupt controller Set 0 Master mode Set 1 Slaved mode Bit 13 Reserved Bit 12 M IO Memory IO space At reset this bit is
70. ectly WLB ies ae BUS HOLD LEAVE WAVEFORM 12 5 Bus Width The R8822 default is 16 bit bus access and the bus can be programmed as 8 bit or 16 bit access when memory or I O access is located inthe LCS MCSx or PCSx address space The UCS code fetched selection can be 8 bit or 16 bit bus width which is decided by the S2 BWSEL pin input status as the RST pin goes from low to high When the S2 BWSEL pin is with a pull low resistor the code fetched selection is 8 bit bus width The DRAM bus width is 16 bits which cannot be changed RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 38 RDC BBR Auxiliary Configuration Register Offset F2h Reset Value 0000h 15 14 13 12 11 10 9 8 7 5 3 2 1 0 Bit 15 8 Reserved NRX1 o NRX0 gt E E Bit 7 USIZ Boot code bus width This bit reflects the S2 BWSEL pin input status when RST pin goes from low to high Set 0 16 bit bus width booting when S2 BWSEL pin is without a pull low resistor Set 1 8 bit bus width booting when S2 BWSEL pin is with a 330 ohm pull low resistor Bit 6 ENRXI Enable the Receiver Request of Serial port 1 Set 1 The CTSI ENRXI pin is configured as ENRXI Set 0 The CTSI ENRXI pin is configured as CTSI Bit 5 RTS1 Enable Request to Send of Serial port 1 Set 1 The RTRI RTSI pin is configured as RTSI Set 0 The RTRI RTSI pin is configured as RTRI Bit 4 ENRXO Enable the Receiver R
71. egister Offset A8h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 15 Reserved Bit 14 8 M6 M0 MCS Block Size These bits determine the total block size for the MCS3 MCSO chip selects Each individual chip select is active for one quarter of the total block size For example if the block size is 32K bytes and the base address is located at 20000h the individual active memory address range of MCS3 to MCS0is MCSO 20000h to 21FFF MCS1 22000 to 23FFFh MCS2 24000h to 25FFFh MCS3 26000h to 27FFFh MCSx total block size is defined by M6 MO M6 M0 Total block size MCSx _address active range 0000001b 8k 2k 0000010b 16k 4k 0000100b 32k 8k 0001000b 64k 16k 0010000b 128k 32k 0100000b 256k 64k 1000000b 512k 128k Bit 7 EX Pin Selector This bit configures the multiplexed output which the PCS6 PCSS5 pins as chip selects or A2 A1 Set 1 PCS6 and PCS5 are configured as peripheral chip select pins Set 0 PCS6 is configured as address bit A2 and PCS5 is configured as Al Bit 6 MS Memory or I O space Selector Set 1 The PCSx pins are active for memory bus cycle Set 0 The PCSx pins are active for I O bus cycle Bit 5 3 Reserved Bit 2 R2 Ready Mode This bit is configured to enable disable the wait states inserted for the PCS5 PCS6 chip selects The R1 and RO bits of this register determine the number of wait state to insert Set 1 external ready 1s ignore
72. emented by 2 after each transfer Set 0 The address is incremented or decremented by 1 after each transfer RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 65 RDC swan o o R882 DMAO Transfer Count Register Offset C8h DMAO Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC15 TCO Bit 15 0 TC15 TCO DMA 0 transfer Count The value of this register is decremented by 1 after each transfer DMAO Destination Address High Register Offset C6h DMAO Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 15 4 Reserved Bit 3 0 DDA19 DDA106 High DMA 0 Destination Address These bits are mapped to A19 A16 during a DMA transfer when the destination address is in memory space or I O space If the destination address is in I O space 64Kbytes these bits must be programmed to 0000b DMAO Destination Address Low Register Offset C4h DMAO Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DDA15 DDAO Bit 15 0 DDA15 DDAO Low DMA 0 Destination Address These bits are mapped to A15 AO during a DMA transfer The value of DDA19 DDAO will be incremented or decremented by 2 after each DMA transfer DMAO Source Address High Register Offset C2h DMAO Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DSA19 DSA16 Bit 15 4 Reserved Bit 3 0 DSA19 DSA16 High DMA 0 Source Address These bits are mapped to A19 A16 during a DMA transfer when
73. equest of Serial port 0 Set 1 The CTS0 ENRXO pin is configured as ENRXO Set 0 The CTS0 ENRXO pin is configured as CTSO Bit 3 RTSO Enable Request to Send of Serial port 0 Set 1 The RTRO RTSO pin is configured as RTSO Set 0 The RTRO RTSO pin is configured as RTRO Bit 2 LSIZ LCS Data Bus Size selection This bit cannot be changed while it is executed from the LCS space or while the Peripheral Control Block is overlaid with PCS space Set 1 8 bit data bus access when the memory access is located in the LCS memory space Set 0 16 bit data bus access when the memory access is located in the LCS memory space Bit 1 MSIZ MCSx and PCSx Memory Data Bus Size selection This bit cannot be changed while it is executed from the associated address space or while the Peripheral Control Block is overlaid on this address space Set 1 8 bit data bus access when the memory access is located in the selection memory space Set 0 16 bit data bus access when the memory access is located in the selection memory space Bit 0 IOSIZ I O Space Data Bus Size selection This bit determines the width of the data bus for all I O space accesses Set 1 8 bit data bus access Set 0 16 bit data bus access RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 39 RDC swam 0 0 R882 13 Chip Select Unit The Chip Select Unit provides 12 programmable chip select pins to access a specific memory or perip
74. ernal interrupt Two independent DMA channels Programmable chip select logic for Memory or I O bus cycle decoder Programmable wait state generator With 8 bit or 16 bit Boot ROM bus size RDC Semiconductor Co Subject to change without notice Final Version 1 6 January 5 2004 R D C i RISC DSP Controller 2 Block Diagram R8822 INT2 INTAO INT1 SELECT CLKOUTA INT3 INTA1 IRQ TMROUTO TMROUT1 Hai DRSI Tar A CLKOUTB SEES INTO NMI TMRINO A rMRIN1 A E ia jmi i vvv i i i i Y Y x1 x2 Clock and Interrupt Timer Control DMA vec Power Control Unit Unit Unit GND Management RST gt LCS ONCE0 Y RASO lt gt Chip UCS ONCEL lt gt Select Inscruction TCS lt Unit Queue 64bits MCSI UCAS 4 MCS2 LCAS 4 F lt 4 DRAM Instruction Micro PIO MCS3 RAS1 Control Decoder ROM KE P1031 P100 PCS5 A1 BILE L Unit PCS6 A2 amp Unit Control Signal Register gt EA LA File Address P RTSO0 RTRO Refresh General Asynchro CTSO ENRXO ARDY J Control Segment nous Serial SRDY gt p it Eflag Register Port0 J gt TxDd TL SZ BWSEL I K RxDO 51 50 DT R amp P RTSI RTR DEN lt Bus pegs Asynchro LA CTSI ENRXT HOLD J Interface Spe
75. ersion 1 6 January 5 2004 13 RDC soom 20 0 R882 When the bit6 of UMCS AOh register is set to 1 the UCS will be disabled and the MCS3 MCSI will be activated as bankl control signals RASI LCAS and UCAS of DRAM controller The DRAM memory is located from 80000h to FFFFFh Upper memory chip select ONCE mode request 1 For UCS feature this pin acts low when the system accesses the defined portion memory block of the upper 512K bytes 80000h FFFFFh memory region UCS default active address region is from F0000h to FFFFFh after power on 57 UCS ONCEI Output Input reset The address range for UCS is programmed by software For ONCEI feature If ONCEO and ONCEI are sampled low on the rising edge of RST The microcontroller enters ONCE mode In ONCE mode all pins are high impedance This pin incorporates a weakly pulled up resistor Lower memory chip select ONCE mode request 0 For LCS feature this pin acts low when the microcontroller accesses the defined portion memory block of the lower 512K 00000h 7FFFFh memory region The address range for LCS is programmed by software For ONCEO feature see UCS ONCEI description This pin incorporates a weakly pulled up resistor When the bit 6 of LMCS A2h register is set to 1 this pin will actas RASO which is the raw address of DRAM bank 0 Peripheral chip selects latched address bit For PCS feature these pins act low when the microcontroller acc
76. es the incremented value which is by 1 or 2 Set 0 Disable the increment function Bit 9 TC Terminal Count Set 1 The synchronized DMA transfer is terminated when the DMA transfer count register reaches 0 Set 0 The synchronized DMA transfer is terminated when the DMA transfer count register reaches 0 Unsynchronized DMA transfer is always terminated when the DMA transfer count register reaches 0 regardless the setting of this bit Bit 8 INT Interrupt Set 1 DMA unit generates an interrupt request when the transfer count is complete The TC bit must be set to to generate an interrupt Bit 7 6 SYN1 SYNO Synchronization Type Selection SYN1 SYNO Synchronization Type 0 0 Unsynchronized 0 1 Source synchronized 1 0 Destination synchronized 1 41 Reserved Bit 5 P Priority Set 1 It selects high priority for this channel when both DMA 0 and DMA 1 are transferred in the same time Bit 4 TDRQ Timer Enable Disable Request Set 1 Enable the DMA requests from timer 2 Set 0 Disable the DMA requests from timer 2 Bit 3 EXT External Interrupt Enable bit Set 1 The external pin is an interrupt pin DMAO function is disabled Set 0 The external pin is DRQ pin Bit 2 CHG Changed Start Bit This bit must be set to 1 when the ST bit is modified Bit 1 ST Start Stop DMA channel Set 1 Starts the DMA channel Set 0 Stops the DMA channel Bit 0 B W Byte Word Select Set 1 The address is incremented or decr
77. esses the fifth or sixth region of the peripheral memory I O or memory 58 LCS ONCEO RASO Output Input space The base address of PCS is programmable These 59 PCS6 A2 PIO2 Output Input pins are asserted with the AD address bus and are not 60 PCS5 A1 PIO3 floating during bus holds For latched address bit feature These pins output the latched address A2 and Al when the EX bit inthe PCS and MCS auxiliary register is cleared The A2 and A1 retain previous latched data during bus holds Peripheral chip selects These pins act low when the microcontroller accesses the defined memory area of the 62 PCS3 RTS1 RTR1 PIO19 peripheral memory block I O or memory address For I O accessed the base address can be programmed in the region i PES oy ENBA HEIDIS Output Input from 00000h to OFFFFh 65 PCSI P 1017 For memory address accesses the base address can be 66 PCSO PIO16 located in the 1M byte memory address region These pins are asserted with the multiplexed AD address bus and are not floating during bus holds Interrupt Control Unit Interface Non maskable Interrupt The NMI is the highest priority hardware interrupt and is non maskable When this pin is asserted NMI transition from low to high the Kd MI Input microcontroller always transfers the address bus to the location specified by the non maskable interrupt vector in the microcontroller interrupt vector table T
78. evel till this interrupt is serviced Bit 4 LTM Level Triggered Mode Set 1 An interrupt is triggered by high active level Set 0 An interrupt is triggered by the low to high edge Bit 3 MSK Mask Set 1 Mask the interrupt source of INT3 Set 0 Enable the INT3 interrupt Bit 2 0 PR Interrupt Priority These bit settings for priority selection are the same as those of bit 2 0 of Register 44h INT2 Control Register Offset 3Ch Reset Value 000Fh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 o mee erm Rested imm msk pre ero Master Mode Bit 15 8 bit 6 5 Reserved Bit 7 ETM Edge trigger mode enable When this bit is set to 1 and bit 4 set to 0 an interrupt is triggered by an edge which goes from low to high The low to high edge will be latched one level till this interrupt is serviced Bit 4 LTM Level Triggered Mode Set 1 An interrupt is triggered by high active level Set 0 An interrupt is triggered by the low to high edge Bit 3 MSK Mask Set 1 Mask the interrupt source of INT2 Set 0 Enable the INT2 interrupt Bit 2 0 PR Interrupt Priority These bit settings for priority selection are the same as those of bit 2 0 of Register 44h RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 52 RDC swen o o R882 INT1 Control Register Offset 3Ah Reset Value 000Fh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 present erm sen o im ue ene eni Pro Master Mod
79. following table shows the interrupt vector addresses type and the priority The maskable interrupt priority can be changed by programming the priority registers The Vector addresses for each interrupt are fixed Interrupt source Interrupt Vector EOI Priority Note Type Address Type Divide Error Exception 00h 00h 1 Trace interrupt Olh 04h 1 1 NMI 02h 08h 1 2 ke Breakpoint Interrupt 03h OCh 1 INTO Detected Over Flow Exception 04h 10h 1 Array Bounds Exception 05h 14h 1 Undefined Opcode Exception 06h 18h 1 ESC Opcode Exception 07h 1Ch 1 Timer 0 08h 20h 08h 2 1 sed Reserved 09h DMA O INTS 0Ah 28h OAh 3 7 DMA I INT6 O0Bh 2Ch OBh 44 INTO OCh 30h OCh 5 INTI O0Dh 34h ODh 6 INT2 OEh 38h OEh 7 INT3 OFh 3Ch OFh 8 INT4 10h 40h 10h 9 Asynchronous Serial port 1 11h 44h llh 9 Timer 1 12h 48h 08h 2 2 TS Timer 2 13h 4Ch 08h 2 3 FRF Asynchronous Serial port 0 14h 50h 14h 9 Reserved 15h 1Fh Note When the interrupt occurs in the same time the priority is 1 1 gt 1 2 2 1 gt 2 2 gt 2 3 Note The interrupt types of these sources are programmable in slave mode 14 3 Interrupt Requests When an interrupt is requested the internal interrupt controller verifies the interrupt is enabled the IF flag is enabled no MSK bit set and that there are no higher priority interrupt requests being serviced or pending If the interrupt
80. h Counter Reload Value The counter value should be set more than 12h Refresh Counter Register Offset E4h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 15 EN Set 1 to enable refresh counter unit This bit will be cleared to 0 after hardware reset Bit 14 0 T14 T0 Refresh Count Read only bits and these bits present value of the down counter which triggers refresh requests RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 R D C e R8822 21 Instruction Set OPCodes and Clock Cycles Function Format Clocks Notes DATA TRANSFER INSTRUCTIONS MOV Move register to register memory 1000100w mod reg r m 1 1 register memory to register 1000101w mod reg r m 1 6 immediate to register memory 1100011w mod 000 r m data data if w 1 1 1 immediate to register lOllwreg data data if w 1 1 memory to accumulator 1010000w addr low addr high 6 accumulator to memory 1010001w jaddr low addr high 1 register memory to segment register 10001110 mod 0 reg r m 3 8 segment register to register memory 10001100 mod 0 reg r m 2 2 PUSH Push memory 11111111 mod 110 r m 8 register 01010 reg 3 segment register 000reg110 2 immediate 011010s0 data data if s 0 1 POP Pop memory 10001111 mod 000 r m 8 register 01011 reg 6 segment register 000 reg 111 reg 01 8 PUSHA Push all 01100000 36 POPA Pop all 01100001 44 XCHG Exchange register memory 1000011w mod reg r
81. haraeteris Diog esee risate Passa a e etii alea tae et E asino dE ad 96 24 AC ChargtfeFisll6s n ooihicooe horae f aei t eI esi aco didi idet scches ide esters ee ded 97 25 Thermal Characteristics cciiccssisccsksseccucsstceassseventcsccacecdesssasseeaschecwacsvevssssdesetssecectes 111 26 Package Information eR c c 112 26 1 POEP soccer ec ceni scs eoa nd ecd denas teen eco uns eeu m D Dese 112 26 2 1561 NT c 113 27 Revision History ssessoessoescoesocesocesscesscesseesocesocesoeesoeesoeecoescoesocesocescooesseeeseesseess 114 RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 R D C li RISC DSP Controller R8822 16 Bit Microcontroller with 8 bit or 16 bit dynamic external data bus 1 Features Five stage pipeline RISC architecture Static Design amp Synthesizable design Bus interface Multiplexed address and Data bus Supports non multiplexed address bus A 19 0 8 bit or 16 bit external bus dynamic access M byte memory address space 64K byte I O space Software is compatible with the 80C186 microprocessor Supports two Asynchronous serial channels with hardware handshaking signals Support CPU ID Supports 32 PIO pins Supports 64kx16 128kx16 256kx16 EDO or FP DRAM with auto refresh control Three independent 16 bit timers and one independent programmable watchdog timer The Interrupt controller with seven maskable external interrupts and one non maskable ext
82. have time to de assert its DRQ signal Fetch Cycle Fetch Cycle T1 T2 T3 T4 T1 T2 T3 T4 TI TI CLKOUTA DRQ Case1 DRQ Case2 ul o QE NETES Case1 Current destination synchronized transfer will not be immediately followed by another DMA transfer Case2 Current destination synchronized transfer will be immediately followed by another DMA transfer Destination Synchronized Transfers RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 69 RDC swam 4B 15 3 Serial Port DMA Transfer The serial port data can be DMA transfer to or from memory or IO space And the B W bit of DMA control Register must be set to 1 for byte transfer The map address of Transmit Data Register is written to the DMA Destination Address Register and the memory or I O address is written to the DMA Source Address Register when the data are transmitted The map address of Receive Data Register is written to the DMA Source Address Register and the memory or I O address is written to the DMA Destination Address Register when the data are received Software is used to program the Serial Port Control Register to perform the serial port DMA transfer When a DMA channel is in use by a serial port the corresponding external DMA request signal is deactivated For DMA to the serial port the DMA channel should be configured as being destination synchronized For DMA from the serial port the DMA cha
83. he EOI register Bit 15 11 Reserved Bit 10 SPO Serial Port 0 Interrupt In Service Set 1 the serial port 0 interrupt is currently being serviced Bit 9 SP1 Serial Port 1 Interrupt In Service Set 1 the serial port 1 interrupt is currently being serviced Bit 8 4 14 10 Interrupt In Service Set 1 the corresponding INT interrupt is currently being serviced Bit 3 2 D1 I6 D0 I5 DMA Channel or INT Interrupt In Service Set 1 the corresponding DMA channel or INT interrupt is currently being serviced Bit 1 Reserved Bit 0 TMR Timer Interrupt In Service Set 1 the timer interrupt is currently being serviced RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 58 RDC swan o o R882 Interrupt In Service Register Offset 2Ch Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Slave Mode The bits in the In Service register are set by the interrupt controller when the interrupt is taken The in service bits are cleared by writing to the EOI register Bit 15 6 Reserved Bit 5 4 TMR2 TMRI Timer2 Timerl Interrupt In Service Set 1 the corresponding timer interrupt is currently being serviced Bit 3 2 D1 I6 D0 I5S DMA Channel or INT Interrupt In Service Set 1 the corresponding DMA Channel or INT Interrupt is currently being serviced Bit 1 Reserved Bit 0 TMRO Timer 0 Interrupt In Service Set 1 the Timer 0 interrupt is currently being serviced Priority Mask Register
84. he NMI pin must be RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 14 RDC 2310 1n R882 asserted for at least one CLKOUTA period to guarantee that the interrupt is recognized Maskable interrupt request 4 Active high This pin indicates that an interrupt request has occurred The microcontroller will jump to the INT4 address vector to execute the service 52 INT4 PIO30 Input Output routine if the INT4 is enabled The interrupt input can be configured to be either edge or level triggered The requesting device must hold INT4 until the request is acknowledged to guarantee interrupt recognition Maskable interrupt request 3 interrupt acknowledge l slave interrupt request For INT3 feature except the differences in the interrupt line and interrupt address vector the function of INT3 is the same as that of INT4 53 INT3 INTAI IRQ Input OutputlFor INTAI feature in cascade mode or special fully nested mode this pin corresponds to INTI For IRQ feature when the microcontroller is as a slave device this pin issues an interrupt request to the master interrupt controller Maskable interrupt request 2 interrupt acknowledge 0 For INT2 feature except the differences in interrupt line and interrupt address vector the function of INT2 is the same as 54 INT2 INTAO PIO31 Input Output that of INT4 For INTAO feature in cascade mode or special fully nested mode this
85. heral device The chip selects are programmed through five peripheral control registers AOh A2h A4h A6h A8h and all the chip selects can be inserted wait states in by programming the peripheral control register 13 1 UCS The UCS default is active on reset for code access The memory active range is upper 512k 80000h FFFFFh which is programmable And the default memory active range of UCS is 64k F0000h FFFFFh The UCS is active to drive low four CLKOUTA oscillators if no wait state is inserted There are three wait states inserted into UCS active cycle on reset Upper Memory Chip Select Register Offset AOh Reset Value FO3Bh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 LB2 LBO 0 0 0 0 oa lue 1 1 1 E R1 RO Bit 15 Reserved Bit 14 12 LB2 LB0 Memory block size selection for UCS chip select pin The active range ofthe UCS chip select pin can be configured by the LB2 LBO The default memory block size is from F0000h to FFFFFh LB2 LB1 LBO Memory Block size Start address End Address l 1 X 2 4 F0000h FFFFFh lo 1 0 Gee 128k E0000h FFFFFh 1 0 0 se 256k C0000h FFFFFh 0 0 0 e 512k 80000h FFFFFh Bit 11 8 Reserved Bit 7 DA Disable Address Ifthe BHE ADEN pin is held high on the rising edge of RST the DA bit is valid to enable disable the address phase of the AD bus If the BHE ADEN pin is held low on the rising edge of RST the AD bus al
86. hibited from counting The INH bit must be set to 1 when the EN bit is written and the INH and EN bits must be in the same write Bit 14 INH Inhibit Bit This bit allows selective updating the EN bit The INH bit must be set to 1 when the EN is written and both the INH and EN bits must be in the same write This bit is not stored and always read as 0 Bit 13 INT Interrupt Bit Set 1 An interrupt request is generated when the count register equals a maximum count If the timer is configured in RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 71 RDC 0 n R882 dual max count mode an interrupt is generated each time the count reaches max count A or max count B Set 0 Timer 0 will not issue interrupt requests Bit 12 RIU Register in Use Bit Set 1 The Maxcount Compare B register of timer 0 is being used Set 0 The Maxcount Compare A register of timer 0 is being used Bit 11 6 Reserved Bit 5 MC Maximum Count Bit When the timer reaches its maximum count the MC bit will be set to 1 by H W In dual maxcount mode this bit is set each time either Maxcount Compare A or Maxcount Compare B register is reached This bit is set regardless of the INT bit 56h 13 Bit 4 RTG Re trigger Bit This bit defines the control function by the input signal of TMRINO pin When EXT 1 56h 2 this bit is ignored Set 1 Timer0 Count Register 50h counts internal events Reset the counting on every TMRIN
87. his mode the timer counts to the value contained in Maxcount Compare A and reset to 0 Then the timer counts to Maxcount Compare A again Maxcount Compare B is not used in this mode Bit 0 CONT Continuous Mode Bit Set 1 The timer runs continuously RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 72 RDC swen o o R882 Set 0 The timer will halt after each counting to the maximum count and the EN bit will be cleared Timer 0 Count Register Offset 50h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC15 TCO Bit 15 0 TC15 TCO Timer 0 Count Value This register contains the current count of timer 0 The count is incremented by one every four internal processor clocks or pre scaled by timer 2 or incremented by one every external clock which is through configuring the external clock select bit based on the TMRINO signal Timer 0 Maxcount Compare A Register Offset 52h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC15 TCO Bit 15 0 TC15 TCO Timer 0 Compare A Value Timer 0 Maxcount Compare B Register Offset 54h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I I I I TC15 TCO Bit 15 0 TC15 TCO Timer 0 Compare B Value Timer 1 Mode Control Register Offset 5Eh Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w eu o o ojeo o o wcjno e ex ar cor These bit definition
88. is the logicOR of WR and AO This pin is floating during reset or bus holds 44 HLDA Output Bus hold acknowledge Active high The microcontroller will issue an HLDA in response to a HOLD request by external bus master at the end of T4 or Ti When the microcontroller is in hold status HLDA is high AD15 ADO A19 A0 WR RD DEN S0 SI S6 BHE DT R WHB and WLB are floating and UCS LCS PCS6 PCSS MCS3 MCSO and PCS3 PCSO will be driven high After HOLD is detected as being low the microcontroller will lower HLDA 45 HOLD Input Bus Hold request Active high This pin indicates that another bus master is requesting the local bus 46 SRDY PIO6 Input Output Synchronous ready This pin performs the microcontroller that the address memory space or I O device will complete a data transfer The SRDY pin accepts a falling edge that is asynchronous to CLKOUTA and is active high SRDY is accomplished by elimination of the one half clock period required to internally synchronize ARDY Tie SRDY high so the microcontroller is always asserted in the ready condition If the SRDY is not used tie this pin low to yield control to ARDY Both SRDY and ARDY should be tied to high if the system need not assert wait states by externality 48 DT R PIO4 Output Input Data transmit or receive This pin indicates the direction of data flow through an external data bus transceiver When DT R is
89. ister 86h 16h 8 pit 8 bit Receive Buffer 8 bit Receive Shift Register Transmit Hold Register Interrupt Request RTS ENRX crs RTR lt gt Control Register 80h 10h Control bid Status Register 82h 12h ac Pee Baud Rate Divisor Register 88h 18h RXD Serial Port Block Diagram 18 1 Serial Port Flow Control The two serial ports are provided with two data pins RXD and TXD and two flow control signals RTS and RTR Hardware flow control is enabled when the FC bit in the Serial Port control Register is set And the flow control signals are configured by software to support several different protocols RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 78 RDC 4 R882 18 1 1 DCE DTE Protocol The R8822 can be as a DCE Data Communication Equipment or as a DTE Data Terminal Equipment This protocol provides flow control where one serial port is receiving data and the other serial port is sending data To implement the DCE device the ENRX bit should be set and the RTS bit should be cleared for the associated serial ports To implement the DTE device the ENRX bit should be cleared and the RTS bit should be set for the associated serial ports The ENRX and RTS bits are in the register F2h The DCE DTE protocol is asymmetric interface since the DTE device cannot signal the DCE device that 1s ready to receive data and the DCE cannot send
90. ister to either 000100dw imodreg r m 1 7 immediate to register memory 100000sw mod 010 r m data data if sw 01 1 8 immediate to accumulator 0001010w data data if w 1 1 INC Increment register memory 1111111w mod 000 r m 1 8 register 01000 reg 1 SUB Subtract reg memory with register to either 001010dw mod reg r m 1 7 immediate from register memory 100000sw mod 101 r m data data if sw 01 1 8 immediate from accumulator 0001110w data data if w 1 1 SBB Subtract with borrow reg memory with register to either 000110dw mod reg r m 1 7 immediate from register memory 100000sw mod 011 r m 1 8 immediate from accumulator 0001110w data data if w 1 1 DEC Decrement register memory 1111111w mod 001 r m 1 8 register 01001 reg 1 NEG Change sign register memory 1111011w mod reg r m 1 8 CMP Compare register memory with register 0011101w mod reg r m 1 7 register with register memory 0011100w mod reg r m 1 7 immediate with register memory 100000sw mod 111 r m data data if sw 01 1 7 immediate with accumulator 0011110w data data if w 1 1 MUL multiply unsigned 1111011w mod 100 r m register byte 13 register word 21 memory byte 18 memory word 26 IMUL Integer multiply signed 1111011w mod 101 r m register byte 16 register word 24 memory byte 21 memory word 29 register memory multiply immediate signed 011010s1 mod reg r m data data if s 0 23 28 DIV Divide unsigned 1111011W mod 110 r m register byte 18 register
91. it 2 R2 Ready Mode This bit is used to configure the ready mode for LCS chip select Set 1 external ready is ignored Set 0 external ready 1s required Bit 1 0 R1 R0 Wait State value When R2 is set to 0 it can insert wait states into an access to the LCS memory area R1 R0 0 0 0 wait state R1 R0 0 1 1 wait state R1 R0 1 0 2 wait states R1 R0 1 1 3 wait states 13 3 MCSx The memory block of MCS3 MCS0 can be located anywhere within the 1M byte memory space exclusive of the areas associated with the UCS and LCS chip selects The maximum MCSx active memory range is 512k bytes The 512k MCSx block size can only be used when located at address 00000h and the LCS chip selects must not be active in this case Locating a 512k MCSx block size at 80000h always conflicts with the range of UCS or RAS1 andis not allowed The MCSx chip selects are programmed through two registers A6h and A8h and these select pins are not active on reset Both A6h and A8h registers must be accessed with a read or write to activate MCS3 MCSO There aren t default values on A6h and A8h registers so the A6h and A8h must be programmed first before MCS3 MCSO are active When the DRAM controller is enabled the MCS3 MCSI are performed as DRAM interface Refer to the DRAM controller unit Midranage Memory Chip Select Register Offset A6h Reset Value 15 44 348 42 4 10 9 8 7 6 5 4 3 2 d 0 BA19 BANS dore fs Ps
92. l purpose registers which can be used to determine offset address of operands in Memory SI String operations DI String operations High Low Accumulator BX Base Register Data Group Cx Count Loop Repeat Shift DX Data Stack Pointer Index Group Base Pointer and Pointer Source Index Destination Index GENERAL REGISTERS RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 24 RDC 8B 82 Segment Registers R8822 has four 16 bit segment registers CS DS SS and ES The segment registers contain the base addresses starting location of these memory segments and they are immediately addressable for code CS data DS amp ES and stack SS memory CS Code Segment The CS register points to the current code segment which contains instruction to be fetched The default location memory space for all instruction is 64K The initial value of CS register is OFFFFh DS Data Segment The DS register points to the current data segment which generally contains program variables The DS register is initialized to 0000H SS Stack Segment The SS register points to the current stack segment which is for all stack operations such as pushes and pops The stack segment is used for temporary space The SS register 1s initialized to 0000H ES Extra Segment The ES register points to the current extra segment which is typically for data storage such as large string operations
93. ling edge of ARDY must be synchronized to CLKOUTA Tie ARDY high so the microcontroller is always asserted in the ready condition If the ARDY is not used tie this pin low to yield control to SRDY Both SRDY and ARDY should be tied to high if the system need not assert wait states by externality 7 ALE Output 8 ARDY Input RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 R D C RISC DSP Controller R8822 Bus cycle status These pins are encoded to indicate the bus status S2 can be used as memory or I O indicator S1 can be used as DT R indicator These pins are floating during a A S2 BWSEL aba ieu bus hold and tene 10 Si Output The S2 BWSEL is to decide the boot ROM bus width when 11 S0 Output RST pin goes from low to high If S2 BWSEL is with a pull low resistor 330 ohm the boot ROM bus width is 8 bits Otherwise the boot ROM bus width is 16 bits Bus Cycle Encoding Description s2 S1 S0 Bus Cycle 0 0 0 Interrupt acknowledge 0 0 Read data from I O 0 1 0 Write data to I O 0 1 1 Halt 1 0 0 Instruction fetch 1 0 1 Read data from memory 1 1 0 Write data to memory 1 1 1 Passive 19 A19 PIO9 Address bus Non multiplexed memory or I O addresses The 20 A18 PIO8 A bus is one half of a CLKOUTA period earlier than the AD 22 A17 MA8 PIO7 bus These pins are in high impedance states during a bus 23 Al6
94. mode the IMROUTO or TMROUTI signals can be used to generate waveforms of various duty cycles Maxcount A Maxcount B Maxcount A Maxcount B Dual Maximum Count Mode Maxcount A 1T Maxcount A 1T Maxcount A Single Maximum Count Mode 1T One Microprocessor clock Timer Counter Unit Output Modes RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 RDC seems o o R8822 17 Watchdog Timer R8822 has one independent watchdog timer which is programmable The watchdog timer is active after reset and the timeout count is with a maximum count value The keyed sequence 3333h CCCCh must be written to the register E6h first then the new configuration to the Watchdog Timer Control Register It is a single write so every writing to Watchdog Timer Control Register must follow this rule When the watchdog timer activates an internal counter is counting If this internal count 1s over the watchdog timer duration the watchdog timeout happens The keyed sequence AAAAh 5555h must be written to the register E6h to reset the internal count and prevent the watchdog timeout The internal count should be reset before the Watchdog Timer timeout period is modified to ensure that an immediate timeout will not occur Watchdog Timer Control Register Offset E6h Reset Value C080h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 9 c E z z Bit 15 ENA Enable Watchdog Timer Set 1
95. n o o O R882 PR2 PR1 PRO Priority 0 0 0 0 High 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 Low INT4 Control Register Offset 40h Reset Value 000Fh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L o ees eme Rested unu asi pre emt ero Master Mode Bit 15 8 bit 6 5 Reserved Bit 7 ETM Edge trigger mode enable When this bit is set to 1 and bit 4 set to 0 an interrupt is triggered by an edge which goes from low to high The low to high edge will be latched one level till this interrupt is serviced Bit 4 LTM Level Triggered Mode Set 1 An interrupt is triggered by high active level Set 0 An interrupt is triggered by the low to high edge Bit 3 MSK Mask Set 1 Mask the interrupt source of INT4 Set 0 Enable the INT4 interrupt Bit 2 0 PR Interrupt Priority These bit settings for priority selection are the same as those of bit 2 0 of Register 44h INT3 Control Register Offset 3Eh Reset Value 000Fh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L0 5 o Pemes ene eserves imu msk pre em ero RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 51 RDC swam 4 0 0 R882 Master Mode Bit 15 8 bit 6 5 Reserved Bit 7 ETM Edge trigger mode enable When this bit is set to 1 and bit 4 set to 0 an interrupt is triggered by an edge which goes from low to high The low to high edge will be latched one l
96. nnel 1 or channel 0 to perform a transfer These pins are level triggered 76 DRQI INT6 PIO13 Input Output and internally synchronized The DRQ signals are not latched 77 DRQO INTS PIO12 and must remain active until service finished For INT6 INTS function When the DMA function is not being used INT6 INTS can be used as an additional external interrupt request They share the corresponding interrupt types RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 15 RD CE sses and register control bits The INT6 5 are level triggered only and not necessary to be held until the interrupt is acknowledged Such high levels keep interrupt requests Notes 1 When PIO mode and direction registers are set 32 MUX definition pins can be set as PIO pins For example the DRQI INT6 PIO13 pin76 can be set as PIO13 2 The PIO status during Power On reset PIOI PIO10 PIO22 and PIO23 are input with pull down PIO4 to PIO9 are in normal operations and the others are input with pull up 4 1 R8822 I O Characteristics of Each Pin PQFP Y i Pin Name Characteristics Pin NO Schmitt Trigger input H BM with an internal 50K pull up resistor Schmitt Trigger input SEDE with an internal 50K pull down resistor 45 HOLD CMOS input 47 NMI with an internal 50K pull down resistor 56 INTO Schmitt Trigger TTL input 55 INTI SELECT with
97. nnel should be configured as being source synchronized RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 70 RDC 4 8B 16 Timer Control Unit TMRIN1 TMRINO Microprocessor Clock 50h Timer 0 Count Register 52h 54h Timer0 Maxcount Compare Register Counter 58h Timer 1 Count Register lt gt Element amp J TMROUT1 J TMROUT2 5Ah 5Ch Timer 1 Maxcount Compare Register 60h Timer 2 Count Register 62h Timer 2 Compare Register Timer2 Control DMA Request Logic Timer0 1 2 Interrupt Request 56h Timer 0 Control Register 5Eh Timer 1 Control Register 66h Timer 2 Control Register 16 bit Internal Address Data Bus Timer Counter Unit Block There are three 16 bit programmable timers in the R8822 The timer operation is independent of the CPU The three timers can be programmed as a timer element or as a counter element Timers 0 and 1 are each connected to two external pins TMRINO TMROUTO TMRIN1 and TMROUT1 which can be used to count or time external events or used to generate variable duty cycle waveforms Timer 2 is not connected to any external pins It can be used as a pre scaler to timer 0 and timer 1 or as a DMA request source Timer 0 Mode Control Register Offset 56h Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 15 EN Enable Bit Set 1 The timer 0 is enabled Set 0 The timer 0 is in
98. nterrupt Mask The state of the mask bit of the asynchronous serial port 1 interrupt Bit 8 4 I4 I0 Interrupt Masks Indicates the state of the mask bit of the corresponding interrupt Bit 3 2 D1 I6 D0 I5S DMA Channel or INT Interrupt Masks Indicates the state of the mask bit of the corresponding DMA Channel or INT interrupt Bit 1 Reserved Bit 0 TMR Timer Interrupt Mask The state of the mask bit of the timer control unit RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 60 RDC o o o o O R882 Interrupt Mask Register Offset 28h Reset Value 003Dh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Slave Mode Bit 15 6 Reserved Bit 5 4 TMR2 TMRI Timer 2 Timerl Interrupt Mask The state of the mask bit of the Timer Interrupt Control register Set 1 Timer2 or Time has its interrupt requests masked Bit 3 2 D1 I6 D0 I5 DMA Channel or INT Interrupt Mask Indicates the state of the mask bits of the corresponding DMA or INT6 INTS control register Bit 1 Reserved Bit 0 TMRO Timer 0 Interrupt Mask The state of the mask bit of the Timer Interrupt Control Register Poll Status Register Offset 26h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I I I I IREQ Reserved S4 S0 Master Mode The Poll Status POLLST register mirrors the current state of the Poll register The POLLST register can be read without affecting the current interrupt request
99. ojo o ejo o olo o u ulto Slave Mode Bit 15 3 Reserved Bit 2 0 L2 L0 Interrupt Type Encoded value indicates the priority of the IS interrupt service bit to reset Writes to these bits cause an EOI to be issued for the interrupt type in slave mode Interrupt Vector Register Offset 20h Reset Value 15 14 13 12 11 10 7 6 5 4 3 9 8 2 1 0 Loje eoje olje o mm EEA Slave Mode Bit 15 8 Reserved Bit 7 3 T4 T0 Interrupt Type The following interrupt type of slave mode can be programmed Timer 2 interrupt controller T4 T3 T2 T1 T0 1 0 1 b Timer interrupt controller T4 T3 T2 T1 TO 1 0 0 b DMA 1 interrupt controller T4 T3 T2 T1 TO 0 1 1 b DMA 0 interrupt controller T4 T3 T2 T1 TO 0 1 0 b Timer 0 interrupt controller T4 T3 T2 T1 TO 0 0 0 b Bit 2 0 Reserved RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 62 RDC BB 15 DMA Unit The DMA controller provides the data transfer between the memory and peripherals without the intervention of the CPU There are two DMA channels in the DMA unit Each channel can accept DMA requests from one of three sources external pins DRQO for channel 0 or DRQI for channel 1 serial ports port 0 or port 1 or Timer 2 overflow The data transfer from source to destination can be memory to memory memory to I O I O to I O or I O to memory Either bytes or words can be transferred to or from even
100. or write access to the A2h register activates this pin Low Memory Chip Select Register Offset A2h Reset Value 11 1 15 14 13 12 0 9 8 y 6 5 4 3 2 1 0 Bit 15 Reserved Bit 14 12 UB2 UBO Memory block size selection for LCS chip select pin The active range ofthe LCS chip select pin can be configured by UB2 UBO The LCS pin is not active on reset but any read or write access to the A2h LMCS register activates this pin UB2 UBI UBO Memory Block size Start address End Address 0 0 0 64k 00000h OFFFFh 0 0 1 128k 00000h IFFFFh 0 1 1 256k 00000h 3FFFFh 1 1 1 512k 00000h 7FFFFh Bit 11 8 Reserved Bit 7 DA Disable Address If the BHE ADEN pin is held high on the rising edge of RST the DA bit is valid to enable disable the address phase of the AD bus If the BHE ADEN pin is held low on the rising edge of RST the AD bus always drives the address and data Set 1 Disable the address phase of the AD15 ADO bus cycle when LCS is asserted Set 0 Enable the address phase of the AD15 ADO bus cycle when LCS is asserted Bit 6 LDEN Lower DRAM Enable This bit is used to enable the bank 0 00000h 7FFFFh DRAM controller Set LDEN to 1 the LCS pin becomes RASO and the MCS1 and MCS2 pins become UCAS and LCAS RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 4 RDC 0 n R882 respectively Bit 5 3 Reserved B
101. pin corresponds to INTO Maskable interrupt request l slave select For INT1 feature except the differences in interrupt line and interrupt address vector the function of INT1 is the same as that of INT4 For SELECT feature when the microcontroller is as a slave 55 INT1 SELECT Input Output device this pin is driven from the master interrupt controller decoding This pin is activated to indicate that an interrupt appears on the address and data bus INTO must be activated before SELECT is activated when the interrupt type appears on the bus Maskable interrupt request 0 Except the differences in 56 INTO Input Output interrupt line and interrupt address vector the function ofl INTO is the same as that of INT4 Timer Control Unit Interface Timer input These pins can be as clock or control signal input which depend upon the programmed timer mode After Input Output internally synchronizing low to high transitions on TMRIN the timer controller increments These pins must be pulled up if not being used Timer output Depending on timer mode select these pins 73 TMROUTI PIOI provide single pulse or continuous waveforms The duty cycle 72 TMRINI PIOO 75 TMRINO PIO11 74 TMROUTO PIO10 Oupuninpar of the waveforms can be programmable These pins float during a bus hold or reset DMA Unit Interface DMA request These pins are asserted high by an external device when the device is ready for DMA cha
102. pt controller clock Bit 14 UART Clk Set 1 to stop the asynchronous serial port controller clock Bit 13 DMA Clk Set 1 to stop the DMA controller clock Bit 12 Timer Clk Set 1 to stop the Timer controller clock Bit 11 0 Reserved Power Down Configuration Register Offset 46h Reset Value 00h 15 14 13 12 11 410 9 8 7 6 5 4 3 2 1 0 wo o e o ojojo w ojo oju e e n o Bit 15 PWD Power Down Enable When this bit is set to 1 the CPU will enter power down mode then the crystal clock will stop The CPU will be waked up when an external INT INTO INT4 are active high It will wait 19 bit counter time for the crystal clock to be stable before CPU is waked up Bit 14 9 Reserved Bit 8 WIF Wake up Interrupt Flag Read only bit When the CPU is waked up by interrupt from power down mode this bit will be set to 1 by hardware Otherwise this bit 1s 0 Bit 7 5 Reserved Bit 4 0 I4 I0 Enable the external interrupt INT4 INTO wake up function Set these bits to 1 to make the INT pins function as power down wake up pins RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 32 RDC swam 4 BB 11 Reset Processor initialization is accomplished with activation of the RST pin To reset the processor this pin should be held high for at least seven oscillator periods The Reset Status Figure shows the status of the RST pin and other related pins When RST goes from low to high
103. rved Bit 3 MSK Mask Set 1 Mask the interrupt source of the DMA 0 controller Set 0 Enable the DMA 1 controller interrupt Bit 2 0 PR Interrupt Priority These bit settings for priority selection are the same as those of bit 2 0 of Register 44h RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 55 RDC o o o R882 Timer Interrupt Control Register Offset 32h Reset Value 000Fh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Lojoro ojo ojo o o ojo usk rnc prs rm Master Mode Bit 15 4 Reserved Bit 3 MSK Mask Set 1 Mask the interrupt source of the timer controller Set 0 Enable the timer controller interrupt Bit 2 0 PR Interrupt Priority These bit settings for priority selection are the same as those of bit 2 0 of Register 44h Timer Interrupt Control Register Offset 32h Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pofofoftofofo ofo ol ojo fusk ere prs rm Slave Mode Bit 15 4 Reserved Bit 3 MSK Mask Set 1 Mask the interrupt source of the timer 0 controller Set 0 Enable the timer 0 controller interrupt Bit 2 0 PR Interrupt Priority These bit settings for priority selection are the same as those of bit 2 0 of Register 44h Interrupt Status Register Offset 30h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Master Mode Reset value undefined Bit 15 DHLT DMA Halt Set 1 Halt any DMA activity when non maskable interrup
104. s disabled regardless of the RXIE bit setting The DMA request is generated internally when a DMA channel is being used for serial port transfers And the DRQO or DRQI is not active when a serial port DMA transfers Hardware handshaking may be used in conjunction with serial port DMA transfers 18 3 The Asynchronous Mode Description There are 4 modes operating in the asynchronous serial port Model Mode 1 is the 8 bit asynchronous communications mode Each frame consists of a start bit eight data bits and a stop bit When parity is used the eighth data bit becomes the parity bit Mode 2 Mode 2 is used together with Mode 3 for multiprocessor communications over a common serial link In mode 2 the RX machine will not complete a reception unless the ninth data bit is a one Any character received with the ninth bit equal to zero is ignored No flags are set no interrupts occur and no data is transferred to Receive Data Register In mode 3 characters are received regardless of the state of the ninth data bit Mode 3 Mode 3 is the 9 bit asynchronous communications mode Mode 3 is the same as mode 1 except that a frame contains nine data bits The ninth data bit becomes the parity bit when the parity feature 1s enabled Mode 4 Mode 4 is the 7 bit asynchronous communications mode Each frame consists of a start bit seven data bits and a stop bit Parity bit is not available in mode 4 Serial Port 0 Control Register Offset 80h Reset Value
105. s for timer are the same as those of register 56h for timer 0 RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 RDC 0 o o R882 Timer 1 Count Register Offset 58h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC15 TCO Bit 15 0 TC15 TCO Timer 1 Count Value This register contains the current count of timer 1 The count is incremented by one every four internal processor clocks or pre scaled by timer 2 or incremented by one every external clock which is through configuring the external clock select bit based on the TMRINI signal Timer 1 Maxcount Compare A Register Offset 5Ah Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC15 TCO 3Bit 15 0 TC15 TCO Timer 1 Compare A Value Timer 1 Maxcount Compare B Register Offset 5Ch Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC15 TCO Bit 15 0 TC15 TCO Timer 1 Compare B Value Timer 2 Mode Control Register Offset 66h Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fev mln ofofolololo ofwlolo o o o Bit 15 EN Enable Bit Set 1 Timer 2 is enabled Set 0 Timer 2 is inhibited from counting The INH bit must be set to 1 during the EN bit is written and the INH and EN bits must be in the same write Bit 14 INH Inhibit Bit This bit allows selective updating the EN bit The INH bit must be set to 1 when the EN bit is written and both the INH and EN bi
106. set to 0 and the PCB map starts at FFOOh in I O space Set 1 The peripheral control block PCB is located in memory space Set 0 The PCB is located in I O space Bit 11 0 R19 R8 Relocation Address Bits The upper address bits of the PCB base address The defaults of the lower eight bits are 00h When the PCB is mapped to I O space the R19 R16 must be programmed to 0000b Offset F4h Processor Release Level Register Reset Value D9h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 This read only register specifies the processor release version and RDC identification number Bit 15 13 read only 011 Bit 12 8 Processor version Olh version A 02h version B 03h version C 04h version D Bit 7 0 RDC identification number D9h Final Version 1 6 RDC Semiconductor Co January 5 2004 Subject to change without notice 29 RDC wow 4 05 R882 10 Power Save amp Power Down PSEN F0h 15 PWD 46h 15 enable disable enable disable Microprocessor Internal Clock xi CLKIN CLOCK or Divisior x2 CLKIN 2 CLK 2 CLK 128 e CLKOUTA CAD F0h 8 CLKIN 2 Select Divisor Select F2 F0 F0h 2 F0h 0 CAF FOh 9 S6 CLKDIV2 je CLKOUTB CBD FOh 10 CBF F0h 11 System Clock The CPU provides power save amp power down functions Power Save In power save mode users can program the Power Save Control Register to divide the internal operating clock Users can also disable
107. the request to send signals TS Request to send TS Clear to send RTR Ready to receive ENRX Enable receiver request DCE DTE Protocol Connection The DCE DTE protocol communication steps a DTE sends data to DCE b RTS signal is asserted by DTE when data is available c The RTS signal is interpreted by the DCE device as a request to enable its receiver d The DCE asserts the RTR signal to response that DCE is ready to receive data 18 1 2 CTS RTR Protocol The serial port can be programmed as a CTS RTS protocol by clearing both ENRX and RTS bits This protocol is a symmetric interface which provides flow control when both ports are sending and receiving data CTS Clear to send RTR Ready to receive CTS RTR Protocol Connection RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 79 RDC 8B 18 DMA Transfer to from a Serial Port Function DMA transfers to the serial port function are regarded as destination synchronized DMA transfers A new transfer is requested when the Transmit Holding Register is empty When the port is configured for DMA transmits the corresponding transmit interrupt is disabled regardless of the TXIE bit setting DMA transfers from the serial port function are regarded as source synchronized DMA transfers A new transfer is requested when the Receive Buffer contains valid data When the port is configured for DMA receives the corresponding receive interrupt i
108. to WR inactive 0 12 ns R8822 RDC Semiconductor Co Subject to change without notice 109 Final Version 1 6 January 5 2004 RDC swen o o o O R882 4 2 w tw w 6 4 W AD15 AD0 MA9 MAO DRAM Refresh Cyde MAX Unit 12 ns 12 ns 12 ns 12 ns 12 ns 12 ns 12 ns 12 ns Z z Z Description CLKOUTA high to Data drive FFFF CLKOUTA high to Row address valid CLKOUTA low to Column address valid CLKOUTA high to RAS active CLKOUTA low to RAS inactive CLKOUTA high to CAS active CLKOUTA low to CAS inactive CLKOUTA low to RD active CLKOUTA lowto RD inactive WO CO NIANA MY BlW N R SO Ol WwW WY W WI DIO aQ RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 110 R D C 2 RISC DSP Controller 25 Thermal Characteristics 0 4 thermal resistance from device junction to ambient temperature P operation power Ta maximum ambient temperature in operation mode Ta 7Tr Px0 4 Package Board Air Flow m s Oya 0 48 8 PQFP 2 Layer aat 2 42 7 3 41 9 0 53 6 LQFP 2 Layer ut 2 45 5 3 44 5 0 38 9 1 35 7 PQFP 4 Layer 5 33 8 3 33 3 0 42 6 1 38 0 LQFP 4 Layer 5 36 1 3 35 3 Recommended Storage Temperature 65 C to 125 C R8822 Unit C Watt Note The IC should be mounted on PC
109. tor Co Subject to change without notice 97 Final Version 1 6 January 5 2004 RDC swen o o O R882 No Description MIN MAX Unit 1 CLKOUTA high to A Address Valid 0 12 ns 2 A address valid to RD low 1 5T 9 ns 3 S6 active delay 0 15 ns 4 S6 inactive delay 0 15 ns 5 AD address Valid Delay 0 12 ns 6 Address Hold 0 12 ns 7 Data in setup 5 ns 8 Data in Hold 2 ns 9 ALE active delay 0 12 ns 10 ALE inactive delay 0 12 ns 11 Address Valid after ALE inactive T 2 5 ns 12 ALE width T 5 ns 13 RD active delay 0 12 ns 14 RD Pulse Width 21 10 ns 15 RD inactive delay 0 12 ns 16 CLKOUTA HIGH to LCS UCS valid 0 15 ns 17 UCS and LCS inactive delay 0 15 ns 18 PCS MCS active delay 0 15 ns 19 PCS MCS inactive delay 0 15 ns 20 DEN active delay 0 15 ns 21 DEN inactive delay 0 15 ns 22 DTR active delay 0 15 ns 23 DTR inactive delay 0 15 ns 24 Status active delay 0 15 ns 25 Status inactive delay 0 15 ns 26 UZI active delay 0 15 ns 27 UZI inactive delay 0 15 ns 1 T means a clock period time 2 All timing parameters are measured at 1 5V with 50 PF loading on CLKOUTA All output test conditions are with CL 50 pF RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 98 R D C li RISC DSP Controller A19 A0 AD15 ADO WHB WLB UCS LCS PCSx MCSx T1 T2 WRITE CYCLE T3
110. ts must be in the same write This bit is not stored and always read as 0 Bit 13 INT Interrupt Bit Set 1 An interrupt request is generated when the count register equals a maximum count Set 0 Timer 2 will not issue interrupt request Bit 12 6 Reserved RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 RDC swen 0 o R882 Bit 5 MC Maximum Count Bit When the timer reaches its maximum count the MC bit will be set to 1 by H W This bit is set regardless of the INT bit 66h 13 Bit 4 1 Reserved Bit 0 COUNT Continuous Mode Bit Set 1 Timer is continuously running when it reaches the maximum count Set 0 The EN bit 66h 15 is cleared and the timer is held after each timer count reaches the maximum count Timer 2 Count Register Offset 60h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC15 TCO Bit 15 0 TC15 TCO Timer 2 Count Value This register contains the current count of timer 2 The count is incremented by one every four internal processor clocks Timer 2 Maxcount Compare A Register Offset 62h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC15 TCO Bit 15 0 TC15 TCO Timer 2 Compare A Value 16 1 Timer Counter Unit Output Mode Timers 0 and 1 can use one maximum count value or two maximum count values Timer 2 can use only one maximum count value Timer 0 and timer can be configured to be a single or dual Maximum Compare count
111. ts occurs Set 0 When an IRET instruction is executed Bit 14 3 Reserved Bit 2 0 TMR2 TMRO Set 1 Indicates the corresponding timer has an interrupt request pending RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 56 RDC swan o o R882 Interrupt Status Register Offset 30h Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Slave Mode Bit 15 DHLT DMA Halt Set 1 Halt any DMA activity when non maskable interrupts occur Set 0 When an IRET instruction is executed Bit 14 3 Reserved Bit 2 0 TMR2 TMR0O Set 1 Indicates the corresponding timer has an interrupt request pending Interrupt Request Register Offset 2Eh Reset Value 15 14 13 12 11 1 0 9 8 Y 6 5 4 3 2 1 0 Master Mode The Interrupt Request register is a read only register For internal interrupts SP0 SP1 D1 I6 D0 IS and TMR the corresponding bit is set to 1 when the device requests an interrupt The bit is reset during the internally generated interrupt acknowledge For INT4 INTO external interrupts the corresponding bit 14 10 reflects the current value of the external signal Bit 15 11 Reserved Bit 10 SPO Serial Port 0 Interrupt Request Indicates the interrupt state of the serial port 0 Bit 9 SP1 Serial Port 1 Interrupt Request Indicates the interrupt state of the serial port 1 Bit 8 4 14 10 Interrupt Requests Set 1 The corresponding INT pin has an interrupt
112. uary 5 2004 RDC swen o R882 Master Mode Bit 15 8 Reserved Bit 7 ETM Edge trigger mode enable When this bit is set to 1 and bit 4 set to 0 an interrupt is triggered by an edge which goes from low to high The low to high edge will be latched one level till this interrupt is serviced Bit 6 SENM Special Fully Nested Mode Set 1 Enable the special fully nested mode of INTO Bit 5 C Cascade Mode Set this bit to 1 to enable the cascade mode for INT1 or INTO Bit 4 LTM Level Triggered Mode Set 1 An interrupt is triggered by high active level Set 0 An interrupt is triggered by the low to high edge Bit 3 MSK Mask Set 1 Mask the interrupt source of INTO Set 0 Enable the INTO interrupt Bit 2 0 PR Interrupt Priority These bit settings for priority selection are the same as those of bit 2 0 of Register 44h INTO Control Register Offset 38h Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Lo o meme i Slave Mode For Timer 1 interrupt control register reset value is 0000h Bit 15 4 Reserved Bit 3 MSK Mask Set 1 Mask the interrupt source of timer 1 Set 0 Enable the timer 1 interrupt Bit 2 0 PR Interrupt Priority These bit settings for priority selection are the same as those of bit 2 0 of Register 44h DMA 1 INT6 Interrupt Control Register Offset 36h Reset Value 000Fh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Eojojojoje oje o ojo o e vsk Pre rr pro Master Mode Bit
113. ve 3 12 ns 9 CLKOUTA low to CAS inactive 3 12 ns 10 CLKOUTA low to RD active 0 12 ns 11 CLKOUTA lowto RD inactive 0 ns RDC Semiconductor Co Final Version 1 6 Subject to change without notice January 5 2004 107 R D C ii RISC DSP Controller a a 82 B R8822 tl aem LJ eN y DRAM Write Cycle with No Wait State No Description MIN MAX Unit 1 CLKOUTA low to A Address Valid 0 12 ns 2 CLKOUTA low to A Data Valid 0 12 ns 3 CLKOUTA high to Row address valid 0 12 ns 4 CLKOUTA low to Column address valid 0 12 ns 5 CLKOUTA low to RAS active 3 12 ns 6 CLKOUTA high to RAS inactive 3 12 ns 7 CLKOUTA high to CAS active 3 12 ns 8 CLKOUTA low to CAS inactive 3 12 ns 9 CLKOUTA low to WR active 0 12 ns 10 CLKOUTA low to WR inactive 0 12 ns RDC Semiconductor Co Subject to change without notice 108 Final Version 1 6 January 5 2004 RDC RISC DSP Controller DRAM Write Cycle with Wait States No Description MIN MAX Unit 1 CLKOUTA low to A Address Valid 0 12 ns 2 CLKOUTA low to A Data Valid 0 12 ns 3 CLKOUTA high to Row address valid 0 12 ns 4 CLKOUTA low to Column address valid 0 12 ns 5 CLKOUTA low to RAS active 3 12 ns 6 CLKOUTA high to RAS inactive 3 12 ns 7 CLKOUTA high to CAS active 3 12 ns 8 CLKOUTA low to CAS inactive 3 12 ns 9 CLKOUTA low to WR active 0 12 ns 10 CLKOUTA low
114. ways drives the address and data Set 1 Disable the address phase of the AD15 ADO bus cycle when UCS is asserted Set 0 Enable the address phase of the AD15 ADO bus cycle when UCS is asserted Bit 6 UDEN Upper DRAM Enable Set this bit to enable the bank2 80000h FFFFFh DRAM controller When the UDEN is set the MCS3 pin becomes RASI and the MCS and MCS2 pins become UCAS and LCAS respectively The UCS pin is disabled when the UDEN bit is set to 1 Users can boot the code from flash memory with UCS pin and switch space to a DRAM bank 1 after system initialization Bit 5 3 Reserved Final Version 1 6 RDC Semiconductor Co January 5 2004 Subject to change without notice 40 RDC 4 8B Bit 2 R2 Ready Mode This bit is used to configure the ready mode for UCS chip select Set 1 external ready is ignored Set 0 external ready is required Bit 1 0 R1 RO Wait State value When R2 is set to 0 it can insert wait states into an access to the UCS memory area The reset value of R1 RO0 is 1 1 R1 RO 0 0 0 wait state RI RO 2 0 1 1 wait state R1 RO 1 0 2 wait states RLRO 1 3 wait states 13 2 LCS The lower 512k bytes 00000h 7FFFFh memory region chip selects The memory active range is programmable which has no default size on reset So the A2h register must be programmed first before accessing the target memory range The LCS pin is not active on reset but any read

16-Bit RISC Microcontroller User's Manual

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