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User Manual - General Standards Corporation

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1. 13 5 register address offset can be selected to be in short address space A16 or in standard address space A24 RO read only WO write only RW read write capability BD Bit Dependent Revision B User Manual for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 3 1 REGISTER BIT MAPS All Reserved bits should be set to O for future compatibility Also the value read from a reserved bit will be indeterminate 3 1 1 3 1 1 1 3 1 1 2 3 1 1 3 3 1 1 4 3 1 2 1 BOARD CONTROL STATUS REGISTERS Board ID Register D0 D16 Reads back hex CEAC Device Type Register D0 D16 Reads back hex F4E4 Board Control Register D0 Board Reset L pulsed 1 vvill generate a self timed pulse that vvill reset the board There is no need for the softvvare to return to clear this bit O will not generate a self timed pulse that will reset the board There is no need for the software to return to clear this bit D1 Enable Interrupts 1 will enable this board to generate VME interrupts 0 will disable the board from generating VME interrupts D2 3 Reserved D4 Spare LED On A software controlled bit 1 will turn off the Fail LED 0 will turn on the Fail LED D5 6 Reserved D7 Fail LED On L A software controlled bit 1 vvill turn off the Fail LED O vvill turn on the Fail LED DS D15 Reserved Board
2. signals should travel beside or be twisted with the signal If the jumpers are installed in the factory configuration then the following pin outs will apply Table 4 4 1 Pin Out for User Connectors P3 Channel 0 P4 Channel 1 P5 Channel 2 P6 Channel 3 Jumper Signal Name Connector Tam aane d 06 En WR Cable Tx Rx CLK LWR Cable Tx Rx CLK UPR Cable TxD RxD UPR Cable TxD RxD UPR Cable CTS DCD UPR Cable CTS DCD UPR Cable Tx Rx CLK UPR Cable Tx Rx CLK Revision B User Manual for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 43
3. D0 D7 RW RSYN 0 7 3 1 6 22 RECEIVE COUNT LIMIT REGISTER ADDRESS 10101 3 1 6 22 1 Low Offset Address 0x54 D0 7 RW RCL 0 7 3 1 6 22 2 High Offset Address 0x56 D0 7 RW RCL 0 7 3 1 6 23 RECEIVE CHARACTER COUNT REGISTER ADDRESS 10110 3 1 6 23 1 Low Offset Address 0x58 D0 7 RO RCC 0 7 Revision B User Manual for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 3 1 6 23 2 High Offset Address 0x5A D0 7 RO RCC 0 7 3 1 6 24 TIME CONSTANT 0 REGISTER ADDRESS 10111 3 1 6 24 1 Low Offset Address Ox5C D0 7 RW TCO 0 7 3 1 6 24 2 High Offset Address OXSE D0 7 RW TCO 0 7 3 1 6 25 TRANSMIT MODE REGISTER ADDRESS 11001 3 1 6 25 1 Low Offset Address 0x64 Tx Enable DI RW DO RW Disable Immediately AEE Si Disable After Transmission FEE SS THE Enable Without Auto Enables Enable With Auto Enables Tx Character Length is 41 S NG Bel EV MBR i ES 11 71 le E EG 5 0 1 E SA Jr id BR EI poe HE all s s E 33 pH 11 i E N 11 EEN E 51 D5 RVV Tx Parity Enable Tx Parity Sense 3 1 6 25 2 High Offset Address 0x66 Revision B User Manual for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 37 D2 RVV Tx CRC Preset Value D1 RW Tx CRC Enable DO RW Tx CRC on E
4. srl 1 0 ResetBOREOM 0 lo 14 1 1 SeEOFFOM 080 0 3 1 6 27 TRANSMIT INTERRUPT CONTROL REGISTER ADDRESS 11011 3 1 6 27 1 Low Offset Address 0x6C D0 RW TCIR Read Count TC D1 RW Tx Overrun LA D2 RW Wait for Send Command D3 RW Tx CRC Sent IA D4 RW Tx EOF EOT Sent IA D5 RW Tx Abort Sent IA D6 RW Tx Idle Sent IA D7 RW Tx Preamble Sent IA 3 1 6 27 2 High Offset Address Ox6E D0 7 RW Tx FIFO Control and Status Fill Interrupt DMA Level 3 1 6 28 TRANSMIT SYNC REGISTER ADDRESS 11100 3 1 6 28 1 Low Offset Address 0x70 D0 7 RW TSYN 0 7 3 1 6 28 2 High Offset Address 0x72 D0 7 RVV TSYN 0 7 3 1 6 29 TRANSMIT COUNT LIMIT REGISTER ADDRESS 11101 3 1 6 29 1 Low Offset Address 0x74 Revision B User Manual for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 D0 7 RVV TCL 0 7 3 1 6 29 2 High Offset Address 0x76 D0 7 RVV TCL 0 7 3 1 6 30 TRANSMIT CHARACTER COUNT REGISTER ADDRESS 11110 3 1 6 30 1 Lovv Offset Address 0x78 D0 7 RO TCC 0 7 3 1 6 30 2 High Offset Address 0x7A D0 7 RO TCC 0 7 3 1 6 31 TIME CONSTANT 1 REGISTER ADDRESS 11111 3 1 6 31 1 Low Offset Address 0x7C D0 7 RW TCI 0 7 3 1 6 31 2 High Offset Address 0x7E D0 7 RW TC1 0 7 Revision B User Manual for the VME SIO4 Board Revision A General Standards Corporation 8
5. Offset Address 0x38 55 e nani ine e aan NE 3 1 6 15 2 High Offset Address 5222 222 3 1 6 16 status interrupt control Register Address 01111 3 1 6 16 1 Low Offset Address Ox3C 3 1 6 16 2 High Offset Address Ox3E65 3 1 6 17 Tx Rx Data Register Address 1x000 sene 3 1 6 17 1 Low Offset Address 0x40 3 1 6 17 2 High Offset Address 0x42 1a rere teer tr tee Dee esha e erem ng race hae Ren ends 3 1 6 18 Receiver Mode Register Address 10001 3 1 6 18 1 Low Offset Address 0x44 3 1 6 18 2 High Offset Address 0x46 seene 3 1 6 19 Receive Command Status Register Address 10010 s 3 1 6 19 1 E0w Offset Address 0x48 ia vede ete ER EROR RE RU UNTER HE ER EE es UIS 1 6 19 2 High OffsetAddress Ox4A wei teniente DR e NER RETE EE 3 1 6 20 Receive Interrupt Control Register Address 10011 3 1 6 20 1 Low Offset Address Ox4C 3 1 6 20 2 High Offset Address Ox4B 3 1 6 21 Receive Sync Register Address 10100 ee ee Ge eene enne eneve 3 1 6 21 1 Love OffsetzAddress 0x50 saue 3 1 6 21 2 High Offset Address 0x52 3 1 6 22 Receive Count Limit Register Address 10101 esee eene 310622 1 Low Offset Address OI oet Re EE e
6. 3 1 6 7 2 High Offset Address Ox1A 3 1 6 8 Test Mode Control Register Address 00111 3 1 6 8 1 Low Offset Address 0x1C 3 1 6 8 2 High Offset Address Ox1E 3 1 6 9 Clock Mode Control Register Address 01000 Ge ee vene veren 27 31 6 9 1 Eow Offset Address 0X20 is pee E DR Hp eee EIER r re 27 3 1 0 9 2 High Ofiset Address 0x22 ere de eet Ge N eive Y ae 28 3 1 6 10 Hardware Configuration Register Address 01001 28 3 1 6 10 1 Low Offset Address 0x24 3 1 6 10 2 High Offset Address Ox ZO an der s 29 3 1 6 11 Interrupt Vector Register Address 01010 sss 30 3 1 6 11 1 Low Offset Address 0x28 3 1 6 11 2 High Offset GE DAD OR EE ne OE ME OR EE EE ERE 3 1 6 12 I O Control Register Address 0 0 3 1 6 12 1 Low Offset Address O0x20 sesde eite tnter eor mm irinn 3 1 6 12 2 High Offset Address OZE or p ieee nt eee att 3 1 6 13 interrupt Control Register Address 01100 i 3 1 6 13 1 Low Offset Address 0x30 4 p o erre Ta E eT ph adest ENVOYER Gog n 3 1 6 13 2 High Offset Address 0x32 4 aet tree eter Ge Ge i dc ees ge Ee E gus ede deer 3 1 6 14 Daisy Chain Control Register Address 01101 3 1 6 14 1 Low Offset Address Ox34 3 1 6 14 2 High RW Offset Address 0x36 3 1 6 15 Misc Interrupt Status Register Address 01110 eene eene 3 1 6 15 Low
7. tt 12 2 1 INTERRUPTS rre RR RENE EE AREE REGIME OE 12 2 2 DESCRIPTION OER DMA 5 5 asa AE ER EE EE EN 12 253 CABRERA 13 2 4 TRANSMIT REGEIVE CLOCK oi AL aida 13 CHAPTER 3 PROGRAMMING seoseereseveveenvennensvnneenennvenevneennenennnennenesenevnnennenennnennennsenenenennennnnnennenevenevnnensennsnnennee 14 3 0 REGISTER MAP ertet de eee d ssa s d y gee 14 3 1 REGISTER BIT MAPS seen 15 3 1 1 BOARD CONTROL STATUS REGISTERS eee 15 Sal E BODD Register SS 3 1 1 2 Device Type Register 3 1 1 3 Board Control Register 3 1 1 4 Board Status Register A 15 314 2 VO CONTROL REGISTERS 3 1 2 1 Channel 0 Control Register same format for Channels 1 3 Control Registers sess 15 3 1 3 Channel 0 FIFO same format for Channels 1 3 16 3 1 4 Channel FIFO Status Register same format for Channels 1 3 FIFO Status Registers 16 3 1 5 INTERRUPT CONTROL STATUS REGISTERS eee 17 3151 Intertupt Control Rester eee eH R s an 3 1 5 2 Interrupt Status Register Dual Purpose Bits ICR Interrupt Control Register 3 123 Interrupt Vector Regist a a DE A EG hd nse dd oe ER d me ee 3 1 5 SERIAL CONTROLLER REGISTERS sesse ee es se esse ee es se es sede ee se ese ee es se ee se ee ee nenen ee serre mee vese ii Ge ee ses 3 1 6 1 Channel Comman
8. 6 28 1 Low Offset Address Ox Osorio e E e EXER E Res Ih T tia 39 3 1 6 28 2 High Offset Address OX72 is es Ese rp rh ter re E e HORE t ei ee a erede ete ede 39 3 1 6 29 Transmit Count Limit Register Address 11101 esses eerte nennen nente 39 3 1 6 29 1 Eow Offset Address OX74 EE eta R EOS oe 39 3 1 6 29 2 High Offset Address 0x70 aree te eese ie 40 3 1 6 30 Transmit Character Count Register Address 11110 essere nnne 40 3 1 6 30 1 Love Offset Address Ox78 ananasen CAREERS 40 3 1 6 30 2 High Offset Address OX TA eem tie nr RO D RE RECHNER IE eet EN 40 3 1 6 31 Time Constant I Register Address JJJ 40 3 1 6 31 1 Low Offset Address 0x7C 3 1 6 31 2 High Offset Address 0x7E CHAPTER 4 HARDWARE 7 41 4 0 THE ON BOARD TRANSMIT RECEIVE CLOCK 41 4 1 IRQ LEVEL SELECT JUMPERS 16 nitro ener te i ei sashes Ee ERGE 41 42 BASE ADDRESS JUMPERS 11 J4 J5 teet t fe iii 41 4 33 THE ZILOG CLOCK SELECT JUMPERS 711 14 ese se see se ee ee ee ee ee ee ee se ee se ee se ese ese core ee nennen 42 44 THE CHANNEL PIN OUT JUMPERS 110 712 J13 115 2 43 Revision B User Manual for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 C
9. D1 2 for information submit request to VITA10229 North Scottsdale Road Suite B Scottsdale AZ 85253 Telephone 602 951 8866 Zilog s USC Universal Serial Controller part number Z16C30 User s Manual and Databook for information submit request to Zilog Inc 210 East Hacienda Ave Campbell CA 95008 6600 Telephone 408 370 8000 Revision B User Manual for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 VME SIO4 Documentation History 1 2 3 4 5 6 7 8 9 10 11 12 The Vme SIO4 documentation was updated March 1997 The manual vvas reformatted for conformity of text and the table of contents vvas corrected The jumper field drawings in Chapter 4 were redrawn and double checked April 27 1997 Chapter 3 page 3 Section 3 1 2 1 D6 amp D7 bit descriptions were corrected instead of 0 will enable Rx it was corrected to be a 1 will enable Rx and instead of 1 will disable Rx it was corrected to be a 0 will disable Rx April 27 1997 Chapter 4 page 2 Section 4 3 added pin numbers for J11 8 J14 drawing changed pin 6 amp 11 to circles they were previously squares which represent pin 1 August 15 1997 merged all files into one September 15 1997 corrected errors Section 4 0 and 4 1 typos September 29 1997 corrected errors Section 1 2 deleted reference to figure 1 2 1 Corrected
10. Status Register D0 D15 Reserved VO CONTROL REGISTERS Channel 0 Control Register same format for Channels 1 3 Control Registers D0 Reset Tx Buffer pulsed 1 will generate a self timed pulse that will reset the Tx Buffer There is no need for the software to return to clear this bit D1 Reset Rx Buffer pulsed 1 will generate a self timed pulse that will reset the Rx Buffer There is no need for the software to return to clear this bit D2 Enable interrupts for channel number 1 will enable this board to generate interrupts for this channel number 0 will disable the board from generating interrupts for this channel number D3 Reserved Revision B User Manual 15 for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 3 1 4 D4 En Drive Lovver Cable H 1 will enable this board to drive the lower cable 0 will disable this board from driving the lower cable D5 En Drive Upper Cable H 1 will enable this board to drive the upper cable 0 will disable this board from driving the upper cable D6 En Rx Lower Cable L 1 will enable RX to drive the lower cable 0 will disable RX from driving the lower cable D7 En Rx Upper Cable L 1 will enable Rx to drive the upper cable 0 will disable Rx from driving the upper cable D8 D15 Reserved CHANNEL 0 FIFO SAME FORMAT FOR CHANNELS 1 3 FIFO D0 D7 Valid D8 D15 Reserved CHANNEL 0 FIFO STATUS REGIS
11. a VME or interrupt access to or from the Zilog is currently taking place and a DMA request is made the DMA will wait until the current access cycle has completed and the bus for the Zilog is free before it starts the DMA transfers 2 5 CABLE The Cable is configured as upper and lower so that one cable can be used for both transmit and receive therefore allowing full duplex capabilities for each channel Each channel has a control register that can be set to transmit upper or lower and to receive upper or lower t is not possible to receive both but it is possible to transmit both If the channel control register is not told to transmit or receive upper and not told to transmit or receive lower then this board will not drive the cable nor will it load the cable i e this channel will be tri stated If an external loopback test is desired to be performed without a cable the software can set it up to do transmit upper or lower and to receive the same The effect given will be an external loopback without a cable 24 TRANSMIT RECEIVE CLOCK The transmit receive clock is controlled via a 3 x 5 jumper If the jumper is removed for a particular clock it is expected that the Zilog will produce the transmit receive clock It cannot output a clock to the half of the cable that 1t is receiving from It can output a clock to the cable it is transmitting to If the jumper is selected for receive clock the Zilog will get its clock from the ca
12. addresses Sections 3 1 6 14 2 3 1 6 15 1 3 1 6 15 2 3 1 6 25 1 and 3 1 6 25 2 Temporarily inserted Figure 1 1 1 after Section 1 2 Verified all serial control register offset addresses September 30 1997 Section 3 1 5 3 moved D3 7 and D8 15 to end of list deleted DO 7 text Changed heading format created new table of contents Section 2 3 Reworded Section 3 1 2 1 added note about self timed pulse Section 3 1 4 changed reference to is status and is not status to is empty and is not empty Section 3 1 5 1 added almost to bit descriptions D1 land D13 Section 3 1 5 3 inserted description of vector register encoding Section 3 1 6 inserted reference to Zilog references which were also inserted into related publications Section 3 1 6 1 1 added WO to description Inserted block diagram figure 1 1 1 directly after section 1 2 Section 1 0 a 6 added note about VME DMA controller October 1 1997 Section 3 1 1 3 added self timed note to bit DO s description Section 3 1 4 Section 3 1 5 1 and Section 3 1 5 2 reworded bit descriptions to be more understandable Section 3 1 5 3 Changed to hardware encoded and software selectable Section 3 1 5 reworded serial controller note Section 3 1 6 16 changed Receive Data Register to Status Interrupt Control which was left out and inserted it s bit descriptions Section 3 1 6 17 made Low and High both Tx and Rx October 21 1997 Section 3 0 Table 3 0 1 adress offset 0x20 c
13. and Device Status Latches Internal Daisy Chain Reserved 0 0 1 Reserved 060 1 Reserved 0808020 0 LO 1 1 Reserved 0802 0 0 Reserved 0 PO 10 1 T Reese 7 1 1 O0 Reserved Revision B User Manual for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 o 1 1 Reserved 0 jan 0 1 0 si cup AA 2 Boli 0 k or qr 1 1 I 4049 1 400 1 1 4044 D5 D7 RVV Reserved 3 1 6 8 2High Offset Address Ox1E D0 D7 RVV Reserved 3 1 6 9 CLOCK MODE CONTROL REGISTER ADDRESS 01000 3 1 6 9 1Lovv Offset Address 0x20 Receive Clock Source Disabled o 0 1 RCPn 0 CPR k o 1 1 DPLLOutput 1 0 BRGOOuput 1 0 1 BRGiOumut 1 1 CTROOupu 1 1 1 CTROuu Transmit Clock Source Disabled f 508100 1 RCPn 0 1 02 1170 ERO Em 5010151 1 PUp y BRGO Output 1 1 BRGIOuput 1 1 CTROOutput Revision B User Manual for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 27 DPLL Clock Source BRGOOwtpue 1 1 1 form 3 1 6 9 2High Offset Address 0x22 BRG60 Clock
14. vvithin 30 minutes The following modes of loop back testing are supported a internal loop back testing does not drive the cable b external loop back testing via an external loop back test cable 1 9 ERROR DETECTION Error detection built into the board includes the following a parity error detection b CRC error detection c Rx overrun d Tx underrun 1 10 INTERRUPTS Interrupts will be provided for the following conditions Sync word detected Tx FIFO empty Rx FIFO not empty Rx FIFO almost full ao T Revision B User Manual 10 for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 Interrupt status bits are cleared by writing a 1 to the respective bit in the interrupt status register A second interrupt from that bit will not occur until after that status bit has been cleared 1 11 DIAGNOSTIC LED DISPLAYS LEDs provide for indication of the following conditions BIT loop back pass fail status FAIL LED Channel 0 Receiver is empty Channel 1 Receiver is empty Channel 2 Receiver is empty Channel 3 receiver is empty IRQ Pending VME Access Spare LED mao AO CO 60 TY 1 12 CABLE INTERFACE CONNECTIONS There are four female DB25 cable interface user UO interface connectors mounted at the front edge of the board P3 Channel 0 P4 Channel 1 PS Channel 2 P6 Channel 3 The pinout is show
15. 0 Rx FIFO Not Empty Interrupt 1 will enable this board to generate an interrupt when the Rx FIFO is not empty O will disable this board from generating an interrupt when the Rx FIFO is not empty Enable Channel 0 Rx FIFO Almost Full Interrupt 1 will enable this board to generate an interrupt when the Rx FIFO is full 0 will disable this board from generating an interrupt when the Rx FIFO is full Enable Channel 1 Rx FIFO Not Empty Interrupt 1 will enable this board to generate an interrupt when Rx FIFO is not empty 0 will disable this board from generating an interrupt when Rx FIFO is not empty Enable Channel 1 Rx FIFO Almost Full Interrupt 1 will enable this board to generate an interrupt when the Rx FIFO is almost full 0 will disable this board from generating an interrupt when the Rx FIFO is almost full Enable Channel 2 Rx FIFO Not Empty Interrupt Revision B User Manual 17 for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 3 1 5 2 1 will enable this board to generate an interrupt when the Rx FIFO is not empty O will disable this board from generating an Interrupt when the Rx FIFO is not empty D13 Enable Channel 2 Rx FIFO Almost Full Interrupt 1 will enable this board to generate an interrupt when the Rx FIFO is almost full 0 will disable this board from generating an interrupt when the Rx FIFO is almost full D14 Enable Channel 3 Rx FIFO Not Empt
16. 149 314 XL IM IVA 049 Odl4 XH PH INA 042 Odla XI IM INA 05 boi WA t 49 bolZ pd INA 0 47 POHZ IJ sr SUS Coys PH paja iso Bey 1 UD pokaals0g 0 snqawa iagram Functional Block Di Figure 1 1 1 Revision B User Manual for the VME SIOA Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 1 3 BOARD CONTROL REGISTER The board control register will provide configuration of the board including the self test modes 1 4 BOARD STATUS REGISTER The board status register will provide status with regard to receive FIFO status and transmit FTFO status 1 5 SYNC WORD SELECTION The sync word selection is used to provide an interrupt upon the reception of a particular character This character is software programmable 1 6 DATA RECEPTION Data is received into the Zilog Z16C30 after which the software may retrieve the data from the Z16C30 or the main Rx FIFOs depending on how the Z16C30 has been initialized 1 7 DATA TRANSMIT Data is received into the Zilog Z16C30 after which the software may write data to the master FIFOs or to the Zilog depending on how the Z16C30 has been initialized At this point the Zilog can be placed into a transmit mode 1 8 LOOP BACK TESTING The card is designed vvith sufficient built in loop back testing capability in order to allovv softvvare to perform fault isolation to the VME card level and replacement
17. 2 RW Transmit Data TUS D3 RVV Transmit Status TUS Revision B User Manual for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 D4 RVV Receive Data TUS D5 RW Receive Status IUS TUS Command da Null Command 1 Nut Command 1 Reset TUS 3 1 6 15 MISC INTERRUPT STATUS REGISTER ADDRESS 01110 3 1 6 15 1 Low Offset Address 0x38 D0 RW BRGO ZC Latched Unlatch D1 RW BRGI ZC Latched Unlatch D2 RW DPLL SYNC Latched Unlatch D3 RW RCC Overflow Latched Unlatch D4 RO CTS D5 RW CTS Latched Unlatch D6 RO DCD D7 RW DCD Latched Unlatch 3 1 6 15 2 High Offset Address Ox3A D0 RO TxREQ D1 RW TxREQ Latched Unlatch D2RO RxREQ D3 RW RxREQ Latched Unlatch D4RO TxC D5 RW TxC Latched Unlatch D6RO RxC D7 RW RxC Latched Unlatch 3 1 6 16 STATUS INTERRUPT CONTROL REGISTER ADDRESS 01111 3 1 6 16 1 Low Offset Address 0x3C D0 RW BRGO ZC IE D1 RW BRGI ZC IE D2 RW DPLL SYNC IE D3 RW RCC Overflow IE D4 RW CTS Interrupts D5 RW CTS Interrupts D6 RW DCD Interrupts D7 RW DCD Interrupts 3 1 6 16 2 High Offset Address 0x3E65 DO RW TxREQ Interrupts D1 RW TxREQ Interrupts D2 RW RxREQ Interrupts D3 RW RxREQ Interrupts Revision B User Manual for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 D4 RW TxC Interrupts
18. 302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 40 CHAPTER 4 HARDWARE CONFIGURATION 4 0 THE ON BOARD TRANSMIT RECEIVE CLOCK The on board oscillator U28 is used for generating a transmit receive clock as vvell as the on board clock for the Zilogs It is factory installed at 20 0 MHz and may be changed to accommodate a wide range of baud rates The desired baud rate is determined by the equation Baud rate Time Constant 1 Oscillator frequency of U28 Using the factory installed 20 0 megahertz oscillator frequency of U28 the following time constants will give the following baud rates Time Baud Constants Rates 307 2K 256 76 8K 38 4K 2048 Any standard dip oscillator 8 pin or 14 pin will fit into the socket of U28 thereby changing the on board transmit receive clock 4 1 IRQ LEVEL SELECT JUMPERS J6 These jumpers are used to select or determine the interrupt request level used by this board They use a binary encoded method with jumpers for pins 1 and 2 being the LSB of a 3 bit value If none of the jumpers are in this is a level select of the lowest priority 7 If all the jumpers are installed this is a level select of 0 and invalid level select Examples of different level select configurations are as follows a Set for b Set for c Set for Level 5 Level 2 Level 3 Pint DO 2 e o o Pin5 loo oo oo 4 2 BASE ADDRESS JUMPERS J1 JA J5 Base address selection involves 3
19. D5 RW TxC Interrupts D6 RW RxC Interrupts D7 RW RxC Interrupts 3 1 6 17 TX RX DATA REGISTER ADDRESS 1X000 3 1 6 17 1 Low Offset Address 0x40 D0 7 RW Tx Rx Data 0 7 3 1 6 17 2 High Offset Address 0x42 D0 7 RW Tx Rx Data 8 15 3 1 6 18 RECEIVER MODE REGISTER ADDRESS 10001 3 1 6 18 1 Low Offset Address 0x44 Rx Enable DIRW DORW EE Disable Immediately 1 Disable After Reception 0 1 Enable Without Auto Enables Enable With Auto Enables Rx Character Length DARW D3RW D2RW Bits pd DM ERE AR D5 RW Rx Parity Enable Rx Parity Sense Even E 10 1 E E NI Spe 3 1 6 18 2 High Offset Address 0x46 D0 RVV Queue Abort D1 RWRx CRC Enable Revision B User Manual for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 34 D2 RVV Rx CRC Preset Value Rx CRC Polynomial eo CRCCCHT 1 CE O E32 00 168602 u Rx Data Decoding EE F 10620 0 50 0 1 NZLE 5008015101 NRZIMak 0 1 NRZISpee L1 0 BiphaseMark L1 0 1 BiphaseSpace 1 1 Biphaselevel 3 1 6 19 RECEIVE COMMAND STATUS REGISTER ADDRESS 10010 3 1 6 19 1 Lovv Offset Address 0x48 D0 RO Rx Character Available D1 RVV Rx Overrun D2 RVV Parity Error Frame Abort D3 RO CRC Framing Error D4 RVV Rx CV EOT EOF D5 RVV Rx Bre
20. HAPTER 1 INTRODUCTION 1 0 INTRODUCTION The VME S104 interface card is capable of transmitting and receiving serial data generating interrupts and providing loop back testing This card provides the following specific functionality a VMEbus Interface 1 6U card single slot IEEE ANSI 1014 compliant A16 D16 support or better 2 VMEbus interrupter functionality 3 Jumper selectable configuration of the interrupt level and programmable interrupt vectors 4 FIFOs 32K x 8 bit are provided for data transmit and for data receive to increase the size of the transmit and receive buffers 5 User interface signal connections are provided via 4 connectors on the front panel 6 All data transfers to from the FIFOs will be via host CPU writes reads i e the board does not include a VME DMA controller hence this board cannot act as a VME bus master 7 The card also provides for self test loop back for verification of proper operation b The following two modes of loop back testing will be supported 1 internal loop back testing does not drive cable 2 external loop back testing via an external loop back test cable 1 1 FUNCTIONAL DESCRIPTION As shown in the functional block diagram see Figure 1 1 1 this board includes the following VMEbus slave interface VMEbus interrupt module board control status registers transceiver control logic LEDs for board status indication an oscillator for synchroniz
21. OF EOM Polynomial Tx CRC EE JI JERCCCITT Ee pE 1 90 0 Jeres Tx Data Encoding cep 29 340 INRA 0 EE EE 0 1 ET 00 5010158511 NRZMak 90 508011 NRZiSpee 0 o Biphase Mark 8 1 1 Biphase Space Pp 1 1 Biphase Level 3 1 6 26 TRANSMIT COMMAND STATUS REGISTER ADDRESS 11010 3 1 6 26 1 Low Offset Address 0x68 DORO Tx Buffer Empty D1 RW Tx Underrun D2 RO All Sent D3 RW Tx CRC Sent D4 RW Tx EOF EOT Sent D5 RW Tx Abort Sent D6 RW Tx Idle Sent D7 RW Tx Preamble Sent 3 1 6 26 2 High Offset Address 0x6A Tx Idle Line Condition I ER i 1 1 1 SYNC Flag Normal 1 Alterating 180 0 j AlZeo 1 AllOnes 0 B 0 Reserved 1 Mark amp Space Space EA ER ALAS 0 Ti D3 RW Tx Wait on Underrun Revision B User Manual for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 Transmit Command o o NullCommad 8972 o o 1 Reserved 820888 o 1 reset CRE o 0 1 1 Reserved 888 1 SelecrFIFOStaws 2 t 1 O SelectFIFOIntermptlevel 1 1 1 SelecrFIFORequestLevel topo 0 Send Frame Message 0 2 0 0 1 Sendaboe topo 1 O0 Reserved 080882 500171 1 Reserved 00 srl 0 O RestDLElhiit 67 srl 1 1 0 f 1 Set DLE Inhibit 08087
22. Outpu 0 Rx Request Output 1 Of Output DCD Pin Control 0 CD Input 1 DCD SYNCInpu to Of Output CTS Pin Control Sip 0 1 Su to Of Output 3 1 6 13 INTERRUPT CONTROL REGISTER ADDRESS 01100 3 1 6 13 1 Low Offset Address 0x30 D0 RW Device Status IE D1 RW I O Status IE D2 RW Transmit Data IE D3 RW Transmit Status IE D4 RW Receive Data IE D5 RW Receive Status IE IE Command Revision B User Manual for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 Null Command 1 Nul Command ro RestE 00 3 1 6 13 2 High Offset Address 0x32 D0 RVV Reserved VIS Level po 10 P 0 10 NA AE ai po 10 X VOStausandAbove po Transmit Data and Above 10 Transmit Status and Above 1011 Receive Data and Above 1 jo Receive Status Only D7 RW MIE D6 RW DLC D5 RW NV D4 RVV VIS 3 1 6 14 DAISY CHAIN CONTROL REGISTER ADDRESS 01101 3 1 6 14 1 Lovv Offset Address 0x34 D0 RW Device Status IP D1 RW VO Status IP D2 RW Transmit Data IP D3 RW Transmit Status IP D4 RW Receive Data IP D5 RW Receive Status IP IP Command NulCommad 1 Reset Pand TUS E ETA 3 1 6 14 2 High RW Offset Address 0x36 D0 RW Device Status TUS D1 RW VO Status TUS D
23. Source 0 CTROOup 1 CTRIOupt 1 feen BRG1 Clock Source CTROOWwpue 1 CR Opu 1 RxPn CRTO Clock Source LBRGOOupu 1 LBRGIOutput 1 RxCPin il CTRI Clock Source Disabled 1 Disabled Pp RCPn 3 1 6 10 HARDWARE CONFIGURATION REGISTER ADDRESS 01001 3 1 6 10 1 Low Offset Address 0x24 D1 RW BRGO Single Cycle Continuous DO RW BRGO Enable Rx ACK Pin Control Revision B User Manual for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 D3RVV D2RVV 3 StateOutput 1 Rx Acknowledge Input 1 0 jOuptO 8 D5 RW BRGI Enable D4 RW BRGI Single Cycle Continuous Tx ACK Pin Control 13 SiteOupu 0 1 TxAcknovvledge Input 9 to Of Output 3 1 6 10 2 High Offset Address 0x26 DPLL Mode o Disabled o 1 NRZNRZ 0 1 Biphase Mark Space PLL Clock Rate 32xClock Mode 1 l xClekMoe to 8xClock Mode D5 RVV Accept Code Violations D4RW CTRI Rate Match DPLL CTRO CTRO Clock Rate D7 RW D6 RW 1 32x Clock Mode 8x Clock Mode 1 4x Clock Mode EE DANI 1 l xClockMode IE EI Revision B User Manual for the VME SIO4 Board Revision A Gener
24. TER SAME FORMAT FOR CHANNELS 1 3 FIFO STATUS REGISTERS DO Tx FIFO Empty L 0 indicates that the Tx FIFO is empty 1 indicates that the Tx FIFO is not empty DI Tx FIFO Almost Empty L 0 indicates that the Tx FIFO is almost empty 1 indicates that the Tx FIFO is not almost empty D2 Tx FIFO Almost Full L 0 indicates that the Tx FIFO is almost full 1 indicates that the Tx FIFO is not almost full D3 Tx FIFO Full L 0 indicates that the Tx FIFO Full L is full 1 indicates that the Tx FIFO Full L is not full D4 Rx FIFO Empty L 0 indicates that the Rx FIFO is empty 1 indicates that the Rx FIFO is not empty D5 Rx FIFO Almost Empty L 0 indicates that the Rx FIFO is almost empty 1 indicates that the Rx FIFO is not almost empty D6 Rx FIFO Almost Full L 0 indicates that the Rx FIFO is almost full 1 indicates that the Rx FIFO is not almost full D7 Rx FIFO Full L 0 indicates that the Rx FIFO is full 1 indicates that the Rx FIFO is not full D8 D15 Reserved Revision B User Manual 16 for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 3 1 5 1 INTERRUPT CONTROL STATUS REGISTERS Interrupt Control Register D0 D1 D2 D3 D4 D5 D6 D7 DS D9 D10 D11 D12 Enable Channel 0 Sync Detected 1 will enable this board to generate an interrupt when a sync word is detected 0 will disable this board from generating an
25. VME SIO4A User Manual Manual Revision B General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 Fax 256 880 8788 URL http www generalstandards com E mail techsupport generalstandards com Revision B User Manual for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 PREFACE Copyright O 1997 General Standards Corp Additional copies of this manual or other General Standards Corporation literature may be obtained from General Standards Corporation 8302A VVhitesburg Drive Huntsville Alabama 35802 Telephone 256 880 8787 Fax 256 880 8788 Company URL www generalstandards com The information in this document is subject to change without notice General Standards Corporation makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Although extensive editing and reviews are performed before release to ECO control General Standards Corporation assumes no responsibility for any errors that may exist in this document No commitment is made to update or keep current the information contained in this document General Standards Corporation does not assume any liability arising out of the application or use of any product or circuit described herein nor is any license conveyed under any pat
26. ak Abort D6 RW Rx Idle D7 RW Exited Hunt 3 1 6 19 2 High Offset Address 0x4A DORO Short Frame CV Polarity D1RO Residue Code 0 D2RO Residue code 1 D3RO Residue Code 2 Receive Command D4WO D5WO BitMap 0 po 0 Nullcommad Lo po 0 1 Reserved psoe SQ 220 0 0 1 1 EnterHuntMode gr oq op MO N OU Reserved x 0 1 O0 f 1 Select FIFO Status Jo 1 1 Select FIFO nteript Level LO 1 1 1 selectF FO RequestLeveli Revision B User Manual for the VME SIOA Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 35 1 0 o Reserved 009898 1 0 0 T Reserved 009887 1 0 1 Reserved 000 0 o 1 f 1 Reserved 08080 1 1 0 Reserved 0 111 I Reserved D6 RO First Byte in Error D7 RO Second Byte in Error 3 1 6 20 RECEIVE INTERRUPT CONTROL REGISTER ADDRESS 10011 3 1 6 20 1 Low Offset Address 0x4C DO RW TCOR Read Count TC D1 RW Rx Overrun IA D2 RVV Parity Error Frame Abort IA D3 RW Status on Words D4 RW Rx CV EOT EOF IA D5 RW Rx Break Abort IA Do RW Rx Idle IA D7 RW Exited Hunt IA 3 1 6 20 2 High Offset Address 0x4E D0 D7 RW Rx FIFO Control and Status Fill Interrupt DMA Level 3 1 6 21 RECEIVE SYNC REGISTER ADDRESS 10100 3 1 6 21 1 Low Offset Address 0x50 D0 D7 RW RSYN 0 7 3 1 6 21 2 High Offset Address 0x52
27. al Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 29 3 1 6 11 INTERRUPT VECTOR REGISTER ADDRESS 01010 3 1 6 11 1 Lovv Offset Address 0x28 D7 D0 RW IV 0 7 3 1 6 11 2 High Offset Address 0x2A DORO IV 0 Modified Vector None 0 1 DeviceStatus 1 Suw 0 1 1 Transmit Data L 0 I I Receive Daa D4 D7 IV 4 7 3 1 6 12 I O CONTROL REGISTER ADDRESS 01011 3 1 6 12 1 Low Offset Address 0x2C RxC Pin Control JjlpitPin 9 0 JRxClckOupt 1 RxByteClockOutput 0 1 1 SYNCOupu 1 0 BRGOOuput topo 1 1 0 1 1 0 CTROuu lo 1 1 DPLERxOupu TxC Pin Control 50 10 hi 0 a Bin i 0 1 TxCockOuu 1 Tx Byte Clock Output 0 1 1 TxCompleteQutput topo JBRGOOupt topo 1 BRGlOup 1 1 CTR Oumu 1 1 1 DPLLTxOupu TxD Pin Control Revision B User Manual for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 D7RW D6RW TxData Output 1 3 State Output 1 jOuptO 3 1 6 12 2 High Offset Address Ox2E RxREQ Pin Control 3StaeQutput 1 RxRequestOupu to 0 TxREO Pin Control 13 State
28. ation of all logic on the board a cable data driver a cable data receiver receive voltage level converter a transmit FIFO a receive FIFO oe Sho o ao op 1 2 BOARD IDENTIFICATION Two 2 read only registers will be provided for board identification a manufacturer s ID and b board type These two registers will be modeled after the VXI specification The manufacturer s ID register will return OXFEAC when read while the board type register will return OxF4E4 when read These two registers will give an indication of basic board response Revision B User Manual 8 for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 sAoqu L puro sppuueyo su ewes peed 6544 1 VME Rd Zilog Ch 1 VME Wr Zilog Ch 1 3 g 8 5 215 ked ruso PH AINA BE bua ais ER i 450314 XHAM VINO 919 XL 100914 xi SWA uad S SO4H L MO 0314 X1 pu via L jeuuguz LER u Wa L UI E vrid L XH mat 45 1 b WO LADY 062912 ojo WO 0 40 xu b WING 0 42 XH DY 5 5 wid ou x1 pura VING 0 42 1 499 al lt N R u lt lt iz gt mim L g s e ENT H H ili epe a 919 sng tied 0 UI fous Old XH PH SINA 42 Odid JM Vind pa H xL E 049 1 XL JM INA E 049034 ti pH Yn 2220 br 042 jebessoy m 50314 0 auueyo 0 43 Boyz PH INA ea 149 Old xu PH INA
29. ble given that the software has chosen the cable as receive If the Zilog clock is chosen for the onboard transmit receive clock then the Zilog will get its clock from the local oscillator factory installed at 20 0 megahertz NOTE Care must be taken when setting these jumpers If the jumper is installed and the Zilog drives a clock out then a conflict between clocks will exist Revision B User Manual 13 for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 CHAPTER 3 PROGRAMMING 3 0 REGISTER MAP The register address map for the VME SI04 is shown belovv This board contains registers for Board Control I O Control FIFO Control Interrupt Control and Serial Controller Table 3 0 1 VME S104 Register Address Map e A o BED gister Name Board 0x00 DI DI6 RO BoardID_ 000 ID Control Status 0x02 DI6 RO Device Type Registers Oxoa 1016 RO Board Status Channel Control Registers FIFO 0x20 1016 RO Channel FIFO Status Status 0322 1016 RO Channel i FIFO Status Registers 0304 1016 RO Channel 2 FIFO Status 0x26 1016 RO 13 FIFO Status Sync Word Registers Interrupt Interrupt Control Control Status Registers Serial 0x20027E D16 BD Chamel0USCControl Controller 0x280 2EE D16 BD Chanel 1 USC Control Registers 0x300 37E_ D16 BD Channel 2 USC Control 380 D16 BD
30. d Address Register Address 0000 ee Re ee essesi Re Re AA ee ee 3 1 6 1 1 Low WO Offset Address 0x00 S 1 2 High WO Offset Address 0x02 s eer eee A ee ES re en d n 3 1 6 2 Channel Mode Register Address 00001 3 1 6 2 1 Low Offset Address 0x04 3 1 6 2 2 High Offset Address 0x06 3 1 6 3 Channel Command Status Register Address 0010 3 1 6 3 1 Lowe Offset Address 0X08 ai daniel deres eee e oer eode erbe ems 3 1 6 3 2 High Offset Address 0 22 eneve eren 3 1 6 4 Channel Control Register Address 00011 3 641 Low Offset Address OXOE EER YE RR SENE ETE YR ES 3 1 604 2 High Address 00011 iere eerte eie e aer eee ee ee eene ee 3 1 6 5 Primary Reserved Register Address 00100 3 1 6 5 1 Low Offset Address Ox10 c Ire REP ete reprae dne ee bet eme Revision B User Manual for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 3 1 6 5 2 High Offset Address 0x12 3 1 6 6 Secondary Reserved Register Address 00101 3 1 0 6 1 Low Offset Address 0x14 ave EER RE deeem kane iaa 3 1 6 62 High Offset Address 16 SE eet rrr en SG ENG ER Gee GN Ge nen SN e Ner ee eae ge s s R 3 1 6 7 Test Mode Data Register Address 00110 3 1 6 7 1 Low Offset Address 0x18
31. e RES UE E ERISQUE ETUR S 3 1 6 22 2 High Offset Address 0x56 2222 3 1 6 23 Receive Character Count Register Address 10110 3 1 6 23 1 Low Offset Address X58 3 1 6 23 2 High Offset Address 0x5A Ee AGE Ged Ee Ve t 3 1 6 24 Time Constant 0 Register Address IO ILI pa aaa ananas ene ene even ever ever eee eee 3 1 6 24 1 Lovv Offset Address Ox5C 3 1 6 24 2 High Offset Address OXSE Lis eise e ete Revision B User Manual 6 for the VME SIOA Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 3 1 6 25 Transmit Mode Register Address 11001 essent nennen nennen entente enne 37 3 1 6 25 1 Low Offset Address 0x64 eee tee er rete vetere Ree ERE e 37 3 1 6 25 2 High Offset Address 0x60 rs ee ee Eee tese tee pre rt rer T 37 3 1 6 26 Transmit Command Status Register Address 11010 cessere eere 38 3 1 6 26 1 Eow Offset Address Ox68 cc ORE RR HERRERA HII ES 38 3 1 6 26 2 High fiset Address OXOA cete ine EE pne tb EH RO nete RAR 38 3 1 6 27 Transmit Interrupt Control Register Address 11011 sese rene 39 3 1 6 27 1 Low Offset Address Ox6C HT 39 3 1 627 2 High Offset Address 0x6E onna e EE Net HERR PER eI ER RAM ESSE PEERS 39 3 1 6 28 Transmit Sync Register Address 11100 sss 39 3 1
32. ent right of any rights of others General Standards Corporation assumes no responsibility resulting from omissions or errors in this manual or from the use of information contained herein General Standards Corporation reserves the right to make any changes without notice to this product to improve reliability performance function or design All rights reserved No parts of this document may be copied or reproduced in any form or by any means without prior written consent of General Standards Corporation This user s manual provides information on the specifications theory of operation register level programming and installation of the VME SIO4 board Information required for customized hardware software development This manual assumes that the user is familiar with the VMEbus interface specification In an effort to avoid redundancy this manual relies on data books other manuals and specifications as indicated in the related publication section Revision B User Manual 2 for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 Related Publications The following manuals and specifications provide the necessary information for in depth understanding of the VMEbus and specialized parts used on this board EIA Standard for the RS 422 A Interface EIA order number EIA RS 422A VMEbus Specification Manual also known as IEC 821 BUS and IEEE P10114
33. eserved 608080 1 Load Tx Character Count Reserved 077 0 LodTC 58 S Select Serial Data LSB First Select Straight MemoryData 0 0 Reserved 00 4 i Get i p RePuge 1 0 Reserved 6000880 0 Reserved Selected upon reset 3 1 6 2 CHANNEL MODE REGISTER ADDRESS 00001 1 Es inci Ed 1 1 Revision B User Manual for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 22 3 1 6 2 1Lovv Offset Address 0x04 Receiver Mode o Asynchronous 1 JExtemalSynchroou 1 o lsochronous o 1 1 LAsynchronovs wh CV 0 1 0 0 Monosync 1 30 s Wer 20 a jn N R 52 La si p T ip e DTE i 8 01 1 1 1 TuasparentBisyne o MA p EG GE pod 217 dhe il ae 2 235 2208023 topo 1 Reserved L1 0 1 1 Reserved 0 srl 1 0 0 Reserved pop TOA 0 an Reseed 1 O ib Reserved o Rx Submode D6RW D5RVV HE TEGE 14 0 3 1 6 2 2High Offset Address 0x06 Transmitter Mode 0 Asynchronous 0 LI Reserved 9 o 1 Imsohonus 7 0 0 0 1 Asyhonos wih CV l 1 Bise EE EI 1 9 0 I 0 INP S 315 O 1 T sie ge 3 1 Reserved 1 1 0 HDLCLoop 5 o 22 b s
34. g the source of the interrupt is not present D3 Channel I Tx FIFO Empty Interrupt If this interrupt is enabled 1 indicates an interrupt has occurred 0 indicates an interrupt has not occurred If this interrupt is not enabled 0 indicates the current status of this interrupt source 1 being the source of the interrupt is present 0 being the source of the interrupt is not present D4 Channel 2 Sync Detected If this interrupt is enabled 1 indicates an interrupt has occurred Revision B User Manual 18 for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 D5 D6 D7 D8 D9 D10 D11 0 indicates an interrupt has not occurred Tf this interrupt is not enabled 0 indicates the current status of this interrupt source 1 being the source of the interrupt is present 0 being the source of the interrupt is not present Channel 2 Tx FIFO Empty Interrupt If this interrupt is enabled 1 indicates an interrupt has occurred 0 indicates an interrupt has not occurred If this interrupt is not enabled 0 indicates the current status of this interrupt source 1 being the source of the interrupt is present 0 being the source of the interrupt is not present Channel 3 Sync Detected If this interrupt is enabled 1 indicates an interrupt has occurred 0 indicates an interrupt has not occurred If this interrupt is not enabled 0 indicates the current status of thi
35. hanged to RO Sept 25 2003 cleaned up Address Jumper Tables Corrected error where text did not match jumpers shown Changed Manual Revision to B Revision B User Manual 4 for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 TABLE OF CONTENTS CHAPTER 1 INTRODUCTION eesovsesvveveeveveverevnenevenevnnensenevnnensenneenenevenevnnennennnnnennenesenevnnennennnnnevnenesenenenennennennennee S 1 0 INTRODUCTION ae 8 1 1 FUNCTIONAL DESGRIPTION tete eh b een ratas PO Febr 8 1 2 BOARD IDENTIPICATION ente ai 8 1 3 BOARD CONTROL REGISTER generi eto exei DA ohai 10 1 4 BOARD STATUS e E eee ec RAR dd 10 1 5 SYNC WORD SELECTION 2 tpe eei a ad 10 1 6 DATA REGEPBTION sesa sis 5 a 10 1 7 DATA TRANSMIT EO ide eec tete er deeper ble s N OE AE 10 1 8 EOOP BACK TESTING i ue eet tees eme a KOEN HET 10 1 9 ERROR DETECTION trn p teet PR ERE CERE A e ERE MT GI GER UR e Eo er ERR z 10 110 INTERRUPT S ent GEE Og SEK ATE Rep ERE 10 1 11 DIAGNOSTICEED DISPLAYS GE eiie cet n L L een R s b n 11 1 12 CABLE INTERFACE CONNECTIONS necne an eienaar ie e e EREKE EE aE ESES E CENERE EREKE 11 CHAPTER 2 THEORY OF 2 12 2 0 THE BOARD INTERPFACB ettet lesan eet ee rent s e EN o E SE
36. i Tx Submode Revision B User Manual for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 3 1 6 3 CHANNEL COMMAND STATUS REGISTER ADDRESS 00010 3 1 6 3 1Lovv Offset Address 0x08 Reserved Loop Sending On Loop HDLC Tx Last Character Length i 2RM 3RW y ELEK D0 RO Tx ACK DI RO Rx ACK 3 1 6 3 2High Offset Address Ox0A D2 RW Clocks Missed Latched Unlatch D3 RW Clocks Missed Latched Unlatch D4 RW DPLL in Sync Quick Sync D5 WO RCC FIFO Clear Do RO RCC FIFO Valid D7 RO RCC FIFO Overflow DLL Adjust Sync Edge DIRW DORW BothEdges Rising Edge Only Falling Edge Only Adjust Sync Inhibit Revision B User Manual for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 3 1 6 4 CHANNEL CONTROL REGISTER ADDRESS 00011 3 1 6 4 1 Low Offset Address Rx Status Block Transfer D7RW D6RW NoStatus Block H RE One Word Status Block 930 1 Two Word Status Block Reserved D5RW Wait for Rx DMA Trigger D0 4 RW Reserved 3 1 6 4 2High Address 00011 Tx Status Block Transfer Offset Address 0x0E NoStatus Block 1 One Word Status Block 1 Two Word Status Block D4 RW Tx Flag Preamble D5 RW Wait for Tx DMA Trigger Tx Prea
37. interrupt when a sync word is detected Enable Channel 0 Tx FIFO Empty Interrupt 1 will enable this board to generate an interrupt when the Tx FIFO is empty 0 will disable this board from generating an interrupt when the Tx FIFO is empty Enable Channel 1 Sync Detected 1 will enable this board to generate an interrupt when a Sync word is detected O will disable this board from generating an interrupt when a Sync word is detected Enable Channel 1 Tx FIFO Empty Interrupt 1 will enable this board to generate an interrupt when the Tx FIFO is empty 0 will disable this board from generating an interrupt when the Tx FIFO is empty Enable Channel 2 Tx Sync Detected 1 will enable this board to generate an interrupt when a Tx Sync word is detected O will disable this board from generating an interrupt when a Tx Sync word is detected Enable Channel 2 Tx FIFO Empty Interrupt 1 will enable this board to generate an interrupt when the Tx FIFO is empty 0 will disable this board from generating an interrupt when the Tx FIFO is empty Enable Channel 3 Tx Sync Detected 1 will enable this board to generate an interrupt when a Tx Sync word is detected 0 will disable this board from generating an interrupt when a Tx Sync word is detected Enable Channel 3 Tx FIFO Empty Interrupt 1 will enable this board to generate an interrupt when the Tx FIFO is empty O will disable this board from generating an interrupt when the Tx FIFO is empty Enable Channel
38. interrupts for the onboard logic use the master vector register The interrupts for the Zilog use the Zilog vector registers All interrupts are mapped directly to the VME and they are prioritized via Round Robin going from 0 to 3 and then to the master board No tvvo levels of interrupts vvill occur at the same time The interrupt level is selected via jumper 2 2 DESCRIPTION OF DMA DMA for all channels is performed in the same manner The request is made that is one of the transmit or receive DMA request signals go active from the Zilog The onboard DMA logic will handshake with the Zilog to either acknowledge valid data going to the Zilog or to get receive data from the Zilog This activity will continue until the Zilog no longer needs DMA service or the external FIFOs can no longer comply If the Zilog no longer wants DMA it will remove its request and the DMA will stop The conditions at which the FIFOs can no longer comply are when during a transmit request and the transmit FIFO is empty or during a receive request when a receive FIFO is full Channel 0 and 1 operate using the same Zilog bus so therefore it must arbitrate between Channel 0 transmit and receive as well as Channel 1 transmit and receive This arbitration takes place without any software initialization If all four 4 DMA requests are active at the same time this will handshake one word for one request and then proceed to the next It will start with the receive data and
39. is not present Channel 1 Rx FIFO Almost Full Interrupt Revision B User Manual 19 for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 D12 D13 D14 D15 Tf this interrupt is enabled 1 indicates an interrupt has occurred 0 indicates an interrupt has not occurred Tf this interrupt is not enabled 0 indicates the current status of this interrupt source 1 being the source of the interrupt is present 0 being the source of the interrupt is not present Channel 2 Tx FIFO Not Empty Interrupt If this interrupt is enabled 1 indicates an interrupt has occurred 0 indicates an interrupt has not occurred Tf this interrupt is not enabled 0 indicates the current status of this interrupt source 1 being the source of the interrupt is present 0 being the source of the interrupt is not present Channel 2 Rx FIFO Almost Full Interrupt Tf this interrupt is enabled 1 indicates an interrupt has occurred 0 indicates an interrupt has not occurred Tf this interrupt is not enabled 0 indicates the current status of this interrupt source 1 being the source of the interrupt is present 0 being the source of the interrupt is not present Channel 3 Rx FIFO Not Empty Interrupt Tf this interrupt is enabled 1 indicates an interrupt has occurred 0 indicates an interrupt has not occurred Tf this interrupt is not enabled 0 indicates the current status of thi
40. it and Receive e Channel 1 3 Zilog uses the onboard OSC for Transmit and cable Receive clock for Receive e Cable Transmit clock will be onboard OSC 1 6 11 On Board 1 6 11 On Board Rx Tx Clock Rx Tx Clock R o 0 CO Do Chan 0 Clock Chan 2 Rx Clock oe oj e Chan 0 Tx Clock Chan 2 Tx Clock O oe O oe Chan 1 Rx Clock L Chan 3 Rx Clock L go O oo Chan 1 Tx Clock Chan 3 Tx Clock 5 10 15 5 10 15 J11 is used for Channels 0 and 1 J14 is used for Channels 2 and 3 Description of Jumpers shown above e Channel 0 2 Zilog uses the on board OSC for Rev and will generate and output a transmit clock of a software programmed frequency Channel 1 3 Zilog uses the enable Rx clock for both transmit and Rev e The transmit clock will be the same as the Rev clock e Channel 0 2 and 1 3 will use the cable Rev clock for Rev and will generate and output a transmit clock of a software programmed frequency Revision B User Manual 42 for the VME SIOA Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 4 4 THE CHANNEL PIN OUT JUMPERS 710 712 J13 J15 Jumpers J10 112 113 and 115 may be removed to allow wire wrapping to accommodate various pin out configurations t is the suggestion of GSC that any reconfiguration of the pin out should alvvays maintain paired signals on the cable i e the
41. mble Length 1 05 1 EE IE 0 0 HT RT gt ee 1 Tx Preamble Pattern All Sync D1 RW D2 RW All Zeros o ANZeros Ones 1 Alternating 1 amp 0 Alternating 0 amp I RW D0 RW Tx Shaved Bit Length Async Only 3 1 6 5 PRIMARY RESERVED REGISTER ADDRESS 00100 3 1 6 5 1Lovv Offset Address 0x10 D0 D7 RW Reserved 3 1 6 5 2High Offset Address 0x12 Revision B User Manual for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 D0 D7 RVV Reserved 3 1 6 6 SECONDARY RESERVED REGISTER ADDRESS 00101 3 1 6 6 1Low Offset Address 0x14 D0 D7 RW Reserved 3 1 6 6 2High Offset Address 0x16 D0 D7 RW Reserved 3 1 6 7 TEST MODE DATA REGISTER ADDRESS 00110 3 1 6 7 1 Low Offset Address 0x18 D0 D7 RW Test Data 0 7 3 1 6 7 2High Offset Address Ox1A D0 D7 RW Test Data 0 7 3 1 6 8 TEST MODE CONTROL REGISTER ADDRESS 00111 3 1 6 8 1Low Offset Address 0x1C Test Register Address Lo 0 0 Nulladdress 0 0 HighByteofShiftes E o0 MN PERE Byte gt 00 85 0 o0 o X f NRL RXFIFOWritey 1 Clock Multiplexer Outputs 1 CTRO and CTRI Counters DELL State 2 0 1 j LowByteofShiters 1 CRCBye 2 0 TX FIFO Read 0 1 Reserved 6 1 WO
42. n below Revision B User Manual 11 for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 CHAPTER 2 THEORY OF OPERATION 2 0 THE BOARD INTERFACE This board operates as an interface for two Zilog Z16C30s giving it Quad Channel capabilities The Zilogs are mapped into the base address of this board and all reads and writes are PIOs This board does not offer DMA across the VMEbus All references to DMA in this documentation are in reference to moving data from the external FIFOs into the Zilogs or from the Zilogs into the receive FIFOs by means of an onboard only DMA These FIFOs operate as additional buffering of 32 K bytes for both transmit and receive These FIFOs are in addition to the internal FIFOs of the Zilog however these FTFOs are not at the same address location To implement the use of the external FTFOs the software must first initialize the Zilog to request DMA services for transmit or receive When the request is made the onboard logic will either move the data from the transmit FIFO into the Zilog or from the Zilog into the receive FIFOs depending on which request was made 2 1 INTERRUPTS The interrupts on this board are divided into two sections a Master Board Interrupts For use with conditions on the board not pertaining to the Zilogs b Zilog Interrupts For use with conditions within the Zilog not pertaining to the Board The
43. s interrupt source 1 being the source of the interrupt is present 0 being the source of the interrupt is not present Channel 3 Rx FIFO Full Interrupt Tf this interrupt is enabled 1 indicates an interrupt has occurred 0 indicates an interrupt has not occurred Tf this interrupt is not enabled 0 indicates the current status of this interrupt source 1 being the source of the interrupt is present 0 being the source of the interrupt is not present Revision B User Manual for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 20 3 1 5 3 Interrupt Vector Register This is a hardware modifiable Interrupt Vector Register to indicate the source of the interrupt encoding is as follows DO being the LSB D0 D2 Hardware Encoded 000 Enable Channel 0 Sync Detected Enable Channel 0 Tx FIFO Empty Interrupt 001 Enable Channel 1 Sync Detected Enable Channel 1 Tx FIFO Empty Interrupt 010 Enable Channel 2 Sync Detected Enable Channel 2 Tx FIFO Empty Interrupt 011 Enable Channel 3 Sync Detected Enable Channel 3 Tx FIFO Empty Interrupt 100 Enable Channel 0 Rx FIFO Not Empty Interrupt Enable Channel 0 Rx FIFO Almost Full Interrupt 101 Enable Channel 1 Rx FIFO Not Empty Interrupt Enable Channel 1 Rx FIFO Almost Full Interrupt 110 Enable Channel 2 Rx FIFO Not Empty Interrupt Enable Channel 2 Rx FIFO Almost Full Interrupt 111 Enable Channel 3 Rx FIFO Not Empty Interrup
44. s interrupt source 1 being the source of the interrupt is present 0 being the source of the interrupt is not present Channel 3 Tx FIFO Empty Interrupt Tf this interrupt is enabled J indicates an interrupt has occurred 0 indicates an interrupt has not occurred Tf this interrupt is not enabled 0 indicates the current status of this interrupt source 1 being the source of the interrupt is present 0 being the source of the interrupt is not present Channel 0 Rx FIFO Not Empty Interrupt Tf this interrupt is enabled J indicates an interrupt has occurred 0 indicates an interrupt has not occurred If this interrupt is not enabled 0 indicates the current status of this interrupt source 1 being the source of the interrupt is present 0 being the source of the interrupt is not present Channel 0 Rx FIFO Almost Full Interrupt If this interrupt is enabled J indicates an interrupt has occurred 0 indicates an interrupt has not occurred If this interrupt is not enabled 0 indicates the current status of this interrupt source 1 being the source of the interrupt is present 0 being the source of the interrupt is not present Channel 1 Rx FIFO Not Empty Interrupt Tf this interrupt is enabled 1 indicates an interrupt has occurred 0 indicates an interrupt has not occurred Tf this interrupt is not enabled 0 indicates the current status of this interrupt source 1 being the source of the interrupt is present 0 being the source of the interrupt
45. sets of jumpers They are J1 J4 and 15 14 is used to select A16 or A24 space and supervisory or non supervisory accesses The jumper for pins 1 and 2 is not installed for address space A24 and is installed for address space A16 Pins 3 and 4 of J4 is installed for non supervisory and not installed for supervisory Revision B User Manual 41 for the VME SIOA Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 Examples of the base address jumpers are shown below b Set for supervisory A24 space at a at a base address of 0x948000 a Set for non supervisory A16 space at a base address of 0xC000 Xue les ao e aise OO A10 E Aic 8 9 ENE E Of Au ne Al Jo o O Ol Al S Ais O OJ AD ee A18 Al3 e e aj O O A13 oo A19 e 9 ja AM Joo ao joo Al4 oo A20 O AIS joo azn joo as OO Az 9 spare Jo ol Az oo Spare O Az pare Jo ol A3 lOO Spare oo A23 ul n J5 4 3 THE ZILOG CLOCK SELECT JUMPERS J11 J14 The purpose of these jumpers is to select where the Zilog clock comes from or goes to If Zilog clock uses the onboard transmit receive clock or the cable clock then the jumpers should be installed If the Zilog is going to generate an output clock to the cable then some of the jumpers should not be installed The Zilog Clock Select Jumpers are shown below e Channel 0 2 Zilog uses the onboard OSC U28 for Transm
46. t Enable Channel 3 Rx FIFO Almost Full Interrupt D3 D7 Software Selectable D8 D15 Reserved 3 1 5 SERIAL CONTROLLER REGISTERS Contact your local Zilog Represenative for Data books and User manuals in reference to the Z16C30 USC Universal Serial Controller for a more detailed description of the following registers see also Related Publications section of this document 3 1 6 1 CHANNEL COMMAND ADDRESS REGISTER ADDRESS 00000 same format for Channels 1 3 USC Control Registers 3 1 6 1 1Low WO Offset Address 0x00 D0 WO Upper Lower Byte Select Always set to Lower for proper operation of this board D1 D5 WO Address 0 4 D6 VVO Byte VVord Access Always set to Byte for proper operation of this board D7 WO DMA Continue Revision B User Manual 21 for the VME SIOA Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 3 1 6 1 2High VVO Offset Address 0x02 Mode Control D0 WO 0 Normal Operation 1 Auto Echo 0 External Local Loop back 1 Internal Local Loop back D1 VVO 0 Normal Operation 0 Auto Echo 1 External Local Loop back 1 Internal Local Loop back D2 VVO Channel Reset Channel Command VVO D7 p D5 D4 D3 BiMp 0080 929 0 0 NulCommand 0 een Gratis Ek si 1 ResetHighestIUS o 01 gr O E EE IN po 1 o Trigger Chanel Load DMA TriggerTxDMA 0 Reserved 4 TxF FOPurge 0 R
47. will acknowledge one word for the receive of Channel 0 then one word of the receive for Channel 1 then one word for the transmit for Channel 0 then one word of the transmit for Channel 1 and then it will start over This transmission of data from one point to another will only occur if the FIFO s are in a valid state 1 e transmit FIFO must not be empty otherwise the handshake will not take place with the Zilog Then the Zilog will not get an acknowledge for its transmit request and will get no data The same is true for the receive FIFO If the receive FIFO is full the DMA will not remove data from the Zilog Therefore the Zilog will not get an acknowledge and will not have any data removed from it Channels 2 and 3 work in the same way but work on a different data bus Therefore DMAs for Channels 2 and 3 to or from the Zilog will not affect Channels 0 and 1 This means Channel 0 can run at full speed and Channel 2 can Revision B User Manual 12 for the VME SIO4 Board Revision A General Standards Corporation 8302A Whitesburg Drive Huntsville AL 3580 Phone 256 880 8787 run at full speed without interfering with each other The VME can read and write the Zilog during DMA cycles However it must wait until the end of the current DMA access when the DMA finishes its current access then the VME will be allowed onto the Zilog bus When the Zilog bus is free from the VME the DMA will restart The same holds true for interrupts If
48. y Interrupt 1 will enable this board to generate an interrupt when the Rx FIFO is not empty 0 will disable this board from generating an interrupt when the Rx FIFO is not empty D15 Enable Channel 3 Rx FIFO Almost Full Interrupt 1 will enable this board to generate an interrupt when the Rx FIFO is almost full O will disable this board from generating an interrupt when the Rx FIFO is almost full Interrupt Status Register Dual Purpose Bits ICR Interrupt Control Register DO Channel 0 Tx FIFO Sync Detected If this interrupt is enabled J indicates an interrupt has occurred O indicates an interrupt has not occurred If this interrupt is not enabled 0 indicates the current status of this interrupt source 1 being the source of the interrupt is present 0 being not true the source of the interrupt is not present DI Channel 0 Tx FIFO Empty Interrupt If this interrupt is enabled 1 indicates an interrupt has occurred O indicates an interrupt has not occurred If this interrupt is not enabled 0 indicates the current status of this interrupt source 1 being the source of the interrupt is present 0 being the source of the interrupt is not present D2 Channel 1 Tx FIFO Sync Detected If this interrupt is enabled 1 indicates an interrupt has occurred 0 indicates an interrupt has not occurred If this interrupt is not enabled 0 indicates the current status of this interrupt source 1 being the source of the interrupt is present 0 bein

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