Home

TDS-BD-APX500 Hardware User Manual

1. CI Gaber byp et Device Checksum TEO desien New Configuration File Delete set Programming Properties Set Erase Properties Edit Attached Flash Properties Launch File Assignment Wizard Figure8 20 Writing into the Device 5 6 Click OK p Device Programming Properties Device 1 Programming Properties Category Device I Attached FLASH M25P128 1 Passat Kan Value A Ee Se M ar ity General GPLD And PROM Properties Erase Before Programming a FPGA Device Specific Programming Proc Assert Cable INIT during programming After programming Flash automatically load FPGA with Flash Cee CER JC Figure8 21 Writing into the Device 6 Rev 0 01 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual inreviun a 7 The write operation into the Flash memory will start E ISE iMPACT Boundary Scan DoH AK3 ST PR IMPACT Flows enasx a 22 Boundary Scan 22 SlaveSerial 22 Direct SPI SystemACE Create PROM File PROM File Formar xc6slx150t bypass Right click device to select operations Configuration Operation Status IMPACT Processes Available Operations are Executing command mb Program mb Verify mb Erase mb Blank Check mb Readback mb Get Device Checksum mb Read Device Status e PROM File Formatter SPI Flash Single FPGA x Boundary Scan 111 SPI access core not detected SPI access core will be downloaded to the device to
2. DC me to w 9 men w ol ie 9 w 14 aao men no Me fen ws 12 99 Rev 0 01 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual inreviun a FPGA ADM Connector FPGA GND 131 132 GND 12 AJ34 LVDS PO 133 134 LVDS PI AH33 12 aN er iso Sey T_T eno 3 1 en 1 Power Supply The board provides 6V output to the P6V pin and 6V output to the N6V pins 3 3V outputs are also provided to the 3P3V pins The power status can be monitored by the adjacent LED ADM 3P3V A DS R120 SML 310MT_NMT 100 NMT A ADM P6V A D11 R122 SML 310MT_NMT 330 NMT SK ADM_N6V DU R121 SML 310MT NMT 330 NMT A Figure 7 7 ADM power LED 2 BD SEL 3 0 The board provides the board ID setting signal to the carrier board User can set the board ID of the carrier board though these pins by FPGA design 3 SCK SCS SDI SDO The board provides a SPI interface for accessing the device on carrier board for each connector User can set the parameter and read the status of the device on the carrier board though these pins by FPGA design 4 RSV 7 0 The board provides reserve pins for expansion in future 5 ECLKO_P N ECLK1_P N TRG IN TRG OUT CLK IN CLK OUT Component side The board provides the external clock and trigger output pins to carrier board The external clocks and triggers can be selected by setting the cross point device on this board
3. p wee e 0 s o wem Jul ur ano ga fee won a fem e a m uer fi wer ro F10 s n ve ee e v e Do eno eo wveo frem er tan LIO ai a o pes on 3 3 Do eno es eno 3s ae were es tap ANO 3 DC eba o mm Do fem pe mk freser eo m a mo Do fem f l sssewax ep es ms yy sen se ses Do rs am Do fees es ear apoy ene ov HT E 65 raso sov Rev 0 01 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual inreviun a Banno enno I I HO Pano ato re il TWRFAWC to TSS RT 2 appa mec u mo formen s me GN CLKO_M2C_P J9 CLKO M2C N a o owr Go a Amo LNCC 7 wre 4 mm DC 1 GND taon 3 eo wer spem 0 C10 LAOS P D10 LAO3_N LAO4 P se il van 0 uw 894 LAP 12 GND 84 LAN 13 Lao P ADo 35 __ CT T 14 LT Tx T eel st LAO7 N AG8 LA12 P GND aa ene ane NS a GND 17 LAIN AH 34 ANTO LA16P 18 enb 1 gt end 20 LASN a9 aa 33 AH13 LAzoP 23 GND YO o 25 LASN FIA 8335 3 AF11 EZ A OND oD 6 LAN Jaco ss 39 Aki2 LA25P 27 GM o 29 LA2AN JA3 83 33 AMO LP 30 O
4. twos pee 61 62 wwosPe axis 3 L5 nom bvosnee os er wosna aor se AA 5 wspo ans Dl a re eo 24 as LwsP 7 s wspo alte amp l eee a po 32 o ivos pie ss 8 wosp ame a DC de 8b ew o5 0 e 32 AGIG Lvos Pie s s wosp ar 2 DC doem 24 AD22 LVDS NiO 105 106 LVDS NH A21 22 DC en tor eb 22 AL20 WDS N8 111 112 WDS NS AN22 22 DC en no 86 23 AH24 WDS Np 117 118 LVDSN7 AN23 22 e no G5 Doo do GND 125 126 GND Rev 0 01 TOKYO ELECTRON DEVICE LIMITED inreviunB FPGA ADM Connector FPGA 1 AE WvosNa 120 190 Wosna aces a eo s me 12 AE27 LVDS PO 133 134 LVDS P1 AF26 12 12 AD27 LVDS NO 135 136 LVDS N1 AE26 12 labg er se aw fen 3 14 eno Table7 7 and Table 7 8 show pinout of ADM connector on mounting side for User FPGA U46 Table 7 7 ADM Connector Pinout Mounting Side CN6 o E 14 2 NV Too apay 3 4 apay 5 6 apay 7 8 apay 9 to apay 11 12 ino apay 13 t4 apay 15 16 apay 17 18 c Rev 0 01 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual inreviun a FPGA ADM Connector FPGA GND maa e Co lan emo see e mi
5. BD ID1 goma Rev 0 01 TOKYO ELECTRON DEVICE LIMITED inreviunB 7 13 PushSW The board provides 2 function PushSWs When the PushSW is held down it generates Low output on the associated FPGA pin VOC 2P5V VOC 2P5V VOC 2P5V FICUR XRST 74LVC1G08GW F1 UR RECFG Sw2 B3FS 1012 Figure 7 18 PushSW Structure Table 7 19 PushSW Pinout Table Device FPGA Swi Fei USER xRST Uds Art 19 swa Fri user RECFG Us m a 7 14 Slide SW The board provides 5 slide switches to select the impedance of the external signal and the program chain of the FPGA The 3 of 5 switches are used for selecting the FPGA program chain The others are used for setting the impedance of the external signals Figure 7 19 Impedance Selection of External Signal Rev 0 01 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual inreviun a FPI TOO SW9 L0 JTAG SET eee e WR MESA BANNA por a EEE sr 2 53 FPI ONLY Figure 7 20 Program Chain Selection 7 15 External Power Supply Connector The board provides an external power supply connectors VCC 12V J3 1 ND 2 12V 292132 2 Fan 3 2494 DGND Figure 7 21 External Power Supply Connector Structure Table 7 20 External Power Supply Connector Pinout Table 7 16 Battery Control The board provides the battery control soldering side connected to the VBATT T5 pin of the PCIE
6. EIN IRI EA EE N n o pie Lew we ow io ws aso so R S H sso 9 9 Wm d 43 mes sss w se penn mf 100 Table 7 8 ADM Connector Pinout Mounting Side CN7 CU E RR 35 4 E co s ew 3 apie vos eso 7 8 wospa ames 2 32 apis ivosno o 10 vosa A23 2 CUT Lee e 22 ANS tvos poe 13 14 tvospoo aa a 22 Ano vos nas 15 16 ivos Ng AHz2 2 Poor 1 24 ares vos poe 19 20 tvospar ames 23 sas os N36 21 22 wosne7 N25 2 0 Les 2 eo 1 en 2 3 95 eb s so Pay Rev 0 01 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual inreviun a nz woso s ivosna ames 2 32 AH18 LVDS P28 43 44 LVDS P29 AN28 23 32 AG18 LVDS N28 45 46 LVDS N29 AM28 23 3 ass vos p25 4 5 0s par 25 aves tvos 26 si se RSS LL EC s oo LVDS P24 LVDS P25 3 ae vos Nes s ss oon ao ns co ewn GND ND 65 66 G er e ios pei ARGS 3 6 70 ivosn akse 12 ean 73 74 vos peo anse i 75 7 wps Neo ame 38 7 Mew 32 ANT wospie 79 80 wosp m 2 em es es Peo as a Los is es 86 wosp aces 23 iw co o ev 1 DC fw es o 95 1 as an wosp s se ios pis AD 12 23 are vosme oo 100 wosnia ao 32
7. 35 Bi oe 5 6 Do Di2 35 35 m m 7 8 Dos os 3 fem 9 10 sw O Rev 0 01 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual inreviun a 7 10 USB UART The board provides a Mini Type USB interface connector CN9 as a means to communicate with an external device using the USB RS232C conversion device U42 for UART communication with FPGA U46 Table 7 16 UART Pinout Table USER FPGA U46 Pin No Bank Level Signal Name 7 11 LED The board provides 8 onboard LEDs These LEDs will light when Low is output from FPGA r i 1 AY die k e M ki pe ke b AR D27 D21 Ly H K D41 ass B Lx 4 Fee LED E FEZ LEDS Figure 7 16 LED Structure Table 7 17 LED Pinout Table FPGA FPGA No Dom emo E a e CET RU t a Det pr LEDa a e Det FP2 LED anas as Fea LED _ Ta per Fee tens IFE Rev 0 01 TOKYO ELECTRON DEVICE LIMITED inreviunB 7 12 DIPSW The board provides three 4 pole DIPSWs When the DIPSW is set to the ON side it generates Low output on the associated FPGA pin Ta DGND K CHAME GHS Figure 7 17 DIPSW Structure Table 7 18 DIPSW Pinout Table FPGA FP1 FP1 15 DIPSWO FPLASDIPSWO w26 14 FP1 15 DIPSW1 USER U46 FP1 15 DIPSW2 FP1 15 DIPSW3 FP2 15 DIPSWO FP2 15 DIPSW1 PCIE U48 FP2 15 DIPSW2 FP2 15 DIPSW3 BD IDO BD ID2 BD ID3
8. Cross Point p Swith NO NAV 4 4 1 pair DS90CP04 4 4 4 DINE Tm LI La Level FPGA1 SPI Bus A 4 4 Shift XC6VLX130T FFG 1156 4 oma eS fopaxefS pas hal o ho Board Select Level 4 shit FE 4 4 4 EH 3 3V Single End DQ DQS xDQS DM 88 SPI FLASH DDR3 2 5V Single End PER Ctrl 35 SO DIMM alr Diff Xtal S 1 5V Single End OS fo dl r A 2 NO ND 2 5V LVDS ola BIS Frat High Speed Differential O16 al5l lolo JTAG sw 4 DQ DQS xDQS DM 22 FPGA2 DDR3 4 XC6VLX75T FFG484 Ctrl 26 TED Component Data 8 NOR Ctrl 30 FLASH o o o x 3 KI d PCI Express Figure 4 1 Block Diagram TOKYO ELECTRON DEVICE LIMITED inreviunB 5 External View of the Board Figure 5 1 and 5 2 shows a board overview JTAG Chain FMC PWR USB User FPGA SW Jumper UART DIPSW AMD Connector DDR3 JTAG FMC Connector OSC FAN Side A SDRAM Connector HPC 156 25MHz CN LED LR gu Reset Recfg E dH PushSW 2 Power 7 i Connector OSC 100MHz OSC 25MHz Digital Connector Analog Connector DDR3 Socket Lane Select PCI Express USER FPGA PCIE Battery DIPSW Edge FLASH FPGA Holder USER EFRON Jitter PCIE FPGA OSC 33MHz Board ID OSC 200MHz Attenuator DIPSW DIPSW Figure 5 1 Component Side PCI Express PCIE FPGA FLASH SEL Edge FLASH SW LTEMA Impedance Select AMD Connector SW Side B Figure 5 2 Solder Side Rev 0 01 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware Use
9. FPGA and VBATT N8 pin of the User FPGA Use a CR1220 button battery This socket is not inserted at factory VBATT KEYSTONE 500 Figure 7 22 Battery Structure Rev 0 01 TOKYO ELECTRON DEVICE LIMITED inreviunB 8 Appendix 8 1 Creating a Configuration File This section describes how to create a configuration file Tool is ISE 11 4 Create a configuration file to write into the Flash memory 1 Double click ISE Tool El iMPACT 2 Click No E ISE iMPACT M 81d File Edit View Operations Output Debug Window Help Dojo anisar Ea Boundary Scan SystemACE Create PROM File PROM File Formatter E WebTalk Data Automatically create and save a project iMPACT Processes 08 x Do you want the system to automatically create and save a project file for you Don t show this message again save the setting in preference Console epneax Welcome to iMPACT iMPACT Version 12 4 dSLLLL a H 991819 Figure8 1 iMPACT Window 1 3 Choose Cancel E New iMPACT Project I want to auto project ipf v C Load most recent project file when iMPACT starts O create a new project Cip default ipf Browse Cancel Figure8 2 iMPACT Window 2 TOKYO ELECTRON DEVICE LIMITED inreviun R 4 Double click Create PROM File PROM File Formatter E ISE iMPACT M 81d File Edit View Operations Output Debug Window Help iMPACT Flows 08 x Gal Boundary Scan i r i a
10. User can set the function by FPGA design Please make caution to the pins named MODE LOAD SI SEL1 SCLK SELO Rev 0 01 TOKYO ELECTRON DEVICE LIMITED 25 TDS BD APX500 Hardware User Manual inreviun a U14 Esta _ un EX CLKILP 7 ETT OUT4 EE j RS TUO TA ds OTa H EX CLKI N Tr N outa Pic EX CLKON 3 ma ouma H I 2 3 OUT Te E as 29 e 13 PUTA 2 RM 100 1 N3 OUT3 Ri 100 1 ING OUT N3 our PA 1 LLI ma eura HI our 127 14 4 N2 OUT2 Ex ouri PLA RIS AH TA E mo out H I E macs name 1 gje om ME n o ma 24 int ouT1 46 m 100 1 INI QUTI 14 FP1 CLK MODE gt Pg KO 22 rso M POL TRO MODE RAE Rso 3 14 EPILCLK LOAD RSCLK dx IG ENG E MOE Da 14 FP1 CLK Sl cso S N ra ax 14 FPI CLK SCLK escik HA 14 FRA TRG SCLK E EE 5 SCLK escu lix 15 FPIZCLKCSELO 15 FP TRG SELO S 54 SELO 1 Figure 7 8 Cross Point Structure 6 RSTN TRG_IN TRG_OUT CLK_IN CLK_OUT Mounting side The board provides the reset signal trigger signal and clock signal for the control communication between this board and the carrier board User can set the pins by FPGA design 7 5 FMC Connector Interface The board provides a Samtec FMC High Pin Count J1 connectors Figure 7 9 show High Pin Count pinout respectively Notice All pins of HPC are not connected to the FPGA K J H G F F D C E A ILVREF B M2C GND VREFAM2C GND 2 GND CLK3 M
11. enable operations i INFO iMPACT Downloading core file C Xilinx 11 1 ISE spartan6 data xc6slx150t spi cor 1 Downloading core Console lt Console Errors Warnines Figure8 22 Write into the Device 7 Rev 0 01 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual inreviun a 8 If the write operation into the Flash memory is successfully completed a message Program Succeeded will appear e ISE iMPACT Boundary Scan Er File Edit View Operations Output Debug Window Help D8H X BXNALk Hae nm KK IMPACT Flows 09 x a Boundary Scan 23 SlaveSerial 22 Direct SPI E SystemACE a Create PROM File PROM File Formar xc6sIx1 50t bypass Right click device to select operations IMPAGT Processes Available Operations are mb Program mb Verify mb Erase mb Blank Check mb Readback mb Get Device Checksum mb Read Device Status Program Su Z PROM File Formatter SPI Flash Single FPGA 59 Boundary Scan Console 1 Programmed successfully PROGRESS END End Operation Elapsed time 662 sec lt Console Errors Warnings M Configuration Platform Cable USB I 6 MHz usb hs Figure8 23 Write into the Device 8 9 The data written in the Flash memory device is used for FPGA configuration using Master SPI The FPGA configuration can be initiated either by turning on the power switch of the board 10 The board provides a LED D34 for configuration status m
12. 2C P CLK MeC P GND 3L GND lT CLK3M2CN GND __ GU MOC N TND 4LCLK2 M C P GND CLKOM2CP ND 5 CLK2 M2C N GND CLKO M2C N GND eL GND I GND LAO P CC GND 7 I LAO2 P LAOON CC 8 I GND LAN GND 9 GND oo si JE VES 10 LA04 P LA N 11 GNO LAW N GND 12 GND GNO LAP GND 13 oP LAN 14 ite NO UDEN GND 15 GND CL cap T ASP q 16 S LAIT PO To LAI2N EI GNO 17 GND LAN _ GND ho be MeCN f G0 18 GND I GND AM6P GND EAN UP LAMP ee a 19 LAISP LAI6N I GND LAA N 20 GND LAISN GND GND LAIZPCC GNO 21 GND I GM LA20P I GND 22 LAIR B LAON 23 I GND AIN GND 24 GND SO 25 EARP CAZAN 26 OND LAZION QN 271 GND I GND AZS PT GND 28 LA24 P LAR N 29 I GND LA24N GND 30 GND GND LA29P GND 31 LA28P LA29N 32 GND LAS N GND L OND 33 GND I GND TAP GNO 34 LA3OP 35 I GND LAN GND X ME VS 36 ND ang OE JE VEGER ro 37 tas P i33 38 CON AN GOD GND 3 40 VIO B M2C GND GN LPC Connector LPC Connector LPC Connector LPC Connector Figure 7 9 High Pin Count Pinout 7 5 1 HPC Connector High Pin Count The board uses a High Pin Count connector Due considerations to the number of FPGA pins the column of E F J K pins are not connected This connector is interf
13. 3 3V output to the 3P3V and 3P3VAUX pins 3 3V and 2 5V output are also selectable for VADJ pins as shown in the following circuit diagram The target pins are E39 and F40 The voltage supply can be provided by short circuiting one portion of JP4 5 and JP9 10 respectively The power status can be monitored by the adjacent LED Caution Do not short circuit JP4 and JP9 on the same time and also JP5 and JP10 VEC 3P3V VOC 2P5V FMC VADJ n Ky 3510 J811 Ade Ade FMZ VADJ qu L DTG31dYKA hi FMC VADJ JP4 JP5 BNI JP9 JP10 SML 310YT d Figure 7 12 VADJ Structure Rev 0 01 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual inreviun a 7 VREF A M2C VREF B M2C The VREF A M2C terminal of the H1 pin can be monitored by PAD12 and the VREF B M2C terminal of the K1 pin by PAD13 8 VIO B M2C The VIO B M2C terminal of each J39 and K40 pin can be monitored by PAD14 7 6 DDR3 SDRAM The board provides one DDR3 SODIMM socket for User FPGA U46 The following pins are connected A 14 0 DQ 63 0 ODT 1 0 DQS 7 0 xDQS 7 0 DM 7 0 CK 1 0 xCK 1 0 CKE 1 0 xRAS XCAS xWE xCS 1 0 and BA 2 0 A 14 are a memory address expansion bit The board comes with a 1GB DDR3 so dimm using A 13 0 Specifications 1GB 128Mword x 8bit x 8bank 1066 7 7 7 Address Structure Bank 3bit Address 14bit Row address 14bit Column address 1 Obit Data Bus Structure Per byte data strobe with write and read
14. Create PROM File PROM File Formatter X WebTalk Data l f A BPI Parallel Daisy Chain pcie fpeabit 0x0000 0000 a E Ext 1 1 1 1 618 Lr 128M xcbvIx75t pcie fpqa bit D o zx is iMPACT Processes enax E Available Operations are E Generate Succeeded Ox07FF FFFF 4 M e PROM File Formatter BPI Flash Single FPGA Console 08 x Writing file C 1Xilinx1 12 4 ISE DS Project PC IE FPGA cfi A f f BATCH CND setCurrentDesign version O D11 v lt s gt El Console O Eros FY Warnings PROM File Generation Target Parallel PROM 26 239 328 Bits used File PCIE FPGA in Location C Xilinx 12 4 ISE_DS Project Figure8 13 iMPACT Window 13 Rev 0 01 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual inreviun 8 2 Writing a Configuration File into the Flash Memory Connect a Platform USB cable to the JTAG connector CN11 as shown in Figure 8 xx After powering on the board start the MPACT and write a configuration file into the Flash memory following the procedure described below FPGA JTAG THIS ELLEN Nhe CNIT Figure8 14 Onboard JTAG Connector 1 Double click Boundary Scan and then click Initialize Chain shown by the arrow ISE iMPACT M 81d Boundary Scan E File Edit View Operations Output Debug Window Help 0 x nau ofk ela nier IMPACT Flows 08x S Create PROM File PROM File Formatter
15. DQS Per byte data mask DM Figure 7 13 DDR3 SDRAM Socket Rev 0 01 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual inreviun a Table 7 10 DDR3 SO DIMM Pinout Table pao CA semis Tc om we somas Tool DQSO E26 DIFF SSTL15 T DCI SSTL15_ EE DCI xDQSO DIFF SSTL15 T DCI B25 SSTL15_T_DCI Dosi ser orrssnistoo vos bes sstuts t ocr Dos Der sets T pcr pas cos SSTLIS toe xDQS2 D30 DIFF SSTL15 T DCI D25 SSTL15_ G DCI DQS3 K18 DIFF SSTL15 T DCI D29 SSTL15 T DCI xDQS3 DIFF_SSTL15_T_DCI ER SSTL15_T_DCI DIFF SSTLIS T DEI Daio Das sms TOC DIFF SSTLIS T DOI SSTLIS T DG DQS5 G15 DIFF_SSTL15_T_DCI DQ12 G27 SSTL15_T_DCI xDQS5 F15 DIFF SSTL15 T DCI DQ13 B28 SSTL15 T DCI DQS6 DIFF_SSTL15_T_DCI DQ14 SSTL15_T_DCI xDQS6 DIFF_SSTL15_T_DCI DQ15 SSTL15_T_DCI DQS7 DIFF_SSTL15_T_DCI DQ16 SSTL15_T_DCI xDQS7 DIFF SSTL15 T DCI DQ17 SSTL15_T_DCI SSTLIS pars SSTLIS T DO SSTLIS para SSTLIS T DO SSTLIS 5020 SSTLIS T DO SSTLIS pagi SSTLIS T Dci SSTLIS Daga SSTLIS TDCi SSTLIS paga SSTLIS T DO SSTLIS Daga SSTLIS T DO SSTLIS pass SSTLIS T DG DT 00 SSTLIS T DO SSTLIS Dae SSTLIS T DO SSTLIS 5028 SSTLIS T DO SSTLIS Daga SSTLIS T DO SSTLIS paso SSTLIS T DO SSTLIS Dos SSTLIS T Dei SSTLIS pase SSTLIS TDCI SSTLIS pasa SSTLIS T DO SSTLIS pasa SSTLIS T DG SSTLIS pass SSTLIS T DO SSTLIS Dass SSTLIS T DO SSTLIS Das SSTLIS T DO SSTLIS pass SSTLIS T DG SSTLIS paso SSTLIS T DG SS
16. E LIMITED TDS BD APX500 Hardware User Manual 9 Default Switch Settings 9 1 Figure 9 1 shows the default switch settings See the switches enclosed in blue box M JP 4 5 JP9 10 renes i tt A E mo XILINX VIRTEMW EL Chi O ES agri hectare ol A lai RS DOSXdW 08 SOL UNIN2SUl ao T OE LECT Ares a a nn r TA rtu ET zx gt ha 1 dim N a a 3 L v 4 BRZ L I Noe T T 1 ba E 4 T sd E k F mel 2 D E SW6 SW7 i ac n pit ae WE La TF 3 TETE TET Mia cc Te Esta aar LI Minmi Espeto bs lib AAA AAA ETA i r O LE p Ka L Taa pr Pad Te a a L Ea Figure9 1 Default Settings component side Table 9 1 Default Settings av E EL 1 0 8 O H a E H sf TT Do H ES I H 8 8 H Rev 0 01 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual inreviun a TOKYO ELECTRON DEVICE PLD Solution Division URL http www inrevium jp eng x fpga board E mail psd support teldevice co jp HEAD Quarter Yokohama East Square 1 4 Kinko cho Kanagawa ku Yokohama City Kanagawa Japan 221 0056 TEL 81 45 443 4016 FAX 81 45 443 4058 Rev 0 01 TOKYO ELECTRON DEVICE LIMITED
17. IO Remarks Device No Device No Standard DDR nere n Uia s Uso Bio toS DDR3 clock for User FP21 200M CK LVCMOS15 BO FPGA a ec Main clock User 14 OSC 33M Us3 3 U48 T13 Lvemosas FPGA Local bus clock for User 15 FP1 LCLK U48 E11 U46 K13 LVCMOS15 i FPGA Local bus clock for PCIE rom FMC CN rom FMC ON INT_CLK Va Single end to Dit rom USER FPGA 34 EXCLKIN CNS 96 uta 5 LVITLG3 Extemalciockinput Rev 0 01 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual inreviun a No Signal Name l IO Remarks Device No Device No Standard single end to differential 36 EX_CLKI_N U13 5 U14 LVDS signal buffer External clock output via 39 EX CLK OUT U15 5 CN5 92 LVTTL33 single end to differential signal buffer USER FPGA ADM CN ADM CN dock CH A 49 ADMA cki N cna 69 U46 M22 LVDS olbek CH A S0 FPi ADM ASCK U46 AD34 CNS 89 LVCMOS25 SPLIF clock via ADM CN cock CH Csa abm B CKiN ON 69 U46 kas LVDS cloc CH B 55 Fri ADM B SCK U46 AGST CNG 89 LVCMOS25 SPLIF clock via ADM CN 60 FPISPI SCK_ vas ani uar 6 LVCMOS25 SPlinteraoe clock Rev 0 01 TOKYO ELECTRON DEVICE LIMITED inreviunB 7 3 Jitter Attenuator The board provides an onboard jitter attenuator generation circuit that uses IDT ICS874001AG1 05LF for PCI Express reference clock For details abo
18. M 83 ALTO LA9N 31 LM8P Amt 33 gt ond se LAN amm 35 O GND iI E end ss LAN APi2 ss 3 ANTS LAssP 36 COND O GND 38 LABAN AN4 35 o 76v 39 OND Lo GND 40 eva Rev 0 01 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual inreviun a 4 GBTCLKO M2C P N This signal is used for reference clock of MGT But it is needs to select this clock or 156 25MHz Oscillator 2 SCL SDA The board provides test points PAD to enable I2C communications with the FMC mezzanine card PADS PADS PAD SDA PAD4 PAD PADA PAD PAD PAD Figure 7 10 SDA SCL GA1 0 TDI TDO Circuit 3 GA 1 0 The board provides test points PAD for notification of an ID to the FMC mezzanine card 4 TDI TDO The board provides a loopback structure for JTAG communication from the FMC mezzanine card By default this loopback function is not provided because the R163 resistor is not installed 5 PG C2M PG M2C PRSNT_M2C_L The board provides test points PAD and pull up resistor to output to the FMC mezzanine card It also provides a similar structure for the column of F pins of the FMC connector The PG_M2C PRSNT M2C L also has a similar structure VEG 3P3V 1 G C1 r PAD2 PAD gem GND Figure 7 11 PG C2M PG M2C PRSNT M2C L Circuit Structure 6 Power Supply The board provides 12V output to the 12P0V pin and
19. Please refer to PCI Express specification Figure 7 14 and Table 7 12 show the setting of PRSNT pins Tonje Figure 7 14 PRSNT Setting Structure Table 7 12 PCI Express Lane Setting Table x8 Default ON 4 2 x4 Default ON BENE NE 3 x1 Default ON Unused 2 Power supply Power can be supply to the board from the PCI Express edge But they are unused in this design I VS FI IVA 12VF 12VP 3 3VA FEE 3 3A 3 348 Ii a 121 122 bud FT 2uFI25V bauF 25V 2uFI25V 2uFI25V ano s JTAG2 TCK ASH DGND DGND DGND JTAGITDI 7 JTAG4 TDO AL JTAGS TMS PES Figure 7 15 Power Supply from PCIE Edge 3 TCK TMS TDI TDO TRST WAKE RSVD They are unused in this design Rev 0 01 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual inreviun a 7 8 Analog Connector The board provides a 4 input 4 output port analog connector And there are 4 sets analog input and 4 sets analog output circuit on the board Table 7 13 shows the feature of the analog part Table 7 13 Feature of Analog Part Input JOE Analog Output Table 7 14 shows the pinout of the analog connector Table 7 14 Analog Connector Pinout Table AIN_0 AIN_1 7 9 Digital Connector The board provides a 4 input 4 output port digital connector to user FPGA U46 Table 7 15 shows the pinout of the digital connector Table 7 15 Digital Connector Pinout Table as at fem a pon Fs 5
20. TLIS paso SSTLIS T DG SSTLIS pas SSTLIS T DG Rev 0 01 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual BA2 K21 SSTL15 SSTL15 T DCI CKO B20 DIFF SSTL15 DQ45 D16 SSTL15 T DCI C23 SSTL15 SSTL15 T DCI xWE SSTL15 T DCI 7 7 PCI Express Edge The board provides one PCI Express Edge interface CN2 It can be linked as x1 x4 x8 Gen2 The PCI Express interface is on PCIE FPGA U48 Table 7 11 shows the edge pin assign of the PCI Express Edge Table 7 11 PCI Express Edge Pinout Table Pin Pin Bank No A Bank No No No o Lu AO pop o ni o pop o pop HI TDI e 3SMDAT Li a ems e B N 00 eea 9 TAGi TRSTA OT E cl Rev 0 01 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual E Pin Pin Bank No A Bank No No No KEY CU TO CT mem Do To a Doo em CU CU UI Do To Do PeRp2 25 DDD O 25 Pers o Doo eo PERS Ta smv DT ras ot Pas ew sc Do CU PER4 os GND i E MGTRXP3 114 MGTRXN3 114 Do CU PERS so GND ND MGTRXP2 114 MGTRXN2 114 MGTRXP1 114 0 CU 0 ae CU Do HU Rev 0 01 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual inreviun a 1 PRSNT1 PRSNT2 The signals are used for Hot plug detection
21. WebTalk Data Right click to Add Device or Initialize JTAG chain iMPACT Processes ensx Available Operations are e PROM File Formatter BPI Flash Single FPGA e Boundary Scan Console 09x BATCH CMD setMode bs A 011 011 2 v E gt Console O Errors EN Warnings No Gable Connection No File Open Figure8 15 Writing into the Device 1 2 Click No Auto Assien Configuration Files Query Dialog 9 Do you want to continue and assign configuration files e C Don t show this message again save the setting in preference Figure8 16 Writing into the Device 2 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual inreviun E 3 Abit jed file configuration window will appear Cancel it Select an FPGA and right click to select Add SPI BPI Flash ISE iMPACT Boundary Scan DER E File Edit View Operations Output Debug Window Help g El Xx BBX ss tx iMPACT Flows epnesax HE Boundary Scan 22 SlaveSerial Bal Direct SPI System CE Create PROM File PROM File Formar mmi Access eFUSE Registers Get Device ID Get Device Signature Usercode Add SPI BPI Flash Set Programming Properties Set Erase Properties Launch File Assienment Wizard Set Target Device iMPACT Processes Available Operations are Program eFUSE Registers wb Read eFUSE Registers mb Set eFUSE Control Register mb Read eFUSE Cont
22. aced as follows High Speed 8 10 ch TX 10 ch RX and 2 ch clocks Low Speed 34 pairs 68 signals and 2 ch clocks Table7 9 shows a HPC connector pinout for User FPGA U46 Rev 0 01 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual inreviun a Table 7 9 HPC Connector Pinout Table A II 6 GND 1 MGTRXP2 116 D5 DP1M2CP 2 GM Cl CT MGTRXN2 116 DO EG DP9 M2C P E3 MGTRXP1 116 GND DP9 M2C_N MGTRXN1 116 MGTRXPO 116 DP2 M2C P ee I MGTRXNO 116 DP2 M2G N 7 pj Kr o 8 SFe Mec MGTRXP3 115 GND 9 DP8 M2C N J4 MGTRXN3 115 MGTRXP2 115 DP3 M2C P 10 GND ICAO reel ao I DT cu fil permer i5 morens ae omen u mens MGTRXPO 115 N3 DP4 M2C P MGTRXNO 115 N4 DP4 M2C N 15 nos arameo e ms menes O NN A AS 2 8 eno ewe e a I a jo H6 MGTREFOLKOP 116 TE a H5 MGTREFCLKON 116 vemen w foneme e ow MGTTkN 116 82 BPI CaMN 25 CT S a IEA pp em Doo To CU em 0 NOS em I Do o es Dl Do To Rev 0 01 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual Inrevium ag 0E E RNC IN O NSAN E Do 5 PG C2M memes ie as oro came e Dm momento m IE mo A __ MGTREFCLKOP 115 NG 1 GBTCLKO_M2C N P5 MGTREFCLKON 115 mens ie s formere em o o Mermws 16 86 peo een 7 em o s mece i a
23. alfunctions due to connection to other devices Tokyo Electron Device Limited assumes no responsibility or liability for 1 Erasure or corruption of data arising from use of this product 2 Any consequences or other abnormalities arising from use of this product or 3 Damage of this product not due to our responsibility or failure due to modification This product has been developed by assuming its use for research testing or evaluation It is not authorized for use in any system or application that requires high reliability Repair of this product is carried out by replacing it on a chargeable basis not repairing the faulty devices However non chargeable replacement is offered for initial failure if such notification is received within two weeks after delivery of the product The specification of this product is subject to change without prior notice The product is subject to discontinuation without prior notice N 2 N Rev 0 01 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual inreviun a 1 Related Documents and Accessories Related documents All documents relating to this board can be downloaded from our website Please see attached paper on the products Board accessories FMC spacer set 2 Overview This board is the application board with Xilinx FPGA Virtex6 LX130T LX195T LX240T There are analog sample logic and digital processing logic on the board Feature B PCI Express BUS In
24. ate Address Figure8 11 IMPACT Window 11 13 Double click Generate File LE ISE iMPACT M 81d PROM File Formatter BPI Flash Single FPGA File Edit View Operations Output Debug Window Help DPR BS wis AN IMPACT Flows O x Boundary Scan pcie fpeabit Ox0000 0000 SystemACE Create PROM File PROM File Formatter WebTalk Data BS X BPI Parallel Daisy Chain Revision 0 v LJ E 128M xcBylx75t pcie_fpga bit 5 o ba iMPACT Processes ensx TEPEE E EE SUERTE nn as LO E mb Generate File Ox07FF FFFF v ue PROM File Formatter BPI Flash Single FPGA Console epneaex BATCH CMD set ttribute design attr RSPin value 00 ff BATCH CMD set ttribute design attr end ddress value 320c2b BATCH CMD set ttribute design attr end ddress value 320c2b v di lt E Console O Errors EN Warnines PROM File Generation Target Parallel PROM 26 239 328 Bits used File PCIE FPGA in Location C Xilinx 12 4 ISE_DS Project Figure8 12 iMPACT Window 12 Rev 0 01 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual inreviun a 14 If the configuration file has been successfully created a message PROM File Generation Succeeded will appear ISE iMPACT M 81d PROM File Formatter BPI Flash Single FPGA DER e File Edit View Operations Output Debug Window Help X Amie PRO eM iMPACT Flows enax 25 Boundary Scan SystemACE
25. ca BE Create PROM File PROM File Formatter IMPACT Processes ensx Console Dx Welcome to iMPACT iMPACT Version 12 4 Sia iai EEIEIEE Figure8 3 IMPACT Window 3 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual inreviun a 5 Choose BPI Flash Configure Single FPGA and then click the right pointing arrow Y PROM File Formatter Step I Select Storage Target Step 2 Add Storage Device s Step 3 Enter Data Storage Device Type Target FPGA SpartangE lieneral File Detai Value Xilinx Flash PROM Checksum Fill ec Non Vvolatile FPGA Storage Device bits 512K Value Spartan3AN L SPI Flash AS Rey ENE Output File Name Untitled Configure Single FPGA I Output File gt REA Configure MultiBoot FPGA Ii cation Ci silinx LL Z TSE DS BPI Flash Configure Single FPGA Configure MultiBoot FPGA Configure from Paralleled PROMs File Format Generic Parallel PROM Flash PROM File Property Use Power of 2 For Start Addr Number of Bitstream 2 Bitstream O Start Address O Bitstream 1 Start Address 675840 Add Non Configuration Data Files Yes Number of Data File Description If you are targeting the Xilinx XCF1 28X BPI Flash PROM or any 3rd party supplied BPI PROM select this storage device type To create a serial or parallel daisy chained PROM file Jead by an SPARTAN 3A device select this storage device type Figure8 4 IMPACT Window 4 6 On Storage Device bits sel
26. cause a malfunction fire or electric shock due to static electricity TOKYO ELECTRON DEVICE LIMITED inreviun R N Caution Do not use or place the product in the following locations Humid and dusty locations Airless locations such as closet or bookshelf Locations which receive oily smoke or steam Locations exposed to direct sunlight Locations close to heating equipment Closed inside of a car where the temperature becomes high Staticky locations Locations close to water or chemicals Otherwise a fire electric shock accident or deformation may occur due to a short circuit or heat generation Do not place heavy things on the product Otherwise the product may be damaged E Disclaimer This product is a board intended for Xilinx FPGA Virtex 6 Tokyo Electron Device Limited assumes no responsibility for any damages resulting from the use of this product for purposes other than those stated Even if the product is used properly Tokyo Electron Device Limited assumes no responsibility for any damages caused by 1 Earthquake thunder natural disaster or fire resulting from the use beyond our responsibility acts by a third party or other accidents the customer s willful or accidental misuse or use under other abnormal conditions Secondary impact arising from use of this product or its unusable state business interruption or others 3 Use of this product against the instructions given in this manual 4 M
27. ect Viretex6 and 128M and then click Add Storage Device E PROM File Formatter Step I Select Storage Target Step 2 Add Storage Device s Step 3 Enter Data i e eneral File Deta Walue Storage Device Type Target FPGA pre Al general ile Detai alue Xilinx Flash PROM sai Checksum Fil Non Yolatile FPGA Storage Device Bytes xcfl 28x 16M w Value Spartan 3AM sas SM Output File Name e SPI Flash Add Storage Device 28K 2utput File Name Untitled P56K i Configure Single FPGA Output File gt Configure MultiBoot FPGA oration Ci Wilinx112 41I5E DS BPI Flash Configure Single FPGA Configure MultiBoot FPGA Configure from Paralleled PROMs gt Generic Parallel PROM Flash PROM File Property File Format BIN Use Power of 2 for Start Addr No Number of Bitstream 2 Bitstream O Start Address O Bitstream 1 Start Address 675840 Add Non Configuration Data Files Yes Number of Data File Description In this step you will select the appropriate target device e Target FPGA This selection allows you to choose the specific FPGA you will be con figurine e Storage Device This selection allows you to choose the specific device memory density you are targetine e Add Storage Device After selecting the memory target use this button to add the device to the target Storage Device list below e Remove Storage Device Use this button to delete the target device from the list below Select the de
28. in which the file named above will be created e File Format PROM files can be generated in any number ofindustry standard formats Depending on the PROM file format your PROM programmer uses you output a MOS HEX UFP ISC or BIN file MCS is the most popular ISC is used when targeting programming flows that utilize IEEE Std 1532 Third Party socket based programmers usually accept any of the listed v Figure8 6 MPACT Window 6 8 Click OK Add Device start adding device file to 1 Revision U Figure8 7 iMPACT Window 7 Rev 0 01 TOKYO ELECTRON DEVICE LIMITED a TDS BD APX500 Hardware User Manual 9 Select a bit file to create a configuration file Add Device Zr JDP OG Project amp E z pcie fpeabit Recent E Yd FAX da lb n 24 xD 774 BD poiefpeabit ZAMORA FPGA Bit Files amp i Figure8 8 IMPACT Window 8 10 Click No Add Device 2 Would vau like to add another device file to Sf Revision 0 7 11 Click OK You have completed the device file entry A Glick Ok to continue Figure8 10 iMPACT Window 10 Rev 0 01 TOKYO ELECTRON DEVICE LIMITED XA TE IL TDS BD APX500 Hardware User Manual inreviun a 12 Click OK LE MultiBoot BPI Revision and Data File Assienment MultiBoot BPI Flash Revision Assignment Only Revision 0 Start Address cannot be changed Revision Start Address Hex j End Address Hex E 320EBB Upd
29. inreviunB TDS BD APX500 Hardware User Manual Rev 0 01 Rev 0 01 TOKYO ELECTRON DEVICE LIMITED inreviun R Revision History Rev 0 01 TOKYO ELECTRON DEVICE LIMITED inreviunB Table of Contents 1 Related Documents and ACCCSSOM CS iota sans CU SC ST RR 9 2 AL RR wW O 9 EEE 25 100 ee ra E 9 BD 10 o External View or NE PO ns NAAN AA MI IM EM AM ANAN NAA NAA 11 6 lt Te Te SCC Ca o q GG aka aaah aba 12 T Description OT Components estais iii ii ii A ennan a nne nn 13 fili FOR NN ur 13 Te KOK OTT 15 La Jier Atenualor ia 18 7 4 ADM Connector Interface rrrrrrnnrnannrnnnvnnvnnnrvrrnnnnernrnnnserrnnnenrnnnnennvnnnsenrnunsennnnnnsenvnnssenrnussennnenn 19 To FMC Connector ene iien a T 26 7 5 1 HPC Connector High Pin Count esse ee eee eee eee 26 AA DOR DRAN a 31 Tele PLENEN Jr 33 A Andog CONNEC nn EEE 36 O 6 1 89 015 110100 AA 36 7 10 DE BAWAT rv 37 7 11 A i e o A 37 7 12 38 7 13 A ee 39 7 14 Y A e 39 7 15 External Power Supply ConneCior ilaele 40 7 16 PN a 40 o A 41 8 1 Creating a Configuration File ii 41 8 2 Writing a Configuration File into the Flash Memory 48 So o ME EE EE E E E E OA 53 9 Default Switch A tds 54 9 1 Figure 9 1 shows the default switch settings e 54 Rev 0 01 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual Lis
30. nnector is interfaced as follows Differential 42 pairs 84 signals 2 ch clocks and 2 ch external clocks Single 1 ch SPI IF 1 ch ID set 1 pin reset 2 pins clock 2 pins trigger and 8 pins reserves Notice Reserve pins ID set pins and reset on component mounting side are connected together Table7 5 and Table 7 6 shows pinout of ADM connector on component side for User FPGA U46 Table 7 5 ADM Connector Pinout Component Side CN5 FPGA ADM Connector FPGA es o5 02 mor Rev 0 01 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual inreviun a FPGA ADM Connector FPGA GND AASS ew 7 7 43 Aes resp sei 79 so 81 82 35 arar cem sete es 9 39 ave resp sets es s pano qj er CU e wm so ow oo pow Sama x eso s CU EM E ELS to x e Table 7 6 ADM Connector Pinout Component Side CN4 PA a el E RR E a a wose 7 s wosem ACS 22 AD20 vos N4o o 10 Wosna abs 32 0 eo 7 7 eo I CUT 7 Peo DC iw 2 a aw ewn s o Peo CUT 95 1 s 3 aed Rev 0 01 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual inreviun a PD Poda eo Ca xem wosms a ios pee an 2 AE22 LVDS_N28 LVDS_N29 AG17 Co eno fs eno ot mes sl mes wm wos pes s s woo aca se LVDS N24 LVDS N25 pee eo mes 3 5 aces
31. onitoring Green D34 indicates that the configuration process has been successfully completed Rev 0 01 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual inreviun a 8 3 Configuration Time Time required to load configuration data into the Flash memory device can be changed by setting the configuration clock on ISE Tool Due to the operational frequency of BPI Flash select 16MHz or below Method 1 Right click Generate Programming File 2 Choose Process Properties 3 Choose Configuration Options 4 Change the Value of Configuration Rate Configuration Clock Frequency MHz Setting Processes m Process Properties Configuration Options Design Summary Reports Ha User Constraints i General Options Fece General Opens E Config JE PQ Synthesize KST Configuration Options pee mn d TIG Implement Design Startup Options Configuration Pin Program n ty Generate Programming File S et e DonePin Configuration Piri bong Er fy Configure Target Device SERIO JTAG Pin TOK i o Update Bitstream with Processor JTAG Pin TDI Lo a Analvze Design Using Chipscope JTAG Pin TOO JTAG Pin TNS ihused DB Pins UserID Code 8 Digit Hexadeci OxFFFFFFFF Figure 8 24 Changing Configuration Time Target for Configuration Time Configuration Rate 2MHz Configuration Time approx 17 seconds Configuration Rate 10MHz Configuration Time approx 6 seconds Rev 0 01 TOKYO ELECTRON DEVIC
32. pair If an unpleasant smell or smoking occurs disconnect the power supply If the product is used as is a fire or electric shock may occur Disconnect the power supply immediately After verifying that no smoking is observed contact our sales personnel for repair Do not disassemble repair or modify the product Otherwise a fire or electric shock may occur due to a short circuit or heat generation For inspection modification or repair contact our sales personnel Do not touch a cooling fan As a cooling fan rotates in high speed do not put your hand close to it Otherwise it may cause injury to persons Never touch a rotating cooling fan Do not place the product on unstable locations Otherwise it may drop or fall resulting in injury to persons or failure If the product is dropped or damaged do not use it as is Otherwise a fire or electric shock may occur Do not touch the product with a metallic object Otherwise a fire or electric shock may occur Do not place the product in dusty or humid locations or where water may splash Otherwise a fire or electric shock may occur Do not get the product wet or touch it with a wet hand Otherwise the product may break down or it may cause a fire smoking or electric shock Do not touch a connector on the product gold plated portion Otherwise the surface of a connector may be contaminated with sweat or skin oil resulting in contact failure of a connector or it may
33. r Manual inreviun a 6 Board Specifications Figure 6 1 shows the board specifications External Dimensions 312 00 mm W x 111 15 mm H Number of Layers 12 layers Board Thickness 1 6 mm Material FR 4 FPGA USER FPGA Xilinx XCOVLX130T FFG1156 PCIE FPGA Xilinx XCOVLX75T FFG484 NOR FLASH Spansion 529GL128P90TFIV1 SPI FLASH Numonyx ST M25PX16 VMW6TG FMC Connector High Pin Samtec ASP 134486 01 ADM Connector Hirose FX8C 100P SV2 91 FX8C 140P SV2 91 DDR3 SDRAM ELPIDA EDJ1116DBSE DJ F DDR3 SODIMM MT8JSF25664HZ 1G4 ADC 16 Bit 8 Channel ADI AD7689BCPZ DAC 16 Bit Serial Input ADI AD5754RBREZ P el e NP Ah o uai et iial E H rs T EUN at iy i Ka K e ali EL T parra Pa dens p ou um e re i WERT Ange E li di hal c an m A m l a E Ae mad Telge r 32 mm E mn E GR 13 E Bron inert EES Am ee fi ST OB IDE mlel juin i JF RI Or al EZ kasii gt imig e TH LER zs 3 7 EE e LL ka Ha i LM Ns mm RR ES R am leZ E 1 L gt Es d l 2 L A A i L 7 15 1 i 19 4 E d L Figure 6 1 Board Dimensions inclusive of wastable substrate Rev 0 01 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual inreviun B 7 Description of Components 7 1 Power Supply Structure Figure 7 1 shows the internal power supply structure EXT CN 12V Power distrib
34. r generation and distribution Table 7 1 Power Status LED 3 oe sav 33 powersupply an ADMON Gem 2 bio sov 60VpowersuppyonADMON Green a om 460V 460V powersupply on ADM CN Green 2 5V Vadj power supply on FMC CN Green 2 5V Vadj power supply on FMC CN Yellow 6 036 rav Aa power suppiyfom ATKCN Green Figure 7 3 Power Status LED TOKYO ELECTRON DEVICE LIMITED inreviunB 7 2 Clock Source The board provides the following clock sources ye PCIE CLKP N cara XX PCIE REFCLKPIN STX_REFCLK XX GTX REFC a FP1_SPI_SCK CI l F2_M_CK 1 K P LSO F2_M_XCK FP21_200M_CK OSC_33M F1 LCLK A F2 LCLK FMC_GBTCLKO_ FMC C M2C_P N OC DDR3_REFCLK_P N 00MHz FP1 MGT REFCLK PIN oa FP1 ECLKO PIN DK FP1 ADM A SCK FP1 ECLKO PIN A DIVI RSV CLK P N 3s ADM ECLK1 P N INT CLK ADM ECLKO P N ADM A CKO P N Gr E G y E V Vo Q E I INT CLK P N ups XX 4 EX CLKI P N LVTTL gt LVD EX_CLK_OUT EX_CLK_IN y e EX CLKO P N Figure 7 5 Clock Distribution Diagram TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual inreviun a Table 7 2 shows the details of onboard clock sources Table 7 2 Details of Onboard Clock Sources No Signal Name
35. rol Register mb Get Device Signature Usercode mb Read Device Status U PROM File Formatter SPI Flash Single FPGA P Boundary Scan Console done PROGRESS END End Operation Elapsed time O sec 14 Console Errors Warnings Configuration Platform Cable USB I 6 MHz usb hs man mo Figure8 17 Writing into the Device 2 3 Select a configuration file xxx mcs to write into the Flash memory Add PROM File FPA MOBMO O Project vr PCIE_FPGA mes 3 Recent 3 TAI FA EXaXvb 94 3563 5 e D 74 LSD Pret BEN PCIE_FPGA mcs Bag 0 Prt DEBO MOS Files mcs y Felt Figure8 18 Writing into the Device 3 Rev 0 01 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual inreviun a 4 Select the onboard Flash SPANSIONS29GL128P and click OK Select Attached SPI BPI Select the PROM attached to FPGA BPI PROM w 28F DAP3D e s 98FODAP30 Data Width 28F128P30 28F256P30 Select RS 1 0 b Pin Address Bits 28F512P30 28F640P30 48F4400P0 a a n LC PSPANSIONS29GL128P SPANSIONS29GL512P KOF128X Figure8 19 Writing into the Device 4 5 On the iMPACT Processes window double click Program E File Edt View Operations Output Debug Window Help 1g kl AB MFN IMPACT Flows O x al Boundary Scan SystemACE Create PROM File PROM File Formatter fH WebTalk Data ID er Erase Blank Check Readback
36. ser Manual List of Tables PEPYS 14 Table 7 2 Details of Onboard Clock Sources nennen nennen nnns nnns 16 Table 7 3 Jitter Attenuator Setting Table eee eee 18 Table 7 4 E SELx Function Setting Table nnn 18 Table 7 5 ADM Connector Pinout Component Side CNB sese eee aa 19 Table 7 6 ADM Connector Pinout Component Side CNA e sees eee 20 Table 7 7 ADM Connector Pinout Mounting Side CNG 22 Table 7 8 ADM Connector Pinout Mounting Side CN7 nnn 23 Table 7 9 APC Connector Pinout Table iius maa GA aa 27 Table 7 10 DDR3 SO DIMM Pinout Table 7 727 aa 32 Table 7 11 PCI Express Edge Pinout Table Xa 33 Table 7 12 PCI Express Lane Setting DE ve 35 Table 7 13 Feature of Analog Part iii 36 Table 7 14 Analog Connector Pinout Table nennen nnne nnnm nnne nnns 36 Table 7 15 Digital Connector Pinout Table nnn 36 Table 7 16 UART Pinout Tadeo Tm 37 Table yal LED Pinout Talante prendo ion 37 Table 7 18 DIFSW Pinout Tablas iaa a Ears eras 38 table 7 19 PusheW Pinout TADIG sses ANA a 39 Table 7 20 External Power Supply Connector Pinout Table aa 40 Rev 0 01 TOKYO ELECTRON DEVICE LIMITED inreviunB Introduction Thank you for purchasing the TDS BD APX500 board Before using the product be sure to carefully read this user manual and fully understand how to correctly use
37. t of Figures Figure 4 1 Block DIGGIAT irc RR Tn TTI 10 Figure 5 1 Component Side i 11 Figure 52 SOIC E AA 11 Figure 6 1 Board Dimensions inclusive of wastable subStrate 12 Figure 7 1 Power Supply Structure ooocccccncccccccooonccnnnncnonnnonnccnnonononnnnnnnnnnnnnonnnannnnnnnnnnnannnnnnnnnnnnns 13 Figure 7 2 Power Supply Diagram i 14 FIOUIO o nn O AAO 14 Figure TT ce ASS 15 Figure 7 5 Clock Distribution Diagram nennen nnne 15 Figure 7 6 Internal Structure of Jitter Attenuator aa 18 FOWE 727 ADI goo Tdi E E 25 Figure 7 8 Cross Poinit SUGA sanam ala 26 Figure 7 9 High Pin Count PiNOUt ii 26 Figure 7 10 SDA SCL GA1 0 TDI TDO Circuit 30 Figure 7 11 PG C2M PG M2C PRSNT M2C L Circuit Structure 30 Figure 7 12 VADJ SIrUcture ii 30 Figure 7 18 DDR3 SDRAM SOCK GSU escote 31 Figure 7 14 PRSNT Setting Structure aaa amma 35 Figure 7 15 Power Supply from PCIE Edge i 35 Figure T6 L ED SIUGIUNE rea 37 pau DIPA UGE AA T T 38 Fito TG PORVI 39 Figure 7 19 Impedance Selection of External Signal e aa 39 Figure 7 20 Program Chain Selection i 40 Figure 7 21 External Power Supply Connector Structure aeee 40 Figure 7 22 Battery Struclur anna 40 Rev 0 01 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware U
38. terface Gen2 5Gbps x8 BH FPGA XC6VLX130T FFG1156 FFG1156 footprint device compatible B DDR3 SDRAM SO DIMM PC3 12800 4GByte B DDR3 SDRAM Component 1333MT s 4Gbit B SPI FLASH 128Mbit 50MHz B ADM Connector x2 Data LVDS 44pair 200MHz Control LVTTL 17pin 100MHz Supply Power 3 3V 1A 6V 3A 6V 1A B FMC Connector x1 Multi gigabit signal 10pair 2 5GHz Data Clock signal 36pair 200MHz Supply Power 12V 1A 2 5V 1A 3 3V 4A B External USB CN UART B External Trigger Input x1 From ADM Connector B External Trigger Output x1 From ADM Connector B External Clock Input x1 From ADM Connector B External Clock Output x1 From ADM Connector B External Digital Input x4 B External Digital Output x4 MW External Analog Input x4 5V 16bit 250K sample B External Analog Ouput x4 5V or 5V 16bit output B LOCAL BUS signal 200MHz x 64bit B Xilinx FPGA can be AES security protected M Opin ATX CN 12V input Rev 0 01 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual inreviun a 4 Block Diagram Figure 4 1 provides a quick overview of the board block diagram FMC CN 1 pair 2 pair 34 pair Ext CLK OUT OUT TTL LVDS a Ext CLK IN TTL gt LVDS LVDS Swith 1 pair tpair Refcik1 DiffXtal Xtal J pair O 1 pair 4 4 1 pair 1 Ext Trig OUT TTL LVDS 1 pair Data LA GBT CLK Refcik0 1 pair Refcik1 1 pair 4 1 pai LVDS Toal 1 pair air i air Ext Trig IN TTLGLVDS
39. the product First read through this manual then always keep it handy SAFETY PRECAUTIONS Observe the precautions listed below to prevent injuries to you or other personnel or damage to property e Before using the product read these safety precautions carefully to assure correct use e These precautions contain serious safety instructions that must be observed e After reading through this manual be sure to always keep it handy The following conventions are used to indicate the possibility of injury damage and classify precautions if the product is handled incorrectly Indicates the high possibility of serious injury or death if the product is handled Danger N incorrectly Indicates the possibility of serious injury or death if the product is handled Warning incorrectly Indicates the possibility of injury or physical damage in connection with houses or Caution household goods if the product is handled incorrectly The following graphical symbols are used to indicate and classify precautions in this manual Examples Turn off the power switch Do not disassemble the product Do not attempt this Rev 0 01 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual inreviun a Rev 0 01 N Warning In the event of a failure disconnect the power supply If the product is used as is a fire or electric shock may occur Disconnect the power supply immediately and contact our sales personnel for re
40. ut setting values refer to the corresponding data sheet Figure 7 6 shows the part of internal block diagram contained in the IDT ICS874001AGI 05LF data sheet PLL Sep Pulp Output Divider 005 CLK Pulldown pu 04 54 CLK PNE Phase WCO 10 2 default Detector 490 640MHz 1141 Intemal Feedback 5 pag Pulkiown F SEL 1 0 PFPulupPuldoan i OE Pullup Figure 7 6 Internal Structure of Jitter Attenuator The frequency of a clock generated by this PLL can be changed by setting the onboard resistors This device connects clocks from the PCI Express Edge A13 A14 pin A reset to this device occurs during power up Table 7 3 Jitter Attenuator Setting Table HE TE PLLSEL PLL select pin High PLL enable Low PLL bypass F SEL1 Frequency select pin Refer Table 7 xx F SELO Frequency select pin Refer Table 7 xx OE Ree Output clock enable High Enable Default setting Table 7 4 F_SELx Function Setting Table Output Divider Output Frequency Range MHz F SEL1 F SELO iw iw 8 s m Hg iw 2 RRR High Hah 1 mes Rev 0 01 TOKYO ELECTRON DEVICE LIMITED inreviunB 7 4 ADM Connector Interface The board provides 2 set ADM connectors for carrying the analog board of ADM 414 One set CN4 CN5 is on component side and the other one CN6 CN7 is on mounting side The ADM connector on the mounting side is not installed in the state of the factory shipment This co
41. ution Required 8 79A Rev 0 01 Digital Part DC DC LTC3850 ma KEN Bulk 1 2 50A 55474 EE 12V gt 1 0V x Required Efficiency 80 Ar DC DC LTC3850 Bulk 1 25A peony Current 25A 12V gt 2 5V Required Efficiency 80 Requireg 1 102A 4 231A Required Bulk 2 25A 8 051A Current 25A 12V gt 1 5V Required Efficiency 80 pari 1 258A 6 051A LDO LP2997 1A pesi 1 5V gt 0 75V pagsama LDO LP2997 1A Required equire DC DC 1 000A 1 5V gt 0 75V 1 000A LTC3850 Bulk 1 25A pesa Current 25A 12V gt 3 3V l Required Efficiency 80 Required 1 468A 4 268A Bulk 2 25A ds i baa ho Required Pee Efficiency 80 1 3534 LDO LTC3026 1 5A ET 1 2V gt 1 0V 0 731A LDO LTC3026 1 5A i Required 0 998A 1 2V gt 1 0V 0 998A Analog Part Required DC DC Required 2 391A LTM4612EV 5A 3 000A si 12V gt 6VD Required Required q MPZ1608S221A 1816A Efficiency 90 MPZ16085221A 2000A DC DC Required m LTM8023EV 2A 1 0004 12V gt 6VD TE Required Required q MPZ1608S221A 0 575A Efficiency 8796 MPZ16088221A 1 000A Figure 7 1 Power Supply Structure TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual inreviun a Power Input Power is supplied through the 12V ATX power supply connector F1 GND GND D ND Figure 7 2 Power Supply Diagram Power Status LED The board provides 6 onboard LEDs to ensure the correct operation of powe
42. vice and click this button to remove it from the list Figure8 5 iMPACT Window 5 Rev 0 01 TOKYO ELECTRON DEVICE LIMITED TDS BD APX500 Hardware User Manual inreviun 7 Click the right pointing arrow Enter a name of directory and location in the Output File Name and Output File Location fields and then click OK PROM File Formatter Step Select Storage Target Step 2 Add Storage Devices Step 3 Enter Data Storage Device Type Target FPGA Mirte a ieneral File Detai Value Xilinx Flash PROM Checksum Fill Non Volatile FPGA Fr Storage Device Bytes 128M v Value Spartan3AN Configure Single FPGA 1 Configure MultiBoot FPGA 128M pe Ci Wilinx412 4ISE DS BPI Flash Configure Single FPGA Configure MultiBoot FPGA Flash PROM File Property Value Configure From Paralleled PROMs ip Generic Parallel PROM File Format MCS Data Width x8 Add Non Configuration Data Files No Description In this step you will enter information to assist in setting up and generating a PROM file for the targeted storage device and mode e Checksum Fill Value When data is insufficient to fill the entire memory ofa PROM the value specified here is used to calculate the checksum ofthe unused portions e Dutput File Name This allows you to specify the base name ofthe file to which your PROM data will be written e Output File Location This allows you to specify the directory

TDS-BD-APX500 Hardware User Manual

Contents

Download Pdf Manuals

Related Search

Related Contents