EVBUM2237 - NCN5193NG Evaluation Board User's Manual
Contents
1. sufficiently decoupled from the power supply such as by a large value ceramic capacitor 1 uF typical The switching output signal will have the desired DC low frequency component but also includes a lot of switching noise that needs to be filtered out before the signal is useful This means that an output low pass filter is required before the DAC output can be used Since the sigma delta modulator is designed for a bandwidth of 25 Hz it is advised that the corner frequency of the output filter is placed on this frequency For more information on how to design this filter see the section on slave implementation To achieve maximum accuracy of the DAC it is also advised to use a separate low noise reference as DACREF instead of tying this pin to Vpp and to keep the DAC line away from noisy signal lines Transmitter The TxA modem pin is accessible through pin 7 of IDC For certain applications it might be required to couple the transmit signal in the circuit by adding a series capacitor Note that this is a difference with the A5191HRTNEVB where this coupling capacitor was provided on the board The output on this pin is a 500 mVpp signal trapezoid waveform shown in figure 11 This pin can only drive impedances higher than 30 and as a consequence may need to be amplified The nominal frequency of the output is 1200 Hz for mark and 2200 Hz for space These frequencies are dependent on the accuracy of the NCN5193 c2. NCN5193NGEVB NCN5193NG Evaluation Board User s Manual Introduction The NCN5193NGEVB includes all external components needed for operating NCN5193 and demonstrates the small PCB surface area such an implementation requires The EVB allows easy design of HART implementations using NCN5193 Overview The NCN5193 is a single chip CMOS modem for use in highway addressable remote transducer HART field instruments and masters The modem and a few external passive components provide all of the functions needed to satisfy HART physical layer requirements including modulation demodulation receive filtering carrier detect and transmit signal shaping The NCN5193 also includes an internal 17 bit sigma delta modulation DAC for easy implementation of slave devices An SPI bus provides easy communication to this DAC and internal registers ON Semiconductor http onsemi com EVAL BOARD USER S MANUAL Features e Single chip Half duplex 1200 bits per Second FSK Modem Bell 202 Shift Frequencies of 1200 Hz and 2200 Hz 1 8 V 3 5 V Power Supply Transmit signal Wave Shaping Receive Band pass Filter Low Power Optimal for Intrinsically Safe Applications Compatible with 1 8 V or 3 5 V Microcontroller Internal Oscillator with 3 68 MHz Crystal Meets HART Physical Layer Requirements Includes 17 bit DAC for Slave Implementation Industrial Temperature Range of 40 C to 85 C Available in 32 pin QFN Applications HART M
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4. aluation board demonstrates alternatives A drawing of the board where the different the external components required for the operation of the IC sections are indicated is shown below We will cover the different sections below as well as possible SPI amp DAC I F Reference Voltages amp Bias Receive Filter Loop 1 Figure 3 Board Drawing with Indication of Different Sections http onsemi com 4 NCN5193NGEVB Power Supply and References Power Supply The NCN5193NGEVB is designed for a nominal voltage of 3 V However NCN5193 can be operated with a power supply of 1 8 V to 3 5 V R20 R19 Figure 4 Supply Voltage and Power on Reset Current consumption of the module is very limited making it ideal to be battery loop powered Measurements of the power consumption of the module are listed in Table 1 The module will use less power when clock signal is applied externally as this allows the modem to shut down the oscillator circuit As is to be expected a higher supply voltage increases current consumption The NCN5193 includes an internal voltage supervisor This will guarantee correct operation of the digital circuitry during start up All that is required for using this supervisor is an external resistor divider R29 The voltage supervisor compares the voltage offered by the resistor divider on the VPOR pin to AREF The resistor divider should be dimensioned such that at the desired turn on poin
5. e start bit transition The start bit transition and a later voltages for more information on these threshold level transition can be shifted in opposite directions for a total of settings When no signal or a signal of limited amplitude is 24 present the CD line is pulled down to 0 V The clock skew and jitter added together 18 45 which 18 The RxD TxD and RTSB signals implement a standard the amount that a bit boundary could be shifted from its UART interface at 1200 baud with start bit 8 data bits parity expected position UARTS that sample at mid bit will not be bit and stop bit 11 bit frame The RTSB signal disconnects affected However there are UARTs that take multiple the transmitter circuit when pulled high and should be held samples during each bit to try to improve on error low before any data is transmitted Data frames are not performance These UARTs may not be satisfactory buffered by the modem Instead data 1s transmitted bit by depending on how close the samples are to each other and bit Care should be taken to avoid clock skew in the receiving how samples are interpreted A UART that takes a majority UART If the same time base is used for both the modem and vote of 3 samples is acceptable the UART a 1 accurate time base may not be sufficient Even if your own time base 18 perfect you still must plan The problem is a combination of receive data jitter and clock on a possible 35 shift in a bit boundary since you don t
6. egative input and dimensioned to approach the impedance seen by the positive terminal The amplifier will then determine the current flowing through the loop by changing the base of a transistor in emitter feedback configuration The value for R is determined by the output range Vo max of the amplifier used max 20 mA It is often recommended to take a value as large as possible so that noise effects are minimal Typically the value of Rg is chosen equal to R7 The voltage over and combined should however be less than 12 V when the current setting is 20 mA Next the value of R4 is chosen depending on the most significant bit of the DAC 2 Vusg Ro 20 R When the DAC is not a switching topology we can now choose Ry and We have 500 mV R 1 2 R 7 max Where R 1 2 In practice C is chosen sufficiently large so that Z R4 Because the integrated DAC has a sigma delta output a circuit using the NCN5193 gets a bit more complicated as can be seen in Figure 16 We need to filter away high frequency DAC components but leave HART signals intact A simple RC filter is not sufficient since the output capacitor has low impedance for HART frequencies We can do this by replacing the summing resistor R4 by a T filter This filter has high output impedance due to the output resistor To dimension this filter without too much calculation we can treat it as a RC filter u
7. l Clock IDC3 Figure 8 UART Interface IDC3 http onsemi com NCN5193NGEVB Table 4 MICROCONTROLLER INTERFACE s me wa Reauestto Send The interface towards a microcontroller is provided in time base in another device is at 101 of nominal the IDC3 This interface can also be used to supply power to the receive data at the receiving UART will be skewed by module The nominal supply voltage for the module is 3 V roughly 21 of one bit time at the end of each 11 bit byte For more information see the section on power supply and This is shown in Figure 9 The skew time is measured from references the initial falling edge of the start bit to the center of the 11th The RESETB line to the modem is an open drain signal bit cell This 2196 skew by itself 1s a relatively good result A pull up resistor of 220 kQ is provided on the board and However there is another error source for bit boundary jitter should not be duplicated on the microcontroller side The The Phase Lock Loop demodulator in the NCN5193 reset signal 1s generated on the board and could be used as produces jitter in the receive data that can be as large as 1296 reset signal for other IC such as the microcontroller of a bit time Therefore a bit boundary can be shifted by as The CD signal rises when a HART signal of ca 100 mVpp much as 24 of a bit time relative to its ideal location based is detected on the current loop See the section on reference on th
8. lock http onsemi com 8 NCN5193NGEVB 421ps 78 13yV l 418s 750 0uV A839uS A828 1pV i0omv 5 2005 500MS s Value Mean Min Max Std Dev gt 70 00000 s 1M points Peak Peak 493 8 493 7m 493 5 493 9m 73 54 23 Feb 2011 10 16 05 Figure 12 Output Waveform Mark i 459ps 1 031 2505 1 047 l A459us A15 63yV omy gt 20035 7 500 5 5 7 0 00v Value Mean Min Max Std Dev 79 00000 5 1M points Peak Peak 491 2mv 491 3m 491 0m 512 0 807 64 23 Feb 2011 10 20 47 Figure 13 Output Waveform Space http onsemi com 9 NCN5193NGEVB Receiver The receive band pass filter is implemented on the NCN5193NGEVB The values are listed in Table 6 and the filter schematic is displayed in Figure 14 This is a band pass filter based on a Sallen Key topology allowing only frequencies around the HART signal frequencies to pass through For a more detailed description of the filter see the user manual of ASI91IHRTNEVB C14 R27 C45 RxAFI Rx HP Filter DEMODULATOR I Table 6 RECEIVE FILTER COMPONENT VALUES e e 2220 01 10 R26 p R23 17 prm HART IN R24 C13 C11 C7 RxAN R46 R22 Ris 1 25 Voc AREF Figure 14 Receive Filter http onsemi com 10 NCN5193NGEVB APPLICATION IDEAS The NCN5193 takes care of generating the HART m
9. odulation This HART signal must then be superimposed on a 4 20 mA current loop The NCN5193 simplifies slave implementation by including an integrated DAC Below are some possible implementations of both a master and slave transmitter Slave Implementation A simple slave implementation is shown in Figure 16 The analog loop current is set by the integrated DAC and HART signals are added to this by a resistive summing network The DAC is implemented as a sigma delta modulator which means that additional filtering should be implemented To explain the operation of this circuit let us first look at an example where the DAC is not of a switching topology such as shown in Figure 15 As one end of Rg is tied to local ground and current passing through R also passes through Re it can easily be seen that the voltage at the negative loop terminal is negative with respect to the local ground Resistor R4 is then chosen so that in steady state their common terminal is a virtual ground point in the absence of HART signals since the negative terminal of the amplifier is also connected to ground A similar principle applies when HART signals are applied So both amplifier inputs are regulated to ground Figure 15 Simple Slave Implementation A compensation capacitor C4 may be required depending on the operational amplifier used To avoid offset generated by bias current in the operational amplifier a resistor should be placed on the n
10. omparators and should be set to approximately 2 5 uA For low cost solutions a 470 k 2 is acceptable with minimal effect on operation Table 3 REFERENCE VOLTAGES AREF Reference Voltage 1 248 V CDREF Reference Voltage 1 163 V http onsemi com 5 NCN5193NGEVB Figure 5 Reference Voltages Schematic Clock Generation NCN5193 is operated on a clock signal of either 460 8 kHz 921 6 kHz 1 84 MHz or 3 68 MHz The NCN5193NGEVB has two options for providing this clock signal The first method is by using a ceramic resonator or a crystal with the internal oscillator The standard populated option is a Murata CSTCC3M68G53 RO ceramic resonator with build in load capacitors Alternatively a clock signal can be provided externally when is removed and is populated by a resistor of Ext Clock Figure 6 Clock Generation Circuit Resonator Option UART Interface IDC3 VCC VCC 0 2 This signal can be provided by a microcontroller or any other external oscillator circuit The module uses less power when clock signal is applied externally as this allows the modem to shut down the oscillator circuit A typical current consumption witnessed by utilizing an external oscillator 18 60 uA less However care must be taken that this external signal has the required frequency accuracy 1 Duty cycle of the clock signal is specified between 35 and 65 Ext Clock Figure 7 Clock Generation Circuit Externa
11. ose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part
12. pedance output which cannot be paralleled with the sense resistor as this would cause problems when the slave is transmitting This problem is solved by adding a series switch such as MC74VHCIG66DTT1G controlled by the RTS signal For a normally open switch the nRTS signal as applied to the NCN5193 must be inverted first To reduce power usage the operational amplifier can be disabled when the transmitter is turned off This is both done by inserting PNP transistor the Vpp connection of the amplifier To couple the signal into the current loop a single capacitor was used For other coupling techniques see application note AND8346 D http onsemi com 12 NCN5193NGEVB 3V KVDE20110406 5 Loop Loop Figure 17 Sample Master Implementation http onsemi com 13 NCN5193NGEVB APPENDIX Evaluation Board Layout Figure 18 Top Layer Layout Figure 19 Bottom Layer Layout ON Semiconductor and are registered trademarks of Semiconductor Components Industries LLC SCILLC SCILLC owns the rights to a number of patents trademarks copyrights trade secrets and other intellectual property A listing of SCILLC s product patent coverage may be accessed at www onsemi convsite pdf Patent Marking pdf SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purp
13. pends on the voltage supply and is chosen roughly half way the operating range of the operational amplifiers This ensures the range of the operational amplifier is maximized A reference voltage of 1 24 V is recommended For NCN5193NGEVB a series regulator is used with an internal reference of 1 25 V The chosen regulator has a very low supply current to optimize power usage Using a series regulator is more desirable from a power usage perspective as a series regulator s current draw will vary with the output current whereas a shunt regulator is dimensioned on the maximum current draw and will always draw the same current Large capacitors on the in and output of the voltage regulator increase the reference stability The CDREF reference voltage sets the threshold for the carrier detect comparator As the received signal is biased at AREF the difference between CDREF and AREF will determine the minimum amplitude needed for the carrier detect comparator to flip A AREF CDREF of 80 mV corresponds to signal of approximately 100 mV peak to peak at the input of the receive filter The CDREF reference voltage on the NCN5193NGEVB is generated by a resistor division of the AREF reference An external resistor is required to set the bias current The voltage over the bias resistor is regulated to AREF so that the resistor determines a bias current This bias current controls the operating parameters of the internal operational amplifiers and c
14. sing its first branch The 3 dB frequency should be placed just above the DAC bandwidth 10 Hz We get with Ry Rs we cm http onsemi com 11 NCN5193NGEVB To dimension the summing resistor of the HART input we can no longer assume that the positive input of the amplifier is a virtual ground as this assumption is only valid for DC signals We can however find a relationship between input amplitude and output amplitude We know that the positive amplifier input voltage has the following form due to the V summing network in V u Z6 The amplifier is configured as an integrator for low frequencies but for high frequencies the amplifier configuration has a gain of 1 and the transistor is configured as a voltage follower so we can conclude that for AC frequencies V Vout Taking this into account we get the following equation R R R Rj 8 a Reconfiguring for unknown Rs Vin VoulRe R3 Vou 1 R4 Rg The amplifier is configured as an integrator for low frequencies Care must be taken that the 3 dB frequency of the integrator is below the HART band so that the amplifier gain in that band is independent of frequency The resistor 15 chosen so that it compensates for input bias current This is achieved by taking a value close to the resistance seen on the positive terminal This means tha
15. skew between transmitting and receiving HART devices If have control over time bases in other HART devices the transmit time base is at 99 of nominal and the receive t Transmitter tsit 99 96 nominal CLK 2 Receiver 45 1200 21 tair 1200 PC20101209 1 UART mid bit sample moment 12 jitter Figure 9 Clock Skew http onsemi com 7 NCN5193NGEVB SPI Interface and Internal Register The NCN5193 also has an SPI interface that is used to control the integrated DAC and set the configuration registers of the IC This interface is accessible on the evaluation board through connector IDC Table 5 SPI DAC INTERFACE IDC Figure 10 SPI Interface IDC Pw At reset of the device all bits of the internal register are set to their reset value This means that before being able to use the evaluation board the device must be configured and all required blocks must be turned on See the description of the internal registers in the NCN5193 datasheet for more information Internal Sigma Delta DAC Figure 11 DAC Interface The 5193 includes an internal DAC that can be used for the implementation of a slave analog transmitter The included DAC has a Sigma Delta topology This means that the output of the DAC is constantly switching between 0 V en DACREF 3 V on the evaluation board To achieve optimum accuracy it is required that DACREF is
16. stal or ceramic resonator or an external clock signal When the device is transmitting data the receive module is shut down and vice versa to conserve power With simple power saving maneuvers the IC can be made to operate with a current consumption of as little as 130 uA The same techniques apply as explained for the A5191HRT in the Design Note ASI9IHRT Design for Low Power Environments AND9030 D http onsemi com 2 NCN5193NGEVB NCN5193NGEVB DESCRIPTION Schematic Diagram BOM List 3VXH dNG dNG ely 69 LA dNG 30242 3022 SM 884 OM EGOS9EOO1SO voal 4908 Lc dooz 19 LLO SWL 8L 19 Figure 2 NCN5193NGEVB Schematic http NCN5193NGEVB Table 2 NCN5193NGEVB BILL OF MATERIALS 77 Manufacturer amp Comments sre 7 75 6 s meu 11210065 3 ere 080 3 Lm p s 1 e Cp ms 2 1 1 e 2000 7 e o 1 7 e Cp os 1 7 mee Fi PoBo Ris DoNetPopuite Ow os 9 mRR o o 3 a EAS 7 0 ww 0 3 Ww Umm 3 rata General Overview The NCN5193NGEVB ev
17. t of the voltage supervisor the VPOR pin is equal to AREF On the evaluation board the resistor divider is dimensioned to make the POR trip at 2 8 V The voltage supervisor will keep the RESETB pin low until its threshold value is reached and will then wait an additional minimum of 30 ms until it releases the RESETB This ensures that some time has passed after the supply voltage reaches the turn on voltage and are 100 nF ceramic decoupling capacitors located directly adjacent to each power pin For analog power pins an additional large value ceramic capacitor may be needed in addition to the 100 nF decoupling capacitor when the application is intended for high noise environments For loop powered devices additional decoupling with alarge value capacitor is advised to prevent digital noise from being transmitted on the current loop Additional ferrite beads in series with power supply lines may help to reduce EMI Reference Voltages and Comparator Bias 5 193 needs an external analog reference voltage This reference is used by receiver or demodulator RX comparator carrier detect CD and voltage supervisor The AREF reference voltage sets the trip point of the demodulation operational amplifier of the NCN5193 The AREF reference voltage is also used in setting the DC operatng point of the received signal after it has passed through the band pass receive filter The ideal value for the AREF reference voltage de
18. t the capacitor C needs to be chosen so that 2 x R4C5 lt 1 kHz out Figure 16 Sample Slave Implementation Master Implementation An example of a possible master implementation is shown in Figure 17 The current loop master has a sense resistor over which the current flowing through the loop can be measured The value of this resistor varies depending on the sensitivity required and range of the ADC A HART Master can have a sense resistor ranging from 230 Q to 600 Q Increasing the sense resistor will result in higher amplitude HART signal received but will also reduce the voltage available on the slave side Furthermore if you wish to sense the analog transmitted signal the MSB of your DAC may limit the resistor size If this limitation is too stringent the sense resistor can be split in two resistors as shown in the figure effectively creating a resistor divider To transmit a HART signal the TxA signal will need to be amplified as the NCN5193 transmit circuit can only drive high impedance circuits gt 30 kKk 2 An additional operational amplifier 1s required Depending on the sense resistor used some gain or attenuation may be required to get a 1 mA peak to peak HART output signal This can be accomplished by the resistors R3 and R4 For a typical sense resistor of 500 6 a unity gain suffices and a unity gain operational amplifier configuration can be used instead The amplifier however has a low im
19. ultiplexers HART Modem Interfaces 4 20 mA Loop Powered Transmitters Figure 1 NCN5193NGEVB Evaluation Board Semiconductor Components Industries LLC 2014 May 2014 Rev 0 Publication Order Number EVBUM2237 D NCN5193NGEVB Table 1 ELECTRICAL CHARACTERISTICS OF THE NCN5193NGEVB BOARD Sm Wm Ww We we Current Consumption 1 80 idle 015 1 21 82 External Clock Vpp 1 80 V idle A External Clock Vpp 3 50 V idle Transmitted Frequency Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions unless otherwise noted Product performance may not be indicated by the Electrical Characteristics if operated under different conditions NCN5193 Description Test and Measurement Tools The NCN5193 modem is a single chip CMOS modem for Listed below are the tools used to acquire the values use in HART field instruments and masters It includes presented in this evaluation board on chip oscillator and a modulator and demodulator module Oscilloscope Tektronix DPO4101 1 GHz communicating with a UART without internal buffer as e Signal Generator Agilent 33250A well as an internal 17 bit sigma delta DAC The NCN5193 requires some external filter components and a 460 8 kHz 921 6 kHz 1 84 MHz or 3 68 MHz clock source This clock source can either be the interface oscillator by using a cry
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