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USER MANUAL IFC 430R

1. 1 enable error interrupt X2 pin 25 reserved The interrupts are edge sensitive they are triggered when changing from inactive to active status provided that they have been enabled by setting the corresponding bits A read access to the interrupt register returns the active interrupt source s After a read access the interrupt status is automatically cleared www rsf at 5 6 Delay Timer for external Sync In Base address 10 write access only Timer value 8 bit 0 timer off 1 to 255 timer on Sync IN X2 Pin 8 select polarity divider delay timer PCI clock 14 bit Sync Signal 16384 He H oy Sync IN active onnon oaan CF inactive Sync Signal active ATA OOO TP timer 0 inactive Sync Signal active meo ene ae LL Lac retrigger retrigger t1 t3 t2 t3 timer value T PCI 16384 T_PCI 30ns at 33 3 MHz PCI frequency T PCI 16384 491 52ms at 33 3 MHz PCI frequency The delay timer serves to activate a drop out delay and thus a debouncing of the Sync In input If the timer value is zero the delay timer is inactive and the Sync signal directly follows the input If the timer value is 0 the timer is triggered each time the input signal is activated If the input signal t2 is inactive longer than the timer t3 the Sync signal is deactivated as soon als the timer has run off Notes The time t3 must be programmed longer than the tim
2. Provides the status of the encoder inputs of an IFC430R Prototype Data IFC EncStatus UCHAR Axis Axis Number of the axis 0 to 23 Data 0 to 7 BitO O trackA inactive 1 active Bit1 0 track B inactive 1 active Bit2 0 track C inactive 1 active IFC EncErr Provides the status of the encoder interfering signal input X1 pin 13 Prototype Data IFC EncErr UCHAR Card Card Number of the card 0 to 7 Data 0 encoder error signal inactive 1 qgctive IFC Reflnit Initializing of external inputs as reference pulse inhibitor Prototype IFC Reflnit UCHAR Card USHORT Data Card Number of the card 0 to 7 Data 0 to 7 Bit0 0 input 1 X2 pin 2 has no influence on the reference pulse 1 acts as reference pulse inhibitor for encoder channel 1 Bit1 0 input 3 X2 pin 4 has no influence on the reference pulse 1 acts as reference pulse inhibitor for encoder channel 2 Bit D mput 5 X2 pin 6 has no influence on the reference pulse 1 acts as reference pulse inhibitor for encoder channel 3 IFC_RefClear Enables the reference pulses clears the reference status Prototype IFC RefClear UCHAR Axis Axis Number of the axis 0 to 23 IFC RefStatus Provides the status of the reference marks already traversed Prototype Data IFC_RefStatus UCHAR Axis Axis Number of the axis 0 to 23 Data 0 to 3 Bit0 0 first reference mark not traversed 1 first reference mark traverse
3. 2 latch counter with timer 3 latch counter with Sync IN at X2 4 latch counter with IN 2 at X2 for encoder channel 1 IN 4 at X2 for encoder channel 2 IN 6 at X2 for encoder channel 3 5 latch counter with next encoder reference mark 6 latch counter with second encoder reference mark 1 latch counter with all encoder reference marks RSF Elektronik IFC_ CntLatch1 Selecting hardware signal for latch register 1 IFC_ CntLatch1 UCHAR Axis UCHAR Value Number of the axis 0 to 23 0 to 7 0 hardware signals disabled 1 latch counter with software function IFC Latchlmp 2 latch counter with timer 3 latch counter with Sync IN at X2 4 latch counter with IN 2 at X2 for encoder channel 1 IN 4 at X2 for encoder channel 2 IN 6 at X2 for encoder channel 3 5 latch counter with next encoder reference mark 6 latch counter with second encoder reference mark Prototype Axis Value 1 latch counter with all encoder reference marks IFC_ CntMode Setting of phase discriminator counting direction and encoder quadrants IFC_ CntMode UCHAR Axis UCHAR Value Number of the axis 0 to 23 Prototype Axis Value Bit1 Bit 0 5 Phase discriminator 0to 1 0 0 0 1 1 0 1 1 Bit 2 Bit 3 Counter without phase discriminator track A counting direction signal track B counter clock signal track C counter load or latch signal Counter with phase discriminator and one fold evaluation
4. Counter with phase discriminator and two fold evaluation Counter with phase discriminator and four fold evaluation Operating mode 0 is intended for counting functions without encoders The operating modes 1 to 3 are intended for encoder applications Counting direction Normal counting direction Inverted counting direction Inverting encoder tracks A and B Encoder tracks A and B are not inverted Encoder ref signal is located in the first quadrant tracks A B and C 1 Encoder tracks A and B are inverted Encoder ref signal is located in the third quadrant tracks A and B 0 C 1 www rsf at DISTRIBUTION CONTACTS AUSTRIA Corporate Head Quarters FRANCE GREAT BRITAIN ITALY NETHERLANDS SWEDEN SWITZERLAND CHINA JAPAN KOREA USA RSF Elektronik Ges m b H HEIDENHAIN FRANCE sarl HEIDENHAIN GB Ltd HEIDENHAIN ITALIANA S r l HEIDENHAIN NEDERLAND B V HEIDENHAIN Scandinavia AB RSF Elektronik Schweiz AG RSF Elektronik HEIDENHAIN K K HEIDENHAIN LTD HEIDENHAIN CORPORATION A 5121 Tarsdorf 93 2 Avenue de la Christallerie 92310 S vres 200 London Road Burgess Hill West Sussex RH15 9RD Via Asiago 14 20128 Milano MI Copernicuslaan 34 6710 BB EDE Stors tragr nd 5 SE 12739 Sk rholmen Vieristrasse 14 CH 8603 Schwerzenbach Tian Wei San Jie Area A Beijing Tianzhu Airport Industrial Zone Shunyi District 101312 Beijing PR China Hulic Kojimach
5. Data Bit0 O input1 low active X2 pin 2 1 high Bit 0 input 2 low active X2 pin 3 1 high Bit2 0O0 input 3 low active X2 pin 4 1 high Bit3 0O0 input 4 low active X2 pin 5 1 high Bit4 0 input 5 low active X2 pin 6 1 high Bitb 0 input 6 low active X2 pin 7 1 high Bit6 D mput Syncin low active X2 pin 8 1 high Bit7 O outputCascOut low active X2 pin 9 high IFC Extin Provides the states of the external inputs of an IFC430R Prototype Data IFC ExtIn UCHAR Card Card Number of the card 0 to 7 Data Bit0 0 input 1 inactive X2 pin 2 1 active Bit 0 input 2 inactive X2 pin 3 1 active Bit2 0 input 3 inactive X2 pin 4 1 active Bit3 0 input 4 inactive X2 pin 5 1 active Bit4 0 input 5 inactive X2 pin 6 1 active Bit5 0 input 6 inactive X2 pin 7 1 active IFC_Casclnit Initializes the output CascOut X2 Pin 9 Prototype IFC Casclnit UCHAR Card USHORT Value Card Number of the card 0 to 7 Value 0 CascOut inactive 1 CascOut active 2 CascOut switched by timer 3 CascOut follows the input signal Syncin P e S RSF Elektronik IFC ExtSync Provides the status of the Syncln input X2 pin 8 Prototype Syncin IFC ExtSync UCHAR Card Card Number of the card 0 to 7 Syncin 0 Syncin inactive 1 activ
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7. of the Registers sssssssseeeeeeeen nentes 10 SystemiControl E WEE 10 TUHAST AEGISTSI ea RE E TASU E E dies aan teen eenten eet 10 ERT 11 Status EE 11 Memup SR ISI MS a E naat na 12 Delay let 13 Counter Load Register 14 Counter Lateh Register nire re Re orc ge IER RE d e kal e tite HR FEE UH EE Eee ERR 14 Counter Control Registr ebore ipae emat t t hu de eerte ee ee 15 Counter Mode RegiSter sisakan E A EE EATE E EA E E EA EE EE SE 15 16 Instructions for Installaton 2 0 ccc cece ceccseseecsssesessssecssssecussseessnsssecussseessvssessssseecsssseessuasecssssecusssasecssisecsisseessssteatsnsetesnitesniatecseeesees 17 NIE EECHELEN 17 installation of the KE 17 Installation of the enclosed Test Software eene treten tnit tette 17 Programming ue 17 DUE Functions ee 18 26 www rsf at 1 GENERAL INFORMATION The functions of a PCI bus are not described in this manual 1 1 Important Information Danger to components if these notes are not observed Please observe the safety precautions according to DIN EN 100 015 when handling ESD components electrostatic discharge Only use antistatic packaging material For mounting observe that the working place must be properly grounded Do not engage or disengage any connectors while the unit is under power Check the correct operating voltages of the encoders before inserting the jumpers of IFC 430R 1 2 Application IFC 430R is a PC expansion board with PCI int
8. 5 reserved IFC IntStatus Returns the interrupt status After reading out the interrupt status all bits are deleted and set anew by the next interrupt event edge sensitive triggering Prototype Status USHORT IFC_IntStatus UCHAR Card Card Number of the card 0 to 7 Status BitO 1 interrupt activation through timer zero crossover Bit 1 interrupt activation through Syncin X2 pin 8 Bit2 1 interrupt activation through INT X2 pin 2 Bit3 1 interrupt activation through IN2 X2 pin 3 Bit4 1 interrupt activation through IN3 X2 pin 4 Bitb 1 interrupt activation through INA X2 pin 5 Dip 1 interrupt activation through IN5 X2 pin 6 Bit 1 interrupt activation through IN6 X2 pin 7 Bit8 1 interrupt activation through first reference mark at Axis 0 Bit9 1 interrupt activation through second reference mark at Axis 0 1 Bit 1 interrupt activation through first reference mark at Axis 1 Bit11 1 interrupt activation through second reference mark at Axis 1 Bit12 1 interrupt activation through first reference mark at Axis 2 Bit13 1 interrupt activation through second reference mark at Axis 2 Bit14 1 interrupt activation through encoder error X1 Pin 25 Bit 15 reserved IFC IntUnMask www rsf at Activation of the interrupt handler When the interrupt handler is active the DLL runs the service routine transferred as pointer with each hardware in
9. 5 1 System Control Register Base address 0 write and read access of software sync ion of Casc Out by software ion of Casc Out by timer ion of Casc Out by sync IN ion of INT as ref pulse inhibitor for encoder channel 1 ivation of IN3 as ref pulse inhibitor for encoder channel 2 ivation of IN5 as ref pulse inhibitor for encoder channel 3 ivation of the interrupt inhibit on the PCI bus as of hardware revision 1 only inverted 2 3 4 5 6 T 8 9 inverted ed ed ed i s N inverted i 99 p Sync IN inverted Casc OUT inverted OT 5 2 Timer Register Base address 2 write and read access Write access Read access Timer value Time remaining until next pulse 0 timer off 1 to FFFFh timer on F PCI frequency 256 timer value 1 5 3 Status Register 1 Base address 4 read access only X1 pins 4a X1 pins 6a X1 pins 7 a X1 pins 8a X1 pins 10 and 23 nnel 3 X1 pins 11 and 24 nnel 3 X1 pins 12 and 25 1 2 3 4 5 6 T 8 9 ference signal X1 pin 13 i ce i NM i Co Sch IA on 5 4 Status Register 2 Base address 6 read access only code code
10. P 4 RSF Elektronik T DLL FUNCTIONS IFC OpenDrv Opens the device driver and returns its status Prototype Data IFC OpenDrv Data 0 driver could not be found 1 driver was opened IFC_CloseDrv Closes the device driver Prototype IFC_CloseDrv IFC_ScanBus Searches the PCI bus for available IFC430R returns number of cards and their base addresses Up to 8 cards are supported and thus 8 long words returned For each IFC430R found the value of the related base address is not zero Prototype Card IFC_ScanBus long pBase Addr Card Numer of cards detected 0 to 8 Data Pointer to 8 long words Long word 0 no IFC430R was found at this position Long word lt gt 0 base address of an IFC430R IFC GetHwRev Feature of hardware revision of IFC430R Prototyp Revision IFC GetHwRev UCHAR Card Revision Hardware Revision 0 bis 255 Card Nummer der Karte 0 bis 7 IFC Init Initializes the IFC430R with the values from an initializing file Prototype Data IFC_Init char pFileName Data 0 no initializing file found 1 initializing file was transferred pFileName Pointer to the file name of the initializing file If no file name is specified by the user the standard initializing file is IFCA30R INI www rsf at IFC Extlnit Initializes the polarity for the external inputs and outputs at X2 Prototype IFC ExtInit UCHAR Card USHORT Data Card Number of the card 0 to 7
11. RSF Elektronik USER MANUAL IFC 430R PC PLUG IN CARD 02 2013 P e S L RSF Elektronik CONTENTS 1 H 12 1 3 General Information ooo eee cccccececesesesesessseeesssnsecssnsssesssssecesssecusssasecssssesusnsesssssecsnsseesssssecstasecussvatesssasecesssecsrsseeecesiecssiseeanitessimeestentestee 03 important leet ccce cioe cierran cre rotor ent cra EC 03 DEE tee ee eeh enee Ee 03 tens S PDIEAE 40282000 RETE EE REESE 03 Specifications iren erar rra eh eren om riae nid ven PER C Rt EP cei EP prr rp e fran stro Ere or rn 04 Mechanical Dimensions and Ambient Conditions tette ttti tette 04 EGIBUS E eit 04 GS OUMILEM MTOR X oen esr DULL LU UU aneset 04 VO nterface XI 04 Counter Operating Modes ttti ttti tette tte tte tte i 04 ER Ee EE 04 Hardware trn min ror UTD ER EI RETE ER ERRARE EE ERE DR RU HEAR E ERE 05 Comipotient LOC ATOM egen rooster teer Dc a rr ere ht rf ue eA 05 Selecting the Encoder Operating Voltage 4 acrem tte nne c aid d eie EEN 05 Pin Assignment XT 06 PIMASSIQAIMENT Em 06 MOUCINA a assent azeena de a eee dete Sena areas enh As 07 Block DIAG s T ERE 08 Address Allocation irn trien a REPRE REDE UTE ORCHARD TEE EE HEEL HERD EH EH E RR 09 Eeer coercet mre tmn mbi brem een e A ombre ta Ambre tina 09 local Address AlOCAtIOMN scisco rida teta rete iia ro P aeo a n d n ta mn ede d e in e RO UE HE 09 Description
12. S FOR INSTALLATION 6 1 Hardware Installation For the installation please observe the safety precautions according to DIN EN 100 015 when handling ESD components electrostatic discharge Disconnect the PC from the line by disengaging the power connector Open the PC Insert the IFC 430R interface card into a free PCI slot Close the PC Engage the power connector to the line Switch the PC on 6 2 Installation of the Drivers WINDOWS XP VISTA 7 8 After the booting procedure the operating system automatically detects the new hardware component For this purpose the related drivers need to be installed Insert the floppy disk with the label IFC430R Driver into the floppy disk drive Follow the instructions on the screen By carrying out these steps an entry is made to the registry and the following files are copied to the system directory eg C WINNT System32 Drivers IFC430R SYS The enclosed disk contains the DLLs for 32 and 64 bit systems The corresponding DLL should be included directly in the application 6 3 Installation of the enclosed Demo Software The test program uses the previously installed drivers No setup of this software is required The demo program can be started from floppy disk or from hard disk after being copied there 6 4 Programming Examples On the supplied disk are programming examples for Borland C Builder 4 Borland Delphi 5 Microsoft Visual Basic 6 Microsoft Visual C 6
13. andler IFC SetTimer Sets the preload value for the timer If the preload value is set to 0 a running timer is stopped at the next zero crossover If the preload value is lt gt 0 a non running timer is immediately started with the specified value a running timer receives the new value at the next zero crossover time timer value 1 256 T PCI timer value preload value T PCI PCI clock time 30ns 33 3MHz Prototype IFC SetTimer UCHAR Card USHORT TimerValue Card Number of the card 0 to 7 TimerValue 0 to 65535 IFC GetTimer Returns the run time remaining until the next zero crossover of the timer During the zero crossover of the timer a signal is generated that can be used for a variety of functions depending on the initializing e g synchronous latching of count values load counter or generating a pulse at the CascOut output Prototype Time IFC GetTimer UCHAR Card Time 0 to 65535 Card Number of the card 0 to 7 IFC SetAdr Writes data directly to the specified address Prototype IFC SetAdr UCHAR Card USHORT Offset USHORT Data Card Number of the card 0 to 7 Offset 0 to 64 address base address of the card offset Data data 16 bits IFC GetAdr Reads data from the specified address Prototype Data IFC GetAdr UCHAR Card USHORT Offset Data 0 to 65535 Card Number of the card 0 to 7 Offset 0 to 64 address base address of the card offset IFC EncStatus
14. atchReg Provides the 32 bit count value previously stored in a latch register Prototype Data IFC_GetLoadReg UCHAR Axis UCHAR Reg Data 32 bit counter value Axis Number of the axis 0 to 23 Reg Number of the latch register 0 or 1 IFC Latch Stores the 32 bit count value of an axis in one of the two latch registers by software The count value can also be stored in the latch regis ters by means of several hardware sources see IFC CntLatch Prototype IFC Latch UCHAR Axis UCHAR Reg Axis Number of the axis 0 to 23 Reg Number of the latch register 0 or 1 IFC Latchimp Generates a hardware pulse that is simultaneously fed to all latch registers of a card thus several count values of a card can be latched synchronously by software The pulse can also be switched to the CascOut output X2 pin 9 at the same time If the CascOut of this card is connected to the Syncin of the next cards several count values of several cards can be latched synchronously by software Prototype IFC Latchlmp UCHAR Card UCHAR Casc Card Number of the card 0 to 7 Casc 0 latch pulse is not fed to CascOut X2 pin 9 1 latch pulse is simultaneously fed to CascOut X2 pin 9 IFC_ CntLatch0 Selecting hardware signal for latch register 0 Prototype IFC CntLatch0 UCHAR Axis UCHAR Value Axis Number of the axis 0 to 23 Value 0to 7 0 hardware signals disabled 1 latch counter with software function IFC Latchlmp
15. code code code code level Sy interrupt req ive as of hardwa ision 1 only ved ved ved ved ved ved www rsf at 11 m RSF Elektronik 5 5 Interrupt Register Base address 8 write and read access e timer interrupt e timer interrupt e sync interrupt e sync interrupt X2 pin 8 e INT interru NT inter N2 inter N2 inter N3 inter N3 inter N4 inter N4 interr N5 inter N5 interr N6 inter N6 interrupt X2 pin 7 CH 3 X2 pin 2 CH X2 pin 3 CH CH X2 pin 4 TI CH X2 pin 5 CH CH X2 pin 6 CH CH e encode nel 1 refl i e encoder nel 1 ref D 0 disable encode nnel 1 ref2i c CH e encoder lref2i 0 disable encode 2 refl CH cc CH 2 enable encoder 2refl 0 disable encode 2 ref2 i D Cc Ra 2 enable encoder 2 ref2 0 disable encode 3 ref CH c CH 3 enable encoder 3refl 0 disable encode 3 ref2 D cc K 3 enable encoder c 3 ref2 D 0 disable error interrup
16. d Bit 0 second reference mark not traversed 1 second reference mark traversed www rsf at P e S RSF Elektronik IFC SetLoadReg Transfers the value for the counter load register Prototype IFC SetLoadReg UCHAR Axis ULONG LoadValue Axis Number of the axis 0 to 23 LoadValue 32 bit value IFC Load The counter of an axis is loaded with the contents of the load register by software A counter can also be loaded by several hardware sources see IFC_LdCIr Prototype IFC Load UCHAR Axis Axis Number of the axis 0 to 23 IFC Clear The counter of an axis is cleared A counter can also be cleared by several hardware sources see IFC L dClr Prototype IFC Clear UCHAR Axis Axis Number of the axis 0 to 23 IFC_ CntLdClr Mode to load or clear a counter by means of a hardware signal Prototype IFC CntLdClr UCHAR Axis UCHAR Value Axis Number of the axis 0 to 23 Value 0to 7 0 hardware signals disabled 1 2 clear counter with next encoder reference mark clear counter with all encoder reference marks clear counter with timer load counter with next encoder reference mark load counter with all encoder reference marks clear counter with all encoder reference marks and additionally load counter with negative zero crossover 7 load counter with IN 1 at X2 for encoder channel 1 IN 3 at X2 for encoder channel 2 IN 5 at X2 for encoder channel 3 www rsf at IFC GetL
17. e IFC_SetSyncDelay Sets the preload value for the delay timer Prototyp Bool IFC_SetSyncDelay UCHAR Card USHORT TimerValue Bool 0 no delay timer available with this hardware revision 1 delay timer was set Card Number of the card 0 to 7 TimerValue 0 to 255 IFC Intlnit Initializes the interrupts The interrupt sources are gated with OR as a consequence several interrupt events can be processed simultaneously Prototype void IFC Intlnit UCHAR Card USHORT Data Card Number of the card 0 to 7 Data BitO 1 interrupt enable on timer zero crossover Bit 1 interrupt enable on activation of Syncin X2 pin 8 Bit2 1 interrupt enable on activation of INT X2 pin 2 Bit3 1 interrupt enable on activation of IN2 2 pin 3 Bit4 1 interrupt enable on activation of IN3 X2 pin 4 Bitb 1 interrupt enable on activation of IN4 X2 pin 5 Bit6 1 interrupt enable on activation of IN5 2 pin 6 Bit 1 interrupt enable on activation of IN6 2 pin 7 Bit8 1 interrupt enable with the next reference mark Axis 0 Bit9 1 interrupt enable with the second reference mark Axis 0 Bit10 1 interrupt enable with the next reference mark Axis 1 Bit11 1 interrupt enable with the second reference mark Axis 1 Bit12 1 interrupt enable with the next reference mark Axis 2 Bit13 1 interrupt enable with the second reference mark Axis 2 Bit14 1 interrupt enable on encoder error X1 Pin 25 Bit 1
18. e for signal drops t1 If the output Casc Out X2 pin 9 is programmed such that it is triggered with the Sync signal see chapter 5 1 System Control Rregister it can be measured at Casc Out ASE Elektronik 5 7 Counter Load Register write access t Encoder channe 1 LO word Encoder channe 1 HI word Encoder channe 2 LO word Encoder channe 2 HI word Encoder channe 2 LO word Encoder channe Note A write access only sets the load register Data transfer from the load register into the counter requires a further hardware or software action see chapter 5 9 Counter control register and chapter 5 10 Counter mode register bits 4 to 6 2 HI word 5 8 Counter Latch Register read access Latch register ister 0 LO word Encoder channe Encoder channe ister 0 HI word Encoder channe ister 1 LO word Encoder channe ister 1 HI word Encoder channe ister 0 LO word ncoder channe ister 0 HI word ncode nne ister 1 LO word ncode nne ister 1 HI word ncode ister 0 LO word ncode ister 0 HI word ncoder c ister 1 LO word Encoder ch Note Each encoder channel features two latch registers To obtain the current count it must be intermediately stored in one of the two latch registers see chapter 5 9 Counter Control Register and chapter 5 10 C
19. er tracks A and B 0 ncoder tracks A and B are not inverted coder ref signal is located in the first quadrant tracks A B and C 1 coder tracks A and B are inverted coder ref signal is located in the third quadrant tracks A and B 0 C 1 Selecting counter load clear signal 4 it6 Bit5 Bit4 5 Hardware signals disabled 6 Clear counter with next encoder reference pulse Clear counter with all encoder reference pulses Clear counter with timer Load counter with next encoder reference pulse Load counter with all encoder reference pulses Clear counter with all encoder reference pulses and additionally load counter with negative zero crossover Load counter with IN 1 at X2 for encoder channel 1 IN 3 at X2 for encoder channel 2 IN 5 at X2 for encoder channel 3 8 9 12 reserved Selecting hardware signal for latch register 0 Bit 10 Bit 9 Bit 8 0 Hardware signals disabled 0 Latch counter with software sync addr 0 bit 0 0 Latch counter with timer 0 Latch counter with Sync IN at X2 Latch counter with IN 2 at X2 for encoder channel 1 IN 4 at X2 for encoder channel 2 IN 6 at X2 for encoder channel 3 Latch counter with next encoder reference pulse Latch counter with second encoder reference pulse Latch counter with all encoder reference pulses reserved Selecting hardware signal for latch register 1 13 identical with bits 8 to 10 14 www rsf at 6 INSTRUCTION
20. erface for the acquisition and evaluation of encoder signals It can also be used for all standard counting functions event counter frequency counter etc 1 3 Items Supplied FC 430R PCI interface board Disc with demo program and driver software User Manual RSF Elektronik 2 SPECIFICATIONS 2 1 Mechanical dimensions and ambient conditions Dimensions of the PCB approx 120 x 92 mm width 1 slot Maximum permissible ambient temperature 40 C D sub female terminal strip 25 pin for the counter inputs D sub female terminal strip 9 pin for the for l O signals 2 2 PCBus PCI connector 5 V 32 bit 2 x 60 pins Target interface slave as per specifications Rev 2 1 Bus clock frequency 40 MHz max Current consumption at 5 V approx 0 5 A without encoders Power supply of the encoders 5 V or 12 V from PCI power supply current consumption depends on encoders connected 2 3 Counter Interface X1 9 RS 422 or TTL inputs for 3 encoders with square wave signals and reference mark Maximum input frequency 5 MHz with delta signals RS 422 2MHz with single end signals 1 TTL input for interfering signal monitoring Separate power supply lines for each encoder 0 5 A max per encoder 2 4 1 0 Interface X2 6 inputs 3 to 30 V that can be used as reference pulse inhibitors or as asynchronous latch signals jinput 3 to 30 V for synchronous latch of several channels 1 out
21. i Bldg 9F 3 2 Kojimachi Chiyoda ku Tokyo 102 0083 202 Namsung Plaza 9th Ace Techno Tower 130 Digital Ro Geumcheon Gu Seoul Korea 153 782 333 East State Parkway Schaumburg IL 60173 5337 Date 02 2013 Art Nr 824550 01 Dok Nr D824550 00 A 01 Technical adjustments in reserve E RSF Elektronik Ges m b H DX A 5121 Tarsdorf M 4 43 0 6278 8192 0 E ER Linear Encoders Cable Systems Precision Graduations Digital Readouts Sg BEC E ER 29 Z9 H Ic D S D 43 62 78 81 92 0 43 62 78 81 92 79 33 1 41 14 30 00 33 1 41 14 3030 44 1444 247711 44 1444 870024 39 02 27075 1 39 02 27075 210 31 318 58 18 00 31 318 58 18 70 46 8 531 933 50 46 8 531 933 77 41 44 955 10 50 41 44 955 1051 86 10 80 42 02 88 86 10 80 42 02 90 81 3 3234 7781 81 33262 2539 82 220 287430 1 847 49011 91 DIN EN ISO 9001 e mail info rsf at internet www rsf at e mail info heidenhain fr internet www heidenhain fr e mail sales heidenhain co uk internet www heidenhain co uk CD mail info heidenhain it ernet www heidenhain i EI mail verkoop heidenhain nl ernet www heidenhain nl Se CD mail sales heidenhain se ernet www heidenhain se EI e mail info rsf ch internet www rsf ch
22. ounter mode register bits 8 to 10 and bits 12 to 14 by means of a hardware or software action ister 1 HI word www rsf at 5 9 Counter Control Register write access Base address 14 encoder channel 1 Base address 24 encoder channel 2 Base address 34 encoder channel 3 1 clear counter 1 load counter 1 store count in latch register 0 1 store count in latch register 1 1 enable encoder reference pulse reserved The counter control register serves to clear the counter by software or to load the contents of the load register the current counts can be stored in one of the two latch registers 5 10 Counter Mode Register write read access Base address 18 encoder channel 1 Base address 28 encoder channel 2 Base address 38 encoder channel 3 Phase discriminator Bit1 BitO 0 0 counter without phase discriminator track A counting direction signal track B counter clock signal track C counter load or latch signal hase discriminator and one fold evaluation hase discriminator and two fold evaluation counter with phase discriminator and four fold evaluation Operating mode 0 is intended for counting functions without encoders The operating modes 1 to 3 are intended for encoder applications Counting direction 0 normal counting direction 1 inverted counting direction 15 m ASE Elektronik Inverting encod
23. put TTL for cascading several cards 2 5 Counter Operating Modes Three counter channels 32 bits each one load and two latch registers for each channel Counting of encoder square wave signals with one fold two fold or four fold evaluation Event counter with direction and clear input Integral timer for measuring pulse width frequency or speed 2 6 Latch Logic Asynchronous latching of the counter values individually for each encoder channel via software reference mark of the encoder or external hardware signal Synchronous latch of several channels by software timer or external signal Output signal for cascading several cards can be programmed for software timer or external hardware synchronization Latch time two bus clock pulses 60 ns at a clock frequency of 33 3 MHz www rsf at 3 HARDWARE 3 1 Component Location Diagram t ooooo fi O000 o00000 000 D STU 50 a E a ea a e ea ea a e E e a a a a a a Bo gggegag Doooo00 X1 female D sub terminal strip 25 pin for counter interface X2 female D sub terminal strip 9 pin for switching and control signals J1 J3 jumper for the selection of the encoder operating voltage 5 V or 12 V ICT PCl interface 3 2 Selecting the Encoder Operating Voltage The operating voltage of the encoders may be set individually for each channel to 5 V or 12 V by means of the jumpers J1 to J3 The selected
24. t any restrictions ASE Elektronik 3 6 Block Diagram latch register latch register II load register o KH 7 EDS E EH SH o o gt lt PCl interface counter channel II identical with counter channel I counter channel III identical with counter channel I X2 control IFC switching and control signals www rsf at 4 ADDRESS ALLOCATION PCI Interface Interface 32 bit PCI bus with 5 V connection Access 40 HEX addresses memory space or 40 HEX addresses 0 Space Base address automatically assigned by the operating system 4 1 Header Configuration Addr ytes Byte2 eyer Byeo Value Her Device ID Vendor ID 9050 10B5 Base address local memory space XXXX XXXX Base address local I O space XXXX XXXX Sub device ID Sub vendor ID 2302 4301 A PCI interface card is identified by its four ID values Sub device ID and Sub vendor ID only refer to IFC 430R 4 2 Local address allocation System control register Write and read Timer register Write and read Status register 1 Read only Status register 2 Read only Interrupt register Write and read Sync In delay timer Write only reserved reserved Counter channel 1 Write and read 16 bits Counter channel 2 Write and read 16 bits Counter channel 3 Write and read 16 bits ASE Elektronik 9 DESCRIPTION OF THE REGISTERS
25. terrupt Different interrupt sources can be initialized see IFC Intlnit Prototype void IFC_IntUnMask UCHAR Card BOOL IrgShared plrqHandler Long Card Number of the card 0 to 7 IrqShared True b Interrupt is shared False b Interrupt is not shared pirgHandler Pointer to interrupt service routine Example of an interrupt service routine void __stdcall IRA Handler USHORT IRQ Number ULONG IRQ Source d Interrupt service routine With every generation the interrupt handler reads the interrupt status of IFC430R and transfers it to the interrupt service routine as parameter IRQ Source The interrupt number is also transferred as parameter IRQ number 1 15 Notes currently not executable under Windows 2000 and Windows XP IFC_IntMask Deactivation of the interrupt handler Prototype Data IFC_IntMask UCHAR Card Card Number of the card 0 to 7 Data 0 b Interrupt handler already inactive 1 b Interrupt handler switched from active to inactive status P e S RSF Elektronik IFC IntlsMask Provides the status of the interrupt handler Prototype Data IFC IntlsMask UCHAR Card Card Number of the card 0 to 7 Data True P Interrupt handler inactive False b Interrupt handler active IFC IntCnt Read out interrupt counter Prototype Data IFC IntCnt UCHAR Card Card Number of the card 0 to 7 Data Number ULONG of the interrupt routines executed since the last activation of the h
26. voltage can be seen from the print on the board Jl encoder channel 1 J2 encoder channel 2 J3 encoder channel 3 Note Observe that incorrect placement of the jumpers may destroy the encoder Default setting for the operating voltages is 5 V RSF Elektronik 3 3 Pin Assignment X1 ND p p inp inp put C input C supply 5 V or 12 V selected by J2 A A C C supply 5 V or 12 V selected by J1 ND A A p p inp inp p inpu Sync WO o IN 0 Jo 00 n ut Casc 3 5 Input Wiring Encoder connection X1 Encoder Power d Schirm an Geh use IFC 430R d Supply 45 V o 12 V D z o H je A gt o ict Encoder Il identisch mit Encoder Encoder Ill identisch mit Encoder Be 62R gt m i E g Ei 62R Ca 62R vol i C mg 101 Suppl II SII ITI II um c As line drivers all standard RS 422 drivers such as MC3487 AM32LS31 etc may be used If there are no delta signals available the inputs can also be wired as single end inputs in this case one of the two delta inputs normally remains open Encoders with 1 Vpp voltage interface may be operated like RS 422 encoders withou

USER MANUAL IFC 430R

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