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MSP430x4xx Family User's Guide (Rev. G - webwww03

1. 19 16 15 0 19 0 Figure 4 49 Rotate Right Arithmetically RRAX B A Non Register Mode 7 0 Ea 7 w po n w 16 Bit MSP430X CPU 4 141 Extended Instructions RRCM A RRCM W Syntax Operation Description Status Bits Mode Bits Example Example Rotate Right through carry the 20 bit CPU register content Rotate Right through carry the 16 bit CPU register content RRCM A _ n Rdst 1 lt n lt 4 RRCM W_ n Rdst or RRCM n Rdst 1 lt n lt 4 C gt MSB gt MSB 1 gt LSB 1 LSB gt C The destination operand is shifted right by one two three or four bit positions as shown in Figure 4 50 The carry bit C is shifted into the MSB the LSB is shifted into the carry bit The word instruction RRCM W clears the bits Rdst 19 16 Note This instruction does not use the extension word N Set if result is negative A Rdst 19 1 reset if Rdst 19 0 W Rdst 15 1 reset if Rdst 15 0 Z Set if result is zero reset otherwise C Loaded from the LSB n 1 LSB 1 n 2 LSB 2 n 3 or LSB 3 n 4 V Reset OSCOFF CPUOFF and GIE are not affected The address word in R5 is shifted right by three positions The MSB 2 is loaded with 1 SETC Prepare carry for MSB 2 RRCM A 3 R5 R5 R5 3 20000h The word in R6 is shifted right by two positions The MSB is loaded with the LSB The MSB 1 is loaded with the contents of
2. CPU Registers Two or three words The sign extended 16 bit index in the next word after the instruction is added to the 20 bits of the PC This delivers a 20 bit address which points to an address in the range 0 to FFFFFh The operand is the content of the addressed memory location Valid for source and destination The assembler calculates the PC index and inserts it ADD W EDE amp TONI This instruction adds the 16 bit data contained in source word EDE and destination word TONI and places the 16 bit result into the destination word TONI For this example the instruction is located at address 2 F034h Source Word EDE at address 3379Ch pointed to by PC 4766h which is the 16 bit result of 3379Ch 2F036h 04766h Address 2F036h is the location of the index for this example Destination Word TONI located at address 00778h pointed to by the absolute address 00778h Before After Address Address Space Space 2F03Ah 2F03Ah 2F038h 2F038h 2F036h 2F036h 2F034h 2F034h 2F036h 3379Eh 04766h 3379Eh 3379Ch Boren 3379Ch 5432h src 0077Ah 0077Ah 2345h_ dst 00778h 00778h Cs a 16 Bit MSP430X CPU 4 27 CPU Registers MSP430X Instruction with Symbolic Mode When using an MSP430X instruction with Symbolic mode the operand can be located anywhere in the range of PC 19 bits Length Three or four words Operation The operand address is the sum of the 20 bit PC and the 20 bit index The four MSBs of the index are c
3. pointed to by R5 Core instruction MOV R5 PC Indirect indirect R5 BR R5 Branch to the address contained in the word pointed to by R5 and increment pointer in R5 afterwards The next time S W flow uses R5 pointer it can alter program execution due to access to next address in a table pointed to by R5 Core instruction MOV R5 PC Indirect indirect R5 with autoincrement BR X R5 Branch to the address contained in the address pointed to by R5 X e g table with address Starting at X X can be an address or a label Core instruction MOV X R5 PC Indirect indirect R5 X 16 Bit MSP430X CPU 4 69 MSP430 Instructions CALL Syntax Operation Description Status Bits Mode Bits Examples Call a Subroutine in lower 64 K CALL dst dst gt tmp 16 bit dst is evaluated and stored SP 2 gt SP PC SP updated PC with return address to TOS tmp PC saved 16 bit dst to PC A subroutine call is made from an address in the lower 64 K to a subroutine address in the lower 64 K All seven source addressing modes can be used The call instruction is a word instruction The return is made with the RET instruction Not affected PC 19 16 Cleared address in lower 64 K OSCOFF CPUOFF and GIE are not affected Examples for all addressing modes are given Immediate Mode Call a subroutine at label EXEC lower 64 K or call directly to address CALL EXEC Start address EXEC CALL 0AA04
4. BIC W BIC B Syntax Operation Description Status Bits Mode Bits Example Example Example Clear bits set in source word in destination word Clear bits set in source byte in destination byte BIC src dst or BIC W src dst BIC B src dst not src and dst dst The inverted source operand and the destination operand are logically ANDed The result is placed into the destination The source operand is not affected N Not affected Z Not affected C Not affected V Not affected OSCOFF CPUOFF and GIE are not affected The bits 15 14 of R5 16 bit data are cleared R5 19 16 O BIC 0C000h R5 Clear R5 19 14 bits A table word pointed to by R5 20 bit address is used to clear bits in R7 R7 19 16 0 BIC W R5 R7 Clear bits in R7 set in R5 A table byte pointed to by R5 20 bit address is used to clear bits in Port1 BIC B R5 amp P10OUT Clear I O port P1 bits set in R5 4 66 16 Bit MSP430X CPU BIS W BIS B Syntax Operation Description Status Bits Mode Bits Example Example Example MSP430 Instructions Set bits set in source word in destination word Set bits set in source byte in destination byte BIS src dst or BIS W src dst BIS B src dst src or dst gt dst The source operand and the destination operand are logically ORed The result is placed into the destination The source operand is not affected N Not affected Z Not affected C Not affec
5. OSCOFF CPUOFF and GIE are not affected The 20 bit value in R5 is incremented by 2 INCDA R5 Increment R5 by two 16 Bit MSP430X CPU 4 165 Address Instructions MOVA Syntax Operation Description Status Bits Mode Bits Examples Move the 20 bit source to the 20 bit destination MOVA Rsrc Rdst MOVA imm20 Rdst MOVA z16 Rsrc Rdst MOVA EDE Rdst MOVA amp abs20 Rdst MOVA Resrc Rdst MOVA Rsrc Rdst MOVA Rsrc z16 Rdst MOVA Rsrc amp abs20 src Rdst Rsrc dst The 20 bit source operand is moved to the 20 bit destination The source operand is not affected The previous content of the destination is lost Not affected OSCOFF CPUOFF and GIE are not affected Copy 20 bit value in R9 to R8 MOVA R9 R8 R9 gt R8 Write 20 bit immediate value 12345h to R12 MOVA 12345h R12 12345h gt R12 Copy 20 bit value addressed by R9 100h to R8 Source operand in ad dresses R9 100h LSBs and R9 102h MSBs MOVA 100h R9 R8 Index 32 K 2 words transferred Move 20 bit value in 20 bit absolute addresses EDE LSBs and EDE 2 MSBs to R12 MOVA amp EDE R12 amp EDE gt R12 2 words transferred Move 20 bit value in 20 bit addresses EDE LSBs and EDE 2 MSBs to R12 PC index 32 K MOVA EDE R12 EDE gt R12 2 words transferred Copy 20 bit value R9 points to 20 bit address to R8 Source operand in addresses R9 LSBs and R9 2 MSBs MOVA R9 R8 R9 gt R8 2 wor
6. 01036h 04766h Address 01036h is the location of the index for this example Destination Byte TONI located at address 00778h pointed to by PC F740h is the truncated 16 bit result of 00778h 1038h FF740h Address 01038h is the location of the index for this example Before After Address Address Space Space 0103Ah 0103Ah 01038h 01038h 01036h 01036h 01034h 01034h 01038h src 0077Ah 0F740h 0077Ah dst 00778h parish 00778h Sum 01036h 0579Eh 04766h 0579Eh 0579Ch Oaah 0579Ch 16 Bit MSP430X CPU 4 25 CPU Registers MSP430 Instruction with Symbolic Mode in Upper Memory If the PC points to an address above the lower 64 KB memory the PC bits 19 16 are used for the address calculation of the operand The operand may be located in memory in the range PC 32 KB because the index X is a signed 16 bit value In this case the address of the operand can overflow or underflow into the lower 64 KB memory space as shown in Figure 4 20 and Figure 4 21 Figure 4 20 Symbolic Mode Running in Upper Memory Upper Memory PC 19 16 gt 0 ia Pa PC 19 0 PC 32 KB Figure 4 21 Overflow and Underflow for the Symbolic Mode Program counter PC 16 bit signed PC index sign 10000 extended to OFFFF 20 bits Lower 64 KB Memory address NN SS PC 19 FFFFF ede PC 19 0 10000 OFFFF PC 19 0 Lower 64 KB 4 26 16 Bit MSP430X CPU Length Operation Comment Example
7. Chapter 4 16 Bit MSP430X CPU This chapter describes the extended MSP430X 16 bit RISC CPU with 1 MB memory access its addressing modes and instruction set The MSP430X CPU is implemented in all MSP430 devices that exceed 64 KB of address space Topic Page AV CPU INtrod ction m e eneee e iret as steve cer ae e a a n 4 2 4 2 interrupts ee E E E e e a a 4 4 4 3 CPU Registers meno aocena nine ae aene weve E ea E E EE e 4 5 4 4 Addressing Modes emeas eneee e a ae e e eters 4 15 4 5 MSP430 and MSP430X Instructions 2 0eeeeeeeeee 4 36 4 6 Instruction Set Description eeee eee e eee eee eee 4 58 4 1 CPU Introduction 4 1 CPU Introduction 4 2 The MSP430X CPU incorporates features specifically designed for modern programming techniques such as calculated branching table processing and the use of high level languages such as C The MSP430X CPU can address a 1 MB address range without paging In addition the MSP430X CPU has fewer interrupt overhead cycles and fewer instruction cycles in some cases than the MSP430 CPU while maintaining the same or better code density than the MSP430 CPU The MSP430X CPU is completely backwards compatible with the MSP430 CPU The MSP430X CPU features include m m m m RISC architecture Orthogonal architecture Full register access including program counter status register and stack pointer Single cycle register operations Large register
8. EDE 6t 8S 4 XORX A5A5h EDE amp EDE 6t 8 4 BITX B 12 amp EDE X Rn Rm 4 5 3 BITX 2 R5 R8 Pc 5 6 3 SUBX A 2 R6 PC X Rm 7t 108 4 ANDX 4 R7 4 R6 EDE 7 108 4 XORX B 2 R6 EDE amp EDE 7t 108 4 BITX 8 SP amp EDE EDE Rm 4 5 3 BITX B EDE R8 Pci 5 6 3 ADDX A EDE PC X Rm 7t 108 4 ANDX EDE 4 R6 EDE 7 108 4 ANDX EDE TONI amp TONI 7 108 4 BITX EDE amp TONI amp EDE Rm 4 5 3 BITX amp EDE R8 PC 5 6 3 ADDX A amp EDE PC X Rm 7 108 4 ANDX B amp EDE 4 R6 TONI 7 108 4 XORX amp EDE TONI amp TONI 7t 108 4 BITX amp EDE amp TONI t Repeat instructions require n 1 cycles where n is the number of times the instruction is executed Reduce the cycle count by one for MOV BIT and CMP instructions Reduce the cycle count by two for MOV BIT and CMP instructions 1 Reduce the cycle count by one for MOV ADD and SUB instructions 4 56 16 Bit MSP430X CPU MSP430X Address Instruction Cycles and Lengths MSP430X Extended Instructions Table 4 19 lists the length and the CPU cycles for all addressing modes of the MSP430X address instructions Table 4 19 Address Instruction Cycles and Length Execution Length of Time MCLK Instruction Addressing Mode Words CMPA CMPA MOVA ADDA ADDA Source Destination BRA SUBA MOVA SUBA Example Rn Rn 1 1 1 1 CMPA R5 R8 PC 2 2 1 1 SUBA R9 PC x Rm 4 2 MOVA R5 4 R6 EDE 4 2 MOVA R8 EDE amp EDE 4 2 MOVA R5 amp EDE Rn Rm 3 1 MOVA R5 R8 PC 3 1 MOVA R9 PC Rn Rm
9. SUBA Rsrc Rdst SUBA imm20 Rdst not src 1 Rdst gt Rdst or Rdst src gt Rast The 20 bit source operand is subtracted from the 20 bit destination register This is made by adding the 1 s complement of the source 1 to the destination The result is written to the destination register the source is not affected N Set if result is negative src gt dst reset if positive src lt dst Z Set if result is zero src dst reset otherwise src dst C Set if there is a carry from the MSB Rdst 19 reset otherwise V Set if the subtraction of a negative source operand from a positive des tination operand delivers a negative result or if the subtraction of a posi tive source operand from a negative destination operand delivers a positive result reset otherwise no overflow OSCOFF CPUOFF and GIE are not affected The 20 bit value in R5 is subtracted from R6 If a carry occurs the program continues at label TONI SUBA R5 R6 R6 R5 gt R6 JC TONI Carry occurred No carry 4 170 16 Bit MSP430X CPU
10. Set if result is negative reset if positive Set if result is zero reset otherwise Loaded from the MSB Set if an arithmetic overflow occurs the initial value is 04000h lt dst lt OCOOOh reset otherwise Set if an arithmetic overflow occurs the initial value is 040h lt dst lt OCOh reset otherwise OSCOFF CPUOFF and GIE are not affected R7 is multiplied by 2 RLA R7 Shift left R7 x 2 The low byte of R7 is multiplied by 4 RLA B R7 Shift left low byte of R7 x 2 RLA B R7 Shift left low byte of R7 x 4 a 680680 OO _o u VuaQa6a450088 a SO aoa a oO Note RLA Substitution The assembler does not recognize the instruction RLA R5 RLA B R5 or RLA B R5 It must be substituted by ADD R5 2 R5 ADD B R5 1 R5 or ADD B R5 16 Bit MSP430X CPU 4 99 MSP430 Instructions RLCL W RLC B Syntax Operation Emulation Description Rotate left through carry Rotate left through carry RLC dst or RLC W dst RLC B dst C lt MSB lt MSB 1 LSB 1 lt LSB lt C ADDC dst dst The destination operand is shifted left one position as shown in Figure 4 39 The carry bit C is shifted into the LSB and the MSB is shifted into the carry bit C Figure 4 39 Destination Operand Carry Left Shift Status Bits Mode Bits Example Example Example Set if result is negative reset if positive Set if result is zero reset othe
11. amp TONI No of Cycles Length of Instruction OWN NIO W WN NIO OO ONNI OO ONNIN MY MY HINYM YB MY HIN NN wo MOV BR ADD XOR MOV AND BR XOR MOV XOR ADD BR XOR MOV MOV MOV BR MOV ADD ADD MOV BR MOV ADD MOV AND BR CMP MOV MOV MOV BR MOV MOV MOV t MOV BIT and CMP instructions execute in 1 fewer cycle Example R5 R8 R9 R5 4 R6 R8 EDE R5 amp EDE R4 R5 R8 R5 8 R6 R5 EDE R5 amp EDE R5 R6 R9 R5 8 R6 R9 EDE JO R9 amp EDE 20 R9 2AEh 0300h 0 SP EDE TONI EDE 0 SP EDE amp TONI amp EDE R8 amp EDE amp EDE TONI amp EDE 0 SP amp EDE amp TONI 16 Bit MSP430X CPU 4 43 MSP430X Extended Instructions 4 5 2 MSP430X Extended Instructions The extended MSP430xX instructions give the MSP430X CPU full access to its 20 bit address space Most MSP430X instructions require an additional word of op code called the extension word Some extended instructions do not require an additional word and are noted in the instruction description All addresses indexes and immediate numbers have 20 bit values when preceded by the extension word There are two types of extension word O Register register mode for Format l instructions and register mode for Format ll instructions _j Extension word for all other address mode combinations 4 44 16 Bit MSP430X CPU MSP430X Extended Instr
12. 4 48 16 Bit MSP430X CPU MSP430X Extended Instructions The four possible addressing combinations for the extension word for format instructions are shown in Figure 4 29 Figure 4 29 Extended Format Instruction Formats 15 14 13 12 11 10 9 8 7 6 5 4 3 0 a src 15 0 dst dst 15 0 src 15 0 dst 15 0 If the 20 bit address of a source or destination operand is located in memory not in a CPU register then two words are used for this operand as shown in Figure 4 30 Figure 4 30 20 Bit Addresses in Memory 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Z O e aa a Ea e aAA aaa enaA Address Operand LSBs 15 0 16 Bit MSP430X CPU 4 49 MSP430X Extended Instructions Extended Single Operand Format ll Instructions Extended MSP430X Format ll instructions are listed in Table 4 14 Table 4 14 Extended Single Operand Instructions Operation Status Bits Mnemonic Operands n VN ZC CALLA dst Call indirect to subroutine 20 bit address POPM A n Rdst Popn 20 bit registers from stack 1 16 POPM W n Rdst Popn 16 bit registers from stack 1 16 PUSHM A n Rsrce Push n 20 bit registers to stack 1 16 PUSHM W n Rsrc Push n 16 bit registers to stack 1 16 PUSHX B A src Push 8 16 20 bit source to stack Se p RRCM A n Rdst Rotate right Rdst n bits through carry 1 4 0 16 20 bit register RRUM A n Rdst Rotate right Rdst n bits unsigned 1 4 0 16 20 b
13. ADD R13 0 R12 Add LSDs ADC 2 R12 Add carry to MSD The 8 bit counter pointed to by R13 is added to a 16 bit counter pointed to by R12 ADD B R13 0 R12 Add LSDs ADC B 1 R12 Add carry to MSD 4 62 16 Bit MSP430X CPU ADDLW ADD B Syntax Operation Description Status Bits Mode Bits Example Example Example MSP430 Instructions Add source word to destination word Add source byte to destination byte ADD src dst or ADD W src dst ADD B src dst src dst gt dst The source operand is added to the destination operand The previous content of the destination is lost Set if result is negative MSB 1 reset if positive MSB 0 Set if result is zero reset otherwise Set if there is a carry from the MSB of the result reset otherwise Set if the result of two positive operands is negative or if the result of two negative numbers is positive reset otherwise OSCOFF CPUOFF and GIE are not affected Ten is added to the 16 bit counter CNTR located in lower 64 K ADD W 10 amp 8CNTR Add 10 to 16 bit counter A table word pointed to by R5 20 bit address in R5 is added to R6 The jump to label TONI is performed on a carry ADD W R5 R6 Add table word to R6 R6 19 16 0 JC TONI Jump if carry No carry A table byte pointed to by R5 20 bit address is added to R6 The jump to label TONI is performed if no carry occurs The table pointer is auto incremented by 1 R6 19 8 0 ADD
14. C Set V Reset OSCOFF CPUOFF and GIE are not affected RAM byte LEO is tested PC is pointing to upper memory If it is negative continue at LEONEG if it is positive but not zero continue at LEOPOS TSTX B LEO Test LEO JN LEONEG LEO is negative JZ LEOZERO LEO is zero LEOPOS _ LEO is positive but not zero LEONEG LEO is negative LEOZERO _ LEO is zero 4 154 16 Bit MSP430X CPU XORX A XORX W XORX B Syntax Operation Description Status Bits Mode Bits Example Example Example Extended Instructions Exclusive OR source address word with destination address word Exclusive OR source word with destination word Exclusive OR source byte with destination byte XORX A src dst XORX src dst or XORX W src dst XORX B src dst src xor dst gt dst The source and destination operands are exclusively ORed The result is placed into the destination The source operand is not affected The previous contents of the destination are lost Both operands may be located in the full address space N Set if result is negative MSB 1 reset if positive MSB 0 Z Set if result is zero reset otherwise C Set if result is not zero reset otherwise carry not Zero V Set if both operands are negative before execution reset otherwise OSCOFF CPUOFF and GIE are not affected Toggle bits in address word CNTR 20 bit data with information in address word TONI 20 bit addres
15. If it is negative continue at R7NEG if it is positive but not zero continue at R7POS TST B R7 Test low byte of R7 JN R7NEG Low byte of R7 is negative JZ R7ZERO Low byte of R7 is zero R7POS n Low byte of R7 is positive but not zero R7NEG ti Low byte of R7 is negative R7ZERO _ Low byte of R7 is zero 16 Bit MSP430X CPU 4 111 MSP430 Instructions XOR W XOR B Syntax Operation Description Status Bits Mode Bits Example Example Example Exclusive OR source word with destination word Exclusive OR source byte with destination byte XOR dst or XOR W dst XOR B dst src xor dst gt dst The source and destination operands are exclusively ORed The result is placed into the destination The source operand is not affected The previous content of the destination is lost N Set if result is negative MSB 1 reset if positive MSB 0 Z Set if result is zero reset otherwise C Set if result is not zero reset otherwise C not Z V Set if both operands are negative before execution reset otherwise OSCOFF CPUOFF and GIE are not affected Toggle bits in word CNTR 16 bit data with information bit 1 in address word TONI Both operands are located in lower 64 K XOR amp TONI amp CNTR Toggle bits in CNTR A table word pointed to by R5 20 bit address is used to toggle bits in R6 R6 19 16 0 XOR R5 R6 Toggle bits in R6 Reset to zero those bits in the low
16. four bit positions as shown in Figure 4 47 The MSB retains its value sign RRAM operates equal to a signed division by 2 4 8 16 The MSB is retained and shifted into MSB 1 The LSB 1 is shifted into the LSB and the LSB is shifted into the carry bit C The word instruction RRAM W clears the bits Rdst 19 16 Note This instruction does not use the extension word N Set if result is negative A Rdst 19 1 reset if Rdst 19 O W Rdst 15 1 reset if Rdst 15 0 Z Set if result is zero reset otherwise C Loaded from the LSB n 1 LSB 1 n 2 LSB 2 n 3 or LSB 3 n 4 V Reset OSCOFF CPUOFF and GIE are not affected The signed 20 bit number in R5 is shifted arithmetically right two positions RRAM A 2 R5 R5 4 gt R5 The signed 20 bit value in R15 is multiplied by 0 75 0 5 0 25 x R15 PUSHM A 1 R15 Save extended R15 on stack RRAM A 1 R15 R15 x 0 5 gt R15 ADDX A SP R15 R15 x 0 5 R15 1 5 x R15 gt R15 RRAM A 1 R15 1 5 x R15 x 0 5 0 75 x R15 gt R15 Figure 4 47 Rotate Right Arithmetically RRAM W and RRAM A 19 16 15 0 19 0 ae a 16 Bit MSP430X CPU 4 139 Extended Instructions RRAX A Rotate Right Arithmetically the 20 bit operand RRAX W Rotate Right Arithmetically the 16 bit operand RRAX B Rotate Right Arithmetically the 8 bit operand Syntax RRAX A Rdst RRAX W _ Rast RRAX Rdst RRAX B _ Rast RRAX A dst RRAX W dst or RRAX dst RRA
17. reset if MSB is 0 Z Set if result is zero reset otherwise C Set if the BCD result is too large address word gt 99999h word gt 9999h byte gt 99h reset otherwise V Undefined OSCOFF CPUOFF and GIE are not affected The 40 bit counter pointed to by R12 and R13 is incremented decimally DADDX A 1 0 R12 Increment lower 20 bits DADCX A 0 R13 Add carry to upper 20 bits 16 Bit MSP430X CPU 4 123 Extended Instructions DADDX A DADDX W DADDX B Syntax Operation Description Status Bits Mode Bits Example Example Example 4 124 Add source address word and carry decimally to destination address word Add source word and carry decimally to destination word Add source byte and carry decimally to destination byte DADDX A src dst DADDX src dst or DADDX W src dst DADDX B src dst src dst C dst decimally The source operand and the destination operand are treated as two B four W or five A binary coded decimals BCD with positive signs The source operand and the carry bit C are added decimally to the destination operand The source operand is not affected The previous contents of the destination are lost The result is not defined for non BCD numbers Both operands may be located in the full address space N Set if MSB of result is 1 address word gt 79999h word gt 7999h byte gt 79h reset if MSB is 0 Z Set if result is zero reset otherwise C Set if
18. 141 dst CALLA Rdst 0 0 0 1 0 1 1 1 0 0 0 amp abs 19 16 CALLA amp abs20 amp abs 15 0 0 0 0 1 0 1 1 1 0 0 41 x 19 16 CALLA EDE x 15 0 CALLA x PC 0 0 0 1 0 1 1 1 0 14 1 imm 19 16 CALLA imm20 imm 15 0 Reserved 0 0 0 1 0 1 1 1 0 1 0 x x x x Reserved 0 0 0 1 0 1i1 1y t x x x x x x PUSHM A 0 0 0 1 0 0 0 n 1 dst PUSHM A n Rdst PUSHM W 0 0 0 1 0 0 1 n 1 dst PUSHM W n Rdst POPM A 0 0 0 1 0 1 0 n 1 dst n 1 POPM A n Rdst POPM W 0 0 0 1 0 cl ak n 1 dst n 1 POPM W n Rdst 16 Bit MSP430X CPU MSP430 Instructions 4 6 2 MSP430 Instructions The MSP430 instructions are listed and described on the following pages 16 Bit MSP430X CPU 4 61 MSP430 Instructions ADCLW ADC B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Add carry to destination Add carry to destination ADC dst or ADC W dst ADC B dst dst C gt dst ADDC 0 dst ADDC B_ 0 dst The carry bit C is added to the destination operand The previous contents of the destination are lost N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if dst was incremented from OFFFFh to 0000 reset otherwise Set if dst was incremented from OFFh to 00 reset otherwise V Set if an arithmetic overflow occurs otherwise reset OSCOFF CPUOFF and GIE are not affected The 16 bit counter pointed to by R13 is added to a 32 bit counter pointed to by R12
19. 16 bit return address lower 64 K pushed onto the stack by a CALL instruction is restored to the PC The program continues at the address following the subroutine call The four MSBs of the program counter PC 19 16 are cleared Not affected PC 19 16 Cleared OSCOFF CPUOFF and GIE are not affected Call a subroutine SUBR in the lower 64 K and return to the address in the lower 64K after the CALL CALL SUBR Call subroutine starting at SUBR E Return by RET to here PUSH R14 Save R14 16 bit data Subroutine code POP R14 Restore R14 RET Return to lower 64 K Figure 4 37 The Stack After a RET Instruction Item n SP SP PCnetum Oo Stack before RET Stack after RET instruction instruction 16 Bit MSP430X CPU 4 97 MSP430 Instructions RETI Syntax Operation Description Status Bits Mode Bits Example Return from interrupt RETI SP SR 15 0 Restore saved status register SR with PC 19 16 SP 2 SP SP PC 15 0 Restore saved program counter PC 15 0 SP 2 gt SP House keeping The status register is restored to the value at the beginning of the interrupt service routine This includes the four MSBs of the program counter PC 19 16 The stack pointer is incremented by two afterwards The 20 bit PC is restored from PC 19 16 from same stack location as the status bits and PC 15 0 The 20 bit program counter is restored to the value at the beginning of the interrupt service routine The
20. 19 16 0 4 18 19 1615 0 FFFFF CPU Register Rn 16 bit byte index 16 bit signed index 10000 OFFFF a a ha x 16 bit signed add Rn 19 0 pa o z oa Memory address Length Two or three words Operation The signed 16 bit index is located in the next word after the instruction and is added to the CPU register Rn The resulting bits 19 16 are cleared giving a truncated 16 bit memory address which points to an operand address in the range 00000h to OFFFFh The operand is the content of the addressed memory location Comment Valid for source and destination The assembler calculates the register index and inserts it 16 Bit MSP430X CPU Example CPU Registers ADD B 1000h R5 O0FOOOH R6 The previous instruction adds the 8 bit data contained in source byte 1000h R5 and the destination byte OFOOOh R6 and places the result into the destination byte Source and destination bytes are both located in the lower 64 KB due to the cleared bits 19 16 of registers R5 and R6 Source The byte pointed to by R5 1000h results in address 0479Ch 1000h 0579Ch after truncation to a 16 bit address Destination The byte pointed to by R6 FOOOh results in address 01778h FOOOh 00778h after truncation to a 16 bit address Before After Address Register Address Register Space Space 1103Ah R5 1103Ah PC R5 11038h R6 11038h R6 11036h 11036h 11034h 11034h 01778h 32h src 0077Ah F000h 0077Ah 45h_ dst 007
21. 2 0 R6 is subtracted from R5 If the result is negative program continues at Label2 Program in full memory range SUB R6 R5 R5 R6 gt R5 JN Label2 R5 is negative R6 gt R5 N 1 R5 0 Continue here R7 20 bit counter is decremented If its content is below zero the program continues at Label4 Program in full memory range SUBA 1 R7 Decrement R7 JN Label4 R7 lt 0 Go to Label4 R7 0 Continue here 4 90 16 Bit MSP430X CPU JNC JLO Syntax Operation Description Status Bits Mode Bits Example Example MSP430 Instructions Jump if No carry Jump if lower unsigned JNC label JLO label lf C 0 PC 2 x Offset PC lfC 1 execute following instruction The carry bit C in the status register is tested If it is reset the signed 10 bit word offset contained in the instruction is multiplied by two sign extended and added to the 20 bit program counter PC This means a jump in the range 511 to 512 words relative to the PC in the full memory range If C is set the instruction after the jump is executed JNC is used for the test of the carry bit C JLO is used for the comparison of unsigned numbers Status bits are not affected OSCOFF CPUOFF and GIE are not affected If byte EDE lt 15 the program continues at Label2 Unsigned data Data in lower 64 K program in full memory range CMP B 15 amp EDE ls EDE lt 15 Info to C JLO Label2 Yes EDE lt 15 C 0 No
22. 20 bit result reset otherwise Set if the result of two positive operands is negative or if the result of two negative numbers is positive reset otherwise OSCOFF CPUOFF and GIE are not affected R5 is increased by 0A4320h The jump to TONI is performed if a carry occurs ADDA 0A4320h R5 Add A4320h to 20 bit R5 JC TONI Jump on carry No carry occurred 16 Bit MSP430X CPU 4 157 Address Instructions BRA Syntax Operation Emulation Description Status Bits Mode Bits Examples Branch to destination BRA dst dst PC MOVA dst PC An unconditional branch is taken to a 20 bit address anywhere in the full address space All seven source addressing modes can be used The branch instruction is an address word instruction If the destination address is contained in a memory location X it is contained in two ascending words X LSBs and X 2 MSBs N Not affected Z Not affected C Not affected V Not affected OSCOFF CPUOFF and GIE are not affected Examples for all addressing modes are given Immediate Mode Branch to label EDE located anywhere in the 20 bit address space or branch directly to address BRA EDE MOVA imm20 PC BRA 01AA04h Symbolic Mode Branch to the 20 bit address contained in addresses EXEC LSBs and EXEC 2 MSBs EXEC is located at the address PC X where X is within 32 K Indirect addressing BRA EXEC MOVA z16 PC PC Note if the 16 bit index is not suffici
23. 21034h 21038h 21036h 21034h PC R5 3579Dh R6 00778h 00778h 32h src 0077Ah 0000h 0077Ah 45h__ dst 00778h 00778h 00778h 77h Sum 3579Dh 3579Dh 3579Ch R5 3579Ch 16 Bit MSP430X CPU 4 33 CPU Registers 4 4 7 Immediate Mode The Immediate mode allows accessing constants as operands by including the constant in the memory location following the instruction The program counter PC is used with the Indirect Autoincrement mode The PC points to the immediate value contained in the next word After the fetching of the immediate operand the PC is incremented by 2 for byte word or address word instructions The Immediate mode has two addressing possibilities Lj 8 or 16 bit constants with MSP430 instructions LJ 20 bit constants with MSP430X instruction MSP430 Instructions with Immediate Mode If an MSP430 instruction is used with Immediate addressing mode the constant is an 8 or 16 bit value and is stored in the word following the instruction Length Two or three words One word less if a constant of the constant generator can be used for the immediate operand Operation The 16 bit immediate source operand is used together with the 16 bit destination operand Comment Valid only for the source operand Example ADD 3456h amp TONI This instruction adds the 16 bit immediate operand 3456h to the data in the destination address TONI Source 16 bit immediate value 3456h Destination Word at address
24. 4 24 Format of the Conditional Jump Instructions 15 8 0 13 12 10 9 Op Code 10 Bit Signed PC Offset Table 4 6 Conditional Jump Instructions Mnemonic S Reg D Reg Operation JEQ JZ Label Jump to label if zero bit is set JNE JNZ Label Jump to label if zero bit is reset Jc Label Jump to label if carry bit is set JNC Label Jump to label if carry bit is reset JN Label Jump to label if negative bit is set JGE Label Jump to label if N XOR V 0 JL Label Jump to label if N XOR V 1 JMP Label Jump to label unconditionally 16 Bit MSP430X CPU 4 39 MSP430 and MSP430X Instructions Emulated Instructions In addition to the MSP430 and MSP430X instructions emulated instructions are instructions that make code easier to write and read but do not have op codes themselves Instead they are replaced automatically by the assembler with a core instruction There is no code or performance penalty for using emulated instructions The emulated instructions are listed in Table 4 7 Table 4 7 Emulated Instructions Instruction Explanation Emulation ADC B dst Add Carry to dst ADDC B 0 dst BR dst Branch indirectly dst MOV dst PC CLR B dst Clear dst MOV B 0 dst CLRC Clear Carry bit BIC 1 SR LRN Clear Negative bit BIC 4 SR CLRZ Clear Zero bit BIC 2 SR DADC B dst Add Carry to dst decimally DADD B 0 dst DEC B dst Decrement dst by 1 SUB B 1 dst DECD B dst Decrement dst by 2 SUB B 2 dst DINT Disable in
25. A few examples MOV W LABEL PC Branch to address LABEL lower 64 KB MOVA LABEL PC Branch to address LABEL 1MB memory MOV W LABEL PC Branch to address in word LABEL lower 64 KB MOV W R14 PC Branch indirect to address in R14 lower 64 KB ADDA 4 PC Skip two words 1 MB memory The BR and CALL instructions reset the upper four PC bits to 0 Only addresses in the lower 64 KB address range can be reached with the BR or CALL instruction When branching or calling addresses beyond the lower 64 KB range can only be reached using the BRA or CALLA instructions Also any instruction to directly modify the PC does so according to the used addressing mode For example MOV W value PC will clear the upper four bits of the PC because it is a W instruction 16 Bit MSP430X CPU 4 5 CPU Registers The program counter is automatically stored on the stack with CALL or CALLA instructions and during an interrupt service routine Figure 4 4 shows the storage of the program counter with the return address after a CALLA instruction A CALL instruction stores only bits 15 0 of the PC Figure 4 4 Program Counter Storage on the Stack for CALLA SPoid SP The RETA instruction restores bits 19 0 of the program counter and adds 4 to the stack pointer The RET instruction restores bits 15 0 to the program counter and adds 2 to the stack pointer 4 6 16 Bit MSP430X CPU CPU Registers 4 3 2 Stack Pointe
26. EDE 15 Continue The word TONI is added to R5 If no carry occurs continue at Label0 The address of TONI is within PC 32 K ADD TONI R5 TONI R5 gt R5 Carry gt C JNC LabelO No carry Carry 1 continue here 16 Bit MSP430X CPU 4 91 MSP430 Instructions JNZ JNE Syntax Operation Description Status Bits Mode Bits Example Example Example Jump if Not Zero Jump if Not Equal JNZ label JNE label If Z 0 PC 2 x Offset gt PC lfZ 1 execute following instruction The zero bit Z in the status register is tested If it is reset the signed 10 bit word offset contained in the instruction is multiplied by two sign extended and added to the 20 bit program counter PC This means a jump in the range 511 to 512 words relative to the PC in the full memory range If Z is set the instruction after the jump is executed JNZ is used for the test of the Zero bit Z JNE is used for the comparison of operands Status bits are not affected OSCOFF CPUOFF and GIE are not affected The byte STATUS is tested If it is not zero the program continues at Labels The address of STATUS is within PC 32 K TST B STATUS Ils STATUS 0 JNZ Label3 No proceed at Label3 Yes continue here If word EDE 1500 the program continues at Label2 Data in lower 64 K program in full memory range CMP 1500 amp 8EDE Is EDE 1500 Info to SR JNE Label2 No EDE 1500 Yes R5 1500 Continue
27. Example Example MSP430 Instructions Double increment destination Double increment destination INCD dst or INCD W dst INCD B dst dst 2 gt dst ADD 2 dst ADD B 2 dst The destination operand is incremented by two The original contents are lost N Set if result is negative reset if positive Z Set if dst contained OFFFEh reset otherwise Set if dst contained OFEh reset otherwise C Set if dst contained OFFFEh or OFFFFh reset otherwise Set if dst contained OFEh or OFFh reset otherwise V Set if dst contained O7FFEh or O07FFFh reset otherwise Set if dst contained 07Eh or 07Fh reset otherwise OSCOFF CPUOFF and GIE are not affected The item on the top of the stack TOS is removed without using a register PUSH R5 R5 is the result of a calculation which is stored in the system stack INCD SP Remove TOS by double increment from stack Do not use INCD B SP is a word aligned register RET The byte on the top of the stack is incremented by two INCD B 0 SP Byte on TOS is increment by two 16 Bit MSP430X CPU 4 83 MSP430 Instructions INVLW INV B Syntax Operation Emulation Emulation Description Status Bits Mode Bits Example Example Invert destination Invert destination INV dst INV B dst NOT dst gt dst XOR OFFFFh dst XOR B 0FFh dst The destination operand is inverted The original contents are lost N Set if result is negative reset i
28. OSCOFF CPUOFF and GIE are not affected The bits set in R5 20 bit data are used as a mask AAA55h for the address word TOM located in two words If the result is zero a branch is taken to label TONI MOVA AAA55h R5 Load 20 bit mask to R5 ANDX A R5 TOM TOM and R5 gt TOM JZ TONI Jump if result O Result gt 0 or shorter ANDX A AAA55h TOM TOM and AAA55h gt TOM JZ TONI Jump if result O A table byte pointed to by R5 20 bit address is logically ANDed with R6 R6 19 8 0 The table pointer is auto incremented by 1 ANDX B R5 R6 AND table byte with R6 R5 1 16 Bit MSP430X CPU 4 117 Extended Instructions BICX A BICX W BICX B Syntax Operation Description Status Bits Mode Bits Example Example Example 4 118 Clear bits set in source address word in destination address word Clear bits set in source word in destination word Clear bits set in source byte in destination byte BICX A src dst BICX src dst or BICX W src dst BICX B src dst not src and dst dst The inverted source operand and the destination operand are logically ANDed The result is placed into the destination The source operand is not affected Both operands may be located in the full address space N Not affected Z Not affected C Not affected V Not affected OSCOFF CPUOFF and GIE are not affected The bits 19 15 of R5 20 bit data are cleared BICX A 0F8000h R5 Clear R5 19 15
29. STATUS is set to 10 Then a jump to label MAINLOOP is made Data in lower 64 K program in full memory range MOV B 10 amp STATUS Set STATUS to 10 JMP MAINLOOP Go to main loop The interrupt vector TAIV of Timer_A3 is read and used for the program flow Program in full memory range but interrupt handlers always starts in lower 64K ADD amp TAIV PC Add Timer_A interrupt vector to PC RETI No Timer_A interrupt pending JMP IHCCR1 Timer block 1 caused interrupt JMP IHCCR2 Timer block 2 caused interrupt RETI No legal interrupt return 16 Bit MSP430X CPU 4 89 MSP430 Instructions JN Syntax Operation Description Status Bits Mode Bits Example Example Example Jump if Negative JN label lf N 1 PC 2 x Offset PC If N 0 execute following instruction The negative bit N in the status register is tested If it is set the signed 10 bit word offset contained in the instruction is multiplied by two sign extended and added to the 20 bit program counter PC This means a jump in the range 511 to 512 words relative to the PC in the full memory range If N is reset the instruction after the jump is executed Status bits are not affected OSCOFF CPUOFF and GIE are not affected The byte COUNT is tested If it is negative program execution continues at Label0 Data in lower 64 K program in full memory range TST B amp COUNT ls byte COUNT negative JN LabelO Yes proceed at LabelO COUNT
30. V Set if the result of two positive operands is negative or if the result of two negative numbers is positive reset otherwise OSCOFF CPUOFF and GIE are not affected The 40 bit counter pointed to by R12 and R13 is incremented INCX A ADCX A R12 R13 Increment lower 20 bits Add carry to upper 20 bits 16 Bit MSP430X CPU ADDX A ADDX W ADDX B Syntax Operation Description Status Bits Mode Bits Example Example Example Extended Instructions Add source address word to destination address word Add source word to destination word Add source byte to destination byte ADDX A _ src dst ADDX src dst or ADDX W src dst ADDX B src dst src dst gt dst The source operand is added to the destination operand The previous contents of the destination are lost Both operands can be located in the full address space Set if result is negative MSB 1 reset if positive MSB 0 Set if result is zero reset otherwise Set if there is a carry from the MSB of the result reset otherwise Set if the result of two positive operands is negative or if the result of two negative numbers is positive reset otherwise OSCOFF CPUOFF and GIE are not affected Ten is added to the 20 bit pointer CNTR located in two words CNTR LSBs and CNTR 2 MSBs ADDX A 10 CNTR Add 10 to 20 bit pointer A table word 16 bit pointed to by R5 20 bit address is added to R6 The jump to label TONI is performed on
31. a carry ADDX W R5 R6 JC TONI Add table word to R6 Jump if carry No carry A table byte pointed to by R5 20 bit address is added to R6 The jump to label TONI is performed if no carry occurs The table pointer is auto incremented by 1 ADDX B R5 R6 JNC TONI Add table byte to R6 R5 1 R6 000xxh Jump if no carry Carry occurred Note Use ADDA for the following two cases for better code density and execution ADDX A Rsrc Rdst or ADDX A imm20 Rdst 16 Bit MSP430X CPU 4 115 Extended Instructions ADDCX A ADDCX W ADDCX B Syntax Operation Description Status Bits Mode Bits Example Example Example Add source address word and carry to destination address word Add source word and carry to destination word Add source byte and carry to destination byte ADDCX A src dst ADDCX src dst or ADDCX W src dst ADDCX B src dst src dst C gt dst The source operand and the carry bit C are added to the destination operand The previous contents of the destination are lost Both operands may be located in the full address space Set if result is negative MSB 1 reset if positive MSB 0 Set if result is zero reset otherwise Set if there is a carry from the MSB of the result reset otherwise Set if the result of two positive operands is negative or if the result of two negative numbers is positive reset otherwise OSCOFF CPUOFF and GIE are not affected Constant 15 an
32. affected OSCOFF CPUOFF and GIE are not affected The 16 bit decimal counter pointed to by R13 is added to a 32 bit counter pointed to by R12 CLRC C 0 defines start DADD R13 0 R12 add 16 bit counter to low word of 32 bit counter DADC 2 R12 add carry to high word of 32 bit counter 4 72 16 Bit MSP430X CPU CLRN Syntax Operation Emulation Description Status Bits Mode Bits Example SUBR SUBRET MSP430 Instructions Clear negative bit CLRN 0 gt N or NOT src AND dst gt dst BIC 4 SR The constant 04h is inverted OFFFBh and is logically ANDed with the destination operand The result is placed into the destination The clear negative bit instruction is a word instruction N Reset to 0 Z Not affected C Not affected V Not affected OSCOFF CPUOFF and GIE are not affected The Negative bit in the status register is cleared This avoids special treatment with negative numbers of the subroutine called CLRN CALL SUBR JN SUBRET If input is negative do nothing and return RET 16 Bit MSP430X CPU 4 73 MSP430 Instructions CLRZ Syntax Operation Emulation Description Status Bits Mode Bits Example Clear zero bit CLRZ 0 gt Z or NOT src AND dst gt dst BIC 2 SR The constant 02h is inverted OFFFDh and logically ANDed with the destination operand The result is placed into the destination The clear zero bit instruction is a word instr
33. are MOVX A MOVX A MOVX A MOVX A MOVX A MOVX A Rsrc Rdst imm20 Rdst amp abs20 Rdst Rsrc Radst Rsrc Rdst Rsrc amp abs20 MOVA Rsrc Rdst Reg Reg MOVA imm20 Rdst Immediate Reg MOVA amp abs20 Rdst Absolute Reg MOVA Rsrc Rdst _ Indirect Reg MOVA Rsrc Rdst Indirect Auto Reg MOVA Rsrc amp abs20 Reg Absolute The next four replacements are possible only if 16 bit indexes are sufficient for the addressing MOVX A MOVX A MOVX A MOVX A z20 Rsrc Rdst Rsrc z20 Rdst symb20 Rdst Rsrc symb20 MOVA z16 Rsrc Rdst Indexed Reg MOVA Rsrc z16 Rdst Reg Indexed MOVA symb16 Rdst Symbolic Reg MOVA Rsrc symb16 Reg Symbolic 16 Bit MSP430X CPU 4 131 Extended Instructions POPM A POPM W Syntax Operation Description Status Bits Mode Bits Example Example Restore n CPU registers 20 bit data from the stack Restore n CPU registers 16 bit data from the stack POPM A n Rdst 1 lt n lt 16 POPM W _ n Rdst or POPM n Rdst 1 lt n lt 16 POPM A Restore the register values from stack to the specified CPU registers The stack pointer SP is incremented by four for each register restored from stack The 20 bit values from stack 2 words per register are restored to the registers POPM W Restore the 16 bit register values from stack to the specified CPU registers The stack pointer SP is incremented by two for each register restored from stack The 16 bit values from stack one word per
34. are cleared bits 19 16 are left unchanged and bits 15 8 are swapped with bits 7 0 When the W extension is used bits 15 8 are swapped with bits 7 0 of the addressed word Not affected OSCOFF CPUOFF and GIE are not affected Exchange the bytes of RAM address word EDE MOVX A 23456h 8EDE 23456h gt EDE SWPBX A EDE 25634h gt EDE Exchange the bytes of R5 MOVA 23456h R5 23456h gt R5 SWPBX W R5 05634h gt R5 Figure 4 55 Swap Bytes SWPBX A Register Mode Before SWPBX A 19 16 15 8 7 0 After SWPBX A 19 16 15 8 7 0 4 150 16 Bit MSP430X CPU Extended Instructions Figure 4 56 Swap Bytes SWPBX A In Memory Before SWPBX A 31 20 19 16 15 8 After SWPBX A 31 20 19 16 15 8 N N oO Oo Oo Figure 4 57 Swap Bytes SWPBX W Register Mode Before SWPBX 19 16 15 8 7 High Byte Low Byte After SWPBX 19 16 15 8 Figure 4 58 Swap Bytes SWPBX W In Memory Before SWPBX 15 8 High Byte Low Byte After SWPBX 15 8 N N N Low Byte High Byte 16 Bit MSP430X CPU 4 151 Extended Instructions SXTX A SXTX W Syntax Operation Description Status Bits Mode Bits Example Extend sign of lower byte to address word Extend sign of lower byte to word SXTX A dst SXTX W dst or SXTX dst dst 7 gt dst 15 8 Rdst 7 gt Rdst 19 8 Register Mode Register Mode The sign of the low byte of the operand Rdst 7 is extended into the bits Rdst 19 8 Other Modes SXTX A
35. bits A table word pointed to by R5 20 bit address is used to clear bits in R7 R7 19 16 0 BICX W R5 R7 Clear bits in R7 A table byte pointed to by R5 20 bit address is used to clear bits in output Port BICX B R5 amp P10UT Clear I O port P1 bits 16 Bit MSP430X CPU BISX A BISX W BISX B Syntax Operation Description Status Bits Mode Bits Example Example Example Extended Instructions Set bits set in source address word in destination address word Set bits set in source word in destination word Set bits set in source byte in destination byte BISX A src dst BISX src dst or BISX W src dst BISX B src dst src or dst gt dst The source operand and the destination operand are logically ORed The result is placed into the destination The source operand is not affected Both operands may be located in the full address space N Not affected Z Not affected C Not affected V Not affected OSCOFF CPUOFF and GIE are not affected Bits 16 and 15 of R5 20 bit data are set to one BISX A 018000h R5 Set R5 16 15 bits A table word pointed to by R5 20 bit address is used to set bits in R7 BISX W R5 R7 A table byte pointed to by R5 20 bit address is used to set bits in output Port1 Set bits in R7 BISX B R5 amp P10UT Set I O port P1 bits 16 Bit MSP430X CPU 4 119 Extended Instructions BITX A BITX W BITX B Syntax Operation Description Status Bit
36. made by adding the 1 s complement of the source 1 to the destination The source operand is not affected the result is written to the destination operand N Set if result is negative src gt dst reset if positive src lt dst Z Set if result is zero src dst reset otherwise src dst C Set if there is a carry from the MSB reset otherwise V Set if the subtraction of a negative source operand from a positive des tination operand delivers a negative result or if the subtraction of a posi tive source operand from a negative destination operand delivers a positive result reset otherwise no overflow OSCOFF CPUOFF and GIE are not affected A 16 bit constant 7654h is subtracted from RAM word EDE SUB 7654h amp EDE Subtract 7654h from EDE A table word pointed to by R5 20 bit address is subtracted from R7 Afterwards if R7 contains zero jump to label TONI R5 is then auto incremented by 2 R7 19 16 0 SUB R5 R7 Subtract table number from R7 R5 2 JZ TONI R7 R5 before subtraction R7 lt gt R5 before subtraction Byte CNT is subtracted from byte R12 points to The address of CNT is within PC 32 K The address R12 points to is in full memory range SUB B CNT 0 R12 Subtract CNT from R12 16 Bit MSP430X CPU 4 107 MSP430 Instructions SUBC W SUBC B Syntax Operation Description Status Bits Mode Bits Example Example Example Subtract source word with c
37. negative MSB 1 reset otherwise MSB 0 Z Set if result is zero reset otherwise C Loaded from the LSB V Reset OSCOFF CPUOFF and GIE are not affected The signed 16 bit number in R5 is shifted arithmetically right one position RRA R5 R5 2 gt R5 The signed RAM byte EDE is shifted arithmetically right one position RRA B EDE EDE 2 gt EDE Figure 4 40 Rotate Right Arithmetically RRA B and RRA W 19 15 7 0 zz 19 15 nc 16 Bit MSP430X CPU 4 101 MSP430 Instructions RRC W RRC B Syntax Operation Description Status Bits Mode Bits Example Rotate Right through carry destination word Rotate Right through carry destination byte RRC dst or RRC W dst RRC B dst C gt MSB gt MSB 1 gt LSB 1 LSB gt C The destination operand is shifted right by one bit position as shown in Figure 4 41 The carry bit C is shifted into the MSB and the LSB is shifted into the carry bit C N Set if result is negative MSB 1 reset otherwise MSB 0 Z Set if result is zero reset otherwise C Loaded from the LSB V Reset OSCOFF CPUOFF and GIE are not affected RAM word EDE is shifted right one bit position The MSB is loaded with 1 SETC Prepare carry for MSB RRC EDE EDE EDE 1 8000h Figure 4 41 Rotate Right through Carry RRC B and RRC W 19 15 7 0 19 15 4 102 16 Bit MSP430X CPU SBC W SBC B Syntax Operation E
38. present identically to mask jump BIC Mask SP INCD SP Housekeeping inverse to PUSH instruction at the start of interrupt subroutine Corrects the stack pointer RETI _ ooo _ __ _ __ a_an6_ nl Note Enable Interrupt The instruction following the enable interrupt instruction EINT is always executed even if an interrupt service request is pending when the interrupts are enable l a SSS 16 Bit MSP430X CPU 4 81 MSP430 Instructions INCLW INC B Syntax Operation Emulation Description Status Bits Mode Bits Example Increment destination Increment destination INC dst or INC W dst INC B dst dst 1 gt dst ADD 1 dst The destination operand is incremented by one The original contents are lost N Set if result is negative reset if positive Z Set if dst contained OFFFFh reset otherwise Set if dst contained OFFh reset otherwise C Set if dst contained OFFFFh reset otherwise Set if dst contained OFFh reset otherwise V Set if dst contained O7FFFh reset otherwise Set if dst contained 07Fh reset otherwise OSCOFF CPUOFF and GIE are not affected The status byte STATUS of a process is incremented When it is equal to 11 a branch to OVFL is taken INC B STATUS CMP B 11 STATUS JEQ OVFL 4 82 16 Bit MSP430X CPU INCD W INCD B Syntax Operation Emulation Emulation Example Status Bits Mode Bits
39. program continues at the address following the last executed instruction when the interrupt was granted The stack pointer is incremented by two afterwards N restored from stack Z restored from stack C restored from stack V restored from stack OSCOFF CPUOFF and GIE are restored from stack Interrupt handler in the lower 64 K A 20 bit return address is stored on the stack INTRPT PUSHM A 2 R14 Save R14 and R13 20 bit data w Interrupt handler code POPM A 2 R14 Restore R13 and R14 20 bit data RETI Return to 20 bit address in full memory range 4 98 16 Bit MSP430X CPU RLA W RLA B Syntax Operation Emulation Description MSP430 Instructions Rotate left arithmetically Rotate left arithmetically RLA dst or RLA W dst RLA B dst C lt MSB lt MSB 1 LSB 1 lt LSB lt 0 ADD dst dst ADD B dst dst The destination operand is shifted left one position as shown in Figure 4 38 The MSB is shifted into the carry bit C and the LSB is filled with 0 The RLA instruction acts as a signed multiplication by 2 An overflow occurs if dst gt 04000h and dst lt OCOOOh before operation is performed the result has changed sign Figure 4 38 Destination Operand Arithmetic Shift Left Status Bits Mode Bits Example Example Word 15 0 fol eee ee ae Byte 7 0 An overflow occurs if dst gt 040h and dst lt OCOh before the operation is performed the result has changed sign
40. results in address 45678h 2100h 7778h Before After Address Register Address Register Space Space 21038h R5 3579Ch 21038h PC R5 3579Ch R6 45678h 21036h R6 45678h PC 21034h 21036h 21034h 45678h 5432h src 4777Ah 02100h 4777Ah 2345h_ dst 47778h 47778h 47778h 7777h Sum 3579Eh 3579Eh 3579Ch 3579Ch R5 4 32 16 Bit MSP430X CPU CPU Registers 4 4 6 Indirect Autoincrement Mode The Indirect Autoincrement mode uses the contents of the CPU register Rsrc as the source operand Rsrc is then automatically incremented by 1 for byte instructions by 2 for word instructions and by 4 for address word instructions immediately after accessing the source operand If the same register is used for source and destination it contains the incremented address for the destination access Indirect Autoincrement mode always uses 20 bit addresses Length One two or three words Operation The operand is the content of the addressed memory location Comment Valid only for the source operand Example ADD B R5 0 R6 This instruction adds the 8 bit data contained in the source and the destination addresses and places the result into the destination Source Byte pointed to by R5 R5 contains address 3 579Ch for this example Destination Byte pointed to by R6 Oh which results in address 0778h for this example Before After Address Register Address Register Space Space R5 3579Ch 21038h R6 00778h 21036h PC
41. the carry flag RRCM W 2 R6 R6 R6 2 R6 19 16 0 Figure 4 50 Rotate Right Through Carry RRCM W and RRCM A 19 16 15 0 eee 19 0 tC 4 142 16 Bit MSP430X CPU RRCX A RRCX W RRCX B Syntax Operation Description Status Bits Mode Bits Extended Instructions Rotate Right through carry the 20 bit operand Rotate Right through carry the 16 bit operand Rotate Right through carry the 8 bit operand RRCX A Rdst RRCX W_ Rast RRCX Rdst RRCX B Rast RRCX A dst RRCX W_ dst or RRCX dst RRCX B dst C gt MSB gt MSB 1 gt LSB 1 LSB gt C Register Mode for the destination the destination operand is shifted right by one bit position as shown in Figure 4 51 The word instruction RRCX W clears the bits Rdst 19 16 the byte instruction RRCX B clears the bits Rdst 19 8 The carry bit C is shifted into the MSB the LSB is shifted into the carry bit All other modes for the destination the destination operand is shifted right by one bit position as shown in Figure 4 52 The carry bit C is shifted into the MSB the LSB is shifted into the carry bit All addressing modes with the ex ception of the Immediate Mode are possible in the full memory N Set if result is negative A dst 19 1 reset if dst 19 O W dst 15 1 reset if dst 15 0 B dst 7 1 reset if dst 7 0 Z Set if result is zero reset otherwise C Loaded from LSB V Reset OSCOFF CPUOFF and G
42. the sign of the low byte of the operand dst 7 is extended into dst 19 8 The bits dst 31 20 are cleared SXTX W the sign of the low byte of the operand dst 7 is extended into dst 15 8 N Set if result is negative reset otherwise Z Set if result is zero reset otherwise C Set if result is not zero reset otherwise C not Z V Reset OSCOFF CPUOFF and GIE are not affected The signed 8 bit data in EDE 7 0 is sign extended to 20 bits EDE 19 8 Bits 31 20 located in EDE 2 are cleared SXTX A amp EDE Sign extended EDE gt EDE 2 EDE Figure 4 59 Sign Extend SXTX A SXTX A Rdst 19 1615 87 6 0 SXTX A dst 31 2019 1615 87 6 0 4 152 16 Bit MSP430X CPU Extended Instructions Figure 4 60 Sign Extend SXTX W SXTXLW Rdst 19 16 15 8 7 6 0 eC SXTXLW dst 15 8 7 6 0 a E 16 Bit MSP430X CPU 4 153 Extended Instructions TSTX A TSTX W TSTX B Syntax Operation Emulation Description Status Bits Mode Bits Example Test destination address word Test destination word Test destination byte TSTX A dst TSTX dst or TST W dst TST B dst dst OFFFFFh 1 dst OFFFFh 1 dst OFFh 1 CMPX A 0 dst CMPX 0 dst CMPX B 0 dst The destination operand is compared with zero The status bits are set according to the result The destination is not affected N Set if destination is negative reset if positive Z Set if destination contains zero reset otherwise
43. to label TONI if R7 contains zero after the instruction R5 is auto incremented by 2 R7 19 16 0 SUBX W R5 R7 JZ TONI Subtract table number from R7 R5 2 R7 R5 before subtraction R7 lt gt R5 before subtraction Byte CNT is subtracted from the byte R12 points to in the full address space Address of CNT is within PC 512 K SUBX B _CNT 0 R12 Subtract CNT from R12 Note Use SUBA for the following two cases for better density and execution SUBX A Rsrc Rdst or SUBX A imm20 Rdst 4 148 16 Bit MSP430X CPU SUBCX A SUBCX W SUBCX B Syntax Operation Description Status Bits Mode Bits Example Example Example Extended Instructions Subtract source address word with carry from destination address word Subtract source word with carry from destination word Subtract source byte with carry from destination byte SUBCX A src dst SUBCX src dst or SUBCX W src dst SUBCX B src dst not src C dst dst or dst src 1 C dst The source operand is subtracted from the destination operand This is made by adding the 1 s complement of the source carry to the destination The source operand is not affected the result is written to the destination operand Both operands may be located in the full address space N Set if result is negative MSB 1 reset if positive MSB 0 Z Set if result is zero reset otherwise C Set if there is a carry from the MSB reset otherw
44. 3 1 MOVA R5 R8 PC 3 1 MOVA R9 PC N Rm 2 3 2 2 CMPA 20 R8 PC 3 3 2 2 SUBA FE000h PC x Rn Rm 4 2 MOVA 2 R5 R8 PC 4 2 MOVA 2 R6 PC EDE Rm 4 2 MOVA EDE R8 PC 4 2 MOVA EDE PC amp EDE Rm 4 2 MOVA amp EDE R8 PC 4 2 MOVA amp EDE PC 16 Bit MSP430X CPU 4 57 Instruction Set Description 4 6 Instruction Set Description The instruction map of the MSP430X shows all available instructions 000 040 080 OCO 100 140 180 1CO 200 240 280 2CO 300 340 380 3C0 anc lancelswes ana Janae sx rusupusudcau nen oaual I Extension Word For Format and Format II Instructions JNE JNZ JEQ JZ JL Oooo OE el MOV MOV B ADD ADD B ADDC ADDC B SUBC SUBC B 4 58 16 Bit MSP430X CPU 4 6 1 Extended Instruction Binary Descriptions Instruction Set Description Detailed MSP430xX instruction binary descriptions are shown below Instruction src or Instruction Group data 19 16 Identifier dst Instruction 15 12 11 8 7 4 3 0 MOVA ojojolo src 0 0 0 0 dst MOVA Rsrc Rdst 0 0 0 0 src 0 0 00 1 dst MOVA Rsrc Rdst 0 0 0 0 amp abs 19 16 0 0 1 0 dst MOVA amp abs20 Rdst amp abs 15 0 ojojolo src 0 0 1 1 dst MOVA x Rsrc Rdst x 15 0 15 bit index x 0 0 0 0 src 0 1 10 amp abs 19 16 MOVA Rsrc amp abs20 amp abs 15 0 0 0 0 0 src al a al dst MOVA Rsr
45. 4 41 MSP430 and MSP430X Instructions Format Il Single Operand Instruction Cycles and Lengths Table 4 9 lists the length and the CPU cycles for all addressing modes of the MSP430 single operand instructions Table 4 9 MSP430 Format ll Instruction Cycles and Length No of Cycles Length of Instruction Example Addressing RRA RRC Length of Mode SWPB SXT PUSH CALL Instruction Example Rn 1 3 3t 1 SWPB R5 Rn 3 3t 4 1 RRC R9 Rn 3 3t 4 1 SWPB R10 N n a 3t 4t 2 CALL LABEL X Rn 4 4t 4t 2 CALL 2 R7 EDE 4 4 4t 2 PUSH EDE amp EDE 4 4 4t 2 SXT amp EDE t The cycle count in MSP430 CPU is 4 The cycle count in MSP430 CPU is 5 Also the cycle count is 5 for X Rn addressing mode when Rn SP Jump Instructions Cycles and Lengths All jump instructions require one code word and take two CPU cycles to execute regardless of whether the jump is taken or not 4 42 16 Bit MSP430X CPU Format I Double Operand Instruction Cycles and Lengths MSP430 and MSP430X Instructions Table 4 10 lists the length and CPU cycles for all addressing modes of the MSP430 format l instructions Table 4 10 MSP430 Format Instructions Cycles and Length Addressing Mode Src Rn Rn Rn N x Rn EDE amp EDE Dst Rm PC x Rm EDE amp EDE Rm PC x Rm EDE amp EDE Rm PC x Rm EDE amp EDE Rm PC x Rm EDE amp EDE Rm PC TONI x Rm amp TONI Rm PC TONI x Rm amp TONI Rm PC TONI x Rm
46. 6 is shifted right by twelve positions RPT 12 RRUX W R6 R6 R6 12 R6 19 16 0 Figure 4 54 Rotate Right Unsigned RRUX B A Register Mode 19 8 7 0 er eee 0 19 16 15 19 0 E 4 146 16 Bit MSP430X CPU SBCX A SBCXLW SBCX B Syntax Operation Emulation Description Status Bits Mode Bits Example Extended Instructions Subtract source and borrow NOT carry from destination address word Subtract source and borrow NOT carry from destination word Subtract source and borrow NOT carry from destination byte SBCX A dst SBCX dst or SBCX W dst SBCX B dst dst OFFFFFh C gt dst dst OFFFFh C gt dst dst OFFh C gt dst SUBCX A 0 dst SUBCX 0 dst SUBCX B 0 dst The carry bit C is added to the destination operand minus one The previous contents of the destination are lost N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if there is a carry from the MSB of the result reset otherwise Set to 1 if no borrow reset if borrow V Set if an arithmetic overflow occurs reset otherwise OSCOFF CPUOFF and GIE are not affected The 8 bit counter pointed to by R13 is subtracted from a 16 bit counter pointed to by R12 SUBX B R13 0 R12 Subtract LSDs SBCX B 1 R12 Subtract carry from MSD ae Note Borrow Implementation The borrow is treated asa NOT carry Borrow Carry bit Ye
47. 78h por 7h 00778h CE SuN 0479Ch 0579Eh 1000h 0579Eh 0579Ch 0579C 0579Ch 16 Bit MSP430X CPU 4 19 CPU Registers MSP430 Instruction with Indexed Mode in Upper Memory If the CPU register Rn points to an address above the lower 64 KB memory the Rn bits 19 16 are used for the address calculation of the operand The operand may be located in memory in the range Rn 32 KB because the index X is a signed 16 bit value In this case the address of the operand can overflow or underflow into the lower 64 KB memory space See Figure 4 16 and Figure 4 17 Figure 4 16 Indexed Mode in Upper Memory Upper Memory Rn 19 16 gt 0 CPU Register Rn 16 bit signed index sign extended to 10000 20 bits OFFFF Lower 64 KB Memory address Figure 4 17 Overflow and Underflow for the Indexed Mode N E Rn 19 0 FFFFF g Rn 19 0 N 1 10000 Rn 19 0 0 FFFF Rn 19 0 Lower 64 KB MQ w 4 20 16 Bit MSP430X CPU Length Operation Comment Example CPU Registers Two or three words The sign extended 16 bit index in the next word after the instruction is added to the 20 bits of the CPU register Rn This delivers a 20 bit address which points to an address in the range 0 to FFFFFh The operand is the content of the addressed memory location Valid for source and destination The assembler calculates the register index and inserts it ADD W 8346h R5 2100h R6 This instruction a
48. Add carry decimally to destination Add carry decimally to destination DADC dst or DADC W src dst DADC B dst dst C gt dst decimally DADD 0 dst DADD B 0 dst The carry bit C is added decimally to the destination N Set if MSB is 1 Z Set if dst is 0 reset otherwise C Set if destination increments from 9999 to 0000 reset otherwise Set if destination increments from 99 to 00 reset otherwise V Undefined OSCOFF CPUOFF and GIE are not affected The four digit decimal number contained in R5 is added to an eight digit deci mal number pointed to by R8 CLRC Reset carry next instruction s start condition is defined DADD R5 0 R8 Add LSDs C DADC 2 R8 Add carry to MSD The two digit decimal number contained in R5 is added to a four digit decimal number pointed to by R8 CLRC Reset carry next instruction s start condition is defined DADD B R5 0 R8 Add LSDs C DADC 1 R8 Add carry to MSDs 4 76 16 Bit MSP430X CPU DADD W DADD B Syntax Operation Description Status Bits Mode Bits Example Example Example MSP430 Instructions Add source word and carry decimally to destination word Add source byte and carry decimally to destination byte DADD src dst or DADD W src dst DADD B src dst src dst C dst decimally The source operand and the destination operand are treated as two B or four W binary coded decimals BCD with positive signs The sourc
49. B R5 R6 Add byte to R6 R5 1 R6 000xxh JNC TONI Jump if no carry Carry occurred 16 Bit MSP430X CPU 4 63 MSP430 Instructions ADDC W ADDC B Syntax Operation Description Status Bits Mode Bits Example Example Example Add source word and carry to destination word Add source byte and carry to destination byte ADDC ADDC B src dst or ADDC W src dst src dst src dst C gt dst The source operand and the carry bit C are added to the destination operand The previous content of the destination is lost Set if result is negative MSB 1 reset if positive MSB 0 Set if result is zero reset otherwise Set if there is a carry from the MSB of the result reset otherwise Set if the result of two positive operands is negative or if the result of two negative numbers is positive reset otherwise OSCOFF CPUOFF and GIE are not affected Constant value 15 and the carry of the previous instruction are added to the 16 bit counter CNTR located in lower 64 K ADDC W 15 amp CNTR Add 15 C to 16 bit CNTR A table word pointed to by R5 20 bit address and the carry C are added to R6 The jump to label TONI is performed on a carry R6 19 16 0 ADDC W R5 R6 JC TONI Add table word C to R6 Jump if carry No carry A table byte pointed to by R5 20 bit address and the carry bit C are added to R6 The jump to label TONI is performed if no carry occurs The table pointer is a
50. CPU 4 163 Address Instructions DECDA Syntax Operation Emulation Description Status Bits Mode Bits Example Double decrement 20 bit destination register DECDA Rdst Rdst 2 gt Rdst SUBA 2 Rdst The destination register is decremented by two The original contents are lost N Set if result is negative reset if positive Z Set if Rdst contained 2 reset otherwise C Reset if Rdst contained 0 or 1 set otherwise V Set if an arithmetic overflow occurs otherwise reset OSCOFF CPUOFF and GIE are not affected The 20 bit value in R5 is decremented by 2 DECDA R5 Decrement R5 by two 4 164 16 Bit MSP430X CPU INCDA Syntax Operation Emulation Example Status Bits Mode Bits Example Address Instructions Double increment 20 bit destination register INCDA Rdst dst 2 gt dst ADDA 2 Rdst The destination register is incremented by two The original contents are lost N Set if result is negative reset if positive Z Set if Rdst contained OFFFFEh reset otherwise Set if Rdst contained OFFFEh reset otherwise Set if Rdst contained OFEh reset otherwise C Set if Rdst contained OFFFFEh or OFFFFFh reset otherwise Set if Rdst contained OFFFEh or OFFFFh reset otherwise Set if Rdst contained OFEh or OFFh reset otherwise V Set if Rdst contained O7FFFEh or 07FFFFh reset otherwise Set if Rdst contained O7FFEh or 07FFFh reset otherwise Set if Rdst contained 07Eh or 07Fh reset otherwise
51. EC dst or DEC W dst DEC B dst dst 1 gt dst SUB 1 dst SUB B 1 dst The destination operand is decremented by one The original contents are lost Set if result is negative reset if positive Set if dst contained 1 reset otherwise Reset if dst contained 0 set otherwise Set if an arithmetic overflow occurs otherwise reset Set if initial value of destination was 08000h otherwise reset Set if initial value of destination was 080h otherwise reset OSCOFF CPUOFF and GIE are not affected R10 is decremented by 1 DEC R10 Decrement R10 Move a block of 255 bytes from memory location starting with EDE to memory location starting with TONI Tables should not overlap start of destination address TONI must not be within the range EDE to EDE OFEh L 1 MOV EDE R6 MOV 255 R10 MOV B R6 TONI EDE 1 R6 DEC R10 JNZ L 1 Do not transfer tables using the routine above with the overlap shown in Figure 4 36 Figure 4 36 Decrement Overlap EDE tc TONI EDE 254 TONI 254 4 78 16 Bit MSP430X CPU DECD W DECD B Syntax Operation Emulation Emulation Description Status Bits Mode Bits Example MSP430 Instructions Double decrement destination Double decrement destination DECD dst or DECD W dst DECD B dst dst 2 gt dst SUB 2 dst SUB B 2 dst The destination operand is decremented by two The original contents are lost N Set if result is negative rese
52. Example Move source address word to destination address word Move source word to destination word Move source byte to destination byte MOVX A src dst MOVX src dst or MOVX W src dst MOVX B src dst src dst The source operand is copied to the destination The source operand is not affected Both operands may be located in the full address space N Not affected Z Not affected C Not affected V Not affected OSCOFF CPUOFF and GIE are not affected Move a 20 bit constant 18000h to absolute address word EDE MOVX A 018000h amp 8EDE Move 18000h to EDE The contents of table EDE word data 20 bit addresses are copied to table TOM The length of the table is 030h words MOVA EDE R10 Prepare pointer 20 bit address MOVX W R10 TOM EDE 2 R10 R10 points to both tables R10 2 CMPA EDE 60h R10 End of table reached JLO Loop Not yet Copy completed The contents of table EDE byte data 20 bit addresses are copied to table TOM The length of the table is 020h bytes MOVA EDE R10 Prepare pointer 20 bit MOV 20h R9 Prepare counter Loop MOVX B R10 TOM EDE 1 R10 R10 points to both tables R10 1 DEC R9 Decrement counter JNZ Loop Not yet done Copy completed 4 130 16 Bit MSP430X CPU Extended Instructions Ten of the 28 possible addressing combinations of the MOVX A instruction can use the MOVA instruction This saves two bytes and code cycles Examples for the addressing combinations
53. F CPUOFF and GIE are not affected Call a subroutine SUBR from anywhere in the 20 bit address space and return to the address after the CALLA CALLA SUBR Call subroutine starting at SUBR nee Return by RETA to here SUBR PUSHM A 2 R14 Save R14 and R13 20 bit data ik Subroutine code POPM A 2 R14 Restore R13 and R14 20 bit data RETA Return to full address space 4 168 16 Bit MSP430X CPU TSTA Syntax Operation Emulation Description Status Bits Mode Bits Example Address Instructions Test 20 bit destination register TSTA Rdst dst OFFFFFh 1 dst OFFFFh 1 dst OFFh 1 CMPA 0 Rdst The destination register is compared with zero The status bits are set according to the result The destination register is not affected N Set if destination register is negative reset if positive Z Set if destination register contains zero reset otherwise C Set V Reset OSCOFF CPUOFF and GIE are not affected The 20 bit value in R7 is tested If it is negative continue at R7NEG if it is positive but not zero continue at R7POS TSTA R7 Test R7 JN R7NEG R7 is negative JZ R7ZERO R7 is zero R7POS i R7 is positive but not zero R7NEG sta R7 is negative R7ZERO _ R7 is zero 16 Bit MSP430X CPU 4 169 Address Instructions SUBA Syntax Operation Description Status Bits Mode Bits Example Subtract 20 bit source from 20 bit destination register
54. IE are not affected 16 Bit MSP430X CPU 4 143 Extended Instructions Example The 20 bit operand at address EDE is shifted right by one position The MSB is loaded with 1 SETC Prepare carry for MSB RRCX A EDE EDE EDE 1 80000h Example The word in R6 is shifted right by twelve positions RPT 12 RRCX WwW R6 R6 R6 12 R6 19 16 0 Figure 4 51 Rotate Right Through Carry RRCX B A Register Mode 19 8 7 0 er eee 19 16 15 19 0 Figure 4 52 Rotate Right Through Carry RRCX B A Non Register Mode 7 0 15 0 e E 31 20 19 0 Ce 4 144 16 Bit MSP430X CPU RRUM A RRUM W Syntax Operation Description Status Bits Mode Bits Example Example Extended Instructions Rotate Right Unsigned the 20 bit CPU register content Rotate Right Unsigned the 16 bit CPU register content RRUM A n Rdst i lt n lt 4 RRUM W n Rdst or RRUM n Rdst 1 lt n lt 4 0 MSB MSB 1 gt LSB 1 LSB gt C The destination operand is shifted right by one two three or four bit positions as shown in Figure 4 53 Zero is shifted into the MSB the LSB is shifted into the carry bit RRUM works like an unsigned division by 2 4 8 or 16 The word instruction RRUM W clears the bits Rdst 19 16 Note This instruction does not use the extension word N Set if result is negative A Rdst 19 1 reset if Rdst 19 O W Rdst 15 1 r
55. R7 20 bit counter is decremented If its content is not zero the program continues at Label4 Program in full memory range SUBA 1 R7 Decrement R7 JNZ Label4 Zero not reached Go to Label4 Yes R7 0 Continue here 4 92 16 Bit MSP430X CPU MOVI W MOV B Syntax Operation Description Status Bits Mode Bits Example Example Loop Example Loop MSP430 Instructions Move source word to destination word Move source byte to destination byte MOV src dst or MOV Wsrc dst MOV B src dst src dst The source operand is copied to the destination The source operand is not affected N Not affected Z Not affected C Not affected V Not affected OSCOFF CPUOFF and GIE are not affected Move a 16 bit constant 1800h to absolute address word EDE lower 64 K MOV 01800h amp EDE Move 1800h to EDE The contents of table EDE word data 16 bit addresses are copied to table TOM The length of the tables is 030h words Both tables reside in the lower 64K MOV EDE R10 Prepare pointer 16 bit address MOV R10 TOM EDE 2 R10 R10 points to both tables R10 2 CMP EDE 60h R10 End of table reached JLO Loop Not yet Copy completed The contents of table EDE byte data 16 bit addresses are copied to table TOM The length of the tables is 020h bytes Both tables may reside in full memory range but must be within R10 32 K MOVA EDE R10 Prepare pointer 20 bit MOV 20h R9 Prepar
56. SP430X CPU 4 159 Address Instructions CALLA Syntax Operation Description Status Bits Mode Bits Examples Call a Subroutine CALLA dst dst tmp20 bit dst is evaluated and stored SP 2 SP PC 19 16 SP_ updated PC with return address to TOS MSBs SP 2 gt SP PC 15 0 SP updated PC to TOS LSBs tmp gt PC saved 20 bit dst to PC A subroutine call is made to a 20 bit address anywhere in the full address space All seven source addressing modes can be used The call instruction is an address word instruction If the destination address is contained in a memory location X it is contained in two ascending words X LSBs and X 2 MSBs Two words on the stack are needed for the return address The return is made with the instruction RETA N Not affected Z Not affected C Not affected V Not affected OSCOFF CPUOFF and GIE are not affected Examples for all addressing modes are given Immediate Mode Call a subroutine at label EXEC or call directly an address CALLA EXEC Start address EXEC CALLA 01AA04h Start address 01AA04h Symbolic Mode Call a subroutine at the 20 bit address contained in address es EXEC LSBs and EXEC 2 MSBs EXEC is located at the address PC X where X is within 32 K Indirect addressing CALLA EXEC Start address at EXEC z16 PC Absolute Mode Call a subroutine at the 20 bit address contained in absolute addresses EXEC LSBs and EXEC 2 MSBs I
57. TONI Before After Address Address Space Space 2103Ah 2103Ah PC 21038h 21038h 21036h 21036h 21034h 21034h 3456h src 0077Ah 0077Ah 2345h_ dst 579Bh Sum 00778h 00778h 4 34 16 Bit MSP430X CPU CPU Registers MSP430X Instructions with Immediate Mode If an MSP430X instruction is used with immediate addressing mode the constant is a 20 bit value The 4 MSBs of the constant are stored in the extension word and the 16 LSBs of the constant are stored in the word following the instruction Length Three or four words One word less if a constant of the constant generator can be used for the immediate operand Operation The 20 bit immediate source operand is used together with the 20 bit destination operand Comment Valid only for the source operand Example ADDX A 23456h amp TONI This instruction adds the 20 bit immediate operand 23456h to the data in the destination address TONI Source 20 bit immediate value 23456h Destination Two words beginning with address TONI Before After Address Address Space Space 2103Ah 21038h 21036h 21034h 21032h 2103Ah 21038h 21036h 21034h 21032h PC 23456h src 7777Ah 7777Ah 12345h__ dst 3579Bh Sum 77778h 77778h 16 Bit MSP430X CPU 4 35 MSP430 and MSP430X Instructions 4 5 MSP430 and MSP430X Instructions MSP430 instructions are the 27 implemented instructions of the MSP430 CPU These instructions are used throughout the 1 MB memory range unles
58. The 20 bit value in R10 is cleared CLRA R10 0 gt R10 4 162 16 Bit MSP430X CPU CMPA Syntax Operation Description Status Bits Mode Bits Example Example Address Instructions Compare the 20 bit source with a 20 bit destination register CMPA Rsrc Rdst CMPA imm20 Rdst not src 1 Rdst or Rdst src The 20 bit source operand is subtracted from the 20 bit destination CPU register This is made by adding the 1 s complement of the source 1 to the destination register The result affects only the status bits Set if result is negative src gt dst reset if positive src lt dst Set if result is zero src dst reset otherwise src dst Set if there is a carry from the MSB reset otherwise Set if the subtraction of a negative source operand from a positive destination operand delivers a negative result or if the subtraction of a positive source operand from a negative destination operand delivers a positive result reset otherwise no overflow OSCOFF CPUOFF and GIE are not affected A 20 bit immediate operand and R6 are compared If they are equal the program continues at label EQUAL CMPA 12345h R6 Compare R6 with 12345h JEQ EQUAL R5 12345h Not equal The 20 bit values in R5 and R6 are compared If R5 is greater than signed or equal to R6 the program continues at label GRE CMPA R6 R5 Compare R6 with R5 R5 R6 JGE GRE R5 gt R6 R5 lt R6 16 Bit MSP430X
59. V Not affected OSCOFF CPUOFF and GIE are not affected Emulation of the decimal subtraction Subtract R5 from R6 decimally Assume that R5 03987h and R6 04137h ADD 06666h R5 Move content R5 from 0 9 to 6 OFh R5 03987h 06666h 09FEDh INV R5 Invert this result back to 0 9 R5 NOT R5 06012h SETC Prepare carry 1 DADD R5 R6 Emulate subtraction by addition of 010000h R5 1 R6 R6 R5 1 R6 0150h 4 104 16 Bit MSP430X CPU MSP430 Instructions SETN Set negative bit Syntax SETN Operation 1 gt N Emulation BIS 4 SR Description The negative bit N is set Status Bits N Set Z Not affected C Not affected V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected 16 Bit MSP430X CPU 4 105 MSP430 Instructions SETZ Syntax Operation Emulation Description Status Bits Mode Bits Set zero bit SETZ 1 gt Z BIS 2 SR The zero bit Z is set N Not affected Z Set C Not affected V Not affected OSCOFF CPUOFF and GIE are not affected 4 106 16 Bit MSP430X CPU SUB W SUB B Syntax Operation Description Status Bits Mode Bits Example Example Example MSP430 Instructions Subtract source word from destination word Subtract source byte from destination byte SUB src dst or SUB W src dst SUB B src dst not src 1 dst dst or dst src dst The source operand is subtracted from the destination operand This is
60. X B dst Operation MSB MSB gt MSB 1 LSB 1 gt LSB gt C Description Register Mode for the destination the destination operand is shifted right by one bit position as shown in Figure 4 48 The MSB retains its value sign The word instruction RRAX W clears the bits Rdst 19 16 the byte instruction RRAX B clears the bits Rdst 19 8 The MSB retains its value sign the LSB is shifted into the carry bit RRAX here operates equal to a signed division by 2 All other modes for the destination the destination operand is shifted right arithmetically by one bit position as shown in Figure 4 49 The MSB retains its value sign the LSB is shifted into the carry bit RRAX here operates equal to a signed division by 2 All addressing modes with the exception of the Immediate Mode are possible in the full memory Status Bits N Set if result is negative A dst 19 1 reset if dst 19 O W dst 15 1 reset if dst 15 0 B dst 7 1 reset if dst 7 0 Z Set if result is zero reset otherwise C Loaded from LSB V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected 4 140 16 Bit MSP430X CPU Extended Instructions Example The signed 20 bit number in R5 is shifted arithmetically right four positions RPT 4 RRAX A R5 R5 16 gt R5 Example The signed 8 bit value in EDE is multiplied by 0 5 RRAX B amp EDE EDE 2 gt EDE Figure 4 48 Rotate Right Arithmetically RRAX B A Register Mode 7 19 8 LSB
61. address word Rotate left arithmetically word Rotate left arithmetically byte RLAX B dst RLAX dst or RLAX W dst RLAX B dst C lt MSB lt MSB 1 LSB 1 lt LSB lt 0 ADDX A dst dst ADDX dst dst ADDX B dst dst The destination operand is shifted left one position as shown in Figure 4 45 The MSB is shifted into the carry bit C and the LSB is filled with 0 The RLAX instruction acts as a signed multiplication by 2 Figure 4 45 Destination Operand Arithmetic Shift Left Status Bits Mode Bits Example MSB 0 A Moa Set if result is negative reset if positive Set if result is zero reset otherwise Loaded from the MSB Set if an arithmetic overflow occurs the initial value is 040000h lt dst lt OCOOOOh reset otherwise Set if an arithmetic overflow occurs the initial value is 04000h lt dst lt OCOOOh reset otherwise Set if an arithmetic overflow occurs the initial value is 040h lt dst lt OCOh reset otherwise OSCOFF CPUOFF and GIE are not affected The 20 bit value in R7 is multiplied by 2 RLAX A R7 Shift left R7 20 bit 16 Bit MSP430X CPU 4 137 Extended Instructions RLCX A RLCX W RLCX B Syntax Operation Emulation Description Rotate left through carry address word Rotate left through carry word Rotate left through carry byte RLCX A dst RLCX dst or RLCX W dst RLCX B dst C lt MSB lt MSB 1 LSB 1 lt LSB lt C ADDCX A dst dst ADDCX
62. arry from destination word Subtract source byte with carry from destination byte SUBC src dst or SUBC W src dst SUBC B src dst not src C dst dst or dst src 1 C dst The source operand is subtracted from the destination operand This is done by adding the 1 s complement of the source carry to the destination The source operand is not affected the result is written to the destination operand Used for 32 48 and 64 bit operands Set if result is negative MSB 1 reset if positive MSB 0 Set if result is zero reset otherwise Set if there is a carry from the MSB reset otherwise Set if the subtraction of a negative source operand from a positive des tination operand delivers a negative result or if the subtraction of a posi tive source operand from a negative destination operand delivers a positive result reset otherwise no overflow OSCOFF CPUOFF and GIE are not affected A 16 bit constant 7654h is subtracted from R5 with the carry from the previous instruction R5 19 16 0 SUBC W 7654h R5 Subtract 7654h C from R5 A 48 bit number 3 words pointed to by R5 20 bit address is subtracted from a 48 bit counter in RAM pointed to by R7 R5 points to the next 48 bit number afterwards The address R7 points to is in full memory range SUB R5 0 R7 Subtract LSBs R5 2 SUBC R5 2 R7 Subtract MIDs with C R5 2 SUBC R5 4 R7 Subtract MSBs with C R5 2 Byte CNT is subtracted from the b
63. ating modes Section 2 Interrupts The interrupt vectors contain 16 bit addresses that point into the lower 64 KB memory This means all interrupt handlers must start in the lower 64 KB memory even in MSP430X devices During an interrupt the program counter and the status register are pushed onto the stack as shown in Figure 4 2 The MSP430X architecture efficiently stores the complete 20 bit PC value by automatically appending the PC bits 19 16 to the stored SR value on the stack When the RETT instruction is executed the full 20 bit PC is restored making return from interrupt to any address in the memory range possible Figure 4 2 Program Counter Storage on the Stack for Interrupts PC 15 0 SP PC 19 16 SR 11 0 4 4 16 Bit MSP430X CPU CPU Registers 4 3 CPU Registers The CPU incorporates sixteen registers RO to R15 Registers RO R1 R2 and R3 have dedicated functions R4 to R15 are working registers for general use 4 3 1 The Program Counter PC The 20 bit program counter PC RO points to the next instruction to be executed Each instruction uses an even number of bytes two four six or eight bytes and the PC is incremented accordingly Instruction accesses are performed on word boundaries and the PC is aligned to even addresses Figure 4 3 shows the program counter Figure 4 3 Program Counter PC 19 16 15 1 0 Program Counter Bits 19 to 1 g The PC can be addressed with all instructions and addressing modes
64. byte of R7 that are different from the bits in byte EDE R7 19 8 0 The address of EDE is within PC 32 K XOR B EDE R7 INV B R7 Set different bits to 1 in R7 Invert low byte of R7 high byte is Oh 4 112 16 Bit MSP430X CPU Extended Instructions 4 6 3 Extended Instructions The extended MSP430X instructions give the MSP430X CPU full access to its 20 bit address space Some MSP430X instructions require an additional word of op code called the extension word All addresses indexes and immediate numbers have 20 bit values when preceded by the extension word The MSP430X extended instructions are listed and described in the following pages For MSP430xX instructions that do not require the extension word it is noted in the instruction description 16 Bit MSP430X CPU 4 113 Extended Instructions ADCX A ADCX W ADCX B Syntax Operation Emulation Description Status Bits Mode Bits Example 4 114 Add carry to destination address word Add carry to destination word Add carry to destination byte ADCX A dst ADCX dst or ADCX B dst ADCX W_ dst dst C gt dst ADDCX A 0 dst ADDCX 0 dst ADDCX B 0 dst The carry bit C is added to the destination operand The previous contents of the destination are lost N Set if result is negative MSB 1 reset if positive MSB 0 Z Set if result is zero reset otherwise C Set if there is a carry from the MSB of the result reset otherwise
65. c X Rdst x 15 0 15 bit index x 0 0 0 0 imm 19 16 1 0 0 0 dst MOVA imm20 Rdst imm 15 0 CMPA 0 0 0 0 imm 19 16 1 0 0 1 dst CMPA imm20 Rdst imm 15 0 ADDA 0 0 0 0 imm 19 16 1 0 10 dst ADDA imm20 Rdst imm 15 0 SUBA 0 00 O imm 19 16 uv a fa dst SUBA imm20 Radst imm 15 0 MOVA 0 0 0 0 src dd lO dst MOVA Rsrc Rdst CMPA 0 0 0 0 src dpi 4 dst CMPA Rsrc Rdst ADDA 0 0 0 0 src i ad a dst ADDA Rsrc Rdst SUBA 0 0 0 0 src tiaiada dst SUBA Rsrc Rdst Instruction Bit Inst Instruction Group loc ID Identifier dst Instruction 15 12 1110 9 8 7 4 3 0 RRCM A 010 00 n 1 0 0 0 1 0 0 dst RRCM A n Rdst RRAM A 00 0 10 n 1 0 1 0 1 0 0 dst RRAM A n Rdst RLAM A 0 0 0 0 n 1 1110 01 00 dst RLAM A n Rdst RRUM A 0 0 0 0 n 1 1111 01 00 dst RRUM A n Rdst RRCM W 0 0 0 0 n 1 0 0 0 1 0 1 dst RRCM W n Rast RRAM W 0 0 0 0 n 1 0 1 0 1 0 1 dst RRAM W n Rdst RLAM W 0 0 0 0 n 1 1 0 0 1 0 1 dst RLAM W n Rdst RRUM W 0 0 0 0 n 1 1 1 0 1 0 1 dst RRUM W n Rdst 16 Bit MSP430X CPU 4 59 Instruction Set Description 4 60 Instruction Identifier dst Instruction 15 12 11 8 765 4 3 0 RETI 0 0 0 1 0 1 1 0 0 0 0 0j 0j 0 0 CALLA 0 0 0 1 0 1 1 0 1 0 0 dst CALLA Rast 0 0 0 1 0 1 1 0 1 0 1 dst CALLA x Radst x 15 0 0 0 0 1 0 1 1 0 1 110 dst CALLA Rdst 0 0 0 1 0 1 1 0 1
66. counter This ensures that the counter is not modified during the move by any interrupt DINT All interrupt events using the GIE bit are disabled NOP MOV COUNTHI R5 Copy counter MOV COUNTLO R6 EINT All interrupt events using the GIE bit are enabled __ ___ ee Note Disable Interrupt If any code sequence needs to be protected from interruption the DINT should be executed at least one instruction before the beginning of the uninterruptible sequence or should be followed by a NOP instruction ee 4 80 16 Bit MSP430X CPU EINT Syntax Operation Emulation Description Status Bits Mode Bits Example MSP430 Instructions Enable general interrupts EINT 1 GIE or 0008h OR SR gt SR src OR dst gt dst BIS 8 SR All interrupts are enabled The constant 08h and the status register SR are logically ORed The result is placed into the SR Status bits are not affected GIE is set OSCOFF and CPUOFF are not affected The general interrupt enable GIE bit in the status register is set Interrupt routine of ports P1 2 to P1 7 P1IN is the address of the register where all port bits are read P1IFG is the address of the register where all interrupt events are latched MaskOK PUSH B amp P1IN BIC B SP amp P1IFG Reset only accepted flags EINT Preset port 1 interrupt flags stored on stack other interrupts are allowed BIT Mask SP JEQ MaskOK Flags are
67. curs otherwise reset OSCOFF CPUOFF and GIE are not affected RAM address word TONI is decremented by 1 DECX A TONI Decrement TONI 16 Bit MSP430X CPU 4 125 Extended Instructions DECDX A DECDX W DECDX B Syntax Operation Emulation Description Status Bits Mode Bits Example 4 126 Double decrement destination address word Double decrement destination word Double decrement destination byte DECDX A dst DECDX dst DECDX B dst dst 2 gt dst SUBX A 2 dst SUBX 2 dst SUBX B 2 dst or DECDX W dst The destination operand is decremented by two The original contents are lost N Setif result is negative reset if positive Z Setif dst contained 2 reset otherwise C Reset if dst contained 0 or 1 set otherwise V Set if an arithmetic overflow occurs otherwise reset OSCOFF CPUOFF and GIE are not affected RAM address word TONI is decremented by 2 DECDX A TONI 16 Bit MSP430X CPU Decrement TONI by two INCX A INCX W INCX B Syntax Operation Emulation Description Status Bits Mode Bits Example Extended Instructions Increment destination address word Increment destination word Increment destination byte INCX A dst INCX dst INCX B dst dst 1 gt dst ADDX A 1 dst ADDX 1 dst ADDX B_ 1 dst or INCX W dst The destination operand is incremented by one The original contents are lost N Set if result is negative re
68. d the carry of the previous instruction are added to the 20 bit counter CNTR located in two words ADDCX A A table word pointed to by R5 20 bit address and the carry C are added to R6 The jump to label TONI is performed on a carry 15 amp 8CNTR Add 15 C to 20 bit CNTR ADDCX W R5 R6 JC TONI Add table word C to R6 Jump if carry No carry A table byte pointed to by R5 20 bit address and the carry bit C are added to R6 The jump to label TONI is performed if no carry occurs The table pointer is auto incremented by 1 ADDCX B R5 R6 Add table byte C to R6 R5 1 JNC TONI Jump if no carry Carry occurred 4 116 16 Bit MSP430X CPU ANDX A ANDX W ANDX B Syntax Operation Description Status Bits Mode Bits Example Example Extended Instructions Logical AND of source address word with destination address word Logical AND of source word with destination word Logical AND of source byte with destination byte ANDX A src dst ANDX src dst or ANDX W src dst ANDX B _ src dst src and dst gt dst The source operand and the destination operand are logically ANDed The result is placed into the destination The source operand is not affected Both operands may be located in the full address space N Set if result is negative MSB 1 reset if positive MSB 0 Z Set if result is zero reset otherwise C Set if the result is not zero reset otherwise C not Z V Reset
69. ddressing mode the absolute address is a 16 bit value and therefore points to an address in the lower 64 KB of the memory range The address is calculated as an index from 0 and is stored in the word following the instruction The RAM and the peripheral registers can be accessed this way and existing MSP430 software is usable without modifications Length Two or three words Operation The operand is the content of the addressed memory location Comment Valid for source and destination The assembler calculates the index from 0 and inserts it Example ADD W amp EDE amp TONI This instruction adds the 16 bit data contained in the absolute source and destination addresses and places the result into the destination Source Word at address EDE Destination Word at address TONI Before Address Space After Address Space 2103Ah 2103Ah PC 21038h 21038h 21036h 21036h 21034h 21034h 5432h src 0777Ah 0777Ah 2345h__ dst 7777h Sum 07778h 07778h 0579Eh 0579Ch 0579Eh 0579Ch 16 Bit MSP430X CPU CPU Registers MSP430X Instruction with Absolute Mode If an MSP430X instruction is used with Absolute addressing mode the absolute address is a 20 bit value and therefore points to any address in the memory range The address value is calculated as an index from 0 The four MSBs of the index are contained in the extension word and the 16 LSBs are contained in the word following the instruction Length Three or four wor
70. dds the 16 bit data contained in the source and the destination addresses and places the 16 bit result into the destination Source and destination operand can be located in the entire address range Source Destination The word pointed to by R5 8346h The negative index 8346h is sign extended which results in address 23456h F8346h 1B79Ch The word pointed to by R6 2100h results in address 15678h 2100h 17778h Figure 4 18 Example for the Indexed Mode Before After Address Register Address Register Space Space 1103Ah R5 23456h 1103Ah PC R5 23456h 11038h R6 15678h 11038h R6 15678h 11036h 11036h 11034h 11034h 15678h 05432h src 1777Ah 02100h 1777Ah 02345h__ dst 47778h 17778h 17778h 07777h Sum 23456h 1B79Eh F8346h 1B79Eh 1B79Ch 1B79Ch 1B79Ch 16 Bit MSP430X CPU 4 21 CPU Registers MSP430X Instruction with Indexed Mode 4 22 When using an MSP480xX instruction with Indexed mode the operand can be located anywhere in the range of Rn 19 bits Length Operation Comment Example Three or four words The operand address is the sum of the 20 bit CPU register content and the 20 bit index The four MSBs of the index are contained in the extension word the 16 LSBs are contained in the word following the instruction The CPU register is not modified Valid for source and destination The assembler calculates the register index and inserts it ADDX A 12346h R5 32100h R6 This in
71. ds Operation The operand is the content of the addressed memory location Comment Valid for source and destination The assembler calculates the index from 0 and inserts it Example ADDX A amp EDE amp TONI This instruction adds the 20 bit data contained in the absolute source and destination addresses and places the result into the destination Source Two words beginning with address EDE Destination Two words beginning with address TONI Before After Address Address Space Space 2103Ah 2103Ah PC 21038h 21038h 21036h 21036h 21034h 21034h 21032h 21032h 65432h src 7777Ah 7777Ah 12345h__ dst 77777h Sum 77778h 77778h 3579Eh 3579Ch 3579Eh 3579Ch 16 Bit MSP430X CPU 4 31 CPU Registers 4 4 5 Indirect Register Mode The Indirect Register mode uses the contents of the CPU register Rsrc as the source operand The Indirect Register mode always uses a 20 bit address Length One two or three words Operation The operand is the content the addressed memory location The source register Rsrc is not modified Comment Valid only for the source operand The substitute for the destination operand is 0 Rdst Example ADDX W R5 2100h R6 This instruction adds the two 16 bit operands contained in the source and the destination addresses and places the result into the destination Source Word pointed to by R5 R5 contains address 3 579Ch for this example Destination Word pointed to by R6 2100h which
72. ds transferred 4 166 16 Bit MSP430X CPU Address Instructions Copy 20 bit value R9 points to 20 bit address to R8 R9 is incremented by four afterwards Source operand in addresses R9 LSBs and RQ 2 MSBs MOVA R9 R8 R9 gt R8 R9 4 2 words transferred Copy 20 bit value in R8 to destination addressed by R9 100h Destination operand in addresses R9 100h LSBs and R9 102h MSBs MOVA R8 100h R9 Index 32 K 2 words transferred Move 20 bit value in R13 to 20 bit absolute addresses EDE LSBs and EDE 2 MSBs MOVA R13 amp EDE R13 gt EDE 2 words transferred Move 20 bit value in R13 to 20 bit addresses EDE LSBs and EDE 2 MSBs PC index 32 K MOVA R13 EDE R13 gt EDE 2 words transferred 16 Bit MSP430X CPU 4 167 Address Instructions RETA Syntax Operation Emulation Description Status Bits Mode Bits Example Return from subroutine RETA SP PC 15 0 LSBs 15 0 of saved PC to PC 15 0 SP 2 gt SP SP PC 19 16 MSBs 19 16 of saved PC to PC 19 16 SP 2 gt SP MOVA SP PC The 20 bit return address information pushed onto the stack by a CALLA instruction is restored to the program counter PC The program continues at the address following the subroutine call The status register bits SR 11 0 are not affected This allows the transfer of information with these bits N Not affected Z Not affected C Not affected V Not affected OSCOF
73. dst dst ADDCX B dst dst The destination operand is shifted left one position as shown in Figure 4 46 The carry bit C is shifted into the LSB and the MSB is shifted into the carry bit C Figure 4 46 Destination Operand Carry Left Shift MSB 0 Status Bits Mode Bits Example Example Set if result is negative reset if positive Set if result is zero reset otherwise Loaded from the MSB Set if an arithmetic overflow occurs the initial value is 040000h lt dst lt OCOOOOh reset otherwise Set if an arithmetic overflow occurs the initial value is 04000h lt dst lt OCOOOh reset otherwise Set if an arithmetic overflow occurs the initial value is 040h lt dst lt OCOh reset otherwise OSCOFF CPUOFF and GIE are not affected The 20 bit value in R5 is shifted left one position RLCX A R5 R5 x 2 C gt R5 The RAM byte LEO is shifted left one position PC is pointing to upper memory RLCX B LEO RAM LEO x 2 C gt RAM LEO 4 138 16 Bit MSP430X CPU RRAM A RRAM W Syntax Operation Description Status Bits Mode Bits Example Example Extended Instructions Rotate Right Arithmetically the 20 bit CPU register content Rotate Right Arithmetically the 16 bit CPU register content RRAM A n Rdst i lt n lt 4 RRAM W n Rdst or RRAM n Rdst 1 lt n lt 4 MSB MSB MSB 1 LSB 1 LSB gt C The destination operand is shifted right arithmetically by one two three or
74. e 16 bit CPU register values on the stack The stack pointer is decremented by two for each register stored on the stack PUSHM A The n CPU registers starting with Rdst backwards are stored on the stack The stack pointer is decremented by n x 4 after the operation The data Rn 19 0 of the pushed CPU registers is not affected PUSHM W The n registers starting with Rdst backwards are stored on the stack The stack pointer is decremented by n x 2 after the operation The data Rn 19 0 of the pushed CPU registers is not affected Note This instruction does not use the extension word Not affected OSCOFF CPUOFF and GIE are not affected Save the five 20 bit registers R9 R10 R11 R12 R13 on the stack PUSHM A 5 R13 Save R13 R12 R11 R10 R9 Save the five 16 bit registers R9 R10 R11 R12 R13 on the stack PUSHM W 5 R13 Save R13 R12 R11 R10 R9 16 Bit MSP430X CPU 4 133 Extended Instructions POPX A POPX W POPX B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Restore single address word from the stack Restore single word from the stack Restore single byte from the stack POPX A dst POPX dst or POPX W _ dst POPX B dst Restore the 8 16 20 bit value from the stack to the destination 20 bit addresses are possible The stack pointer SP is incremented by two byte and word operands and by four address word operand MOVX B A SP dst T
75. e counter MOV B R10 TOM EDE 1 R10 R10 points to both tables R10 1 DEC R9 Decrement counter JNZ Loop Not yet done Copy completed 16 Bit MSP430X CPU 4 93 MSP430 Instructions NOP No operation Syntax NOP Operation None Emulation MOV 0 R3 Description No operation is performed The instruction may be used for the elimination of instructions during the software check or for defined waiting times Status Bits Status bits are not affected 4 94 16 Bit MSP430X CPU POP W POP B Syntax Operation Emulation Emulation Description Status Bits Example Example Example Example MSP430 Instructions Pop word from stack to destination Pop byte from stack to destination POP dst POP B dst SP gt temp SP 2 gt SP temp gt dst MOV SP dst or MOV W SP dst MOV B SP dst The stack location pointed to by the stack pointer TOS is moved to the destination The stack pointer is incremented by two afterwards Status bits are not affected The contents of R7 and the status register are restored from the stack POP R7 POP SR Restore R7 Restore status register The contents of RAM byte LEO is restored from the stack POP B LEO The low byte of the stack is moved to LEO The contents of R7 is restored from the stack POP B R7 The low byte of the stack is moved to R7 the high byte of R7 is 00h The contents of the memory pointed to by R7 and the status re
76. e operand and the carry bit C are added decimally to the destination operand The source operand is not affected The previous content of the destination is lost The result is not defined for non BCD numbers N Set if MSB of result is 1 word gt 7999h byte gt 79h reset if MSB is 0 Z Set if result is zero reset otherwise C Set if the BCD result is too large word gt 9999h byte gt 99h reset otherwise V Undefined OSCOFF CPUOFF and GIE are not affected Decimal 10 is added to the 16 bit BCD counter DECCNTR DADD 10h amp DECCNTR Add 10 to 4 digit BCD counter The eight digit BCD number contained in 16 bit RAM addresses BCD and BCD 2 is added decimally to an eight digit BCD number contained in R4 and R5 BCD 2 and R5 contain the MSDs The carry C is added and cleared CLRC Clear carry DADD W amp BCD R4 Add LSDs R4 19 16 0 DADD W amp BCD 2 R5 Add MSDs with carry R5 19 16 0 JC OVERFLOW Result gt 9999 9999 go to error routine Result ok The two digit BCD number contained in word BCD 16 bit address is added decimally to a two digit BCD number contained in R4 The carry C is added also R4 19 8 0 CLRC Clear carry DADD B amp BCD R4 Add BCD to R4 decimally R4 0 00ddh 16 Bit MSP430X CPU 4 77 MSP430 Instructions DEC W DEC B Syntax Operation Emulation Emulation Description Status Bits Mode Bits Example Decrement destination Decrement destination D
77. els They are only labels They have no special meaning b 16 Bit MSP430X CPU 4 15 CPU Registers 4 4 1 Register Mode Operation The operand is the 8 16 or 20 bit content of the used CPU register Length One two or three words Comment Valid for source and destination Byte operation Byte operation reads only the 8 LSBs of the source register Rsrc and writes the result to the 8 LSBs of the destination register Rdst The bits Rdst 19 8 are cleared The register Rsrc is not modified Word operation Word operation reads the 16 LSBs of the source register Rsrc and writes the result to the 16 LSBs of the destination register Rdst The bits Rdst 19 16 are cleared The register Rsrc is not modified Address Word operation Address word operation reads the 20 bits of the source register Rsrc and writes the result to the 20 bits of the destination register Rdst The register Rsrc is not modified SXT Exception The SXT instruction is the only exception for register operation The sign of the low byte in bit 7 is extended to the bits Rdst 19 8 Example BIS W R5 R6 This instruction logically ORs the 16 bit data contained in R5 with the 16 bit contents of R6 R6 19 16 is cleared Before After Address Register Address Register Space Space 21036h xxxxh R5 AA550h 21036h PC R5 AA550h 21034h D506h PC R6 11111h 21034h D506h R6 0B551h A550h or 1111h B551h 4 16 16 Bit MSP430X CPU CPU Registers E
78. ent a 20 bit index may be used with the following instruction MOVX A EXEC PC 1M byte range with 20 bit index Absolute Mode Branch to the 20 bit address contained in absolute addresses EXEC LSBs and EXEC 2 MSBs Indirect addressing BRA amp EXEC MOVA amp abs20 PC Register Mode Branch to the 20 bit address contained in register R5 Indirect R5 BRA R5 MOVA R5 PC 4 158 16 Bit MSP430X CPU Address Instructions Indirect Mode Branch to the 20 bit address contained in the word pointed to by register R5 LSBs The MSBs have the address R5 2 Indirect indirect R5 BRA R5 MOVA R5 PC Indirect Auto Increment Mode Branch to the 20 bit address contained in the words pointed to by register R5 and increment the address in R5 afterwards by 4 The next time the S W flow uses R5 as a pointer it can alter the program execution due to access to the next address in the table pointed to by R5 Indi rect indirect R5 BRA R5 MOVA R5 PC R5 4 Indexed Mode Branch to the 20 bit address contained in the address pointed to by register R5 X e g a table with addresses starting at X R5 X points to the LSBs R5 X 2 points to the MSBs of the address X is within R5 32 K Indirect indirect R5 X BRA X R5 MOVA z16 R5 PC Note if the 16 bit index is not sufficient a 20 bit index X may be used with the following instruction MOVX A _X R5 PC 1M byte range with 20 bit index 16 Bit M
79. eset if Rdst 15 0 Z Set if result is zero reset otherwise C Loaded from the LSB n 1 LSB 1 n 2 LSB 2 n 3 or LSB 3 n 4 V Reset OSCOFF CPUOFF and GIE are not affected The unsigned address word in R5 is divided by 16 RRUM A 4 R5 R5 R5 4 R5 16 The word in R6 is shifted right by one bit The MSB R6 15 is loaded with O RRUM W 1 R6 R6 R6 2 R6 19 15 0 Figure 4 53 Rotate Right Unsigned RRUM W and RRUM A 16 19 15 0 19 0 ia 16 Bit MSP430X CPU 4 145 Extended Instructions RRUX A RRUX W RRUX B Syntax Operation Description Status Bits Mode Bits Example Rotate Right unsigned the 20 bit operand Rotate Right unsigned the 16 bit operand Rotate Right unsigned the 8 bit operand RRUX A Rdst RRUX W Rdst RRUX Rdst RRUX B Rdst C 0 gt MSB MSB 1 gt LSB 1 LSB gt C RRUxX is valid for register Mode only the destination operand is shifted right by one bit position as shown in Figure 4 54 The word instruction RRUX W clears the bits Rdst 19 16 The byte instruction RRUX B clears the bits Rdst 19 8 Zero is shifted into the MSB the LSB is shifted into the carry bit N Set if result is negative A dst 19 1 reset if dst 19 O W dst 15 1 reset if dst 15 0 B dst 7 1 reset if dst 7 0 Z Set if result is zero reset otherwise C Loaded from LSB V Reset OSCOFF CPUOFF and GIE are not affected The word in R
80. et if dst contained O7FFEh or 07FFFh reset otherwise Set if dst contained 07Eh or 07Fh reset otherwise OSCOFF CPUOFF and GIE are not affected RAM byte LEO is incremented by two PC points to upper memory INCDX B LEO 4 128 16 Bit MSP430X CPU Increment LEO by two INVX A INVX W INVX B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Extended Instructions Invert destination Invert destination Invert destination INVX A dst INVX dst or INVX W dst INVX B dst NOT dst gt dst XORX A 0FFFFFh dst XORX OFFFFh dst XORX B 0FFh dst The destination operand is inverted The original contents are lost N Set if result is negative reset if positive Z Set if dst contained OFFFFFh reset otherwise Set if dst contained OFFFFh reset otherwise Set if dst contained OFFh reset otherwise C Set if result is not zero reset otherwise NOT Zero V Set if initial destination operand was negative otherwise reset OSCOFF CPUOFF and GIE are not affected 20 bit content of R5 is negated twos complement INVX A R5 Invert R5 INCX A R5 R5 is now negated Content of memory byte LEO is negated PC is pointing to upper memory INVX B LEO Invert LEO INCX B LEO MEM LEO is negated 16 Bit MSP430X CPU 4 129 Extended Instructions MOVX A MOVX W MOVX B Syntax Operation Description Status Bits Mode Bits Example Example Loop
81. etition count in bits 3 0 0 Use Carry 01 Address word Pee PPE TP e o e e e XORX instruction Source R9 Destination R8 Destination register mode 9 Source register mode Figure 4 28 Example for an Extended Immediate Indexed Instruction CC eeen p ae XORX A 12345h 45678h R15 X Rn 01 Address PC ord 18xx extension word 12345h Immediate operand LSBs 2345h Index destination LSBs 5678h 16 Bit MSP430X CPU 4 47 MSP430X Extended Instructions Extended Double Operand Format l Instructions All twelve double operand instructions have extended versions as listed in Table 4 13 Table 4 13 Extended Double Operand Instructions Status Bits Mnemonic Operands Operation V N ZC MOVX B A src dst src dst ADDX B A src dst src dst dst nn as ADDCX B A srce dst src dst C gt dst ee eS SUBX B A src dst dst not src 1 dst nr a es SUBCX B A src dst dst not src C dst pe get Be CMPX B A src dst dst src ee DADDX B A src dst src dst C gt dst decimal BITX B A src dst src and dst o oF FZ BICX B A src dst not src and dst dst BISX B A src dst src or dst dst XORX B A src dst src xor dst gt dst one Vie 6 ANDX B A src dst src and dst gt dst o Z ne The status bit is affected The status bit is not affected O The status bit is cleared 1 The status bit is set
82. extension word for non register modes is shown in Figure 4 26 and described in Table 4 12 An example is shown in Figure 4 28 Figure 4 26 The Extension Word for Non Register Modes 15 12 11 10 7 6 5 4 3 0 0 0 0 1 Source bits 19 16 jan o o Destination bits 19 16 Table 4 12 Description of the Extension Word Bits for Non Register Modes Bit Description 15 11 Extension word op code Op codes 1800h to 1FFFh are exten sion words Source Bits The four MSBs of the 20 bit source Depending on the source 19 16 addressing mode these four MSBs may belong to an immedi ate operand an index or to an absolute address A L Data length extension bit Together with the B W bits of the fol lowing MSP430 instruction the AL bit defines the used data length of the instruction A L B W Comment 0 0 Reserved 0 1 20 bit address word 1 0 16 bit word 1 1 8 bit byte 5 4 Reserved Destination Bits The four MSBs of the 20 bit destination Depending on the des 19 16 tination addressing mode these four MSBs may belong to an index or to an absolute address Te Note B W and AIL Bit Settings for SWPBX and SXTX The B W and A L bit settings for SWPBX and SXTX are A L B W 0 0 SWPBxX A SXTX A 0 1 n a 1 0 SWPB W SXTX W 1 1 n a ss 4 46 16 Bit MSP430X CPU MSP430X Extended Instructions Figure 4 27 Example for an Extended Register Register Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XORX A R9 R8 1 Rep
83. f positive Z Set if dst contained OFFFFh reset otherwise Set if dst contained OFFh reset otherwise C Set if result is not zero reset otherwise NOT Zero Set if result is not zero reset otherwise NOT Zero V Set if initial destination operand was negative otherwise reset OSCOFF CPUOFF and GIE are not affected Content of R5 is negated twos complement MOV 00AEh R5 R5 OOOAEh INV R5 Invert R5 R5 OFF51h INC R5 R5is now negated R5 O0FF52h Content of memory byte LEO is negated MOV B 0AEh LEO MEM LEO OAEh INV B LEO Invert LEO MEM LEO 051h INC B LEO MEM LEO is negated MEM LEO 052h 4 84 16 Bit MSP430X CPU Jc JHS Syntax Operation Description Status Bits Mode Bits Example Example Example MSP430 Instructions Jump if carry Jump if Higher or Same unsigned JC label JHS label lf C 1 PC 2 x Offset gt PC If C 0 execute the following instruction The carry bit C in the status register is tested If it is set the signed 10 bit word offset contained in the instruction is multiplied by two sign extended and added to the 20 bit program counter PC This means a jump in the range 511 to 512 words relative to the PC in the full memory range If C is reset the instruction after the jump is executed JC is used for the test of the carry bit C JHS is used for the comparison of unsigned numbers Status bits are not affected OSCOFF CPUOFF and GIE are no
84. fected If byte EDE lower 64 K contains positive data go to Label1 Software can run in the full memory range TST B amp EDE ls EDE positive V lt 0 JGE Label1 Yes JGE emulates JP No 80h lt EDE lt FFh If the content of R6 is greater than or equal to the memory pointed to by R7 the program continues a Label5 Signed data Data and program in full memory range CMP R7 R6 Is R6 gt R7 JGE Label5 Yes go to Label5 No continue here If R5 gt 12345h signed operands the program continues at Label2 Program in full memory range CMPA 12345h R5 Is R5 gt 12345h JGE Label2 Yes 12344h lt R5 lt 7FFFFh No 80000h lt R5 lt 12345h 16 Bit MSP430X CPU 4 87 MSP430 Instructions JL Syntax Operation Description Status Bits Mode Bits Example Example Example Jump if Less signed JL label If N xor V 1 PC 2 x Offset gt PC If N xor V 0 execute following instruction The negative bit N and the overflow bit V in the status register are tested If only one is set the signed 10 bit word offset contained in the instruction is multiplied by two sign extended and added to the 20 bit program counter PC This means a jump in the range 511 to 512 words relative to the PC in full memory range If both bits N and V are set or both are reset the instruction after the jump is executed JL is used for the comparison of signed operands also for incorrect resul
85. file reduces fetches to memory 20 bit address bus allows direct access and branching throughout the entire memory range without paging 16 bit data bus allows direct manipulation of word wide arguments Constant generator provides the six most often used immediate values and reduces code size Direct memory to memory transfers without intermediate register holding Byte word and 20 bit address word addressing The block diagram of the MSP430X CPU is shown in Figure 4 1 16 Bit MSP430X CPU Figure 4 1 MSP430X CPU Block Diagram 16 T MDB Memory Data Bus ZN 19 16 15 lt J RO PC Program Counter aS Ga H E R2 SR Status Register _ gt R3 CG2 Constant Generator e gt JA R6 General Purpose gt R7 General Purpose a R8 General Purpose e co f gt R11 General Purpose gt R12 General Purpose lt gt R13 General ae General papos gt CEY Tas General Negative N K Vv Memory Address Bus MAB ZN Zero Z Carry C f Overflow V 16 20 bit ALU K MCLK CPU Introduction 16 Bit MSP430X CPU 4 3 Interrupts 4 2 Interrupts The MSP430X uses the same interrupt structure as the MSP430 _j Vectored interrupts with no polling necessary _j Interrupt vectors are located downward from address OFFFEh Interrupt operation for both MSP430 and MSP430X CPUs is described in Chapter 2 System Resets Interrupts and Oper
86. fter the addition of the PC and the signed 16 bit index This means the calculated memory address is always located in the lower 64 KB and does not overflow or underflow out of the lower 64 KB memory space The RAM and the peripheral registers can be accessed this way and existing MSP430 software is usable without modifications as shown in Figure 4 15 Figure 4 19 Symbolic Mode Running in Lower 64 KB Lower 64 KB PC 19 16 0 19 1615 0 FFFFF Program counter PC 16 bit byte index 16 bit signed PC index 10000 OFFFF 16 bit signed add PC 19 0 Lower 64 KB Memory address Operation The signed 16 bit index in the next word after the instruction is added temporarily to the PC The resulting bits 19 16 are cleared giving a truncated 16 bit memory address which points to an operand address in the range 00000h to OFFFFh The operand is the content of the addressed memory location Length Two or three words Comment Valid for source and destination The assembler calculates the PC index and inserts it Example ADD B EDE TONI 4 24 16 Bit MSP430X CPU CPU Registers The previous instruction adds the 8 bit data contained in source byte EDE and destination byte TONI and places the result into the destination byte TONI Bytes EDE and TONI and the program are located in the lower 64 KB Source Byte EDE located at address 0 579Ch pointed to by PC 4766h where the PC index 4766h is the result of 0579Ch
87. gister are restored from the stack POP B 0 R7 The low byte of the stack is moved to the the byte which is pointed to by R7 Example R7 203h Mem R7 low byte of system stack Example R7 20Ah Mem R7 low byte of system stack POP SR Last word on stack moved to the SR O Note The System Stack Pointer The system stack pointer SP is always incremented by two independent of the byte suffix ee 16 Bit MSP430X CPU 4 95 MSP430 Instructions PUSH W PUSH B Syntax Operation Description Status Bits Mode Bits Example Example Save a word on the stack Save a byte on the stack PUSH dst or PUSH W _ dst PUSH B dst SP 2 gt SP dst gt SP The 20 bit stack pointer SP is decremented by two The operand is then copied to the RAM word addressed by the SP A pushed byte is stored in the low byte the high byte is not affected Not affected OSCOFF CPUOFF and GIE are not affected Save the two 16 bit registers R9 and R10 on the stack PUSH R9 Save R9 and R10 XXXXh PUSH R10 YYYYh Save the two bytes EDE and TONI on the stack The addresses EDE and TONI are within PC 32 K PUSH B EDE Save EDE xxXXh PUSH B TONI Save TONI xxYYh 4 96 16 Bit MSP430X CPU RET Syntax Operation Description Status Bits Mode Bits Example SUBR MSP430 Instructions Return from subroutine RET SP PC 15 0 Saved PC to PC 15 0 PC 19 16 lt 0 SP 2 SP The
88. h Start address OAA04h Symbolic Mode Call a subroutine at the 16 bit address contained in address EXEC EXEC is located at the address PC X where X is within PC 32 K CALL EXEC Start address at EXEC z16 PC Absolute Mode Call a subroutine at the 16 bit address contained in absolute address EXEC in the lower 64 K CALL amp EXEC Start address at EXEC Register Mode Call a subroutine at the 16 bit address contained in register R5 15 0 CALL R5 Start address at R5 Indirect Mode Call a subroutine at the 16 bit address contained in the word pointed to by register R5 20 bit address CALL R5 Start address at R5 4 70 16 Bit MSP430X CPU CLR W CLR B Syntax Operation Emulation Description Status Bits Example Example Example MSP430 Instructions Clear destination Clear destination CLR dst or CLR W dst CLR B dst 0 gt dst MOV 0 dst MOV B 0 dst The destination operand is cleared Status bits are not affected RAM word TONI is cleared CLR TONI 0 gt TONI Register R5 is cleared CLR R5 RAM byte TONI is cleared CLR B TONI 0 gt TONI 16 Bit MSP430X CPU 4 71 MSP430 Instructions CLRC Syntax Operation Emulation Description Status Bits Mode Bits Example Clear carry bit CLRC 0 gt C BIC 1 SR The carry bit C is cleared The clear carry instruction is a word instruction N Not affected Z Not affected C Cleared V Not
89. he item on TOS is written to the destination operand Register Mode Indexed Mode Symbolic Mode and Absolute Mode are possible The stack pointer is incremented by two or four Note the stack pointer is incremented by two also for byte operations Not affected OSCOFF CPUOFF and GIE are not affected Write the 16 bit value on TOS to the 20 bit address amp EDE POPX W amp EDE Write word to address EDE Write the 20 bit value on TOS to R9 POPX A R9 Write address word to R9 4 134 16 Bit MSP430X CPU PUSHX A PUSHX W PUSHX B Syntax Operation Description Status Bits Mode Bits Example Example Extended Instructions Save a single address word on the stack Save a single word on the stack Save a single byte on the stack PUSHX A src PUSHX src or PUSHX W src PUSHX B src Save the 8 16 20 bit value of the source operand on the TOS 20 bit addresses are possible The stack pointer SP is decremented by two byte and word operands or by four address word operand before the write operation The stack pointer is decremented by two byte and word operands or by four address word operand Then the source operand is written to the TOS All seven addressing modes are possible for the source operand Note This instruction does not use the extension word Not affected OSCOFF CPUOFF and GIE are not affected Save the byte at the 20 bit address amp EDE on the stack PUSHX B amp EDE Save byte at add
90. ise V Set if the subtraction of a negative source operand from a positive des tination operand delivers a negative result or if the subtraction of a posi tive source operand from a negative destination operand delivers a positive result reset otherwise no overflow OSCOFF CPUOFF and GIE are not affected A 20 bit constant 87654h is subtracted from R5 with the carry from the previous instruction SUBCX A 87654h R5 Subtract 87654h C from R5 A 48 bit number 3 words pointed to by R5 20 bit address is subtracted from a 48 bit counter in RAM pointed to by R7 R5 auto increments to point to the next 48 bit number SUBX W R5 0 R7 Subtract LSBs R5 2 SUBCX W R5 2 R7 Subtract MIDs with C R5 2 SUBCX W R5 4 R7 Subtract MSBs with C R5 2 Byte CNT is subtracted from the byte R12 points to The carry of the previous instruction is used 20 bit addresses SUBCX B amp CNT 0 R12 Subtract byte CNT from R12 16 Bit MSP430X CPU 4 149 Extended Instructions SWPBX A SWPBX W Syntax Operation Description Status Bits Mode Bits Example Example Swap bytes of lower word Swap bytes of word SWPBX A dst SWPBX W dst or SWPBX dst dst 15 8 lt dst 7 0 Register Mode Rn 15 8 are swapped with Rn 7 0 When the A extension is used Rn 19 16 are unchanged When the W extension is used Rn 19 16 are cleared Other Modes When the A extension is used bits 31 20 of the destination address
91. it register RRAM A n Rdst Rotate right Rdst n bits arithmetically 45 T E 16 20 bit register RLAM A n Rdst Rotate left Rdst n bits arithmetically Taq oe Pee 16 20 bit register RRCX B A dst Rotate right dst through carry 1 o eS 8 16 20 bit data RRUX B A dst Rotate right dst unsigned 8 16 20 bit 1 Ore a lt 8 RRAX B A dst Rotate right dst arithmetically 1 A SWPBX A dst Exchange low byte with high byte 1 SXTX A Rdst Bit7 gt bit8 bit19 1 Be OR SXTX A dst Bit7 gt bit8 MSB 1 a 4 50 16 Bit MSP430X CPU MSP430X Extended Instructions The three possible addressing mode combinations for format Il instructions are shown in Figure 4 31 Figure 4 31 Extended Format II Instruction Format 14 11 TEE Op code Op code e E eee Op code dst 15 0 ES BS Extended Format II Instruction Format Exceptions Exceptions for the Format II instruction formats are shown below Figure 4 32 PUSHM POPM Instruction Format 16 Bit MSP430X CPU 4 51 MSP430X Extended Instructions Figure 4 34 BRA Instruction Format c imm abs19 16 O PC imm15 0 amp abs15 0 index15 0 Figure 4 35 CALLA Instruction Format index15 0 imm15 0 index15 0 amp abs15 0 4 52 16 Bit MSP430X CPU Extended Emulated Instructions Table 4 15 Extended Emulated Instructions Instruction Explanation MSP430X Extended Instructions The extended instructions together with the c
92. ited to the lower 64 KB address range CALLA and RETA instructions have been added to the MSP430X CPU to handle subroutines in the entire address range with no code size overhead MSP430 Double Operand Format I Instructions Figure 4 22 shows the format of the MSP430 double operand instructions Source and destination words are appended for the Indexed Symbolic Absolute and Immediate modes Table 4 4 lists the twelve MSP430 double operand instructions Figure 4 22 MSP430 Double Operand Instruction Format 15 12 11 8 7 6 5 4 0 Source or Destination 15 0 Destination 15 0 Table 4 4 MSP430 Double Operand Instructions Mnemonic S Reg Operation Status Bits D Reg Vv N zZz c MOV B src dst src dst ADD B src dst src dst dst i P F ADDC B src dst sre dst C dst s is SUB B src dst dst not src 1 dst ji SUBC B src dst dst not src C gt dst i 2 x CMP B src dst dst src is hj d i DADD B src dst src dst C dst decimally i Bs 5 BIT B src dst src and dst 0 z z Z BIC B src dst not src and dst gt dst BIS B src dst src or dst dst XOR B src dst src xor dst gt dst j j Z AND B src dst src and dst gt dst 0 i i Z The status bit is affected The status bit is not affected 0 The status bit is cleared 1 The status bit is set 16 Bit MSP430X CPU 4 37 MSP430 and MSP430X Instructions Single Operand Format Il Instructi
93. itive result reset otherwise no overflow OSCOFF CPUOFF and GIE are not affected Compare EDE with a 20 bit constant 18000h Jump to label TONI if EDE equals the constant CMPX A 018000h EDE JEQ TONI Compare EDE with 18000h EDE contains 18000h Not equal A table word pointed to by R5 20 bit address is compared with R7 Jump to label TONI if R7 contains a lower signed 16 bit number CMPX W R5 R7 Compare two signed numbers JL TONI R7 lt R5 R7 gt R5 A table byte pointed to by R5 20 bit address is compared to the input in I O Porti Jump to label TONI if the values are equal The next table byte is addressed CMPX B R5 amp P11N JEQ TONI Compare P1 bits with table R5 1 Equal contents Not equal Note Use CMPA for the following two cases for better density and execution CMPA Rsrc Rdst or CMPA imm20 Rdst 16 Bit MSP430X CPU DADCX A DADCX W DADCX B Syntax Operation Emulation Description Status Bits Mode Bits Example Extended Instructions Add carry decimally to destination address word Add carry decimally to destination word Add carry decimally to destination byte DADCX A dst DADCX dst or DADCX W src dst DADCX B dst dst C gt dst decimally DADDX A 0 dst DADDX 0 dst DADDX B 0 dst The carry bit C is added decimally to the destination N Set if MSB of result is 1 address word gt 79999h word gt 7999h byte gt 79h
94. mp EDE RRAM n 1 2 2 z 2 RRCM n 1 7 RRUM n 1 as 7 z z RLAM n 1 z Z z PUSHM 2 n 1 z PUSHM A 2 2n 1 z z POPM 2 n 1 z z POPM A 2 2n 1 5 Z CALLA 4 1 5 1 5 1 4 2 6t 2 6 2 6 2 RRAX B 1 n 2 4 2 4 2 x 5 3 5 3 5 3 RRAX A 1 n 2 6 2 6 2 z 7 3 7 3 7 3 RRCX B t4n 2 4 2 4 2 5 3 5 3 5 3 RRCX A 1 n 2 6 2 6 2 7 3 7 3 7 3 PUSHX B 4 2 4 2 4 2 4 3 5t 3 5 3 5 3 PUSHX A 5 2 6 2 6 2 6 3 71 3 7 3 7 3 POPX B 3 2 z z Z 5 3 5 3 5 3 POPX A 4 2 z 3 7 3 7 3 7 3 T Add one cycle when Rn SP MSP430X Format I Double Operand Instruction Cycles and Lengths Table 4 18 lists the length and CPU cycles for all addressing modes of the MSP430X extended format instructions 16 Bit MSP430X CPU 4 55 MSP430X Extended Instructions Table 4 18 MSP430X Format Instruction Cycles and Length No of Length of Addressing Mode Cycles Instruction Source Destination B W A B W A Examples Rn Rmt 2 2 2 BITX B R5 R8 PC 3 3 2 ADDX R9 PC X Rm 5t 78 3 ANDX A R5 4 R6 EDE 5 78 3 XORX R8 EDE amp EDE 5t 78 3 BITX W R5 amp EDE Rn Rm 3 4 2 BITX R5 R8 PC 3 4 2 ADDX R9 PC X Rm 6t 98 3 ANDX A R5 4 R6 EDE 6t 9 3 XORX R8 EDE amp EDE 6t 98 3 BITX B R5 amp 8EDE Rn Rm 3 4 2 BITX R5 R8 PC 4 5 2 ADDX A R9 PC X Rm 6t 98 3 ANDX R5 4 R6 EDE 6t 98 3 XORX B R8 EDE amp EDE 6t 98 3 BITX R5 amp EDE N Rm 3 3 3 BITX 20 R8 Pc 4 4 3 ADDX A FE000h PC X Rm 6t 88 4 ANDX 1234 4 R6
95. mulation Description Status Bits Mode Bits Example Example MSP430 Instructions Subtract source and borrow NOT carry from destination Subtract source and borrow NOT carry from destination SBC dst or SBC W dst SBC B dst dst OFFFFh C gt dst dst OFFh C gt dst SUBC 0 dst SUBC B 0 dst The carry bit C is added to the destination operand minus one The previous contents of the destination are lost N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if there is a carry from the MSB of the result reset otherwise Set to 1 if no borrow reset if borrow V Set if an arithmetic overflow occurs reset otherwise OSCOFF CPUOFF and GIE are not affected The 16 bit counter pointed to by R13 is subtracted from a 32 bit counter pointed to by R12 SUB R13 0 R12 Subtract LSDs SBC 2 R12 Subtract carry from MSD The 8 bit counter pointed to by R13 is subtracted from a 16 bit counter pointed to by R12 SUB B R13 0 R12 Subtract LSDs SBC B 1 R12 Subtract carry from MSD ee Note Borrow Implementation The borrow is treated asa NOT carry Borrow Carry bit Yes 0 No 1 ee 16 Bit MSP430X CPU 4 103 MSP430 Instructions SETC Syntax Operation Emulation Description Status Bits Mode Bits Example DSUB Set carry bit SETC 1 gt C BIS 1 SR The carry bit C is set N Not affected Z Not affected C Set
96. n the result of an operation is negative and cleared when the result is positive 16 Bit MSP430X CPU 4 9 CPU Registers Bit Description Z Zero bit This bit is set when the result of an operation is zero and cleared when the result is not zero C Carry bit This bit is set when the result of an operation produced a carry and cleared when no carry occurred 4 10 16 Bit MSP430X CPU CPU Registers 4 3 4 The Constant Generator Registers CG1 and CG2 Six commonly used constants are generated with the constant generator registers R2 CG1 and R3 CG2 without requiring an additional 16 bit word of program code The constants are selected with the source register addressing modes As as described in Table 4 2 Table 4 2 Values of Constant Generators CG1 CG2 Register As Constant Remarks R2 00 Register mode R2 01 0 Absolute address mode R2 10 00004h 4 bit processing R2 11 00008h 8 bit processing R3 00 00000h 0 word processing R3 01 00001h 1 R3 10 00002h 2 bit processing R3 11 FFh FFFFh FFFFFh 1 word processing The constant generator advantages are _j No special instructions required _j No additional code word for the six constants Lj No code memory access required to retrieve the constant The assembler uses the constant generator automatically if one of the six constants is used as an immediate source operand Registers R2 and R3 used in the constant mode cannot be addressed e
97. ndirect addressing CALLA amp EXEC Start address at EXEC Register Mode Call a subroutine at the 20 bit address contained in register R5 Indirect R5 CALLA R5 Start address at R5 4 160 16 Bit MSP430X CPU Address Instructions Indirect Mode Call a subroutine at the 20 bit address contained in the word pointed to by register R5 LSBs The MSBs have the address R5 2 Indi rect indirect R5 CALLA R5 Start address at R5 Indirect Auto Increment Mode Call a subroutine at the 20 bit address con tained in the words pointed to by register R5 and increment the 20 bit address in R5 afterwards by 4 The next time the S W flow uses R5 as a pointer it can alter the program execution due to access to the next word address in the table pointed to by R5 Indirect indirect R5 CALLA R5 Start address at R5 R5 4 Indexed Mode Call a subroutine at the 20 bit address contained in the ad dress pointed to by register R5 X e g a table with addresses starting at X R5 X points to the LSBs R5 X 2 points to the MSBs of the word ad dress X is within R5 32 K Indirect indirect R5 X CALLA X R5 Start address at R5 X z16 R5 16 Bit MSP430X CPU 4 161 Address Instructions CLRA Syntax Operation Emulation Description Status Bits Example Clear 20 bit destination register CLRA Rdst 0 gt Rdst MOVA 0 Rdst The destination register is cleared Status bits are not affected
98. o reset otherwise C Set if result is not zero reset otherwise C not Z V Reset OSCOFF CPUOFF and GIE are not affected The signed 8 bit data in EDE lower 64 K is sign extended and added to the 16 bit signed data in R7 MOV B amp EDE R5 EDE gt R5 00XXh SXT R5 Sign extend low byte to R5 19 8 ADD R5 R7 Add signed 16 bit values The signed 8 bit data in EDE PC 82 K is sign extended and added to the 20 bit data in R7 MOV B EDE R5 EDE gt R5 00XXh SXT R5 Sign extend low byte to R5 19 8 ADDA R5 R7 Add signed 20 bit values 4 110 16 Bit MSP430X CPU TST W TST B Syntax Operation Emulation Description Status Bits Mode Bits Example Example MSP430 Instructions Test destination Test destination TST dst or TST W dst TST B dst dst OFFFFh 1 dst OFFh 1 CMP 0 dst CMP B 0 dst The destination operand is compared with zero The status bits are set accord ing to the result The destination is not affected N Set if destination is negative reset if positive Z Set if destination contains zero reset otherwise C Set V Reset OSCOFF CPUOFF and GIE are not affected R7 is tested If it is negative continue at R7NEG if it is positive but not zero continue at R7POS TST R7 Test R7 JN R7NEG R7 is negative JZ R7ZERO R7 is zero R7POS n R7 is positive but not zero R7NEG an R7 is negative R7ZERO _ R7 is zero The low byte of R7 is tested
99. o set continue If R5 15000h 20 bit data the program continues at Label2 CMPA 15000h R5 Is R5 15000h Info to SR JEQ Label2 Yes R5 15000h Z 1 No R5 4 15000h Continue R7 20 bit counter is incremented If its content is zero the program continues at Label4 ADDA 1 R7 Increment R7 JZ Label4 Zero reached Go to Label4 R7 0 Continue here 4 86 16 Bit MSP430X CPU JGE Syntax Operation Description Status Bits Mode Bits Example Example Example MSP430 Instructions Jump if Greater or Equal signed JGE label If N xor V 0 PC 2 x Offset gt PC If N xor V 1 execute following instruction The negative bit N and the overflow bit V in the status register are tested If both bits are set or both are reset the signed 10 bit word offset contained in the instruction is multiplied by two sign extended and added to the 20 bit program counter PC This means a jump in the range 511 to 512 words relative to the PC in full Memory range If only one bit is set the instruction after the jump is executed JGE is used for the comparison of signed operands also for incorrect results due to overflow the decision made by the JGE instruction is correct Note JGE emulates the non implemented JP jump if positive instruction if used after the instructions AND BIT RRA SXTX and TST These instructions clear the V bit Status bits are not affected OSCOFF CPUOFF and GIE are not af
100. ode Rn Indexed mode X Rn Symbolic mode ADDR Absolute mode amp ADDR Indirect register Rn mode Indirect Rn autoincrement Immediate mode N Description Register contents are operand Rn X points to the operand X is stored in the next word or stored in combination of the preceding extension word and the next word PC X points to the operand X is stored in the next word or stored in combination of the preceding extension word and the next word Indexed mode X PC is used The word following the instruction contains the absolute address X is stored in the next word or stored in combination of the preceding extension word and the next word Indexed mode X SR is used Rn is used as a pointer to the operand Rn is used as a pointer to the operand Rn is incremented afterwards by 1 for B instructions by 2 for W instructions and by 4 for A instructions N is stored in the next word or stored in combination of the preceding extension word and the next word Indirect autoincrement mode PC is used The seven addressing modes are explained in detail in the following sections Most of the examples show the same addressing mode for the source and destination but any valid combination of source and destination addressing modes is possible in an instruction gt Ke OC Note Use of Labels EDE TONI TOM and LEO Throughout MSP430 documentation EDE TONI TOM and LEO are used as generic lab
101. ons Figure 4 23 shows the format for MSP430 single operand instructions except RETI The destination word is appended for the Indexed Symbolic Absolute and Immediate modes Table 4 5 lists the seven single operand instructions Figure 4 23 MSP430 Single Operand Instructions 15 7 6 5 4 0 Destination 15 0 Table 4 5 MSP430 Single Operand Instructions Mnemonic S Reg Operation Status Bits peg V N Z Cc RRC B dst GoMSBs 18SB56 gt o gt o RRA B dst MSB gt MSB LSB gt C 0 j 5 PUSH B sre SP 2 gt SP src gt SP SWPB dst bit 15 bit 8 bit 7 bit O CALL dst Call subroutine in lower 64 KB RETI TOS gt SR SP 2 gt SP i j i TOS gt PC SP 2 gt SP SXT dst Register mode 0 i i Z bit 7 gt bit 8 bit 19 Other modes bit 7 gt bit 8 bit 15 The status bit is affected The status bit is not affected O The status bit is cleared 1 The status bit is set 4 38 16 Bit MSP430X CPU MSP430 and MSP430X Instructions Jumps Figure 4 24 shows the format for MSP430 and MSP430X jump instructions The signed 10 bit word offset of the jump instruction is multiplied by two sign extended to a 20 bit address and added to the 20 bit program counter This allows jumps in a range of 511 to 512 words relative to the program counter in the full 20 bit address space Jumps do not affect the status bits Table 4 6 lists and describes the eight jump instructions Figure
102. onstant generator form the extended Emulated instructions Table 4 15 lists the Emulated instructions Emulation ADCX B A dst BRA dst RETA CLRA Rdst CLRX B A dst DADCX B A dst DECX B A dst DECDA Rdst DECDX B A dst INCX B A dst INCDA Rdst INCDX B A dst INVX B A dst RLAX B A dst RLCX B A dst TSTA Rdst TSTX B A dst POPX dst Add carry to dst Branch indirect dst Return from subroutine Clear Rdst Clear dst Add carry to dst decimally Decrement dst by 1 Decrement dst by 2 Decrement dst by 2 Increment dst by 1 Increment Rdst by 2 Increment dst by 2 Invert dst Shift left dst arithmetically Shift left dst logically through carry Subtract carry from dst Test Rdst compare with 0 Test dst compare with 0 Pop to dst ADDCX B A 0 dst MOVA dst PC MOVA SP PC MOV 0 Rdst MOVX B A 0 dst DADDX B A 0 dst SUBX B A 1 dst SUBA 2 Rdst SUBX B A 2 dst ADDX B A 1 dst ADDA 2 Rdst ADDX B A 2 dst XORX B A 1 dst ADDX B A dst dst ADDCX B A dst dst SUBCX B A 0 dst CMPA 0 Rdst CMPX B A 0 dst MOVX B A SP dst 16 Bit MSP430X CPU 4 53 MSP430X Extended Instructions MSP430X Address Instructions MSP430X address instructions are instructions that support 20 bit operands but have restricted addressing modes The addressing modes are restricted to the register mode and the Immediate mode except for the MOVA ins
103. ontained in the extension word the 16 LSBs are contained in the word following the instruction Comment Valid for source and destination The assembler calculates the register index and inserts it Example ADDX B EDE TONI The instruction adds the 8 bit data contained in source byte EDE and destination byte TONI and places the result into the destination byte TONI Source Byte EDE located at address 3579Ch pointed to by PC 14766h is the 20 bit result of 3579Ch 21036h 14766h Address 21036h is the address of the index in this example Destination Byte TONI located at address 77778h pointed to by PC 56740h is the 20 bit result of 77778h 21038h 56740h Address 21038h is the address of the index in this example Before Address Space After Address Space 2103Ah 21038h 21036h 21034h 21032h 2103Ah 21038h 21036h 21034h 21032h 21038h 32h src 7777Ah 56740h_ 7777Ah 45h_ dst 77778h 77778h 77778h 77h Sum 21036h 3579Eh 14766h__ 3579Eh 3579Ch 3579Ch 3579Ch 4 28 16 Bit MSP430X CPU CPU Registers 4 4 4 Absolute Mode The Absolute mode uses the contents of the word following the instruction as the address of the operand The Absolute mode has two addressing possibilities _j Absolute mode in lower 64 KB memory 1 MSP430X instruction with Absolute mode 16 Bit MSP430X CPU 4 29 CPU Registers Absolute Mode in Lower 64 KB 4 30 If an MSP430 instruction is used with Absolute a
104. r SP The 20 bit stack pointer SP R1 is used by the CPU to store the return addresses of subroutine calls and interrupts It uses a predecrement postincrement scheme In addition the SP can be used by software with all instructions and addressing modes Figure 4 5 shows the SP The SP is initialized into RAM by the user and is always aligned to even addresses Figure 4 6 shows the stack usage Figure 4 7 shows the stack usage when 20 bit address words are pushed Figure 4 5 Stack Pointer 19 1 0 Stack Pointer Bits 19 to 1 g MOV W 2 SP R6 Copy Item I2 to R6 MOV W R7 0 SP Overwrite TOS with R7 PUSH 0123h Put 0123h on stack POP R8 R8 0123h Figure 4 6 Stack Usage Address PUSH 0123h POP R8 Oxxxh Oxxxh 2 Oxxxh 4 SP Oxxxh 6 Oxxxh 8 Figure 4 7 PUSHX A Format on the Stack SPoid Item n 1 SP Item 15 0 16 Bit MSP430X CPU 4 7 CPU Registers The special cases of using the SP as an argument to the PUSH and POP instructions are described and shown in Figure 4 8 Figure 4 8 PUSH SP POP SP Sequence PUSH SP POP SP Ooo o Oooo SPoid O eo SP4 SP4 SP3 SP The stack pointer is changed after The stack pointer is not changed after a POP SP a PUSH SP instruction instruction The POP SP instruction places SP1 into the stack pointer SP SP2 SP1 4 8 16 Bit MSP430X CPU CPU Registers 4 3 3 Status Register SR The 16 bit status register SR R2 used as a source or destination regi
105. register are restored to the CPU registers Note This does not use the extension word POPM A The CPU registers pushed on the stack are moved to the extended CPU registers starting with the CPU register Rdst n 1 The stack pointer is incremented by n x 4 after the operation POPM W The 16 bit registers pushed on the stack are moved back to the CPU registers starting with CPU register Rdst n 1 The stack pointer is incremented by n x 2 after the instruction The MSBs Rdst 19 16 of the restored CPU registers are cleared Not affected except SR is included in the operation OSCOFF CPUOFF and GIE are not affected except SR is included in the op eration Restore the 20 bit registers R9 R10 R11 R12 R13 from the stack POPM A 5 R13 Restore R9 R10 R11 R12 R13 Restore the 16 bit registers R9 R10 R11 R12 R13 from the stack POPM W 5 R13 Restore R9 R10 R11 R12 R13 4 132 16 Bit MSP430X CPU PUSHM A PUSHM W Syntax Operation Description Status Bits Mode Bits Example Example Extended Instructions Save n CPU registers 20 bit data on the stack Save n CPU registers 16 bit words on the stack PUSHM A n Rdst 1 lt n lt 16 PUSHM W n Rdst or PUSHM n Rdst 1 lt n lt 16 PUSHM A Save the 20 bit CPU register values on the stack The stack pointer SP is decremented by four for each register stored on the stack The MSBs are stored first higher address PUSHM W Save th
106. ress EDE Save the 20 bit value in R9 on the stack PUSHX A R9 Save address word in R9 16 Bit MSP430X CPU 4 135 Extended Instructions RLAM A RLAM W Syntax Operation Description Status Bits Mode Bits Example Rotate Left Arithmetically the 20 bit CPU register content Rotate Left Arithmetically the 16 bit CPU register content RLAM A n Rdst 1 lt n lt 4 RLAM W n Rdst or RLAM n Rdst 1 lt n lt 4 C amp MSB amp MSB 1 LSB 1 LSB e 0 The destination operand is shifted arithmetically left one two three or four positions as shown in Figure 4 44 RLAM works as a multiplication signed and unsigned with 2 4 8 or 16 The word instruction RLAM W clears the bits Radst 19 16 Note This instruction does not use the extension word N Set if result is negative A Rdst 19 1 reset if Rdst 19 0 W Rdst 15 1 reset if Rdst 15 0 Z Set if result is zero reset otherwise C Loaded from the MSB n 1 MSB 1 n 2 MSB 2 n 3 MSB 3 n 4 V Undefined OSCOFF CPUOFF and GIE are not affected The 20 bit operand in R5 is shifted left by three positions It operates equal to an arithmetic multiplication by 8 RLAM A 3 R5 R5 R5x8 Figure 4 44 Rotate Left Arithmetically RLAM W and RLAM A 19 16 15 0 19 0 4 136 16 Bit MSP430X CPU RLAX A RLAX W RLAX B Syntax Operation Emulation Description Extended Instructions Rotate left arithmetically
107. rwise Loaded from the MSB Set if an arithmetic overflow occurs the initial value is 04000h lt dst lt OCOOOh reset otherwise Set if an arithmetic overflow occurs the initial value is 040h lt dst lt OCOh reset otherwise OSCOFF CPUOFF and GIE are not affected R5 is shifted left one position RLC R5 R5 x 2 C gt R5 The input P1IN 1 information is shifted into the LSB of R5 BIT B 2 amp P1IN Information gt Carry RLC R5 Carry P0in 1 gt LSB of R5 The MEM LEO content is shifted left one position RLC B LEO Mem LEO x 2 C gt Mem LEO a aT Note RLC and RLC B Substitution The assembler does not recognize the instruction RLC R5 RLC B R5 or RLC B R5 It must be substituted by ADDC R5 2 R5 ADDC B R5 1 R5 or ADDC B R5 4 100 16 Bit MSP430X CPU RRALW RRA B Syntax Operation Description Status Bits Mode Bits Example Example MSP430 Instructions Rotate Right Arithmetically destination word Rotate Right Arithmetically destination byte RRA B dst or RRA W dst MSB MSB gt MSB 1 gt LSB 1 LSB gt C The destination operand is shifted right arithmetically by one bit position as shown in Figure 4 40 The MSB retains its value sign RRA operates equal to a signed division by 2 The MSB is retained and shifted into the MSB 1 The LSB 1 is shifted into the LSB The previous LSB is shifted into the carry bit C N Set if result is
108. ry Register 4 12 16 Bit MSP430X CPU CPU Registers Figure 4 11 and Figure 4 12 show 16 bit word handling W suffix The handling is shown for a source register and a destination memory word and for a source memory word and a destination register Figure 4 11 Register Word Operation Register Word Operation High Byte Low Byte 19 1615 87 0 Register Memory Memory Figure 4 12 Word Register Operation Word Register Operation High Byte Low Byte Memory Register Register 16 Bit MSP430X CPU 4 13 CPU Registers Figure 4 13 and Figure 4 14 show 20 bit address word handling A suffix The handling is shown for a source register and a destination memory address word and for a source memory address word and a destination register Figure 4 13 Register Address Word Operation Register Address Word Operation High Byte Low Byte 19 1615 87 0 Figure 4 14 Address Word Register Operation Address Word Register Operation High Byte Low Byte 19 1615 87 0 Register 4 14 16 Bit MSP430X CPU 4 4 Addressing Modes CPU Registers Seven addressing modes for the source operand and four addressing modes for the destination operand use 16 bit or 20 bit addresses The MSP430 and MSP430xX instructions are usable throughout the entire 1 MB memory range Table 4 3 Source Destination Addressing As Ad 00 0 01 1 01 1 01 1 10 11 11 Addressing Mode Syntax Register m
109. s XORX A TONI amp CNTR Toggle bits in CNTR A table word pointed to by R5 20 bit address is used to toggle bits in R6 XORX W R5 R6 Toggle bits in R6 R6 19 16 0 Reset to zero those bits in the low byte of R7 that are different from the bits in byte EDE 20 bit address XORX B EDE R7 INV B R7 Set different bits to 1 in R7 Invert low byte of R7 R7 19 8 0 16 Bit MSP430X CPU 4 155 Address Instructions 4 6 4 Address Instructions MSP430X address instructions are instructions that support 20 bit operands but have restricted addressing modes The addressing modes are restricted to the Register mode and the Immediate mode except for the MOVA instruction Restricting the addressing modes removes the need for the additional extension word op code improving code density and execution time The MSP430X address instructions are listed and described in the following pages 4 156 16 Bit MSP430X CPU ADDA Syntax Operation Description Status Bits Mode Bits Example Address Instructions Add 20 bit source to a 20 bit destination register ADDA Rsrc Rdst ADDA imm20 Rdst src Rdst gt Rdst The 20 bit source operand is added to the 20 bit destination CPU register The previous contents of the destination are lost The source operand is not affected Set if result is negative Rdst 19 1 reset if positive Rdst 19 0 Set if result is zero reset otherwise Set if there is a carry from the
110. s Mode Bits Example Example Example Test bits set in source address word in destination address word Test bits set in source word in destination word Test bits set in source byte in destination byte BITX A src dst BITX src dst or BITX W src dst BITX B src dst src and dst The source operand and the destination operand are logically ANDed The result affects only the status bits Both operands may be located in the full address space N Set if result is negative MSB 1 reset if positive MSB 0 Z Set if result is zero reset otherwise C Set if the result is not zero reset otherwise C not Z V Reset OSCOFF CPUOFF and GIE are not affected Test if bit 16 or 15 of R5 20 bit data is set Jump to label TONI if so BITX A 018000h R5 JNZ TONI Test R5 16 15 bits At least one bit is set Both are reset A table word pointed to by R5 20 bit address is used to test bits in R7 Jump to label TONI if at least one bit is set BITX W R5 R7 JC TONI Test bits in R7 C not Z At least one is set Both are reset A table byte pointed to by R5 20 bit address is used to test bits in input Port1 Jump to label TONI if no bit is set The next table byte is addressed BITX B R5 amp P11N Test input P1 bits R5 1 JNC TONI No corresponding input bit is set At least one bit is set 4 120 16 Bit MSP430X CPU CLRX A CLRX W CLRX B Syntax Operation Emulation De
111. s their 16 bit capability is exceeded The MSP430X instructions are used when the addressing of the operands or the data length exceeds the 16 bit capability of the MSP430 instructions There are three possibilities when choosing between an MSP430 and MSP430X instruction Lj To use only the MSP430 instructions The only exceptions are the CALLA and the RETA instruction This can be done if a few simple rules are met m Placement of all constants variables arrays tables and data in the lower 64 KB This allows the use of MSP430 instructions with 16 bit addressing for all data accesses No pointers with 20 bit addresses are needed m Placement of subroutine constants immediately after the subroutine code This allows the use of the symbolic addressing mode with its 16 bit index to reach addresses within the range of PC 32 KB Lj To use only MSP430xX instructions The disadvantages of this method are the reduced speed due to the additional CPU cycles and the increased program space due to the necessary extension word for any double operand instruction Lj Use the best fitting instruction where needed The following sections list and describe the MSP430 and MSP430X instructions 4 36 16 Bit MSP430X CPU MSP430 and MSP430X Instructions 4 5 1 MSP430 Instructions The MSP430 instructions can be used regardless if the program resides in the lower 64 KB or beyond it The only exceptions are the instructions CALL and RET which are lim
112. s 0 No 1 ee 16 Bit MSP430X CPU 4 147 Extended Instructions SUBX A SUBX W SUBX B Syntax Operation Description Status Bits Mode Bits Example Example Example Subtract source address word from destination address word Subtract source word from destination word Subtract source byte from destination byte SUBX A src dst SUBX src dst or SUBX W src dst SUBX B src dst not src 1 dst gt dst or dst src dst The source operand is subtracted from the destination operand This is made by adding the 1 s complement of the source 1 to the destination The source operand is not affected The result is written to the destination operand Both operands may be located in the full address space N Set if result is negative src gt dst reset if positive src lt dst Z Set if result is zero src dst reset otherwise src dst C Set if there is a carry from the MSB reset otherwise V Set if the subtraction of a negative source operand from a positive des tination operand delivers a negative result or if the subtraction of a posi tive source operand from a negative destination operand delivers a positive result reset otherwise no overflow OSCOFF CPUOFF and GIE are not affected A 20 bit constant 87654h is subtracted from EDE LSBs and EDE 2 MSBs SUBX A 87654h EDE Subtract 87654h from EDE 2 EDE A table word pointed to by R5 20 bit address is subtracted from R7 Jump
113. scription Status Bits Example Extended Instructions Clear destination address word Clear destination word Clear destination byte CLRX A CLRX CLRX B 0 gt dst MOVX A MOVX MOVX B dst dst or CLRX W dst dst 0 dst 0 dst 0 dst The destination operand is cleared Status bits are not affected RAM address word TONI is cleared CLRX A TONI 0 gt TONI 16 Bit MSP430X CPU 4 121 Extended Instructions CMPX A CMPX W CMPX B Syntax Operation Description Status Bits Mode Bits Example Example Example 4 122 Compare source address word and destination address word Compare source word and destination word Compare source byte and destination byte CMPxX A _ src dst CMPX src dst or CMPX W src dst CMPX B src dst not src 1 dst or dst src The source operand is subtracted from the destination operand by adding the 1 s complement of the source 1 to the destination The result affects only the status bits Both operands may be located in the full address space Set if result is negative src gt dst reset if positive src lt dst Set if result is zero src dst reset otherwise src dst Set if there is a carry from the MSB reset otherwise Set if the subtraction of a negative source operand from a positive destination operand delivers a negative result or if the subtraction of a positive source operand from a negative destination operand delivers a pos
114. set if positive Z Set if dst contained OFFFFFh reset otherwise Set if dst contained OFFFFh reset otherwise Set if dst contained OFFh reset otherwise C Set if dst contained OFFFFFh reset otherwise Set if dst contained OFFFFh reset otherwise Set if dst contained OFFh reset otherwise V Set if dst contained O7FFFh reset otherwise Set if dst contained O7FFFh reset otherwise Set if dst contained 07Fh reset otherwise OSCOFF CPUOFF and GIE are not affected RAM address word TONI is incremented by 1 INCX A TONI Increment TONI 20 bits 16 Bit MSP430X CPU 4 127 Extended Instructions INCDX A INCDX W INCDX B Syntax Operation Emulation Example Status Bits Mode Bits Example Double increment destination address word Double increment destination word Double increment destination byte INCDX A dst INCDX dst INCDX B dst dst 2 gt dst ADDX A 2 dst ADDX 2 dst ADDX B 2 dst or INCDX W_ dst The destination operand is incremented by two The original contents are lost N Set if result is negative reset if positive Z Set if dst contained OFFFFEh reset otherwise Set if dst contained OFFFEh reset otherwise Set if dst contained OFEh reset otherwise C Set if dst contained OFFFFEh or OFFFFFh reset otherwise Set if dst contained OFFFEh or OFFFFh reset otherwise Set if dst contained OFEh or OFFh reset otherwise V Set if dst contained O7FFFEh or O7FFFFh reset otherwise S
115. ster can only be used in register mode addressed with word instructions The remaining combinations of addressing modes are used to support the constant generator Figure 4 9 shows the SR bits Do not write 20 bit values to the SR Unpredictable operation can result Figure 4 9 Status Register Bits 15 9 8 7 0 OSC CPU rw 0 Table 4 1 describes the status register bits Table 4 1 Description of Status Register Bits Bit Description Reserved Reserved V Overflow bit This bit is set when the result of an arithmetic operation overflows the signed variable range ADD B ADDX B A Set when ADDC B ADDCX B A positive positive negative ADDA negative negative positive otherwise reset SUB B SUBX B A Set when SUBC B SUBCX B A positive negative negative SUBA CMP B negative positive positive CMPX B A CMPA otherwise reset SCG1 System clock generator 1 This bit when set turns off the DCO dc generator if DCOCLK is not used for MCLK or SMCLK SCGO System clock generator 0 This bit when set turns off the FLL loop control OSCOFF Oscillator Off This bit when set turns off the LFXT1 crystal oscillator when LFXT1CLK is not used for MCLK or SMCLK CPUOFF CPU off This bit when set turns off the CPU GIE General interrupt enable This bit when set enables maskable inter rupts When reset all maskable interrupts are disabled N Negative bit This bit is set whe
116. struction adds the 20 bit data contained in the source and the destination addresses and places the result into the destination Source Destination 16 Bit MSP430X CPU Two words pointed to by R5 12346h which results in address 23456h 12346h 3579Ch Two words pointed to by R6 32100h which results in address 45678h 32100h 77778h CPU Registers The extension word contains the MSBs of the source index and of the destination index and the A L bit for 20 bit data The instruction word uses byte mode due to the 20 bit data length with bits A L B W 01 Before After Address Register Address Register Space Space 2103Ah 23456h 2103Ah PC R5 23456h 21038h 45678h 21038h R6 45678h 21036h 21036h 21034h 21034h 21032h 21032h 45678h 65432h src 7777Ah 32100h 7777Ah 12345h__ dst 77778h 77778h 77778h 77777h Sum 23456h 3579Eh 12346h 3579Eh 3579Ch 3579Ch 3579Ch 16 Bit MSP430X CPU 4 23 CPU Registers 4 4 3 Symbolic Mode The Symbolic mode calculates the address of the operand by adding the signed index to the program counter The Symbolic mode has three addressing possibilities H Symbolic mode in lower 64 KB memory J MSP430 instruction with symbolic mode addressing memory above the lower 64 KB memory J MSP480xX instruction with symbolic mode Symbolic Mode in Lower 64 KB If the PC points to an address in the lower 64 KB of the memory range the calculated memory address bits 19 16 are cleared a
117. t affected The state of the port 1 pin P1IN 1 bit defines the program flow BIT B 2 amp P1IN Port 1 bit 1 set Bit gt C JC Label1 Yes proceed at Label1 No continue If R5 gt R6 unsigned the program continues at Label2 CMP R6 R5 Is R5 gt R6 Info to C JHS Label2 Yes C 1 No R5 lt R6 Continue If R5 gt 12345h unsigned operands the program continues at Label2 CMPA 12345h R5 Is R5 gt 12345h Info to C JHS Label2 Yes 12344h lt R5 lt F FFFFh C 1 No R5 lt 12345h Continue 16 Bit MSP430X CPU 4 85 MSP430 Instructions JEQ JZ Syntax Operation Description Status Bits Mode Bits Example Example Example Jump if equal Jump if zero JZ label JEQ label lfZ 1 PC 2 x Offset PC If Z 0 execute following instruction The Zero bit Z in the status register is tested If it is set the signed 10 bit word offset contained in the instruction is multiplied by two sign extended and added to the 20 bit program counter PC This means a jump in the range 511 to 512 words relative to the PC in the full memory range If Z is reset the instruction after the jump is executed JZ is used for the test of the Zero bit Z JEQ is used for the comparison of operands Status bits are not affected OSCOFF CPUOFF and GIE are not affected The state of the P2IN 0O bit defines the program flow BIT B 1 amp P2IN Port 2 bit O reset JZ Label1 Yes proceed at Label1 N
118. t if positive Z Set if dst contained 2 reset otherwise C Reset if dst contained 0 or 1 set otherwise V Set if an arithmetic overflow occurs otherwise reset Set if initial value of destination was 08001 or 08000h otherwise reset Set if initial value of destination was 081 or 080h otherwise reset OSCOFF CPUOFF and GIE are not affected R10 is decremented by 2 DECD R10 Decrement R10 by two Move a block of 255 words from memory location starting with EDE to memory location starting with TONI Tables should not overlap start of destination address TONI must not be within the range EDE to EDE 0FEh G Example MOV EDE R6 MOV 510 R10 L 1 MOV R6 TONI EDE 2 R6 DECD R10 JNZ L 1 Memory at location LEO is decremented by two DECD B LEO Decrement MEM LEO Decrement status byte STATUS by two DECD B STATUS 16 Bit MSP430X CPU 4 79 MSP430 Instructions DINT Syntax Operation Emulation Description Status Bits Mode Bits Example Disable general interrupts DINT 0 gt GIE or OFFF7h AND SR SR NOT src AND dst gt dst BIC 8 SR All interrupts are disabled The constant 08h is inverted and logically ANDed with the status register SR The result is placed into the SR Status bits are not affected GIE is reset OSCOFF and CPUOFF are not affected The general interrupt enable GIE bit in the status register is cleared to allow a nondisrupted move of a 32 bit
119. table word pointed to by R5 20 bit address is used to test bits in R7 Jump to label TONI if at least one bit is set R7 19 16 are not affected BIT W R5 R7 JC TONI Test bits in R7 At least one bit is set Both are reset A table byte pointed to by R5 20 bit address is used to test bits in output Port1 Jump to label TONI if no bit is set The next table byte is addressed BIT B R5 amp P1OUT JNC TONI Test I O port P1 bits R5 1 No corresponding bit is set At least one bit is set 4 68 16 Bit MSP430X CPU BR BRANCH Syntax Operation Emulation Description Status Bits Example MSP430 Instructions Branch to destination in lower 64K address space BR dst dst gt PC MOV dst PC An unconditional branch is taken to an address anywhere in the lower 64K address space All source addressing modes can be used The branch instruction is a word instruction Status bits are not affected Examples for all addressing modes are given BR EXEC _ Branch to label EXEC or direct branch e g 0A4h Core instruction MOV PC PC BR EXEC Branch to the address contained in EXEC Core instruction MOV X PC PC Indirect address BR amp EXEC _ Branch to the address contained in absolute address EXEC Core instruction MOV X 0 PC Indirect address BR R5 Branch to the address contained in R5 Core instruction MOV R5 PC Indirect R5 BR R5 Branch to the address contained in the word
120. ted V Not affected OSCOFF CPUOFF and GIE are not affected Bits 15 and 13 of R5 16 bit data are set to one R5 19 16 0 BIS A000h R5 Set R5 bits A table word pointed to by R5 20 bit address is used to set bits in R7 R7 19 16 0 BIS W R5 R7 A table byte pointed to by R5 20 bit address is used to set bits in Port1 R5 is incremented by 1 afterwards Set bits in R7 BIS B R5 amp P10OUT Set I O port P1 bits R5 1 16 Bit MSP430X CPU 4 67 MSP430 Instructions BITLW BIT B Syntax Operation Description Status Bits Mode Bits Example Example Example Test bits set in source word in destination word Test bits set in source byte in destination byte BIT src dst or BIT W src dst BIT B src dst src and dst The source operand and the destination operand are logically ANDed The result affects only the status bits in SR Register Mode the register bits Rdst 19 16 W resp Rdst 19 8 B are not cleared N Set if result is negative MSB 1 reset if positive MSB 0 Zz Set if result is zero reset otherwise C Set if the result is not zero reset otherwise C not Z V Reset OSCOFF CPUOFF and GIE are not affected Test if one or both of bits 15 and 14 of R5 16 bit data is set Jump to label TONI if this is the case R5 19 16 are not affected BIT C000h R5 JNZ TONI Test R5 15 14 bits At least one bit is set in R5 Both bits are reset A
121. terrupt BIC 8 SR EINT Enable interrupt BIS 8 SR INC B dst Increment dst by 1 ADD B 1 dst INCD B dst Increment dst by 2 ADD B 2 dst INV B dst Invert dst XOR B 1 dst NOP No operation MOV R3 R3 POP dst Pop operand from stack MOV SP dst RET Return from subroutine MOV SP PC RLA B dst Shift left dst arithmetically ADD B dst dst RLC B dst Shift left dst ADDC B dst dst logically through Carry SBC B dst Subtract Carry from dst SUBC B 0 dst SETC Set Carry bit BIS 1 SR SETN Set Negative bit BIS 4 SR SETZ Set Zero bit BIS 2 SR TST B dst Test dst CMP B 0 dst compare with 0 16 Bit MSP430X CPU MSP430 and MSP430X Instructions MSP430 Instruction Execution The number of CPU clock cycles required for an instruction depends on the instruction format and the addressing modes used not the instruction itself The number of clock cycles refers to MCLK Instruction Cycles and Length for Interrupt Reset and Subroutines Table 4 8 lists the length and the CPU cycles for reset interrupts and subroutines Table 4 8 Interrupt Return and Reset Cycles and Length Execution Time Length of Action MCLK Cycles Instruction Words Return from interrupt RETI 3t 1 Return from subroutine RET 3 1 Interrupt request service cycles 5t needed before 1 instruction WDT reset 4 Reset RST NMI 4 7 t The cycle count in MSP430 CPU is 5 The cycle count in MSP430 CPU is 6 16 Bit MSP430X CPU
122. the BCD result is too large address word gt 99999h word gt 9999h byte gt 99h reset otherwise V Undefined OSCOFF CPUOFF and GIE are not affected Decimal 10 is added to the 20 bit BCD counter DECCNTR located in two words DADDX A 10h amp DECCNTR Add 10 to 20 bit BCD counter The eight digit BCD number contained in 20 bit addresses BCD and BCD 2 is added decimally to an eight digit BCD number contained in R4 and R5 BCD 2 and R5 contain the MSDs CLRC Clear carry DADDX W BCD R4 Add LSDs DADDX W BCD 2 R5 Add MSDs with carry JC OVERFLOW Result gt 99999999 go to error routine Z Result ok The two digit BCD number contained in 20 bit address BCD is added decimally to a two digit BCD number contained in R4 CLRC Clear carry DADDX B BCD R4 Add BCD to R4 decimally R4 000ddh 16 Bit MSP430X CPU DECX A DECX W DECX B Syntax Operation Emulation Description Status Bits Mode Bits Example Extended Instructions Decrement destination address word Decrement destination word Decrement destination byte DECX dst DECX dst DECX B dst dst 1 gt dst SUBX A 1 dst SUBX 1 dst SUBX B 1 dst or DECX W dst The destination operand is decremented by one The original contents are lost N Set if result is negative reset if positive Z Set if dst contained 1 reset otherwise C Reset if dst contained 0 set otherwise V Set if an arithmetic overflow oc
123. tive src gt dst reset if positive src dst Z Set if result is zero src dst reset otherwise src dst C Set if there is a carry from the MSB reset otherwise V Set if the subtraction of a negative source operand from a positive des tination operand delivers a negative result or if the subtraction of a posi tive source operand from a negative destination operand delivers a positive result reset otherwise no overflow OSCOFF CPUOFF and GIE are not affected Compare word EDE with a 16 bit constant 1800h Jump to label TONI if EDE equals the constant The address of EDE is within PC 32 K CMP 01800h EDE Compare word EDE with 1800h JEQ TONI EDE contains 1800h Not equal A table word pointed to by R5 10 is compared with R7 Jump to label TONI if R7 contains a lower signed 16 bit number R7 19 16 is not cleared The address of the source operand is a 20 bit address in full memory range CMP W 10 R5 R7 Compare two signed numbers JL TONI R7 lt 10 R5 R7 gt 10 R5 A table byte pointed to by R5 20 bit address is compared to the value in output Port1 Jump to label TONI if values are equal The next table byte is addressed CMP B R5 amp P10UT Compare P1 bits with table R5 1 JEQ TONI Equal contents Not equal 16 Bit MSP430X CPU 4 75 MSP430 Instructions DADCL W DADC B Syntax Operation Emulation Description Status Bits Mode Bits Example Example
124. truction as listed in Table 4 16 Restricting the addressing modes removes the need for the additional extension word op code improving code density and execution time Address instructions should be used any time an MSP430X instruction is needed with the corresponding restricted addressing mode Table 4 16 Address Instructions Operate on 20 bit Registers Data Status Bits Mnemonic Operands Operation VN ZC ADDA Rsrc Rdst Add source to destination ae Re imm20 Rdst register MOVA Rsrc Rdst Move source to destination imm20 Rdst z16 Rsrc Rdst EDE Rdst amp abs20 Rdst Rsrc Rdst Rsrc Rdst Rsrc Z16 Rdst Rsrc amp abs20 CMPA Rsrc Rdst Compare source to destina imm20 Rdst tion register SUBA Rsrc Rdst Subtract source from des SR CI imm20 Rdst tination register 4 54 16 Bit MSP430X CPU MSP430X Extended Instructions MSP430X Instruction Execution The number of CPU clock cycles required for an MSP430X instruction depends on the instruction format and the addressing modes used not the instruction itself The number of clock cycles refers to MCLK MSP430X Format ll Single Operand Instruction Cycles and Lengths Table 4 17 lists the length and the CPU cycles for all addressing modes of the MSP430X extended single operand instructions Table 4 17 MSP430X Format II Instruction Cycles and Length Execution Cycles Length of Instruction Words instr cti n Rn Rn Rn N X Rn EDE a
125. ts due to overflow the decision made by the JL instruction is correct Status bits are not affected OSCOFF CPUOFF and GIE are not affected If byte EDE contains a smaller signed operand than byte TONI continue at Label1 The address EDE is within PC 32 K CMP B amp TONI EDE lIs EDE lt TONI JL Label1 Yes No TONI lt EDE If the signed content of R6 is less than the memory pointed to by R7 20 bit address the program continues at Label Label5 Data and program in full memory range CMP R7 R6 Is R6 lt R7 JL Label5 Yes go to Label5 No continue here If R5 lt 12345h signed operands the program continues at Label2 Data and program in full memory range CMPA 12345h R5 Is R5 lt 12345h JL Label2 Yes 80000h lt R5 lt 12345h No 12344h lt R5 lt 7FFFFh 4 88 16 Bit MSP430X CPU JMP Syntax Operation Description Status Bits Mode Bits Example Example MSP430 Instructions Jump unconditionally JMP label PC 2 x Offset PC The signed 10 bit word offset contained in the instruction is multiplied by two sign extended and added to the 20 bit program counter PC This means an unconditional jump in the range 511 to 512 words relative to the PC in the full memory The JMP instruction may be used as a BR or BRA instruction within its limited range relative to the program counter Status bits are not affected OSCOFF CPUOFF and GIE are not affected The byte
126. uction N Not affected Z Reset to 0 C Not affected V Not affected OSCOFF CPUOFF and GIE are not affected The zero bit in the status register is cleared CLRZ Indirect Auto Increment mode Call a subroutine at the 16 bit address con tained in the word pointed to by register R5 20 bit address and increment the 16 bit address in R5 afterwards by 2 The next time the software uses R5 as a pointer it can alter the program execution due to access to the next word ad dress in the table pointed to by R5 CALL R5 Start address at R5 R5 2 Indexed mode Call a subroutine at the 16 bit address contained in the 20 bit address pointed to by register R5 X e g a table with addresses starting at X The address is within the lower 64 KB X is within 32 KB CALL X R5 Start address at R5 X z16 R5 4 74 16 Bit MSP430X CPU CMP W CMP B Syntax Operation Description Status Bits Mode Bits Example Example Example MSP430 Instructions Compare source word and destination word Compare source byte and destination byte CMP src dst or CMP W src dst CMP B src dst not src 1 dst or dst src The source operand is subtracted from the destination operand This is made by adding the 1 s complement of the source 1 to the destination The result affects only the status bits in SR Register Mode the register bits Rdst 19 16 W resp Rdst 19 8 B are not cleared N Set if result is nega
127. uctions Register Mode Extension Word The register mode extension word is shown in Figure 4 25 and described in Table 4 11 An example is shown in Figure 4 27 Figure 4 25 The Extension Word for Register Modes 15 12 3 0 11 10 9 8 7 6 5 4 Table 4 11 Description of the Extension Word Bits for Register Mode Bit Description 15 11 Extension word op code Op codes 1800h to 1FFFh are extension words 10 9 Reserved ZC Zero carry bit 0 The executed instruction uses the status of the carry bit C 1 The executed instruction uses the carry bit as 0 The carry bit will be defined by the result of the final operation after instruction execu tion Repetition bit 0 The number of instruction repetitions is set by extension word bits 3 0 1 The number of instructions repetitions is defined by the value of the four LSBs of Rn See description for bits 3 0 A L Data length extension bit Together with the B W bits of the following MSP430 instruction the AL bit defines the used data length of the instruction A L B W Comment 0 O Reserved 0 1 20 bit address word 1 0 16 bit word 1 1 8 bit byte 5 4 Reserved 3 0 Repetition Count 0 These four bits set the repetition count n These bits contain n 1 1 These four bits define the CPU register whose bits 3 0 set the number of repetitions Rn 3 0 contain n 1 16 Bit MSP430X CPU 4 45 MSP430X Extended Instructions Non Register Mode Extension Word The
128. uto incremented by 1 R6 19 8 0 ADDC B R5 R6 JNC TONI Add table byte C to R6 R5 1 Jump if no carry Carry occurred 4 64 16 Bit MSP430X CPU ANDLW AND B Syntax Operation Description Status Bits Mode Bits Example Example MSP430 Instructions Logical AND of source word with destination word Logical AND of source byte with destination byte AND src dst or AND W src dst AND B src dst src and dst gt dst The source operand and the destination operand are logically ANDed The result is placed into the destination The source operand is not affected N Set if result is negative MSB 1 reset if positive MSB 0 Z Set if result is zero reset otherwise C Set if the result is not zero reset otherwise C not Z V Reset OSCOFF CPUOFF and GIE are not affected The bits set in R5 16 bit data are used as a mask AA55h for the word TOM located in the lower 64 K If the result is zero a branch is taken to label TONI R5 19 16 0 MOV AA55h R5 Load 16 bit mask to R5 AND R5 amp TOM TOM and R5 gt TOM JZ TONI Jump if result O Result gt 0 or shorter AND AA55h amp TOM TOM and AA55h gt TOM JZ TONI Jump if result 0 A table byte pointed to by R5 20 bit address is logically ANDed with R6 R5 is incremented by 1 after the fetching of the byte R6 19 8 0 AND B R5 R6 AND table byte with R6 R5 1 16 Bit MSP430X CPU 4 65 MSP430 Instructions
129. xample BISX A R5 R6 This instruction logically ORs the 20 bit data contained in R5 with the 20 bit contents of R6 The extension word contains the A L bit for 20 bit data The instruction word uses byte mode with bits A L B W 01 The result of the instruction is Before After Address Register Address Register Space Space 21036h R5 AA550h 21036h 21034h 21032h PC R5 AA550h R6 11111h 21034h R6 BB551h 21032h AA550h or 11111h BB551h 16 Bit MSP430X CPU 4 17 CPU Registers 4 4 2 Indexed Mode The Indexed mode calculates the address of the operand by adding the signed index to a CPU register The Indexed mode has three addressing possibilities Lj Indexed mode in lower 64 KB memory Li MSP430 instruction with Indexed mode addressing memory above the lower 64 KB memory J MSP430X instruction with Indexed mode Indexed Mode in Lower 64 KB Memory If the CPU register Rn points to an address in the lower 64 KB of the memory range the calculated memory address bits 19 16 are cleared after the addition of the CPU register Rn and the signed 16 bit index This means the calculated memory address is always located in the lower 64 KB and does not overflow or underflow out of the lower 64 KB memory space The RAM and the peripheral registers can be accessed this way and existing MSP430 software is usable without modifications as shown in Figure 4 15 Figure 4 15 Indexed Mode in Lower 64 KB Lower 64 KB Rn
130. xplicitly they act as source only registers Constant Generator Expanded Instruction Set The RISC instruction set of the MSP430 has only 27 instructions However the constant generator allows the MSP430 assembler to support 24 additional emulated instructions For example the single operand instruction CLR dst is emulated by the double operand instruction with the same length MOV R3 dst where the 0 is replaced by the assembler and R3 is used with As 00 INC dst is replaced by ADD 0 R3 dst 16 Bit MSP430X CPU 4 11 CPU Registers 4 3 5 The General Purpose Registers R4 to R15 The twelve CPU registers R4 to R15 contain 8 bit 16 bit or 20 bit values Any byte write to a CPU register clears bits 19 8 Any word write to a register clears bits 19 16 The only exception is the SXT instruction The SXT instruction extends the sign through the complete 20 bit register The following figures show the handling of byte word and address word data Note the reset of the leading MSBs if a register is the destination of a byte or word instruction Figure 4 10 shows byte handling 8 bit data B suffix The handling is shown for a source register and a destination memory byte and for a source memory byte and a destination register Figure 4 10 Register Byte Byte Register Operation Register Byte Operation Byte Register Operation High Byte Low Byte High Byte Low Byte 19 1615 87 0 Register Memory Memory Register Memo
131. yte R12 points to The carry of the previous instruction is used The address of CNT is in lower 64 K SUBC B amp CNT 0 R12 Subtract byte CNT from R12 4 108 16 Bit MSP430X CPU SWPB Syntax Operation Description Status Bits Mode Bits Example MSP430 Instructions Swap bytes SWPB dst dst 15 8 lt dst 7 0 The high and the low byte of the operand are exchanged PC 19 16 bits are cleared in register mode Not affected OSCOFF CPUOFF and GIE are not affected Exchange the bytes of RAM word EDE lower 64 K MOV 1234h amp EDE 1234h gt EDE SWPB amp EDE 3412h gt EDE Figure 4 42 Swap Bytes in Memory Before SWPB 15 8 7 0 After SWPB 15 8 7 0 Low Byte High Byte Figure 4 43 Swap Bytes in a Register Before SWPB 19 16 15 8 7 0 After SWPB 19 16 15 8 7 0 16 Bit MSP430X CPU 4 109 MSP430 Instructions SXT Syntax Operation Description Status Bits Mode Bits Example Example Extend sign SXT dst dst 7 gt dst 15 8 dst 7 dst 19 8 Register Mode Register Mode the sign of the low byte of the operand is extended into the bits Rdst 19 8 Rdst 7 0 Rdst 19 8 000h afterwards Rdst 7 1 Rdst 19 8 FFFh afterwards Other Modes the sign of the low byte of the operand is extended into the high byte dst 7 0 high byte 00h afterwards dst 7 1 high byte FFh afterwards N Set if result is negative reset otherwise Z Set if result is zer

MSP430x4xx Family User's Guide (Rev. G - webwww03

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