5256VA Demoboard User Manual Version 1.1
Contents
1. CAUTION Do not feed an external clock signal to X6 pind with both Y3 and Y4 set You will probably kill your clock source the onboard oscillator or both CAUTION Do not feed external 2 5V with Jumpers Y1 and Y2 both set Set Y1 for VCCIO 3 3V AN from on board supply or set Y2 for VCCIO 2 5V connect a 2 5V 30mA supply to X6 Pin 11 9 Accessories stuff you may need You need some kind of software to produce the JEDEC Files for the ispLSI5256VA At the time this manual is written a starter software is available free of charge from Lattice Semiconductors homepage www latticesemi com Software which supports VHDL or Verilog can be purchased for a few hundred dollars which is a good investment With any Software you buy from Lattice you get a download cable The download cable can be purchased separately for less than 100 at any Lattice Representative or Distributor The order code is PDS4102 DL2 10 Application Examples Support Application examples for this demoboard can be downloaded from our homepage www bosshard elektronik ch If you do an interesting funny useful strange or smart application we would be happy to receive a copy Please include your approval or denial to post your application on our homepage Customized versions of the Demoboard are possible e ispLSI5256VA in BGA208 with different soeed grades e ispLSI5384VA in BGA208 all available speed grades e different frequenci2. 5 ms 36 me ia Sta A ae E 3 e 40 ka X3 an Device Pin Function VCC 2 GND Zo ER iS A S A A Table 4 X3 Pin connections Bosshard Elektronik 26 GND 27 J os 2 as 2 30 Bi E A lo EEE AR A pa vc ae gt GND EAS May 200 0 www bosshard elektronik ch ispLSI5256VA Demoboard User Manual May 2000 X4 Pin Device Pin Function X4 Pin Device Pin Function Table 5 X4 Pin connections 7 JTAG Interface The JTAG interface can be used for In System Programming and for Boundary Scan Test X5 corresponds to the standard Lattice Download cable pinout see table 6 After programming you should reset the device to ensure proper operation For details on In System Programming and Boundary Scan Test please refer to the Lattice documentation or the Lattice homepage www latticesemi com Device Pin Function VCC TDO TDI TMS GND TCK 1 2 3 4 5 6 7 8 Table 6 X5 Pin connections JTAG Port Bosshard Elektronik 7 www bosshard elektronik ch ispLSI5256VA Demoboard User Manual May 2000 8 Jumper settings Here you find a brief summary of the jumper settings Function Factory setting connects VCCIO Pin to VCC 3 3V connects VCCIO Pin to X6 Pin 11 connects CLK2 Pin to on board Oscillator connects CLK2 Pin to X6 Pin 5 pulls TOE I O O to GND Table 7 Jumper settings
3. BosSSHARD ELEKTRONIK WWW BOSSHARD ELEKTRONIK CH ispLSI5256VA Demoboard User Manual Version 1 1 We are aware of the fact that very few designers read manuals Nevertheless we recommend to read this manual before starting to work with the demoboard A lot of FAQ s are answered here Copyright 1999 Bosshard Elektronik All brand or product names are trademarks or registerd trademarks of their respective holders The specifications and information herein are subject to change without notice Bosshard Elektronik Undelstrasse 48 CH 8493 Saland Switzerland May 2000 Tel 41 0 52 394 13 13 Fax 41 0 52 394 13 14 www bosshard elektronik ch ispLSI5256VA Demoboard User Manual May 2000 0 Kit Contents Please check the contents of the box when receiving the demoboard It should contain the following items e ispLSI5256VA Demoboard e Application example description e This Manual e The schematic of the board We do not ship any software with the board The application examples can be downloaded from our website www bosshard elektronik ch 1 Introduction This demoboard was designed to give an easy access to the features of the Lattice 5kVA Family for design engineers The popularity of this CPLD family is growing rapidly Please refer to Lattice documentation or homepage for more details on the architecture and capabilities of this device family The board can be used for prototyping as well as for design verific
4. ation performance tests education purposes evaluation of the 5kVA CPLD family or simply to play around with it and have some fun 2 Features e Equipped with an ispLSI5256VA 100LB208 Translation In System programmable 3 3V CPLD with 256 Macrocells specified to run at max 100MHz in a BGA208 package On board 3 3V voltage regulator On board oscillator running at 4MHz All device pins are available on standard single or double row headers Prototyping area for your own circuitry In System programmable via JTAG Port Use the Lattice Download Cable for direct download from the PC parallel port to the demoboard 4 Digit LED display User switches connected to CPLD e 4User Keys e Reset Key e 8 DIP switches Bosshard Elektronik 2 www bosshard elektronik ch ispLSI5256VA Demoboard User Manual May 2000 3 Board Layout Use figure 1 to locate the different components on the board GND 5Vin f VCC out X3 ial 4 SW DI D2 D3 D4 O http www bosshard elektronik ch Evaluationboard 5256VA lo o o o O 12345678 TA1 TA2TA3 TA4 Power Reset cole Y A foe ispLSI f b x4 E 5256VA e c i a P Segment allocation for D1 D4 X5 X6 Figure 1 ispLSI5256VA Demoboard Layout 4 Power Supply The board needs a 5 Volt 1A power supply The on board regulator generates the needed 3 3V which is available at X7 for use in other peripherals Th
5. e power consumption of the ispLSI5256VA depends mainly on your JEDEC file and the clock frequency This varies the current available from the 3 3V output but even in worst case you can draw 100mA The onboard voltage regulator is overcurrent and overtemperature protected The ispLSI5256VA supports 2 5V VCCIO which need to be supplied externally Jumper Y1 connects VCCIO to the 3 3V supply Jumper Y2 connects the VCCIO device pin to X6 Pin 11 REMARK To clarify the VCCIO issue It is optional to supply 2 5V for VCCIO and is only needed when you want to interface to 2 5V components from on board supply or set Y2 for VCCIO 2 5V connect a 2 5V 30mA supply to X6 A CAUTION Do not feed external 2 5V with Jumpers Y1 and Y2 both set Set Y1 for VCCIO 3 3V Pin 11 Bosshard Elektronik 3 www bosshard elektronik ch ispLSI5256VA Demoboard User Manual May 2000 5 Clocks Output Enables and Reset Preset All clocking options available from the ispLSI5256VA are usable on this board For test applications an on board oscillator running at 4MHz is connected via jumper Y3 to the CLK2 pin Figure 3 shows the clock structure of the device You can see here why we chosen CLk2 for the onboard clock it s the most flexible one because it can be used inverted internal clock line CLK2 and non inverted internal clock line CLK3 at the same time In case the clock signal is used in product terms the CLK2 pin is configured as I O pin by
6. es for the on board oscillator e customized silk screen Please contact sales bosshard elektronik ch for pricing lead times Support for any demoboard related issues can be obtained by contacting support bosshard elektronik ch Please do not request our support for issues concerning design software or the ispLSI5256VA device This is supported by the Lattice Representatives or Distributors in your area Bosshard Elektronik 8 www bosshard elektronik ch ispLSI5256VA Demoboard User Manual May 2000 11 Specifications Parameter NOMINAL Supply Voltage 5 0 Current Consumption VCCIO optional 2 5 Current needed for VCCIO Pin Voltage available at VCCout X7 3 3 Current available from VCCout Operating Temperature Physical Dimension 12 Additional comments Our boards are much better than our english 100 x 160 Any suggestions for improvements on this document are highly welcome Please email to demoboard bosshard elektronik ch Bosshard Elektronik www bosshard elektronik ch
7. software CLKO CLKO CLK 1 CLK1 IO CLK 2 m To GRP CLK2 CLK3 IO CLK 3 i To GAP Figure 3 ispLSI5256VA clock structure Jumper Y4 connects the CLK2 pin to X6 pin 5 If you want to feed an external clock to CLK2 or use it as I O set jumper Y4 and remove jumper Y3 CAUTION Do not feed an external clock signal to X6 pind with both Y3 and Y4 set You will probably kill your clock source the onboard oscillator or both All connections for X6 are listed in table1 Device pin Remark Use for fast clock CLK2 lO 89 Connected via Y4 to X6 via Y3 to onboard osc CLK3 lO 98 GSET GRST On board RESET button pulls this pin to GND a 10kQ pull up is connected to this pin TOE 10 0 Jumper Y5 pulls this pin to GND GOEO General Output Enable 0 GOE1 General Output Enable 1 VCCIO Connected via Y2 GND Table 1 X6 connections Bosshard Elektronik 4 www bosshard elektronik ch ispLSI5256VA Demoboard User Manual May 2000 6 I O Connections LED Switches and pushbuttons All 1 O pins are connected to the headers The connections are listed in tables 2 3 4 and 5 Every I O can be selected to run at VCC 3 3V or VCCIO 2 5V externally supplied to VCCIO Pin by software Choosing I Os to run at VCCIO with a floating VCCIO Pin is not specified in the ispLSI5256VA datasheet and will show an unpredictable behavior HINT Inputs that run on 3 3V can be driven with a 5V signal O
8. utputs are 5V TTL compatible To achieve 5V CMOS compatible output levels select the open drain option for the output in the software and add an external pull up The board features four 7 Segment LED displays with decimal point dp and colon col The LED segments are ON when the device pin is driven LOW Figure 4 shows the segment allocation a col O SES Led AE Odp Figure 4 LED display segment allocation The switches SW1 SW8 and the pushbuttons TA1 TA4 pull the corresponding l O pin to GND when switched on or pushed A 10kQ pull up resistor is connected to all of these signals to ensure a logic high on the pin when the switch is in off position or the pushbutton is not pressed When connecting external signals to X1 pins 4 19 please take in account these pull ups When connecting external signals to X4 your signal source has to be able to sink approx 7 mA current through LED segments to drive logic low X1 au Device Pin Function X1 Pin Device Pin Function VCC 26 Table 2 X1 Pin connections Bosshard Elektronik 5 www bosshard elektronik ch is LSI5256VA Demoboard User Manual X2 fm Device Pin Function VCC gp DE EEN ee CT RA ERAN SS 6 m E E Se ee A eee pe ee vos ee 0 ene TT EA A EA ee IET TRU IN 44 pmp 5 O Table 3 X2 Pin connections 26 GND 27 Re E EPA E No gt 20 EM gt gt gt par AMA JE INNER YC e asf vc pa pp oD
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