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ispDesignExpert User Manual

1. 02 220005 137 Running Functional Timing SSH E STD dax ace o E EOERCR COR RC COCRCOI RRCRECEDE 4 137 Showing the Waveforms in the Waveform Viewer 00 2000eeeeeaee 139 HDL Cross Probing for IspLSI GAL Designs nnna kranke Rr E RR RE Rn 140 MIAN EO T M IO 140 ispDesignExpert User Manual 7 Running Stand alone Lattice Logic Simulator 000020 cee eee 141 Equation Simulator for MACHIPBL iu cectucsdicivvebedeeetebedcewricsseudes ees 144 Ce ed ioa tho Ae acido dE eb ek ew pa dey RE RE Oe ER dol ee ee 144 Creating Test Vectors for Equation Simulator 0 cece eee 144 Running the Equation SIMIAN Las oca dodo o eaa Re eee d Ouid c E RR eed 144 The Simulator Model Ret I P pr DN 145 Controlling the Simulation Report lllliiilelsielllell seen 146 Displaying the Waveforms in the Waveform Viewer lllls elles 147 JEEG Sy ud op EE E d Rhee OC ORE e dedo dede e OCC IUE ee net d eiae 148 Simulating B JEDEC FIle Lu s da dci eR eod poe f p RR ee eR CRGO op d Re eae o ege 148 Viewing the Simulation Waveform i issososs Rak kh no o khen awe 148 Fandom SII EI su uices ad dq ER RUeU Edna bk wraPWqdedeRbetusaskedcd bdd edi 149 Generating Test OQUTENIE La eu uen warn sinana anue ded ud eur a sah ee dra ed id 149 Manually Create VHDL Test Bench or Verilog Test Fixture 150 Create VHDL Test Bench or Verilog Test Fixture U
2. Figure 6 6 Tpd Table ispDesignExpert User Manual 158 Timing Analyzer for ispLSI Pop Up Menus from the Timing Tables When you click the right mouse button from the signal name row or column headers in the Timing Matrix Table the following commands are available m Sort Rearranges the table so the values in the column with the cursor are arranged from lowest to highest or in alphabetical order as appropriate m Show Timing Data Shows the timing data for the entire row or column m AddSignal When you select the command a dialog box displays so you can enter the name of a signal you want to add to the table m Remove Signal When you select this command the signal name where the cursor is located is removed from the table When you click the right mouse button on a cell in the Timing Matrix Table the following commands are available m Show Timing Data Shows the timing data for that cell m Display Timing Path Cascades to show Longest Path Shortest Path and Both Paths Choose one of these options to have the path display in the Connectivity window of the Physical Viewer The Physical Viewer tool bar icon changes to show you are in Timing Mode m Report Timing Path In a new window displays the timing path as a text report When you click the right mouse button on the signal name in the Frequency Table the Display Timing Path and Report Timing Path commands are available When you click th
3. Precedence Design Attribute 1 BFM LOCK LOCK BFM LOCK GRP LXOR2 OPENDRAIN OPTIMIZE OUTDELAY PRESERVE PROTECT PULL RESERVE PIN SLOWSLEW VOLTAGE XOR SAP EAP SNP ENP SCP ECP SLP ELP STP ETP c1 AJOJN CLK CRIT GROUP REGTYPE ispDesignExpert User Manual 101 MACH Design Attributes MACH Design Attributes MACH Design Attributes applied to MACH designs only in ispDesignExpert affect how ispDesignExpert implements your MACH designs After you import these attributes the Fitter will use as local design assignments in the design implementation process Design Attributes can be set in a schematic or an ABEL HDL file Assigning MACH Design Attributes in Project Sources In Schematics Attributes in schematics are used to describe the characteristics or properties belonging to or associated with a symbol pin or net Attributes only apply to describing characteristics in schematics There are two types of attributes used in the Schematic Editor symbol and net Symbol attributes describe features related to a whole symbol Symbol attributes usually apply only to the symbol on which they appear Net attributes describe characteristics associated with nets Every attribute consists of four components name value modifier and window You can assign either symbol or net attributes to a schematic via the Symbol Attribute Editor or Net Attribute Editor dialog box of the Schematic Edi
4. iapiacignEnpart Fitter Repert File Versios 0 0 ejCapyright Lattice Z2immircndactar 1999 Di iaeprODLS p apeyacexamples HACH PFAL n Tue Now 23 13 42 73 1999 HdAn 322432 A4ELCC Figure 4 24 Fitter Report ispDesignExpert User Manual 135 Chapters Design Verification The ispDesignExpert provides you a full simulation environment The Lattice Logic Simulator is a flexible tool that helps you verify the operation and logic functionality of your ispLSI or GAL design The Equation Simulator enables you to verify a MACH or PAL design The ispDesignExpert also has an integration interface with ModelSim providing you easy access to VHDL and Verilog HDL simulation This chapter covers the following information m Lattice Logic Simulator for ispLSI GAL m Equation Simulator for MACH PAL m JEDEC Simulation for PAL GAL m ModelSim Simulation ispDesignExpert User Manual 136 Lattice Logic Simulator for ispLSI GAL Lattice Logic Simulator for ispLSI GAL Overview Lattice Logic Simulator is the Lattice proprietary gate level simulation tool so that you can run both Functional Simulation and Timing Simulation Functional Simulation pre route design verification occurs before the design has been fitted and routed It helps you find logical or coding error in early design cycle Timing simulation post route simulation confirms that your design is compatible with the timing and propagation delays that exist in a specific dev
5. About the Project Navigator About the Project Navigator nput pin TSELE FIH nF AST nH LD ASL TEST rOLOH AH VH HE Le Using the Project Navigator you can select all the source components for a design as well as specification documents and test files and assemble them into one project file The Project Navigator also helps you keep track of all the processing steps necessary to move the design from the conceptual stage through to implementation of a programmable device When you switch the target device the Project Navigator automatically changes the design flow and processes to one that is appropriate for the new target device The Project Navigator also associates all the tools needed for a particular design step For example for HDL source files the Project Navigator associates the Text Editor and HDL synthesis tools for schematic sources the Project Navigator associates the Schematic Editor Symbol Editor Hierarchy Navigator Library Manager tools and schematic compiling tools and for waveform stimulus source files the Project Navigator associates Waveform Editor Waveform Viewer and Lattice Logic Simulator Furthermore the Project Navigator keeps track of preferences for you automatically setting options that work for most systems until you want to modify the options yourself Soke meadlic Eanair COC MOF Sbp mii E EM Wew Add Iove ORC Deion phia Aus Delij a sae EE sa PPP B cloc
6. Figure 3 47 Lower level VHDL Module mux2x1 vhd vhd ispDesignExpert User Manual 79 Hierarchical Design Hierarchical Verilog HDL Design The following steps outline how to specify a lower level VHDL module mux2x1vhd vhd and a lower level schematic mux2x1 sch in an upper level schematic mux4x1 sch Figure 3 44 shows a schematic block and a VHDL module instantiated in another schematic B epeng pert Project Maiga DSPTOOLSIISPS YS LAMP In x Ede bee Source hncess Options thiedow Tools pb Di fal See BE spit SITDITEE 125L 144 igi et ped EDIF Mailis T i Constrnini Manage Ejmux zl mux x1 sch D Compile Design Spatial eh i JEDEC Fila DCompiler Report i Timing Anobywin K Timmy Explorar dj Mmamum Frequency Repor dry diui Rapai Tpd Rapar n y rn Aepor B Pipaical Wiirear RSF Daisy Chain Download Tinuhkeriick ta bin am A fand deve Deutin rick En riam m fre bl or elect len Piet baton sianhe picos Eakecitha P mperbez bubon to rlertiie property Mew pen Sj 1s Ready Figure 3 48 Hierarchical Schematic Verilog HDL Design To instantiate a lower level schematic and a lower level VHDL module in a schematic 1 In the Project Navigator choose Window Schematic Editor to open the Schematic Editor The Schematic Editor opens with a new sheet This schematic is going to be the top level schematic Next you will place a Block symbol a functional block in the schematic that will represent a more det
7. Figure 3 56 New Block Symbol Dialog Box A symbol is added to your Local library and the symbol is attached to your cursor Place the symbol in the proper position of the symbol you have already added Click with the right mouse button to place the symbol and to display the Symbol Libraries dialog box Figure 3 55 again Close the dialog box Complete the top level schematic by adding the necessary wires net names and I O Markers to finish the design Refer to the instructions for adding nets and symbols from the Schematic Entry User Manual if you need assistance When you finish perform a consistency check and create a matching symbol Save your design and exit the Schematic Editor To verify the correctness and consistency of your top level design you can move through the design levels using the Hierarchy Browser or the Hierarchy Navigator feature A number of editing functions are available through the Navigator In the Sources in Project list of the ispDesignExpert Project Navigator window highlight the top level schematic sch In the Processes list double click on Hierarchy Browser or Navigate Hierarchy The Hierarchy Browser and the Hierarchy Navigator window appears with your top level design You can traverse the design hierarchy by clicking on the hierarchy tree shown in the Hierarchy Browser If a relevant module of the selected instance is defined in a schematic source file it will be opened in the Hierarchy Nav
8. PIBISEB 5 prb Fr d WO RR Hc Vai ada o olo C eb pt RU OC e oltra 9 What is in this Manual 2c csccececceecbenscceeoddedeee et a 10 Where to Look for Information sick bs ooo hoe hee CR C ee RR eee eee 10 Doc mentalion COnVemi NS 66 64 ee eens beer OE HP EGER RC ee Kober RE ERR es 11 Related Documentation pese hea eee be OR RC IER EKG Oe Re ede Sree ES 12 Chapter T Introduction 2uuoikxesaawdod deae d bee REOR EE CI eR RR CALI eee dn 13 Starting the ispDesignExpert Project Navigator 0 0 0 cece eens 14 Crealimg a New Projeti pu had Fd RC ei DUO EO dn dole EE ERR ER OR CRGO o a de TR ER 15 BU Your Projecta Ts add dE CIE CO ER See Ce EC Re RE d Cet 16 mponina Projoct SOURCES a ua nsdn ener ber nese dened oud ce EdEdA RS PIeRAdaSAE 17 Targeting the Design to a Device ccc ecceen ci cede es de Ph bbs Ge botiwitags dase se 18 aite ptg c EPI mem 20 vew PISO PMID ddr d Ooo he d d ode OCC Ue Rl dO ab eR d doe EC d KR eG dial dede 21 Delete the Project Files su aco eh ehh eS ed HORACE e deo fol oa Ra o Qe d 22 Chapter 2 Project Management L sseeuuueeesss 23 About the Project Navigator nao eed eq tmm rim ala RE HE wadna ee aa a REA A 24 Project Navigator Screen 0 00 eee eee 25 A EE PM MT 26 DOSE BENE accesos d dee OER EE RU dea del dd d END EA Klee dl e E GR 26 jc d Dp 26 UCSF P PEMEPTCC O0K OUS Mnr rrrre 26
9. qnn seg abl EJPRESCILEB pensrir nhi a Compile Panigr igi JEDEC File fom pater Heport n Tamang Annbyxsit Timing Explore Wd rocimam Freruescy Hepnor 8 y Sate py Hoki agent Diced edb the d m is Ihas tid Dr sakin ha Eist bution lo plat the procs Selurt fia Propeta bion tn sect thes proper Bec ron osea gern Bisucenir axccatr abh Dloubkretch to chiiis a dfar dica Hee Onen Ready Figure 3 54 ispDesignExpert Project Navigator 2 Add the symbol for the schematic you created earlier Select Add Symbol The Symbol Libraries dialog box appears with the Local library selected The symbols display in the Symbols text box Figure 3 55 Select the symbol you need to add and place it on your schematic ispDesignExpert User Manual 87 Mixed Entry Design ocho E diinr jniedi Sheet 1 Ae Eom uw Adi Toi DRC Opiom Hab Des ABa a zu C a Bi se s E 4 Symbol Enter Hame of Symbol Figure 3 55 Schematic Editor with Symbol Libraries Dialog Box The next step is to create a top level symbol for your ABEL HDL design file A symbol can be created for any lower level design module as long as you know its interface In this way the actual ABEL HDL file for your design can be completed later 3 In the Schematic Editor select Add New Block Symbol In the New Block Symbol dialog box Figure 3 56 that appears type a name for the top level symbol in the Block Name text field relevan
10. Open menu item From the Project Navigator choose Window Text Editor ispDesignExpert User Manual 43 Schematic Design Entry Schematic Design Entry This section describes using a schematic as an entry for your design that supports ispLSI GAL MACH and PAL devices Add a Schematic to Your Design To add a schematic to your design you can either import a sch file or create a new schematic file in the Schematic Editor window To import a schematic to your design 1 Choose Source Import from the menu bar The Import File dialog box Figure 3 7 appears The project type Schematic ABEL is shown in the title bar of the dialog box letting you double check your project type before importing the source files Figure 3 7 Import File Dialog Box 2 In the Import File dialog box select the desired drive and path 3 Choose Schematic sch from the Files of type field and highlight the sch file you want to import from the File name field 4 Click OK The selected schematic file appears in the Sources of Project list of the Project Navigator The processes associated with the sch source vary from different devices and different project type you have chosen 5 Highlight the Schematic icon and note the processes associated with it Use the Schematic Editor or just double click the sch icon from the Sources list to view the schematic Figure 3 8 The Schematic Editor is available from the Windows Schemat
11. To complete your design you need to add net names and I O Markers When adding net names you will use a feature of the ispDesignExpert that allows you to add the net name and the net simultaneously I O Markers are special symbols required to indicate which signals represent pins The markers assume the name of the net they are attached to and are different from I O Pad symbols ispDesignExpert User Manual 47 Schematic Design Entry To add net names or I O markers 1 Select Add Net Name from the Schematic Editor menu bar The status bar at the bottom of the window will prompt you to enter the net name Type the net name and press Enter The Net Name will be attached to your cursor Move the cursor to the net where you want to add a name click and hold on the unconnected end of the net i e the red box at the left end of the net drag to the left and release This will place the net name and create a net simultaneously The net name should now be attached to the end of the net Repeat this procedure to add net names to other nets in the schematic Select Add I O Marker from the Schematic Editor menu bar The I O Markers dialog box appears Choose Input Move the cursor to the end of an input net between the end of the net and the net name and click An input marker appears with the net name inside of it Move to the next input and click again Repeat until all inputs have I O Markers 4 TIP To add all the input
12. are set e The Iconic option is enabled to run all DOS processes in an iconic DOS window e The Observe option enables you to run all DOS processes in a visible window which is useful for debugging If this option is not checked DOS engines are run minimized as icons e The Observe and Pause option allows you to run all DOS processes in a visible window and pause after each process This allows you to see program output before the DOS window is dismissed Three options Verbose Show if Warnings Occur and Show Always are set in the Auto make Log area This area specifies what type of information to record in the auto make log and when to display the log e The Verbose option is set to generate a verbose version of the log containing more detail on each processes s progress e The Show if Warnings Occur option is set to show the auto make log when Warnings are encountered e The Show Always option enables you to show the auto make log whenever an auto make process is started Observe and Observe and Pause options Refer to the Project Navigator online help for more information Cleaning Up a Project Before you archive the project directory you may want to delete non critical or intermediate files created during processing of a project This procedure avoids archiving unnecessary files m Todelete only intermediate files for the current project choose File Clean Up m
13. precedence of 101 processing 99 MACH 102 assigning in ABEL HDL 103 assigning in schematic 102 syntax in ABEL HDL 103 Design control properties ispLSI 51 Design entry ABEL HDL 40 EDIF 61 mixed Schematic and ABEL HDL 87 mixed Schematic and Verilog HDL 95 mixed Schematic and VHDL 94 Schematic 44 Verilog HDL 57 VHDL 53 Detailed Report 160 Device targeting 18 Device options ispLSI 125 ISP 125 ISP except Y2 125 Lowpower 126 Security 125 TOE AS O 126 Y1 as reset 126 Device selection 29 dialog box 29 E EDIF create for ispLSI 56 59 import mechanism for MACH PAL 66 import netlist 61 property files for MACH PAL 64 Effort ispLSI compiler property 120 Environment and configuration change 34 Equation simulation run 144 Equation Simulator for MACH PAL 144 simulation model 145 view 145 simulation report control 146 ispDesignExpert User Manual 171 F File names reserved 37 fMAX analysis type Performance Analyst 161 Force a process to run 34 Free all pin locks ispLSI compiler property 122 Frequency calculation from Timing Viewer 156 Frequency Table pop up menus from 159 Functional simulation ispLSI GAL run 137 Verilog HDL perform 152 VHDL perform 152 G Global optimization options MACH 128 Balance partitioning advanced 129 Boolean logic reduction 129 Boolean logic synthesis 129 Collapse all nodes for speed 130 Collapse selective nodes for area 130 D T synthesis 130 Maximum 96 macrocells per block us
14. Click the Properties button at the bottom of the Project Navigator to open the Properties dialog box 3 In the Properties dialog box Figure 5 8 select Report Type and set the List property to Macro cell Then close the dialog box Doutlg ckck f ead ached iam ko Genie i poiabk choices orum the combo box in the edit region tors bet ol Figure 5 8 Properties Dialog Box Report Type Macro cell isoDesignExpert User Manual 145 Equation Simulator for MACH PAL When you select the Macro cell List property the simulation results will be displayed for all dot extensions associated with I O macrocells Note that this display option is detailed and should be used in conjunction with the Signal option to reduce the size of the output report Macro cell reports provide the same information as Tabular with the addition of internal device information such as OR gate outputs and the final outputs The Macro cell report option produces large files if all pins and nodes are traced for all vectors To generate a smaller file use the Watch Signals and Vector Range to Display properties to specify the pins or nodes for a limited number of vectors If you do not specify which signals to watch the first I O pin in the device is traced Controlling the Simulation Report Report and trace types and break points allow you to control the amount of information the simulation provides Simulation can provide simple error messages indicating t
15. Frequency Table Setup and Hold Table Tco Path Table and Tpd Table icons from the tool bar If you select these icons before requesting a table through a popup menu the table displays but it does not contain any data You can also close a table or the Signal Navigator by deselecting an icon or a menu item on the View menu Timing Matrix Table clock D ispTOOLS ispsys80 examples ISPLSI 1 a BETES Destinations MUSF MUSE DEF 2398 10 60 12 10 G0_SC5_Q DO H 9 Figure 6 2 Timing Matrix Table When paths in the Timing Matrix table are preceded by D the delay is to the data input of that register When paths are preceded by CLK the delay is to the CLK of that register ispDesignExpert User Manual 157 Timing Analyzer for ispLSl Mock Freqeency Tobis clock Diep TOOLS epee BITS emm en Bel x Frequency Table hb RI Ri ba bl Ed jia SS RS RI RES bH Rd OC Sete and Held Teble clock Djip TOOLS epayi iesampien Me El Setup and Hoki Table zia Hafn mmm 001 05 TT Tr E 4 SYEH Eis svsruk svadi savsan arsan arsa grau SYTCLH svete STEL T T T T T T T r Tt F F 5 3D Do E I zb an im Ei a Ei A Tpd Table Source Destine Dee ne DATAIN2 DATAOUT 10 80 DATAINT DATAOUT 10 80
16. Minimize GLB levels for all paths advanced 124 Parameter file 123 Settings 118 Single PT function packing for routability advanced 125 Strategy 120 Timing Analyzer 123 Use extended routing 122 Use global reset 120 Use internal tristate IO driver advanced 124 R Reserved file names 37 Run Simulate menu function in Simulator Control Panel 139 143 S Schematic Editor open 33 Schematics add a blank sheet to a design 45 add to a design 44 add to an ABEL HDL file 87 import 44 Security ispLSI device option 125 Set and Hold Table Timing Explorer 157 Set Reset don t care MACH global optimization option 130 Show Edit menu function in Waveform Viewer 139 Show Waveforms dialog box in Waveform Viewer 139 Show Waveforms 139 View menu function in Simulator Control Panel 139 Show waveforms 147 148 Signal Navigator 155 ispDesignExpert User Manual 174 pop up menus from 156 Simulation log 140 Simulator Control Panel File menu functions Open Design 141 Open Stimulus 142 Simulate menu function Run 139 143 View menu functions Show Waveforms 139 window 138 Single PT function packing for routability advanced ispLSI compiler property 125 Source ABEL HDL test vector 27 Sources ABEL HDL 27 being placed in the Project Navigator 32 create 32 document 27 EDIF netlist 27 hierarchy 28 import 31 modify 33 project notebook 27 remove 34 schematic 27 target device 27 undefined 27 Verilog HDL 27 Verilog HDL test fixt
17. Open t Men 151 Log Start ar bring a window ta the foreground nr set wines aside Figure 5 10 Opening the Waveform Viewer n NOTE Refer to the Design Verification Tools User Manual for detailed information on other Waveform Viewer commands and functions ispDesignExpert User Manual 147 JEDEC Simulation JEDEC Simulation JEDEC simulation simulates your GAL or PAL design JEDEC file as a final indication that the information to be programmed into your GAL or PAL is correct Simulating a JEDEC File For GAL or PAL devices you can simulate the JEDEC fuse file by using the ABEL HDL test vector process Simulate JEDEC File This process simulates the JEDEC fuse map as compared to an internal model of the target device itself To simulate the JEDEC file 1 Select the ABEL HDL test vector abv in the Sources window of the Project Navigator Double click the Simulate JEDEC File process from the Processes window or click the Start button to run the process Figure 5 11 H ispDesignExpert Project Navigator D ISPTOOLS ISPSYS EXA Mi x File View Source Process Options Window Tools Help D I Strategy Normal Sources in Project Processes for Current Source C Mixed Output Level Counter Compile Test Vectors 3 GAL22V10D 4LJ S Compiler Listing Simulate JEDEC File micount wdl S JEDEC Simulation Report E mixlev mixlev abl X JEDEC Simulation Waveform X Functional Simulati
18. When designs can be broken into multiple levels this is called hierarchical design ispDesignExpert supports full hierarchical design allowing you to create a design that is divided into multiple levels either to clarify its function or permit the reuse of functional blocks Tips for Defining Projects Use the following guidelines when saving and naming source files and your project Understand and use the different methods for hierarchical design Avoid using ABEL HDL or EDIF reserved words for module and signal names in any of your source files Avoid saving a project that has the same base file name as one of its sources If a source and project have the same base name you may have problems with the Project Navigator s Auto make feature Each source must have a unique name in the project You cannot have two different sources with the same name You can use the same source many times in a design by instantiating the source but two different sources with the same name can cause problems with the hierarchy For example do not use an ABEL HDL source called compare and a schematic source also called compare The file name and module name of an EDIF file should be the same ispDesignExpert User Manual 30 Describing a Project Importing an Existing Source To import an existing source 1 Choose Source Import to open the Import File dialog box Figure 2 4 imposi File won acc sh eife mi Figure 2 4 Import File Dial
19. breaking apart a complex design some may be better than others In general Each module should have a clearly defined purpose or function and a well defined interface Look for functions or component groupings that can be reused in other projects The way in which a design is divided into modules should clarify the structure of the project not obscure it Hierarchy vs Sheets in Schematics A hierarchical design is not the same as creating a schematic with multiple sheets In a schematic you can add as many sheets as desired to extend beyond the original sheet However regardless of how many sheets you add all the components of the design are still at a single level all sheets are still contained in the same module Approaches to Hierarchical Design Hierarchical designs consist of one top level module This module can be of any format such as ABEL HDL VHDL Verilog HDL schematic or EDIF netlist Lower level modules can be of any supported sources also and are represented in the top level module by a functional block or other place holders Following are some rules you need to follow when creating a hierarchical design in ispDesignExpert The top level source can be of any format such as ABEL HDL VHDL Verilog HDL schematic or EDIF netlist For hierarchical Schematic ABEL designs If the upper level source is a schematic file the lower level source can be either a schematic or an ABEL HDL file If the uppe
20. ispDesignExpert User Manual 8 Preface The ispDesignExpert software is used to create designs to program ispLSI MACH GAL and PAL devices from Lattice Semiconductor Corporation LSC This manual describes the Project Navigator the Graphical User Interface GUI for the ispDesignExpert software The design procedures provided in this manual are intended to help you understand how to use the ispDesignExpert software to create designs for different devices ispDesignExpert User Manual 9 What is in this Manual What is in this Manual This manual contains the following information Overview of the software Discussion on project management procedure Introduction of the supported design entries Design considerations for design entries Applying design attributes Usage of the Constraint Manger and the Constraint Editor Design verification in different simulation environment Running timing analysis Where to Look for Information Chapter 1 Introduction Provides a brief description of all ispDesignExpert tools Chapter 2 Project Management Covers general information about the Project Navigator and its user interface Chapter 3 Design Entry Describes the supported design entries in the ispDesignExpert and some design rules Chapter 4 Design Implementation Presents the method of adding compiler control options or device control options to your design Chapter 5 Design Verification Contains descriptio
21. it only tests the equations in your MACH or PAL design as specified by test stimulus To make the simulation process available you have to select the test vector file in the Sources window The simulation process appears in the Processes window To invoke the Equation Simulation process 1 Select the ABEL HDL test vector file abv of a MACH or PAL design from the Sources in Project window in the ispDesignExpert Project Navigator Figure 5 7 ispDesignExpert User Manual 144 Equation Simulator for MACH PAL t Mawigaior DAIS TOOLS erui pine mes n n P n HE counter cnumar abl R Egunian Bimelabon WWevel rm EX Simulate Pre i E paas Pm Fil Equation Simeleteon Pin peri R Pro Fil Equation Simslateon Wersclone Doeble cick m opende selected tes Doutip ckck fe famon fe iet arseleci fie Stet verto Baio in andthe process Select Aa Propsries Bains in sh tha onsparty adie Figure 5 7 Running the Equation Simulator 2 Select the Simulate Compiled Equations process to start the simulation The Simulator Model The Equation Simulator uses the Equation file to build a model of the design This method includes macrocells sum terms and product terms Select the Report Type Macro cell property to display the model To view the simulation model 1 In the Sources window select the test vector abv file 2 In the Processes window select the associated Simulate Pre Fit Equations process
22. pm sich RF Gonstraint kane qe Ejmux zl jmutx sh D Compile Designu zy miete a a i hil ig JEDEC Fila DCompiler Report i Timing B amp nnbyiix K Timmg Explorar d bimamum Frequency Hepo dry dia Rapai HT pd Rapar dr co Appor B Pipaical Wren RSF Daisy Chain Download Doub berth i chinas in chee device Deubin rkck En rem n bre lait rama len Piet baton aien ha pipzases Eakecitha Emnpertes button to neithe property tewbe msi aed oen ong Figure 3 44 Hierarchical Schematic VHDL Design To instantiate a lower level schematic and a lower level VHDL module in a schematic 1 In the Project Navigator choose Window Schematic Editor to open the Schematic Editor The Schematic Editor opens with a new sheet This schematic is going to be the top level schematic Next you will place a Block symbol a functional block in the schematic that will represent a more detailed schematic or VHDL module at the next lower level To add a block symbol that represents the lower level schematic mux2x1 sch in this schematic choose Add Symbol to open the Symbol Libraries dialog box Select Local from the library list then select the target symbol mux2x1 If mux2x1 is not available from the Local symbol library generate it upon the sub level module mux2x1 sch Refer to page 50 for more details on how to create a symbol Move the pointer back over to the Schematic Editor Notice that the symbol you selected is attached to the point
23. select the top level sch file in the Sources in Project list 2 For an ispLSI 1000 2000 and 3000 device select the Compile Schematic icon in the Processes for Current Source list For an ispLSI 5000V 6000 or 8000 device select EDIF Netlist icon in the Processes for Current Source list 3 Select the Properties button at the bottom of the Project Navigator window The Properties dialog box appears as shown in Figure 3 13 Figure 3 14 Figure 3 15 and Figure 3 16 E Moma Schomeatic Gene Home Schomelic Figure 3 14 ispLSI 5000V EDIF Netlist Properties Dialog Box isoDesignExpert User Manual 51 Schematic Design Entry nma Schpmhlic E Pomel Schemealic Figure 3 16 ispLSI 8000 EDIF Netlist Properties Dialog Box 4 Set the appropriate Design Control Property depending on your target device Check the ispEXPERT Compiler User Manual for device dependencies 5 Click Close isoDesignExpert User Manual 52 VHDL Design VHDL Design This section describes using VHDL as an entry for your design that supports the ispLSI GAL MACH and PAL devices Add a VHDL Module to Your Design To add a VHDL module to a design you can either import a vhd file or create a new VHDL module file in the ispDesignExpert Text Editor To import a VHDL module to your design 1 Choose Source gt Import from the menu bar The Import File dialog box appears Figure 3 17 The project type Schematic VHDL
24. selected source in the Project Navigator to generate a Verilog test fixture declarations file t 1 that should be included in the test fixture By using the Text Fixture Declarations include file in your simulation test fixtures you ensure your design and test fixture stay synchronized Add relevant contents to the t i file and then you have a Verilog test fixture for your project A CAUTION The Verilog HDL Test Fixture Declarations t i is an intermediate file that can be deleted when using the File Clean Up All command of the Project Navigator Do not save your modifications to the t fi file ispDesignExpert User Manual 150 ModelSim Simulator Export VHDL Test Bench or Verilog Test Fixture from Waveform Editor If you have a source wd1 file in your project you can export the VHDL test bench or the Verilog test fixture from the Waveform Editor To export VHDL test bench or Verilog test fixture from Waveform Editor WET 1 Select the source wd1 file from the Sources window of the Project Navigator and open it in the Waveform Editor NOTE If you import a wd1 file to your project for the first time and want to view the waveform of the wd1 file in the Waveform Editor select Edit 2 Show from WET In the prompt Show Patterns dialog box choose the desired signals and click the Show button The waveform of the desired signals are thus shown in WET 2 Choose File Export from the
25. you can still assign attributes directly to a source file For information on how to assign attributes in a source file such as a schematic or an ABEL HDL file refer to Chapter 3 Design Entry The Constraint Manager consists of the Design Browser a Pin Attributes Table a Net Attribute Table and a Symbol Attributes Table If your EDIF design contains attributes or if you read in an EDIF Property File when you created your project or if you set pin attributes using the Compiler Graphic User Interface GUI those values display in the attribute tables If you make changes to the attribute tables the new values are reflected in your project You can create a Property File by selecting the File Save Property As menu item You can open an existing Property File by selecting the File 2 Open Property menu item The values from the Property File being opened are reflected in the property tables You can save changes to the open file using File gt Save Property Main Window Use the main Constraint Manager window to set attribute values for signals the pins and the symbols To invoke the Constraint Manager 1 Select the target ispLSI device from the Sources window of the Project Navigator 2 In the Processes window double click Constraint Manager The main window of the Constraint Manager appears Figure 4 1 ispDesignExpert User Manual 106 Constraint Manager for ispLSI Designs Design Attribute Table Browser
26. D2 D3 This override becomes the reference at all levels of the hierarchy If in the suggested 16 bit register the DO D1 D2 inputs were connected to wires named and marked Bit0 Bitl Bit15 these new names take precedence and the DO D1 D2 names would no longer be accessible at any level of the hierarchy ispDesignExpert User Manual 86 Mixed Entry Design Mixed Entry Design The ispDesignExpert supports mixed entry mode Schematic and ABEL HDL Schematic and VHDL and Schematic and Verilog HDL They are mutually exclusive so you must choose one of the three types when you begin a new project Schematic and ABEL HDL Mixed Entry You can use the ispDesignExpert software to create an ABEL HDL file or a schematic and then connect it to the top level schematic or the ABEL HDL file To add a schematic to a project 1 With the device selected Figure 3 54 select Source New from the Project Navigator menu bar In the dialog box select Schematic and click OK Enter the file name in the File Name text box Click OK You are now in the Schematic Editor TRRETOTETUUIEUURETTDTCUEGERSADBBUEILSEEYESYUESU Me E Preceeeee inr Curent Soure Aa pdas All Soke mati Files 1 Link Dasign Linked Equestions E Reduce nic ig EDIF Matiis bicockingp abw X Cnneirmint Manager Bicinckinp clackinp sch Bjenniral innra sh EJ HOURS cers abt Seren irreg nbi EjHIHLFTES minutes nbl
27. Design igi R Conitrnini banag Compile Design igi JED File 2 Compilar Rapar E Timing Analyses Timing Explorer DO Maximum Frequency Fiapenrt ZjSetup tinld Repost S Tipu Rapai us Report R Physical Veneer REF Dabse run Chain Download EL aramon he interact te Doutip cick Slat befont dian ihe process Salacija ye haton to ur peocess Bad isc the cine Vice Figure 3 28 Verilog HDL Design Flow 2 Click the Start button or double click on the Merged EDIF Netlist process to start creating the edt file for the ispEXPERT Compiler The Verilog HDL file will be synthesized in this process as well For a GAL MACH or PAL devices the EDIF netlists will be created when you run the Fit Design process For more information about ispLSI Design Attributes Device Control Options EDIF Property Files or Parameter Files see the isoEXPERT Compiler User Manual ispDesignExpert User Manual 60 EDIF Design EDIF Design You can import an EDIF design netlist description into the ispDesignExpert from third party synthesis or schematic tools for the isoLSI GAL MACH or PAL designs To import an EDIF netlist into your design 1 In the Project Navigator choose Source Import to open the Import File dialog box 2 Choose EDIF Netlist ed from the Files of Type field of the Import File dialog box Figure 3 29 And then select the EDIF file you want to import Fuge mee Files php Figure 3 29 Import Fil
28. Fn Shee Poser di A Figure 4 2 Constraint Editor Main Window ispDesignExpert User Manual 109 Constraint Editor for MACH Designs Note that the design signal labels are only listed exclusively in the Location and Group Assignments dialog boxes For instance if signal 1d new alrm time is assigned to a pin via the Location Assignment dialog box then this signal will not be listed in the Group Assignment dialog and vice versa This feature prevents conflicting assignments from being implemented Location Assignment Use the Location Assignment dialog box to assign input and output pins and buried nodes Available pins for the selected device Type of assignment Signal List in the Design Filis Click at the column label to sort the list Figure 4 3 Location Assignment Dialog Box To make a location assignment 1 Select a signal from the Signal List The signal list can be controlled using the Filter check boxes 2 Select the assignment type Pin Macrocell Block or Segment 3 Click Add You can make modifications to the existing list with the Delete Modify and Undo Modify buttons The Cancel button discards all new edits and returns to the previous assignment list list prior to opening the dialog box ispDesignExpert User Manual 110 Constraint Editor for MACH Designs Group Assignment Use the Group Assignment dialog box to assign a group to a Block or Segment m For MACH 1 2 and 4
29. IOU CO PIOKNESDN oca dodasadedeRRl r4et rbPEdIAR ERRARE ON LOedAdaddpE 28 Processes Vi sos rinine pdd EErEE RANAUT ENEE Gorse satan dee Cree es 28 Process PUR 0 6 d OLOR EEG EU eO ER di FUR ECOLE AUR oO ER aod 29 Besering Rui oc MT TP M Oh Oe a EE RS 29 It gei 4s o RETE CU mmm 29 Device Selection 0 0 00 cee eee 29 Sect Project FES ctecdtieee duced dawns AR d RE dc dad Merce een aod de 30 Design Piera y sot chee ee vp 30 Tips for Defining Projects 5 ors he ke dodo lab Gr he o Re ee KORR EORR CO e ORCI GE 30 importing an Pd SOBRE i iaa d etc ied kd dolci doe Cb a CR ao oe 31 Where the Source File is Placed in the Project Navigator 32 Creating d New SOUCO cs uae Rd iens dn n CRUA RO Ri Cot eaa atr SUR Res e A 32 Modifying a Source ce cccueudu hmmm mmt ARRERRRES Rr mr RRESSAA RE 33 Enna EMIME Luna smadaauAan des ied d dios d doa Rd dE RR Od od Ron den di ubi S dii 33 AE EUIS da VOIE ERE Rel ER ORE ELEM LA AEE eh CREER Re dea d 33 ispDesignExpert User Manual 4 eo NG M GOET iat aad duum ker d uoa dnqddabebehdrewa xps Rai d 34 Processing a DSi coedasdda qtd e PedqedebecreqeedaspSbepridedsa tiq rider he 34 F r ing a PIBOSSS to RUM a sae Aka ded Rh oro doa ardore de c od tob ade CI E A 34 Changing the Environment and Configuration 0000 eee eee 34 Cleaning Up a Projet cacao dO cn ed KR ACT OC Eee o deed d dede eb b e RU 36 A OPO M PUT 36 Dscd io o M C rrrrrrnrm 37 Tips Tor Savin
30. Mode ES E clock Inputs NSLOW NFAST NHOLD SYSCLK TEST Outputs Bi directional Registers H DO H D1 GO_SC1_G HO_D2 H D3 C BC Q LO_DO LO_D1 GO_SC5_Q CO_BC2_Q LO_D2 CO_BC11_Q E A H E EE REI Figure 6 1 Signal Navigator ispDesignExpert User Manual 155 Timing Analyzer for ispLSI Pop up Menus from the Signal Navigator When you click the right mouse button within the Signal Navigator a number of commands are available depending on where the cursor is when you click the right mouse button From the Signal Navigator window you can select the following commands m Fan In Mode Changes the display to fan in mode m Fan Out Mode Changes the display to fan out mode m Hide Removes the Signal Navigator from the screen From the design name in the Signal Navigator tree you can select the following commands m Timing Matrix Table Displays the Timing Matrix Table for the design m Longest Timing Path Calculates and highlights the design s longest timing path in the Timing Matrix Table m Shortest Timing Path Calculates and highlights the design s shortest timing path in the Timing Matrix Table m Frequency Calculates and highlights the maximum design frequency in the Frequency Table From a signal category or signal name in the Signal Navigator tree you can select the following commands m Add Source Timing Tag Adds the highlighted signal to the source
31. Signal Pin Symbol Names Assign Attribute Values Figure 4 1 Constraint Manager Main Window Design Browser The Design Browser shows all the Input Pins Output Pins Bidirectional Pins Nets and Cells Click on the to expand the list to see signal pin or symbol names To add a signal pin or symbol to an Attribute Table double click on the signal pin or symbol name To add all the signals pins or symbols in a category to an Attribute Table double click on the category name Input Pins Output Pins Bidirectional Pins Nets and Cells Pin Attributes Table The Pin Attributes Table allows you to set attributes for input pins output pins and bidirectional pins in your ispLSI design The Pin Attributes Table displays when you click on a pin or input output or bidirectional pin category in the Design Browser Depending on the device used in the design you can set the following pin attributes CRIT LOCK LOCK BFM LOCK GRP OPENDRAIN PULL SLOWSLEW VOLTAGE ispDesignExpert User Manual 107 Constraint Manager for ispLSI Designs The Reserved Pin attribute must be set from the Assign Pin Attributes dialog box of the ispEXPERT Compiler Net Attributes Table The Net Attributes Table lets you set net and path attributes for the nets in your ispL Sl design The Net Attributes Table displays when you click on a signal or nets category in the Design Browser Depending on the device used in the design you can set the foll
32. Table Timing Explorer 157 Collapse all nodes for speed MACH global optimization option 130 Collapse selective nodes for area MACH global optimization option 130 Compiler properties ispLSI 118 BFM packing advanced 125 Carry pin direction 123 Case sensitive 123 Effort 120 Free all pin locks 122 Ignore reserved pins 122 invoke dialog box 118 Maximum GLB inputs 121 Maximum GLB outputs 121 ispDesignExpert User Manual 170 Minimize GLB levels for all paths advanced 124 Parameter file 123 Settings 118 Single PT function packing for routability advanced 125 Strategy 120 Timing Analyzer 123 Use extended routing 122 Use global reset 120 Use internal tristate IO driver advanced 124 Constraint Editor Assigning Power Level 113 for MACH 109 Group Assignment 111 invoke 109 JEDEC File Options 112 Location Assignment 110 make 110 main window 109 Output Slew Rate Control 114 Pin Reservation 112 Constraint Manager Assign Attribute Values 108 Design Browser 107 for ispLSI 106 invoke 106 main window 106 Net Attributes Table 108 Pin Attributes Table 107 Symbol Attributes Table 108 Constraints MACH PAL 66 D D T synthesis MACH global optimization option 130 Design hierarchy 30 67 ispLSI GAL compiling fitting 132 MACH PAL compiling fitting 134 procedures 23 processing 20 34 targeting a device 18 Design attributes add to a symbol 48 ispLSI 96 assigning in ABEL HDL 98 assigning in schematic 97 Index
33. The Global Optimization tab Figure 4 16 offers you optimization options Use the Defaults button to reset the selections to their default settings Use the Apply button to apply the options Git ni Opismixgtiun Goal pimihan Logis Syrnatasis Lireban Desiens Cgobrrar mon prkons C Pack di prose dezion Arkomncmd opion Hert F E Figure 4 16 Global Optimization Dialog Box Global Optimization Pack Design If this radio button is checked the Fitter packs the design pack by pack This option packs the design for maximum density and speed It sets both the Balance Partitioning and Spread Placement features to FALSE Spread Design If this radio button is checked the Fitter spreads the design throughout the device This option allows the design to be partitioned and placed in a spread out method This method of placement enhances the upgrade capability of the design by spreading the resources throughout the device However the disadvantage is that more resources may be used because the design is partitioned evenly through all the blocks This option sets Balance Partitioning and Spread Placement to TRUE ispDesignExpert User Manual 128 MACH Global Optimization Options Advanced Options This option lets you choose the Balance Partitioning and Spread Placement algorithms m Balance Partitioning When this option is enabled the design is partitioned evenly among all the blocks in the device So eac
34. VCC and GND are to be read as Nets or Cells The default representation is a net You can also specify VCC and GND names The default names are VCC and GND In the logic evaluation phase for the signals connected to the PRN pin and CLRN pin the conversion program must know the name of the power and ground signals The ispDesignExpert supports EDIF files that contain arrays for ispLSI designs A design ary file is created automatically by the EDIF Reader and is used during VHDL and Verilog output generation after the design is compiled The vectors or buses are automatically reconstructed and included for VHDL or Verilog post route outputs based on the information provided by the array file Use the Array Index Ordering radio buttons to specify the index range Use the Least Significant Bit radio buttons to specify whether the leftmost bit or the rightmost bit is to be the least significant bit LSB Select this option to ground all floating output pins If you choose Altera in the Vendor field the dialog box expands to display the Altera Options section Refer to the ispEXPERT Compiler User Manual for more information on this section ispDesignExpert User Manual 62 Import EDIF EDIF File tadd8 edf EDIF Design Import as C Custom OK TES Cancel Hee Help Figure 3 31 Import EDIF Dialog Box Custom field CAE Vendors The default setting for power and ground in ispDesignExpe
35. Waveform Editor The WET Export dialog box appears Figure 5 13 WET Erpin ee ed ed Duriput Piia lock ti Epot lu Figure 5 13 WET Export Dialog Box e Input File Enables you to choose an input wd1 file Output File Enables you to have an output file default name of which is the same as the input file chosen The file extension varies with the Export Style you choose e Export Style Specifies the style of the file you need to export either a Verilog test fixture t or a VHDL test bench vht or tb NOTE The exported vht or tb file needs to be renamed to vha before it is to be used as a VHDL test bench in your project ispDesignExpert User Manual 151 ModelSim Simulator Performing the VHDL Verilog Functional Timing Simulation You can simulate a VHDL or Verilog HDL design using the VHDL Verilog Functional Timing Simulation process in the Project Navigator To run VHDL Verilog Functional Timing Simulation 1 Choose the VHDL test bench vhd or the Verilog test fixture t from the Sources window of the Project Navigator NOTE If the test stimulus file vha or t is associated with the selected device both VHDL Verilog Functional and Timing Simulation processes are supported However if you associate the test stimulus file vha or t with a design module schematic only VHDL Verilog Functional Simulation is available 2 Select
36. can be used to locate the occurrence of a specific logic event Delays between events can be measured with markers The Waveform Viewer is typically used in conjunction with a simulator You must run simulator before you can run the Waveform Viewer without simulation information the Waveform Viewer has no data to display Therefore you open the Waveform Viewer by running the simulation To open the Waveform Viewer 1 In the Sources window select the abv file The associated processes appear in the Processes window of the Project Navigator 2 In the Processes window double click the last process to run the simulation After the simulation runs the Waveform Viewer opens Figure 5 10 displaying the simulation waveforms M iwen Vimerr History File Edi Ve Obed TE rion Jump eb clk clr reik i Rusti premi a upDesigaEsxpam Project Mavigainr AERTS US AMFLE S N MEE Bis View Source Process Coto Mindow Tools rrr Cif ia Strategy Homs el s Sources in Propert Processes inr Curent Source Pulse Wit Modebete dl Ls Compile Test Vectors ELETE Psat Sj Cioempiidus Lislimg kinima Compilud Equations QE quntinn xmulntina Repon l SBusz p mem mne graced nbi Jjenuster ceras bas n Es F E gestion Esmulntiua Wisi ut Simaa Pre Fit Equations DIU Fra il Equation t Dowtie cick io open the seiecied test Duublecich he A warns naires Mew
37. click on the net you want to edit In the Net Attribute dialog box Figure 3 12 enter the relevant contents of the attribute Close the dialog box Net Attribute Editor AsyncPath CriticalPath NoMinimizePath Preserve Figure 3 12 Net Attribute Dialog Box ispLSI Devices 5 Check your schematic for errors by using DRC Consistency Check An Error Report window pops up to show the error message If no error is found the message No errors detected will display in the Error Report window 6 From the Schematic Editor menu bar choose File Save to save your design Select File Exit to close the Schematic Editor window ispDesignExpert User Manual 49 Schematic Design Entry Create a Symbol A useful feature of the ispDesignExpert software is to quickly create a symbol for a schematic By using this you create a reusable macro that can be placed on a higher level schematic sheet To create a symbol 1 Open the schematic file by double clicking on the schematic source sch in the ispDesignExpert Project Navigator 2 In the Schematic Editor menu bar select File Matching Symbol 3 Select File Exit to close the schematic 4 The symbol is created and added to your symbol list It can be found in the Local symbol library Or to any design that contains naf file 1 In the Schematic Editor select File Generate Symbol 2 The Select File dialog box appears prompting you to choose a naf
38. current schematic The name of the lower level schematic must match the block name schematic or the interface name ABEL HDL in the upper level module This associates the lower level module with the symbol representing it For example the schematic in Figure 3 37 must be named aad sch The net name in the lower level schematic correspond to the pin names schematics or pin names ABEL HDL in the upper level module ispDesignExpert User Manual 72 Hierarchical Design Hierarchical Schematic Design The following steps outline how to specify a lower level block symbol in a schematic Figure 3 38 shows a schematic block add sch instantiated in another schematic top sch However you can follow the same procedures to instantiate a lower level ABEL HDL block symbol in a schematic sagnExpert Project Miga DISPROOLS SPSyS EXAMPLES Sel EI z farce hoen piene Wiadow Toole T3 Woes All Suchemmarc Files igi Mesred EDIF Isrllsst E RF Constraint Maemnnges Ejnaid miii sch Di Compils Len ign igi JEDEC Fila n Compiler Fopentt Oi Timing Ann hyena Ky Timing Explorer D kimiimum Frequency He port Iz y Eerlup Hold Mapari a Rapi DTe Aeport F Pinyaical Venir Dinulilirccheck t chaiis deen dee Deutlu ckrk ba Fam helsl rassarifia giat batoe io sari die process Salecttha Shomer beg nig mier he propert sinr Now Deer Sef ef to Rendy Figure 3 38 Hierarchical Schematic Design To instant
39. dede e 122 isoDesignExpert User Manual 6 Inno Reserved PINS caouoea Gea duda wd dA ae diese ducem Add s md a AE 122 Use Extended ROWING 2ausd gea ba dede d p EPPrEREd AG PPEPIWduSu rear dede RE 122 Carty Pin Dreco e duae eo dio Vk dee dom doble he e d oae A doi book pol CR Rd 123 Care GOME MPr nme 123 WR er orne rnane TOIT E ERE EEE EREA 123 Poses PE aaa cR rr DN 123 Interfaces Dialog BOX 000 ees 124 Advanced Compiler Settings Dialog Box 0 00 eee ees 124 Minimize GLB Levels For All PSUIB ooi Od REOR ER ODIO DECIR Fey RE EROR 124 Use Internal Tristate IO Driver amp osceoa bb ERR RECCRRCRHCR IE RR RR RI RO R 124 BL PBORIBOL ick od heed dd dd vice reo al doin o doce feb da lo 9 125 Single PT Function Packing for Rowtability 2 22 22ceds enel 4 RR 125 EE le sis nk che eae eed rmm 125 BGC pe ka metho deddee oon aram e ie m ado eee i pde aci a beeen abb aa ss 125 ISP Lieb ope dp tds vat Ed qr HORROR Ab dein eiie da Hao Peto ac 125 OP COR T ih oh OE EOE peior d Rd QR CO EROR ID dolci deor don d 125 LiT 11 MCCC RE he eae Oe EN a rhe ers 126 TOE a 0 biG ee Ew eee ae Ao ade Agee ee ACh ee Gees Ge 126 LOWMINBI cudicascepileuedamdbpbedeceetihpabesd4Ak A paddeseddped id da 126 DBB E E E E N em daa d idadii xd e dk aU ad QE oe C NM ees 126 ruo Apo a ne er ee eee ee a eee ee ree re ee ere eee ree re 127 cisci o MAMMMMEMTC L 127 MACH Global Optimization Options 29d eh
40. devices Block Any If this option is selected all the signals in a group are grouped together in a single Block or Segment but it could be any block or segment in the device m For MACH 5 devices Block Any Segment Any If this option is selected all the signals in a group are grouped together in a single Block of the Any Segment Note that if you specify Any Segment by default you can only select Any for Block Block Any Segment Number If this option is selected all the signals in a group are grouped in a single Block in the specified Segment The Clear button clears the current selected signal list and group name Group name for the current assignment List selected signals for the current group assignment Peig dogs s quen Pompa OF epee D Dasho n Ergo rms cm pan eren led Giai EE Umen Leg eme Figure 4 4 Group Assignment Dialog Box ispDesignExpert User Manual 111 Constraint Editor for MACH Designs Pin Reservation Pin Reservation constraints are soft constraints If the design failed to fit the Fitter ignores the pin reservation constraints The software issues a warning message to the ERROR or LOG file when the constraint is discarded Prr Pansa icr inti Ps Toa P ipe r Oami i Quch Fas Type of Pin Reservation Tupa ca Blacker Por Egan 7 Est Pig State of pin d T Oem Le for Output or Kore mgderan I O type I emma Eht pm mote t Beh Paie 8 8 rente
41. functional and timing simulation in other words any step along the way from design entry to implemented Lattice Semiconductor devices The table below Table 2 2 lists the ispDesignExpert process types and shows its corresponding icons Table 2 2 ispDesignExpert Process Types Process Type Icon Process e Report B Output File Tools X ispDesignExpert User Manual 28 Describing a Project Process Flows One of the most powerful features of the ispDesignExpert is that the Project Navigator is context sensitive and automatically adjusts the processes for you depending on what you want to do The steps in the Processes window are context sensitive in two ways First the process flow changes depending on what kind of source file is highlighted in the Sources window source level flow Second the processing for a given file changes depending on the target device you have chosen project level flow Describing a Project You describe a project by targeting a particular device implementation and by specifying the project files that will represent the design Targeting a Device The Project Navigator lets you target a design to a specific device at any time during the design process If you do not know the specific device you can target the ispL SI Default Device ispLSI5384V 125LB388 Device Selection Because the Project Navigator is context sensitive when you choose the ispLSI Default Device processes al
42. is shown in the title bar of the dialog box letting you double check your project type before importing the source files L3 n HE pali Sole ml va rris Tau uud HD Flnchula sh Figure 3 17 Import File Dialog Box 2 Choose the desired VHDL module vha and click OK 3 The Import Source Type dialog box appears Figure 3 18 Choose the type of source you want to import into your project either VHDL Module or VHDL Test Bench from the Type of Source field Click OK import Source Typ Figure 3 18 Import Source Type Dialog Box isoDesignExpert User Manual 53 VHDL Design NOTE If you have not chosen Schematic VHDL as the project type the vhd file will be imported as a VHDL test bench without prompting the Import Source Type dialog box 4 The selected VHDL file appears in the Sources in Project list of the Project Navigator as shown in Figure 3 19 igi Vardag Taal Fixture Declares DHOL Test Bench Templabe Doubek m opan the delectkad amare Deuble thek tha ikam in Pra iter select Pis io view Pi repo e _ ce we m ag Fieadiy Figure 3 19 Project Navigator Window with a VHDL Module File Imported Highlight the VHDL icon and use the text editor to view the syntax of the VHDL module Figure 3 20 Ee Tess Editor rnc Tuer vie J Ble Edi View Temples us Options W mdsw Help Cue e C Te s po E Cd 6 ie ai 8 library imam 66a lowe std logic L15
43. ispDesignExpert User Manual 132 Compiling Fitting the isoLSI GAL Design B ispDesignExpert Project Navigator D ISPTOOLS ISPSYS EXAMP Miel E3 File View Source Process Options Window Tools Help Strategy Normal Sources in Project ABL HDL system macros used S comp wri ispLS11016E 80LJ44 E comp vectors E comp comp abl Processes for Current Source e Oates S Linked Equations e OQ Reduce Logic e i EDIF Netlist X Constraint Manager e Compile Design e iiEDECFile e Compiler Report Or Timing Analysis X Timing Explorer E Maximum Frequency Report Hold R Double click to choose a different device New Open Double click the item in the list or selectthe Start button to startthe process Selectthe Properties button to startthe property Start View Properties Log Figure 4 20 ispDesignExpert Project Navigator after the Compile Fit Design Process of ispLSI GAL Designs NOTE Yellow exclamation besides the process points indicate that warnings were generated Red Xs indicate that errors were encountered The warning or error is described in the auto make log file displayed in the Report Viewer Green check marks indicate the process completed successfully 4 Double click on Compiler Report in the Processes window to see the statistics related to the fitting of your design Figure 4 21 Ee Repor Viewer cnmp rpi Ble Ed
44. level source is an HDL module the corresponding waveform will be shown in the Waveform Viewer NOTE Refer to the Design Verification Tools User Manual for detailed information on other Waveform Viewer commands and functions Simulation Log The Simulator logs errors and status information in one of the three files depending on the nature of the information automake log logs processing information err Logs logic errors slg Logs simulation status information If a simulation error occurs it is recorded in and may be viewed by selecting the View Simulator Log menu item in the Simulator Control Panel window Simulation errors do not automatically cause the Report Viewer to appear ispDesignExpert User Manual 140 Lattice Logic Simulator for ispLSI GAL Running Stand alone Lattice Logic Simulator The Lattice Logic Simulator can be invoked in its stand alone mode by selecting the Tools Lattice Logic Simulator menu item from the ispDesignExpert Project Navigator The stand alone simulator enables you to simulate the design file or stimulus file outside the current project Even if you have previously opened the Simulator for a project you can change to the stand alone mode To run the stand alone simulator 1 Select Tools Lattice Logic Simulator from the Project Navigator The Simulator Control Panel window appears Figure 5 4 in its stand alone mode S Swi nor oie ee Stnnd ninne belie Fig
45. markers at once click and hold the cursor and drag it to select all the input net names This procedure works for output pins as well Choose Output from the I O Markers dialog box and click on the end of the output net Save your schematic Add Design Attributes Attributes can be added to either symbols or nets In the ispDesignExpert pin attributes are actually added to the I O Pad symbols not the I O Markers I O Pad symbols are only necessary if you want to add attributes to pins Otherwise you only need I O Markers To add design attributes to a symbol 1 From the Schematic Editor menu bar select Edit gt Attribute gt Symbol Attribute The Symbol Attribute Editor dialog box appears On the schematic click on a symbol or an I O Pad attached to an net A list of related attributes appears in the dialog box Click List All Attributes to display all of the available symbol design attributes Select the attribute you need to add or edit and replace with proper values as shown in Figure 3 11 in the text box Click Go To to add the value of the selected attribute to the I O Pad or symbol in the schematic Close the dialog box ispDesignExpert User Manual 48 Schematic Design Entry Symbol Attribute Editor SynarioPin e GoTo Find Instances I List All Attributes Figure 3 11 Symbol Attribute Editor Dialog Box ispLSI Devices 4 The steps are similar for adding a Net attribute On the schematic
46. or block depending on the device selected Power level for the unassigned macrocell signals or blocks are set to the Default Power Level setting For MACH 1 and 2 Power level can be assigned to individual macrocell signal so the signal labels will be listed in the Default Power Level list For MACH 4 Power level can be assigned to the block number for example A B C D etc For MACH 5LV Power level can be assigned to the block number in the segment such as 1A 1B 2A etc The number indicates the segment number Note that the Default Power Level is set to HIGH to reduce timing delays Any changes to the power level will affect the design timing Power level assigned to specified macrocell signal labels of blocks List Macrocell signal labels or Block numbers Figure 4 7 Assigning Power Level Dialog Box ispDesignExpert User Manual 113 Constraint Editor for MACH Designs Output Slew Rate Control This dialog box lets you set the output slew rate of the device By default the output slew rate is set to FAST If the output is set to SLOW slew rate it will delay the design timing The Default button discards the current changes and return back to the previous settings before the dialog box is opened I Siew Finke Canini Eai haben E fares rra n C SLOW dew rain F FAST slewraio Aasigaad Gigs Fina unpre deih io FAST Curgrux memgnic SLCAM pem Figure 4 8 Output Slew Rate Control Dialog Box
47. register inputs or data input of transparent latches Default tOE Path Trace This path starts from the primary input pin and traces any number of levels of combinatorial logic through the Enable of output buffers to the primary output 5 EN Figure 6 13 Default tOE Path Tracing tCOE Clock to Output Enable Time This path trace analysis reports the input clock to output enable path delay starting from the primary input going through the clock of flip flops or gate of latches going through the Enable of output buffer and ending at the primary output You can specify whether reporting is enabled for paths traced through asynchronous register inputs ripple clocks or data input of transparent latch ispDesignExpert User Manual 165 Performance Analyst for MACH Designs Default tCOE Path Tracing This path starts from primary input pin and traces through the Register Clock through any number of levels of combinatorial logic to the Enable of output buffers Figure 6 14 Default tCOE Path Tracing Running Timing Analysis You must target a certain MACH device for your design before you run timing analysis If you have not already run the Fitter ispDesignExpert will fit the device automatically when you start the Timing Analysis process To start the Performance Analyst 1 In the Sources window select the target device Note that you must have a specific MACH device chosen 2 Double click the Timing Ana
48. when running the simulation You cannot run simulation successfully though you have loaded the design You will get a message stating Loading design file sim edf Or edn successfully in the Simulator Control Panel window But the toolbar is still gray at this moment Choose File Open Stimulus The Open Stimulus dialog box appears prompting you to select a stimulus file wd1 abv or ab1 Figure 5 6 Open Stimulus Look in S clock El c EE File name clocktop abv Files of type Stimulus File abv Caral Figure 5 6 Open Stimulus Dialog Box isoDesignExpert User Manual 142 Lattice Logic Simulator for ispLSI GAL NOTE The stimulus file you choose must be in the same directory as the netlist file A message Loading netlist successfully appears in the Simulator Control Panel window The toolbar is activated at this moment 5 Click the Run icon from the toolbar or select Simulate Run to start the simulation NOTE If you keep the View gt Show Waveforms menu item checked the Waveform Viewer is invoked in the course of simulation to show the simulation results in waveforms Refer to Showing the Waveforms in the Waveform Viewer on 139 for details on viewing the waveforms 40 NOTE Refer to the Design Verification Tools User Manual for detailed information on other Waveform Viewer commands and functions isp
49. 0 00 Q3 1 30 data arrival time Detailed Report Figure 6 7 Timing Path Information Window ispDesignExpert User Manual 160 Performance Analyst for MACH Designs Performance Analyst for MACH Designs The Performance Analyst is a static timing analysis tool that enables a user to quickly determine the performance of MACH designs implemented in ispDesignExpert Worst case signal delays are reported in a graphical spreadsheet format that can be filtered by the user to verify the speed of critical paths and identify performance bottlenecks The Performance Analyst traces each logical path in the design and calculates the path delays using the device s timing model and worst case AC specs supplied in the device data sheet The Performance Analyst performs six distinct analysis types fMAX tSU tPD tCO tOE and tCOE Timing threshold filter source and destination filter and path filter can be used to independently fine tune each analysis Analysis Types There are six types of analysis you can perform using the Performance Analyst The first type fMAX is an internal register to register delay analysis fMAX measures the maximum clock operating frequency limited by worst case register to register delay The remaining five types are external pin to pin delay analysis The following describes these types fMAX Maximum Clock Operating Frequency The fMAX path trace analysis reports the worst case f MAX maximum clock ope
50. 1 Select the device in the Sources in Project field of the Project Navigator window and observe the related processes lf you have chosen an ispLSI device the ispDesignExpert software has several user controls that can be accessed from the Project Navigator highlight Compile Design and click the Properties button at the bottom of the Navigator window The Compiler Properties dialog box Figure 4 9 Figure 4 10 Figure 4 11 with compiler settings device options and UES in it appears See the ispEXPERT Compiler User Manual or online help for explanations If you have chosen a GAL device you can also access some design properties highlight the Fit Design process and click the Properties button to open the Fit Design Properties dialog box Figure 4 19 with design settings Refer to the online help for more information on these properties Custom Finer m Run Doublg click on the salectad nam o logga rs tiere use fe migon and pss T o F crouse the combo bozio seie Figure 4 19 Fit Design Properties Dialog Box for GAL Designs Double click the Compile Fit Design process or click the Start button The ispDesignExpert Process dialog box appears The ispDesignExpert finishes compiling the source then links the source files together Finally the software partitions and fits the design into the target device Note that check marks have been added to Compile Fit Design process that have been successfully completed Figure 4 20
51. 23 Use extended routing 122 Use global reset 120 Use internal tristate IO driver advanced 124 XOR 120 ispLSI device options 125 ISP 125 ISP except Y2 125 Lowpower 126 Security 125 TOE AS O 126 Y1 as reset 126 J JEDEC simulation GAL PAL run 148 L Lattice Logic Simulator for ispLSI GAL 137 invoke 141 stand alone mode run 141 Log simulation 140 Lowpower ispLSI device option 126 M MACH global optimization options 128 Balance partitioning advanced 129 Boolean logic reduction 129 Boolean logic synthesis 129 Collapse all nodes for speed 130 Collapse selective nodes for area 130 D T synthesis 130 Maximum 96 macrocells per block used 131 Maximum of block inputs used 131 Pack design 128 Product term collapsing 130 Product term equation splitting 130 Index Set Reset don t care 130 Spread design 128 Spread placement advanced 129 Macro add to schematic 46 Maximum of block inputs used MACH global optimization option 131 Maximum 96 of macrocells per block used MACH global optimization option 131 Maximum GLB inputs ispLSI compiler property 121 Maximum GLB outputs ispLSI compiler property 121 Menus pop up in Signal Navigator 156 Minimize GLB levels for all paths advanced ispLSI compiler property 124 ModelSim Simulator 149 N Net names add in schematic 48 Nodes assigning properties to 97 O Open Design File menu function in Simulator Control Panel 141 Open Stimulus File menu
52. 3 ORG Rd REOR REOR eA Ee ln eh dal hd 128 Global Optimirallaft iiia aueh dior Rae dd RR ERE herd ambe ded s 128 Pack DESIGN a ne ee ee ee ee een eer eee re re eee ee wee ee 128 Bp DOS oc sirrin stiate Adv aren e Side 5 oe a 625 a dde 128 Advanced ngo ETT PP 129 Log PDA 2453 3 d dci doi Eolo OE Ro ob ddnde bab RE belio do BP od dnbie edat a dod 129 Boolean Logic Synthesis ag Rack ed d CIR Ue SORE OR d dedo e oe RRR RRO 129 LET BN cen adea e Rd e dE RIS dauid td d d di Ead du Bd a cd db T 130 Set Reset Don t Care 0 0 enn 130 NOUS LOBOS Liansna nds ad ed xd dis adore d 6 PR dera ninni Mal idc add 130 PUG Term Collapsing artrita br bok GR ER RE So GE RC RCR IDE NDA Ie ER ee ed op d ERE 130 Product Term Equation Splitting doe se keke Re CRESCE per EROR EC OR OR el 130 Muse js PPP Fr 130 Maximum of Macrocells per Block Used 20000 eee eee 131 Maximum of Block Inputs Used 2 2 12 ec sna eeeudeu ker sec daabceenuae ue 131 Compiling Fitting the ispLSI GAL Design 0060 c cee eee 132 Compiling Fitting the MACH PAL Designs 2 000 eee 134 Chapter 5 Design Verification 022 cece eee 136 Lattice Logic Simulator Tor ispLSI GAL occc siren kandtewacietanes da E RA RARE ERR RE ea 137 CRUDUM LL ou ed ancien eidododosua Qe e erii Boni sce Lol aedi ond pete eet ida Dod dou sca ea at 137 Creating Test Stimulus for Lattice Logic Simulator
53. 4 211 mntity muzzxivhd is pert 2 cut atd logie a b B1 im mtd logic 1 re murzxl arch of murzzxlvhd is Rech Howen DOS PES Figure 3 20 Text Editor with Sample VHDL Module File ispDesignExpert User Manual 54 VHDL Design To create a new VHDL module 1 Choose Source New from the menu bar The New Source dialog box appears Figure 3 21 The project type Schematic VHDL is shown in the title bar of the dialog box letting you double check your project type before creating the source files ABEL Tel vedo Schemes Lise Document Waaka Tail Frdura WHOL T r Bence Wakari Skmaulus Figure 3 21 New Source Dialog Box 2 In the New Source dialog box choose VHDL Module and click OK The Text Editor window appears together with the New VHDL Source dialog box Figure 3 22 v Text Editor File View Templates Tools Options Help esd 2 ST T5 T5383 Yl a E B C New VHDL Source Eile Name D Entity Architecture Figure 3 22 Text Editor Window with New VHDL Source Dialog Box 3 In the New VHDL Source dialog box enter relevant contents into the text fields 4 Click OK The new VHDL file appears in the Text Editor window 5 Use the items in the Edit menu to cut copy paste or replace text ispDesignExpert User Manual 55 VHDL Design Create an EDIF File for ispLSl Before fitting your VHDL design into an ispLSl part you will need to create a ed file for input to t
54. CH and PAL devices Add a Verilog HDL Module to Your Design To add a Verilog HDL module to a design you can either import a v file or create a new Verilog HDL module file in the Text Editor To import a Verilog HDL module to your design 1 Choose Source Import from the menu bar The Import File dialog box appears The project type Schematic Verilog HDL is shown in the title bar of the dialog box letting you double check your project type before importing the source files 2 In the Import File dialog box select the desired v file Click OK 3 The selected Verilog HDL file appears in the Sources in Project list of the Project Navigator as shown in Figure 3 24 linpLersqnExpesi Project Pervigator DCMESPTODLSVESPSYSVECXAMPLE Mm E Source Grocer Options Cedmw Toole Hep J Se ie vrbs Tasi Fixture Daclarnlinna EyvHDL Test Bench Templain Duke chsk open ee selected binte Deuh etiek he Ramon he kii a emad he ioe to sigs o pat _Hew_ _Cpen__ me Mee eres tows Ready Figure 3 24 Project Navigator Window with v File Imported Highlight the Verilog HDL icon and use the text editor to view the syntax of the Verilog HDL module Figure 3 25 ispDesignExpert User Manual 57 Verilog HDL Design Figure 3 25 Text Editor with Sample Verilog HDL File To create a new Verilog HDL module 1 Choose Source New from the menu bar The New Source dialog box appears Figure 3 26 The proj
55. Chapter 1 Introduction NOTE Indicates a special note A CAUTION Indicates a situation that could cause loss of data or other problems TIP Indicates a special hint that makes using the software easier gt Indicates a menu option leading to a submenu option For example View gt Toolbar ispDesignExpert User Manual 11 Related Documentation Related Documentation In addition to this manual you might find the following reference material helpful ispDesignExpert Getting Started Manual ispDesignExpert Release Notes Design Verification Tools User Manual Schematic Entry User Manual ABEL Design Manual ABEL HDL Reference Manual ispLSI Macro Library Reference Manual 5K 8K Macro Library Supplement ispEXPERT Compiler User Manual ISP Daisy Chain Download User Manual ispDOWNLOAD Cable Reference Manual VHDL and Verilog Simulation User Manual Synplicity Synplify User Guide These manuals provide technical specifications for the ispDesignExpert software They give helpful information on device use and design development They are located in the manuals directory on the CD ROM The ispDesignExpert Help menu also provides access to the manuals ispDesignExpert User Manual 12 Chapter1 Introduction The ispDesignExpert software provides support for the isoLSI GAL MACH and PAL device families under the ispDesignExpert Project Navigator The software contains all executable libraries and device support lists nec
56. DesignExpert User Manual 143 Equation Simulator for MACH PAL Equation Simulator for MACH PAL Overview Equation Simulator is a design verification tool enabling you to verify your ABEL HDL or schematic designs with a MACH or PAL device Equation simulation is similar to Functional simulation uses design test vectors that you supply to simulate the design logic or equations independent of any device The more comprehensive and detailed your test vectors are the more useful your simulation results will be Equation simulation can be conducted before you select a device It only tests the equations in your design as specified by test stimulus ABEL HDL test vectors Creating Test Vectors for Equation Simulator You need to create test stimulus with ABEL test vectors before you do equation simulation for a MACH or PAL design You can specify the test vectors in the way described on page 137 When using test vectors you specify the required input pattern and the expected outputs at the device pins and buried nodes The simulator applies inputs from the test vectors to the simulated circuit and compares the simulated output with the output specified in the test vectors If there is any difference an error is indicated Running the Equation Simulation Equation Simulation similar to Functional Simulation tests your design without using device specific information Equation Simulation can be conducted before you select a device However
57. Execute commands from the keyboard by pressing the Alt key and the letter underscored in the menu called the hot key For example to execute File Open Project press and hold the Alt key and press F and O The ellipsis following some of the menu items in the pull down menus indicate that a dialog box appears when this menu item is selected Toolbar The toolbar contains functions found in the menu bar The toolbar icons provide a quick and easy way to access the most commonly used features of the ispDesignExpert The toolbar icons and their equivalent menu bar functions are discussed in the online help You can use View Toolbar to display or hide the toolbar Sources Window The Sources window on the left side of the Project Navigator shows all the design files associated with a project listed in their logical hierarchical order Each object in the list is identified with an icon For example at the top of the Sources window is the Project Notebook it is denoted with the Project icon To see all the objects in the project use the scroll bar at the right edge of the Sources window to move up and down in the list There are several kinds of design sources in ispDesignExpert including schematics ABEL HDL modules VHDL modules Verilog HDL modules EDIF netlists and couple test stimulus files for simulation Listed below Table 2 1 are the acceptable sources for a project When you begin a new project there will be no sour
58. File Associations option is enabled checked document sources use Windows file associations for non Project Navigator sources e The Source Window Width in number of characters of the Sources window The Project Navigator uses this value and the average character width of the currently selected font to determine the width of the Sources window The recommended available range is from 20 to 60 characters Three mutually exclusive options for Process Force are Auto make One Level and Full e f you choose Auto make option the Project Navigator will use the auto make instructions when a process is started e f you choose One Level option the Project Navigator always runs the last step for a process regardless of the auto make state e f you enable Full option the Project Navigator always runs all steps for a process regardless of the auto make state Two options are set in the System Settings area e f Fast Redraw is enabled the Project Navigator display is altered to speed up screen redrawing For example 3 D controls are displayed as 2 D If this option is disabled normal screen drawing is performed e The Update on Editor Save option specifies whether the Project Navigator should update the Sources window hierarchy when you save a source file from the Text Editor or the Schematic Editor ispDesignExpert User Manual 35 Cleaning Up a Project In the DOS Processes area Iconic
59. Hierarchy The schematic definition for the latch circuit contains both local and external nets The output of the inverter is connected to the AND gate with a local net Two other local nets connect the outputs of the AND gates to the inputs of the OR gate Assume these nets have been named N1 N2 and N3 When16 copies of this circuit are combined in reg16 16 copies of these local nets are created The 16 local nets named N1 are individual nets not branches of the same net so the Hierarchy Navigator creates a unique name for each The local net name N1 is prefixed with the instance name of the schematic where the net is defined A dash separates the net and instance names The 16 N1s then become Rl1 L1 N1 R1 L2 N1 R4 L3 N1 R4 L4 N1 The latch schematic contains three external nets D ENABLE and Q The symbol pins on the latch connect these nets to the hierarchical level mentioned above ispDesignExpert User Manual 85 Hierarchical Design Automatic Aliasing of Nets When a design is loaded into the Hierarchy Navigator nets take the name of the highest top level net in the design That is the name of top level net propagates downward through the hierarchy to override the local name By forcing all nets to the same name this aliasing feature greatly speeds signal tracing in a multi level design In the preceding example the net name D from the latch is overridden by the higher level external reference to become D1
60. LOITRhERUTETCHEMURISEDRUBNURTERADDBIESTER TED EE ME x Ede Mee Garne Goocewe Options yiedow Tools biaip CEE Sem fore Jama Biapl 8IB3E4V 125LH3E8 Fi Cositr int kariga Myton hog abl O Compile Desige Ej ned scii ati lig EDE Fis fy Campilgr Raport X Timing A amp nnlyzss K Timing Expniurer Dy Maximum Frequency Fra port Z Setup Hold Report Tp Mapari E Ropon R Physical Vemenr R EP Deny Chain Download Dudhk chekta ghaois a diawal dese Deunlu tkck he mamon h kal Gr select he Start baton m oan thee piocesz Sulactthia Siea patton tra PE pes md verre Shee Mew ren Seven e ios Hierarchy is up tu date Figure 3 34 Hierarchical ABEL HDL Design To instantiate a lower level module in an ABEL HDL module 1 In a Text Editor open your ABEL HDL file File Open or create a new ABEL HDL file File gt New 2 In the ABEL HDL file use the interface and functional block keywords to instantiate lower level files You can place multiple instances of the same interface in the same design by using the functional block statement The interface must have the same names as the corresponding nets schematics or pin names ABEL HDL in the lower level module ispDesignExpert User Manual 69 Hierarchical Design ABEL HDL Hierarchy Examples Figure 3 35 below shows an upper level ABEL HDL module top ab1 that refe rences either a lower level ABEL HDL module add ab1 Following that Figure 3 36 show
61. Lattice y Ez rsrs ss Semiconductor TTTTI Corporation ispDesignExpert User Manual Version 8 0 Technical Support Line 1 800 LATTICE or 408 428 6414 DE UM Rev 8 0 1 Copyright This document may not in whole or part be copied photocopied reproduced translated or reduced to any electronic medium or machine readable form without prior written consent from Lattice Semiconductor Corporation The software described in this manual is copyrighted and all rights are reserved by Lattice Semiconductor Corporation Information in this document is subject to change without notice The distribution and sale of this product is intended for the use of the original purchaser only and for use only on the computer system specified Lawful users of this product are hereby licensed only to read the programs on the disks cassettes or tapes from their medium into the memory of a computer solely for the purpose of executing them Unauthorized copying duplicating selling or otherwise distributing this product is a violation of the law Trademarks The following trademarks are recognized by Lattice Semiconductor Corporation Generic Array Logic ISP ispANALYZER ispATE isoCODE ispDCD ispDOWNLOAD ispDS ispDS ispEXPERT ispGDS ispGDX ispHDL ispJTAG ispSmartFlow ispStarter ispSTREAM ispSVF ispTA ispTEST ispTURBO ispVECTOR ispVerilog ispVHDL ispVM Latch Lock LHDL pDS RFT and Twin GLB are trademarks of Lattice Semicond
62. O symbols I O symbols Any output symbol Supported Devices All 1000 2000 3000 5000V 8000 1000 2000 3000 6000 All 8000 8000 2000E 2000V 2000VE 5000V 8000 5000V All 1000 2000 3000 6000 All 100 ispLSI Design Attributes Supported Attribute Purpose Syntax Applies To Devices Voltage Marks I O symbols to VCC or VCCIO I O symbols 5000V be programed to VCC or VCCIO Two other attributes available in the Schematic Editor control pin assignment and schematic logic optimization Attribute Purpose Syntax Applies To SynarioPin Tags I O pad with pin number pin number or pin name O symbols SynarioSrcType Marks a symbol as External or blank Block symbols representative of a module not in the current project Precedence of Design Attributes When several Design Attributes are used in a design they are all honored as long as they do not conflict or overlap If they conflict one or more of the Design Attributes will be ignored depending on the design If they overlap one Design Attribute can override other Design Attributes Table 3 1 groups Design Attributes in their order of precedence when relating to the same logic A Design Attribute with a higher precedence for example 1 overrides those with lower precedence for example 5 A Design Attribute with the same level of precedence will generally not override another unless they conflict Table 3 1 Design Attribute Precedence
63. RTY CLK CLKA CLK1 ispDesignExpert User Manual 98 ispLSI Design Attributes ISpLSI Attribute Processing Attribute BFM Clock type Group Preserve XOR SAP EAP SCP ECP SLP ELP SNP ENP STP ETP Use XOR Optimize Protect The ispDesignExpert makes use of schematic attributes by embedding them within the file compiled from the schematic as PLSI PROPERTY statements Attributes available for nets are all similar though the attributes available for a particular symbol are dependent upon the symbol type The attributes are shown in the table below The attributes available for a particular symbol are dependent upon the symbol type Supported Purpose Syntax Applies To Devices Places the logic of a signal_name Net 8000 specific net into one lt BigFastMegaBlockl bigfastmegablock ndex gt Assigns ispLSI clock CLKO CLK1 CLK2 Net All type CLK3 IOCLKO IOCLK1 FASTCLK SLOWCLK Marks net to be Identifier Net 1000 2000 included in a group 3000 6000 Marks net to be Y or N Net All preserved Defines user defined ON or OFF Net 5000V 8000 XOR gate Marks begin or end of S identifier or Net All Asynchronous path E identifier Marks begin or end of S identifier or Net All Critical path E identifier Marks begin or end of S identifier or Net 5000V 8000 LowPower path E identifier Marks begin or end of S identifier or Net All No Minimize path E identifier Marks begin or end of S identifier or Net 5000V 8000 Turb
64. To delete both intermediate and report files for the current project choose File gt Clean Up All Saving a Project To save a new project choose File Save As The Project Navigator prompts you for a file name for the project ispDesignExpert User Manual 36 What is Saved Saving a Project Saving a project saves a project file syn extension with the following information m The title of the project m The sources in the project m Matching Symbol files these are sym files with the same name as their relevant modules in the design source matching symbols are used as functional blocks in schematics to represent a lower level module m Constraint files ispDesignExpert also tells the Schematic Editor and the Text Editor to Save at the same time you save a project When you choose Save As to save a project to another directory ispDesignExpert copies all of the project files to that directory Tips for Saving and Naming Projects Use the following guidelines when saving and naming source files and projects m Do not save more than one project in the same directory m Avoid saving a project that has the same base file name as one of its sources If a source and project have the same base name you may have problems with the Project Navigator s Auto make feature For instance avoid calling your project myFile synifit contains a source named myFile abl Reserved File Names ispDesignExpert reserves several filename
65. able the Setup and Hold Table the Tco Table the Tpd Table This option does not let you select the Path Analysis information and report types that you can set when you set the Timing Analyzer Settings and run Timing Analysis from the Tools menu of the ispEXPERT Compiler as a separate procedure Parameter File The Parameter File option specifies the name of an optional Parameter File for the compiler to use for compilation specifications The Parameter File contains alternate sets of Compiler Options and Device Options that can be used to run different iterations of your design You can create this file using an ASCII text editor The Parameter File name should have a par extension and must be different from the design name When a Parameter File is used all relevant files and parameters are passed to the appropriate ispDesignExpert software modules Once a design is routed ispDesignExpert merges the various report files into a report file design rpt anda log file design 1og containing messages warnings or errors issued by ispDesignExpert ispDesignExpert User Manual 123 ispLSI Compiler Properties Interfaces Dialog Box Click on the Interfaces button in the Settings tab The Interfaces dialog box appears Figure 4 12 You can specify the output netlist format that is to be generated for the post route simulation The possible values are EDIF VHDL Verilog and LMC No default value is set for this option Intereses C
66. ailed schematic or Verilog HDL module at the next lower level 2 To add a block symbol that represents the lower level schematic mux2x1 sch in this schematic choose Add Symbol to open the Symbol Libraries dialog box Select Local from the library list then select the target symbol mux2x1 If mux2x1 is not available from the Local symbol library generate it upon the sub level module mux2x1 sch Refer to page 50 for more details on how to create a symbol 3 Move the pointer back over to the Schematic Editor Notice that the symbol you selected is attached to the pointer Place the symbol by clicking on the schematic 4 Move the cursor back to the Symbol Libraries dialog box and select another target symbol mux2x1v Place the symbol in its proper position on the schematic 5 From the Schematic Editor menu bar select relevant menu items to add wires net names and I O markers for the schematic ispDesignExpert User Manual 80 Hierarchical Design NOTE You must generate a symbol file for the lower level schematic or the lower level Verilog HDL module before you create the upper level schematic Refer to the Schematic Entry User Manual for details on how to generate a symbol Schematic Verilog HDL Hierarchy Example Figure 3 49 shows the upper level schematic mux4x1 sch that references a lower level schematic and a lower level Verilog HDL module Following that Figure 3 50 shows the lower level schematic mu
67. al Pins l Bun Cancel Edit Figure 3 39 New Block Symbol Dialog Box 4 When you are finished click Run The new symbol attaches to the cursor and is ready for placement 5 Click in the schematic sheet to place the new Block symbol Figure 3 40 To end the symbol entry process right click anywhere in the sheet Figure 3 40 New Block Symbol Add Schematic Hierarchy Examples Figure 3 41 shows an example of how the new symbol corresponds to an underlying schematic In this figure pin A on the Block symbol corresponds to the net in the schematic which is also named A The other pins B Cl Carry In CO Carry Out and SUM also correspond to named nets in the schematic Figure 3 41 A Block Symbol and its Underlying Schematic ispDesignExpert User Manual 74 Hierarchical Design Figure 3 42 shows one top level schematic and different ways to implement the lower level modules gt p Om feo E Fis Figure 3 42 Top level Schematic for Top NOTE If you are in a lower level schematic you can click Use Data From This Block button in the New Block Symbol dialog box to automatically create a functional block symbol for the current schematic The name of the lower level schematic must match the block name schematic or the interface name ABEL HDL in the upper level module This associates the lower level module with the symbol representing it For example the schematic
68. ally be generated and saved under the current project directory Refer to page 50 for more information on how to create a symbol 8 Click Run Follow step 5 to 9 on page 89 to complete adding the symbol to your design Schematic and Verilog HDL Mixed Entry You can use the ispDesignExpert software to create a Verilog HDL file and then connect it to the schematic from the previous steps for a top level schematic Make sure schematics are not instantiated by Verilog HDL sources This complete design will be simulated and compiled into an ispL Sl device Add a Verilog HDL source file to your project in the same way as adding a VHDL source file ispDesignExpert User Manual 95 ispLSI Design Attributes ispLSI Design Attributes ispLSI Design Attributes can only be applied to ispLSI designs in ispDesignExpert They will affect how the ispDesignExpert implements your ispLSI design When you assign Design Attributes the compiler uses them as local design assignments Design Attributes can be set in a schematic an ABEL HDL file or in an EDIF property file Assigning ispLSI Design Attributes in Project Sources In Schematics Attributes in schematics are used to describe the characteristics or properties belonging to or associated with a symbol pin or net Attributes only apply to describing characteristics in schematics There are two types of attributes used in the Schematic Editor symbol and net Symbol attributes describe feat
69. and evaluating the results 1 In the Analysis field of the Performance Analyst click Run The Performance Analyst calculates the delay paths according to the options you have chosen and displays them in the table Figure 6 17 Figure 6 17 Performance Analyst Calculating the Delay Paths 2 You can analyze individual timing components used to calculate the timing path by double clicking on the field to open the Expanded Path dialog box Figure 6 18 Expanded Paths Dialog Box 3 Click Ok to close the Expanded Paths dialog box 4 You can print an entire analysis report by clicking the Print icon in the Toolbar or by selecting File Print Also you can print the timing results of individual paths by clicking Print button in the Expanded Path dialog box ispDesignExpert User Manual 168 Performance Analyst for MACH Designs Running Timing Analysis in Batch Mode There may be times when you want more precision and flexibility while running timing analysis than is available with the Performance Analyst graphic user interface For example on the Options dialog you can select Bidirectional path tracing as either on or off However this selection applies to all Bidirectional I O s in design There is no way to select an individual one or a partial set Or in another example six fixed groups cover the total path traces allowed by the user interface There is no way to report a path between two arbitrary points in a d
70. arranty period contact Lattice Semiconductor Corporation at Phone 1 800 LATTICE Fax 408 944 8450 E mail applications latticesemi com If the Lattice Semiconductor support personnel are unable to solve your problem over the phone we will provide you with instructions on returning your defective software to us The cost of returning the software to the Lattice Semiconductor Service Center shall be paid by the purchaser Limitations on Warranty Any applicable implied warranties including warranties of merchantability and fitness for a particular purpose are hereby limited to ninety days from the date of purchase and are subject to the conditions set forth herein In no event shall Lattice Semiconductor Corporation be liable for consequential or incidental damages resulting from the breach of any expressed or implied warranties Purchaser s sole remedy for any cause whatsoever regardless of the form of action shall be limited to the price paid to Lattice Semiconductor for the Lattice Semiconductor software The provisions of this limited warranty are valid in the United States only Some states do not allow limitations on how long an implied warranty lasts or exclusion of consequential or incidental damages so the above limitation or exclusion may not apply to you This warranty provides you with specific legal rights You may have other rights which vary from state to state ispDesignExpert User Manual 3 Table of Contents
71. art from the Process menu To fit the design 1 In the Sources window select the Target Device 2 Figure 1 12 In the Processes window select the Compile Design or Fit Design process ElispDesignExpert Project Navigator D ISPTOOLS ISPSYS EXAM cix File View Source Process Options Window Tools Help Strategy Normal Sources in Project B test ispLSI1032E 100LJ84 clock wdl E clocktop abv P clocktop clocktop sch control control sch S HOURS hours abl Esseg sseg abl MINUTES minutes abl E sseg sseg abl F PRESCLR presclr abl F seccntr seccntr abl Processes for Current Source A Constraint Manager tw Compile Design ig JEDEC File S Compiler Report Qr Timing Analysis X Timing Explorer E Maximum Frequency Report S Setup Hold Report S Tpd Report S Tco Report X Physical Viewer ISP Daisy Chain Download Double click to choose a different device New Open Double click the item in the list or selectthe Start button to start the process Select he Properties button to start the property Start view Properties Lag Ready Figure 1 12 Project Navigator Compile Design Process 3 Start the processing in one of these ways Choose the Process gt Start menu item Click the Start button at the bottom of the Project Navigator window Double click the process label Compile Design or Fit Design 4 The Project Nav
72. cal design and it will be automatically linked and merged into the final netlist to be passed on to the ispEXPERT Compiler Be cautious when using properties in lower level modules that are instanced more than once Project Navigator does not interpret unique names given in certain properties such as the user defined path name used in the Asynchronous Path property If a module uses a property such as this and is instanced more than once the netlist file will reflect more than one path using the same name and this will cause a fatal error during fitter processing In cases such as this it is best to modify the lower level source to bring the required nodes up to the level of instantiation so that truly unique names can be given for each instance Consider the following schematics Pe am ui D1 ES LL ta 89 E S PATH1 iis CE PATH d s di Panli L U3 U6 A FB Figure 3 62 Sample Case This first schematic shows a top level design with a subfunction called SUBFUNC There are two DUMMY pins on the symbol from which nets are drawn and the desired attributes in this case the beginning and the end of a No Minimize path are attached The schematic for the lower level function is shown below gt O U2 See eS ii U6 e tu S por ET I vs gt Io A L nem EE E eU BB _________ DUMMY1 gt DUMMY gt F
73. ces except for the Project Notebook ispDesignExpert User Manual 26 About the Project Navigator Table 2 1 Acceptable ispDesignExpert Project Source Files Source Type Icon File Extension Syn Target Device Document Source wri dOS txt xls hlp prp par or any extension not recognized by the Project Navigator Schematic Source ABEL HDL VHDL Verilog HDL Waveform Stimulus VHDL test bench Undefined or incorrect source reference Any E ispDesignExpert User Manual 27 About the Project Navigator Source Hierarchy One source file in a project is the top level source for the design which can be an HDL module or schematic The top level source defines the inputs and outputs that will be mapped into the device and references the logic descriptions contained in lower level sources The referencing of another source is called instantiation Lower level sources can also instantiate sources to build as many levels of logic as necessary to describe your design NOTE If you build a project with a single source that source is automatically the top level source Processes Window The Processes window on the right side of the Project Navigator shows all the processing tasks that apply to whatever object or file is highlighted in the Sources window on the left side A processing task includes netlisting compiling logic reduction logic synthesis placement and routing
74. chematics are not instantiated by VHDL sources Create a VHDL Source File You have previously created a top level schematic Now you need to create a VHDL source file to link it to the symbol of the top level schematic To add a VHDL source file to your project 1 Highlight the top source in the Sources window Then select Source New In the New Source dialog box check the project type from the title bar of the dialog box Choose VHDL Module and click OK The Text Editor window appears with New VHDL Source dialog box In order for the file to be linked to the symbol the Module Name must match the symbol name The File Name does not need to match the symbol name Fill in the text fields with relevant contents Click OK You will now be in the Text Editor and will see the VHDL framework already started for you Enter your design in the Text Editor window Select File Save then File Exit Notice in the Project Navigator that the icon next to the source has changed This means you have a VHDL file associated with this source and it is linked correctly Now you have a sub level VHDL source file for your mixed Schematic and VHDL design The next step is to create a symbol for the VHDL source you just created To add a symbol to your top level schematic 6 Open the top level schematic in the Schematic Editor Select Add New Block Symbol The New Block Symbol dialog box appears Figure 3 61 New Block Sy
75. clock path delay shortest data path delay internal hold time For simplicity in the Timing Analysis spreadsheet tHD will be shown as a 0 if the calculation is negative regardless of its value However the exact hold time can be observed on the Expanded Delay Path window which is opened by double clicking on the spreadsheet cell Figure 6 10 Tracing tSU at D T CE CLOCK and S R ispDesignExpert User Manual 163 tPD Performance Analyst for MACH Designs Register D T Inputs Reports tSU tHD at Register data input D T Register CE Inputs Reports tSU tHD at Register Clock Enable CE Register Asynch S R Inputs Reports Recovery time at Register Set Reset Propagation Delay Time The tPD path trace analysis reports input pin to output pin delay of combinatorial signals You can specify whether reporting is enabled for paths traced through asynchronous register inputs and transparent latches Default tPD Path Trace tCO This path starts at an input pin and traces through any number of levels of combinatorial logic through the data path of the output buffer to the output pin Combinatorial gt m Lm c OgIC ates L M Figure 6 11 Default tPD Path Tracing Clocked Output to Pin Time The tCO path trace analysis reports clock to out delay starting from the primary input going through the clock of flip flops or gate of latches and ending at the primary output You can specify w
76. could be repeated by using the Schematic Editor s File Matching Symbol command or File Generate Symbol command if the corresponding naf file has been generated to create a symbol for schematic reg4 then placing the reg4 symbol in a higher level schematic If you created a schematic for a 16 bit register reg16 by placing four copies of symbol reg4 you would be defining a circuit with a total of 64 gates But instead of having to view 64 gates on a single level you can work with symbols that represent gates at the appropriate level of detail ispDesignExpert User Manual 83 Hierarchical Design Hierarchical Naming In the latch schematic Figure 3 52 the inverter has the instance name 11 In schematic reg4 four copies of the symbol latch are placed and assigned instance names L1 through L4 Schematic reg4 therefore contains four copies of inverter 11 The Hierarchy Navigator distinguishes among these otherwise identical inverters by combining the inverter s instance name with the instance name of the latch containing it The four inverters are therefore named in the Hierarchy Navigator L1 L2 1 HISE L4 11 If we created a 16 bit register by combining four reg4 symbols the resulting schematic would represent a new hierarchical level containing four copies of reg4 named R1 through R4 Each copy of reg4 contains the four inverters as named above The Hierarchy Navigator would then name the 16 inv
77. ct Navigator with an Open Project The ispDesignExpert is a design entry tool You must create or open a project to begin working Only basic menus are available until you open or create a project Once you do all the menu options display ispDesignExpert User Manual 14 Creating a New Project Creating a New Project After starting the Project Navigator you can create a new project Design projects are made of one or more sources which can be ABEL HDL files VHDL files Verilog HDL files schematics test vector files waveform stimulus VHDL test bench files Verilog test fixture files or documentation files A new project can be created by selecting existing ABEL HDL VHDL Verilog HDL files or Schematics and using the Project Navigator menus to import the existing source s or by creating new sources from within the Project Navigator You need to specify the type of the project by choosing Schematic ABEL Schematic VHDL Schematic Verilog HDL or EDIF from the Project Type field To create a new project 1 Choose File New Project to open the Create New Project dialog box 2 Go to the directory in which you want to place your project files and then type a name for your project The default project name is unt itled syn ln this example go to the lt drive gt lt isptools_path gt lt ispsys_path gt examples test directory 3 Create a new folder called test Then go into this folder and name the project file test sy
78. default all user defined XOR gates are expanded unless a local XOR attribute has been specified This option is only supported on ispLSI 5000V and 8000 devices ispDesignExpert User Manual 120 isoLSI Compiler Properties Maximum GLB Inputs The Maximum GLB Input option specifies the maximum number of GLB inputs the compiler is allowed to use for each GLB This applies to every GLB in your design The values and default for each device family are shown in the following table Device Family Range Default Value ispLSI1000 and 2000 2 to 18 16 ispLSI 3000 and 6000 2 to 24 24 ispLSI 5000V 34 to 68 68 ispLSI 8000 22 to 44 42 Maximum GLB Outputs The Maximum GLB Outputs option specifies the maximum number of GLB outputs the compiler is allowed to use for each GLB This applies to every GLB in your design The values and default for each device family are shown in the following table Device Family Range Default Value ispLSI 1000 2000 3000 1 to 4 4 and 6000 ispLSI 5000V 32 32 ispLSI 8000 20 ispDesignExpert User Manual 121 isoLSI Compiler Properties Free All Pin Locks The Free All Pin Locks option instructs ispDesignExpert to either ignore or honor the pin locking attributes in your design This option is the same as the IGNORE_FIXED_PIN parameter file option m Turn on Free All Pin Locks so the compiler will ignore the pin locking attributes in your design This allows the compiler t
79. ditor NOTE In order for Windows file associations to work properly with ispDesignExpert in the Project Navigator choose Options Environment Then under Window Settings select Use File Associations Schematic Editor Use the ispDesignExpert Schematic Editor to edit a schematic source You can open the Schematic Editor in these ways m Inthe Project Navigator choose Window gt Schematic Editor m Double click the schematic source name m Select the schematic source and choose Source gt Open m Select the schematic source and then click Open at the bottom of the Project Navigator The Symbol Editor the Hierarchy Navigator and or the Hierarchy Browser work in conjunction with the Schematic Editor You can open the Symbol Editor from the Schematic Editor toolbar or on the Project Navigator Window menu Text Editor The Text Editor provides several macros and templates to help you enter and edit test stimulus and behavioral modules written in ABEL HDL VHDL or Verilog HDL You can open the Text Editor in these ways m Inthe Project Navigator choose Window Text Editor m Double click the text source name m Select the text source and choose Source gt Open m Select the text source and click Open at the bottom of the Project Navigator Also you can use any ASCII editor to edit behavioral modules ABEL test vectors VHDL test benches and Verilog test fixtures Then you can import them into your proj
80. e Dialog Box 3 Click Open If you have selected an ispLSI or GAL device the EDIF Reader Settings dialog box appears Figure 3 30 If you have selected a MACH or PAL device the Import EDIF dialog box displays Figure 3 31 Both dialog boxes are used to specify the vendor whose tool was used to prepare the design file and to specify settings to be used when the EDIF design is read into the project EDIF Fante Sonina F Load vendor mpsckr tni Pirsa and Gesutd Sera WC GMD Pepe renisnion G ja r Cell woGMeme fC er GHO Heme zc Cancel Bus Reconstruction Am pie Decking 7 Un C Dn Lammi Syrr cnri Ert E Lok C Figal Fe Qna Fcesiincs output pies Figure 3 30 EDIF Reader Settings Dialog Box ispDesignExpert User Manual 61 Vendor field VCC and GND Bus Reconstruction Ground Floating Output Pins EDIF Design From the pull down menu select the vendor of the third party software used to create the design If you select Altera the format expands to show the Altera specific fields If you turn on the Load vendor specific defaults check box before selecting a vendor the defaults for the vendor you select display If you do not wish to display the default settings when you change vendors deselect this check box You may make changes after selecting a vendor You can specify whether VCC or GND symbols are represented as Nets or Cells when an EDIF design file is read In the VCC GND Representation area check whether
81. e Notebook icon and Targeted Device icon If the source is a logic description the source is placed in alphabetical order for each level of hierarchy following the project notebook and the targeted device For example if the source is called mu1tiplx and the top level source a schematic called myChip contains a functional block called mult ip1x the source is placed underneath myChip in the Sources window If the source is an ABEL test vector file the source is placed beneath the Targeted Device icon Creating a New Source To create a new source Ts e 3 Choose Source New to open the New Source dialog box New Source ABEL Test Vectors ABEL HDL Module Schematic User Document Verilog Test Fixture VHDL Test Bench Waveform Stimulus Figure 2 5 New Source Dialog Box In the dialog box select the type of source you want to create and then click OK The Project Navigator starts an editor that you can use to enter the information for your new source For ABEL HDL VHDL Verilog HDL ABEL test vector VHDL test bench and Verilog test fixture sources the Text Editor is started For schematic sources the Schematic Editor is started For waveform stimulus sources the Waveform Editor is started In the editor create a source ispDesignExpert User Manual 32 Describing a Project Modifying a Source You can edit any of the sources that make up your project by double clicking on them to open the corresponding e
82. e gt 1ib from the library list then select the target symbol or macro 3 Move the pointer back over to the Schematic Editor notice that the symbol you selected is attached to the pointer Place the symbol by clicking on the schematic 4 Move the cursor back to the Symbol Libraries dialog box and select another symbol Place the symbol in its proper position on the schematic 5 From the Schematic Editor menu bar select Add Wire Click on the output pin of a gate to start the wire Each successive click will bend the wire a double click will end the wire if it is not connected Connect the wire to the input of a gate 6 Repeat the above procedure to add other symbols or macros from the Symbol Library Figure 3 10 is an example of a simple schematic ispDesignExpert User Manual 46 Schematic Design Entry FERES ERE TH Lirtiled Shei I Onions pep J Cole am B E Select A Command Figure 3 10 Building the Schematic 7 Choose File gt Save from the menu bar of the Schematic Editor window to save your design If you cannot find a symbol that you just generated from the Symbol Libraries of the Schematic Editor select Options ispLSI GAL MACH PAL Schematic Configuration from the Project Navigator In the Symbol Paths tab of the Schematic Environment dialog box add the path of the newly generated symbol in the Paths field Then you will be able to add the symbol to your schematic from the Symbol Libraries
83. e right mouse button on a cell in the Source Register or Destination Register columns in the Frequency Table the following additional commands are available m Setup and Hold Table Displays the setup and hold values of the selected register in the Setup and Hold Table m Tco Table Displays the Tco data of the selected register in the Tco Table From a cell in the Register column of the Setup and Hold Table you can access the Tco Table and it will contain a value for the highlighted register From a cell in the Register column of the Tco Table you can access the Setup and Hold Table and it will contain a value for the highlighted register ispDesignExpert User Manual 159 Timing Analyzer for ispLSl Timing Path Report When you select the Report Timing Path command the Timing Path Information Window Figure 6 7 displays The report information varies depending on the table you were in when you requested the report The boundary report displays when you access the Timing Path Report Click the Detailed Report button to switch to the detailed report When the detailed report displays click the Boundary Report button to switch back to the boundary report Click the Display Path button to display the path in the Connectivity window of the Physical Viewer Timing Path Information Boundary Report Point to Point Delay Path Startpoint QI3 Endpoint Q3 Delay 0 00 1 90 data arrival time Shortest Path Name Delay QI3
84. ect Navigator The Hierarchy Browser appears together with the HDL Viewer for you to verify the design if the source you selected is a schematic file double click the Navigate Hierarchy process from the Project Navigator The Hierarchy Navigator displays the underlying logic in the schematic file Compile the ABEL HDL Source File 10 In the Sources in Project field of the Project Navigator select the source ab1 In Processes for Current Source double click on Reduce Logic The Compiler will take care of running the Compile Logic process before it executes the Reduce Logic process When the process is finished your Navigator should match the one in Figure 3 60 ispDesignExpert User Manual 92 Mixed Entry Design SAMPLE PST ul Ui Compila Logic lis pi SITUE 0 880 LII Gi Check Syntan cock wd EjCompiles Lasting E Compiled Equations clocking clockinp sch ini Vor og Test l ifurp Declaration m DURS SpVHER Toat Ranch Templnts Moers Fa Hjern Fai an Reduced E quaitsnns one minutes nbl asig ieg ab B PRESOLA pemsrir nihil Eysucentr arce ah Du ck the item n Be binaria sertis ee iic Figure 3 60 Project Navigator after ABEL HDL Compiling ispDesignExpert User Manual 93 Mixed Entry Design Schematic and VHDL Mixed Entry You can use the ispDesignExpert software to create a VHDL file and then connect it to the schematic from the previous steps for a top level schematic Make sure s
85. ect type Schematic Verilog HDL is shown in the title bar of the dialog box letting you double check your project type before creating the source files Hie Source dan ahg HO x ABEL Tail acie Scheme Ane H3ncumeni Maiky Tasi Pitan WHOL Tesi Bench Wrak Skrmaulus Figure 3 26 New Source Dialog Box 2 In the New Source dialog box choose Verilog Module and click OK The Text Editor window appears together with the New Verilog Module dialog box Figure 3 27 ispDesignExpert User Manual 58 Verilog HDL Design Irch Opiera Heip E EA pan ts ie a E mja me acm Yering Models Figure 3 27 Text Editor Window with New Verilog Module Dialog Box 3 In the New Verilog Source dialog box enter relevant contents into text fields 4 Click OK The new Verilog HDL file appears in the Text Editor window 5 Use the items in the Edit menu to cut copy paste find or replace text Create an EDIF File Before fitting your Verilog HDL design into an ispLSI part you will need to create a edf file for input to the ispEXPERT Compiler The synthesis of the Verilog HDL file will be finalized in this process To a edf file before fitting your design to an ispLSl part 1 In the Project Navigator select the target device icon to display the associated processes in the Processes window as shown in Figure 3 28 ispDesignExpert User Manual 59 Hipp propi Iinuble ciick tn choose a didi eren dene Verilog HDL
86. ect using drag and drop from the Windows Explorer or by choosing Source Import ispDesignExpert User Manual 33 Changing the Environment and Configuration Removing a Source Sometimes you may want to remove a source from a project To remove a source from a project you must use the ispDesignExpert Remove command You cannot remove a source using the Window s Delete command 1 In the Sources window select the source that you want to remove 2 Choose Source Remove ispDesignExpert removes the source from the project Processing a Design A process is a specific task in the overall processing of a source or project Typical processing tasks include netlisting compiling logic reduction logic synthesis fitting the design and simulation To view the available processes for a source select the source Then ispDesignExpert displays the processes for that source in the Processes window Forcing a Process to Run If the process is up to date indicated by a check mark to the left of the process it will not run again You can however force a process to run by doing the following m Choose Process Force to start the highlighted process and run all the steps even if the process is up to date When the process is finished running the Project Navigator displays the selected file if applicable This command allows you to temporarily override the Process Force settings in Options gt Environment to start the highlighted p
87. ed If you need EDIF properties to be imported to ispDesignExpert do the following 1 Choose Tools Import Source Constraint Option Import Source Constraints Option iv Import constraints from design source Disable constraint overwrite warning message Cancel Help Figure 3 33 Import Source Constraints Option Dialog Box The Import Source Constraints Option dialog box Figure 3 33 lets you import constraints such as Location pin code Assignments Group Assignments and Output Slew Rate from source files ABEL schematic VHDL Verilog HDL or EDIF 2 Check Import constraints from design source and click OK When the Import constraints from design source option is selected ispDesignExpert displays a confirmation dialog box prior to implementing the function This confirmation dialog box will appear every time you run the Fit Design process unless you check the Disable constraint overwrite warning message option On the warning message dialog box if you click Yes the constraints from the source files are written into the project constraint file NOTE Constraints from source files and existing constraints in project constraint file are not merged existing constraints are overridden by the new constraints Existing constraints only Location Assignments Group Assignments and Output Slew Rate are affected in the project are cleared regardless if there are constraints in the source file If th
88. ed 131 Maximum of block inputs used 131 Pack design 128 Product term collapsing 130 Product term equation splitting 130 Set Reset don t care 130 Spread design 128 Spread placement advanced 129 H HDL cross probing for ispLSI 140 HDL Viewer use 92 Hierarchical design 67 ABEL HDL 69 example 70 abstract 67 advantages of 67 approach 68 Block symbols 67 Index considerations 83 naming 84 nets 85 aliasing 86 overview 67 rules of creating 68 Schematic 73 example 74 Schematic Verilog HDL example 81 Schematic VHDL example 78 structure 83 techniques 68 Verilog HDL 80 VHDL example 77 Hierarchy modular design 67 vs sheets in schematics 68 Hierarchy Browser use 92 Hierarchy Navigator use 92 l Icons Frequency Table 157 processes 28 project 26 schematic 44 Setup and Hold Table 157 sources 27 Tco Path Table 157 Timing Matrix Table 157 Tpd Table 157 Ignore reserved pins ispLSI compiler property 122 INI files edit 34 Instantiation 28 ISP ispLSI device option 125 ISP except Y2 ispLSI device option 125 ispLSI compiler properties BFM packing advanced 125 Carry pin direction 123 Case sensitive 123 Effort 120 Free all pin locks 122 Ignore reserved pins 122 ispDesignExpert User Manual 172 Maximum GLB inputs 121 Maximum GLB outputs 121 Minimize GLB levels for all paths advanced 124 Parameter file 123 Single PT function packing for routability advanced 125 Strategy 120 Timing Analyzer 1
89. ee 67 Advantages of Hierarchical Design occu ce esti unu Ren hx npn non m REA Rua 67 Hierarchy vs Sheets in Schematics sii 4 54a be odd E ROROEROR ROI RR de po CER CR ER RO RC 68 Approaches to Hierarchical Design iua d aec ee dae dee ee dada ede a Ce d 68 Hierarchical ABEL AMDL Design a o acia d AER ORE ee ON RC ILE e ded de ee 69 ABEL HDL Hierarchy Examples 0200000 cece ees 70 Hierarchical Schematic Deg us es ep curando RSRR RR RRRN EE au EE EG E AREReRER RSS 73 Schematic Hierarchy Examples i ciocrdeu cicigegi dete sol eebocidicegeadee ss 74 Hierarchical VHDL Design i xpi evden o CY RE OR ERE UE QE de tans D EO eee es 77 Schematic VHDL Hierarchy Example iau kackeka ak RC ok Ee Ee en 78 Hierarchical Verilog HDL Design qe cicagca kc or RR XR CR ACC R ERE Rede E or ae de 80 Schematic Verilog HDL Hierarchy Example 0 002 000 e eee eee 81 Hierarchical Design Considerations illii 83 Hierarchical Design SUCU o osas ouod daba d RR i piani Een AER dA Red RE 83 Misc Ns acto GUI eRe EOD EU ORC EE E UR CREADO eR e ie d o ee 84 PES in the Hierarchy our sardo X de der REA EC e ud Cb Jede de Pop d edo uc p ee 85 FUCA Aliasing OI PISIS iucundo cioe i bdo EROR ROC hd R YE loa iC iic 86 Mixed Enty DESO occ dose dadqzebPebeterQ relEbe4 qd qu RU qq aded d dae 4h 87 ispDesignExpert User Manual 5 Schematic and ABEL HDL Mixed EMIV Lc cccstscuced us eeeeiedees Nx mmu ERR 87 Create an ABEL HDL Source File 2o
90. elp Strategy Norma gl Sources in Project ispLSI1032E 100L J84 8 clocktop abv 9 clocktop clocktop sch control control sch HOURS hours abl E sseg sseg abl F MINUTES minutes abl Esseg sseg abl PRESCLR presclr abl seccntr seccntr abl Processes for Current Source Update All Schematic Files B G Link Design Linked Equations OG Reduce Logic i EDIF Netlist X Constraint Manager GCompile Design i JEDEC File E Compiler Report Or Timing Analysis X Timing Explorer E Maximum Frequency Report Double click to choose a different device New Open Double click the item in the list or select the Start button to startthe process Selectthe Properties button to start the property WT Properties Log Ready Figure 1 11 Project Navigator with Target Device Selected isoDesignExpert User Manual 19 Processing a Design Creating a New Project A process is a specific task in the overall processing of a source or project Typical processing tasks include creating a netlist compiling the design reducing and synthesizing the logic fitting the design and analyzing the timing You can run a process on a single source or on the entire project You can view the available processes for a source by selecting the source and the processes for that source appear in the Processes window In general you start a process by selecting a source and then choosing St
91. er Place the symbol by clicking on the schematic Move the cursor back to the Symbol Libraries dialog box and select another target symbol mux2x1vhd Place the symbol in its proper position on the schematic From the Schematic Editor menu bar select relevant menu items to add wires net names and I O markers for the schematic ispDesignExpert User Manual 77 Hierarchical Design NOTE You must generate a symbol file for the lower level schematic or the lower level VHDL module before you create the upper level schematic Refer to the Schematic Entry User Manual for details on how to generate a symbol Schematic VHDL Hierarchy Example Figure 3 45 shows the upper level schematic mux4x1 sch that references a lower level schematic and a lower level VHDL module Following that Figure 3 46 shows the lower level schematic mux2x1 sch and Figure 3 47 shows the lower level VHDL module mux2x1vhd vhd Figure 3 45 Top level Schematic mux4x1 sch JST _1 Lou re Figure 3 46 Lower level Schematic mux2x1 sch ispDesignExpert User Manual 78 Hierarchical Design library ieee use ieee std logic 1164 all entity mux2xlvhd is port z out std logic a b s in std logic end architecture mux2x1 arch of mux2xlvhd is begin process s a b begin case s is when 0 gt Z lt a when 1 gt z b when others z lt X end case end process end mux2xl_arch
92. er if you did not check the View Show Waveforms menu item before running the simulation Select Edit Show in the Waveform Viewer window the Show Waveforms dialog box appears Figure 5 3 Figure 5 3 Show Waveforms Dialog Box ispDesignExpert User Manual 139 Lattice Logic Simulator for ispLSI GAL 6 Select the signals in the Nets field then click the Show button to add the selected waveforms in the display area of the Waveform Window You can also select desired signals to form buses and add them in the view Refer to the Design Verification Tools User Manual for more information on how to create multi signal buses HDL Cross Probing for ispLSI GAL Designs For an ispLSI GAL design you can use the cross probing function between the Waveform Viewer Editor and the Hierarchy Navigator HDL viewer to probe an item after invoking the Hierarchy Browser To probe an item in an HDL source or a schematic 1 Select the top level source from the Sources window of the Project Navigator 2 Double click on the Hierarchy Browser process in the Processes window The Hierarchy Browser will be opened together with the Hierarchy Navigator or the HDL Viewer 3 Run the Functional Simulation or the Timing Simulation process associated with the top level source Select Tools Probe Item then click on a net in the Hierarchy Navigator if your top level source is a schematic or just click on a port signal name in the HDL Viewer if your top
93. ere are constraints in the source file then the new constraints are written into the project constraint file If there are no constraints in the source file then no constraints will be written into the file ispDesignExpert User Manual 66 Hierarchical Design Hierarchical Design A design with more than one level is called hierarchical A single level design is referred to as being flat Converting a section of circuitry to a block makes a flat design hierarchical This is commonly referred to as hierarchical design Overview of Hierarchical Design ispDesignExpert supports full hierarchical design Hierarchical structuring permits a design to be broken into multiple levels either to clarify its function or permit the reuse of functional blocks For instance a large complex design does not have to be created as a single module By using a hierarchical design each component or piece of a complex design can be created as a separate module A design is hierarchical when it is broken up into functional blocks or modules For example you could create a top level schematic describing an integrated circuit In the schematic you could place a Block symbol a Block symbol represents a functional block that provides a specific function of the chip You can then elaborate the underlying logic for the Block symbol as a separate schematic or as a separate HDL module The module represented by the Block symbol is said to be a
94. erters by combining the instance names of the four xeg4 symbols with each of the four instance names of the inverters as follows Riv ble kd RISBAILIl Rlsb3 Il1 Ribas Td R2 Ll 11 R2 02 T1 R2 L3 11 R2 D4 1 RS LIIIT R3 52 Il RIBI IL R3 54 rl RA L1 I1 RA4 L2 I1 RA4 L3 I1 R4 L4 I When you view an individual latch schematic in the Schematic Editor you see the instance names of the gates without the hierarchical context When the schematic becomes part of a larger design and is viewed in the Hierarchy Navigator the instance names include the hierarchical path as shown above to assure their uniqueness If you select the top level schematic source in the Project Navigator double click the Hierarchy Browser process associated The Hierarchy Browser will be opened together with the Hierarchy Navigator if the source is a schematic or with the HDL Viewer if itis an HDL file All the instances will be listed in the Hierarchy Browser Figure 3 53 ispDesignExpert User Manual 84 Hierarchical Design EE Hierarchy Maye guine CLULE TLR 5 Boost EN Fri Ed ew Took DRC Gate Help E H a ip pl Se pies nie wele vj s piae 8 icackragpi y LA escort E iIPRESCLER 16 corral Lal z m DE E H MES Ej ur HO 8 OME E DIES iia g wj aj Zoom Qut Pick Center Paini Figure 3 53 Hierarchy Browser Nets in the
95. esign In addition to using the graphical user interface to run timing analysis you can run the Performance Analyst in batch mode This feature is called the Batch Timer The Batch Timer executes a user predefined command file and puts the result into a log file Refer to the Design Verification Tools User Manual for details of Batch Commands and Batch Timer usage ispDesignExpert User Manual 169 Symbols abl 27 40 92 abv 27 137 location of 137 doc 27 ed 27 edf 56 59 142 edn 142 err 140 hlp 27 ini 34 sch 27 44 50 sim 142 ps 140 wdi 27 137 association of 137 wri 27 Is 27 A ABEL HDL modules add to a design 40 compile 92 create 42 91 import 40 Assigning properties to nodes in ABEL HDL 98 in lower level schematics 97 Attributes ispLSI design 96 assigning in ABEL HDL 98 Index assigning in schematic 97 precedence of 101 processing 99 MACH design 102 assigning in ABEL HDL 103 assigning in schematic 102 syntax in ABEL HDL 103 processing 99 table of 99 B Balance partitioning advanced MACH global optimization option 129 BFM packing advanced ispLSI compiler property 125 Boolean logic reduction MACH global optimization option 129 Boolean logic synthesis MACH global optimization option 129 Boundary Report 160 Calculate frequency in Timing Viewer 156 Carry pin direction ispLSI compiler property 123 Case sensitive ispLSI compiler property 123 Clock Frequency
96. essary to configure the Project Navigator for design entry timing simulation and fuse map creation for these devices The Project Navigator is the main interface for ispDesignExpert Using the Project Navigator you can create a project that represents your design run processes on the sources in your project compile your design simulate your design and create JEDEC files that can be used to physically implement your design into a target device Furthermore you can access other ispDesignExpert tools from the Project Navigator ispDesignExpert User Manual 13 Starting the ispDesignExpert Project Navigator Starting the ispDesignExpert Project Navigator To start the Project Navigator choose the Start menu In the Start menu select the menu item Programs gt Lattice Semiconductor gt ispDesignExpert System The Project Navigator window appears Figure 1 1 H ispDesignExpert Project Navigator D ISPTOOLS ISPSYS EXA OLX File View Source Process Options Window Tools Help Strategy 4 Sources in Project Processes for Current Source No Processes Available Selectthe New button to add source or No processes are available for the Import inthe Source menu to add from an projectnotebook Select another item in existing design the Source listto get processes New Open Eaa vier E mes Create open or save projects or quit the Project Navigator Figure 1 1 ispDesignExpert Proje
97. esses associated with it Use the Text Editor or just double click the ab1 icon from the Sources list to view the syntax of the ABEL HDL module Figure 3 3 The Text Editor is available from the Window Text Editor menu item in the Project Navigator w Mike Kove Laatti 5emiran iurtnr r ragi kis damiga 1s comprised ef 4 mein unctinns 12 hit BILE zynehreG nebB Pasa ter with decade ani t autput and gen Define ronstent EQERE R 22 4 R R FLSI PROPERLY Fec ot No Wrap DOS NE Figure 3 3 Text Editor with Sample ABEL HDL File 5 With the ABEL HDL file highlighted the Compile Logic item in the Process list should also be highlighted Click the Properties button The Properties dialog box Figure 3 4 appears ispDesignExpert User Manual 41 ABEL HDL Design Entry amp Properties Normal ABEL Properties Urda Compile Control Definitions perante Advanced Retain Redundant Logic T F False Help ABEL Compatibility List None Double click the selected item to cycle through possible choices or use the combo box in the edit region for a list of Figure 3 4 Properties Normal ABEL Dialog Box 6 The properties you see are the defaults for the ABEL HDL module When any of the properties are changed the Defaults button becomes active so you can revert to the default settings if you desire The Undo button allows you to undo the latest change you made To create a n
98. ew ABEL HDL module 1 Choose Source New from the menu bar The New Source dialog box appears Figure 3 5 New Source ABEL Test Vectors Schematic User Document Verilog Test Fixture VHDL Test Bench Waveform Stimulus Figure 3 5 New Source Dialog Box 2 In the New Source dialog box choose ABEL HDL Module and click OK The Text Editor window appears together with the New ABEL HDL Source dialog box Figure 3 6 ispDesignExpert User Manual 42 ABEL HDL Design Entry New ABEL HDL Source x Module Name top File Name Cancel fot Browse Figure 3 6 New ABEL HDL Source Dialog Box In the New ABEL HDL Source dialog box enter relevant contents into text fields Click OK or press Enter The new ABEL HDL file appears in the Text Editor window Use the items in the Edit menu to cut copy paste find or replace text You can also add design attributes to the ABEL HDL file Refer to ABEL HDL Reference Manual for more information The Language Editor The Language Editor the Text Editor can be used to create or modify HDL modules ABEL HDL test vectors VHDL test benches and Verilog HDL test fixture files You have several ways to open the Language Editor From the Project Navigator Sources window double click on an HDL file for example design abl Or select the HDL source from the Sources window of the Project Navigator click the Open button at the bottom or choose the Source gt
99. extensions for its own use You should avoid using the following extensions when naming your own files ln sc _SYy _wt asc asy bin ed Hierarchy Navigator log file Schematic Editor log file Symbol Editor log file Waveform Editing Viewer log file Waveform Viewer log file ASCII schematic file ASCII symbol file Binary waveform file EDIF netlist ispDesignExpert User Manual 37 err his nam pin sch sym tre vci vct VCO vtr Wav wdl wet Saving a Project Error OUTPUT file Waveform Viewer history file Binary waveform name file Netlist file for generic netlist by pin Schematic Editor files Symbol Editor file Hierarchy Navigator file Constraint file Temporary copy of the constraint file Constraint output from the Fitter Hierarchy Navigator temporary file Waveform Viewer waveforms and trigger information Waveform Editing Tool database Waveform Editing Tool database ispDesignExpert User Manual 38 Chapter3 Design Entry The chapter describes the supported design entry of the ispDesignExpert It contains information on ABEL HDL Design Schematic Design VHDL Design Verilog HDL Design EDIF Design Hierarchical Design Mixed Entry Design Design Attributes ispDesignExpert User Manual 39 ABEL HDL Design Entry ABEL HDL Design Entry This section describes using ABEL HDL as an entry for your design that supports the ispLSI GAL MACH and PAL devices Add an ABEL HDL M
100. file When you import create or save a design source abl sch vhd or v file in a project naf file s containing port information of module s in the design source will automatically be generated and saved under the current project directory n NOTE If you cannot find a desired nat file when creating a symbol open the corresponding source in the Text Editor if it is an HDL source or the Schematic Editor if it is a schematic source Make a modification to that source which will not change its original functionality for example add a space at the end of an HDL file or add a wire to a schematic file and then remove the wire Save the modified source file Then you will be able to find the relevant nat file NOTE The base name of a naf file is the same as its relevant module 3 Click Open A notice will appear telling you Symbol has been generated The symbol has been created and added to your symbol list It can be found in the Local symbol library Refer to page 87 for more details on the Local symbol library ispDesignExpert User Manual 50 Schematic Design Entry Add Design Control Properties ispLSI Designs Only A subset of Compilation Properties Device Control Options are device dependent and define the objective for the design implementation process To set the properties from a schematic design flow use the following procedures 1 In the Project Navigator
101. function in Simulator Control Panel 142 Optimization schematic attributes for 101 P Pack design MACH global optimization option 128 Parameter file ispLSI compiler property 123 Performance Analyst analysis types fMAX 161 tCO 164 tCOE 165 tOE 165 tPD 164 tSU 162 evaluate results 168 for MACH PAL 161 run 168 ispDesignExpert User Manual 173 start 166 Pin locking for GAL PAL 115 in Verilog HDL designs 116 example 116 117 syntax for LeonardoSpectrum 117 syntax for Synplify 116 in VHDL designs 115 example 115 syntax 115 Pop up menus Signal Navigator 156 Timing Tables 159 Probe in HDL 140 in schematic 140 Process flow 29 Process types output file 28 process 28 report 28 tools 28 Processes window Project Navigator 28 Product term collapsing MACH global optimization option 130 Product term equation splitting MACH global optimization option 130 Project clean up 36 create 15 describe 29 giving a title 16 icon 26 import sources 17 removing files 22 save 36 tips for defining 30 tips for naming 37 tips for saving 37 view path 21 Project Navigator features 24 menu bar 26 processes window 28 screen 25 sources window 26 title bar 26 toolbar 26 tools associated 24 Properties ispLSI compiler 118 Index BFM packing advanced 125 Carry pin direction 123 Case sensitive 123 Effort 120 Free all pin locks 122 Ignore reserved pins 122 invoke dialog box 118 Maximum GLB inputs 121 Maximum GLB outputs 121
102. g and Naming Projects cece sensa Rh ER mr RR ERE RR SE 37 Reserved File Names ccd berks oo ODER ORRIN ndate A i Rd ol ede OR os 37 Chapter 3 Design Entry aukescunuxsua d x yk Era RR FERAWESXRERMRRRAN TY REPRITE CE 39 ABEL HDL Design Entry 2 cee n 40 Add an ABEL HDL Module to Your Design 0 00020 e eee eee 40 Wie Language Ba cuicoaqaddpde i RIciqer rePRede4eRbeate edasiieirdduad ps 43 Schematic Design REC aec ar Ae eek dS de Se Oe o dpud op d OUR C EEA 44 Add a Schematic to Your Design iui odckockoro 4 dob eee Lhe dG ede o oo dra 44 Add Design FINIS acaba dejes deb dnbio Ve dee cl cr Sa voe erra ES 48 deli o 0 EMINET rcr ME 50 Add Design Control Properties ispLSI Designs Only 220005 51 Li RM PPM 53 Add a VHDL Module to Your Design uua dci FE dod Eo ORE REDDE e hod C 53 Create an EDIF File for BB e rie bd OO Op RC CARGO EROR CR o eC dea 56 Di DoR DOSI PrTrrrrrrrrem 57 Add a Verilog HDL Module to Your Design 2 224442 cocer essor RR 57 Gede aM EDIF FIE rt 59 EDIF DESIG i perai ma monau maaa a A E RA aa aat d de aE gae teed a EA E EB BSa aa dayat jan b aa a a a R E 61 MACH PAL Properties in the EDIF Fil coeno ehh rorm REED 64 POE LE EEEE edad d OR ENEE CRI P EE E re ee eer 64 Import Mechanism tor MACH PAL uia desc doe ea wie RR IR CR Rom RE eC C RC eae 66 alti iere HB PPP TTPTT 67 Overview of Hierarchical Design seucccuucleleaes4 RR RR ree ce ch 4d RR
103. gnExpert software as input The timing information for the device part in the sim file must exist to perform timing analysis Timing Explorer The Timing Explorer provides an interactive method for viewing and querying timing information for the design The Timing Explorer is accessed in the Processes window of the Project Navigator Information is calculated in response to your query and the turn around time is fast Only the data you requested displays This section describes methods to use to obtain the timing information you need ispDesignExpert User Manual 154 Timing Analyzer for ispLSl To start the Timing Explorer 1 With the device selected double click the Timing Explorer process from the Project Navigator 2 The Timing Explorer is invoked with the timing reports generated If you have not run the Compiler ispDesignExpert will automatically fit the device first The Timing Explorer consists of the Signal Navigator and several tables Refer to the remainder of this section for details on adding data to your Timing Explorer tables Signal Navigator The Signal Navigator Figure 6 1 lists design signals in a tree format and groups them into four categories Inputs Outputs Bidirectional and Registers You can traverse the design in fan in or fan out mode click the right mouse button to select the mode You can expand the signal tree until the selected signal is a boundary signal or starts a loop BEDESIGN LIST Fan in
104. h block should have about the same amount of resources used When this option is disabled the design is partitioned block by block filling up one block at a time Some blocks may be filled up completely while others may be unused m Spread Placement When this option is enabled the design signals are placed evenly or spread out among macrocells in the block Spreading out the placement allows the user to make minor changes to the existing output and node signals in the block When this option is disabled the design signals are assigned to the first available macrocell in the block This placement method will leave all unused macrocells at the end of the block making it easier to add new outputs or nodes to this block Logic Synthesis The Logic Synthesis tab Figure 4 17 lets you select the synthesis or optimization options Use the Defaults button to reset the selections to their default settings Use the Apply button to apply the options Clot Opi amp mizgtiun Cine Opwesirsun Logie Synthasis Listen Options F Boolean Log Aeducton E D T Synit tii Deas V EuiinratDipat Cera App E Ha colpe E Golas All Moder for speed 7 Colles Bakeca Modea fw awaj Fiadact Tem Gdapag Equation Spotting Figure 4 17 Global Optimization Dialog Box Logic Synthesis Boolean Logic Synthesis This option enables or disables boolean logic reduction Its default state is Enabled ispDesignExpert User Manual 129 MACH Global Optimizat
105. hat the actual outputs differ from the outputs you predicted in your test vectors or detailed information about the states of internal registers and product terms of a device during simulation If you simulate a design with Report Type set to None Figure 5 9 you can determine if any errors exist If there are errors you can use the more detailed Report and Trace types to increase the amount of information provided until you have enough information to solve the problem LM ping DE nib MELLE NE EL DE Vactor High meedance 2 Yaha Fisgrir Peering Vals Welch Sionsis Vedo Range in D Dicublg cick fig ssl pciad iam ko cycks through poss ke choices or use the combo bow in a edit region for s int ol Figure 5 9 Properties Dialog Box Report Type None NOTE In order to see the clock waveform in the Waveform Viewer you need to use Trace Type Detailed which is the default Otherwise you will not see the clock edges displayed For more details on controlling the simulation report refer to the Design Verification Tools User Manual ispDesignExpert User Manual 146 Equation Simulator for MACH PAL Displaying the Waveforms in the Waveform Viewer The Waveform Viewer displays the results of logic simulation The nets whose waveforms are to be displayed can be interactively chosen from the schematic Query functions can be used to trace signals to their source on the schematic Trigger functions
106. he following is the list of properties which are supported by the fitter EDIF property handling for CPLD 1 PIN LOCATION PROPERTY NAME LOC VALUE PIN Example LOC P20 SCOPE IO PORT net connect to the IO port 2 GROUPING NAME GROUPING VALUE GROUP NAME NAME LOC VALUE LOCATION NAME Example Use the following command to assign signal locations in your design In this case you have a list of internal node a b c d e f and g and you want to assign them into a group mg and the location of this group need to be assign to Block A Segment 2 ispDesignExpert User Manual 64 On net a grouping mg On net a loc A 2 On net b grouping mg On net b loc A 2 On net c grouping mg On net c loc A 2 On net d grouping mg On net d loc A 2 On net e grouping mg On net e loc A 2 On net f grouping mg On net f loc A 2 On net g grouping mg On net g loc A 2 OUTPUT SLEW PROPERT Y NAME SLEW VALUE Fast Slow EDIF Design Example To set port A to high slew put the following property on the net or on the Port SLEW Fast SCOPE OUTPUT PORT NET Signal Optimization PROPERTY NAME OPT VALUE KEEP COLLAPSE SCOPE On any net of the design isoDesignExpert User Manual 65 EDIF Design Import Mechanism for MACH PAL By default properties in EDIF files are ignor
107. he ispDesignExpert Compiler The synthesis of the VHDL file will be finalized in this process For an ispLSI design to create a edf file before fitting your design 1 In the Project Navigator select the target device icon to display the associated processes in the Processes window as shown in Figure 3 23 IB Prag 53 Money Mop Link D Dealgan Ej nked Equations prep 3 nin U Redece Logic ajpi isp ipS inp nbl ini Epreg prepa aen B Con eteniat kisanga FicCompile Design ig JEDEC Fila Compiler Anport Timang Annhysis Y Timengq Explorer phase Frequancy Rapor 2 Setup Holt Aluport T IDautie ckzk in chipre n deren chore Centres Ere tem mtha bai pr geed tha She Wio to eiertthe process Sete tha Bipa bua m sien proces and ipa he Piwa Cres Start ew ee Figure 3 23 VHDL Design Flow 2 Click the Start button or double click on the EDIF Netlist process to start creating the edf file for the ispDesignExpert Compiler The VHDL file will be synthesized in this process as well For a GAL MACH or PAL devices the EDIF netlists will be created when you run the Fit Design process For more information about ispLSI Design Attributes Device Control Options EDIF Property Files or Parameter Files see the isoEXPERT Compiler User Manual ispDesignExpert User Manual 56 Verilog HDL Design Verilog HDL Design This section describes using Verilog HDL as an entry for your design that supports the isoLSI GAL MA
108. hether reporting is enabled for paths traced through asynchronous register inputs ripple clocks or data input of transparent latch Default tCO Path Trace This path starts at an input pin and traces through any number of levels of combinatorial logic to the clock pin of a register Tracing continues through the clock to output path of the register and through any number of levels of combinatorial logic through the data path of the output buffer to the output pin Only a single register clock to output delay exists in this path When tracing input latch gate to output delays the path starts at the pin traces through the gate to output path of the latch and through any number of levels of combinatorial logic through the data path of the output buffer to the output pin Only a single latch gate to output delay exists in this path ispDesignExpert User Manual 164 Performance Analyst for MACH Designs Paths are not reported if they trace through asynchronous register set reset inputs ripple clocks output enable paths or transparent input latches Combinatorial Figure 6 12 Default tCO and tGO Path Tracing tOE Output Enable Path Delay The tOE path trace analysis reports the input pin to output enable path delay starting from the primary input through the Enable of output buffers ending at the primary output You can specify whether reporting is enabled for paths passing through the asynchronous
109. iate a lower level schematic block in a schematic 1 In the Project Navigator choose Window Schematic Editor to open the Schematic Editor The Schematic Editor opens with a new sheet This schematic is going to be the top level schematic Next you will place a Block symbol a functional block in the schematic that will represent a more detailed schematic or other source at the next lower level 2 To add a new Block symbol to the schematic choose Add New Block Symbol to open the New Block Symbol dialog box from the Schematic Editor 3 Type a Block name and input and output pin names in the relevant fields of the New Block Symbol dialog box The first character of each pin name must be alphabetic Separate pin names with a comma Figure 3 39 The symbol pins must have the same names as the corresponding lower level I O markers schematics or pin names ABEL HDL in the lower level module For example a wire connected to a pin named A on the symbol is also connected to the net named A in the lower level module The DRC Consistency Check command in the Schematic Editor and the DRC Check Circuit command in the Hierarchy Navigator flag an error if a Block symbol has a pin without a corresponding net in the related schematic ispDesignExpert User Manual 73 Hierarchical Design New Block Symbol Block Name Add Use Data From This Block Use Data From NAF File Input Pins JA B CI Output Pins co SUM Bidirection
110. ic Editor menu item in the Project Navigator ispDesignExpert User Manual 44 Schematic Design Entry i5 Schematic Editor X WS TEE ihient 1 Figure 3 8 Schematic Editor with Sample Schematic File To add a blank schematic sheet source to your project 1 Choose Source New from the menu bar of the ispDesignExpert Project Navigator window The New Source dialog box appears 2 In the New Source dialog box choose Schematic and click OK or press Enter 3 The New Schematic dialog box appears with a blank schematic asking you to enter the name for a new schematic Enter the file name in the Schematic File Name field The default file extension shown in Save as type field is sch Click OK or press Enter NOTE To avoid naming conflicts problems use different names for the source file and the project file ispDesignExpert User Manual 45 Schematic Design Entry To add symbols or macros to your schematic 1 Choose Add gt Symbol from the Schematic Editor The Symbol Libraries dialog box Figure 3 9 appears Symbol Libraries DA ASYMBOLSYVANFUNC LIB DA ISPSYS sym_libs title lib D i MIS ZUM za i ansia Mz LIB DA AGENERICAGENERICYOPADS LB wl Symbol Figure 3 9 Symbol Libraries Window TIP Use the Zoom features under the View pull down menu or on the Schematic Editor Toolbar for viewing the opened sch file 2 In the Symbol Libraries dialog box select lt driv
111. ice Creating Test Stimulus for Lattice Logic Simulator Before simulation you must create a stimulus file that specifies the input waveforms There are two ways to create a stimulus file m Create a graphic waveform file The Waveform Editing Tool WET lets you graphically create input stimulus waveforms for your design by drawing them directly on the screen The stimuli can be edited graphically or by modifying values in dialog boxes The WET then converts the waveforms into a stimulus file that the simulator recognizes Waveform files in Waveform Description Language format are also useful as input to automatic test equipment or as documentation of the circuit s expected behavior If you associate the waveform stimulus file wd1 with the selected device in your design both the functional and timing simulation processes are supported However if you associate the waveform stimulus file with a design module only functional simulation is available m Create a test vector file You can create a test vector file in a text editor using proper keywords Test vectors are sets of input stimulus values and corresponding expected outputs that can be used with both functional and timing simulators Test vectors can be specified either in a top level ABEL HDL source or in a separate ABEL HDL test vector format file called a abv file The abv file is considered a text document and is kept above the device level in the Sources window Whethe
112. igator If a relevant module of the selected instance is defined in an HDL source file it will be opened in the HDL Viewer Select View Push Pop from the Hierarchy Navigator The cursor becomes cross hairs Click on the desired symbol The Hierarchy Navigator will open the sheet for that symbol at the next level There will be no sheet for a primitive cell if you click on a symbol that is a primitive cell If the symbol you choose is generated from an HDL module the Text Editor will pop up for with that HDL file Select File Exit to close the Hierarchy Navigator window You will be asked to save changes you made if any Select File Exit to close the Hierarchy Browser window ispDesignExpert User Manual 89 Mixed Entry Design To add symbols or macros to your schematic 1 Choose Add Symbol from the Schematic Editor The Symbol Libraries dialog box Figure 3 57 appears Symbol Libraries Library Local C GENERIC GENERICAMISC C4 PLSISPLSISARITH LIB D APLSISPLSINCODER LIB Symbol Figure 3 57 Symbol Libraries Window with ispLSI Libraries lt TIP Use the Zoom features under the View pull down menu or on the Schematic Editor Toolbar for viewing the opened sch file 2 In the Symbol Libraries dialog box select lt drive gt 1ib from the library list then select the target symbol or macro 3 Move the pointer back over to the Schematic Editor notice that the symbol you
113. igator processes the design up to the specific step highlighted in the Processes window In this case it is Compile Design Figure 1 13 ispDesignExpert User Manual 20 Creating a New Project BispDesignExpert Project Navigator D 5ISPTOOLS ISPSYS EXAMP Mi Ea Eile View Source Process Options Window Tools Help Strategy Normal gt Sources in Project ispLSI1032E 100L J84 8 clocktop abv 2 clocktop clocktop sch control control sch S HOURS hours abl sseg sseg abl MINUTES minutes abl Asseg sseg abl PRESCLR presclr abl E seccentr seccntr abl Processes for Current Source Update All Schematic Files ef Link Design Linked Equations e O Reduce Logic e i EDIF Netlist X Constraint Manager e Cees e amp JEDEC File S Compiler Report G Timing Analysis X Timing Explorer S Maximum Frequency Report New Open Double click to choose a different device Double click the item in the list or select the Start button to start the process Selectthe Properties button to startthe property Start wi Properties Log Ready Figure 1 13 Project Navigator Complete the Compile Design Process NOTE View Project Path Yellow exclamation beside the process points indicate that warnings were generated Red Xs indicate that errors were encountered The warning or error is described in the auto make log file displayed in the Repor
114. igure 3 63 Sample Case ispDesignExpert User Manual 97 ispLSI Design Attributes The second schematic shows where the paths for no minimization are taken from Note that when the design is processed by the ispEXPERT Compiler the unused nets DUMMY1 and DUMMY will be removed since they do not reach output pins The properties remain attached and active for the intended nodes By attaching all necessary design control properties at the top level using this technique it is possible to call a subfunction or lower level module more than once while maintaining unique path names and attributes for each instance of the subfunction In ABEL HDL The same information holds true for ABEL HDL designs as well Properties may be assigned at any level of a hierarchical ABEL HDL design though properties requiring unique names should not be used in lower level modules that are instanced more than once If necessary lower level nodes may be brought up to the instancing module for property assignment Since the properties are used at the upper level each module would be assured of having properties containing truly unique names Syntax PLSI PROPERTY property name property values where property name the name of the property property values the numerals or strings assigned to the constraint Example Inputs IN1 IN2 IN3 IN4 pin 15 16 17 18 CLKA CLKB pin 35 33 Properties PLSI PROPE
115. ill see the ABEL HDL framework already started for you 8 Enter your design in the Text Editor window Make sure that you enter it between the TITLE statement and the END statement ispDesignExpert User Manual 91 Mixed Entry Design f Text Editor sseg abl Of x EJ File Edit View Templates Tools Options Window Help 8 x MODULE sseg TITLE seven segment decoder DO D1 D2 D3 pin B C D E F G pin istype com Figure 3 59 ispDesignExpert Text Editor with Code Entered 9 Select File Save then File Exit Notice in the Project Navigator that the icon next to the source has changed This means you have an ABEL HDL file associated with this source and it is linked correctly If you have chosen an ispLSI or GAL device to verify the correctness of your design or to check the hierarchical structure of the whole project you can use the Hierarchy Browser Choose the upper level source in Sources window of the Project Navigator In the Processes window double click the Hierarchy Browser The Hierarchy Browser will be opened together with the Hierarchy Navigator if the source you selected is a schematic or the HDL Viewer if the source you selected is an HDL file All the instances included in the top level design are listed in the Hierarchy Browser upon the hierarchical level To a MACH or PAL design if the source you selected is an HDL file double click the associated Hierarchy Browser process from the Proj
116. in Figure 3 42 must be named add sch The nets in the lower level schematic correspond to the pin names schematics or pin names ABEL HDL in the upper level module The symbol should be a Block symbol If the symbol used is in a module directory it can also be a Cell symbol Figure 3 43 presents the lower level ABEL HDL module for the Add block symbol it can also be instantiated by the top sch design ispDesignExpert User Manual 75 Hierarchical Design MODULE add inputs A B CI pin outputs CO SUM pin EQUATIONS SUM A amp B amp CI tlA amp B amp CI A amp BE amp CI A amp BE amp CI CO A amp B TA amp CI B amp CI END Figure 3 43 Lower level ABEL HDL Module for Add Block Symbol NOTE It is best to create the lowest level sources first and then import or create the higher level sources ispDesignExpert User Manual 76 Hierarchical Design Hierarchical VHDL Design The following steps outline how to specify a lower level VHDL module mux2x1vhd vhd and a lower level schematic mux2x1 sch in an upper level schematic mux4x1 sch Figure 3 44 shows a schematic block and a VHDL module instantiated in another schematic inpEbersgnE spent Project Navigator DAMSETODLSISPSYSUEXANMEPL BRESTIET Eie Yew Gorce Poocess p oes ihindow Took e Sichem n hdl AT ETITIDEFEIBETI igi eped EDIF Mailis Hime
117. in these ways m Highlight the device icon in the Sources window of the Project Navigator and select the Compile Design process in the Processes window Choose the Process Properties menu item or click the Properties button at the bottom of the Project Navigator m With an ispLSI project opened in the Project Navigator choose Tools Compiler Properties NOTE Invoke the ispEXPERT Compiler Graphic User Interface if you need to specify a post route pin file ppn See the ispEXPERT Compiler User Manual for more information There are three tabs in the Compiler Properties dialog box Settings The Settings tab Figure 4 9 Figure 4 10 and Figure 4 11 lets you set options that can control how the compiler processes your design Not all options are available for all devices In addition the values for some of options will vary upon the different device you choose Figure 4 9 Compiler Properties Dialog Box Settings for ispLSI1000 2000 and 3000 devices ispDesignExpert User Manual 118 ispLSI Compiler Properties Figure 4 10 Compiler Properties Dialog Box Settings for ispLSI 5000 and 8000 devices Figure 4 11 Compiler Properties Dialog Box Settings for ispLSI 6000 devices isoDesignExpert User Manual 119 isoLSI Compiler Properties Strategy Effort The options of the Strategy option are m Area Maximum resource utilization m Delay Maximum performance m No Logic Optim
118. ion Options D T Synthesis This option enables or disables D and T type synthesis When enabled the Venus optimizer synthesizes the registered signals to use the D or T type flip flop with the least number of product term implementation When disabled the register type specified is left untouched Its default state is Enabled Set Reset Don t Care This option allows the signals that have defined Set and Reset functions to fit into the same block as signals which don t If this option is disabled signals without set or reset function will not be partitioned into the same block as signals that contain set or reset functions and hence may inhibit design fitting Its default state is Enabled Node Collapsing This option enables or disables node collapsing If the user has specified specific nets or nodes to Keep these nets or nodes will not be collapsed regardless of whether Node Collapsing option is enabled Its default state is Enabled m Collapse All Nodes Collapses all nodes up to the set Product Term limit without regard for the logic m Collapse Selective Nodes Collapses all nodes up to the set Product Term limit but considers common product terms and groups them into nodes Product Term Collapsing This option sets the product term limit for the Node Collapsing algorithm Normally this value should equal the product term limit for Equation Splitting The default value is its Family default Product Term Equation Spl
119. ispDesignExpert User Manual 114 Pin Locking for GAL PAL Devices Pin Locking for GAL PAL Devices For GAL PAL devices if you have a VHDL or Verilog HDL module as the top level source in your project you can only specify pin locking information in the design sources vhd Or v VHDL Designs If you have a VHDL module as the top level source in your project modify the VHDL file adding pin locking information before fitting your design to the target device Syntax attribute loc string attribute loc of signal name signal is P lt pin_number gt Example The following example shows how to lock an input signal a to pin 5 library ieee use ieee std logic 1164 all entity mux2xlvhd is port z out std logic a b s in std logic attribute loc string attribute loc of a signal is P5 end architecture mux2x1 arch of mux2xlvhd is begin process s a b begin case s is when 0 gt Z lt a when 1 gt z lt b when others s gt z X end case end process end mux2xl1 arch ispDesignExpert User Manual 115 Pin Locking for GAL PAL Devices Verilog HDL Designs If you have a Verilog HDL module as the top level source in your project modify the Verilog HDL file adding pin locking information before fitting your design to the target device However there are two synthesis tools supported in the ispDesignExpert software Synplicity Synplif
120. itting This option sets the product term limit for the equation splitting algorithm Normally this value should equal the product term limit for Node Collapsing The default value is its Family default Utilization Options The Utilization Options tab Figure 4 18 lets you specify the utilization limits for macrocells block inputs segment inputs and inter segment lines These limits are Soft Constraint which means that the Fitter will ignore these constraints if they inhibit design fitting Warnings will be specified if the constraints are ignored Use the Default button to reset the selections to their default settings Use the Apply button to apply the options ispDesignExpert User Manual 130 MACH Global Optimization Options Cleat Opimixgtiun Gora Optiminwon Logie Syrian UWirabnn Doriens phon poem NT Apply pee Figure 4 18 Global Optimization Dialog Box Utilization Options Maximum 96 of Macrocells per Block Used This option sets the limit for the number macrocells to be used in a block Maximum 96 of Block Inputs Used This option sets the limit for the number of inputs to be used going into a block ispDesignExpert User Manual 131 Compiling Fitting the isoLSI GAL Design Compiling Fitting the ispLSI GAL Design Once you completed an ispLSI or GAL design you may want to fit the design into a target device Since you selected a device earlier in your design the remaining steps are straightforward
121. ization Minimal change to the design The following points are important to remember when you use the Strategy option m Forlogic level considerations DELAY offers the least number of logic levels default m AREA optimizes for device utilization and consequently may use more logic levels m NOLOGIC OPTIMIZATION bypasses the synthesis and optimization stage and maps your design directly into the isoLSI architecture The Effort option provides three different optimization levels m low m Medium m High The higher the effort the longer the runtime and the larger the memory requirement While a higher effort level usually leads to better results this is not guaranteed Try different effort levels to find the best result for a specific design The default value is Medium Use Global Reset XOR The User Global Reset option makes the global reset pin available for use by the compiler The default is ON For ispLSI 5000V and 8000 device families Use Global Reset is always ON If a registered preset or reset is not found in an ispLS 5000V or 8000 device design the fitter will automatically assign global reset The XOR option preserves user defined XOR gates on primary output nodes during the logic optimization process The XOR compiler option when applied globally preserves all user defined XOR gates on primary output nodes To preserve other user defined gates apply a local attribute When the global attribute is turned off
122. ject Navigator with Sources Imported Targeting the Design to a Device The target device is the device in which you intend to implement your design When you open a new project the default target device is ispLSI5384V 125LB388 If you do not want to use the default device you can target the design for a specific supported device To target a specific device 1 In the Sources window double click the default device icon to open the Device Selector dialog box Figure 1 8 The Device Selector contains all the supported devices and their options Figure 1 8 Device Selector Dialog Box 2 Under Select Device select the ispLSI 1K device family and ispLSI1032E 100LJ84 within that family Accept the default options isoDesignExpert User Manual 18 Creating a New Project Figure 1 9 Device Selector Dialog Box with Target Device Selected 3 When you are finished click OK The Confirm change dialog box appears Figure 1 10 Confirm Change Lx Y ou are aboutto change device kits This will result in changes in the Project Navigator design environment Do you wish to continue with this operation Figure 1 10 Confirm Change Dialog Box 4 Click Yes The specified target device appears in the Sources window Also all the processes for that device are shown in the Processes window Figure 1 11 FlispDesignExpert Project Navigator D ISPTOOLS ISPSYS EXAMP ET E3 File View Source Process Options Window Tools H
123. k wal CFA ue PED Took FF T PIH PIN PIH PIH E pin declaration PIH Tae ire Level Hi Figure 2 1 Project Navigator and Other Tools isoDesignExpert User Manual 24 About the Project Navigator Project Navigator Screen Once the ispDesignExpert software is invoked the Project Navigator is displayed on the screen as shown in Figure 2 2 Title Bar ispDesignExpert Project Navigator Menu Bar File Options Window Help Tool Bar Strategy o d Sources in Project Processes for Current Source No Project Open No Processes Available Sources Window Processes Window Select New Project or Open Project in the File menu to open a project Open a projectto make processes available Status Bar view Prapenies Close the current project Figure 2 2 Project Navigator Screen Your files are listed in the Sources Window while the Processes connected to your files are shown in the Processes Window If no project is open the Sources and Processes windows would be empty as shown in Figure 2 2 isoDesignExpert User Manual 25 About the Project Navigator Title Bar The Title Bar displays the ispDesignExpert Project Navigator name and the current project name if any Menu Bar The Menu Bar contains menu topics related to the functions used to create the design Each menu item has one character underlined This character is used to execute the command from the keyboard
124. l reset ispLSI compiler property 120 Use internal tristate IO driver advanced ispLSI compiler property 124 V Verilog HDL modules add to a design 57 create 58 import 57 VHDL modules add to a design 53 94 create 55 94 import 53 W Waveform Viewer Edit menu function Show 139 Waveforms show 139 147 14 X XOR ispLSI compiler property 120 Y Y1 as reset ispLSI device option 126 ispDesignExpert User Manual Index 176
125. lculated when the source and destination registers are clocked by two clock signals or by different edge of the same clock signal In the first case the delay obtained is actually the setup time of the destination register through the clock to output path of the source register In the second case the actually fMAX will be half of what is calculated by the tool Setup Time The tSU path trace analysis reports setup and hold time for data and clock enable signals with respect to a clock edge or the register recovery time from asynchronous S R inputs You can specify whether tracing is checked at the registers D T CE or S R inputs Default tSU Path Trace This data path starts at an input pin and then traces through any number of levels of combinatorial logic to the D T or CE inputs of a register The internal tSU of the register is added to the delay path The value of the internal tSU is dependent on the register being clocked by a global clock or product term clock The global clock net clock delay is modeled as Ons for MACH CPLDs so it is not used in the tSU calculation The tSU of the register is adjusted for the skew between the global clock and data path ispDesignExpert User Manual 162 Performance Analyst for MACH Designs Combinatorial Figure 6 9 Default tSU Path Tracing Path Endpoints for tSU tSU longest data path delay shortest clock path delay internal setup time tHD longest
126. lowed for the ispLSI devices are shown If you choose a MACH PAL or GAL device family the processes change to reflect your selection To target a specific device or device family 1 In the Sources window double click the Target Device icon to open the Device Selector dialog box Figure 2 3 The Device Selector dialog box contains all available devices and their options Sale Dee Device nimaki Fir Damad girdi frij Pa Ti Dena gems E gt Lampe ceh KI cmi 1 Irc parsAsgccrdmgss HO pen foeni widrmminpzi t Fren Uwi ae fee 85 m Figure 2 3 Device Selector Dialog Box ispDesignExpert User Manual 29 3 4 Describing a Project Under Select Device select a device family and a specific device within that family Then choose the options you want for that device When you are finished click OK The Confirm Change dialog box appears Click Yes The specified target device appears in the Sources window Specifying Project Files You define a project by importing existing sources into the project You can also create new sources or modify existing sources using an editor Design Hierarchy A single module design is a flat design in which there is only one source describing the entire design such as a single schematic You can also have a test file such as ABEL HDL test vectors in a flat design because all processes such as functional simulation in the flat design involve the entire design
127. lysis process in the Processes window The ispDesignExpert Process dialog box appears momentarily indicating the progress Then the Performance Analyst window is displayed as shown in Figure 6 15 Preferences Yid Help BHIN 12 74 Operekng cond tree Figure 6 15 Performance Analyst Window isoDesignExpert User Manual 166 Performance Analyst for MACH Designs To set options and filters 1 In the Analysis filed select the path analysis report that you want to run These choices determine the path tracing rules that the Performance Analyst will follow during timing analysis 2 Click Options to open the Options dialog box Figure 6 16 Pah Tracy shane Tren wrniiari raraq Dreiser pat 7 Degre arh EV pu D Darpara Diag arte T Pile ripcks EN Fox E s ou Pai mopon irie Driest Pp iri T Figure 6 16 Options Dialog Box NOTE The Options dialog box will vary slightly depending on the analysis type you have chosen 3 In the Source Registers and Destination Registers fields exclude the items from the list that you do not want to include in the timing analysis 4 In the Path Tracing Options field select the tracing path and endpoint options you want to use f NOTE Endpoint options are only enabled for tSU 5 Click OK to close the Options dialog box isoDesignExpert User Manual 167 Performance Analyst for MACH Designs To run timing analysis
128. mbol Block Name Use Data From This Block Input Pins Output Pins Bidirectional Pins Bun Cancel Edit Figure 3 61 New Block Symbol Dialog Box ispDesignExpert User Manual 94 Mixed Entry Design 7 In the New Block Symbol dialog box type a name for the top level symbol in the Block Name text field relevant input pins in the Input Pins text field relevant output pins in the Output Pins text field and relevant bidirectional pins in the Bidirectional Pins text field If you want to create a symbol that represents the current schematic click on the Use Data From This Block button The edit fields are automatically filled with the names of those nets that are labeled with I O markers If you have already labeled all nets with I O markers you won t have to enter anything manually If you want to create a symbol from an existing design source including ABEL HDL VHDL Verilog HDL or schematic click on the Use Data From NAF File button The Select File dialog box opens Select the naf file whose base name is the same as that of the symbol you want to create the edit fields are automatically filled with the names of those nets defined in the naf file When you import create or save a design source abl sch vhd or v file in a project naf file s containing all the information of module ports in the design source with the same name as modules in the abl sch vhd Or v file will automatic
129. mend Type r emit Pas tci En Fer CU ier P F Dega C om aid e Carre tem Figure 4 5 Pin Reservation Dialog Box JEDEC File Options Depending on the device selected you can select these special features Zero Hold Time This is a MACH 4 feature that sets the Zero Hold Time ZHT fuse This fuse controls the time delay associated with loading into all I O cell registers or latches When turned ON ZHT increases the data path setup delays to input storage elements matching equivalent delays in the clock path When turned OFF setup time to the input storage element is minimized User Signature This feature allows you to enter a design identifier such as revision number design codes etc The design identifier is programmed into the device and can be read from the device regardless of the state of the device s security bit Pull up All MACH 4 and MACH 5 devices have a Bus Friendly input structure that weakly holds an input at its last driven state When you select this option ispDesignExpert disables the Bus Friendly structure on all I O pins and enables the pull up resistor structure ispDesignExpert User Manual 112 Constraint Editor for MACH Designs JEDEC File Options Zero Hold Time Cancel User Signature 3 Help izle Figure 4 6 JEDEC File Options Dialog Box Assigning Power Level This dialog box lets you set the power level for the macrocell
130. mulator 40 NOTE If the test stimulus file is associated with the selected device both Functional and Timing Simulation processes are supported However if you associate the test stimulus file with a design module schematic only Functional Simulation is available 3 The Simulator Control Panel window appears Figure 5 2 ispDesignExpert User Manual 138 Lattice Logic Simulator for ispLSI GAL P Ximulninr Costrol Pomel CL OCKTUOP fie gree Simuh Aem Jous Helo i Sar Step intervatliog ong RuninTimeb53400ns ciBulstor Version 1 1 Ceserighr ie 1998 1999 by Darrisa Eugicandu eter Carperatian In timlizing mapping data aitis ag mapping data successfully tleksize 100 pa etepeize OD pm eee unit osding netlist Siding nwtligt succwaaEully Figure 5 2 Simulator Control Panel 4 Click the Run icon from the toolbar or select the Simulate Run menu item to start the simulation Z NOTE If you keep the View gt Show Waveforms menu item checked in the Simulator Control Panel the Waveform Viewer is invoked in the course of simulation to show the simulation results in waveforms Showing the Waveforms in the Waveform Viewer 5 When the simulation ends the waveforms of the signals display in the Waveform Viewer You can click the Waveform Viewer icon from the toolbar or select Tools Waveform Viewer from the Simulator Control Panel window to open the Waveform View
131. n Specify the type of the new project by choosing Schematic ABEL Schematic VHDL Schematic Verilog HDL or EDIF from the Project Type list Figure 1 2 Figure 1 2 Create New Project Dialog Box 4 Click Save The untitled project appears in the Sources window of the Project Navigator ispDesignExpert User Manual 15 Creating a New Project Giving Your Project a Title The default title for a new project is Untitled You can create a title for the project with many characters The title can contain spaces and any other keyboard character except tabs and returns To give your project a title 1 In the Sources window double click the title of the project Unt it led to open the Project Properties dialog box amp Project Properties Eg Figure 1 3 Project Properties Dialog Box 2 Type the name Clock for the title of your project and then click OK The new project title appears in the Sources window See Procereng for Curent Seu Ha Foecu ooa syverkabia Exlpchha New baRoninaddzcuce dr Mn pibcasses eng salahke Tor tha project import inthe Saurce menu im add inom mn nateboak Selectenotheriiem n Bie ening rmi ga Source leis ge preces New opem ge vied exse zer Handy Figure 1 4 Project Navigator Window with Project Title Entered ispDesignExpert User Manual 16 Creating a New Project Importing Project Sources You define the logic in a design by importing sources into the project These
132. ns for the Lattice Logic Simulator Equation Simulator and ModelSim Simulator Chapter 6 Timing Analysis lllustrates how to use the Timing Analyzer and the Performance Analyst ispDesignExpert User Manual 10 Documentation Conventions Documentation Conventions This user manual follows the typographic conventions listed here Convention Definition and Usage Italics Italicized text represents variable input For example design syn This means you must replace project with the file name you used for all the files relevant to your design Valuable information may be italicized for emphasis Book titles also appear in italics The beginning of a procedure appears in italics For example To import an ABEL HDL module to your design Bold Valuable information may be boldfaced for emphasis Commands are shown in boldface For example 1 In the Schematic Editor select File Generate Symbol Courier Monospaced Courier font indicates file and directory names and text that the Font system displays For example In the examples ispLSI_GAL clock directory select Bold Bold Courier font indicates text you type in response to system prompts For Courier example SET YBUS Y0 Y6 BA Vertical bars indicate options that are mutually exclusive you can select only one For example INPUTJOUTPUT BIDI Quotes Titles of chapters or sections in chapters in this manual are shown in quotation marks For example See
133. ntrols whether a lower power mode ON or a faster speed mode OFF is used for the ispLSI 5000V and 8000 devices The LowPower Device Options allow you to globally select a lower power mode or a faster higher power speed mode Default for the ispL SI 8000 device family is ON Default for the ispLSI 5000V device family is OFF The UES tab Figure 4 15 lets you choose the data type and specify the User Electronic Signature ispDesignExpert User Manual 126 ispLSI Compiler Properties pin m TERI Ioan Dacia Dues UE EmTe F bed fers F ramen Figure 4 15 Compiler Properties Dialog Box UES Data Type Check one of the radio buttons to indicate that your UES should be binary hexadecimal or ASCII format Signature Size The Maximum Signature Size field tells how many characters can be used for signature this varies depending on the format of signature and the device type Once you enter the maximum number of characters no additional characters are accepted in this field ispDesignExpert User Manual 127 MACH Global Optimization Options MACH Global Optimization Options If you have a MACH design you can set the optimization options for the Fitter in the Global Optimization Options dialog box With a MACH project opened in the Project Navigator choose Tools Global Project Optimization to invoke the Global Optimization dialog box There are three tabs in this dialog box Global Optimization
134. o SegmentNo NoOfSignals Signal list PinNo BlockNo SegmentNo Any block or segment Not applicable for BlockNo or SegmentNo MACH GROUP GroupA 4 Q0 01 02 03 MACH GROUP GrpA B 2 A0 A1 MACH GROUP GrpB 2 B0 B1 MACH SLEW SLOW NoOfSignals Signal list Default unlisted signals to FAST Slew rate MACH SLEW FAST NoOfSignals Signal list Default unlisted signals to SLOW Slew rate MACH SLEW SLOW 2 00 01 MACH RESERVE PinType PinNo Output state PinType Input Output Bidir Output state Not applicable Output state MACH RESERVE Output 8 out_high MACH RESERVE input 13 ispDesignExpert User Manual 103 MACH Design Attributes Inputs Clk Clr pin Dir OE pin 5 4 Outputs 03 02 01 Q0 pin 03 02 1200 ISTYPE req buffer A1 A0 B1 B0 pin A1 A0 B1 B0 ISTYPE com Special Constants Cy Xpo AL GZ Cee cy Xe WW v Set assignments A A1 A0 B B1 B0 Count Q3 00 equations Count OE OE Count Clk Clk Count Count fb 1 amp Clr include counter inc equations A OE Dir B OE Dir A B pin Combinatorial signal can only have pin feedback B A pin for this device include buffe
135. o path E identifier Tags this gate to be Y or N G XOR or All hard XOR in GLB XOR2 symbol Changes hard macros ON or OFF ispLSI hard 1000 2000 to soft macros macros 3000 6000 Marks primitive Y or N Any symbol All symbol to be preserved ispDesignExpert User Manual 99 Attribute Register Type Reserve Pin Critical LOCK LOCK BFM LOCK GRP OpenDrain Outdelay Pull PullUp SlowSlew Purpose Assigns register type Prevents package pins from being assigned during the Compiler s pin locking process Marks output as critical Assigns design signals to specific package pins Places I O pin s into a particular BFM with BFM index or any BFM without BFM index place I O pin s into a particular GRP with GRP index or any GRP without GHRP index Marks output to use open drain feature Makes the output buffer slower by 0 5 ns for output or bidirectional pins Marks I O symbols to have a pullup or datahold attached Marks output to have a pullup attached Marks output to use a slow slew rate Syntax GLB or IOC pin_number YorN pin_number Y or 0 to lt maxBigFastMegaBl ock 1 gt Y or Oto lt maxNumGFP 1 gt YorN YorN UP or OFF or HOLD YorN YorN ispDesignExpert User Manual ispLSI Design Attributes Applies To Any Register I O symbols Any output symbol I O symbols I O symbols I O symbols Any output symbol Any output symbol I
136. o place I Os anywhere on the device without restriction m Turn off Free All Pin Locks so the compiler will honor any pin locking attributes on your design The default is Off The pin assignments from the source design are read into the project when it is created they are not read again at any other time unless you specifically update the project These assignments may be edited in the Assign Pin Locations window of the ispEXPERT Compiler These assignments shown in the Assign Pin Locations window are the ones used when you compile If you want to compile with all pins free set this option to On Ignore Reserved Pins The Ignore Reserved Pins option instructs the ispDesignExpert to either ignore or honor the reserved pin assignments in your design m Turn on Ignore Reserved Pins so the compiler will ignore the reserved pin assignments in your design This allows the compiler to place I Os anywhere on the device without restriction m Turn off Ignored Reserved Pins so the compiler will honor any pin assignments in your design The default is Off Use Extended Routing The Use Extended Routing option instructs the ispDesignExpert to use a complete routing cycle in an attempt to route a design or question the user if routing time is very long The default is On m Turn on Use Extended Routing to instruct the ispDesignExpert to continue until the design is fully routed or until routing fails m Turn off Use Extended Routing to instr
137. o the constraint file are made via the function dialogs such as Location Assignment Group Assignment Pin Reservation JEDEC File Options Assign Power Level and Output slew rate Control Note that the Constraint Editor implements a simple error checking to ensure that the user assignments or constraints are applicable to the selected device and that there are no conflicting assignments If the user constraints do not apply to the selected device or are conflicting with the selected device Constraint Editor will display these constraints in red user can choose the color via the Option Color command For instance if you change the device type after specifying some pin assignments the Constraint Editor will display the non applicable pin assignments in red You can delete these constraints in the Loc function dialog boxes or via the Clear Project Assignments dialog box The features of the Constraint Editor and all its function dialog boxes are available only if they are applicable to the selected device Main Window Use the main window to set attribute values for signals and pins To invoke the Constraint Editor 1 Select the target MACH device from the Sources window of the Project Navigator 2 In the Processes window double click Constraint Editor The main window of the Constraint Editor appears Figure 4 2 Eg I IL sni j Ein Edt eate ee Opiore Help Tyee EigesiHsme Group Meme Eegm Block Macro
138. odule to Your Design To add an ABEL HDL module to a design you can either import a ab1 file or create a new ABEL HDL module file in the ispDesignExpert Text Editor using ABEL HDL syntax To import an ABEL HDL module to your design 1 Choose Source gt Import from the menu bar The Import File dialog box appears Figure 3 1 The project type Schematic ABEL is shown in the title bar of the dialog box letting you double check your project type before importing the source files LI n Hio cti Jb ud J oo aE mi Figure 3 1 Import File Dialog Box 2 In the Import File dialog box select the desired drive and path 3 Choose ABEL HDL Module a1 from the Files of type field and highlight the abl file you want to import from the File name field 4 Click OK The selected ABEL HDL file appears in the Sources in Project list of the Project Navigator as shown in Figure 3 2 ispDesignExpert User Manual 40 ABEL HDL Design Entry vigai O ISPPOOLS ISPt XAMPLES MEE ipi SIb38EZV 125L H3ER UC Dos Login abel ox yuctors Ci Check Syninx Compiled Equntons igi Vorheg Tost Fixture Daclesaiions DVHDL Test Bench Templnin D Ande Logit Tj Ardicod Equations lgl EDF Heii Cob bsscticic in opens geleced nume Coubte cick tm tam n he batarsa in are Viae thie ra pce Sis sew 5 p top SS a ae ee Figure 3 2 Project Navigator Window with ab1 File Imported Highlight the ABEL HDL icon and note the proc
139. og Box 2 Find the source file you want to import You can change the type of file that is displayed in the Files of type field 3 When you are finished selecting the source click Open ispDesignExpert imports the selected sources into the project and displays them in the Sources window Depending on the source type you are importing you may be prompted to provide additional information in the Import Source Type dialog box For example if you choose a vhd file you are prompted to choose to import it as a VHDL Module or a VHDL Test Bench in the Import Source Type dialog box TIP You can import the lower level sources before or after importing upper level sources However if you import a source that has links to lower level sources and the lower level sources are not already part of your project you will get undefined sources in your project until you import the missing lower level sources Also import test files that are to be associated with other sources after importing or creating the other source ispDesignExpert User Manual 31 Describing a Project Where the Source File is Placed in the Project Navigator After you import a source into the Project Navigator it appears in the Sources window However where the source appears in the window depends on the following If the imported source is a documentation file or a file type not recognized as a logic description or test file the source appears between th
140. on X Timing Simulation Double click to open the selected test Double click the item in the list or selectthe vectors Start button to start the process Select he Properties button to start the New Open Start View Properties Log Ready Figure 5 11 Running JEDEC Simulation Viewing the Simulation Waveform Like all the other simulation you can also view the simulation result via the Waveform Viewer 40 NOTE Refer to the Design Verification Tools User Manual for detailed information on other Waveform Viewer commands and functions ispDesignExpert User Manual 148 ModelSim Simulator ModelSim Simulator The ispDesignExpert software has an interface integration with ModelTech ModelSim Simulation Tool providing you a VHDL and Verilog Simulator Figure 5 12 Modelim varia pi ee bey Raed Ben giae Denon Wind eb e ee SR EEN pau pp pega pen Model Sim gt Figure 5 12 ModelSim Simulator Generating Test Stimulus You can specify the test stimulus before performing the VHDL Verilog simulation in these ways m manually create VHDL test bench or Verilog test fixture m create VHDL test bench or Verilog test fixture using the template m export a VHDL test bench or Verilog test fixture from the Waveform Editor if you have a source wdl Following are the rules you need to comply with when creating a VHDL test bench file m the entity name of the test bench is
141. on influences the device security cell programming However this option does not guarantee that the security cell is set or cleared because device programmer options also affect the security cell The default is Off ISP The In System Programming ISP option informs the software that you want to use the ISP pins on an ispLSI device Default is On ISP Except Y2 The ISP Except Y2 option allows the software to use the Y2 clock input for routing which increases resource utilization This option is device dependent Default is Off ispDesignExpert User Manual 125 isoLSI Compiler Properties Y1 as RESET The Y1 AS RESET option determines how the Y1 RESET pin is used Default is On The Y1 RESET pin is a global reset input if Y1 AS RESET is turned on The Y1 RESET pin is the Y1 clock input if Y1 AS RESET is turned off This option is device dependent You cannot lock a signal to the Y1 RESET input pin If Y1 AS RESET is turned on the Global Reset signal is automatically connected to the Y1 RESET pin and you will get an error if you try to lock a signal to this pin TOE AS IO The TOE AS O option determines the use of the TOE IO shared pin The TOE IO shared pin in the ispLSI 5000V device can be defined either as a TOE Test Output Enable or a regular IO pin The default setting of Off indicates the pin will be a TEST OE pin You cannot lock to pin IOO unless you set TOE AS IO to On LowPower UES The LowPower option co
142. owing net and path attributes CLK GROUP PRESERVE EAP ECP ELP ENP ETP XOR Symbol Attributes Table The Symbol Attributes Table lets you set attributes for the symbols in your ispLSl design The Symbol Attributes Table displays when you click on a symbol or cells category in the Design Browser Depending on the device used in the design you can set the following symbol attributes m OPTIMIZE m PROTECT m REGTYPE Assign Attribute Values The table cells are used to assign the attribute values Click the right mouse button on a cell to display a list of the attribute values that can be used for that attribute You can set multiple cells by holding the Control key down when you select them You can select all cells in a column by clicking on the attribute name in the column heading If no values are listed selected Edit from the right button menu to enter a value Then type in the values If an attribute is not supported for a particular pin or signal or symbol type such as input pins N A displays in the cell ispDesignExpert User Manual 108 Constraint Editor for MACH Designs Constraint Editor for MACH Designs The MACH Constraint Editor lets you select pin and node assignments group assignments pin reservation power level settings output slew rate and JEDEC file options such as User Signature and Zero Hold Time bits This window reads the constraint file and displays the constraint settings Modifications t
143. puso ed ed oed Red ence d ees 108 Constraint Editor for MACH Designs 00 0c eee ens 109 PO le Cabo Sod debui d Rd Ew Ub doge abe ER e e n REESE a ed 109 Location Hae uo ops da CR earn ea kis E RIO EO er ee 110 Group ASSIgNMENT aida Baw eR o PA ae ear ca E C dele ee o olea deca ce oe 111 w k p0 0 RESET TITIO T To 10 000 TIT 112 JEDEU PES CIN coudsd debes d Exe qRh PA dod bPPIZqCQe vA pn edd dp bt 112 Assigning Power LEE PCM TROPPO 113 Output Slew Rate SI s he Gh ON EREI ER EOS DLE ERA ob C 114 Pin Locking for GAL PAL DIOE de ek seeks oie Je e diea Eo ddp uen e 115 VER DISSE duoi aede ede RE EUR UR OY EA Re d ale CC Kee al oa 115 cc m errore 115 Verilog HDL Design mTMPCP rrrPT 116 Oynar IO DUO ccd aes dt Deib dirii eo E e e a ea aii E 116 Syntax for LeonardoSpectrum ssns eessen earan 117 spLSilCompiler PIOBEIUSE eses dodo deo ein da odor Ce EL Rd ee eae 118 DENN oo bad n PEE Rem Eschubu da Kx de abor a deb anoo ka dC ee d ACIE REOR 118 CA e a ee eae a adde EOUA Nds ue da iens dicum UE d RE Rari aq ed eai uri wu M 120 EIU Leon sies Amira ed entes q pda are ar Ec aae d ahi dle quad nox a anos acd ioa drababab E 120 A Jic doncc PEPERIT IIT T TIL 120 TOR ee sd eee ee dpa qe ere XR id Gc UR ICE EY ebd ooa 120 Maximum EESTI aac doe elo ee die de e To QR SC EUR di ew dO or ee d 121 Maximum GLE OUPS X em 121 Fees Pin LOGS ci deren ce hettee csi tinia ead shee hese
144. quirements Timing Analyzer for ispLSI The Timing Analyzer enables you to evaluate the performance of the ispLSI or GAL designs after successful compilation The Timing Analyzer performs the following functions m Determines maximum frequency for clocking a design containing two or more flip flops and or latches It also lists the clock periods between all the internal register pairs and the frequencies along with the names of the signals that drive the clock inputs of those registers The frequency is provided only for those sets of registers that are driven by the same reference clock otherwise the field is left blank The clock signal could be a primary input register Q output or a module I O It also lists the number of GLB levels for each path Calculates setup and hold time for boundary registers Calculates Tpd and Tco path delays Calculates GLB boundary delays Performs path enumeration by calculating path delays from all the source nodes to all the primary output nodes The delays listed are in descending order and the source nodes are primary inputs register Q outputs or module l Os To obtain path delays for the remaining destination nodes that include register inputs and module I Os use the ispEXPERT Compiler Design Manager menus Once you compile the ispLSI or GAL design and run Timing Analysis either automatically or manually the Timing Analyzer can be run The Timing Analyzer uses the sim file generated by the ispDesi
145. r inc end isoDesignExpert User Manual 104 Chapter4 Design Implementation After you create a design you can use compiler options and device options to control how the compiler analyzes synthesizes partitions places and routes your design using the physical resources of a selected target device These options represent design goals and restrictions that you want but that may not be critical to the successful operation of a design For an ispLSl design you can use the Constraint Manger to set or edit the constraints If it is a MACH design you can use the Constraint Editor to finish the assignment and modification of the constraints Once you finish setting the design the ispDesignExpert software uses the compiler control options the design attributes and pin assignments to fit your design into the device according to your design constraints and the device architecture This chapter covers the following information m Constraint Manager for ispLSl Constraint Editor for MACH Pin Locking for GAL PAL Devices Compiler Properties Compiling Fitting the Design ispDesignExpert User Manual 105 Constraint Manager for ispLSI Designs Constraint Manager for ispLSI Designs The ispLSI Constraint Manager lets you set pin symbol and net attributes for the signals the pins and the symbols in your ispLSI designs You can also read in an existing Property File or save the attributes as a Property File Besides the Constraint Manager
146. r level source is an ABEL HDL file the lower level source can be either a schematic or an ABEL HDL file For hierarchical Schematic VHDL designs If the upper level source is a schematic file the lower level source can be either a VHDL file or a schematic file If the upper level source is a VHDL file the lower level source can only be a VHDL file For hierarchical Schematic Verilog HDL designs If the upper level source is a schematic file the lower level source can be either a Verilog HDL file or a schematic file If the upper level source is a Verilog HDL file the lower level source can only be a Verilog HDL file For EDIF designs Hierarchical EDIF design is not allowed ispDesignExpert User Manual 68 Hierarchical Design You can create the top level module first or create it after creating the lower level modules For example in the Schematic Editor you can create schematic project components in any order and then combine them into a complete design You can draw a schematic first and then create a Block symbol for it or specify the Block first and then create the schematic for it later Hierarchical ABEL HDL Design The following steps outline how to specify a lower level block symbol in an ABEL HDL design Figure 3 34 shows an ABEL module Add instantiated in another ABEL HDL module Top However you can follow the same procedures to instantiate a lower level schematic Block symbol in an ABEL module as well
147. r the test vectors are part of a top level ABEL HDL source or are in a separate file they will be compiled and passed to the simulator For more details refer to the Design Verification Tools User Manual Running Functional Timing Simulation You can simulate an ispLSI or a GAL design using the Functional Timing Simulation process in the Project Navigator This process launches the Lattice Logic Simulator to verify your design operation ispDesignExpert User Manual 137 Lattice Logic Simulator for ispLSI GAL To run Functional Timing Simulation 1 Select the ABEL HDL test vector file abv or the waveform stimulus file wd1 of an ispLSI or a GAL design from the Sources window of the ispDesignExpert Project Navigator Figure 5 1 E ic pL hessgnExpest Frnpect PResigator DESETOOLSVISESS Y 1 3 iAP IE x Eie Mere Garsse Process pine jWiedow Took Help Seay fore s Sa EN Sources m Project Prrerser far Curen Somra Check mrsgn Compile Test erciors P y wl Compilar Lritin ispLsmuxze 180L 104 i clock dl V Timing Simuintinn licinckinp clockiop sch Bjennirai fennall ach EJHOURS hoses abl Tjersg 1xeg nbij TES minutes oblh jjeng Haeg abel EjPRESCLE pres cir a l Eyaucen asicntr abl Dorbeck n open the misiad best Deoubie rick the fem n he lator geld the hiiri Piia le iia Bie ripas peur Figure 5 1 Running the Lattice Logic Simulator 2 Select the Functional Timing Simulation process to launch the Si
148. rating frequency for each clock in the design fMAX is equal to reciprocal of the worst case register to register delay Figure 6 8 Figure 6 8 Default Register to Register Delay Path Tracing ispDesignExpert User Manual 161 Performance Analyst for MACH Designs The Performance Analyst reports all register to register delays in a spreadsheet format with clock sources displayed You can specify which clocks the Performance Analyst reports in the spreadsheet and whether tracing is enabled through all tracing paths When there are no register paths in the design the Start button is disabled and the spreadsheet is empty The Performance Analyst does not attempt to report external fMAX because it cannot make assumptions about the arrival time of signals driving MACH device inputs and the tSU of devices driven by MACH device outputs Therefore it is up to you to determine the external MAX based on the operating requirements of the system Default fMAX Path Trace tSU The default fMAX path starts at the source register clock input and traces through the clock to output path of the register through any number of levels of combinatorial logic through internal feedback only to the D T or CE inputs of the destination register including destination register setup time tSU The Performance Analyst assumes that the same clock signal and the same edge of the clock signal clock the source and destination registers However delays are ca
149. rocess m Choose Process Force One Level to start the highlighted process Changing the Environment and Configuration You can set many environment variables and change settings for the Project Navigator and programs started from within the Project Navigator You can even add menus to access other Windows programs Changes to the environment can be made by m Editing ini files used by the Project Navigator and other programs m Choosing Options Environment from the Project Navigator menus The Environment Options dialog box appears ispDesignExpert User Manual 34 Changing the Environment and Configuration amp Environment Options Window Settings p Process Force I Open Previous Project Auto make Iv Use File Associations C One Level Cancel Source Window Width je C Full OK Help m System Settings DOS Processes Fast Redraw Iconic iv Update On Editor Save C Observe C Observe and Pause p Auto Make Log M Verbose M Showlf Warnings Occur Show Always a Figure 2 6 Environment Options Dialog Box There are three options in the Window Settings area e lf the Open Previous Project option is checked the project that was opened when the Project Navigator was last running is opened when you start the ispDesignExpert If the project no longer exists or cannot be found this option is ignored and the Project Navigator opens without loading a project e Ifthe Use
150. rt are the VCC and GND symbols Check the Custom radio button if you know that the EDIF generated by other tools use different conventions After you check the Custom radio button the whole Custom field becomes active Select either Symbol or Net representation Then type the new names for VCC and GND If you generate the EDIF file from the supported third party design kit you can then select CAE Vendors and then choose from the list the vendor that generated the EDIF file 4 Click OK The software adds the selected EDIF file ed to the project sources Figure 3 32 ispDesignExpert User Manual 63 EDIF Design BE irpLhessgnE xpert Project Nenesgnine DOLESETCROLSYISESS TIS EXAM ME EI Eie ewm Source Grocers Otome window Toole Hep CUSTER Seeman finest AA Soumat m Proja Processes or Correal Source Lini pd GODGDICI M CF Dasign teeddl nb Ej Pre Fit Equations y TAD indi mij Ej Esgnnl Gnas Findemacs 2 Fitter Rapar Fs PosHit Pinauts igi JEDE Fis E Timing Analysis OGenerste Timang Simulation Files Bapor Fila D chk chck t cnni amp laser heana Deutia clck hg far inre kal ni eal aci ia awe To agua th port Ready Figure 3 32 Project Navigator after Importing EDIF Netlist MACH PAL Properties in the EDIF File Property List If you have chosen a MACH or PAL device for your EDIF design the ispDesignExpert takes design specific constraints as properties from an EDIF netlist T
151. s a lower level module implemented as an ABEL HDL block while Figure 3 37 shows the lower level module implemented as a schematic block add sch Both add abl and aad sch can be instantiated in the upper level source top abl MODULE top inputs AIN UJ IN CARRYIN pin outputs CARRYOUT SUMOUT pin add INTERFACE A B CI gt SUM CO my add functional block adg EQUATIONS my_add A AIN my_add B BIN my_add CI CARRYIN SUMOUT my add SUM CARRYOUT my add CO Figure 3 35 Top level ABEL HDL Module top abl ispDesignExpert User Manual 70 Hierarchical Design MODULE add inputs A B CI pin outputs CO SUM pin EQUATIONS SUM A amp B amp CI A amp BE amp CI A amp BE CI A amp BE amp CI CO A amp B A amp C B amp CI END Figure 3 36 Lower level ABEL HDL Module add abl Figure 3 37 shows the schematics for the lower level ABEL HDL module Add It can also be instantiated by the top ab1 design Figure 3 37 Lower level Schematic Block add sch ispDesignExpert User Manual 71 Hierarchical Design NOTE fyou are in a lower level schematic you can choose Add New Block Symbol and then click Use Data From This Block on the dialog box to automatically create a functional block symbol for the
152. s in the Timing Matrix Table You need to select Show Timing Data to calculate values for this source m Add Destination Timing Tag Adds the highlighted signal to the destinations in the Timing Matrix Table You need to select Show Timing Data to calculate values for this destination m Frequency Adds the highlighted signal to the frequency table and shows the values for that signal m Tco Path Displays the Tco Path Table with the Tco values for that signal m Setup and Hold Displays the Setup and Hold Table with the Setup and Hold values for that signal m Tpd Path Displays the Tpd Table with the Tpd values for that signal ispDesignExpert User Manual 156 Timing Analyzer for ispLSl Timing Explorer Tables The following tables are available in the Timing Explorer They are displayed when you request that timing information from the Compiler Results menu from the Physical Viewer or from within the Timing Explorer m Timing Matrix Table Figure 6 2 Clock Frequency Table Figure 6 3 Setup and Hold Table Figure 6 4 Tco Table Figure 6 5 Tpd Table Figure 6 6 You may wish to tile or cascade the tables for easier access You can adjust the column widths by moving the cursor to the line at the right side of the column heading and dragging it to change the column size Once the tables have been created you can move between the tables or redisplay a closed table using the View menu or the Timing Matrix Table
153. selected is attached to the pointer Place the symbol by clicking on the schematic 4 Move the cursor back to the Symbol Libraries dialog box and select another symbol Place the symbol in its proper position on the schematic 5 From the Schematic Editor menu bar select Add Wire Click on the output pin of a gate to start the wire Each successive click will bend the wire a double click will end the wire if it is not connected Connect the wire to the input of a gate 6 Repeat the above procedure to add other symbols or macros from the Symbol Library If necessary add design attributes and design control properties to the schematic ispDesignExpert User Manual 90 Mixed Entry Design Create an ABEL HDL Source File Now you need to create an ABEL HDL source file and link it to the symbol on the top level schematic 7 To create the source highlight the top source then select Source New In the New Source dialog box choose ABEL HDL Module and click OK The Text Editor window appears with New ABEL HDL Source dialog box Figure 3 58 PAIS if el F be Tara Qmm be BEBE sqm E034 E ES i Fia mr Figure 3 58 Text Editor Window with New ABEL HDL Source Dialog Box In order for the file to be linked to the symbol the Module Name must match the symbol name The File Name does not need to match the symbol name Fill in the text fields with relevant contents Click OK You will now be in the Text Editor and w
154. sing the Template 150 Export VHDL Test Bench or Verilog Test Fixture from Waveform Editor 151 Performing the VHDL Verilog Functional Timing Simulation 045 152 Chapter 6 Timing Analysis seeeleeeeeeeeeeeee 153 ney Aris COVERS PETERET IT TT TIL T 100 TIULTTTDTTTTM 154 Timing Analyzer for IBBEST ce ees eke oi AS RIO OEC AGE E eR dob ca ea 154 yrs MMC Tr T m 154 SS ORI kerrin bee abe 64 hed eRe eR dobolbb d oC opidi deba abba die 155 Pop up Menus from the Signal Navigator 00 0c eee eee eee 156 Tm Explorer TAGES coude ua cdd dere ns ee d OH ED eu a aG EE 157 Pop Up Menus from the Timing Tables 00 000 eee 159 ELI ERO EE 500014200122 a a de kee ae Ree bal BE ah 160 Performance Analyst for MACH D SIONS 2 sce d oss x ER oe Pe eee se ee ACA RI RO E RR 161 Anass ch hs ai dore Je doo i Pob Epl I RE e RC dee Reese OE APA 161 P M O OPPPTM 161 ci Se p bepiqbrAqas ee ee ee ees ee eee ee re re ET E 162 IM oues ecd eR axe URS VES Md ar are nee nme Pee RUE qq xA 164 lt 2 P H Y XG 164 EL ewe IDA hr HERR EAT on ied Rai gas de dede ied pape Pact caen deed 165 I SEE E ESE qat IRE SS eoe dd PR C UN ERE ORE eO Ll ee 165 Running Timing Analysis naaa cour RR RRRRRR mx mer 166 Running Timing Analysis in Batch Mode 00002 cece eee ees 169
155. sources can include several types such as ABEL HDL descriptions VHDL descriptions Schematics EDIF netlists or simulation files To import existing sources into your project 1 Choose Source Import to open the Import File dialog box Figure 1 5 L3 nnper riori wi Figure 1 5 Import File Dialog Box 2 Inthe examples ispLSI_GAL clock directory select all of the files clock wdl clocktop abv clocktop sch control sch hours abl minutes abl presclr abl seccntr abl and sseg ab1 These will be the source files for your new project Figure 1 6 impor Fila Reaches ABEL 1280 abi clackiop abe ciorkiep ich conti n i Emors ab sok whi Figure 1 6 Import File Dialog Box Select Existing Source Files 3 When you are finished selecting these sources click OK The selected sources appear in the Project Navigator Sources window Figure 1 7 ispDesignExpert User Manual 17 Creating a New Project Pie wies nuce moris phori wWindoe Took Hep SES Tl sirang Ps Ee spl 550 d 125L UH clock sit clocking nine 2 clucking fehorkinp ek jj ceaniral intres ioc p eec tape abi reng omg abil EV MINUTES mimoos shi Eiseng s5eq nbi j PRESCLR tprescir abi Z eecrenir eeccntr nbi Selectthe Hew bulang ddd icce cr Hapro are malahi ter the Pimper inthe Sacs menudo add im n pr gertnaisbock Select another fem in iexisin design the Source kehto gel proteinai Ready Figure 1 7 Pro
156. t Viewer Green check marks indicate the process completed successfully You can use the File Full Project Path menu item of the Project Navigator to view your Project Path from the prompt Full Project Path dialog box Figure 1 14 Full Project Path Lx d isptools ispsys examples test TEST SYN Figure 1 14 Full Project Path Dialog Box ispDesignExpert User Manual 21 Creating a New Project Delete the Project Files After you have completed this quick tutorial you can delete the project files from your computer To delete the project files 1 Choose the File Close Project menu item 2 Using the Windows Explorer or similar tool go to the examples directory and delete the cest folder ispDesignExpert User Manual 22 Chapter2 Project Management The Project Navigator is the primary interface for the ispDesignExpert and provides an integrated environment for managing the project elements and processes This chapter contains a detailed explanation of how to use the Project Navigator to interact with the software from creating design files through downloading the design The design procedures are described with examples of the menus and dialog boxes needed to perform these tasks This chapters covers information on the following topics About the Project Manager Describing a Project Changing the Environment and Configuration Cleaning up a Project Saving a Project ispDesignExpert User Manual 23
157. t input pins in the Input Pins text field relevant output pins in the Output Pins text field and relevant bidirectional pins in the Bidirectional Pins text field If you want to create a symbol that represents the current schematic click on the Use Data From This Block button The edit fields are automatically filled with the names of those nets that are labeled with I O markers If you have already labeled all nets with I O markers you won t have to enter anything manually If you want to create a symbol from an existing design source including ABEL HDL VHDL Verilog HDL or schematic click on the Use Data From NAF File button The Select File dialog box opens Select the naf file whose base name is the same as that of the symbol you want to create the edit fields are automatically filled with the names of those nets defined in the naf file When you import create or save a design source abl1 sch vhd or v file in a project naf file s containing all the information of module ports in the design source with the same name as modules in the abl sch vhd Or v file will automatically be generated and saved under the current project directory Refer to page 50 for more information on how to create a symbol 4 Click Run ispDesignExpert User Manual 88 Mixed Entry Design New Block Symbol Block Name Use Data From This Block Input Pins Output Pins Bidirectional Pins Bun Cancel Edit
158. t one level below the schematic in which the symbol appears Or the schematic is at one level above the Block s module Regardless of how you refer to the levels any design with more than one level is called a hierarchical design Advantages of Hierarchical Design The most obvious advantage of hierarchical design is that it encourages modularity A careful choice of the circuitry you select to be a module will give you a Block symbol that can be reused Another advantage of hierarchical design is the way it lets you organize your design into useful levels of abstraction and detail For example you can begin a project by drawing a top level schematic that consists of nothing but Block symbols and their interconnections This schematic shows how the project is organized but does not display the details of the modules Block symbols You then draw the schematic for each Block symbol These schematics can also contain Block symbols for which you have not yet drawn schematics This process of decomposition can be repeated as often as required until all components of the design have been fully described as schematics Breaking the schematic into modules adds a level of abstraction that lets you focus on the functions and their interaction rather than on the device that implements them At the same time you are free to view or modify an individual module ispDesignExpert User Manual 67 Hierarchical Design Although there are many ways of
159. the VHDL Verilog Functional Timing process from the Processes window The ModelSim Simulator prompts with simulation messages showing in the Transcript window When the simulation is done you will see End in the Transcript window ispDesignExpert User Manual 152 Chapter6 Timing Analysis The ispDesignExpert has two built in static Timing Analyzers that are device dependent For ispLSI devices the Timing Analyzer can be accessed to provide accurate pin to pin timing formation for your design For MACH and PAL devices you can use the Performance Analyst to analyze the permanence of your design after it had been optimized and implemented by the Fitter The Timing Analyzer calculates maximum clock frequency calculates chip boundary setup and hold requirements calculates Tpd and Tco path delays calculates GLB boundary delays and performs path enumeration Generally speaking Timing Analysis can be performed after you compile or fit a design This chapter covers information on the following topics m Timing Analysis Overview m Timing Analyzer for ispLSl m Performance Analyst for MACH ispDesignExpert User Manual 153 Timing Analysis Overview Timing Analysis Overview The static timing analyzer enables you to evaluate the performance of the design after successful compilation The analyzer traces all the signal paths and their delays determines critical timing paths and evaluates maximum frequency of the design and setup hold re
160. the same as the file name of the test bench m the instance name of the top design module is UUT While creating a Verilog test fixture file you need to following these rules m the name of the test module must be the same as the file name of the test fixture m the instance name of the top design module is a ispDesignExpert User Manual 149 ModelSim Simulator Manually Create VHDL Test Bench or Verilog Test Fixture You can manually create a VHDL test bench or a Verilog test fixture in the Text Editor Refer to other third party manuals for VHDL test bench and Verilog test fixture syntax rules Create VHDL Test Bench or Verilog Test Fixture Using the Template Once you have an ABEL HDL a schematic a VHDL or a Verilog HDL source in your ispLSl GAL MACH or PAL project you can use the VHDL Test Bench Template process associated with the selected source in the Project Navigator to generate a template file vht for the test bench In order to use the test bench you must edit or rename it with the extension vhd Then you can add relevant contents to the vhd file and save it as the VHDL test bench for your project A CAUTION The VHDL Test Bench Template vht is an intermediate file that can be deleted when using the File gt Clean Up All command of the Project Navigator Do not save your modifications to the vht file And you can use the Verilog Test Fixture Declarations process associated with the
161. the software partitions and fits the design into the target device Note that check marks have been added to Compile Fit Design process that have been successfully completed Figure 4 23 ispDesignExpert User Manual 134 y he rag nL ped Frnject Hoensgale Lying mp sch E prep prep ech A pcompeeg compare abl Zycnunter caur amp er ifj Compiling Fitting the MACH PAL Designs CASE TOOLS SPSr soe Mm x Optom ndre Jons Hep Processes ine Corres Source DX Upieie Al Schemebe Files KW Coma aim E diti a EPF Exquntinns EyEsgnal Cross Pakana Ey nter Report E Poet Fit Pinnute a ab JEDEC Fle V Timing Aahyees Oi Ganernia Timesg Simulntinn Filisi EjRapart Fae Dovbledichs dogi a diwenidesce Coutechck he Famin he buloi elad ha Sit baina m an te peocess Salertiha Fanperter betonia raithe property editor Saj e iaa Figure 4 23 ispDesignExpert Project Navigator after the Fit Design Process of MACH PAL Designs NOTE Yellow exclamation besides the process points indicate that warnings were generated Red Xs indicate that errors were encountered The warning or error is described in the auto make log file displayed in the Report Viewer Green check marks indicate the process completed successfully 4 Double click on the Fitter Report process from the Processes window to see the statistics related to the fitting of your design Figure 4 24 Py Repor Viewer pz Tut pi
162. tor With the schematic source opened in the Schematic Editor choose the Edit Attribute Symbol Attribute or Edit gt Attribute Net Attribute menu item The Symbol Attribute Editor or Net Attribute Editor dialog box appears prompting you to assign attributes For example if you want to add a symbol attribute to a symbol 1 With the schematic source opened in the Schematic Editor select Edit gt Attribute Symbol Attribute The Symbol Attribute Editor dialog box displays Select the target symbol from the schematic source 2 In the Symbol Attribute Editor dialog box check the List All Attributes option to show all the available symbol attributes Choose the desired symbol attribute and set the value to the attribute 3 Click Go To or press Enter in the Symbol Attribute Editor dialog box ispDesignExpert User Manual 102 MACH Design Attributes In ABEL HDL ABEL HDL source files have their own syntax for describing characteristics MACH LOCATION PinName PinType PinNo BlockNo SegmentNo Example module cntbuf2 title Counter and Bidirectional Buffer Library mach MACH LOCATION PinName PinType PinNo BlockNo SegmentNo PinType Input Output Node PinNo BlockNo SegmentNo Any pin block or segment Not applicable for BlockNo or SegmentNo MACH LOCATION Clk input 11 MACH_LOCATION Clr input B MACH GROUP GroupName BlockN
163. uct the ispDesignExpert to question the user if routing time is very long You can decide to continue or stop and relax some design constraints before trying to compile again ispDesignExpert User Manual 122 isoLSI Compiler Properties Carry Pin Direction The Carry Pin Direction option maintains user specified pin directions in any simulation output The default is Off m Carry Pin Direction On attempts to maintain user specified pin directions for 3 state outputs into any simulation output netlist The 3 state outputs can be connected to external output pins or bidirectional pins m Carry Pin Direction Off converts 3 state outputs to external output pins in any simulation output netlist Case Sensitive The Case Sensitive option enables ispDesignExpert to treat identifiers such as pin names and net names as case sensitive or case insensitive The default is Off m Turning on Case Sensitive results in consideration of identifiers as case sensitive m Turning off Case Sensitive results in consideration of identifiers as case insensitive Timing Analyzer The Timing Analyzer option allows you to run the Timing Analyzer during the compiler step or turn off the Timing Analyzer m If you specify TIMING ANALYZER Off your turn off the Timing Analysis during the compilation and a timing report is not generated m If you specify TIMING ANALYZER On the Timing Analyzer runs during the compilation This generates the Clock Frequency T
164. uctor Corporation E CMOS GAL ispGAL ispLSI pDS pLSI Silicon Forest and UltraMOS are registered trademarks of Lattice Semiconductor Corporation SPEEDSearch Perfomance Analyst and DesignDirect are trademarks of Vantis Corporation Kooldip MACH MACHPRO MACHXL Monolithic Memories PAL PALASM and Vantis are registered trademarks of Vantis Corporation Project Navigator is a trademark of Data I O Corporation ABEL HDL is a registered trademark of Data I O Corporation Microsoft Windows and MS DOS are registered trademarks of Microsoft Corporation All other trademarks and registered trademarks are the property of their respective owners Lattice Semiconductor Corporation 5555 NE Moore Ct Hillsboro OR 97124 503 268 8000 December 1999 ispDesignExpert User Manual 2 Limited Warranty Lattice Semiconductor Corporation warrants the original purchaser that the Lattice Semiconductor software shall be free from defects in material and workmanship for a period of ninety days from the date of purchase If a defect covered by this limited warranty occurs during this 90 day warranty period Lattice Semiconductor will repair or replace the component part at its option free of charge This limited warranty does not apply if the defects have been caused by negligence accident unreasonable or unintended use modification or any causes not related to defective materials or workmanship To receive service during the 90 day w
165. uodasocoezaduR RR Ru crebrius 91 Compile the ABEL HDL Source Ple iu desear uon cheeks Ron RC ee de oe RC C a 92 Schematic and VHDL Mixed PEDIS oo dede dO EORR B Reb Pede ee eee 94 Create a VHDL Source File ge cick ded dc did EET a ARE e Re eR ded Rb Ra eO ER E A 94 Schematic and Verilog HDL Mixed Entry 00 00 eee eee 95 ispLSI Design Attributes 0 0 nee 96 Assigning ispLSI Design Attributes in Project Sources 0000 cee eee 96 he SIG REPETI c PCT 96 ey 6 6 6 tbe HENCE E donde ip Ho UC AE PCIE o OR no HERE Cj ra 98 HLS AMOUS PI eee 22d dob ioo doc dodo dd fbl bed d DOR d EO ODE FCR Re dal odd 99 Precedence of Design Attributes o 2ocscuooulcoclu acce Roux re wor dbed uua 101 MACH Design AMrDUTES paEMNM nnm 102 Assigning MACH Design Attributes in Project Sources 0000 0c eee 102 p ODE C aaa gei EROR obo VOY AER ab dee defer Pe doa d Ea eed 102 i BRL NO eid FIRE eee CEDERE E E d GO dp RICE Cn die da aoo 103 Chapter 4 Design Implementation luueeee 105 Constraint Manager for ispLSI Designs liliis 106 Man POI PFETTTRPCTICUMT TT TrrTTTTT 106 DS SH UBI a dod 3 a b e re EE acr e I OE ORI Rol dad 107 FILODIDUIES Vs a or cd Che bet ORC ER EUR dH CE e e oa het di e od ede 107 HET AIDS Tabie 21 d bas dled oe Rocio poo oC oce Rob boe d deos 108 Symbol Atiributes Tabl iosadeteRbetbusckossexdaduEARRESRadE o DIIed donee 108 Bos BONIS VUES dau ue atr E coos ea
166. ure 27 VHDL 27 VHDL test bench 27 waveform stimulus 27 Sources window Project Navigator 26 Spread design MACH global optimization option 128 Spread placement advanced MACH global optimization option 129 Starting ispDesignExpert 14 Strategy ispLSI compiler property 120 Symbol add to schematic 46 add to top level schematic 94 create 50 Symbol Libraries 46 Index T tCO analysis type Performance Analyst 164 Tco Table Timing Explorer 157 tCOE analysis type Performance Analyst 165 Test stimulus create for Lattice Logic Simulator 137 generate for ModelSim Simulator 149 Test vector create for Equation Simulator 144 Text Editor open 33 43 Timing Analyzer for ispLSI GAL 154 functions 154 ispLSI compiler property 123 Timing Explorer accessing 154 adjust table columns 157 Clock Frequency Table 157 Setup and Hold Table 157 Signal Navigator 155 Tco Table 157 Timing Matrix Table 157 Tpd Table 157 Timing Matrix Table pop up menus from 159 Timing Explorer 157 Timing Path Report 160 Timing Paths displaying 160 Timing simulation ispLSI GAL run 137 Verilog HDL perform 152 VHDL perform 152 tOE analysis type Performance Analyst 165 TOE AS IO ispLSI device option 126 tPD analysis type Performance Analyst 164 Tpd Table Timing Explorer 157 ispDesignExpert User Manual 175 tSU analysis type Performance Analyst 162 U UES Data type 127 Signature size 127 Use extended routing ispLSI compiler property 122 Use globa
167. ure 5 4 Simulator Control Panel Stand alone Mode 2 Select File Open Design from the Simulator Control Panel window The Open Design dialog box displays Figure 5 5 Open hisi ae fo SO Es i Fila pana Filas Df he malen Figure 5 5 Open Design Dialog Box ispDesignExpert User Manual 141 3 Lattice Logic Simulator for ispLSI GAL In the Files of type field select the type of design you need to open Either a design for functional simulation edn or ed or a design for timing simulation sim The Simulation type field enables you to choose either Functional Simulation or Timing Simulation Choose a desired edn edf or sim file from the project directory amp NOTE A design with other file extensions can be loaded in the simulator But only design with correct format can be used to perform simulation successfully For example if you choose design s1 With sim format to do timing simulation a warning message will be issued The selected file extension does not match the simulation type Make sure that the edf edn file is used for functional simulation and Sim file is used for timing simulation Press OK to continue Click OK to continue You can load the file in the simulator successfully And you should be able to run timing simulation successfully after loading a stimulus file If you choose to load design s2 design that is not sim format you will get an error message
168. ures related to a whole symbol Symbol attributes usually apply only to the symbol on which they appear Net attributes describe characteristics associated with nets Every attribute consists of four components name value modifier and window You can assign either symbol or net attributes to a schematic via the Symbol Attribute Editor or Net Attribute Editor dialog box of the Schematic Editor With the schematic source opened in the Schematic Editor choose the Edit gt Attribute Symbol Attribute or Edit gt Attribute gt Net Attribute menu item The Symbol Attribute Editor or Net Attribute Editor dialog box appears prompting you to assign attributes For example if you want to add a symbol attribute to a symbol 1 With the schematic source opened in the Schematic Editor select Edit gt Attribute Symbol Attribute The Symbol Attribute Editor dialog box displays Select the target symbol from the schematic source 2 In the Symbol Attribute Editor dialog box check the List All Attributes option to show all the available symbol attributes Choose the desired symbol attribute and set the value to the attribute 3 Click Go To or press Enter in the Symbol Attribute Editor dialog box ispDesignExpert User Manual 96 ispLSI Design Attributes In Lower level Schematics Properties controlling design placement and routing are effective in any level of a hierarchical design You may place a property on any net or symbol in a hierarchi
169. urpul Fore BDF maisi i net Fl werlag netigi M LE Figure 4 12 Interfaces Dialog Box Advanced Compiler Settings Dialog Box Click on the Advanced button in the Settings tab The Advanced Compiler Settings dialog box displays Figure 4 13 This dialog box is used to specify additional compiler settings Figure 4 13 Advanced Compiler Settings Dialog Box Minimize GLB Levels For All Paths The Minimize GLB Levels For All Paths advanced option instructs the compiler to reduce the GLB levels on all paths in your design Default is High Use Internal Tristate IO Driver The Use Internal Tristate IO Driver advanced option controls whether the I O driver from the GRP is used for the internal tristate bus This option is only valid for ispLSI 8000 devices Default is Off ispDesignExpert User Manual 124 ispLSI Compiler Properties BFM Packing The BFM Packing advanced option controls the number of BFMs into which your design is placed in ispLSI 8000 devices Single PT Function Packing for Routability The Single PT Function Packing for Routability advanced option specifies how single PTs are mapped to macrocells in ispLSI 8000 devices Default is 0 Device Options The Device Options tab Figure 4 14 is for you to define objectives for the design implementation Options that are not applicable on that device are grayed out Figure 4 14 Compiler Properties Dialog Box Device Options Security The Security opti
170. wiew Options nim Hip TIMING AMALVZER LIE GLOBAL BESET HOR inteni Wi MEDIUM 2 OFF 16 4 Windows HT 4 0 comp COP KPa DELAY OFF Figure 4 21 Compiler Report isoDesignExpert User Manual 133 Compiling Fitting the MACH PAL Designs Compiling Fitting the MACH PAL Designs If you have completed your MACH PAL design you may want to fit the design into a target device Since you selected a device earlier in your design you can do the following 1 Select the device in the Sources in Project field of the Project Navigator window and observe the related processes If you have a MACH device no properties can be set for the Fit Design process If you have chosen a PAL device the ispDesignExpert software has several user controls that can be accessed from the Navigator highlight Fit Design and click the Properties button at the bottom of the Navigator window The Properties dialog box Figure 4 22 with design settings in it appears See the online help for explanations enre Fedundem Ficdinr klar Ecuscnlasi Feedback hue Doublg clck on the salecad Pam o toggle Fe tiat use te win region and pss T or F crouse the combo borio sed Figure 4 22 Fit Design Properties Dialog Box for PAL Designs 3 Double click the Fit Design process or click the Start button The ispDesignExpert Process dialog box appears The ispDesignExpert finishes compiling the source then links the source files together Finally
171. x2x1 sch and Figure 3 51 shows the lower level Verilog HDL module mux2x1v v Figure 3 49 Top level Schematic mux4x1 sch tpn Opp Figure 3 50 Lower level Schematic mux2x1 sch ispDesignExpert User Manual 81 module mux2xlv a b s output z input a b s reg z always 8 a or b or s begin case s l bi z b dT pO a default z bx endcase end endmodule Hierarchical Design Figure 3 51 Lower level Verilog HDL Module mux2x1 v v ispDesignExpert User Manual 82 Hierarchical Design Hierarchical Design Considerations Apply the following considerations when using hierarchical design techniques We take a hierarchical schematic design as an example The rules implied in the following example are also applicable to other types of hierarchical designs Hierarchical Design Structure When a symbol is placed in a schematic the component or subcircuit the symbol represents is added to the circuit For example when you place a latch symbol you are actually including the OR gate inverter and two AND gates from the latch s schematic Figure 3 52 shows on the left a 4 bit register REG4 constructed from four latch symbols 1atch sym The right side of the figure shows the underlying components The four latch symbols represent a total of eight AND gates four OR gates and four inverters Figure 3 52 Circuit REG4 and its Equivalent Circuit This hierarchical building process
172. y and Exemplar LeonardoSpectrum You need to vary pin locking syntax in a Verilog HDL file with the synthesis tool you are going to use Syntax for Synplify input signal name synthesis loc P lt pin_number gt output signal name synthesis loc P pin number Example The following example shows how to lock an input signal a to pin 5 module mux2xlv a b s z output z input a synthesis loc P5 b s reg z always Q8 a or b or s begin case s bis m5 1 b0 z a default z bx endcase end endmodule ispDesignExpert User Manual 116 Pin Locking for GAL PAL Devices Syntax for LeonardoSpectrum exemplar attribute signal name loc P pin number Example The following example shows how to lock an output signal z to pin 25 module mux2xlv a b s z output z input a b s reg z exemplar attribute z loc P25 always 8 a or b or s begin case s Pps a2 by 1 b0 z a default z bx endcase end endmodule ispDesignExpert User Manual 117 ispLSI Compiler Properties ispLSI Compiler Properties The Compiler Properties dialog box for ispLSI devices only lets you set options that can control the compiler process of your design specify global design control properties and User Electronic Signature Refer to the jspEXPERT Compiler User Manual for more details on design compilation options You can invoke the Compiler Properties dialog box

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