User Manual - MPL AG Switzerland
Contents
1. J7 J8 PC104 7T ISA Connector D6 User LED 1 zl am EH J5 Power Connector J2 JTAG J4 TPU Serial J6 Debug Connector Connector Connector Figure 3 1 PATI Parts Location 2009 by MPL AG 10 MEH 10102 001 Rev D High Tech Made in Switzerland 3 1 Connectors 3 1 1 J1 Analog Input and CAN Connector Signal Name I O Function Signal Name Pin Number Pinout reserved CAN2 High CAN2 Low 8 posu dc ode jm reserved High Low iid reserved Analog Input CH2 Tabelle 3 1 Analog Input and CAN connector 3 1 2 J2 JTAG Connector The JTAG connector is used for manufacturing only and is not intended to be used by the customer It is connected to the 2 EPLDs only The CPU is available on the Debug connector PORST 5 Tabelle 3 2 JTAG connector 2009 by MPL AG 11 MEH 10102 001 Rev D High Tech Made in Switzerland 3 1 3 J3 PC104 Interface pin numbers Number RowA RowB R2. High Tech Made in Switzerland PATI PowerPC controlled Analog and Timing I O Intelligence The PATI is a highly integrated I O board in PC 104 form factor Build around the MPC555 Motorola PowerPC Processor and the PLX9056 PCI Bridge it brings the superb MPC555 peripherals to a standard PCI interface With the possibilities for firmware update over the PCI bus parameter passing via the on board SDRAM allowing the PATI to access the host memory via PCI busmaster access and various configurations options it is well suited for fast prototyping application A stand alone mode allows the PATI to work without the host Application developed and tested in a host environment can be executed on the PATI in the stand alone mode without any code modification The MPC555 peripherals are available on 2 standard 50 pin 2 54mm header which offers easy connections It features 8 differential 10bit Analog Digital channels 32Bit TPU channels 2 serial Interfaces and 2 CAN interfaces e Features e Motorola MPC555 PowerPC Processor Low power consumption e 40MHz Processor Clock e 5V only Power Supply e 16MByte SDRAM on board 8 differentials 10bit Analog Digital converter channels up to 8MByte on board Flash e 32Bit TPU channels e 32Bit 33MHz PCI Agent Interface 2 Serial Interface Bus Master capable 2 CAN Interface 2009 by MPL AG 1 MEH 10102 001 Rev D High Tech Made in Switzerland 1 INTRODUCTION 1 1 AB
3. wait some time write data bits D11 first DO last for i 11 i gt 0 i clock is low if config amp 1 lt lt i 0 reg amp 1 lt lt 26 clear bit else reg 1 lt lt 26 set bit write32cfg pci cfg mem base PCI9056 EEPROM STAT reg clock eeprom 2009 by MPL AG 21 MEH 10102 001 Rev D High Tech Made in Switzerland written take it out from reset reg amp 0xF lt lt 24 clear all EEPROM bits set usero udelay 100 write32cfg pci cfg mem base PCI9056 EEPROM CTRL STAT reg 1 lt lt 16 clear usero write32cfg pci cfg mem base PCI9056 EEPROM STAT reg amp 1 lt lt 16 udelay 100 set usero write32cfg pci cfg mem base PCI9056 EEPROM CTRL STAT reg 1 lt lt 16 udelay 100 4 6 2 Hardware Configuration Word description The first programmed date is D11 the last is DO D11 D10 D9 D8 06 D5 D4 D3 D2 DO Desc PCIM BDIS PRPM ISBO ISB1 ISB2 IP FLAG Tabelle 4 10 Hardware configuration Bits PCIM Desc S 0 Normal Operation CPU and PCI Bridge can access the local bus PCI Only Mode Only PCI Bridge can access the local bus BDIS 0 Memory bank 0 is active and matches all addresses immediately after reset default Memory controller is not activated after reset PRPM 0
4. 025 026 027 p28 029 030 D31 ESNENM EN NEM 0 01 B5NO Tabelle 4 12 EPLD Configuration Register Bits Whereas SYS denotes the Source from the System Controller and SDRAM the SDRAM Controller Notes e Access to the EPLD register must be done as 32bit access only the byte enable lines are ignored in this area To reset these register a Power On or LRESET from the PCI Bridge is used So it is possible for the local CPU to write a new Hardware config word and performs a HRESET to start up in the new configuration 4 7 3 PLD Register Map Address Offset PLD ID Register Board Revision Timing and SDRAM Controller Register Tabelle 4 13 EPLD Configuration Register Address 4 7 3 1 EPLD ID Register The EPLD ID Register is used to identify the EPLD Part and Version Depending on these ID s the Registers may differ This Document describes the initial Version V00 POO and VOO P01 of the EPLD s System Controller Part ID Default d wh 1i 0 Tabelle 4 14 EPLD Part ID Register 2009 by MPL AG 23 MEH 10102 001 Rev D High Tech Made in Switzerland 4 7 3 2 Board Revision amp Timing SDRAM Controller Register System Controller o Di Ds Di B5 5 1030 E SDRAM Controller Tabelle 4 15 Board Revision amp Timing Register Board Revision Binary value o
5. RCPU starts up normal default RCPU starts up in Slave Mode CONF Desc O0 j Hardreset Config is sampled from PLD default if SW1 7 Off Hardreset Config is sampled from internal Flash default if SW1 7 On ISB 2 0 Base address ofthe internal memory space 001 010 011 100 101 110 111 Desc Exception vector table starts at 0 0000 0000 default if SW1 5 On 1 Exception vector table starts at OXFFFO 0000 default if SW1 5 Off FLAG This Bit can be set or cleared when writing the Hardware configuration word and can be read back by the local CPU May be used for deciding the start up mode Boot Index 2009 by MPL AG 22 MEH 10102 001 Rev D High Tech Made in Switzerland 4 7 EPLD Configuration Register 4 7 1 Configuration Registers Mapping Ara Sie CPU CCP PCIBridge Registers CS3 0x00000000 0x00000FFF Access via base address in PCIBARO PLD Registers CS3 0x00001000 0x00001FFF 0 07000000 0x07001FFF Tabelle 4 11 EPLD Configuration Register Mapping 4 7 2 EPLD Registers The EPLD Register are located in a 32Bit wide area but not all bits are useable Since 2 EPLDs are using the same config area the registers are fragmented Bits DO D1 5 D3 D4 D5 56 57 bs D9 1010 D11 D12 D13 D14 015 Ah 5o D lL Bits D16 D17 D18 D19 020 D21 022 023 024
6. 32 enD GND l Tabelle 3 7 PC 104 connector 2009 by MPL AG 14 MEH 10102 001 Rev D High Tech Made in Switzerland 3 2 Switch Default switch settings are bold 3 2 1 DIP switch S1 Configuration switch Switch On X Jot X 3 J J 9S S12 PCI Slot Selection see below Tabelle 3 8 S1 Software Configuration Switch 1 1 amp S1 2 sets the PC104 Slots The Slot 1 is if the PATI is mounted direct on the host Slot 2 is if there is another card between the PATI and the host 1 2 S1 1 PCIMux Off Slot 1 Slot 2 Slot1 Slt2 PCI Disabled If this switch is on the PATI act in stand alone mode Do not switch on if using the PATI in PCI Agent mode It will assert the PCI Reset Signal and your host system will become inoperable Zee e888 ERREEN If switched on the PATI will boot regardless if it is initiated by the PCI host If switched on the host has to issue the Hardware configuration word to start up the PATI These switches are not defined in the PCI Agent mode They are readable via the Software In Stand alone Mode these switches decide over different boot modes 2009 by MPL AG 15 MEH 10102 001 Rev D MPL High Tech Made in Switzerland 4 Operation PATI The following chapters describes the operation of the PATI in the PCI Agent mode The information are based on the environment used for
7. 6 1 Flash access problem while programming the MPC555 PLL When programming the MPC555 PLL to 40MHz the access to the external flash fails The reason is that the CLOCK Out Signal of the MPC555 is unstable in this state To solve this problem the part which programs the PLL is copied into the internal SRAM and executed from there 6 2 MPC555 does not allows access to the internal Peripheries The MPC555 does not allow access to it s internal peripheries while running in normal mode In Slave Mode Bit PRPM set this access works This problem has not yet been solved since the U Boot mapping doesn t allow the access to the internal peripheries anyway This is because the internal peripheral must be mapped below the first 16MByte to allow external master access and this entire area is assigned to the SDRAM 6 3 MPC555 asserts resets if using PATI in PCI only mode or slave mode Since the MPC555 watchdog is enabled after a power on reset the MPC555 asserts HRESET if the CPU does not get the local bus PCl only mode or and it is configured in slave mode This may lead to erroneous access which may even cause a system hang Workaround e configure the PATI in PCI only mode CPU slave and IMMR below 16MBytes e disable the watchdog write OXFFFFFFO01 to the SYPCR Register 6 4 PLX Bridge hangs if an access doesn t terminate missing TA If a direct slave access is disturbed by a HRESET happens only if the MPC555 is not running the PLX Brid
8. Slave Space 1 Register for SDRAM access To map the Direct Slave Space to other areas the registers Direct Slave Space 1 Local Base Address and Local Address Space Local 1 Bus Descriptor must be set accordingly The range register should not be touched because the PCI mapping done by the BIOS relies on the size of the initial configuration Following contents is used to access the flash Register 1 Contents Description 1 1 LAS1BA PCIBARO 0xF4 0x03000001 Local address of the Flash and enabled LBRD1 PCIBARO 0xF8 0 00000241 Bus Descriptor clear 8 no burst set 9 prefetch set 6 TA enable set 1 0 to 0x1 bussize 16bit Tabelle 4 6 Direct Slave Space 1 Register for Flash access Following contents is used to access the CPU Register sd LAS1BA PCIBARO 0xF4 0x01000001 Local address of the CPU and enabled Bus Descriptor clear 8 no burst set 9 no prefetch set 6 TA enable set 1 0 to 0x3 bussize 32bit Tabelle 4 7 Direct Slave Space 1 Register for CPU access LBRD1 PCIBARO 0xF8 0 00000243 Note e The CPU access is only possible if taking the MPC555 in slave mode and change the IMMR Address below the first 16MByte 4 5 5 Direct Master Mapping The CS2 signal is used to select the direct master area on the PCI Bridge The EPLD converts the CS2 signal to the local address 0x01XXXXXX So the PCI Bridge sees the access to the direct maste
9. access to the EPLD configuration Registers and to the SDRAM area 1 Set the bits CAL RCD WREQ PR and RC in the Board Revision amp Timing SDRAM Controller Register according to the populated SDRAM Chips currently CAL 1 RCD 0 WREQ 0 PR 0 RC 0 Note Access to the EPLD area MUST be done 32 bit wide So read the register first set clear the bits and write it back Set the bit IIP in the Board Revision amp Timing SDRAM Controller Register This issues a precharge all command to the SDRAM Poll the IIP Bit and if it is cleared wait for at least 8 refresh 200usec before proceeding 8 refresh a 17usec 136usec Set the bit LMR in the Board Revision amp Timing SDRAM Controller Register This causes the next access is a set mode register command to the SDRAM The Mode register address is 0x0C8 if the CAL bit is 1 and 0x88 if CAL is 0 Read from the SDRAM Start Mode Register Address to load the value into the SDRAM The SDRAM should now be accessible normal 5 6 Start Up the PATI To start up the local CPU write the hardware configuration word with the PCIM and the PRPM cleared The default hardware configuration word is OxOOFO If using in the default configuration it is sufficient to clear the USERo bit and set it again If the S1 4 is On the PATI starts with the default configuration word after power up 2009 by MPL AG 29 MEH 10102 001 Rev D High Tech Made in Switzerland 6 Open issues
10. disable the CPU set the bit PCIM and the PRPM bit in the hardware configuration word You may set also the ISP bits to an address below 16MByte to have access to the CPU peripheries After the Hardware configuration word is written you have access via the PCI Bridge to the area you have programmed in the LASORR LASOBA LBRDO and the LAS1R LAS1A LBRD1 Registers 5 4 Program the Flash To erase program the external flash you have to configure to have access to the EPLD configuration Registers and to the Flash area 1 Set the external Flash VPP by setting the Bit EXT VPP and clearing the Bit EXT WP in the Misc Config Register Note Access to the EPLD area MUST be done 32 bit wide So read the register first set clear the bits and write it back Determinate the flash type by reading its ID and erase program it according the specified algorithm Refer to the datasheet of the respective flash manufacturer for details Note Access to the Flash MUST be done in 16Bit mode only Please calculate the flash address via the various mapping register to get the physical starting address from the PATI 2009 by MPL AG 28 MEH 10102 001 Rev D High Tech Made in Switzerland 5 5 Set Up the SDRAM In normal operation the SDRAM is set up by the firmware on the PATI itself So set up the SDRAM from the PCI Bridge is only necessary in special cases such as booting directly from SDRAM To set up the SDRAM you have to configure to have
11. of measurement EN 55024 Information technology equipment Immunity characteristics Limits and methods of measurement EN 61000 4 1 Electromagnetic compatibility EMC Part 4 1 Testing and measurement techniques Overview of IEC 61000 4 series EN 61000 4 2 Level 3 Criterion B Electromagnetic compatibility EMC Part 4 2 Testing and measurement techniques Electrostatic discharge immunity test EN 61000 4 3 Level 3 Criterion A Electromagnetic compatibility EMC Part 4 3 Testing and measurement techniques Radiated radio frequency electromagnetic field immunity test EN 61000 4 4 Class 3 Electromagnetic compatibility EMC Part 4 4 Testing and measurement techniques Electrical fast transient burst immunity test EN 61000 4 5 Class 3 Electromagnetic compatibility EMC Part 4 5 Testing and measurement techniques Surge immunity test EN 61000 4 6 Class 3 Electromagnetic compatibility EMC Part 4 6 Testing and measurement techniques Immunity to conducted disturbances induced by radio frequency fields EN 61000 6 1 Electromagnetic compatibility EMC Part 6 1 Generic standards Immunity for residential commercial and light industrial environments EN 61000 6 2 Electromagnetic compatibility EMC Part 6 2 Generic standards Immunity for industrial environments EN 61000 6 3 Electromagnetic compatibility EMC Part 6 3 Generic standards Emission standard for residential commercial
12. 00 0 0 0 O CFGx Used for various Configurations SDRAM Type TBD 2009 by MPL AG 25 MEH 10102 001 Rev D High Tech Made in Switzerland 4 7 3 4 Misc Config Register The Misc Config Register is used to set the Hardware Reset word Since this doesn t make sense if the CPU is up and running this Register should only be read by the CPU Some of these bits are settable via the EEPROM channel please refer to 4 6 Hardware Configuration Word System Controller Bis DO D1 D5 D16 D20 D28 D29 D30 Lo _ f vP WP Defaut o o x x X xX x 0 o yo SDRAM Controller Bits D10 D14 D12 D13 D14 D19 D31 MUX1 Res Res Res Res Res Res Defaut x x o o o o O O Tabelle 4 17 Misc Config Register Memory bank 0 is active and matches all addresses immediately after reset default Co Memory controller is not activated after reset PCM PCIM O0 Normal Operation default Config Inputs These Bits are set if the corresponding DIP switch is on CFGO is D3 and CFG4 is D20 Normal Mode 54458 Description S On CFGx 1 Standalone Mode S4 CFGO Description S of P 0 SOE S5 CFG1 Description o Of 0 BootfromexemalFlash 10 0 0 00 S6 CFG2 Description gt S Off O Hardreset Config is sampled from PLD de
13. 5 OPERATION VIA THE PCI BUS 5 1 Normal Set Up 5 2 Set Up without programmed EEPROM 5 3 Set Up the PATI via PCI Bridge 5 4 Program the Flash 5 5 Set Up the SDRAM 5 6 Start Up the PATI 6 OPEN ISSUES 6 1 Flash access problem while programming the MPC555 PLL 6 2 MPC555 does not allows access to the internal Peripheries 6 3 MPC555 asserts resets if using PATI in PCI only mode or slave mode 6 4 PLX Bridge hangs if an access doesn t terminate missing TA 7 DEBUG CABLE WIRING 8 1 3 Safety 8 1 4 Type Approval 9 COPYRIGHT 10 DISCLAIMER 11 TRADEMARKS 12 SUPPORT 12 1 SERIAL NUMBER AND REVISION 12 2 CONTACT MPL AG 2009 by MPL AG 3 MEH 10102 001 Rev D High Tech Made in Switzerland TABLE OF FIGURES Figure 3 1 PATI Parts Location Figure 4 1 PATI Block Schematic Figure 4 2 PATI Mapping Overview Figure 12 1 PATI Label 2009 by MPL AG 4 MEH 10102 001 Rev D High Tech Made in Switzerland 1 INTRODUCTION 1 1 ABOUT THIS MANUAL This document describes the integration of the MPC555 SDRAM Flash and PCI Bridge on the PATI For detailed description of the MPC555 refer to the User Manual on www mot com and for a detailed description of the PCI Bridge PLX9056 refer to the User Manual on www plxtech com The manual is written for technical personnel responsible for integrating the PATI into their systems It is strongly recommended to read this manual before the PATI is switched on 1 2 SAFTY PRECA
14. BRO OXFFC00807 define ORO SCY is not used if external TA is set C81 SDRAM Bank Valid Burst Inhibit Port Size 32Bit External TA define BR1 0x00000007 define OR1 OxFF000000 SCY is not used if external TA is set CS2 PCI Bank Valid Burst Inhibit Port Size 32Bit External TA define BR2 0 03000007 define OR2 OxFFOO0000 SCY is not used if external TA is set CS3 Config registers Bank Valid Burst Inhibit Port Size 32Bit External TA define 0 04000007 define OR3 OxFFFFOOOO SCY is not used if external TA is set The internal Memory mapping is mapped via the Hardware Configuration word to 0x01C00000 set the Bits ISB 0 3 to 0x7 define IMMR 0 01 00000 Physical start address of internal memory map The U Boot bootloader fetches the first instruction from OxFFF00100 and reprograms the IP bit to O during initialization in order to set up its exceptions in the SDRAM So set the IP bit to 1 in the hardware configuration word 2009 by MPL AG 18 MEH 10102 001 Rev D High Tech Made in Switzerland 4 5 PCI Memory Map 4 5 1 PCI Bridge Local Bus Memory Mapping Since the PCI Bridge don t have a chipselect logic the local mapping of the PCI bridge is fixed Local Area Range Descriptor Tabelle 4 2 PCI Bridge Local Bus Memory Map Notes e Areas smaller than 16MByte are mirrored over the entire 16MByt
15. OUT THIS MANUAL 1 2 SAFTY PRECAUTIONS AND HANDLING 1 3 ELECTROSTATIC DISCHARGE ESD PROTECTION 1 4 EQUIPMENT SAFETY 1 5 MANUAL REVISIONS 1 5 1 RELATED PRODUCTS 1 5 2 REVISION HISTORY 1 6 RELATED DOCUMENTATION 1 7 ORDERING INFORMATION 2 SPECIFICATIONS 3 PARTS LOCATION 3 1 Connectors 3 1 1 J1 Analog Input and CAN Connector 3 1 2 J2 JTAG Connector 3 1 3 J3 PC104 Interface pin numbers 3 1 4 J4 TPU and Serial Connector 3 1 5 J5 Power Connector 3 1 6 J6 Debug Connector 3 1 7 J7 8 PC104 interface pin numbers 3 2 Switch 3 2 1 DIP switch S1 Configuration switch 4 OPERATION 4 1 Block Schematic 4 2 Mapping Overview 4 3 Used Environment 4 4 Local Memory Map 4 5 PCI Memory Map 4 5 1 PCI Bridge Local Bus Memory Mapping 4 5 2 PCI Bridge PCI Memory Map 4 5 3 Direct Slave Space 0 Mapping 4 5 4 Direct Slave Space 1 Mapping 4 5 5 Direct Master Mapping 4 6 Hardware Configuration Word 4 6 1 Writing the Hardware Configuration Word 4 6 2 Hardware Configuration Word description 4 7 EPLD Configuration Register 4 7 1 Configuration Registers Mapping 4 7 2 EPLD Registers 4 7 3 PLD Register Map 4 7 3 1 EPLD ID Register 4 7 3 2 Board Revision amp Timing SDRAM Controller Register 4 7 3 3 Hardware Word Config Register and Population Option Register 4 7 3 4 Misc Config Register 4 7 3 5 Reset Register 4 8 Resets 4 9 Interrupts and I Os 2009 by MPL AG 2 MEH 10102 001 Rev D High Tech Made in Switzerland
16. UTIONS AND HANDLING For personal safety and safe operation of the PATI follow all safety procedures described here and in other sections of the miscellaneous manual Remove power from the system before installing or removing the PATI to prevent the possibility of personal injury electrical shock and or damage to the product Handle the product carefully i e dropping or mishandling the PATI can cause damage to assemblies and components Do not expose the equipment to moisture WARNING There are no user serviceable components on the PATI 1 3 ELECTROSTATIC DISCHARGE ESD PROTECTION Various electrical components within the product are sensitive to static and electrostatic discharge ESD Even a small static discharge can be sufficient to destroy or degrade a component s operation With an open housing do not touch any electronic components Handle or touch only the unit chassis 1 4 EQUIPMENT SAFETY Great care is taken by MPL AG that all its products are thoroughly and rigorously tested before leaving the factory to ensure that they are fully operational and conform to specification However no matter how reliable a product there is always the remote possibility that a defect may occur The occurrence of a defect on this device may under certain conditions cause a defect to occur in adjoining and or connected equipment It is your responsibility to protect such equipment when installing this device MPL accepts no responsibil
17. and light industrial environments EN 61000 6 4 Electromagnetic compatibility EMC Part 6 4 Generic standards Emission standard for industrial environments MIL STD 461E REQUIREMENTS FOR THE CONTROL OF ELECTROMAGNETIC INTERFERENCE CHARACTERISTICS OF SUBSYSTEMS AND EQUIPMENT 2 2 2 Environmental 50155 Railway applications Electronic equipment used on rolling stock MIL STD 810 F ENVIRONMENTAL ENGINEERING CONSIDERATIONS AND LABORATORY TESTS 2 2 3 Safety 60601 1 Medical electrical equipment Part 1 General requirements for safety 60950 Class III Information technology equipment Safety 2 2 4 Type Approval EN 60945 Protected Equipment Maritime navigation and radiocommunication equipment and systems General requirements Methods of testing and required test results ACS E10 Test Specification for Type Approval 2009 by MPL AG 9 MEH 10102 001 Rev D High Tech Made in Switzerland 3 Parts Location J1 Analog Input S1 Config Connector E D4 Power OK i LED _ J3 PC104 PCI Connector
18. at support mopl ch Our local Distributor 2009 by MPL AG 32 MEH 10102 001 Rev D
19. e range e The CPU access is only possible if taking the MPC555 in slave mode and change the IMMR Address below the first 16MByte 4 5 2 PCI Bridge PCI Memory Map The PCI addresses are full configurable on the PCI side In a PC environment the configuration space must be mapped to the IO Space all others areas are mapped to the memory space The term Direct Slave denotes an area whereas the PCI host can access local memory The term Direct Master denotes an area whereas the MPC555 can access PCI host memory To save PCI resources the direct slave space 0 is assigned to the PLD configuration area and its size has been restricted to 256bytes The size of the direct slave space 1 is 1MByte and this space can be used for all other areas by reprogram the LAS1BA base address and LBRD1 Bus descriptor registers PCI Area Base Register Size Defaultlocal Area PCIBARO Configuration Space 3 PCI Confia Cycle 0x10 512Bytes PCI Bridge configurations Registers Aro 0 14 PCI Bridge configurations Registers Bec MN 0x18 EPLD configuration Registers Tabelle 4 3 PCI Bridge PCI Memory Map The EEPROM on the PATI sets all local addresses and sizes on start up The host BIOS should set the PCI addresses where these areas are accessible from the PCI bus 4 5 3 Direct Slave Space 0 Mapping The Direct Slave Space 0 is mapped by the EEPROM to the EPLD area This leads to following re
20. ent To have full access to the PCI resources the environment used to test the PATI consist of a PCI Host MIP405 without a operating system Instead a special version of the bootloader U Boot has been used The bootloader on the PATI is also a special version of the U Boot 4 4 Local Memory Map Although the PATI supports different boot modes only the boot from external flash is used so far and therefore discussed in this document The U Boot requires to have the SDRAM started from address 0 but with other software other mapping is also possible Local Address CS Area _ Size BusSize 0x01C00000 0x01FFFFFF MPC Internal Registers and Memory 4MByte 32Bit _ Tabelle 4 1 Local Memory Map Notes The EPLD Config Area and the External Flash are accessible only in their bus size The byte enable signals on these areas are ignored Access to all areas are self timed which means the MPC555 memory controller has to be programmed with the SETA bit Since the IP Bit is set on start up the MPC555 fetches its first instruction from the flash at address OxFFF00100 The PCI Master area is seen on the address 0x01000000 on the local bus of the PCI Bridge not on address 0x03000000 This is because the CS2 issues 0 01 to the PCI Bridge This mapping leads to the following MPC555 memory controller definition CSO Flash Bank Valid Burst Inhibit Port Size 16Bit External TA define
21. esentation either expressed or implied with respect to this product its quality performance merchantability or fitness for a particular purpose In no event will MPL AG be liable for direct indirect special incidental or consequential damages resulting from any defect in the product or its documentation even if advised of the possibility of such damages In particular MPL AG shall have no liability for any parts connected to this product MPL AG reserves the right to make changes to any product herein to improve reliability function or design 10 TRADEMARKS Brand or product names are trademarks and registered trademarks of their respective holders 11 SUPPORT 11 1 SERIAL NUMBER AND REVISION For support it is needed that you know the product name the product variant and the serial number of your PATI Please have a look at the label on the PATI for this MPL PATI 1 S N 100 A Production Production Serial Number Revision Number Figure 11 1 PATI Label 11 2 CONTACT MPL AG In case of general information questions please feel free to contact us at our homepage www mpl ch or per email info mopl ch In case of sales information questions please send an email to sales mopl ch If you have a technical problem with a PATI first please read the BIOS User Manual the Technical Reference Manual and also this manual carefully If you can t solve the problem on your own you can contact us for technical support per email
22. et the EECLK High wait some time set EECLK low again EOKCKCKCKCkCk Ck k ck ck ck ck kk A A k k k k k k k k k k k k k k k k k k k k k k kk k kk kk kkk kkk KK KK void clock_eeprom void unsigned long reg clock is low data is valid reg read32cfg pci cfg mem base PCI9056 EEPROM CTRL STAT udelay 1 set clock high reg 1 lt lt 24 write32cfg pci cfg mem base PCI9056 EEPROM CTRL STAT reg wait some time udelay 1 set clock low reg amp 1 lt lt 24 write32cfg pci cfg mem base PCI9056 EEPROM STAT reg wait some time udelay 1 J K K E E H kCkCkCk Ok ke ko kCkCkCK ko kCkCkCK Ok ko ko kk kk IARI IAAI IIIA I I Write HW config word Bit 11 in config is Bit 11 of Hardware config word Fe ck E AE E AE E ko AE E AE RRR RRA void write_hw_config unsigned long config we write the config via the BARO register into the configuration unsigned long reg int i reg read32cfg pci cfg mem base PCI9056 EEPROM CTRL STAT first assert LRESET reg 1 19 assert reset set usero as usero write32cfg pci cfg mem base PCI9056 EEPROM CTRL STAT reg udelay 100 wait some time reg amp 1 lt lt 16 1 lt lt 24 clear usero and clock write32cfg pci cfg mem base PCI9056 EEPROM CTRL STAT reg udelay 100 wait some time reg 1 25 set EECS write32cfg pci cfg mem base PCI9056 EEPROM CTRL STAT reg udelay 100
23. f the PCB Revision DO is MSB currently 0000 Waitx Waitstates for Flash access Access waitx 3 clocks Default 7 CAL CAL CAL o CAS Latency 2 1 CAS Latency 3 RCD o ACTIVE to READ or WRITE Delay RAS to CAS Delay lt 25ns ACTIVE to READ or WRITE Delay RAS to CAS Delay lt 50ns Desc o Write Recovery tWR lt 25ns Write Recovery tWR lt 50ns Desc Oo Precharge Command Time tPR lt 25ns Precharge Command Time tPR 50ns RC O Auto Refresh to Active Time lt 75ns Auto Refresh to Active Time 100ns Set this bit to write the Mode Register of the SDRAM If set the next access to the SDRAM is the Load Mode Register Command Set this bit to initialize the SDRAM Setting this bit issues a PRECHARGE ALL command to the SDRAM if read back as 0 the PRECHARGE ALL command has been issued To set up the SDRAM follow these steps e f set up via the PCI Bridge set the direct slave space 1 to the SDRAM start Set the bits CAL RCD WREQ PR and RC in the Register Set the bit IIP to issue a PRECHARGE ALL command After the IIP is read back 0 wait at least for 9 refresh cycles ca 200usec calculate the contents of the mode register set the LMR bit and read from the address MODE REGISTER SDRAM START 2009 by MPL AG 24 MEH 10102 001 Rev D High Tech Made in Switzerland 4 7 3 3 Hardware Word Config Register and Population Option Register The Hardware W
24. fault Dese UUU U O 0 Boot disabled no auto startup on power on SW1 4isOf CPU_VPP O0 _ VPP for the internal Flash is switched off default Cd EXT_VPP 0 VPP for the external Flash is switched off default Cid CPU_VPP O External Flash is not write protected default 1 External Flash is write protected 2009 by MPL AG 26 MEH 10102 001 Rev D High Tech Made in Switzerland MUX 0 1 Signals from PCI Muxers PCICLK PCIIRQ REQ GNT 1 On On 1 1 CLK3 IRQD REQ2 GNT2 Slot3 4 7 3 5 Reset Register A write to the Reset Register offset 0x010 causes the assertion of the HRESET 4 8 Resets The various reset sources of the PATI are assigned to following 3 reset states Reset States irr PORST HRESET SRESET Registers HRESET deasserted asserted asserted not reset Table 4 18 Reset States Reset State Remarks PCI RST Power On Reset Resets also the entire PCI Bridge PCI Software Reset CNTRL 30 1 asserts Power On Reset Resets parts of the PCI Bridge LRESET PCI Bridge USERO 0 CNTRL 19 1 HRESET State to write the HW Config CNTRL 16 0 Word PO CPU HRESET _ CPU SRESET CT SRESETH EPLD write to the Reset Register offset 0x010 HRESET Table 4 19 Reset Sources 4 9 Interrupts and I Os Several different states of the PCI Bridge may cause the assertion of the LINTo of
25. ge waits forever for a TA To reset the PLX Bridge a Power on reset is needed Workaround e Program the PLX Register LMISC2 PCI 0Fh LOC 8Fh Local Miscellaneous Control 2 to 0x0330 This causes a PCI Target Abort if the TA is not sampled within 1024 local bus clocks after TS Please note that on the PLX Bridge no method exists to detect this failure The register should only be modified on debug purposes 2009 by MPL AG 30 MEH 10102 001 Rev D MPL High Tech Made in Switzerland 7 Debug Cable wiring To connect the PATI to an ABATRON BDI2000 or similar Debuging Tools an atapter cable is necessary Please use the following wiring PATI J6 BDI2000 TARGET A 10pin 2mm Header 10pin 2 54mm Header female female Pin Number C Pin Number VFLSO VFLSO SRESET GND DSCK GND VFLS1 HRESET DSD DSDO Tabelle 7 1 Debug Cable wiring Notes e Please consult the documentation of your debug tool details 2009 by MPL AG 31 MEH 10102 001 Rev D High Tech Made in Switzerland 8 COPYRIGHT Copyright 2009 by MPL AG Elektronikunternehmen All rights are reserved Reproduction of this document in part or whole by any means is prohibited without written permission from MPL AG Elektronikunternehmen 9 DISCLAIMER MPL AG has fully tested the PATI and reviewed the documentation However MPL AG makes no warranty or repr
26. gister contents Register Contents Description LASORR PCIBARO 0x00 OxFFFFFFOO Range Register 256B LASOBA PCIBARO 0x04 0x07000001 Local address of the EPLD and enabled LBRDO 0x42430143 Bus Descriptor clear 24 no burst set 8 no prefetch set 6 PCIBARO 0x18 TA enable set 1 0 to 0x3 bussize 32bit Tabelle 4 4 Direct Slave Space 0 Register for EPLD access 2009 by MPL AG 19 MEH 10102 001 Rev D High Tech Made in Switzerland 4 5 4 Direct Slave Space 1 Mapping The Direct Slave Space 1 can be used to access the SDRAM Flash and CPU It s size is 1MByte To access an address which lies over the size of the Direct Slave Space 1 the higher part of the address has to be added to the local base address and written to the LAS1BA register For example an access to the SDRAM address 0x0089ABCD takes place when the LAS1BA register is programmed to 0x06800001 and an access at address of direct 1 contents of PCIBAR3 0x0009ABCD is performed The SDRAM area is the default mapping of the Direct Slave Space 1 This leads to following register contents Register Contents Description ae OxFFF00000 Range Register 1MByte 0x06000001 Local address of the SDRAM and enabled PCIBARO 0xF4 0x00000043 Bus Descriptor clear 8 no burst clear 9 prefetch set 6 PCIBARO 0xF8 TA enable set bit 1 0 to 0x3 bussize 32bit Tabelle 4 5 Direct
27. ity whatsoever for such defects however caused 2009 by MPL AG 5 MEH 10102 001 Rev D High Tech Made in Switzerland 1 5 MANUAL REVISIONS 1 5 1 RELATED PRODUCTS Revisions B De PATIA Rev A S 1 5 2 REVISION HISTORY Manual Description Revisions A 2004 01 05 Initial release of this document B 2007 03 14 j Refomated 0 0 0 0 0 0 O D 2009 10 01 Corrected Write Configuration Word Code 2009 by MPL AG 6 MEH 10102 001 Rev D High Tech Made in Switzerland 1 6 RELATED DOCUMENTATION The following documents are related to this manual For detailed Information about a specific PATI feature or setting please refer to this additional manuals Available from PATI Datasheet MPL AG www mpl ch 1 7 ORDERING INFORMATION The table below gives you an overview of the different PATI variants and its features Product Name Product Features 1 PATI 1 PATI 1 Board Revision A 2009 by MPL AG 7 MEH 10102 001 Rev D High Tech Made in Switzerland PATI 2 General information and specifications This chapter provides a general overview over the PATI and its features It outlines the electrical and physical specifications of the product its power requirements and a list of related publications 2 1 Specifications 2 1 1 Electrical Processor Freescale MPC555 PowerPC 32Bit RISC Processor Clock frequency 40 Mhz Very l
28. ord Config Register and Population Option Register is used to set the Hardware Reset word Since this doesn t make sense if the CPU is up and running this Register should only be read by the CPU Some of these bits are settable via the EEPROM channel please refer to 4 6 Hardware Configuration Word System Controller D16 D20 D28 D29 D30 Bis DO D1 D3 D5 Read i Read FLAG Boot Config Index PRPM CONF ISB Defaut o 0 o o o 0 o o o o SDRAM Controller Bits D9 D10 Dii D12 D13 D14 D19 D31 1 CFG2 CFG3 CFG4 CFG6 Defaut o o o o j O o o Tabelle 4 16 Hardware Word Config Register and Population Option Register This Bit can be set or cleared when writing the Hardware configuration word and can be read back by the local CPU May be used for deciding the start up mode After reset Exception vector table starts at the physical address 0x0000 0000 default After reset Exception vector table starts at the physical address OxFFFO 0000 a eae 0 BootfromExtemalFlash default Boot from Internal Flash 4 o 1 sd Bootfrom SDRAM PRPM Desc S O RCPU starts up normal default RCPU starts up in Slave Mode o Hardreset Config is sampled from PLD default Hardreset Config is sampled from internal Flash ISB Baseaddress of the internal memory space 000 0 0000 0000 defaut 0 0
29. ow power consumption Bootloader ROM Up to 8MB Flash EEPROM 512kB U Boot open source boot loader Memory 16MByte SDRAM on board PC 104 Plus Interface 32Bit 33MHz Master Slave Target only Analog 8 x differential Input Signal Input voltage range 0 V to 5 V Common mode range 5 V to 10 V 25kHz Samplingrate each 10Bit Converter Resolution TPU 32 Channel TTL Level CAN 2 x CAN2 0B Interface TTL Level 2 1 2 Physical Power Form factor PC 104 Plus compliant Module Length 95 9 mm 3 775 inches Width 90 2 mm 3 550 inches Weight Typical 90g Power supply Over PC 104 bus interface or through separate 3 pin Mini Combicon power connector Input Power requirement 5VDC 5 Power consumption Typical 2 5W 2 1 3 Environment Storage temperature range 45 C to 85 C Operating temperature range 20 C to 60 C 4 F to 140 F without heat sink extended temperature range available Relative humidity 5 95 non condensing 2009 by MPL AG 8 MEH 10102 001 Rev D High Tech Made in Switzerland 2 2 STANDARDS COMPLIANCE The PATI is designed to meet or exceed the most common industry and military standards Particular references are 2 2 1 EMC EN 55022 Class B Information technology equipment Radio disturbance characteristics Limits and methods
30. owC RowD 6 ADi1 5V ADi0 M66EN 33VP C BET aD15 33V 9 SERR GND SBO X PAR INTD INTA INTB INTC Tabelle 3 3 J10 PC 104 Plus connector Signal not available SBO SDONE and LOCK are pull up to 5V M66EN is connected to GND and 12V and 12V are not connected 3 3V pins are connected to a plane but not connected to the 3 3V Power Supply 2009 by MPL AG 12 MEH 10102 001 Rev D High Tech Made in Switzerland 8 GND 35 GND a ERO ae TXD1 1 amp 2 RS232 RXD2 TXD2 Tabelle 3 4 TPU and Serial connector 3 1 5 J5 Power Connector This connector is needed for stand alone operation only 3 pin power connector Phoenix Contact AG type MC1 5 3 G 3 81 Counterpart is the Phoenix Contact AG connector type MC1 5 3 ST 3 81 5 10 OI NNNM RR Pt Vn inpet voltage 65 Voc 2 3 SRESET System Reset Input active 10w Tabelle 3 5 J9 Power connector 2009 by MPL AG 13 MEH 10102 001 Rev D High Tech Made in Switzerland 3 1 6 J6 Debug Connector The Debug Signals of the MPC555 is available on a 10Pin 2mm Header 2 4 2 O 4 6 HRESET DSDI 8 VCC3 DSDO Tabelle 3 6 J6 Debug connector 3 1 7 J7 8 PC104 interface pin numbers The PC104 ISA connector is not used on the PATI only the power suppl
31. r area on the local address 0x01000000 Register Descripion Acces Tabelle 4 8 Register used to configure direct master access Note e The base address in the register DMPBAM will be set from the PCI host when enabling the master access 2009 by MPL AG 20 MEH 10102 001 Rev D High Tech Made in Switzerland The default mapping of the direct master access leads to following register contents Register Contents Description i O bit 31 16 PCI Address bit 15 0 0x0001 Enabled Tabelle 4 9 Default register contents for master access 4 6 Hardware Configuration Word To have this flexibility on the it is necessary to control the start up behavior of the MPC555 Therefore Parts of the Hardware configuration word for the MPC555 is writable via the PCI Bridge 4 6 1 Writing the Hardware Configuration Word This is done via the USERo Signal and the EEPROM channel 1 Assert LRESET gt asserts Power On Reset System Reset 2 Deassert USERo USERo 0 reset 3 Deassert LRESET gt PLL of CPU Starts but since the USERo is deasserted HRESET is asserted 4 Write the configuration via the EEPROM Channel into the PLD Data is latched with the rising edge of the clock 5 Assert USERo gt HRESET is released and the Hardware Configuration Word is latched in Following code is used for this purpose BK KK KKK ke ke s
32. rt the PATI up You could now reprogram the direct slave space 1 Registers to access another area than the SDRAM If using the direct master mode program the Direct Master Registers accordingly 5 2 Set Up without programmed EEPROM Setting up the PCI Bridge without programmed EEPROM is only needed if the EEPROM has been erased or wrongly programmed before Note Be careful if you assign PCI addresses to the different PATI address spaces The host BIOS may have already assigned the PCI address you like to assign It is recommended only to reprogram the EEPROM in this state and reboot the system Find the PCI Device with the Vendor ID 0x10B5 Device ID 0x9056 default PLX IDs Set the bits Memory Space access and IO Space access in the PCI Command register Get the Config Base Address by reading the PCIBARO Set registers LASORR LASOBA LBRDO and LAS1RR LAS1BA LBRD1 to a valid value Write OxFFFFFFFO to the registers PCIBAR2 and PCIBAR3 Read the registers PCIBAR2 and PCIBAR3 back to determinate the size value Set the registers PCIBAR2 and PCIBARS to a valid value Read the register PCIBAR2 and PCIBARS to get the base address of the direct slave spaceO and space1 area 1 2 3 4 5 6 T 6 5 3 Set Up the PATI via PCI Bridge After the PCI Bridge is set up you may want to program the flash or set up the SDRAM without the local CPU intervention This can be done by writing the Hardware Configuration word accordingly To
33. the PCI Bridge This allows the host to interrupt the local CPU The local CPU may interrupt the host by setting certain register bits in the PCI Bridge which causes the assertion of the PCI INT signal Additional the LINTi signal of the PCI Bridge is connected to the CPU with which the local CPU may also issue a PCI interrupt Two CPU I O signals are connected to user LED s with which the local CPU can signal different states to the user Following table shows the assigning of the interrupt and I O Signals CPU Connected to Signal Configured Direction Device Remarks Not yet used Table 4 20 Interrupts and I O routing 2009 by MPL AG 27 MEH 10102 001 Rev D High Tech Made in Switzerland 5 Operation via the PCI bus 5 1 Normal Set Up This chapter describes how to set up the PCI Bridge if the EEPROM is programmed 1 Find the PCI Device with the Vendor ID 0x18E6 Device ID Ox00DA 2 The bits Memory Space access IO Space access and Master enable in the PCI Command register should be already set by the BIOS 3 Getthe four Base Address for PCI Bridge config access I O space PCIBAR1 PCI Bridge config access in Memory space PCIBARO Direct Slave Space 0 Config Registers PCIBAR2 Direct Slave Space 1 SDRAM Access PCIBAR3 Depending on your host system you may set the endian register BIGEND PCIBARO OxOC If the PATI is not in the Boot direct mode clear USERO and set it again to sta
34. the first power up and may not be valid for other environments 4 1 Block Schematic 10 Connector1 50Pin Dual Row 2 54mm TPU amp RS232 RS232 Interface Serial 0 32Channel TPU RS232 Interface Serial 1 System Conroller PC 104 Connector PCI Part PCI Bridge PEI PLX9096 PowerPC MPC555 Local Bus Up to 8MByte Flash Analog Filter Analog In Up to 16MByte SDRAM soldered on Board SDRAM Conroller Figure 4 1 PATI Block Schematic 2009 by MPL AG IO Connector2 50Pin Dual Row 2 54mm Analog amp CAN Power Reset Connector Power Supply Module MEH 10102 001 Rev D D PATI High Tech Made in Switzerland 4 2 Mapping Overview MPC555 PCI Bridge Direct Slave 0x04001000 0x040010FF 0x07000000 0x070000FF Space 0 Local 0x04000000 0x04000FFF Configurations Register CPU 0x03000000 OxO3FFFFFF PCI 0x01000000 0x01FFFFFF Direct Master Address Access only possible if CPU in Slave Mode and translation IMMR below 16MByte Direct Slave 0x00000000 OxOOFFFFFF 0x06000000 OxO6FFFFFF Space 1 OxFFCO0000 OxFFFFFFFF 0x03000000 0x03FFFFFF Figure 4 2 PATI Mapping Overview Note e Accessing the CPU is only possible if taking the MPC555 in slave mode and change the IMMR Address below the first 16MByte 2009 by MPL AG 17 MEH 10102 001 Rev D High Tech Made in Switzerland 4 3 Used Environm
Download Pdf Manuals
Related Search