MANUAL UPDATE SHEET FOR TMS320C5X USER'S GUIDE
Contents
1. 107 106 105 104 103 102 101100 99 98 97 HINT WE EMUO HD1 EMU1 OFF _ RD Vssc PBK package HDO VSsCc HRDY TOUT E Top view VODA BCLKX A15 CLKX A14 Vppe C A13 BFSR A12 BCLKR A11 RS A10 READY CLKMD1 HOLD VSSA BIO VSSA Vooe C TDI vonc C DSi IAQ HDS2 TRST 1 VDDI VssI VDDI Vss L A9 MP MC A8 D150 A7 D14 A6 D13 AS D12 A4 D11 C A3 D10 A2 D9 A1 Ds AO Vppb VSSA VDDD HCS 34 35 36 37 38 39 40 41 42 43 46 47 48 49 50 51 52 RKRouowyrtrmOArao bart IN OO x JS AB Boa AA BASU BBS ABGEERCESES SEE AAR Re FFE aor vot z22ezere orano gt gt 6 63 gt gt gt I Oss I I 12 Page Change or Add A 7 In Table A 3 change the signal name on pin 108 to X2 CLKIN and reorder the signal names Table A 3 Signal Pin Assignments for the LC57 in 128 Pin TQFP Cle Cee Signal Pin Signal Pin AO 67 CLKMD3 107 VDDD 47 A1 68 CLKOUT1 125 HAS VDppi 77 A2 69 CLKR 61 NMI Vppi 78 A3 70 CLKx 8 PS Vppi 126 A4 71 DO 42 RD Vppi 127 A5 72 D1 41 HCS Vssa 66 AG 73 D2 40 RS VSSA 82 A7 74 D3 39 W VSSA 83 A8 75 D4 38 STRB Vssc 4 AQ 76 D5 37 Vssc 5 A10 85 D6 36 Vssc 97 A11 86 D7 35 Vssc 98 A12 87 D8 30 Vssp 33 A13 88 i D9 29 Vssp 34 A14 89 28 HDST TRST Vssp 49 A15 90 27 HDS2 VssD 50 BCLKR 11 26 HINT Vssi 20 BCLKX 7 25 HOLD Vssi 21 BDR 59 24 HOLDA Vssi 112 BDX 122 23 Vss 113 BFSR 10 DR 58 W WE 96 BFSX 119 DS IAQ X1 109 BIO 15 DX I2. the OVM bit Table 4 5 Status Register 0 STO Bit Summary Reset Bit Name value Function 15 13 ARP X Auxiliary register pointer These bits select the auxiliary register AR to be used in indirect addressing When the ARP is loaded the previous ARP value is copied to the auxiliary register buffer ARB in ST1 The ARP can be modified by memory refer ence instructions when you use indirect addressing and by the MAR or LST 0 instruction When an LST 1 instruction is executed the ARP is loaded with the same value as the ARB 11 OVM X Overflow mode bit This bit enables disables the accumulator overflow saturation mode in the arithmetic logic unit ALU The OVM bit can be modified by the LST 0 instruction OVM 0 Disabled An overflowed result is loaded into the accumulator without modification The OVM bit can be cleared by the CLRC OVM instruc tion OVM 1 Overflow saturation mode An overflowed result is loaded into the ac cumulator with either the most positive 00 7FFF FFFFh or the most negative value FF 8000 0000h The OVM bit can be set by the SETC OWM instruction 4 12 In Table 4 5 change the reset value for the DP bit so it has a reset value of X In other words there is no reset value for the DP bit Table 4 5 Status Register 0 STO Bit Summary Continued Reset Bit Name value Function 8 0 DP X Data memory page pointer bits These bits specify the address of the current data memory page T
3. 34 EMU1 OFF t 83 BIO 17 FSR t 97 BR 119 FSX t 101 CLKMD1 94 HAS t 117 CLKMD2 130 HBIL t 120 CLKMD3 121 HCNTLO t 125 CLKOUTI 140 HCNTL1 t 141 CLKR 68 HCS t These pins are not connected reserved 15 Page Change or Add D 2 In Figure D 1 change the PD pin 5 from 5V to Vpp Figure D 1 Header Signals and Header Dimensions TMS TRST TDI GND Header Dimensions PD Vpp No pin key Pin to pin spacing 0 100 in X Y TDO GND Pin width 0 025 in square post TCK_RET GND Pin length 0 235 in nominal TCK GND EMUO EMU1 In Table D 1 change the voltage for pin 5 the PD pin from 5V to Vpp Table D 1 XDS510 Header Signal Description Target Pin Signal State State Description 5 PD O Presence detect Indicates that the emulation cable is connected and that the target is powered up PD should be tied to Vpp in the target system 16 Page Change or Add D 5 In Figure D 2 change the voltages from 5V to Vpp Figure D 2 Emulator Cable Pod Interface i el SY Q JP1 74F175 TDO Pin 7 i D Q TMS Pin 1 TDI Pin 3 GND Pins 4 6 8 10 12 vias TCK Pin 11 EMUO Pin 13 TRST Pin 2 EMU1 Pin 14 TCK_RET Pin 9 PD Pin 5 NOTE All devices are 74AS unless otherwise specified 17 Page Change or Add D 7 In Figure D 4 change the voltages from 5V to Vpp Figure D 4 Target System Generated Test Clock Greater than 6 inche
4. NTT X2 CLKIN 108 BR 106 EMUO INT2 XF 124 CLKMD1 84 EMU1 OFF CLKMD2 115 FSR 13 Page Change or Add A 10 In Figure A 5 correct the signal names for pins 1 16 28 45 57 71 and 78 141 change the signal name on pin 122 to X2 CLKIN Figure A 5 Pin Signal Assignments for the C57S in 144 Pin TQFP E a Zo Q 3 5 S Q 5S co oO aac 4 xX RnpoxwS G5O Q Of 2 Je ADD OOOO SE OS Kee Oo Gee PES oe ede eeShee gage gt gt gt ZOXI QMAIMIKLIOI gt gt FZ Z gt XxXXOZ MIZ vV amp AOAI gt gt O HINT EMUO NC EMU1 OFF Vssc Vssc TOUT PGE package BCLKX CLKX Top view VDDC BFSR BCLKR RS READY HOLD NC BIO VDDC VDDC IAQ TRST VssI YSSl MP MC D15 D14 o NOAR WD HCNTLO TCK 54 BDR FSR CLKR VDDA VDDA HAS Note NC These pins are not connected reserved 14 Page Change or Add A 11 In Table A 5 correct the signal names for pins 1 16 28 45 57 71 and 78 141 change the signal name on pin 122 to X2 CLKIN reorder the signal names Table A 5 Signal Pin Assignments for the C57S in 144 Pin TQFP Sana Pin sora Pin sora Pin Sanat Pm Sanat AO 75 Vssp 37 A1 76 Vssp 38 A2 77 Vssp 55 A3 79 Vssp 56 A4 80 Vss 22 A5 81 Vss 23 A6 82 Vss 127 A7 84 Vss 128 A8 85 WE 108 AQ 86 X1 123 A10 95 X2 CLKIN 122 A11 96 XF 139 A12 98 t 3 A13 99 t 16 A14 100 f 28 A15 102 t 33 BCLKR 12 i 41 BCLKX 8 t 45 BDR 66 t 57 BDX 137 t 72 BFSR 11 EMUO t 78 BFSX 1
5. SPRZ113A Manual Update Sheet DATE June 1 1998 Document Being Updated TMS320C5x User s Guide Literature Number Being Updated SPRU056C Manual Included in a Kit Yes This Manual Update Sheet SPRZ113A ships with the TMS320C5x User s Guide Updates within paragraphs appear in a bold typeface Page Change or Add 3 3 In the bottom half of Figure 3 1 the auxiliary register file MUX output now connects with the trailing wire bus found on the data bus Figure 3 1 Block Diagram of C5x DSP Central Processing Unit CPU DATA BUS 7LSB from IREG 3 t ici STO ARP STO DP Serial mux J DBM Bort ars E E oT TREGO Mux J Timer CBCR 8 MULTIPLIER PRESCALER CBSR1 SFL 0 16 PREG 32 t e a CBSR2 ka 32 Host Port CBER1 S Ss Interface P SCALER NUL lt a 8 0 1 4 ves 32 32 1 0 Ports ARCR PRESCALER SFR 0 16 PAO E MUX y Emulation ARAU vux ie PA15 2 ua 32 Data Program Lux Y Sme q s2 SARAM Data Program Data DARAM DARAM ACCH ACCL ACCB 32 2 BO B2 32 5 O E POSTSCALER f vux 0 7 gt gt Notes All registers and data lines are 16 bits wide unless otherwise specified DATABUS t Not available on all devices Page Change or Add 4 11 In Table 4 5 change the reset values for the ARP bit and the OVM bit so both have a reset value of X In other words there is no reset value for the ARP bit and
6. ange from 0040h to 8000h 8 11 In Table 8 6 change the values in the Off Chip column for the first and fifth rows Table 8 6 C57S Program Memory Configuration on SARAM DARAM BO CNF RAM MP MC 2K words 6K words 512 words Off Chip 0 0 0 0000 07FF Off chip Off chip 8000 FFFF 1 0 0 0000 07FF Off chip FE00 FFFF 8000 FDFF 8 32 Change the last sentence in the fourth bullet J 32K words of global data memory are enabled initially in data spaces 8000h to FFFFh After the code transfer is complete the global memory is disabled before control is transferred to the destination address in pro gram memory 9 10 In Table 9 4 change the sentences after Soft 0 and Soft 1 Also add a sentence to the TSS register Table 9 4 Timer Control Register TCR Bit Summary Reset Bit Name value Function 11 Soft 0 This bit is used in conjunction with the Free bit to determine the state of the timer when a halt is encountered When the Free bit is cleared the Soft bit selects the emulation mode Soft 0 The timer stops immediately Soft 1 The timer stops after decrementing to zero 4 TSS 0 Timer stop status bit This bit stops or starts the on chip timer At reset the TSS bit is cleared and the timer immediately starts timing Note that due to timer logic implementation two successive writes of one to the TSS bit are required to properly stop the timer 9 11 Delete the last sentence in the Notes section and replace it with the senten
7. base address of the ABU memory may not be the same in all cases The 2K word block of BSP memory is located at 800h FFFh in data memory or at 8000h 87FFh in program memory as specified by the RAM and OVLY conirol bits 10 Page A 4 Figure A 2 Pin Signal Assignments for the C51 TQFP EMUO EMU1 OFF Vssc TOUT READY HOLD BIO TRST Vssl Vssi MP MC D15 D14 D13 D12 D11 D10 D9 D8 VDDD Change or Add Note VDDC VDDI VDDI CLKOUT1 CLKMD2 Vssl VDDC VssI TDO X1 In Figure A 2 change the signal name on pin 80 to R W X2 CLKIN 100 99 26 27 28 29 30 31 32 33 34 35 36 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PZ package Top view 37 38 39 40 41 44 45 46 47 48 49 50 VSSD VSSD D7 D6 D5 D4 D3 D2 D1 DO TMS VDDD Q Bo Fs CK VSSD INTI a zZ INT3 C52 C53S and LC56 in 100 Pin WE RD VDDA A15 A14 A13 A12 A11 A10 CLKMD1 VSSA VSSA TD VDDI A9 A8 A7 A6 A5 A4 A3 A2 A1 AO VSSA These pins are reserved for specific devices see Table A 6 on page A 12 11 Page Change or Add A 6 In Figure A 3 change the signal name on pin 108 to X2 CLKIN Figure A 3 Pin Signal Assignments for the LC57 in 128 Pin TQFP E a Zo Q 3 5 x lt S Q xS co QOQ AQQ x Q HDROA 8 or NDAD aaau pA Sta sana ssoaorg aes yp BIG gt gt gt 0XToOO TomrTerorsrsxXxxX OmrwMenelarss
8. ce indicated The current value in the timer can be read by reading the TIM the PSC can be read by reading the TCR Because it takes two instructions to read both registers there may be a change between the two reads as the counter decrements Therefore when making precise timing measurements it may be more ac curate to stop the timer to read these two values Due to timer logic implementation two instruc tions are also required to properly stop the timer therefore two successive writes of one to the TSS bit should be made when the timer must be stopped Page Change or Add 9 62 Change the XINT and RINT labels found in the lower right portion of Figure 9 35 Figure 9 35 ABU Block Diagram BCLKX lt gt _ BFSX 4 gt _ SPCE WXINT gt Serial Port Interrupt oe Control Logic Control g BRSR WRINT gt BDRR BSPC BDX BDR BCLKR BFSR gt Serial Port Interface Module Page Change or Add 9 63 Change the last sentence in the first paragraph The internal C5X memory used for autobuffering consists of a 2K word block of single access memory that can be configured as data program or both as with other single access memory blocks This memory can also be used by the CPU as general purpose storage however this is the only memory block in which autobuffering can occur Since the BSP is implemented on several dif ferent TMS320 devices the actual
9. ents of the accumulator low byte ACCL are loaded into the PC Execution continues at this address The CALAD instruction is used to perform computed subroutine calls CALAD is a branch and call instruction see Table 6 8 6 87 Change the description for the CALLD instruction Description The current program counter PC is incremented by 4 and pushed onto the top of the stack TOS Then the one 2 word instruction or two 1 word instructions following the CALLD instruction are fetched from program memory and executed before the call is executed The program memory address pma is loaded into the PC Execution contin ues at this address The current auxiliary register AR and auxiliary register pointer ARP are modified as specified The pma can be either a symbolic or numeric address CALLD is a branch and call instruction see Table 6 8 Page Change or Add 6 91 Change the description for the CCD instruction Description If the specified conditions are met the current program counter PC is incremented by 4 and pushed onto the top of the stack TOS Then the one 2 word instruction or two 1 word instructions following the CCD instruction are fetched from program memory and executed before the call is executed Then the program memory address pma is loaded into the PC Execution continues at this address The pma can be either a symbolic or numeric ad dress Not all combinations of the conditions are meaningful I
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11. ge or Add 5 22 In Example 5 13 add two new lines at the beginning of the example Example 5 13 Circular Addressing mar ldp splk splk splk Lar Lacc tar Lacc Lar Lacc tar Lacc Lar Lacc Lar Lacc Lar adrk Lae adrk ar6 0 200h CBSR1 203h 0Eh ar6 ar6 ar6 RL ar6 wL ar6 ae ar6 E ae ar6 2 ar6 2 CBI CBC 200 203 200 203 200 203 202 ER1 R nN 203 Circular buffer start register Circular buffer end register Enable AR6 pointing to buffer 1 Case 1 AR6 200h ase 2 R6 203h ase 3 R6 201h ase 4 R6 200h ase 5 R6 1FFh oD ase R6 200h ase 7 R6 204h ase 8 R6 200h PA PA PA PA PA PA FA Page Change or Add 6 32 Change the second operand for the ADD instruction Operands O lt shift lt 16 defaults to 0 6 44 Change the fourth operand for the AND instruction Operands 0 lt shift lt 16 6 83 Change the operand for the BSAR instruction Operands 1 lt shift lt 16 6 85 Change the description for the CALAD instruction Description The current program counter PC is incremented by 3 and pushed onto the top of the stack TOS Then the one 2 word instruction or two 1 word instructions following the CALAD instruction are fetched from program memory and executed before the call is executed Then the cont
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13. he DP bits are concatenated with the 7 LSBs of an instruction word to form a direct memory address of 16 bits The DP bits can be modified by the LST 0 or LDP instruction Page Change or Add 4 13 In Table 4 6 change the reset value for the ARB bit and the TC bit so they have no reset value Table 4 6 Status Register 1 ST1 Bit Summary Reset Bit Name value Function 15 13 ARB X Auxiliary register buffer This 3 bit field holds the previous value contained in the auxiliary register pointer ARP in STO Whenever the ARP is loaded the previous ARP value is copied to the ARB except when using the LST 0 instruction When the ARB is loaded using the LST 1 instruction the same value is also copied to the ARP This is useful when restoring context when not using the automatic con text save in a subroutine that modifies the current ARP 11 TC X Test control flag bit This 1 bit flag stores the results of the arithmetic logic unit ALU or parallel logic unit PLU test bit operations The TC bit is affected by the APL BIT BITT CMPR CPL NORM OPL and XPL instructions The status of the TC bit de termines if the conditional branch call and return instructions execute The TC bit can be modified by the LST 1 instruction Page Change or Add 5 2 In Figure 5 1 change the page 0 length to 128 WORD PAGE Figure 5 1 Direct Addressing STO 16 bit data memory address eee y DAB DARAM B2 Page Chan
14. n addition the NTC TC and BIO conditions are mutually exclusive If the specified conditions are not met control is passed to the next instruction The CCD functions in the same manner as the CALLD instruction page 6 87 if all conditions are true CCD is a branch and call instruction see Table 6 8 6 103 Change the opcode for the CRLT instruction to reflect the new values for bits 2 1 and 0 Opcode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 1 1 1 1 0 0 0 0 1 1 1 0 0 6 115 Change the third operand for the LACC instruction Operands O lt shift lt 16 defaults to 0 6 127 Change the table Cycles for a Single Instruction short immediate addressing Cycles for a Single Instruction short immediate addressing Operand ROM DARAM SARAM External Memory 2 2 2 2 Pcode 6 129 Change the table Cycles for a Single Instruction short immediate addressing Cycles for a Single Instruction short immediate addressing Operand ROM DARAM SARAM External Memory _ 2 2 2 2 Pcode 6 188 Change the fourth operand for the OR instruction Operands O lt shift lt 16 6 261 Change the second operand for the SUB instruction Operands 0 lt shift lt 16 defaults to 0 6 278 Change the data memory address in Example 1 from 1905h to 1005h 6 282 Change the fourth operand for the XOR instruction Operands 0 lt shift lt 16 Page Change or Add 8 6 In Figure 8 6 change the word Off chip to Reserved on the Program memory map for the r
15. s gt VDD Emulator header EMUO e EMU1 TRST lt q TMS lt gt TDO NC TCK gt TCK_RET System test clock D 8 In Figure D 5 change the voltages from 5V to Vpp Figure D 5 Multiprocessor Connections Emulator header EMUO PD EMU1 TRST TMS TDI TDO TCK TCK_RET 18 VDD GND Page Change or Add D 9 In Figure D 6 change the voltages from 5V to Vpp Figure D 6 Emulator Connections Without Signal Buffering lt gare _ VDD Emulator header EMUO EMU1 TRST TMS TDI TDO i TCK TCK_RET D 10 In Figure D 7 change the voltages from 5V to Vpp Figure D 7 Buffered Signals l Greater than 6 inches VDD Emulator Header EMUO PD EMU1 TRST TMS TDI lt q gt TDO gt TCK TCK_RET 19 VDD GND GND IMPORTANT NOTICE Texas Instruments and its subsidiaries Tl reserve the right to make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement including those p
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