Nios II Custom Instruction User Guide
Contents
1. ri V How to Find Information i e alinea ana v How to Contact Altera Typographic Conventions M 1 vii Chapter 1 Nios II Custom Instruction Overview Introduction iscrisse eher m EEUU Hen seb aa Kaavaa ER aD EE FIRE REB ree LECHE REEL TS 1 1 Custom Instruction Overview sees eee eee n ea e tns ttes tese th sets ets eee 1 2 Implementing Custom Instruction Hardware sus 1 3 Implementing Custom Instruction Software Custom Instruction Architectural Types urina Combinatorial Custom Instruction Architecture ens n e n na asa aseeen 1 5 Combinatorial Port Operation ss 1 5 Multi Cycle Custom Instruction Architecture sn 1 6 Multi Cycle Port Operation Extended Custom Instruction Architecture iii Extended Custom Instruction Port Operation ss Internal Register File Custom Instruction Architecture Internal Register File Custom Instruction Port Operation External Interface Custom Instruction iii Chapter 2 Software Interface Tritt O AUCH ONY scettr tet ebrio cha EE ter tee ariana PCIE Eee ELE Chapter Overview cess irteeraren EI ET EP iei idees eredi e iva Bit Swap Custom Instruction Example A Bit Swap Custom Instruction Example B Built in Functions amp User Defined Macros Custom Instruction Assembly Software Interface sss 2 4 Chapter 3 Implementing a Nios II Processor Custom Instr2. Library Name Clock Cycles N Port Opcode Extension Bit Swap leading zero detector Combinatorial 1 cycle 00000000 0 Endian Converter gt gt For this tutorial to work correctly the custom instruction s top level module name must be leading zero detector Altera Corporation 3 9 December 2004 Nios II Custom Instruction User Guide Implementing Custom Instruction Hardware in SOPC Builder 3 10 The Clock Cycles field shows that the instruction is a combinatorial logic custom instruction If the tutorial custom instruction was a fixed length multi cycle custom instruction instead you can edit this field to specify the number of clocks In the case of a variable length multi cycle custom instruction the Clock Cycles field displays Variable The N port field displays a indicating that the leading zero detector design is not an extended custom instruction In the case of an extended custom instruction this field shows the width of the N port The op code extension displays 00000000 0 that indicates the encoding of the N field in the instruction word 10 Click Finish to add the leading zeros detector custom instruction to the system and return to the SOPC Builder window Generate the SOPC Builder System amp Compile in Quartus Il Software Now that the custom instruction logic has been added to the system you are now ready for system generation and Quartus II compilation During s
3. builtin custom fnif fnip int fnfi fnff fnfp fnpi int fnpf int fnpp int int n int n int n int n floatdataa floatdataa floatdataa void datab void dataa void dataa void dataa void datab floatdatab void datab intdatab floatdatab intdatab floatdatab builtin custom pn int n builtin custom pni int n intdataa builtin custom pnf int n floatdataa builtin custom pnp int n void dataa builtin custom pnii int n intdatab builtin custom pnif int n floatdatab builtin custom pnip int n void datab builtin custom pnfi int n floatdataa intdatab builtin custom pnff int n floatdataa floatdatab builtin custom pnfp int n floatdataa void datab builtin custom pnpi int n void dataa intdatab builtin custom pnpf int n void dataa floatdatab builtin custom pnpp int n void dataa void datab Nios II Custom Instruction User Guide Altera Corporation December 2004 Appendix C Porting First AND E RYA w Generation Nios Custom Instructions to Nios Il Systems Hardware amp Software Porting Considerations Altera Corporation December 2004 Most first generation Nios custom instructions will port over to a Nios II system with minimal changes This section clarifies hardware and software considerations when porting first generation Nios custom instructions to your Nios II system
4. define UDEF MACRO2 B builtin custom fnp UDEF MACRO2 N B La 8 int main void 9 10 float a 1 789 11 float b 0 0 12 float pt a 13 14 UDEF MACROI a 15 b UDEF MACRO2 void pt a 16 return O TIY amp a On lines 2 through 6 the user defined macros are declared and mapped to the appropriate built in functions The macro UDEF_MACRO1 takes a float as an input parameter and does not return anything The macro UDEF MACRO takes a pointer as an input parameter and returns a float Lines 14 and 15 show the use of the two user defined macros 2 3 Nios II Custom Instruction User Guide Chapter Overview Custom Instruction Assembly Software Interface The Nios II processor custom instructions are also accessible in assembly code This section describes the assembly interface Custom instructions are R type instructions with a 6 bit op code three 5 bit register index fields and an 11 bit op code extension field The 11 bit op code extension field is broken into an 8 bit N field for the extended custom instruction and 3 bits for the readra readrb and writerc bits Figure 2 1 is a diagram of the op code for custom instructions excerpted from the Instruction Set Reference chapter in the Nios II Processor Reference Handbook Figure 2 1 Op Code for Custom Instructions Diagram 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 NF uP OP
5. pof file Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters Examples Delete key the Options menu Subheading Title References to sections within a document and titles of on line help topics are shown in quotation marks Example Typographic Conventions Courier type Signal and port names are shown in lowercase Courier type Examples data1 tdi input Active low signals are denoted by suffix n e g resetn Anything that must be typed exactly as it appears is shown in Courier type For example c qdesigns tutorial chiptrip gdf Also sections of an actual file such as a Report File references to parts of files e g the AHDL keyword SUBDESIGN as well as logic function names e g TRI are shown in Courier Numbered steps are used in a list of items when the sequence of the items is important such as the steps listed in a procedure Bullets are used in a list of items when the sequence ofthe items is not important The checkmark indicates a procedure that consists of one step only The hand points to information that requires special attention The caution indicates required information that needs special consideration and understanding and should be read prior to starting or continuing with the procedure or process CAUTION A The warning indicates information that should be read prior to starting or continuing the procedure or processes e The ang
6. required for variable muli cycle signal dataa IN STD LOGIC VECTOR 31 DOWNTO 0 operand A always required signal datab IN STD LOGIC VECTOR 31 DOWNTO 0 operand B optional signal n IN STD LOGIC VECTOR 7 DOWNTO 0 N field selector required for extended signal a IN STD LOGIC VECTOR 4 DOWNTO 0 operand A selector used for Internal register file access signal b IN STD LOGIC VECTOR 4 DOWNTO 0 operand B selector used for Internal register file access signal c IN STD LOGIC result destination selector used for Internal register file access signal readra IN STD LOGIC register file index used for Internal register file access gt signal readrb IN STD LOGIC register file index used for Internal register file access gt signal writerc IN STD LOGIC register file index used for Internal register file access gt signal result OUT STD LOGIC VECTOR 31 DOWNTO 0 result always required i END _ entity name ARCHITECTURE a OF entity name IS signal clk IN STD LOGIC signal reset IN STD LOGIC signal clk en IN STD LOGIC signal start IN STD LOGIC signal readra IN STD LOGIC signal readrb IN STD LOGIC signal writerc IN STD LOGIC signal n IN STD LOGIC VECTOR 7 DOWNTO 0 signal a IN STD LOGIC VECTOR 4 DOWNTO 0 signal b IN STD LOGIC VECTOR 4 DOWNTO 0 signal c IN STD LOGIC VECTOR 4 DOWNTO 0 Signal dataa IN STD LOGIC VECTOR 31 DOWNTO 0
7. 31 0 port Extended custom instructions can be either combinatorial or multi cycle custom instructions To implement an extended custom instruction simply add ann 7 0 port to the interface for your custom instruction logic The bit width of then 7 0 portis a function of a number of operations the extended custom instruction can perform Extended Custom Instruction Port Operation Then 7 0 port behaves similarly to the dataa 31 0 port The CPU presents then 7 0 portfor execution on the rising edge of clock when start is asserted and the n 7 0 port remains stable throughout the execution of the custom instruction Each custom instruction s bit width of then 7 0 portis a function of the number of unique operations the custom logic block is able to perform All other custom instruction port operations remain the same Internal Register File Custom Instruction Architecture The Nios II processor allows custom instruction logic to access its own internal register file for I O which provides you the flexibility to specify if operands should be read from the Nios II processor s register file or the custom instructions internal register file In addition results from operations can be written to the local register file rather than the Nios II processor s register file Internal registers accessing custom instructions use readra readrb and writerc to determine if I O should take place between the Nios II register file o
8. Code Castor readra readrb writerc Instruction Fields A Register index of operand A B Register index of operand B C Register index of operand C N 8 bit number that selects instruction readra 1 if instruction uses rA 0 otherwise readrb 1 if instruction uses rB 0 otherwise writerc 1 if instruction provides result for rC 0 otherwise The assembler syntax for the custom instruction is custom N xC xA xB Where N is the custom instruction op code number xC is the destination register for the result 31 0 port xAis operand1 and xB is operand2 To access the Nios II CPU s register file replace x with r To access a custom register file replace x with c The following shows the syntax for two examples of custom instruction assembler calls Example 1 custom 0 r6 r7 r8 Example 2 custom 3 cl r2 c4 2 4 Altera Corporation Nios II Custom Instruction User Guide December 2004 Software Interface Altera Corporation December 2004 Example 1 executes a custom instruction with an op code number of 0 The contents of the Nios II processor register r7 and r8 are used as input with the results stored in the Nios II processor register r6 Example 2 executes a custom instruction with an op code number of 3 The contents of the Nios II processor register r2 and custom register c4 are used as inputs The results are stored in the custom register c1 2 5 Nios II Custom Instruction User Guide Ch
9. Corporation N DTE JA About this User Guide This user guide provides comprehensive information about Altera Nios II custom instructions Table 1 1 shows the user guide revision history December Table 1 1 Tutorial Revision History December 2004 Updates for the Nios Il version 1 1 release September 2004 Updates for the Nios Il version 1 01 release May 2004 First release of custom instruction user guide for the Nios II processor How to Find m The Adobe Acrobat Find feature allows you to search the contents of a PDF file Click the binoculars toolbar icon to open the Find dialog Information box W Bookmarks serve as an additional table of contents m Thumbnail icons which provide miniature previews of each page provide a link to the pages m Numerous links shown in green text allow you to jump to related information Altera Corporation v How to Find Information Nios Il Custom Instruction User Guide How to Contact Altera For the most up to date information about Altera products go to the Altera world wide web site at www altera com For technical support on this product go to www altera com mysupport For additional information about Altera products consult the sources shown below Information Type Technical support Product literature USA amp Canada www altera com mysupport All Other Locations altera com mysupport 800 800 EPLD 3753 7 00 a m to 5 00
10. Hardware Porting Considerations Both combinatorial and multi cycle first generation Nios custom instructions will work with a Nios II system without any changes However because parameterized first generation Nios custom instructions allow a prefix to be passed to the custom instruction logic block parameterized first generation Nios custom instructions require a design change There is no strict definition for the use of prefixes in first generation Nios systems but in most cases the prefix controls the operation performed by the custom instruction However in a Nios II system the prefix option is supported directly by extended custom instructions Therefore any parameterized first generation Nios custom instruction that uses a prefix to control the operation executed by the custom instruction should be ported to a Nios II extended custom instruction Refer to Extended Custom Instruction Architecture on page 1 9 Any other use of the prefix may be accomplished with one of the Nios II custom instruction architecture types Refer to Custom Instruction Architectural Types on page 1 4 Software Porting Considerations All first generation Nios custom instructions will require a small change to application software Assuming no hardware changes i e not a parameterized first generation custom instruction software porting should be nothing more than a search and replace operation The first generation Nios and Nios II system mac
11. Signal datab IN STD LOGIC VECTOR 31 DOWNTO 0 signal result OUT STD LOGIC VECTOR 31 DOWNTO 0 signal done OUT STD LOGIC BEGIN Altera Corporation A 1 December 2004 Process Statement Concurrent Procedure Call Concurrent Signal Assignment Conditional Signal Assignment Selected Signal Assignment Component Instantiation Statement Generate Statement END a Verilog HDL Template Sample Verilog HDL template file Verilog Custom Instruction Template module __module name clk reset clk_en start done dataa datab readra readrb writerc result input clk CPU s master input clk lt required for multi cycle gt CPU s master asynchronous reset lt required for multi cycle gt Clock qualifier lt required for multi cycle gt True when this instr issues lt required for multi cycle gt True when instr completes lt required for variable muli cycle gt operand A lt always required gt operand B lt optional gt N field selector lt required for extended gt operand A selector lt used for Internal register file access gt operand b selector lt used for Internal register file access gt result destination selector lt used for Internal register file access gt register file index lt used for Internal register file access gt register file index lt used for Internal register file access gt register file index lt used f
12. Tri State Bridge amp Move Up W Move Down Done checking for updates Generate Altera Corporation December 2004 2 Choose Edit Module menu The Nios II Processor Configuration wizard appears 3 Click on the Custom Instructions tab 3 7 Nios II Custom Instruction User Guide Implementing Custom Instruction Hardware in SOPC Builder 4 Click Import The Interface to User Logic wizard appears See Figure 3 5 Figure 3 5 Interface to User Logic Wizard AN Interface to User Logic custominstruction cpu 0 Ports Publish ie Design Files F Add v Delete Top module leading zero detector Port Information Port Name Direction dataa input resuit 32 output Read port list from files JV Simulate custom instruction logic with system Cancel Next Addto System The Interface to User Logic wizard is used to import Nios II custom instruction logic To import custom instruction logic into the system you must m Add HDL source files to the list m Specify the top level module m Readin the port list Nios II custom instructions require specific port names see Custom Instruction Architectural Types on page 1 4 of Chapter 1 Any port name not matching the expected port names will be listed as a type export i e export is a type assigned to a signal that is not an expected cust
13. datab Built in Functions Returning int int builtin custom in int n int builtin custom ini int n intdataa int builtin custom inf int n floatdataa int builtin custom inp int n void dataa int builtin custom inii int n intdataa intdatab int builtin custom inif int n intdataa floatdatab int builtin custom inip int n intdataa void datab int builtin custom infi int n floatdataa intdatab int builtin custom inff int n floatdataa floatdatab int builtin custom infp int n floatdataa void datab int builtin custom inpi int n void dataa intdatab int builtin custom inpf int n void dataa floatdatab int builtin custom inpp int n void dataa void datab Built in Functions Returning float float builtin custom fn int n float builtin custom fni int n intdataa float builtin custom fnf int n floatdataa float builtin custom fnp int n void dataa float builtin custom fnii int n intdataa intdatab Built In Functions B 2 float float float float float float float float Built in Functions Returning a Pointer void void void void void void void void void void void void void E 0X HF builtin custom builtin custom builtin custom builtin custom builtin custom builtin custom builtin custom
14. 1 0 and datab 31 0 ports as inputs and drives the results on the result 31 0 port Because the logic is able to complete in a single clock cycle control signals are not needed Table 1 2 lists the combinatorial custom instruction signals Table 1 2 Combinatorial Custom Instruction Signals Signal Name Direction Required Purpose dataa 31 0 Input No Input Operand to custom instruction datab 31 0 Input No Input Operand to custom instruction result 31 0 Output Yes Result from custom instruction The only required port for combinatorial custom instructions is the result 31 0 port The dataa 31 0 and datab 31 0 signals are optional and should only be included if the application requires input operands If only a single data port is needed use dataa 31 0 Combinatorial Port Operation This section describes the combinatorial custom instruction hardware interface port operation Figure 1 4 shows the combinatorial custom instruction hardware interface timing diagram 1 5 Nios II Custom Instruction User Guide Custom Instruction Architectural Types In Figure 1 4 the CPU presents the dataa 31 0 anddatab 31 0 ports on the rising edge of the CPU clock The CPU reads the result 31 0 port on the following rising edge of the CPU clock The Nios II processor issues combinatorial custom instructions speculatively and therefore combinatorial custom instructions cannot have an e
15. 8600034 Random Case Software Number of clocks 22419 The number mills seconds 0 4483799934 Hardware Number of clocks 8056 The number mills seconds 0 1611199975 Best Case Software Number of clocks 12402 The number mills seconds 0 2480400205 Hardware Number of clocks 8032 The number mills seconds 0 1606400013 KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK 3 11 Nios Il Custom Instruction User Guide Accessing the Custom Instruction from Software 3 12 Altera Corporation Nios II Custom Instruction User Guide December 2004 Appendix A Custom lt Instruction Templates VH DL amp Ve ri log This section provides VHDL and Verilog HDL custom instruction templates that you can reference when writing custom instructions in H DL Te m pl ates VHDL and Verilog HDL You can download the template files from the Altera world wide website at www altera com nios VHDL Template Sample VHDL template file LIBRARY library name USE library name package name ALL ENTITY entity name IS PORT signal clk IN STD LOGIC CPU s master input clk required for multi cycle gt signal reset IN STD LOGIC CPU s master asynchronous reset required for multi cycle gt signal clk en IN STD LOGIC Clock qualifier required for multi cycle gt signal start IN STD LOGIC True when this instr issues required for multi cycle gt signal done OUT STD LOGIC True when instr completes
16. Nios II Nios Il Custom Instruction User Guide A DTE RYAN 101 Innovation Drive San Jose CA 95134 408 544 7000 http www altera com Copyright 2004 Altera Corporation All rights reserved Altera The Programmable Solutions Company the stylized Altera logo specific device des ignations and all other words and logos that are identified as trademarks and or service marks are unless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other countries All other product or service names are the property of their respective holders Al tera products are protected under numerous U S and foreign patents and pending applications maskwork rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the ap plication or use of any information product or service described herein except as expressly agreed to in writing by Altera NSAI Corporation Altera customers are advised to obtain the latest version of device specifications before relying on any published in formation and before placing orders for products or services DI Printed on recycled paper UG N2CSTNST 1 2 LS EN ISO 9001 ii Altera Corporation N E Ja Contents About this User Guide
17. age 1 10 or External Interface Custom Instruction on page 1 12 Altera Corporation Nios II Custom Instruction User Guide December 2004 Nios II Custom Instruction Overview Figure 1 6 Multi Cycle Custom Instruction Timing Diagram TO T1 T2 T3 T4 T5 T6 clk clk_en start reset dataal da done result Extended Custom Instruction Architecture Extended custom instruction architecture allows for a single custom logic block to output results for different operations Extended custom instructions make use of the N field to specify which logic operation is performed by the custom logic The 8 bit wide N field in the op code allows for 256 different operations for a single block of custom logic Figure 1 7 is a block diagram of an extended custom instruction with bit swap byte swap and half word swap operations Figure 1 7 Extended Custom Instruction with Swap Operations dataa 31 0 bit swap operation byte swap operation result 31 0 half word swap operation n 7 0 Altera Corporation 1 9 December 2004 Nios II Custom Instruction User Guide Custom Instruction Architectural Types The Figure 1 7 swap operations are performed on data coming in via the dataa 31 0 port The n 7 0 portis used as a select signal on an output multiplexer to select which operation is presented to the result
18. al register file indexed by a 4 0 readrb Input No If readrb is high dataa 31 0 and datab 31 0 are supplied by the Nios II CPU If readrb is low custom instruction logic should read the internal register file indexed by a 4 0 writerc Input No Signal s custom instructions to write result of c 4 0 to custom instruction internal register file a 4 0 Input No Custom instruction internal register file index b 4 0 Input No Custom instruction internal register file index c 4 0 Input No Custom instruction internal register file index 1 11 Nios II Custom Instruction User Guide Custom Instruction Architectural Types Internal Register File Custom Instruction Port Operation The readra readrb writerc anda 4 0 b 4 0 andc 4 0 ports behave similarly to dataa 31 0 When the start signal is asserted the CPU presents the readra readrb writerc a 4 0 b 4 0 and c 4 0 signals on the rising edge of the CPU clock All the ports remain stable throughout the execution of the custom instructions To determine how to handle register file I O custom instruction logic should read the active high readra readrb and writerc signals The a 4 0 b 4 0 and c 4 0 ports should be used as register file indexes When readra or readrb are not asserted the custom instruction logic should ignore the corresponding a 4 0 or b 4 0 port When writec is not asserted the CPU ignores the value driven on the res
19. apter Overview 2 6 Altera Corporation Nios II Custom Instruction User Guide December 2004 3 Implementing a Nios Il ANU 8 RYA Processor Custom Instruction Introduction Hardware amp Software Reguirements Tutorial Files Altera Corporation December 2004 This chapter walks you through the process of implementing a Nios II processor custom instruction and illustrates the enormous time savings that are possible with Nios II custom instructions The instructions in this chapter reguire the following hardware and software m Quartus II software version 4 1 SP1 or later m Nios II development kit m Nios development board Stratix II Stratix Stratix Professional or Cyclone Edition The tutorial design files are installed with the Nios II development kit The hardware design files are stored in the tutorials directory lt Nios II kit path gt tutorials Nios2_Custom_Instruction board version gt Each development board has its own tutorial design file directory see Table 3 1 The Quartus II project files are contained in the quartus_project directory and the hardware for the custom instruction is contained in the rtl directory Table 3 1 Design File Directories Nios Development Board Tutorial Directory Stratix Il Edition niosll stratixll 2560 es Stratix Edition niosll stratix 1810 amp niosll stratix 1s10 es Stratix Professional Edition niosll stratix 1s40 Cyclon
20. e Edition niosll cyclone 1c20 This tutorial uses the Nios II integrated development environment IDE software template design files located in the following directory lt Nios II kit path NexamplesNsoftwareNci tutorial IS The software files in this directory are copied to your working project directory in the Nios II IDE so there is no need to move the files 3 1 Design Example Leading Zeros Detector Design Example Leading Zeros Detector Running the Software Algorithm in Nios Il IDE 3 2 The leading zeros detector design is a simple application that is relevant to floating point math algorithms The number of leading zeros found in floating point operands is used during the normalization process before the floating point operation takes place This design example counts the number of leading zeros of an array of numbers Without Nios II custom instructions the software algorithm loops until it finds the first 1 which takes several iterations and multiple CPU clocks cycles However with Nios II custom instructions the same algorithm can complete in a single clock cycle using priority encoder custom logic block The following guides you through the steps required to run the leading zeros detector software algorithm while providing an opportunity to see the design s functionality and software algorithm s performance This section includes m Creating a new Nios IT IDE project m Building and downloading the
21. ementing Custom Instruction Hardware Figure 1 2 is a hardware block diagram of a Nios II processor custom instruction Figure 1 2 Hardware Block Diagram of a Nios Il Processor Custom Instruction Optional interface to external memory FIFO or other logic dataa 31 0 gt datab 31 0 Combinatorial gt result 31 0 ck p pes N Multi cycle m done start MEN n 7 0 9 Extended a 4 0 readra J b 4 0 Ji Internal readrb _ Register File C 4 0 mm writerc _ gt The basic operation of Nios II custom instruction logic is to receive input on the dataa 31 0 and or datab 31 0 and drive out the result on its result 31 0 port The designer generates the custom instruction logic that produces the results The Nios II processor supports different architectural types of custom instructions Figure 1 2 lists the additional signals that accommodate different architectural types Only the ports used for the specific custom instruction implementation are required Figure 1 2 also shows an optional interface to external logic The interface to external logic allows designers to include a custom interface to system resources outside of the Nios II processor data path Altera Corporation 1 3 December 2004 Nios II Custom Instruction User Guide Custom Instruction Architectural Types Custom Instruction Architectural Types Implementing Custom Instruct
22. ibrary refer to the Nios II Software Developer s Handbook Building amp Downloading the Software Application This section provides the steps to download the leading zeros software application to the Nios development board Before the application is executed you should examine the leading zeros ci c file B Thecontents of main should include three sets of test data i e best case worse case and random data sets that have the leading zeros counted and placed into another array m There are conditional compile statements based on the existence of theALT CI LEADING ZERO DETECTOR symbol This is the name of the macro that is defined when the leading zeros custom instruction is added to the system later in the tutorial 1 Choose Run As gt Nios II Hardware Run menu The build process begins Depending on the current hardware image on the Nios development board Nios II IDE might recognize that the current hardware image is not the image required for the tutorial design If this occurs the Nios II IDE displays an error message and launches the Quartus II Programmer see Figure 3 3 If the Quartus II Programmer does not launch skip to Step 8 3 4 Altera Corporation Nios II Custom Instruction User Guide December 2004 Implementing a Nios Il Processor Custom Instruction Figure 3 3 Quartus Il Programmer Window gt Quartus II Programmer Chain1 cdf File Edit Processing Help Hardware Setup USB Blas
23. ion Software The Nios II processor custom instruction software interface is simple and abstracts the details of the custom instruction from the programmer For each custom instruction the Nios II integrated development environment IDE produces a macro that is defined in the system header file You can call the macro from C or C application code as a normal function call and you do not need to program assembly to access custom instructions Custom instructions can also be accessed via the Nios II processor assembly code For more information refer to Chapter 2 Software Interface There are different custom instruction architectures available to suit the application s requirements The architectures range from a simple single cycle combinatorial architecture to an extended variable length multi cycle custom instruction architecture The chosen architecture determines what the hardware interface looks like Table 1 1 shows custom instruction architectural types application and the associated hardware interface Table 1 1 Custom Instruction Architectural Types Application amp Hardware Interface Architectural Type Application Hardware Interface Combinatorial Single clock cycle custom logic blocks dataa 31 result 31 0 0 datab 31 0 Multi cycle Extended Multi clock cycle custom logic block of fixed or variable durations Custom logic blocks that are capable of performing multiple operati
24. led arrow indicates you should press the Enter key The feet direct you to more information on a particular topic Altera Corporation vii How to Find Information Nios II Custom Instruction User Guide viii Altera Corporation 1 Nios Il Custom Instruction AND E RYA Overview Introduction Altera Corporation December 2004 With the Altera Nios II embedded processor system designers can accelerate time critical software algorithms by adding custom instructions to the Nios instruction set With custom instructions system designers can reduce a complex sequence of standard instructions to a single instruction implemented in hardware System designers can use this feature for a variety of applications e g to optimize software inner loops for digital signal processing DSP packet header processing and computation intensive applications The Nios II CPU configuration wizard which is accessed via the Quartus II software s SOPC Builder provides a graphical user interface GUI used to add up to 256 custom instructions to the Nios II processor The custom instruction logic connects directly to the Nios II arithmetic logic unit ALU as shown in Figure 1 1 Figure 1 1 Custom Instruction Logic Connects to the Nios II ALU Nios Il Embedded Processor Custom Logic Custom Instruction Overview Custom Instruction Overview 1 2 This chapter m Describes the Nio
25. m h 1 2 3e 4 int main void 5 6 int a 0x12345678 7 int a swap 0 8 9 a swap ALT CI BSWAP a 10 return 0 ir Chapter Overview 2 2 In this example the system h file is included on line 1 to locate the custom instruction macro definitions Two integers are declared one on line 6 and one on line 7 Integer a is passed as input to the bit swap custom instruction with the results loaded into a_swap on line 9 The bit swap Example B accommodates most applications using custom instructions The macros defined by the Nios II IDE only make use of c integer types Occasionally applications need to make use of input types other than integers and therefore need to pass expected return values other than integers gt gt The Nios II processor custom instructions allow you to define custom macros that allow for other 32 bit input types to interface with custom instructions Built in Functions amp User Defined Macros The Nios II processor uses gcc built in functions to map to custom instructions Using built in functions allows for types other than integers to be used with custom instructions There are 52 uniquely defined built in functions to accommodate the different combinations of the supported types Refer to Appendix B Custom Instruction Built In Functions for more information on custom instruction s built in functions Built in functions have the following format builtin_custo
26. m_ lt return type gt n lt parameter types gt Table 2 1 shows 32 bit input types supported by custom instructions as parameters and return types as well as the abbreviations used in the built in function definition Table 2 1 32 Bit Input Types Support by Custom Instructions Input Type Built In Function Abbreviation int i float f void p Altera Corporation Nios II Custom Instruction User Guide December 2004 Software Interface Altera Corporation December 2004 Example C shows the prototype definition for two built in functions Example C void builtin custom nf int n float dataa float builtin custom fnp int n void dataa In Example C the builtin custom nf function takes an int and a float as inputs and does not return a value Whereas the _builtin custom fnp function takes an integer and a pointer as an input and returns a float To support non integer input types you should define macros that map to the specific built in function required for the application Refer to Appendix B Custom Instruction Built In Functions for a list of built in functions Example D shows user defined custom instruction macros used in an application Example D 1 define void udef macrol float data 2 define UDEF MACRO1 N 0x00 3 define UDEF MACROI A builtin custom nf UDEF MACRO1 N A 4 define float udef macro2 void data 5 define UDEF MACRO2 N 0x01 6
27. nd remain valid throughout the duration of the custom instruction execution Fixed or variable length custom instruction port operation e Fixed length The CPU asserts start waits a specified number of clock cycles and then reads result 31 0 For an recycle operation the custom logic block must present valid data on the n 1 rising edge after the start signal is asserted e Variablelength The CPU waits until the active high done signal is asserted The CPU reads the result 31 0 port on the clock edge that done is asserted The custom logic block should present data on the result 31 0 port on the same clock that the done signal is asserted The Nios II system clock feeds the custom logic block s c1k signal and the Nios II master reset feeds the active high reset signal The reset signal is asserted only when the whole Nios II system is reset The custom logic block should use the active high clk_en signal as a conventional clock qualifier signal and should ignore all clock rising edges while c1k enis deasserted Any port in the custom logic block that is not recognized as a custom instruction signal is considered to be an external interface signal Multi cycle custom instructions can be further optimized utilizing the extended internal register file and external interface custom instructions Refer to Extended Custom Instruction Architecture on page 1 9 Internal Register File Custom Instruction Architecture on p
28. nstruction execution is complete Table 1 3 lists multi cycle custom instruction signals Table 1 3 Multi Cycle Custom Instruction Signals Signal Name Direction Required Application clk Input Yes System clock clk en Input Yes Clock enable reset Input Yes Synchronous reset start Input No Signals custom instruction logic to start execution done Output No Custom instruction logic signals the CPU that execution is complete dataa 31 0 Input No Input operand to custom instruction datab 31 0 Input No Input operand to custom instruction result 31 0 Output No Result from custom instruction Altera Corporation December 2004 1 7 Nios II Custom Instruction User Guide Custom Instruction Architectural Types As indicated in Table 1 3 the clk clk_en and reset signals are required for multi cycle custom instructions However the start done dataa 31 0 datab 31 0 and result 31 0 signals are optional and should only be used if required for the specific application Multi Cycle Port Operation The section provides operational details for the multi cycle custom instruction hardware interface Figure 1 6 shows the multi cycle custom instruction timing diagram 1 8 The CPU asserts the active high start port on the first clock cycle of execution when the custom instruction issues through the ALU At this time the dataa 31 0 and datab 31 0 signals have valid values a
29. om instruction name Exported signal types are considered to be a part of the custom instruction s external interface In addition to specifying custom instruction port information you have the option of specifying whether or not the custom instruction will be simulated with the system or if it will be black boxed Also custom instructions can be published for later re use in different projects 3 8 Altera Corporation Nios II Custom Instruction User Guide December 2004 Implementing a Nios II Processor Custom Instruction TA For more information refer to AN 333 Developing Peripherals for SOPC Builder 5 Click Add A Windows Explorer dialog box appears Browse up one directory and descend into the rtl directory 6 Choose the leading zero detector v file in the rtl directory 7 Click Open to select the leading zero detector v file and return back to the Interface to User Logic wizard 8 Click the Read port list from files button This will read the port information from the HDL files The Figure 3 5 example uses dataa 31 0 and result 31 0 ports 9 Click Add to System to complete the custom instruction importing process The Nios II Processor Configuration wizard appears Figure 3 6 shows that once the custom instruction is imported the top level module name is listed in the Name field Figure 3 6 Altera Nios Il cpu 0 Altera Nios Il cpu_0 Nios II Core JTAG Debug Module Custom Instructions
30. ons dataa 31 result 31 0 clk clk en tart reset done ataa 31 0 datab 31 0 0 datab 31 0 esult 31 0 clk clk en Internal Register File Custom logic blocks that access internal register file for input and or output c 4 0 ataa 31 esult 31 0 clk clk en tart reset done n 7 0 a 4 0 readra b 4 0 readrb 0 datab 31 0 S d rf Start reset done n 7 0 d rf S writerc External Interface Custom logic blocks that interface to logic outside of the NIOS II processor s data path Standard custom instruction signals plus user defined interface to external logic 1 4 This section discusses the basic functionality and hardware interface of each custom instruction architecture type listed in Table 1 1 Nios II Custom Instruction User Guide Altera Corporation December 2004 Nios II Custom Instruction Overview Altera Corporation December 2004 Combinatorial Custom Instruction Architecture Combinatorial custom instruction architecture consists of a logic block that is able to complete in a single clock cycle Figure 1 3 shows a block diagram of a combinatorial custom instruction architecture Figure 1 3 Combinatorial Custom Instruction Architecture dataa 31 0 Combinatorial result 31 0 datab 31 0 The Figure 1 3 combinatorial custom instruction diagram uses dataa 3
31. or Internal register file access gt result lt always required gt input reset input clk_en input start input readra input readrb input writerc input 7 0 input 4 0 input 4 0 input 4 0 n a b c input 31 0 dataa input 31 0 datab output 31 0 result output done Port Declaration Wire Declaration Integer Declaration Concurrent Assignment Always Construct endmodule A 2 Nios II Custom Instruction User Guide Altera Corporation December 2004 Appendix B Custom Instruction Built In Functions Built In Functions Altera Corporation December 2004 This section lists the following custom instruction built in functions Returning void Returning int Returning float Returning a pointer Built In Functions Returning Void void builtin custom n int n void builtin custom ni int n intdataa void builtin custom nf int n floatdataa void builtin custom np int n void dataa void builtin custom nii int n intdataa intdatab void builtin custom nif int n intdataa floatdatab void builtin custom nip int n intdataa void datab void builtin custom nfi int n floatdataa intdatab void builtin custom nff int n floatdataa floatdatab void builtin custom nfp int n floatdataa void datab void builtin custom npi int n void dataa intdatab void builtin custom npf int n void dataa floatdatab void builtin custom npp int n void dataa void
32. or s data bus 1 13 Nios II Custom Instruction User Guide Custom Instruction Architectural Types 1 14 Altera Corporation Nios II Custom Instruction User Guide December 2004 2 Software Interface Introduction Chapter Overview Altera Corporation December 2004 The Nios II processor custom instruction details are abstracted from the application code During the build process the Nios II integrated development environment IDE automatically generates macros that allow easy access from application code to custom instructions This chapter provides custom instruction software interface details including m Bit swap custom instruction examples W Built in functions amp user defined macros m Custom instruction assembly software interface Bit Swap Custom Instruction Example A Example A shows a portion of the system h header file that defines the macro for a bit swap custom instruction This bit swap example uses one 32 bit input and performs only one function define ALT CI BSWAP N 0x00 define ALT CI BSWAP A builtin custom ini ALT CI BSWAP N A In bit swap Example A ALT CI BSWAP Nis defined to be 0x0 which is the custom instruction s op code number The ALT CI BSWAP A macro is mapped to a gcc built in macro that takes a single argument Bit Swap Custom Instruction Example B The following bit swap example illustrates a bit swap custom instruction used in application code include syste
33. p m Pacific Time www altera com 408 544 7000 1 7 00 a m to 5 00 p m Pacific Time www altera com Altera literature services lit regOaltera com 1 lit regOaltera com 1 Non technical customer service 800 767 3753 408 544 7000 7 30 a m to 5 30 p m Pacific Time FTP site ftp altera com ftp altera com Note to table 1 Youcan also contact your local Altera sales office or sales representative vi Altera Corporation About this User Guide How to Find Information Typogra ph ic This document uses the typographic conventions shown below Conventions Visual Cue Meaning Bold Type with Initial Command names dialog box titles checkbox options and dialog box options are Capital Letters shown in bold initial capital letters Example Save As dialog box bold type External timing parameters directory names project names disk drive names filenames filename extensions and software utility names are shown in bold type Examples fmax qdesigns directory d drive chiptrip gdf file Italic Type with Initial Capital Document titles are shown in italic type with initial capital letters Example AN 75 Letters High Speed Board Design Italic type Internal timing parameters and variables are shown in italic type Examples tpa n 1 Variable names are enclosed in angle brackets gt and shown in italic type Example file name gt project name gt
34. r an internal register file Additionally signals a 4 0 b 4 0 and c 4 0 specify which internal registers to read from and or write to For example if readra is deasserted i e read from the internal register a 4 0 provides an index to the internal register file Figure 1 8 shows a simple multiply accumulate custom logic block 1 10 Altera Corporation Nios II Custom Instruction User Guide December 2004 Nios Il Custom Instruction Overview Figure 1 8 Multiply Accumulate Custom Logic Block dataa 31 0 _ __ gt datab 31 0 qQ readrb Multiply gt Accumulate result 31 0 When readrb is deasserted the multiplication of dataa 31 0 and datab 31 0 occurs and the results are stored in the accumulate register Those results can be read back by the Nios II processor or alternatively that value in the accumulator can be read as input to the multiplier by asserting readrb Table 1 4 lists the internal register file custom instructions signals The signals are optional and should only be used if required by the application Altera Corporation December 2004 Table 1 4 Internal Register File Custom Instruction Signals Signal Name Direction Required Application readra Input No If readra is high dataa 31 0 and datab 31 0 are supplied by the Nios II CPU If readra is low custom instruction logic should read the intern
35. ro definition nomenclature is different therefore first generation Nios macro calls should be replaced by the Nios II macros In the case of parameterized first generation custom instructions additional changes will be required depending on the implementation Refer to Chapter 2 Software Interface Hardware amp Software Porting Considerations C 2 Altera Corporation Nios II Custom Instruction User Guide December 2004
36. s II processor custom instruction feature W Discussesthe requirements for implementing a custom instruction in hardware amp software m Defines custom instruction architectural types For information regarding custom instructions software interface refer to Chapter 2 Software Interface A tutorial with design files and step by step instructions for implementing a custom instruction is found in Chapter 3 Implementing a Nios II Processor Custom Instruction With Nios II processor custom instructions system designers are able to take full advantage of the flexibility of FPGAs to meet system performance requirements Custom instructions allow system designers to add custom functionality to the Nios II processor ALU Nios II processor custom instructions are custom logic blocks adjacent to the ALU in the CPU s data path This gives system designers the ability to tailor the Nios II processor core to meet the needs of a particular application System designers have the ability to accelerate time critical software algorithms by converting them to custom hardware logic blocks Because it is easy to alter the design of the FPGA based Nios II processor custom instructions provide an easy way to experiment with hardware software trade offs during an embedded system s implementation phase rather than the specification phase Altera Corporation Nios II Custom Instruction User Guide December 2004 Nios II Custom Instruction Overview Impl
37. software application Creating a New Nios II IDE Project In this section you will create a new Nios II IDE project using a software template The example s design files are pre installed with the Nios II development kit To create a new Nios II IDE project perform the following steps 1 Choose Programs gt Altera gt Nios II Development Kit version number gt Nios II IDE Windows Start menu 2 Choose New gt C C Application File menu The first page of the New Project wizard appears See Figure 3 1 on page 3 3 3 From Select Project Template select Custom Instruction Tutorial 4 Leave the default selection for the project s name and ensure that Use Default Location is checked Altera Corporation Nios II Custom Instruction User Guide December 2004 Implementing a Nios II Processor Custom Instruction Figure 3 1 New Project Window C C Application x Click Finish to create this project with a default system library D Name ci tutorial 0 M Use Default Location Select Target Hardware SOPC Builder System D edatools altera kits nios2 tutorials Nios2_Custom_Instruct Browse CPU cpu 0 Select Project Template Description Leading Zeros Custom Instruction Software Details This example exercises the leading zeros custom instruction included in the Custom Instruction Tutorial hardware design The application counts the number of leading zeros on an array of val
38. tem and compile the design in Quartus II Altera Corporation Nios II Custom Instruction User Guide December 2004 Implementing a Nios II Processor Custom Instruction Open The Custom Instruction Hardware Design 1 Choose Programs gt Altera gt Quartus II version Windows Start menu 2 Choose Open Project File menu 3 Browse to the quartus project directory for your board 4 Choosethe custom instruction qpf and click Open 5 Choose SOPC Builder Tools menu to start SOPC Builder Add The Leading Zeros Custom Instruction Logic This section walks you through the process of adding a custom instruction to an SOPC Builder system and also provides custom instruction tool flow explanations 1 Selectcpu 0 in the Altera SOPC Builder System Contents page See Figure 3 4 Figure 3 4 SOPC Builder System Contents Page Altera SOPC Builder system File System Module View Tools Help System Contents More cpu_0 Settings System Generation YA Altera SOPC Builder Interface to User Logic Avalon Modules AHB Modules All Available Components amp elo j Q check Target Nios Development Board Cyclone EP1C20 5 sys clk timer ed Timer high res timer interval timer Tag uart JTAG UART sysid System D Peripheral 0x00010808 offchip memory sram IDT71V418 SRAM 0x00200000 v T T 7 System Clock Frequency 50 lag n 0x00010820 0x00010800 tri state bridge Avalon
39. ter USB 0 Wi Start n Auto Detect X Delete Ch Add File E Change File 8 Add Device Mode JTAG File Security Bit Checksum Usercode 1 custom_instruction sof _EP1C20F400 004796C5 FFFFFFFF Altera Corporation December 2004 When the Nios II IDE detects that the SOPC Builder system for the current project differs from the SOPC Builder system on the board you must download an appropriate configuration file for the FPGA To download a new FPGA configuration file SRAM object file sof to the Nios development board perform the following steps 2 Choose Open File menu A Windows Explorer dialog box appears Select custom instruction sof See Figure 3 3 Click Open to add the custom instruction sof programming file to the Quartus II Programmer file list and return to the Quartus II Programmer From the file list turn on Program Configure for the custom instruction sof programming file See Figure 3 3 Choose Start Processing menu to download the programming file 3 5 Nios II Custom Instruction User Guide Implementing Custom Instruction Hardware in SOPC Builder Implementing Custom Instruction Hardware in SOPC Builder 3 6 Your Altera programming hardware must first be configured correctly before you can click the Start button If necessary click Hardware Setup to configure your programming hardware 7 Exit the Quartus II Programmer and return to
40. the Nios II IDE 8 Inthe Nios IL IDE choose Run As Nios II Hardware Run menu This will start the build process and download the software image to the development board After the image is downloaded the terminal will display the results of running 500 samples through the leading zeros detector in software The worse case number is if all the samples are a value of 0x1 The best case numbers are for the case of 0x80000000 The random case is random samples The following is an example of the three sets of test data Now measuring the time to find leading zeros for 500 samples kk ce ck ke ck ck ce ce ke ke ck ce ce ke ke ck cec ck ke ce ke ke ck ke ke ke ke ck ck ce e ke ke ck ck ck ck kk kc kk KE Worst Case Software Number of clocks 138410 The number mills seconds 2 7681999207 Random Case Software Number of clocks 21926 The number mills seconds 0 4385199845 Best Case Software Number of clocks 12434 The number mills seconds 0 2486800104 K KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK Program Complete This section walks you through the process of implementing Nios II custom instructions in hardware and also provides custom instruction tool flow explanations To implement the Nios II custom instruction for the leading zeros design you must 1 Open the custom instruction tutorial hardware design 2 Addtheleading zeros custom instruction logic to the Nios II CPU 3 Generate the SOPC Builder sys
41. uction troducebnoni isanil LA LALA ali Hardware amp Software Requirements Tutorial Files i Design Example Leading Zeros Detector Running the Software Algorithm in Nios II IDE ss Creating a New Nios II IDE Project urina Building amp Downloading the Software Application Implementing Custom Instruction Hardware in SOPC Builder sse 3 6 Open The Custom Instruction Hardware Design seen 3 6 Add The Leading Zeros Custom Instruction Logic ss 3 7 Altera Corporation iii Contents Generate the SOPC Builder System amp Compile in Quartus II Software _ 3 10 Accessing the Custom Instruction from Software ss 3 11 Custom Instruction Templates 1 VHDL amp Verilog HDL Templates A 1 VHDL UL C aSa A 1 Verilog HDL Template aaa A 2 Custom Instruction Built In Functions 1 Built In FUNCHONS 4112 coc iL ARL i B 1 Built In Functions Returning Void sise B 1 Built in Functions Returning int sine B 1 Built in Functions Returning float si B 1 Built in Functions Returning a Pointer ns B 2 Porting First Generation Nios Custom Instructions to Nios Il Systems 1 Hardware amp Software Porting Considerations ss C 1 Hardware Porting Considerations esistente ente teri te eben tette etie tents C 1 Software Porting Considerations ss C 1 Mona cuu M MELLE D RR IRE rei I FARI C 1 iv Altera
42. ues first using simple software algorithm and then using a custom instruction to accelerate the algorithm See the Nios II Custom Instruction User Guide for additional details MicroC OS II Message Box Next gt Cancel 5 Click Browse in Select Target Hardware The Select Target Hardware dialog box appears 6 Browse to the custom instruction tutorial hardware design for the Nios development board that you are targeting 7 Choose the system ptf SOPC Builder system file 8 Click Open to return to the New Project wizard The SOPC Builder System field from the Select Target Hardware window is now specified with the custom instruction project SOPC Builder system See Figure 3 1 In addition the CPU field now contains the name of the CPU in the system 9 Click Finish Altera Corporation 3 3 December 2004 Nios Il Custom Instruction User Guide Running the Software Algorithm in Nios Il IDE At this point the new Nios II project file creation is complete Figure 3 2 shows that upon successful project creation the C C Projects window contains the following m Application project ci tutorial 0 m HAL software library for the custom instruction hardware ci tutorial O syslib m Niosll device drivers Figure 3 2 C C Projects Window P Gar A EI 6 ci tutorial 0 ci tutorial O syslib system Nios II Device Drivers s For more information on the HAL software l
43. ult 31 0 port All other custom instructions port operations remain the same External Interface Custom Instruction Figure 1 9 shows that the Nios II processor custom instructions allow you to add an interface to communicate with logic outside of the processor s data path At system generation any signals that are not recognized as custom instruction signals will propagate out to the top level of the SOPC Builder module where external logic can access the signals Figure 1 9 Custom Instructions Allow the Addition of an External Interface Optional Interface dataa 31 0 datab 31 0 clk P done rese start gt result 31 0 1 12 Altera Corporation Nios II Custom Instruction User Guide December 2004 Nios II Custom Instruction Overview Altera Corporation December 2004 Figure 1 9 shows a multi cycle custom instruction that has an external memory interface Because the custom instruction logic is able to access memory external to the CPU it extends the capabilities of the custom instruction logic Custom instruction logic can perform various tasks e g store intermediate results or read memory to control the custom instruction operation The optional external interface also provides a dedicated path for data to flow into or out of the CPU For example custom instruction logic can feed data directly from the CPU s register file to an external FIFO memory buffer bypassing the process
44. xternal interface Combinatorial custom instructions can be further optimized by utilizing the extended custom instructions architecture Refer to Extended Custom Instruction Architecture on page 1 9 Figure 1 4 Combinatorial Custom Instruction Interface Timing Diagram TO TI T2 T3 T4 1 11 K 3 dataan D 1 GI date mmm Gi I result result valid 1 6 Multi Cycle Custom Instruction Architecture Multi cycle or sequential custom instructions consists of a logic block that requires two or more clocks to complete an operation Multi cycle custom instruction can complete in either a fixed or variable number of clock cycles Additional control signals are required for multi cycle custom instructions See Table 1 3 Figure 1 5 shows the multi cycle custom instruction block diagram Altera Corporation Nios II Custom Instruction User Guide December 2004 Nios II Custom Instruction Overview Figure 1 5 Multi Cycle Custom Instruction Block Diagram Optional Interface dataa 31 0 datab 31 0 clk gt done rese start gt result 31 0 As stated previously multi cycle custom instructions can be either fixed or variable length in duration Fixed length You specify the required number of clock cycles during system generation Variable length The start and done signals are used in a handshaking scheme to determine when the custom i
45. ystem generation SOPC Builder will wire the custom logic to the Nios II CPU 1 Click Generate in the SOPC Builder 2 Click Exit when SOPC Builder system generation is complete 3 Return to the Quartus II window 4 Choose Start Compilation Processing menu to begin compilation Altera Corporation Nios II Custom Instruction User Guide December 2004 Implementing a Nios Il Processor Custom Instruction Accessing the Custom Instruction from Software Altera Corporation December 2004 Now that you have added the custom logic block to hardware you are ready to access it from software Because there is a change to the SOPC Builder system contents the Nios II IDE project needs to be rebuilt to accommodate the changes One important change will be that the system h header file will be updated with the macros for the custom instruction Return to the Nios IT IDE Building amp Downloading the Software Application on page 3 4 and repeat steps 1 through 8 Once you are done you will see the difference the custom instructions make in performance Refer to the following console output Now measuring the time to find leading zeros for 500 samples kk ce kk ck ck ce ce ke ke ck ce ce ke ke ck cec ck ke ce ck ck ck ke ke ke ck ck ck ck ck ck ke ck ck ck ck ko kc kc EE kk Worst Case Software Number of clocks 139632 The number mills seconds 2 7926399708 Hardware Number of clocks 8443 The number mills seconds 0 168
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