PHASE-1 User Manual - IPHC
Contents
1. Section 4 Synchronization and Digital Output Channel 2 ad Name Description Cell Type DI activate readout marker and clock ICPD pulldown ee probe Pa Probe VDD3ALLP _ Power DI synchronize the outputs pulldown o probe Pa Probe VDD3ALLP _ Power me probe Pa Probe LVDS TX_ DO LVDS LVDS TX_ DO LVDS e a probe Pa Probe GND3ALLP__ Power GND3ALLP_ power DO 57 OUT2_CMOS lt 3 gt data output slow speed channel 2 stream 3 BU4P 4mA GND3ALLP _ power DO 3 state 59 OUT2_CMOS lt 2 gt data output slow speed channel 2 stream 2 BU4P 4mA GND3ALLP _ power pf probePad probe LVDS TX___ DOLVDS LVDS TX_ DO LVDS July 2008 PHASE 1 User Manual v1 0 23 PHASE 1 probe Trobe VDD3ALLP __ power RRE 64 OUT2_CMOS lt 1 gt data output slow speed channel 2 stream 1 BU4P digital power power VDD3ALLP power DO La eene EE OUT2_CMOS lt 0 gt data output slow speed channel 2 stream 0 BU4P 4mA een _Prob ial powee ooo power VDD3ALLP power digitalpower S power PS E EE EE probe 69 CLKD_p readout clock for digital data LVDS TX__ DO LVDS LVDS TX_ DO LVDS wooo e O WE RES plen Jesse Et SCH 72 RSTB asynchronous reset active low ISUP schmitt ee probe Pad probe GND3ALLP power Section 5 Analog bias for pixels Pad Name Description Cell AGND3ALLP direct pad AVDD3ALLP Section 6 Master clock LVDS Pad Name Description Cell GND3ALLP s Jodi Jagtigouna O fonva E E DES LVDS RX_ DI2. July 2008 PHASE 1 User Manual v1 0 12 PHASE I Bias synthetic block diagram PIXELS SCAN lAnaBUF E E E T Gg ToT VCLPDIS yy GC DISCRIMINATORS BUFFERS 7 A i E f B j E A LE BUFBIAS VTEST1 VTEST2 VDREF1 VDREF2 DISCLP 639 0 POWER PULSE LVDS LVDS LE LIT Or _ BYR RECEIVER DRIVER e v Dj oj PWRSWBIAS IDIS1 IDIS2 ID1PWRS ID2PWRS ILVDSTX 3 3 Setting the Readout Configuration Registers If the desired operating mode does not correspond to the default one set RO MODEO RO_MODE1 CONTROL_REG SEQUENCER_REG LINEPATO_REG LINEPATI_REG registers following the 2 2 6 2 2 7 2 2 8 2 2 9 and 2 2 11 3 4 Readout 3 4 1 Signal protocol After JTAG registers have been loaded the readout of PHASE 1 can be initialized with following signal protocol e Start readout clock Master Clock 160 MHz e Initially set SPEAK signal to 0 e Set to 1 the START signal for 2000 ns minimum During this step the internal reset is generated and then the clock dividers start to produce the clkdiv10 16 MHz and clkdiv 1 MHz e The readout controller starts at the first falling edge of clkdiv Signal markers allow the readout monitoring and the data outputs analogue and digital sampling gt CLKA and CLKD are running when readout controller starts CLKA is a logic OR between Read and Calib signals and CLKD corresponds to 160 MHz fast readout or 40 MHz slow readout gt When SPEAK signal is a
3. iPHC Institut PR Ale PHASE I1 User Manual PRELIMINARY VERSION A Himmi G Bertolone A Brogna W Dulinski C Colledani A Dorokhov Ch Hu F Morel I Valin Institut de Recherches Subatomiques IN2P3 CNRS ULP Strasbourg France UNIVERSIT LOUIS PASTEUR STRASBOURG a OI PHASE I Document history Version Date Description July 2008 Creation based on Mimosa22 version PHASE 1 chip 1 0 Submitted July AMS C35B4 Opto 640x640pixels pitch Preliminary version 2008 30um readout 160 MHz July 2008 PHASE 1 User Manual v1 0 2 PHASE I Me Een ar Tu pagers ss Se E Sessa orca meee dees eee Soon E ner mane E E E EE E E E E 4 EE EE ee 5 2 1 AE EE an a EE e meee E AE EEE E AT E E AT E AE 5 22 UTE PGS ING SSL E 5 Aak TOER ic a E E E E creer ty 6 GR KA TR RE 6 ZZ Bypass e LEE 6 224 Boundary Scan E 6 22 9 BIAS DAC EE 7 220 RO MODE REGIS 60 eege 7 227 RO TRIER EE 8 2240 CONTROL REG RESISTI oeoa SE EEEIEE EE AAEE EaU nE 8 229 SEENEN eegen 9 2 2 10 DIS DISCRI Register EE II 2 2 11 LINE PATO E II 22A2 LINEPATI REG Register ccnancasaasdeausassaponsmeneaennssicneaeataisweouuninepenastacheassnngasneeteoenseatinensnaaaagteaooys 11 3 Poona Ti E IK 3 1 PTT EE 12 3 2 BSS HS Phase EE 12 3 3 Setting the Readout Configuration Registers ccccccccccccssssssssssseseeeececeeeeeeeeeeaeaesssseseeeeeeeeeeeees 13 3 4 EE Ee 13 JAL Signal POLO ON ogc dsatsmeseeriaedouieaseatcaateneneme ean ia ee E
4. 3 state P probePad probe gnda _ Prob digital ground GND3ALLP power DO 3 state 109 tstlpad readout test pad 1 BT2P 2mA ee probe Pad probe vdd _ Prob digital power VDD3ALLP power DO 3 state tst2pad readout test pad 2 BT2P 2mA SOOO ooe probePad probe digital ground GND3ALLP power Section 10 Analog test for discriminator ad Name Description Cell Type gnda _Prob analog ground AGND3ALLP power analog ground AGND3ALLP power AVDD3ALLP power July 2008 PHASE 1 User Manual v1 0 23 PHASE 1 AVDD3ALLP _ power power AVDD3ALLP _ power power AGND3ALLP power or veu Jain Jumm im 121 Vtstl vtestl external injection APRIOP Ohm power 123 v2 Jet senge Ju is 123 Vtst2 vtest2 external injection APRIOP Ohm AGND3ALLP power leen beten favor D 125 Vref2 vref2 external injection APRIOP Ohm 126 gnda sid analog ground isi sSCid ground AGND3ALLP power oy ven ven sende Je is 127 Vrefl vref2 external injection APRIOP Ohm 128 gnda analog ground AGND3ALLP power analog power power 130 vdda analog power AVDD3ALLP power AVDD3ALLP AVDD3ALLP analog ground AGND3ALLP enda _Prob analog ground AGND3ALLP Section 11 Digital Output Channel 0 ad Name Description Cell Type gnd _ Prob digital ground GND3ALLP power leng 3 state 136 OUTO_CMOS lt 3 gt data output slow speed channel 0 stream 3 BU4P 4mA
5. Onf ffr Sict_Row_int 0 r Camp d RSTI O f Read Calib Latch MK_CLK_A CLK_A 2 372 000ns 2 374 000ns SE i Data Ana Row 0 First Row add second Row add Last bit frame of serialization f A Last Row of frame REECH EEN r rL EI Ze EE E kuaaaaautuaaatat1auatuaantat AAA AAA y ar 8 OK OOIEK XO UTEK OITUK DP RPRRRL GPP RRR IDLO PPRR RD LORPRRRROLOPRR MWEIEKOUHK OTUIEK OTI OI OTI A HIH AO UI OUT OUIRKOOTTIEKO UU OU HEK OH OO HIE OU UU BR i sebbbi pel Wet tl aaa bi hath as abb Ta op 0 t O e e e enee e e e e ee e ON ka Dogeg Read phase Vieatl b Data Discri Row 639 LinePat0Reg LinePatiReg Data Discri Row0 selected in analogue outputs and during Calib phase Vtest2 is selected Figure 7 interframe timing diagram shows the ending of frame and first row digital data serialization when En_LineMarker is set to 1 and MODE_SPEAK is set to 0 These options are set via the RO_MODEO register July 2008 PHASE 1 User Manual v1 0 17 PHASE I 639 629 480 479 320 319 160 159 0 lt Trame_id 9 0 gt LINEPATLOReg 629 0 or LINEPATL1 Reg 629 0 START Frame n Frame n 1 Frame n 2 MK_LineMarker B 10_0000_0000 B 01_0000_0000 B 00_1000_0000 ae B 00_0000_ 0001 Trame_id 9 0 MK_LineMarker Latch Hx402AAA _ Hx401555 LinePatOReg LinePat1Reg Fig
6. power E z 3 state 138 OUTO_CMOS lt 2 gt cata output slow speed channel 0 stream 2 BU4P 4mA GND3ALLP __ power probed probe LVDS TX_ DO LVDS LVDS TX___ DO LVDS o Probe poe VDD3ALLP _ power ja z 3 state 143 OUTO_CMOS lt 1 gt data output slow speed channel 0 stream 1 BU4P 4mA 144 v VDD3ALLP _ power DO Ta OUTO_CMOS lt 0 gt aa output slow speed channel 0 stream 0 BU4P 4mA 146 power Section 12 Test PLL synthesizer Description Cell Type DI pullup 147 asynchronous reset active low ISUP schmitt July 2008 PHASE 1 User Manual v1 0 26 PHASE 1 VDD3ALLP _ power ICCK2P Bes What 150 FB feedback BU4P digital ground EE GND3ALLP power LVDS TX___ DO LVDS LVDS TX___ DO LVDS 154 AVDD3ALLP power power ass Jon frotagecomttorosinr Juge Jo 156 CTL voltage control for oscillator APRIOP 0 Ohm AVDD3ALLP _ power power AVDD3ALLP _ power power Section 13 Analog bias for pixels ad Name Description Cell clamping voltage for pixels DIRECTPAD _ direct pad v_clp _Prob clamping voltage for pixels DIRECTPAD _ direct pad Section 14 Test Analog outputs from the matrix ad ame escription Cell Type be haen test pad analog ground test pad analog power analog output lt 0 gt test mode analog output lt 1 gt test mode analog output lt 2 gt test mode analog output lt 3 gt test mode Lt WE ee analog output lt 5 gt test mode Lt analog output lt 6 gt test mode L
7. in Section 2 the information to operate the chip are in the Section 3 and the layout of the padring with chip bonding are in the Section 4 172 163 Ki Ca a D ta m analog data processing serializer serializer seralizer serializer DACs bias JTAG Icontroller PLL PLL test 1 162 Figure 1 abstract view of the die it does not reflect the real floorplan since the scale factor is altered for sake of clarity but it shows all the main blocks and the chip architecture July 2008 PHASE 1 User Manual v1 0 4 PHASE I 2 Control Interface The control interface of PHASE 1 complies with Boundary Scan JTAG IEEE 1149 1 Rev1999 standard It allows the access to the programmable internal registers On power on an internal reset Power On Reser is automatically generated for the control interface the initial status of the Test Access Port TAP is Test Logic Reset and the ID register is selected PHASE 1 has been designed in order to be fully tuneable via the control interface nevertheless some voltages level might be forced from the external pads 2 1 JTAG Instruction Set The Instruction Register of the JTAG controller is loaded with the code of the desired operation to perform or with the code of the desired data register to access D se Selected Register EXTEST BSR JTAG mandatory instruction ZU eis instruction TI DU e instruction instruction D instruction NU Bi Reserved Not Used AS oe oS ona rose
8. the data for the High Speed output at 160 MHz Please observe the sequence at the output this 2 levels architecture scrambles the data coming out from the high speed output July 2008 PHASE 1 User Manual v1 0 19 PHASE I 3 6 3 Main Signal Specifications Parameter Typical Notes Value ITAG READOUT CKRD Frequency Up to 100 MHz Readout Clock LVDS signal ee START Setup Hold Time 5 ns Chip Initialisation CMOS signal Input Dynamic range Rise time E Fall time ooo Bandwidth Pd up ConeneRange 4 Pad Ring The pad ring of PHASE 1 is build with e Pads full custom designed for some of the analogue signals and power supplies e Pads from the AMS library for the digital signals and power supplies The pad ring is split in 8 functional independent parts CMOS JTAG and Test purpose pads LVDS Read Out Drivers Digital outputs Read Out Analogue Outputs Bias Test Analogue and Digital Power supplies Test structure Test structure 2 Each part has its own supply pads July 2008 PHASE 1 User Manual v1 0 20 PHASE 1 4 1 PHASE 1 Pad Ring and Floor Plan View a e eee eat P lt 8 gt 19G lt T gt 9 Section14 lt e gt me ka SA lt 9 gt 1nG lt 9 gt 10G a DEER July 2008 Sp AGGA SE Ou i EHL E Gi Section 12 HN 1i is adh d m pe Section 12 te sos tdko mm MMU Za ag eevee Section 11 Vgl 8Lno BEESON w A
9. v1 0 18 P Baseline v 2 375 046 875ns EP Cursor Baseline v 100ns Name v Gr en_hs gt CkDiv10 Pwr_On 639 Sict_Row_int 639 Clamp 639 RSTI 639 Pwr_On 0 Ski Pow mt Camp RSTI 0 ra Caib E Latch E MK_CLK_A gt CLK_A a Tg selbO Ba grp t OI PA MK_CLK_D Cursor s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PHASE I En_LineMarker 1 MODE _SPEAK 0 En _HS 0 Data Ana Row 0 ee EE KO fa 2 fs fo fa f2 fs fo fa f2 fs fo fa fe fs 1 asl bar eae Geen first bit frame of serialization Figure 10 When En_HS is set to 0 the Low Speed mode is activated The readout clock at 40 MHz comes out from the CLKD pad or CLK_D internal signal and a synchronization marker MK_CLK_D appears at the last serialized bit of each frame This signal is used to sample the first bit of the new frame on the next raising edge of CLKD 01234567 Low speed stream 1 40 41 42 43 44 45 80 81 82 83 84 85 120 121 122 123 124 Low speed Low speed Low speed stream 2 stream 3 stream 4 Main Stream at High Speed 160MHz 0 40 80 120 1 41 81 121 2 42 82 122 Figure 11 There are 4 identical serializers in PHASE 1 one for each High Speed output Here is the basic architecture of one of them which shows the 2 hierarchical levels of multiplexing The first 40 1 generates the slow speed streams at 40 MHz only for testing purpose and the second one 4 1 assembles
10. 0 DataClp Set reference voltage for 01CO Clamp clamping 79 64 DataCalib Sample after clamping 3C00 63 48 DataRdDsc Sample before clamping OOLC 47 32 DataLatch Latch state of the 6000 1 Latch discriminator Activate power supply for TEFFFFFF pixel July 2008 PHASE 1 User Manual v1 0 9 PHASE I 1 Example Generation of Latch Signal lt 160 ns gt TESTEN 8 9 A BC D E F0 z Latch 15 14 13 12 i 9 se 7 e s5 4 3 2 1 o Patatatch o 1j o o o o o o o o jo o jo jo o e Related timing with fckaiv o 16 MHz Read Calib Latch signals are used by the column readout circuitry The Rst signal is not used for pixel e This is readout sequence of the pixel and discriminator for 2 successive rows of matrix In the wave form the indexation of internal signal vectors is reversed compared with the Phasel functional view for example the signal Pwr_On 639 corresponds to the row at the top of matrix A Baseline Y 447 171 GZ Sd LCusor Basehreen A8 le Name Cursors pm im Ckdivio aE Pwr_On 639 wilt Slot_Row_int 639 l hae d RSTI B39 a dt Clamp i633 beer t Pr Dr d Sict_Row_int 633 aE RSTI 638 d Ciampl3s e gt gt H H e GN O H July 2008 PHASE 1 User Manual v1 0 10 PHASE I 2 2 10 DIS_DISCRI Register The DIS_DISCRI register is 640 bits large The purpose of this register is to disable the discriminator on a specific column if i
11. E aE E Ean 13 3 4 2 Successive frames and resvpnchrontsaton 14 3 5 Analogue and digital Data Format 14 3 5 1 Normal mode data e e E E 14 39 2 Test mode Gata e EE 15 3 6 PHASE 1 Tomine Tio AS sna vanescencacausennneasaaaanadeadaanea ia a aa aioa quant S aniar ann aiaiai 16 3601 Normal e 16 302 Ee E E 16 3 6 5 Main Signal ele ee 20 Be MA AE 20 4 1 PHASE 1 Pad Ring and Floor Plan View 21 4 2 PPA E EE 22 July 2008 PHASE 1 User Manual v1 0 3 PHASE I 1 Introduction PHASE 1 is the intermediate version of the monolithic integrated detector to be used in the STAR experiment at RICH The architecture is based on Mimosa22 with faster readout and larger matrix of pixels The design process is Austria Mikrosysteme AMS C35B4 OPTO which uses 4 metal and 2 poly layers The thickness of the epitaxial layer is 14 um The design tools are provided by CMP Cadence DFH v5 1 IUS v 5 7 SoC v4 1 LDV v5 as well as the verification tools Diva Assura v3 17 Calibre v2007 02 The chip was submitted as Engineering Run on July 2008 The size of the chip is 19 52 mm x 20 93 mm but the active area is 19 2mm x 19 2 mm and contains an array of 640 x 640 pixels with a pitch of 30 um An abstract view of the die is depicted in Figure for the sake of clarity the picture is not in scale and does not reflect the real layout even if it shows all the main blocks and the chip architecture Details how to program the internal functionalities of the chip are
12. LVDS 80 CKR_n master clock LVDS compatible LVDS RX__ DI LVDS mf probePad pobe VDD3ALLP VDD3ALLP Section 7 Master clock PLL synthesizer Pad Name Description Cell Type 83 vppp Joes pone JNDD3ALLE GND3ALLP ICCK2P DI clockin 86 GNDA amalogground SF AGNDBALLP AVDD3ALLP Section 8 Analog bias for pixels Description Cell 89 gnda analog ground AGND3ALLP power 90 v_clp clamping voltage for pixels DIRECTPAD direct pad July 2008 PHASE 1 User Manual v1 0 24 PH AA 91 vdda analog power AVDD3ALLP power fi Section 9 Digital Output Channel 1 and Readout clock Description Cell Type e ae clock CMOS compatible ICCK2P DI clockin probePad probe power GND3ALLP _ power DO 2 _CMOS lt 3 gt data output slow speed channel 1 stream 3 BU4P 4mA 96 ead GND3ALLP __ power DO 3 state 97 OUTI_CMOS lt 2 gt data output slow speed channel 1 stream 2 BU4P 4mA 98 gnd digital ground e LOND3ALLE power Pf probed prote EL a a sofa LVDS TX___ DO LVDS LVDS TX___ DO LVDS o Probe pote power DO 3 state T OUTI_CMOS lt 1 gt data output slow speed channel 1 stream 1 BU4P 4mA digital power VDD3ALLP power DO 3 state 104 OUTI_CMOS lt 0 gt data output slow speed channel 1 stream 0 BU4P 4mA 5 vdd _ Prob digital power VDD3ALLP power abe z 3 state 106 CLKA readout clock for analog data BT4P 4mA ee probe Pad probe DO MK_CLKA marker and clock for analog data BT4P 4mA
13. T analog output lt 7 gt test mode Probe pads are used only for test purpose and should not be bonded July 2008 PHASE 1 User Manual o Dad o Dad o Dad o Dad o Dad o Dad o Dad o Dad o Dad Gs o Dad o Dad o Dad o Dad o Dad o Dad test pad test pad test pad test pad test pad test pad test pad test pad test pad test pad test pad test pad test pad test pad test pad test pad test pad test pad
14. a Not Used BYPASS 1F BYPASS JTAG mandatory instruction 1 Instruction codes implemented but not the corresponding registers To be fixed in the next version 2 2 JTAG Register Set JTAG registers are implemented with a Capture Shift register and an Update register JTAG standard imposes that the last significant bit of a register is downloaded shifted first Register Name INSTRUCTION REG 3 R W__ Instruction Register _ __ O Z ooo Ron J ooo O July 2008 PHASE 1 User Manual v1 0 5 PHASE I Bak RW BIAS DAC 120 R W____ Previous value shifted out during write RO_MODEO 8 LIN 1 Previous value shifted out during write RO MODEI 8 R W_ Previous value shifted out during write LINEPATLO_REG 640 R W__ Previous value shifted out during write UNEPATLI_REG 640 MN __ Previous value shifted out during write Notimplemented For future us 2 2 1 Instruction Register The Instruction register is a part of the Test Access Port Controller defined by the IEEE 1149 1 standard The Instruction register of PHASE 1 is 5 bits long On reset it is set with the ID_CODE instruction When it is read the 2 last significant bits are set with the markers specified by the standard the remaining bits contain the current instruction xX x x 1 o 2 2 2 DEV_ID Register The Device Identification register is a read only 32 bit register When selected by the ID_CODE instruction or after the fixed value is
15. are serialized on fall Cebra edge clock of CLKD E Besa EA Cp Ph Laich E Erak i iktr B T pil aj c Be opt o When the first fall edge clock of ckdiv arrived The sequence of sequencer_reg is actived for state machine Readout Controller during the low level period of Sloadb signal When Sload signal is rising the state machine of Readout Controller generates usefull signals for pixel and discriminator readout Figure 5 zoom on readout start after a latency of 5 clkdiv cycles readout of matrix starts the zone on the right will be expanded for clarity July 2008 PHASE 1 User Manual v1 0 16 PHASE 1 F Cursor B Name Cursor v Ee chkdivid EA ckdiv gt Pwr_On 639 Ex Siet_Row_Int 639 8 Clamping 639 E Read gt Caib Select low speed output gt EnaMux L T ckdv D sdf I ok Sm opt 0 E gt CLK_D es Discri How When EnaMux is rising the Select high serializer of data discriminators speed output starts Data are serialized on fall edge clock of CLKD Figure 6 start of the serializer the latch signal enables the outputs Data are sent on falling edge of CLKD It is visible the readout of the first row and the beginning of the serialization A Baseline v 2 373 171 875ns En_LineMarker 1 MODE _SPEAK 0 LP Cursor Baseline v 2000ns Name v Cursor 370 000ns CkDiv10 Pwr_On 639 ffr Set Boa ku EZ er Clamp 639 iis ASTI 639 uf For
16. ctive markers of synchronisation for analogue and digital outputs are generated on MK_CLK_A and MK_CLK_D pads July 2008 PHASE 1 User Manual v1 0 13 PHASE I 3 4 2 Successive frames and resynchronisation Successive pixel frames are read meanwhile the readout clock is running The frame resynchronisation can be performed at any time by setting up the START token again Previous frame Current frame Next frame Last frame gt a gt a w ma gt LastRow SPEAK LastRow LastRow l MK_SYNC_CLK_A l MODE_SPEAK 0 i MK_SYNC CLK A i i MODE_SPEAK 1 MK_SYNC_CLK D LastRow LastCol a a LastRow gea l MODE_ SPEAK l el MK_SYNG_CLK_D L MODE_SPEAK 1 lt Read Calib Clk 160 Mhz I R Disable MK SYNC_CLK A or 40 Mhz and MK_SYNC_CLK_D SPEAK signal allows to generate markers signals which are used by DAQ When SPEAK signal is set to 1 during the current frame an analogue marker appears on MK_SYNC_CLK_A pad and digital marker appears on MK_SYNC_CLK_D pad on next frame In the MODE_SPEAK 0 see Figure 9 Figure 10 the MK_SYNC_CLK_A marker corresponds to last row of the frame and the MK_SYNC_CLK_D marker corresponds to last bit frame In the MODE_SPEAK 1 the MK_SYNC_CLK_A signal corresponds to a sampling clock for analogue outputs data same as CLKA which starts at the first row of frame MK_SYNC_CLK_D signal corresponds to readout clock
17. for digital data same as CLKD which starts at the first bit frame When SPEAK signal is set to 0 MK_SYNC_CLK_A and MK_SYNC_CLK_D are set to 0 3 5 Analogue and digital Data Format PHASE 1 uses the pads at the bottom edge for all its operations whatever is collecting data from the pixels using the pixels and the discriminators or in test mode reproducing at the outputs the pre programmed patterns All the digital signals to synchronize and programming the chip are necessary to operate successfully Analog outputs located on the top edge of the chip are not used for the normal operations The main purpose is to characterize the pixels or to check the dead pixels Therefore measurements on these pads deal with normal pixel signals as well as test signals but they still require the synchronization and the markers and it is activated on demand by setting to 1 the En_AnaCol bit in the RO_MODE I register 3 5 1 Normal mode data format The digital part includes three blocks One is JTAG controller interface which allows configure the internal registers used to readout chip The second circuit generates the patterns necessary for addressing resetting and double sampling of the signals in pixels in a column parallel way The clock scans line by line at 1 MHz and latches the data in the output register which is divided in 4 parts each connected to one of the 4 main outputs Figure 11 shows the internal structure of the output register and the seriali
18. is signal is active at high level 2 When En_ExtStart is disabled it s possible to generate internal START by accessing JTAG_Start bit JTAG_Start signal is realized by three JTAG access First step this bit is set to 0 second step it is set to 1 and at last it is set to O 2 2 7 RO _MODE1 Register The RO_MODEI registers are 8 bits large they allow selecting specific analogue mode of the chip a 2 a a O o o 5 En PixScan Enable scan pixel mode OP 4 DisBufRef Disable the internal reference 0 Select Internal Buffer 3 En HS Enable High speed mode Select low speed mode 2 En AOP_Disc__ Enable the Power pulse Amplifier 0 Normal mode 1 En Pulse Discri Enable the discri power pulse mode 0 Normal moie 0 En TstDis Enable the discri test mode 0 Normal mode 2 2 8 CONTROL REG Register The CONTROL_REG registers are 40 bits large they allow setting parameters of the readout controller EE sene S 3230 SelPadi Selection bit of TestlPad 0 MK Test Asignal 29 20 RowMkLast Row number of the frame It depends of Normal mode the number of row readout mode matrix is 640 When the En_HalfMatrx mode is active the value is OxO13F otherwise 0x027F When the En_LineMarker mode is active add two rows at the end of matrix TI Fe test mat dung Mereadout marker MK_Test_D matrix during the readout marker MK_Test_A of matrix during the readout The purpose of this array is to de
19. l of the new frame on the next raising edge of CLKA Further when the En_PixScan must be set to 1 this marker appears at the end of the frame for each submatrix Frame N 79 Frame N 78 Frame N 2 Frame N 1 Figure 2 Analog characterization of the pixel the matrix is divided in stripes of 8 columns and fully scanned at each frame then swapped with the next block of 8 columns at right and so on until all the columns are analyzed Ka Ga Figure 3 Mode scan for analog output 3 5 2 Test mode data format This test readout mode allows obtain the transfer function of discriminator and calibrate the pixel readout chain During the test mode the pixel matrix is not connected to discriminators and output analogue buffers Instead of this two test levels Vtstl Vtst2 are connected to discriminator inputs to emulate pixel signal July 2008 PHASE 1 User Manual v1 0 15 PHASE I The Vtstl voltage is applied to the positive discriminator input during the Read phase and the Vtst2 voltage is applied during the Calib phase Voltages can be adjustable via 2 DACs or can be provided via 2 pads The difference voltage Vtstl Vtst2 corresponds to the pixel output signal 3 6 PHASE 1 Timing Diagrams PHASE 1 needs an initialization step before starting the normal acquisition After the master reset the JTAG should be loaded with configuration and bias settings then the START signal begi
20. nators 2AAAAA_AAAAAAAA AAAAAAAA AAAAAAAA rows 1 This code is valid only after START 2 Example of pattern used in simulation 2 2 12 LINEPAT1_REG Register The LINEPAT1_REG register is 640 bits large but only the first 630 are programmable The purpose of this register is to emulate discriminators outputs rows in En_LineMarker and Pattern_Only modes When Pattern_Only is active the values stored in the pixel matrix are ignored and the value of LINEPATO_REG is sent to the output This is a test mode which emulates the digital pixel response with the contents programmed into the LINEPATO_REG register in order to verify the digital processing The pattern is alternated with the contents of the LINEPAT1_ REG In the En_LineMarker mode it adds two rows at the end of matrix for a readout chip and the LINEPATLI_REG register is read to emulate the discriminators outputs of these two supplementary rows This mode allows generating pattern marker in matrix data frame to detect chip readout desynchronization 639 630 Not used Reserved for the frame 200 counter read only 629 0 LinePatL1Reg Emulate discriminators 155555_55555555_55555555_55555555 rows 1 This code is valid only after START 2 Example of pattern used in simulation July 2008 PHASE 1 User Manual v1 0 1 PHASE I 3 Running Phaset The following steps describe how to operate PHASE 1 3 1 After reset On RstB active low signal All BIAS registers are
21. ns the automatic scanning ad readout of the pixel matrix 3 6 1 Normal Readout Ge Basel H LP Cursor Baseline v 9 S Name 0 40us 80us 120us 160us 200us J RSTB I CkRdLp i TCK START bn SeqhstB 1 a continuous LATCH 1 35065e 10 v 4 1 ie dir continuous CALIB 2 23512e 08 1 d 3 d i continuous LATCH 1 35065e 10 3 F3 3 3181V dir continuous EnTstMk 4 13325e 07 v i c k 0 00202967 V Lam LastRow MO h E CLKA 0 H 2 92017 R continuous Aout t 2 39376 sa i 1 I v 2 92017 Ka continuous Aout 0 2 39376 v i A 1 l Reset Jtag access init 1rst row readout j Successive row readouts Figure 4 Beginning of readout mode after Reset and JTAG settings the data are immediately available at the main outputs Subsequent frames are automatically handled by the internal logic 3 6 2 Readout synchronisation After 2 rise edge clock of CLKR when START signal is rising is rising the internal reset SeqRstB signal is generated The data sequencer_reg is loaded to a state machine Readout Controller RAA weld UE e Haira 449 171 ETSA d iii Curr e Ke Ra ges o BaD Ons D Rap 000ns CLEA START d i mE Hi obir E gt ck ei ai EA bmk 7 Sloat Readout of matrix starts Fa ChLoad Ill Il sy When EnaMux is rising the x l E pe Es Ee Ei be nipas 5 clock cycles of latenc serializer of data discriminators starts Data
22. od ipus z goad Beem a CS uppa I DbbA SC va Secton 13 i aipu SR ap Wb ZZ een v7 oS SdKD1un0 S TF PF sono 20 S t HEED ection EE EE spu SPORA I LNO sap a HE anno me Cen 5 sg ipu es M ps The ege ggf Nuet Secon ge iw epus b AIND DR zg ST Section RS Hig iPPA E iia em oe Section 6 Su 2 gt USCAT LNO ES d tt LNO Section 4 pus 2 gt SOWI 2Lno Be gt SOW9_ 2LN0 aig was SES mm 2 ch i PPA Ep hayas TI 9 44 ippa T aF MVadS ei 3 bi er A ee Section 3 re pug IN Aad apu ut i BENS Aa eLno E J T PF sono Lno SPP i RRENEN He BLnO 2 Section 2 7 4 C O Section 1 Bead BIC a SS ir SN a PHASE 1 User Manual v1 0 Figure 12 The pad layout of PHASE 1 Only the top edge and the bottom edge are visible The pads used for the test with a probe station are also drawn but not named because they reproduce the functionality of the adjacent pad 21 PH AA 4 2 Pad List i Section 1 Temperature sensor and Analog bias for pixels ad ame Description Cell Type EEN direct pad AGND3ALLP gnda _Prob AGND3ALLP DIRECTPAD 6 vdda _Prob AVDD3ALLP AVDD3ALLP Section 2 JTAG control and Digital Output Channel 3 ad Name Description Cell Type 8 Lat per aigitalpower JVDDOALUE __ power 9 vat de power power power ICCK2P DI clockin GT leste DI p
23. scribe the internal signals which can be checked using 2 test pads Tst1 Pad and tst2Pad The internal signals can be selected with SelPad1 and SelPad2 bits SelPadt TstiPad SelPad2 Tot2Pad MK_Test_A Analogue marker is delayed MK_Test_D Digital marker of 500 ns respect to MK_A corresponding to last signal This signal rises up serialized digital data at the beginning read phase It depends of and falls down at the end of RowMkd selection Calib phase It depends of parameter RowMka selection July 2008 PHASE 1 User Manual v1 0 8 PHASE I po parameters 1 Mk_Rd Analogue marker 1 PwrOns Same signal as PwOn corresponding to Rd phase but shifted of 16 main of readout pixel It depends clock of RowMka selection parameter 2 Mk_Calib Analogue marker Z PwOn Activate power corresponding to Calib supply for pixel phase of readout pixel It depends of RowMka selection parameter Ckdiv10 Main Clock is devised by 10 3 SlcRowInt Connect pixel output to common column Analogue marker Set reference voltage corresponding to readout for clamping pixel sequence It depends of RowMka selection parameter Set reference voltage for RstDiode Set reference voltage clamping for diode discriminator clamping clamping 2 2 9 SEQUENCER _REG Register The SEQUENCER_REG registers are 128 bits large this register contains all parameters to generate readout pixel and discriminator sequence fee Name common column diode 95 8
24. set to the default value i e 0 DIS_DISC is set to 0 te all columns are selected RO_MODEDO is set to 0 RO MODEL is set to 0 CONTROL_REG is set to 0 SEQUENCER_REG is set to 0 LINEPATLO_REG is set to 0 LINEPATLI1_REG is set to 0 JTAG state machine is in the Test Logic Reset state JTAG ID_CODE instruction is selected Then the bias register has to be loaded The same for the RO_MODEO RO MODERT CONTROL_REG SEQUENCER_REG LINEPATLO_REG LINEPATL1_REG and DIS_DISC registers if the running conditions differ from defaults Finally the readout can be performed either in normal mode or in test mode 3 2 Biasing Phaset The BIAS_DAC register has to be loaded before operating Phase The 16 DACs constituting this register are built with the same 8 bits DAC current generator which has a 1 uA resolution Specific interfaces like current mirror for current sourcing or sinking and resistors for voltages customise each bias output The following table shows the downloaded codes which set the nominal bias Internal Simulation Resolu Range Experimental Codes acInternal Output tion Code Codej Code current yA_ value 255 uA Dl o OO ATA bech aeee e lt lt gt aoo f N LA Cl CO p ID2PWRS IDIPWRS BufBias IPwrSW Bias 1 Referenced with respect to IVDREF 2 The threshold voltage of the discriminators is AVth Vref1 Vref2 and the relationship is Vrefl Vref2 AVth
25. shifted via TDO the JTAG serial output of the chip PHASE 1 ID_CODE register value is 0x50483101 Default value Code 31 0 ID_CODE Device Identification register 50483101 ASCII Poo 50 H 9 2 2 3 Bypass Register The Bypass register consists of a single bit scan register It is selected when its code is loaded in the Instruction register during some actions on the BSR and when the Instruction register contains an undefined instruction 2 2 4 Boundary Scan Register The Boundary Scan Register according with the Jtag instructions tests and set the IO pads The PHASE 1 BSR is 10 bits long and allows the test of the following input and outputs pads Corresponding Pad s foun opt foa paa ooo 7 CkCMOS ss CkCMOS CMOS Clock vps casey LVDS CkRdLn CkRdLp ClkLvds Resulting CMOS signal after LVDS Receiver July 2008 PHASE 1 User Manual v1 0 6 PHASE I START START Readout Input synchronisation SPEAK SPEAK Active Readout Marker amp Clock Ema MK_CLK_A MK_CLK_A_ Readout Analogue Marker amp Clock Readout Analogue Clock Tst2Pad Tst2Pad Readout Test Pad 2 0 Tst1 Pad Tel Pad Readout Test Pad 1 2 2 5 BIAS DAC Register The BIAS_DAC register is 128 bit wide it sets simultaneously the 16 DAC registers As show bellow these 8 bit DACs set voltage and current bias After reset the register is set to 0 a value which fixes the minimum power consumption of the circuit The current values of the DACs are read while
26. t is noisy by gating Latch signal and setting the output discriminator at Q The default value of the DIS_DISCRI register is 0 it means that all discriminators are activated Setting a bit to 1 disables the corresponding discriminator In Phasel the DisableLatch lt 639 gt is on the left hand side while DisableLatch lt 0 gt is on the right hand side 639 Msb 0 Lsb DisableLatch lt 639 gt DisableLatch lt 0 gt 2 2 11 LINEPATO_REG Register The LINEPATO_REG register is 640 bits large but only the first 630 are programmable The purpose of this register is to emulate discriminators outputs rows in En_LineMarker and Pattern_Only modes When Pattern_Only is active the values stored in the pixel matrix are ignored and the value of LINEPATO_REG is sent to the output This is a test mode which emulates the digital pixel response with the contents programmed into the LINEPATO_REG register in order to verify the digital processing The pattern is alternated with the contents of the LINEPAT1_ REG In the En_LineMarker mode it adds two rows at the end of matrix for a readout chip and the LINEPATLO_REG register is read to emulate the discriminators outputs of these two supplementary rows This mode allows generating pattern marker in matrix data frame to detect chip readout desynchronization Bit Name Basic configuration value Code 639 630 Not used Reserved for the frame 200 counter read only 629 0 LinePatLOReg Emulate discrimi
27. the new values are downloaded during the access to the register An image of the value of each DAC can be measured on its corresponding test pad Bit DAC DAC Internal DAC purpose Corresponding range Name Test Pad 39 32 DAC4 ID2PWRS__ Discriminator bias 2 mode low consp 31 24 DAC3 IDIPWRS Discriminator bias 1 mode low consp ICLPDISC DISCLP 2 2 6 RO MODEO Register The RO_MODEO registers are 8 bits large they allow the user to select specific digital mode of the chip Basic configuration value En_TstBuf Enable the internal injection of VTEST External injection of VTEST h Set the row shift register to 320 in place of 640 bits Normal mode 640 row shift register selected a DisLVDS Disable LVDS and active clock CMOS o LVDS selected En_LineMarker Add two rows at the end of matrix for a chip Readout Normal mode The LINEPAT_REG register is selected to emulate discriminators outputs For analogue outputs the 2 Test Levels VTEST1 and VTEST2 are selected which emulate a pixel output 2 Select Marker signal or Readout Clock for digital and ane analogue data MK_CLKA and MK_CLKD pads SOOS e e ES discriminators outputs Enable external START input synchronisation 0 Normal mode July 2008 PHASE 1 User Manual v1 0 7 PHASE I d M JTAG_Start Enable Jtag START input synchronisation 2 1 The minimum wide of asynchronous external START is 2000 ns and th
28. ullup t l oa dE Ta ede are icp ___ DI pullup D i stat gg TAG data ee BT4P SC CS EE aaO O power GND3ALLP__ power power DO 3 state OUT3_CMOS lt 3 gt data a slow speed channel 3 stream 3 BU4P 4mA sand digital ground JONDOALLE power i tte OUT3_CMOS lt 2 gt _ data ro slow speed channel 3 stream 2 BU4P poem ooo ooo di asa o ground GND3ALLP power probe Ce EE TX___ DOLVDS LVDS TX_ DO LVDS ee Probe probe VDD3ALLP _ power DO 3 state OUT3_CMOS lt 1 gt data output slow speed channel 3 stream 1 4mA digital power VDD3ALLP E 5 state OUT3_CMOS lt 0 gt data a slow speed channel 3 stream 0 BU4P a vdd _Prob digital power i S power VDD3ALLP power July 2008 PHASE 1 User Manual v1 0 22 PH AA Description Cell a analog ground Power gnda analog ground AGND3ALLP Power analog power Power 31 vdda analog power AVDD3ALLP_ Power analog power Power 33 vdda _ Prob analog power AVDD3ALLP _ Power analog ground Power 35 Itest APRIOP Power Se Probe 36 gnda analog ground AGND3ALLP Power discriminator clamping external injection direct pad 38 gnda analog ground AGND3ALLP Power so Jumm steen Ju Jo 39 VKIMO circuit monitoring APRIOP 0 Ohm AGND3ALLP _ Power direct pad AGND3ALLP _ Power vdda _Prob AVDD3ALLP _ Power AVDD3ALLP Power AVDD3ALLP Power AVDD3ALLP _ Power AGND3ALLP Power gnda _Prob AGND3ALLP Power
29. ure 8 When En_LineMarker is set to 1 the test of the digital data processing is active and 2 additional lines of pre programmed patterns are added at the end of each frame Then a new frame begins with the fresh data Data format of the test patterns is explained in 2 2 11 and 2 2 12 The frame counter is initialized to 0x200 after START and shifted to right at each frame En_LineMarker 1 MODE_SPEAK 0 vc Baseline es 2 375 109 375ne H Cursor Baseline Y 34 3753 En_HS 1 Mame Cursor d73 000ns Sex en_hs E CkDIVIO i ie Ever Ont ull Slet_Row_int B39 r Champes B ASTI 639 He Pwr On ae Slet_Row inti c Ciampi ve RSTI Ch Read i i Calib E gt Latch i EA MK_CLK_A d e afa 1e0ns Data Ana Row 0 e gt e gt e e e e Ge e e e CG Be CLK_A Gn sem ad DC E E a See EE GH opt 0 ha Bp A AS A8 A8 CD JS A AM EC CC JS A AM SR JS A DAS ce f CLK_D 1 E MK_CLK_D ae first bit frame of serialization Last bit frame of serialization Figure 9 When En_HS is set to 1 the High Speed mode is activated The readout clock at 160 MHz comes out from the CLKD pad or CLK_D internal signal and a synchronization marker MK_CLK_D appears at the last serialized bit of each frame This signal is used to sample the first bit of the new frame on the next raising edge of CLKD July 2008 PHASE 1 User Manual
30. zer There are 2 levels of multiplexing first one runs at full speed of 160 MHz and the second one 4 1 which is used mainly for test purpose runs at lower speed of 40 MHz Because of these additional multiplexing the output data are scrambled The Vrefl voltage is applied to the negative discriminator input during the read phase and the Vref2 voltage is applied during the Calib phase The difference voltage Vrefl Vref2 set the threshold of the discriminator Voltages can be adjustable via 2 DACs or can be provided via 2 pads When En_AnaCol bit is set to 1 in the RO_MODEI register the rightmost 8 columns of pixels are connected to the analog outputs via a voltage follower and the signal is available on the pads To start the analog test the En_PixScan must be set to 1 in the RO_MODE1 The scanning of the matrix now starts and stripes of 8 pixels are connected to the analog output The analog test is performed considering a reduced size of the array about 640 rows x 8 columns therefore it takes 80 frame acquisitions to analyze the full matrix Figure 1 shows how to do the analog characterization and which parts of the matrix are under test for each frame The MK_CLKA is the synchronization marker for the analog outputs and it works like its digital homologue see When En_AnaCol bit is set to 1 it appears at the end of each frame this signal is used to sample the analog July 2008 PHASE 1 User Manual v1 0 14 PHASE I channe
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