MIMOSA26 User Manual - IPHC
Contents
1. START i i o oa i i io NE U 1 LI LI H LI H Frame 0 1 Frame 1 1 Frame 573 i 1 Frame575 H Frame0 Frame 1 1 i Frame 573 1 1 Frame575 I 1 1 1 1 H H 1 1 1 MKD lo h 4 bo i 1 1 F LI T 1 1 1 La 1 Li LI 1 Pata diser Row Data discriRow1 tana aa Data diseri Rovv 575 DatadiscriFow0 DatadiscriRow1 OLOR DatadiciRowS78 D i I i re gt re a veu wi 4 b s NE ita gt i 1 edge of CLKD i H t edge of CLKD 1 edge of CLKD i i edge of CLKD I H H 1 I H 1 H H DOO E gt 1 I 1 a I 1 D 1 1 D i H I 1 H 1 H i T e Data T T T Data T T FK Data n T n FK Data T H H I H H 1 1 1 1 1 1 H 115248 edge of CLKD H 1 1 H 4 115248 edge of CLKD 1 1 H 11152 edge of CLKD 1 1 1 1152 edge at bp 1 1 1152 edge of dLKD 1 H NG 1152 edge of PLKD i gt 4 Pit gt I i 1 DO1 H 1 U D H D LI 1 ri 1 Li LI L L L L 1 n L L L L 1 i n Data 1 f 1 x Data 1 1 Data 1 i i 1 1 Data t 1 H 1 H 1 1 1 H 1 H i i i I 1 I 1 H I H I i 1 U I 1 1 1 I 1 LI 1 Li H ee Rnnnnnnpnnnnn T I P FU i I 1 i 1 1 I 1 I 1 LI U U H H U U u u H ng Figure 19 scanning automatic test of the Data discriminator En auto scan discri2. 1151 864 863 576 575 288 287 0 Digital READOUT ILVDSTx HS March 2011 Figure 8 Bias synthetic block diagram MIMOSA26 User Manual V 1 5 21 MIMOSA26 3 3 Setting the Readout Configuration Registers If the desired operating mode does not correspond to the default one set LINEPATO REG SEQUENCER PIX REG CONTROL PIX REG LINEPATI REG SEQUENCER SUZE REG HEADER REG CONTROL SUZE REG RO MODEO RO MODEI registers following the 82 3 5 82 3 7 82 3 8 82 3 9 82 3 10 82 3 11 82 3 12 82 3 13 82 3 14 34 Readout 3 4 1 Signal protocol After JT AG registers have been loaded the readout of MIMOSA26 can be initialized with following signal protocol e Start readout clock CLKL e Set SPEAK signal to 0 e Set START signal to 1 during 500 ns minimum The internal reset is created after 2 rising edge of CLKL After this reset CkDiv16 input clock with 1 16 ratio is generated e The readout controller starts at the first falling edge of CkDiv16 after START set to 0 Signal markers allow the readout monitoring and the data outputs analogue and digital sampling CLKA CLKD and MKD are running when readout controller starts CLKA is signal which is generated by logic OR between Read and Calib si
3. 0405 II 101 71 10 Discriminator output here unused e E e ES e S aa em Sem a a I T Figure 25 Test of the PLA March 2011 MIMOSA26 User Manual V 1 5 36 SH CONFIGURATION int stateout int statesource Sa scanlinetst Jii entstdatadisc SI test after mp SI Pattern Only Sr cptlinedisc X MUXOUTPUT Mo etat9l 15 0 T etatBl 15 0 T etatzl 15 0 e etatBl 15 0 e etatsi 15 0 MC etatdl 15 0 Ms etat3l 15 0 T etat2l 15 0 T etatll 15 0 MIMOSA26 H b n 3 Q bei o urce test pattern 2Zlines n H ode test ater mux ejej e LA qus qe y ye ys po yi po y3 pa ys pe er Joo ps po yor Yaz ps pa ps pe jer ps Qo poo yu yar yis yai 1 of the MUX states BA res o ele oo Q o 3 REX EE BAA ES 05 645 00500049 0053 0049 0059 Joo45 Joos9 00490055 0049 Jooss 0042 Joss Joo45 yooss p04s Jooss Jooas Jooss yoods 0052 yoo4s Jose yood9 0059 yoo4s Jooss yooas oo 00 9023 00300025 0039 60299035 Joozs J0039 6023 0035 Joozs yo039 0023 fo03s Joozs y0039 p02s fo0s foozs ose yoozs 0032 foozs Joo3s yoo29 0039 foo2s Jooss yooz oo 001910029 0019 0029 0019 0029 0019 0029 0019 0029 0019 0029 0019
4. Header0 Figure 10 Detail of the beginning of a data frame March 2011 MIMOSA26 User Manual V 1 5 25 MIMOSA26 Mode 40 MHz Mono channel clkrate 0 and dualchannel 0 The maximum number of data generated by the suppression of zeros is 278 x 16 bits for the output After this overflow the data frame will be truncated This mode 0 giving too little information is irrelevant but can be used as test only 0123 45 6 7 8 9 1011 12 13 14 15 Frequency cukp 40 MHz cikrate 0 T gt Dualchannel 0 C Statusinq150 gt 0 lt Data lengtho 139 0 lt Data length1 139 CLKD MDAC SO CL El ie Osn 9 A JN _ DO de _ __ 2222222222222 222222222222222222222222 222 3 T TIEN 5 ine 5 7 meta om ll i P 7 i 7 DO1 m Headerd 15 0 l l Headert 15 0 lt Framecpi 15 0 gt Framecp 31 16 p Data lengtho 3 Data length1 p lt StatusLine 15 0 gt lt State 15 0 P lt State 15 0 lt EE gt lt Trailer 0 15 0 Trailer 1 15 0 gt 0 1 j 15 0 in this diagram means 16 consecutive bits J datalengtho datalength1 Figure 11 Format of the output Data of MIMOSA 26 Mono Channel and 40 MHz Mode 40 MHz Dual channel clkrate 0 and dualchannel 1 The maximum number of data generated by the suppression of zeros is 282 x
5. Figure 17 discriminator test block diagram March 2011 MIMOSA26 User Manual V 1 5 30 MIMOSA26 Timing diagram CLKL rstline Cklatch Clkscan CLKL 8 Loadscan LE a sese CLKD MKD DOO sr IC LL ran er E E Bit 576 Bit577 Bit 1151 DO1 Scanning timing location Figure 18 timing diagram Sequence of the line reading The SCANLINETST of the CONTROL SUZE REG Register gives the row address into the frame For both modes the following bits of the CONTROL SUZE REG registers are set Value configuration Two modes are defined When En auto scan discri is set to 0 we select one row defined into SCANLINETST 0 to 23F When this mode is started at each frame the selected row is scanned the readout process is continuous To change the row address we define other scan line into SCANLINETST and generate a new START signal When En auto scan discri is set to 1 we select the row automatic scanning from line 0 to 575 and the process stops when last row is scanned see the Figure below but line 0 and line 573 are not scanned
6. LINEIPAT REG is set to 0 JTAG state machine is in the Test Logic Reset state JTAGID CODE instruction is selected Then the bias register has to be loaded The same for the RO MODEO RO MODEI CONTROL PIX REG CONTROL SUZE REG SEQUENCER PIX REG LINEOPAT REG LINEIPAT REG HEADER REG and DIS DISC registers if the running conditions differ from defaults Finally the readout can be performed either in normal mode or in test mode March 2011 MIMOSA26 User Manual V 1 5 19 MIMOSA26 32 Biasing MIMOSA26 The BIAS_DAC register has to be loaded before operating MIMOSA26 The 19 DACs constituting this register are built with the same 8 bits DAC current generator which has a 1 HA resolution Specific interfaces like current mirror for current sourcing or sinking and resistors for voltages customise each bias output The following table shows the downloaded codes which set the nominal bias Internal Simulation Resolution Range Experimental DAC Codey DacInternal Output Code Name Code current pA value Code VKIMO 64 100 100 1V 10 mV From 0 up to 2 55 V IPIX 32 50 50 50uA JIuA From 0 up to 255 uA IDIS2 20 32 32 SuA 156 nA From 0 up to 255 HA IDISI 20 32 32 10uA 312nA From 0 up to 255 HA VDISREF2 76 118 118 118V 10mV From 1 up to 1 5 V VDISREFIA 80 128 128 1 18V 250uV From 32 up to 32 mV 1 VDISREFIB 80 128 128 1
7. MIMOSA 26 User Manual Preliminary version Institut Pluridisciplinaire Hubert Curien IN2P3 CNRS 7 UdS Strasbourg France CEA Saclay DAPNIA SEDI March 2011 MIMOSA26 User Manual V 1 5 MIMOSA26 Document history MIMOSA26 chip Submitted November JAMS 035 Opto Version 576 x 1152 pixels 2008 March 2011 MIMOSA26 User Manual V 1 5 MIMOSA26 L_z 4 1 1 General description of EUDET CMOS pixel senger 4 L2 JIEGIFTAL PART SIZE ella 3 2 Control mH ees 6 2 1 lipidica 6 2 2 IHS 6 2 3 RK EE 7 2 3 1 Instruction Reperat 7 2 3 2 Lie 7 2 3 3 Boundary Scan Register a M 8 2 3 4 BIAS IDA GJ Ge ND rallenta 8 2 3 5 LINEPA TO REG Reset alleata 9 2 3 6 DOES DUS EE CU IM s shen has m t h dh one he 9 2 3 7 e E n iaioa 10 2 3 8 CONTROL PIX REG Regist f i ei i si 12 2 3 9 LINEPATI REG eebe xs nde rl 13 23 10 SEQUENCER SUZE REG pasim 14 23 41 HEADER EU gur ev v ni veten i 15 232 SUZE REG Refill 16 2313 RO EE 17 2 3 14 RO MODELI Register cos sht jes iste eeen gp bes s drodh c s dr Eit 17 23 13 BI PASSARE aironi teri 18 ct Rum MIMOSA 6 19 3 1 IC RR REI 19 32 aere MIMOSA nees 20 3 3 Setting the Readout Configuration Registers enen e ene e enen 22 si Riddle 22 3 5 Analogue and digital Diane 23 3 5 1 Normal mode data format E 23 3 5 2 EE 28 30 MIMOSA260 iolanda 33 3 6 1 Normal Reado t lia 33 3 6 2 earth eegene 34 3 6 3
8. 0 0 0 0 1 1 0 0 0 0 0 Figure 5 Simulation timing diagram for signals of SEQUENCER_PIX_REG 2 March 2011 MIMOSA26 User Manual V 1 5 11 MIMOSA26 2 3 8 CONTROL PIX REG Register The CONTROL PIX REG registers are 40 bits large they allow setting parameters of the readout controller These registers are reserved for sensor s debugging by the IPHC IRFU group A end user has to respect to the default values 39 36 NU Reserved Non se o SCS 3535 Sebai Selection bit of Tespa 0 June 3730 SelPad Selection bito Tesa 0 MK TexDsemi 29 20 RowMkLast Row number of the frame It depends of Normal mode the number of row readout mode matrix is 576 When the En_HalfMatrx mode is active the value is 0x013F otherwise 0x023F When the En_LineMarker mode is active add two rows at the end of matrix 19 10 RowMkd Selection parameter of row for digital Digital marker place is first row of marker MK Test D matrix during the readout RowMka Selection parameter of row for analogue analogue marker place is first row marker MK Test A of matrix during the readout March 2011 MIMOSA26 User Manual V 1 5 12 MIMOSA26 2 3 9 LINEPAT1 REG Register The LINEPATI REG register is 1152 bits large The purpose of this register is to emulate discriminators outputs rows in En LineMarker and Pattern Only modes When Pattern Only is active the values stored in the pixel matrix are ignored and the v
9. 0 March 2011 MIMOSA26 User Manual V 1 5 22 MIMOSA26 3 5 Analogue and digital Data Format Two Types of signal can be generated on analogue outputs e Normal pixel signal e Test signal In concern to digital outputs tyvo types of signal can be generated e Digital pixel signal after zero suppression processing e Test discriminator and test zero suppression logic Digital pixel signal by discriminator Test pattern used by zero suppression logic read to LINEPAT REG register MIMOSA26 uses the pads at the bottom edge for all its operations whatever is collecting data from the pixels using the pixels and the discriminators or in test mode reproducing at the outputs the pre programmed patterns All the digital signals for the synchronization and the programming of the chip are necessary for successful operation Analog outputs located on the top edge of the chip are not used for the normal operations The main purpose is the characterization of the pixels or the checking of the dead pixels Therefore measurements on these pads deal with normal pixel signals as well as test signals but they still require the synchronization and the markers and it is activated on demand by setting to 1 the EnTestAnalog bit in the RO MODEI1 register 3 5 1 Normal mode data format 3 5 1 4 Introduction This chip is the combination between MIMOSA 22 and SUZE 1 The inputs are the main clock the reset and an input synchronization START for initiali
10. 0029 0019 0029 0019 0029 0019 f0029 0019 0029 0019 0029 0019 0029 0019 0029 0019 00 9018 0008 yoo1s yo008 0013 fo009 0012 f0005 Jo012 0005 Jo01 2 0005 fo01 9 6005 fo019 0005 0019 0005 001 90005 0615s 0009 o01s f0009 6012 f0005 012 f0005 Jo01 2 0005 foo h 1000010002T0000 0009 0000 10009 10000 10009 0000 10009 0000 10009 0000 10009 0000 10009 1000010009 10000 0009 10000 0009 10000 0009 1000010009 1000010009 100001001 Em o o n ER E March 2011 To etat0i 15 0 fos to NET MT TIT EE 209 9519 9579 Oe Oo eres Jets 6 65 67 E TEE CLKD WO MKD ES DOO 1 0 11 1 o0j11 0 0000001 116 0 ep Unsed PAD m 9 c B o o n o4 DO1 unused Discriminator output here unused SS Fe State0 15 0 State1 15 0 Figure 26 Test of the MUX MIMOSA26 User Manual V 1 5 37 I A MODE NORMAL SI jsupinitmem gt J clkrateout SI dualchannelout FORMAT header Ja header Le trailer2 Le traileri M MODE TEST SI en scan SI Pattern Only SI debuttrame 1 cik 4 cptlinedisc amp do1 15 0 amp do2 15 0 Ja framecpt 31 0 MIMOSA26 mE a INNI CIAO PA II Ts er 81 COlxxxx 8009 OQOQIxxxx 0000 000700000003 E nml amp 0 OUTP UT 5 times clock E prirur s MKD DOO Unused DO1 110 110 110 110 411901l 1l 1L01 1l 0 11 Lo T1 o j1l1
11. 16 bits for each output After this overflow the data frame will be truncated 0123 4 5 6 7 8 9 1011 12 13 14 15 Frequency cLkp 40 MHz cikrate 0 T 0 Data lengtho lt 282 0 Data length1 lt 282 Dualchannel 1 CLKD A S MKD e TTT 0 1 i datalengtho DOO Header0 15 0 Framecpt 15 0 Data length0 StatusLine 15 0 State2 15 0 State 15 0 gt n Ge Trailer 0 15 0 DO1 Header1 15 0 Framecpt 31 16 Data length1 State 15 0 gt EE StatusLine 15 0 lt EEN Trailer 1 15 0 al SEN 0 1 j datalength1 15 0 in this diagram means 16 consecutive bits Figure 12 Format of the output Data of MIMOSA 26 Dual Channel and 40 MHz March 2011 MIMOSA26 User Manual V 1 5 26 MIMOSA26 Mode 80 MHz Mono channel cikrate 1 and dualchannel 0 The maximum number of data generated by the suppression of zeros is 564 x 16 bits for the output After this overflow the data frame will be truncated 0 1234 56 7 8 9 1011121314 15 Frequency cukp 80MHz clkrate 1 T Dualchannel 0 0 lt Data lengtho lt 282 Osns9 0 lt Data length1 282 CLKD A 7 E MKD EH DO Ee Dol A Hea
12. 5nsx H H H H H H H H H H i H H H i H 80 MHz i H H i H i H H H Hi Hi H H Hi H i Latch Las Pra ns ef mlrolofejfrjelslalsietalol DataLatch Po a rlololololololololololololol Figure 3 Example Generation of Latch Signal e Related timing with f x 80 MHz Read Calib Latch signals are used by the column readout circuitry A Baseline vs 491 531 25ns Cursor Baseline v 200ns Baseline 491 531 25ns Name v Cursor v 1 820ns 431 491 600ns F gt ck EI 141 EE E Sict Row Int Em nst S ES Clamping Tra Read o gt Latch F gt Calib det 64dns 491 680ns KEE 491 Y20ns mmu m e erem oat TT lt 200 ns I l e l l l l Figure 4 Simulation timing diagram for signals of SEQUENCER_PIX_REG 1 e This is readout sequence of the pixel and discriminator for 2 successive rows of matrix In the waveform the indexation of internal signal vectors is reversed compared with the MIMOSA26 functional view for example the signal Pwr_On 575 corresponds to the row at the top of matrix March 2011 MIMOS A26 User Manual V 1 5 10 MIMOSA26 431 50 ns 491 600ns 491 700ns 491 800ns Name v MA 300n5 491 400ns F Fa On E75 Ei Skt Row MES PI ES Fa Dag E Pur On 74 gt Set Row Int 574 T PE Ei Clamping 574 Ee Latch Lis cw 1
13. CLK A KS EnTestAnalogMk H fi SelAnaDriver 0 143 E MK CLK A Elie OutAnaDriver 7 0 Bn OutAnaDriver 7 Bir OutAnaDriver 6 Kr OutAnaDriver S ER OutAnaDriverH4 QutAnaDriver 3 Shp OutAnaDriver 2 A gt Out naDriver 1 G OutanaDriver 0 March 2011 Cursor v h 8000 00 0 8 values 1 38334 i 1 38334 j 1 38334 1 1 98334 f 1 38334 i 1 38334 1 1 38334 j 1 38334 j MIMOSA26 IL 7 138 0000 00000000 00000000 00000000 00000001 8000 00000000 00000000 00000000 00000000 Data Ana How Data Ana Row 0 becond Row a Vtesti Vtest2 Vesti Vtesta I 8 values First Row add id 2 04692v 4 B 2 04692V LA IS e 2 04692V I D L I A I I I Figure 16 Mode scan for analog output MIMOSA26 User Manual V 1 5 29 MIMOSA26 3 5 2 2 Transfer function of discriminator and pixel digital readout calibration This test readout mode allows obtaining the transfer function of discriminator and calibrating the digital readout Pixel discriminator Transfer function of discriminator During the test mode when EnTestDiscri bit is set to 1 in the RO MODEI register the pixel matrix is not connected to discriminators Instead of that one test level Vtest2 is connected to discriminator input to emulate pixel base line The Vtest2 voltage can be adj
14. DO1 March 2011 00 00000003 ee ACT Jese JI 1 qg gt et E Header1 frameCpt 15 0 nmi 15 0 Status0 Header2 frameCpt 31 16 Nml 2 31 16 Status1 Figure 29 Normal working mode Clkrate 20 Dualchannel 1 MIMOSA26 User Manual V 1 5 MIMOSA26 i i MODE NORMAL I jsupinitmem 1 21 cikrateout 1 SI dualchannelout 1 t FORMAT DAAA 5555 sm trailer2 4 4 trailer ep MODE TEST E en scan 0 es Pattern Only 1 ks debuttrame I ck uuu uuu uuu uuu nu uu 42 cptlinedisc Z A9 4 5 6 7 8 Se do1 15 0 000 xxx 8009 Jos Je Je do2 15 0 001 xxxx 0000 0019 0039 9 4 framecpt 31 0 000 gt 00000003 i 256 UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUL 0 9 0 0 8 3 2 0 0 0 0 0 Header1 frameCpt 15 0 Nml 2 15 0 Status0 Header2 frameCpt 31 16 Nml 2 15 0 I Status1 Figure 30 Normal working mode Clkrate 1 Dualchannel 1 March 2011 MIMOSA26 User Manual V 1 5 al MIMOSA26 3 6 3 Main Signal Specifications rerameter typical Value Notes TAG READOUT a SE ret ee gui SYNC Se ST Time Ze ns n Initialisation CMOS signal Starts LEN CT 1 edge on Irst CKRD sampling Input Za range 0 7 up to 1 2 V 7 up to 1 2 V Differential ij eS 10 90 for fully input dynamic range Fall time sns nS
15. Main Signal Speci i catlofis Pm 42 Bae SO ONE T EN 50 gt Glossary Abbreviations and acronyms tables vdcev sedi eneve dri dEr a Ren 51 March 2011 MIMOSA26 User Manual V 1 5 3 MIMOSA26 1 Introduction 11 General description of EUDET CMOS pixel sensor MIMOSA26 is the final sensor chip of EUDET JRA1 beam telescope for the ILC vertex detector studies Its architecture is based on the MIMOSA22 Monolithic Active Pixel Sensor MAPS with fast binary readout and on a prototype circuit named SUZEOI which performs integrated zero suppression The size of the chip is 13 7 mm x 21 5 mm and the sensor matrix is composed by 576x1152 pixels of 18 4 um pitch The pixel design is based on self biased diode radtol architecture The design process is Austria Mikrosysteme AMS C35B4 OPTO which uses 4 metal and 2 poly layers The thickness of the epitaxial layer is 14 um The design tools are CADENCE DFII 5 1 with DIVA ASSURA CALIBRE rules The chip has been submitted in an Engineering Run via CMP on 19 December 2008 In the EUDET beam telescope the hit rate is less than 5 hits image However MIMOSA26 is suited for charged particles detecting with density up to 10 hits cm s The design of the sensor is driven by the high readout frequency in order to keep the track multiplicity per frame at a low level It is done by read out pixel columns in parallel row by row The chip readout time is 115 2 us Each pixel includes an amplification and Correlat
16. are totally configurable by JTAG the header and the trailer of each data frame can be different The Table 1 see 82 3 11 shows the possible Header and Trailer values 3 5 1 5 Frame counter Frame counter is the number of frame since the chip was reset This counter 32 bits is reset to 0 when the maximum is reached FFFFFFFF in hexadecimal and continues to work The Frame counter when separated into 2 words is given in the Data line 0 Frame counter 0 with the LSB s and in the Data line 1 Frame counter 1 the MSB s March 2011 MIMOSA26 User Manual V 1 5 23 MIMOSA26 3 5 1 6 Data Length Data Length is the number of word of 16 bits of the useful data Data Length is written on 32 bits In the case of one data line the number of words is repeated 2 times The sum determines the real value of the useful data In the case of no hit during a frame Data Length 0 and Data Length 1 are set to zero 3 5 1 7 Useful data States Line State The useful data is the daisy chain of States Line and States The maximum number of the useful data bits sends during one frame is 570 words of 16 bits 9120 In some rare case the number of data generated by the suppression of zeros exceeds the maximum bits capable to be sent thus the data frame will be truncated The data are periodically sent at the beginning of each new frame and the number of bits which could be sent between two headers is variable and depends on the numbers of the words recorded
17. at last it is set to 0 2 3 14 RO MODE1 Register The RO MODEI registers are 8 bits large they allow selecting specific analogue mode of the chip ese sic configuration valle value ee i Reinitializes the frame counter to 0 6 EnTestAnalog Enable analog output 15 TJ EnAnaDriverScan Enable scan pixel mode 4 DisBufRef Disabletheinternalreference LO Select Internal Buffer 3 Emp Enable internal PLL OP 2 EnDiscriAOP LEnable the Power pulse Amplifier LO Normal mode March 2011 MIMOSA26 User Manual V 1 5 17 MIMOSA26 1 EnDiscriPwrSave Enable the discri power pulse mode Normal mode 0 EnTestDiscri Enable the discri test mode Normal mode 2 3 15 BYPASS Register The Bypass register consists of a single bit scan register It is selected when its code is loaded in the Instruction register during some actions on the BSR and when the Instruction register contains an undefined instruction March 2011 MIMOSA26 User Manual V 1 5 18 MIMOSA26 3 Running MIMOSA26 The following steps describe how to operate MIMOSA26 3 1 After reset On RSTB active low signal All BIAS registers are set to the default value i e 0 DIS DISC is set to 0 i e all columns are selected RO MODEO is set to 0 RO MODEI is set to 0 CONTROL PIX REG is set to 0 CONTROL SUZE REG is set to 0 SEQUENCER PIX REG is set to 0 SEQUENCER SUZE REG is set to 0 HEADER REG is set to 0 LINEOPAT REG is set to 0
18. gt bit and on DOJ is discri lt 576 gt bit During Read phase Vtest1 is selected in analogue outputs Sample before clamping Sample after clamping of And during Calib phase Vtest2 of Row0 Read Rovvo Calib is selected Figure 23 Test of the discriminator 1 2 MIMOSA26 User Manual V 1 5 35 MIMOSA26 Ws int stateout Test mode int statesource source test pattern 21lines int statetest Mode test discri int state write pattern SI auto scan discri 3a scanlinetst i entstdatadisc i test after mux i Pattern Only amp cptlinedisc 14 DS De a kre Da 20 pa ez 23 24 Ja BiLigneBit 53 0 Ccccccccc cC Cccccccc CCCC jCCCCCCCC CCCC jCCCCCCCC CCCC jcCCCCCCCC CCCCP jCCCCCCCC CCCCr jCCCCCCCC CCCCP jCCCCCCCC CCCCP jCCCCCCCC CCCCP jCCCCCCCC CCCC ccd amp BIOLigneBitj6s 0 xk OUTPUT CLKD MKD DOO DOT 3 MODE TEST Te p A 1 0 1 Figure 24 Test of the discriminator 2 2 im MODE TEST I en scan Li auto scan discri Es a scanlinetst i8 entstdatadisc m test after mux 1 Pattern Only m stgrl 2 U ig stgr2 2 0 DA TRY OY Olle oj me LA
19. register of MIMOSA26 is 5 bits long On reset it is set with the ID CODE instruction When it is read the 2 last significant bits are set with the markers specified by the standard the remaining bits contain the current instruction x x GD Jo 2 3 2 DEV ID Register The Device Identification register is implemented It is 32 bits long and has fixed value hardwired into the chip When selected by the ID_CODE instruction or after the fixed value is shifted via TDO the JTAG serial output of the chip MIMOSA26 ID CODE register value is M26 0x4D323601 Default value Code 31 0 ID CODE Device Identification register 4D323601 ASCII M 120 ae e 36 March 2011 MIMOSA26 User Manual V 1 5 7 MIMOSA26 2 3 3 Boundary Scan Register The Boundary Scan Register according with the Jtag instructions tests and set the IO pads The MIMOSA26 BSR is 10 bits long and allows the test of the following input and outputs pads 5 SPEAK mm SPEAK Active Readout Marker amp lk p fex Imm JOE CMOS Clock E LVDS CLKL n CLKP p CIkLvds Resulting CMOS signal after LVDS Receiver EET No Used Ee I e e E o muri Owput pd Readout TestPad 2 3 4 BIAS DAC Register The BIAS_DAC register is 152 bit wide it sets simultaneously the 19 DAC registers As show bellow these 8 bit DACs set voltage and current bias After reset the register is set to 0 a value which fixes the minimum power consumptio
20. serial output0 AAAA EEN Synchronisation trailer serial output Aaaa For both modes according to the register DUALCHANNEL the header and the trailer of each data frame can be different The following table shows the possible Header and the Trailer which ensure the unicity in the data frame The unicity is guaranteed without the Frame counter Bits 0 3 in hexa 4 1 Va A nw un Possible Header or Trailer paj paj PX PST PST pe P lt paj paj PX PST pej did Anm OO alw Sleoi Al A MW A DW Table 1 possible Header and Trailer for mode 0 and 1 to ensure unicity or mode 2 with 32 bits March 2011 MIMOSA26 User Manual V 1 5 15 MIMOSA26 2 3 12 CONTROL SUZE REG Register The CONTROL SUZE REG registers are 48 bits large they allow setting parameters of the readout controller for SUZE We suggest an end user to only use default values except for data stream output parameters Bit Name NU E cp ion 42 40 SelPad3 Selection bit of Test3Pad i Debugging reserved for IPHC Cf 3 5 2 2 En_auto_scan_discri Enable mode scan test discriminators all matrix Test_after_mux Enable mode scan test for multiplexer of Debugging reserved for IPHC SUZE ped entestdatadisc Enable mode scan test discriminators Debugging reserved for IPHC Cf 83 5 22 35 26 RowLastSuze Row number of the frame It depends of 023F Normal mode the number of row readout mode matrix is 576 Wh
21. sns Simulated With Zjoga 2 100 Ohm and 2 5pF Current Gn Bawon pom 8 338 Transconductance gain Tse P 00000000 I Output Current Range 2323m amp JT Input Dynamicrange 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRise time i Analogue Falltime 0 j Driver Bandwiah dd Qua conte LT OI Note 1 The differential current output buffer can be modeled as an ideal current source Its performances in terms of raising and falling times are limited by its load s time constant Rjoaa x Cioad Note 2 Simple source follower March 2011 MIMOSA26 User Manual V 1 5 42 MIMOSA26 4 Pad Ring The pad ring of MIMOSA26 is build with Pads full custom designed for some of the analogue signals and power supplies Pads from the AMS library for the digital signals and power supplies March 2011 MIMOSA26 User Manual V 1 5 43 4 1 MIMOSA26 Pad Ring and Floor Plan View 234 215 LI Test pads Pixels Array 1152 Columns 576 Rows e erbe pusbe 4 Memory Blocks March 2011 MIMOSA26 User Manual V 1 5 44 MIMOSA26 4 2 Pad List The bonding of the povver supply pads specified in red colour is mandatory Pad 6 vdda Analogue power LAVDDSALLP Powr 9 VDiscriReflD VDiscriRefl Bank D bidir test pad d APRIO
22. 1 March 2011 MIMOSA26 User Manual V 1 5 3l MIMOSA26 3 5 2 3 PLA test structure The mode is reserved for IPHC group 3 5 2 4 SUZE multiplexer test The mode is reserved for IPHC group March 2011 MIMOSA26 User Manual V 1 5 32 MIMOSA26 3 6 MIMOSA26 Chronograms The following chronograms describe typical access to the chip Reset JTAG download sequence and then the readout 3 6 1 Normal Readout 3 Baseline 769us Name v Cursor v x e 100us n e N poous A poous 8 700us e 3 Pet CLKL 9 RD TCK 1 RENE i 0 M Ee aa ea Fe START ov Lf Calib I A Latch WE LastRow H gt CLK A 0 2 AH dntinuous OutanaDriver 1 1 96425 i 13 furr lt ntinuous QutAnaDriver Ef 96425 j 2 04839V 2 04839V ay Successive row readouts Figure 20 Data readout mode simulation timing diagram e Reset Jtag access A rst row readout This figure shows the beginning of typical data readout mode After Reset and JTAG setting one can see the initialisation phase of the readout of the first pixel row March 2011 MIMOSA26 User Manual V 1 5 33 MIMOSA26 3 6 2 Readout synchronisation The data sequencer pix reg is loaded to a state machine Readout Controller After 2 rise edge clock of CIKL when START signal is rising the internal reset SeqRstB signal is generated 3U ZULY al AVUN 3U BULL KR GO rpm R
23. 18 V 250 nV From 32 up to 32 mV 1 VDISREFIC 80 128 128 1 18 V 250 nV From 32 up to 32 mV 1 VDISREFID 80 128 128 1 18V 250uV From 32 up to 32 mV 1 IAnaBUF 32 50 50 500 HA 10 uA From 0 up to 255 pA VTEST2 76 118 J118 118V 10mV From 1 up to 1 5 V VTESTI 80 128 128 1 18 V 250pV From 32 up to 32 mV 1 ILVDS 20 32 32 TUA 218 nA From 0 up to 255 uA ILVDSTX 28 40 40 40uA lpA From 0 up to 255 pA IDis2PwrS A 10 10 100nA J10nA From 0 up to 255 pA IDis1PwrS A 10 10 100 nA 10nA From 0 up to 255 pA IBufBias A 10 10 10uA JluA From 0 up to 255 uA IPwrSWBias A 10 10 10pA JluA From 0 up to 255 pA VDISCLP 64 100 100 2 1V 10mV From 1 2 up to 3 2 V 1 Referenced with respect to IVDREF2 The threshold voltage of the discriminators AVth is defined as Vrefl Vref2 Vref1 Vref2 AVth March 2011 MIMOSA26 User Manual V 1 5 20 MIMOSA26 IAnaBUFI GE IPIX GJ VTESTI VTEST2 VDISREF2 VDISREF1A VDISREF1B VDISREF1C VDISREF1D VDISCLP BUFBIAS PWRSWBIAS IDIS1 IDIS2 IDIPVVRS ID2PWRS ILVDSRx E VDiscriRef1D PAD VDiscriCip PAD Analogue READOUT VDiseriRef2A VDiscriRef2B VDiscriRef VDiscriRef2D P xel A rra NTEST2 VDiscriRef2B VDiscriRef2C VDiscriRef2D VDiscriRef1A VDiscriRef1B VDiscriRef1C VDiscriRef1D p P
24. 8 dcklatchhit Synchronization signal every line for 3000 CkLatch bi v II UE memory management Priority Look Ahead 95 80 dckreadpix5ns Synchronization signal 6 times every line 82aa CkReadPix5ns for memory management shifted of 5 ns compared with CkReadpix for memory management memory management SUZE part Priority Look Ahead management e Related timing with fax 80 MHz Theses signals are used by zero suppression circuit 492 320ns 492 60ns ai and uke adie an ns Name Cursor v j492 280ns em A i ck KY Latch E RstLine li CkReadPix El KS CkMemLatch gt RstPix gt CkReadPixMux KS CkLatchMem gt CkReadPixSns cr pes bet Fi Ft re LI ria EE E Ls 1 1 1 0 D 0 0 0 0 1 1 0 i PERMET EISES ESET CIO UO CERERE EECH P Cklateh E E EET LI RstTrame m e F E reni Ce debuts ii debutigne RENE RE QN EE UE E p qs pee muy quur et Ei adline 10 0 a2 0 i n lt 200 ns Figure 7 Simulation timing diagram for signals of SEQUENCER_SUZE_REG March 2011 MIMOS A26 User Manual V 1 5 14 MIMOSA26 2 3 11 HEADER REG The register called Header Reg includes 4 registers of 16 bits as shown below Basic configuration valve value 63 48 Synchronisation header for serial output0 5555 47 32 Synchronisation header for serial output1 5555 31 16 Synchronisation trailer
25. 9 states are kept PLA Priority Look Asynchronous way to access from a hit to another hit The next one has the priority Ahead Word or locution Description or explanation Frame The frame is a set of line here compound of MaxAdrRow lines Line duration In default mode 200 ns i e 16 times the period of the main clock 80 MHz 12 5 ns Frame duration duration line x the content of the cycleMax register March 2011 MIMOSA26 User Manual V 1 5 5
26. ES id ooo DoDD 355909900 ge x x BERE 2 n E o9 Figure 1 MIMOSA26 functional view Does not correspond to the floorplan neither for the core neither for the pad ring March 2011 MIMOSA26 User Manual V 1 5 4 MIMOSA26 12 DIGITAL PART SUZE The following synoptic shows the implementation of SUZE into MIMOSA 26 Line of pixels Config Registers TABLE of Configuration Config Registers Registers Config Registers Address of Line CLKL Synchronization Line signals RSTB Synchronization Frame signals Control signals Test signals Test Structure START Figure 2 top view implementation of SUZE in MIMOSA 26 This digital part manages sequentially each line for the whole frame composed of 576 lines of 1152 columns The main sequencer gives to the structure the address of lines and all synchronisations and controls signals A JTAG controller brings the configuration information Table of configurations registers A test structure simulates a matrix of pixel in order to check the functions of SUZE These debugging tests are reserved for the IPHC IRFU group March 2011 MIMOSA26 User Manual V 1 5 5 MIMOSA26 2 Control Interface 2 1 Introduction The control interface of MIMOSA26 complies with Boundary Scan JTAG IEEE 1149 1 Rev1999 standard It allows the access to the internal registers of the chip like the bias Register and the different registers control On Power On R
27. LinePatLOReg Emulate discriminators AAAAAA AAAAAAAA AAAAAAAA AAAAAA TOWS AA 1 Example of pattern used in simulation In MIMOSA26 the LinePatLOReg lt 0 gt is on the left hand side while LinePatLOReg lt 1151 gt is on the right hand side 2 3 6 DIS DISCRI Register The DIS_DISCRI register is 1152 bits large The purpose of this register is to disable the discriminator on a specific column if it is noisy by gating Latch signal and setting the output discriminator at 0 The default value of the DIS_DISCRI register is 0 it means that all discriminators are activated Setting a bit to 1 disables the corresponding discriminator In MIMOSA26 the DisableLatch lt 0 gt is on the left hand side while DisableLatch lt 1151 gt is on the right hand side 0 Lsb 1151 Msb DisableLatch lt 0 gt DisableLatch lt 1151 gt March 2011 MIMOSA26 User Manual V 1 5 9 MIMOSA26 2 3 7 SEQUENCER PIX REG Register The SEQUENCER_PIX_REG registers are 128 bits large this register contains all parameters to generate readout pixel and discriminator sequence Bit Bit Name Purpose Basic configuration Signal Name value Code Slt Row Int 127 112 DataRdPix Connect pixel output to common column FFFF Slct Row Int 111 96 Set reference voltage for diode Activate power supply for pixel Example Generation of Latch Signal 7 n T A 7 160n 7 S a n gt i 0 i 1 i 2 i 3 i 4 i 5 i 6 i 7 8 9 i A i B i C i D i E i F i 0 12
28. P_ AlO0Ohm 30 NotConnected G 32 NotComeced S S G 35 NotComeced _ 37 NotComeced S9 NotComeced 4i NotComeced y March 2011 MIMOSA26 User Manual V 1 5 45 MIMOSA26 Not Connected O Not Connected O Not Connected 164 I Not Connected 66 NotConnected 68 NotComected Glod Digital ground JONDALLE mer 76 vdd latch Digital latch power VDD3ALLP Power 80 gnd latch Dram latch ground GND3ALLP Power 86 gnda Analogue ground LAGONDALLE 89 gnda Analogue ground LAONDALLE Powr 90 gnda Analogue ground LAONDALLE Powr 96 vdda Analogue power LANDDALLE Powr 98 vdda Analogue power LANDIDDALLE Power 99 vdda Analogue power LANDDALLE Powr March 2011 MIMOSA26 User Manual V 1 5 46 48 49 50 51 52 53 54 55 56 57 58 59 61 MIMOSA26 Digital memory ground GND3ALLP Digital memory ground GND3ALLP 111 vdd mem Digital memory power VDD3ALLP Power 112 vdd mem Digital memory power VDD3ALLP Power 113 vdd mem Digital memory power VDD3ALLP Power vdd mem Digital memory power VDD3ALLP Power 114 116 117 118J nd Digital ground JGNDSALLP Power 1 119 Not Connected 120 121 122 Data output channel 1 LVDS TX DOLVDS DOI p Data output channel 1 LVDS TX DOL
29. VDS Not Connected o Digital ground AGND3ALLP Not Connecte R gnd d N d Not Connected O Not Connected O Not Connected ll O 130 Not Connected Not Connected o O 137 Not Connected Da March 2011 MIMOS A26 User Manual V 1 5 47 MIMOSA26 169 gnd Digital ground GND3ALLP Power 170 CS Chip select BT2P DO 3 state 2mA 171 gnd Digital ground GND3ALLP Power 189 gnda Analogue ground AGND3ALLP Power 209 210 Pad Name Description Cel pe 211 CLKPLL p PLL output clock LVDS TX DOLVDS Digital LVDS pad power VDD3ALLP March 2011 MIMOSA26 User Manual V 1 5 48 MIMOSA26 Pad ring segment 3 Pad Name Description Ca rop 215 Not Connected fe ooo O 217 NotComected ooo o 219 NotComected III O 221 Not Connected o T O 223 Not Connected 225 Not Connected IT 227 Not Connected TTT Sr ro rr E EE 1 The buffer could be disable by the bit name DisBufRef in the RO_MODEI Register see 2 3 14 consequently the pad can be used as an injection point March 2011 MIMOSA26 User Manual V 1 5 49 MIMOSA26 4 Index of the figures Figure 1 MIMOSA2 6 functional View e pisi ipee i a aoe ieee 4 Figure 2 top view implementation of SUZE in MIMOSA 26 i 5 Figure 3 SUZE block diagram rara Erreur Signet non d fini Nj PLA Block Cia e
30. alue of LINEPATI REG is sent to the output This is a test mode which emulates the digital pixel response with the contents programmed into the LINEPATO REG register in order to verify the digital processing The pattern is alternated with the contents of the LINEPATI REG In the En LineMarker mode it adds two rows at the end of matrix for a readout chip and the LINEPATLI REG register is read to emulate the discriminators outputs of these two supplementary rows Bit Bit Name Purpose Basic configuration value Code 0 1151 LinePatL1Reg Emulate discriminators 555555 55555555 55555555 55555555 TOWS 1 Example of pattern used in simulation In MIMOSA26 the LinePatL1Reg 0 is on the left hand side while LinePatLIReg 1151 is on the right hand side With Linel DAT REG together these two signals will form the elements of the simulated frame given to SUZE part Rue pupa o 025 Row 0 Row 1 Row0 Row 1 x times Row 575 Figure 6 Generation of the test frame pattern March 2011 MIMOSA26 User Manual V 1 5 13 MIMOSA26 2 3 10 SEQUENCER SUZE REG The SEQUENCER SUZE REG registers are 160 bits large this register contains all parameters to generate readout zero suppression SUZE sequence Bit Bit Name Purpose Basic Signal Name configuration value Code 159 144 dckreadpixmux Sample signal for multiplexer after 0555 CkReadPixMux peel ere 143 12
31. der0 15 0 Headeri 15 0 gt lt Framecpt 15 0 gt lt Framecpt 1 16 Data lengtho P4 Data length1 gt StatusLine 15 0 gt lt State 15 0 gt lt State 15 0 gt cx Trailer 0 15 0 gt lt Trailer 1 15 0 0 1 j 15 0 in this diagram means 16 consecutive bits J datalengtho datalength1 Figure 13 Format of the output Data of MIMOSA 26 Mono Channel and 80 MHz Mode SO MHz dualchannel cikrate 1 and dualchannel 1 The maximum number of data generated by the suppression of zeros is 570 x 16 bits for each output After this overflow the data frame will be truncated 0 1234 5 6 7 8 9 1011 12 13 14 15 Frequency cikp 80 MHz clkrate 1 T Dualchannel 1 0 lt Data length0 lt 570 0 lt n lt 9 0 lt Data length1 lt 570 CLKD H MKD DOO Header0 15 0 Framecpi 1 5 0 Data length0 StatusLine 15 0 State 15 0 State 15 0 gt tt lt Trailer 0 15 0 DO1 i Headerij15 0 j l Framecpi 31 16 Datalengtht gt lt State150 gt C StatusLine 15 0 gt GE D Trailer 1150 gt 0 i datalength1 15 0 in this diagram means 16 consecutive bits Figure 14 Format of the output data Mode 80 MHz dual channel March 2011 MIMOSA26 User Manual V 1 5 ZI 3 5 2 Test mode 3 52 1 Analogue outputs Normal pixel signal When EnT
32. during the last frame Each data lines have the same number of bits Consequently Data Length 0 and Data Length 1 are the same States Line and State have exactly the same meaning whatever the selected mode The number of words sent in a data frame depends of the number of hits If the number of words for the two data lines is odd the last Status of Data line 1 is false This operating way allows having the same number of bits Data length in the both DOO and DOI in every case During the treatment of the line we consider the first word of 16 bits like a status line n following of n states and this operation is done several times until the end of the communication We propose to detect this false state case number of words odd to count the number of words of 16 bits for each new line If a last word considered like a status line is the last word counted as the total number of words Data Length then it is a false word that to be ignored In the following example the data length is exactly the same but the total number of words can be odd or even Header1 15 0 Frame cpt Data length Status Line 0007 0002 0003 DO 16 bits 0400 AAAA 0000 DO 16 bits DO 16 bits IER E DAAA 0000 ong 0100 xxxx AAAA 10000 DAAA UU WIR UJUU 1002 usu AAAS youuu 2 Data length 0006 0200 AAAA 0000 DO 16 bits False Status Line States Line contains the address of the line which is hi
33. eadout of matrix starts E gt Seafotb 1 OP dab B dion T HE did h Pa Pa ukh 4e atune Lre Dien Lr Cibi Lor Rata F Onanas Ko Olina ko Ck eadPoSes EI When Sloadb signal is rising the state machine of Readout Controller 1 generates usefull signals for pixel and discriminator readout After the end of START signal When the first fall edge clock of CKDiv16 arrived the sequence of sequencer pix reg The data sequencer suze reg is When Sloadb signal is rising the state is aciived tor state Maohie Readout loaded to a state machine Readout machine of Readout Controller 2 generates Controller during the low level period of Controller usefull signals for zero suppression algorithm SLoadb signal Figure 21 zoom on the readout start simulation timing diagram After a latency of 5 CkDiv16 cycles readout of matrix starts EISE Pattern Only 1 En scan 0 dualchannelout 1 and clkrateout 1 bat soon pe D ns ba 200n jaan anons 31 Ons n Data of Row0 after processing is sampled by CkLatch signal befor the memory managment processing 00000003 40000000 0000099 MKD is shifted of 4 rising edge of CIkL to debuttrame signal MKD signal is set during 4 clock s rising edges of CLKD Multiplexer processing Pdl Analog processin PLA processing of Memory managment Sample data discri Row0 i E 0 j Pata Discri Row O data discri RowO data disc
34. ed Double Sampling CDS and each end of column is equipped with a discriminator After analogue to digital conversion digital signals pass through the zero suppression circuits The digital signals are processed in parallel on 18 banks then arranged and stored in a memory row by row Two memories banks have been implemented in the sensor to perform read and write operations simultaneously see Figure 1 MIMOSA26 functional view Analog Supplies vdda gnd 171eAJgeuyino lt 0 gt J8Aligeuyino gnd vdd v clp lt 2 Digital Supplies M 2 P T j HI i 2 8 Gj E e Hj E E t E Ji 5 SH 3 E Ef S sls 8 3 sl O lij O ol ni j Test d H Pads 4 VDiscriCip Venten ag Jop VDiscriRef1A 4 VDiscriRef1B E LA LL ELEC LA VDiscriRef1C ee ee I O e ELA CLA CLA VDiscriRef1D LINEPAT1 REG Register lt 0 1151 gt VDiscriRef2A 5 Priority Look Ahead algorithm PLA VDiscriRef2B PLA 0 PLA 1 PLA 17 VDiscriRef2C Gene N states N states VDiscriRef2D 7 Selection of M states among 18xN states for each row test J E Memory Management Vtest Memory with M states storage and serial transmission Power Supplies BSR JRoModeoORoMode1 i Pie S PLL CMOS Signals LVDS Signals TEMP JTAG Controller il Analogue Signals l a Sg x g bot vag ec 5ocac yeeo x al Ber E FEEFEE gg99282 5 S
35. en the En HalfMatrx mode is active the value is 0x013F otherwise 0x023F When the En_LineMarker mode is active add two rows at the end of matrix 25 16 ScanLineTst Selection parameter of row for digital Digital marker place is first row 3 3 3 3 En_scan Enable mode scan test Debugging reserved for IPHC Cf 3 5 2 2 aj of matrix during the readout dualchannelout Determines the data stream on the Cf explanation of the data stream Di FE I RE clkrateout Determines the clock rate of the outputs Cf explanation of the data stream Eo FE eege jsupinitmem Authorizes the initialization test of the 1 NN e I BE LI sickmodgue Diseriminator switched ONO o des Cr fe multiplexors configuration 0 1 R6 foga m TT des dm 9 dei Dm DT The internal following signals can be selected with SelPad3 and SelPad4 bits SelPad3 Tst3Pad SelPad4 Tst4Pad Purpose o o cklatchhit Cf sequencer SUZE reg debutligne 1 ckltchhitmem rstline 12 ckmemlatch o debuttrame 11 9 9 8 7 6 15 14 13 12 rsttrame ckreadpixsns 1 rst_frame S ekreadpixmax rstpix 6 an synmux Main clock divided by 8 7 segrstb March 2011 MIMOSA26 User Manual V 1 5 16 MIMOSA26 Data stream output clkrateout dualchannelout Description The data are sampled by the The data stream is output on data line 1 frequency output clock 40 MHz on
36. eset an internal reset for the control interface is generated The finite state machine of the Test Access Port TAP of the controller enters in the Test Logic Reset state and the ID register is selected MIMOSA26 has been designed in order to be fully adjustable via the control interface Nevertheless several voltages level can be set either via the control interface or via a pad 2 2 JTAG Instruction Set The Instruction Register of the JTAG controller is loaded with the code of the desired operation to perform or with the code of the desired data register to access PNUD La JDATAREGH N2 IB A ATAREGI2Z JI NG Leo J J J DATAREGI3 JI 1 Instruction codes implemented but not the corresponding registers To be fixed in the next version March 2011 MIMOSA26 User Manual V 1 5 6 2 3 JTAG Register Set JT AG registers are implemented with a Capture Shift register and an Update register JTAG standard imposes that the last significant bit of a register is downloaded shifted first DEV ID 3 ROny PO LCONTROLER p10b REGI 312 lrony fd NUI NU3 lo Notimplemented For future use ROMODEI HE RW__ Previous value shifted out during write OJ RO_ MODEO 8 Previous value shifted out during write 2 3 1 Instruction Register The Instruction register is a part of the Test Access Port Controller defined by the IEEE 1149 1 standard The Instruction
37. estAnalog bit is set to 1 in the RO MODEI register the rightmost 8 columns of pixels are connected to the analog outputs via a voltage follower and the signal is available on the pads To start the analog test the EnAnaDriverScan must be set to 1 in the RO MODEI The scanning of the matrix now starts and stripes of 8 pixels are connected to the analog output The analog test is performed considering a reduced size of the array about 576 rows x 8 columns therefore it takes 144 frame acquisitions to analyze the full matrix Figure 26 shows how to do the analog characterization and which parts of the matrix are under test for each frame The MKA is the synchronization marker for the analog outputs see When EnTestAnalog bit is set to l it appears at the end of each frame this signal is used to sample the analog channel of the new frame on the next raising edge of CLKA Further when the EnAnaDriverScan must be set to 1 this marker appears at the end of the frame for each submatrix LO co N ST Z Z cb E E D bal Be LL LL Frame N 2 Frame N 1 L575 Figure 15 Analog characterization of the pixel The matrix is divided in stripes of 8 columns and fully scanned at each frame then swapped with the next block of 8 columns at right and so on until all the columns are analyzed March 2011 MIMOSA26 User Manual V 1 5 28 Baseline v 1 E Cursor Baseline v 400ns Name v E gt LastCol i
38. gnals When SPEAK signal is active marker of synchronisation for analogue outputs is generated on MKA pad Marker of synchronisation for digital outputs is generated on MKD pad this signal is shifted of 4 rising edge of CLKL to debuttrame signal MKD is set during 4 clock s rising edges of CLKD and is not depended of signal SPEAK 3 4 2 Successive frames and resynchronisation Successive pixel frames are read until the readout clock is stopped A frame resynchronisation can be performed at any time by setting up the START token again I I I I I Previous frame i Current frame i Next frame i i Last frame i gt lt gt lt gt gt i 1 i 1 LastRow 1 i i SPEAK iE J t i I I LastRow LastRow MKA MODE SPEAK 0 MKA MODE SPEAK funt IN i Calit I i i i I i I i i i I Read Figure 9 Successive frames and resynchronization timing diagram SPEAK signal allows to generate markers signals which are used by DAQ When SPEAK signal is set to 1 during the current frame analogue marker appears on MKA pad during next frame In the MODE SPEAK 0 the MKA marker corresponds to last row of the frame In the MODE SPEAK I MKA signal corresponds to a sampling clock for analogue outputs data same as CLKA which starts at the first row of frame When SPEAK signal is set to 0 MKA is set to
39. inning of data rane 25 Figure 22 Format of the output Data of MIMOSA 26 Mono Channel and 40 MHZ 26 Figure 23 Format of the output Data of MIMOSA 26 Dual Channel and 40 MHZ 26 Figure 24 Format of the output Data of MIMOSA 26 Mono Channel and 80 MHz 27 Figure 25 Format of the data Mode SO MHz dual channel 27 Figure 26 Analog characterization of the pixel ue operi rettet dt te eR M papse edem dt 28 Figure 27 Mode scan for analog output uuu Does sone trag aeter totos e 29 Figure 28 discriminator test block diagram iii 30 Figure 29 timing diagram Sequence of the Ime reading ur ina 31 Figure 30 scanning automatic test of the Data discriminator En auto scan discri 1 31 Figure 31 PLA test structure block diagram eese Erreur Signet non d fini Figure 32 PLA Test timing diagram na essence et ek ee In ipe b Sua lar e taedia Erreur Signet non d fini Figure 33 Format of the PLA word Tests Erreur Signet non d fini Figure 34 MUX test structure block diagram eese Erreur Signet non d fini Figure 35 Format of th MUX word Test Erreur Signet non d fini Figure 36 Data readout mode simulation timing diagram sese 33 Figure 37 zoom on the readout start simulation timing diagram eee 34 Figure 38 Pipeline of the readout processi
40. ly Data line O stay to low level The data stream is output on both data line 0 and 1 The data are sampled by the The data stream is output on data line 1 frequency output clock 80 MHz only Data line 0 stay to low level The data stream is output on both data line O and 1 2 3 13 RO MODEO Register The RO MODEO registers are 8 bits large they allow the user to select specific digital mode of the chip Basic configuration value _ AZ VTEST shift register selected Lie DisLVDS Disable LVDS and active clock CMOS 0 LVDS selected En LineMarker Add two rows at the end of matrix for a chip Readout Normal mode The LINEPAT REG register is selected to emulate discriminators outputs For analogue outputs the 2 Test Levels VTESTI and VTEST2 are selected which emulate a pixel output MODE SPEAK Select Marker signal or Readout Clock for digital and Marker signal active INL he MK CEKA MK CLD pato ENS 2 Pattern_Only Test Mode Select LINEPAT_REG to emulate Normal mode Enable external START input synchronisation pee 3 1 EN NN Enable Jtag START input synchronisation EDT 2 1 The minimum wide of asynchronous external START signal is 500 ns and this signal is active at high level 2 When En ExtStart is disabled it s possible to generate internal START by accessing JTAG Start bit JTAG_ Start signal is realized by three JT AG access First step this bit is set to 0 second step it is set to 1 and
41. n of the circuit The current values of the DACs are read while the new values are downloaded during the access to the register An image of the value of each DAC can be measured on its corresponding test pad DAC ft DAC Internal DAC purpose Corresponding da Name ve Pad Vtest 71 64 DACS8 IVTST2 I Test Level emulates a pixel output 63 56 DAC7 JIVISTI DEM 0 39 3 DAC4 ID2PWRS Discriminaorbias2 modelowconsp 31 24 DAC3 IDIPWRS Discriminatorbias 1 mode low consp March 2011 MIMOSA26 User Manual V 1 5 8 MIMOSA26 2 3 5 LINEPATO REG Register The LINEPATO REG register is 1152 bits large The purpose of this register is to emulate discriminators outputs rows in En LineMarker and Pattern Only modes When Pattern Only is active the values stored in the pixel matrix are ignored and the value of LINEPATO REG is sent to the output This is a test mode which emulates the digital pixel response with the contents programmed into the LINEPATO REG register in order to verify the digital processing The pattern is alternated with the contents of the LINEPATI REG In the En LineMarker mode it adds two rows at the end of matrix for a readout chip and the LINEPATLO REG register is read to emulate the discriminators outputs of these two supplementary rows After the initialisation phase reset this register is preset to 0 Bit Bit Name Purpose Basic configuration value Code 0 1151
42. ng from analog to memory part simulation timing diagram SR 34 Figure 39 Test of the discriminator Li 35 Figure 40 Test of the discriminator 2 2 sirena 36 Fig re 41 Test of the PLA g va r alicell 36 Fig re 42 Test of the MPA lecca 37 Figure 43 Normal working mode Clkrate 0 Dualchannel e 38 Figure 44 Normal working mode Clkrate 1 Dualchannel U N 39 Figure 45 Normal working mode Clkrate 0 Dualchannel 1 eee 40 Figure 46 Normal working mode Clkrate 1 Dualchannel cl al March 2011 MIMOSA26 User Manual V 1 5 50 MIMOSA26 5 Glossary Abbreviations and acronyms tables Abbreviation f Meaning Description or acronym ETU Elementary Time 1 1 Unit ETU Itimeclock 12 5ns main _chip _ frequency 80MHz SUZE Suppression of Zeroes AD Address D Il Data TCK Test clock Cf JTAG interface IEEE 1149 TMS Test Cf JTAG interface IEEE 1149 Management System TDI Test Data Input Cf JTAG interface IEEE 1149 TDO Test Data Output ff Cf JTAG interface IEEE 1149 FIFO Memory First In first Out LVDS Low voltage differential signalling PLA Priority Look Asynchronous way to access from a hit to another hit The next one has the priority Ahead MUX Multiplexer Structure that catches only nine groups of pixels among 6 x 18 groups The first
43. o 11oI1410 1 11011 S B T 5 e 85 T 86 A tr A Db Header1 Header2 Figure 27 Normal working mode Clkrate 0 Dualchannel 0 March 2011 MIMOSA26 User Manual V 1 5 38 MIMOSA26 m MODE NORMAL 21 jsupinitmem 1 SI clkrateout 1 dualchannelout 0 cd FORMAT tm header2 DAAA D header 5555 Fe trailer2 AAA a Fe traileri AAAA g MODE TEST pa SI en scan SE Pattern Only 1 debuttrame REGA jii 92 cptlinedisc CET CT SS Gs a Ce 1 0 Sa do1 15 0 Lass 8009 Sa do2 15 0 zxxx 0 000 Sa framecpt 31 0 00000003 amp nml 8 0 456 ie OUTPUT 5 times dlock CLKD E MKD et D SST DOT DD ake uice uu di n LI noli 1 H K 5 KO 0 Ko XK SEN PL 1 0 E KT 0 a Header2 Cptframe 15 0 Cptframe 31 16 nml15 0 nml15 0 I Figure 28 Normal working mode Clkrate 1 Dualchannel 0 March 2011 MIMOSA26 User Manual V 1 5 39 HO MODE NORMAL 3 jsupinitmem 1 clkrateout SI dualchannelout AX FORMAT SI Pattern Only II debuttrame I cik i DZ cptlinedisc e dol 15 0 Fe do2 15 0 MIMOSA26 e I I A I I I O0 xxxx 8009 0009 0029 Diruxxx 0 CI 0015 0035 ES framecpt 31 0 amp nmi 9 0 sx OUTPUT CLKD MKD DOO
44. rat lara Erreur Signet non d fini Figure 3 format of the PLA results aget se moder e con Pesca e Erreur Signet non d fini Figure 6 Synchronization signals for PLA timing diagram Erreur Signet non d fini Figure 7 Multiplexor top view eese nennen Erreur Signet non d fini Figure 8 Synchronization signals for MUX 6 x 9 gt 9 top view Erreur Signet non d fini Figure 9 Module 6 x 9 VIP Erreur Signet non d fini Figure 10 Module 6 x 9 gt ART Erreur Signet non d fini Figure 11 format or the Mux Tesla Erreur Signet non d fini Figure 12 Memory management top VIEW cani Erreur Signet non d fini Figure 13 Example Generation of Latch Signal eeseesesessseesessrsessesresresrrsserssesreesresersereseesseneeesreses 10 Figure 14 Simulation timing diagram for signals of SEQUENCER PIX REG 1 10 Figure 15 Simulation timing diagram for signals of SEQUENCER PIX REG 2 11 Figure 16 5 Generation Of the test frame pattern saa case si sone rolla 13 Figure 17 Simulation timing diagram for signals of SEQUENCER_SUZE_REG 14 Figure 18 Cfg multiplexors configuration esee Erreur Signet non d fini Figure 19 Bias synthetic block diabiami lla chie 21 Figure 20 Successive frames and resynchronization timing diagram seen 22 Figure 21 Detail of the beg
45. ri Rowo after pl for the zero suppression PLA processing Figure 22 Pipeline of the readout processing from analog to memory part simulation timing diagram March 2011 MIMOSA26 User Manual V 1 5 34 IPHC Insurua Phuridisciginsire Mubere Luna STARS Cursor Name v Cursor v KS ckdiv8 EX CkDivi amp pr Fa DES KE Set Row Int 575 LI Rst 575 FS Chmping 75 E Pwr Ono gt Sict Row kp LI Pap Fis Clampinglo i F Read F gt Caib F gt Latch gt debuttrame Lr en tst data Efka adine 10 0 gt EnTest nalogMk Er CU A gt MK CLK A gt Pattern Only Et test after ms pa en scan TP entstdatadise SE dualchannelout NT cikrateout Gj scanlinetst 9 0 fg MKD li MKC Er CLKD 0 Fr Doo H F Do H March 2011 721 400ns r2 600ns 2 800ns 722 000ns 722 200ns 722 400ns 722 600ns l Data Ana Row 575 e re je Row add econd Row add Ana R A SSS SS J j G Rep sM A Re Eee e rotto A E Ee Lee n M When loadscan is set to 1 data discri of Row0 scanlinetst is set to 0 are serialized on fall edge clock of CLKD same of clkdiv8 When MKD is set to 1 first bit of data discri of RowO is sampled on rising edge clock of CLKD On DOO pad the first bit serialized is discri lt 575 gt bit and for DO1 pad is discri lt 1151 gt bit The last bit serialized on DOO is discri lt 0
46. t the number of State for this line i e a number between one and nine and an overflow flag The following table describes the signification of the bits in Status Line word Status line Po 1123 4 5 6 7 8 9 10 11 12 13 14 I5 The address of the line States Table 2 Description of States line word State contains the address of the first hit pixel and the number of successive hit pixels as shown on the table below o 12 3 4 5 6 7 8 9 10 11 12 13 14 1s SENE Bit 0 10 the address of the column not used Table 3 Description of State word March 2011 MIMOSA26 User Manual V 1 5 24 MIMOSA26 The table below resumes the maximum length of the output frame according to the selected mode Dual Header Cptframe Datalength Number of useful trailer channel data out words of 16 bits Header0 Cptframe0 Datalength0 Trailer0 amp amp amp amp Headerl Cptframel Datalengthl Trailer Header0 Cptframe0 Datalength0 Trailer0 Headerl Cptframel Datalengthl Trailer Header0 Cptframe0 Datalength0 Trailer0 amp amp amp amp Headerl Cptframel Datalengthl Trailer Header0 Cptframe0 Datalength0 Trailer0 Headerl Cptframel Datalengthl Trailer O 1 2 3 4 5 6 7 8 9 10 1112 13 14 15 CLKD
47. ustable via DAC and has to be chosen close to the VDISREF2 voltage The transfer function is obtained by varying the VDISREFI voltage A B C and D corresponding to the four banks Pixel digital readout calibration During the test mode when EnTestDiscri bit is set to 0 in the RO MODEI register the pixel is connected to discriminators This mode allows obtaining pixel digital readout calibration During one frame one row is processed and the outputs of discriminators are serialized with falling edge of CLKD CLKL 8 and send off chip via DOO and DOI pads The synchronisation marker for digital outputs is generated on MKD pad and corresponding to first bit serialized The pixel array calibration can be realized in automatic mode when En auto scan discri is set to 1 82 3 11 In this mode the scanning of the pixel array uses 576 frames and stop Synoptic According to the synoptic the whole line 1152 bits is scanned and given to two shift register of 576 bits wide Discriminator test structure Cikscan Cikscanout disc CLKD M DFF Scansyncout disc MKD Loadscan En_tstdata En Loadscan En Loadscan Y Clkscan Line bit 1151 L H i H Shift H Register i r1 H Ee i PADS Line bit 576 og dataouto_disc DOO En Loadscan Line bit 575 gt Shift n Register Tooo n Deno jH ataout1_disc DO1
48. zing the readout control The output data of the last frame are sparsified and are sent during the acquisition of the current frame The outputs serializing the data of SUZE 1 with the same number of pads of MIMOSA 22 include A clock CLKD Two data lines DOO and DO1 and A marker MKD The serial output has four configuration modes according to 2 registers cikrate and dualchannel see 2 3 12 as shown later All the words 16 bits are read from the LSB to the MSB The different part of the data frame is the Header Frame counter Data Length States Line State and Trailer The 2 words elements ie Header Frame counter Data Length and Trailer are divided into two parts For instance the header includes Header corresponds to the 16 bits LSB and header corresponds to the 16 bits MSB The Header the Trailer and the Marker signal could be used together to detect lose of synchronization 3 5 1 2 The Clock The clock is always present even if the data transmission is finished Its rate depends on the clkrate register 80 MHz or 40 MHz 3 5 1 3 Marker The marker MKD is available in all modes The Marker signal is set during 4 clock s rising edges and may also be used to detect the beginning of a data transmission 3 5 1 4 Header trailer The Header and the Trailer are composed of 2 x 16 bits header0 header1 trailer0 trailer1 and allows detecting the beginning and the end of a data transmission The Header and the Trailer
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