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ADM-XRC-6T1#User Manual

1. Target FPGA 250MHz RefCIk250M Osc p PCle Bridge FPGA XMC P5 100MHz to 250MHz PCleRefClk Synth Buf XMC P6 Figure 6 MGT Clocks 3 10 Memory Interfaces The ADM XRC 6T1 has four independent banks of DDR3 SDRAM Each bank consists of two 16 bit wide memory devices in parallel to provide a 32 bit datapath capable of running up to 400MHz DDR 800 1Gb devices Micron MT41J64M16 187E are fitted as standard to provide 256MB per bank 2Gb devices giving 512MB per bank are available as an ordering option The memory banks are arranged for compatibility with the Xilinx Memory Interface Generator MIG Figure 7 DRAM Banks Shows the component references and FPGA banks used Full details of the interface signaling standards and an example design are provided in the SDK Page 12 ALPHA DATA est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 sAg4nCtional Description Alpha Data Parallel Systems Ltd AD 001201 UG ADM XRC 6T1 User Manual V0 1 31st May 2010 ALPHA DATA DRAM Bank 0 DRAM Bank 1 U14 amp U27 U17 amp U24 Adr Ctl 36 37 27 Adr Ctl 27 26 25 DQ 37 37 36 36 DQ 25 25 26 26 Virtex 6 U16 Adr Ctl 32 22 23 12 Adr Ctl 23 DQ 22 22 32 32 DQ 12 12 13 13 DRAM Bank 3 DRA
2. 2 1 SOWAN acie NER PLC 22 Hardware Installation H X 2 2 1 Handling Instructions esses esee 2 2 2 Motherboard Carrier Requirements eene 223 COON REMEN GINS us amens iussu apad aspe pa aaa Pala aaa pi aa pa ai a ng kaa aa M UU MEE 3 Functional Description vannsiden OO IT ajaa aaa aaa ia 31 TN NN KE DIS EEE OZ AMO P l AICI ACC MEETS ENE GE E JP NES m EE OE 324 MAS TIL 32 IMS GOE EE EE ane 320 MPRESENT F cassi ee Ree ee SETER EE ee KE KO DOC SAC TT Bad aaa aaa aaa T e ae an SE ENE NAVN SI e OAT REFCGLK2QOM RER PRE EEE 3 4 2 PCIe Reference Clock PCIEREFCLK eranenan awanane aane anan ananawur anan enane 3 4 3 HEFCTKZOM EE EE Eeer GAD MGT OCLIC Se sde 10m da aies a sonne anne Dane eme ae eco ent NNN EE 20 1 Fow r Up SCOUCICE cm aaa ag A AN ge E Dak a da a ak aa A KAN baga a ng abad ang abg an ka OF PICA MONO ee ee nee co EEE NE 3 7 1 Automatic Temperature Monitoring sessi eee FO LOC DU aaa E 10 OO ER 10 29 WO BANK eegene 10 3 9 2 Target MGT Links 11 310 MEMNON MONACOS RENT 12 3 11 XRM Interface and Front Panel 1 0 13 3 11 1 XRM Connector CN 13 OO O OO CO MN NN OO OO OO OO OO Om Ou Ou OAOA A A A RWWA ND NNN ON ON mmo ALPHA DATA est distribu par TECHWAY www techway fr info techway fr 33 0 1
3. 33 SF SPK SJARM Connector Pinouts Alpha Data Parallel Systems Ltd AD 001201 UG ADM XRC 6T1 User Manual V0 1 31st May 2010 ALPHA DATA B 1 XRM Connector CN1 Field 1 Signal FPGA Samtec Samtec FPGA Signal DA NO N39 1 2 M39 DA N1 DA PO N38 3 4 M38 DA P1 DA N2 T36 5 6 P40 DA P3 DA P2 U36 7 8 P41 DA_N3 DA N4 L40 9 10 L42 DA N5 DA P4 L39 11 12 L41 DA P5 DA N6 T35 13 14 R42 DA N7 DA P6 T34 15 16 P42 DA P7 DA P8 R39 17 18 M41 DA P9 DA N8 P38 19 20 M42 DA N9 DA N10 P37 21 22 T40 DA N11 DA P10 N36 23 24 R40 DA P11 DA N12 R38 25 26 N40 DA P13 DA P12 T39 27 28 N41 DA N13 DA N14 M37 29 30 T41 DA P15 DA P14 M36 31 32 T42 DA_N15 DB_NO Y37 33 34 V36 DB Ni DB_PO W37 35 36 W36 DB P1 SA 0 N35 37 38 P36 DA CC P16 39 40 P35 DA CC N16 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Table B1 XRM Connector CN1 Field 1 Front XRM Connecter PIREUS est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 Page 21 AD 001201 UG Alpha Data Parallel Systems Ltd ADM XRC 6T1 User Manual ALPHA DATA V0 1 31st May 2010 B 2 XRM Connector CN1 Field 2 Signal FPGA Samtec Samtec FPGA Signal DB N2 V39 61 62 U34 DB N3 D
4. A 4 Kbit I2C EEPROM type M24C04 is connected to the XMC IPMI This memory contains board information type voltage requirements etc as defined in the XMC based specification 3 2 2 MBIST Built In Self Test This output signal is driven active low until the FPGA with PCle interface is configured In normal operation this is the bridge FPGA In Bridge Bypass mode it is the target FPGA 3 2 3 MVMRO XMC Write Prohibit This signal is an input from the carrier When asserted high all writes to non volatile memories are inhibited This is indicated by the Amber LED D7 Page 4 On board JTAG chain is isolated from P5 Tgt RearMGT 7 6 are connected to P5 No fault detected ALPHA DATA est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 sAg4nCtional Description Alpha Data Parallel Systems Ltd AD 001201 UG ADM XRC 6T1 User Manual V0 1 31st May 2010 ALPHA DATA This signal cannot be internally driven or over ridden A buffered version of the signal is connected to the target FPGA at pin AD30 3 2 4 MRSTI XMC Reset In This signal is an active low input from the carrier When asserted the bridge FPGA will be reset At the end of the reset the target FPGA configuration sequence will start See Section 3 6 Configuration The MRSTI signal is translated to 2 5V levels and connected to the target FPGA at pin AC30 3 2 5 MRSTO XMC Reset Out This optional output signa
5. 168 166 172 170 176 174 180 178 102 104 Alpha Data Parallel Systems Ltd FPGA AL42 AM42 AL41 AM41 AF40 AG41 AK39 AL39 AG42 AH41 AH40 AJ41 AF39 AG39 AJ37 AK37 AH34 AJ35 Table C4 XRM 10146 Pinout pins 115 152 ALPHA DATA est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 ADM XRC 6T1 User Manual v0 1 31st May 2010 Signal DD P1 DD Ni DD P3 DD N3 DD P5 DD N5 DD P7 DD N7 DD P9 DD N9 DD P11 DD N11 DD P13 DD N13 DD P15 DD N15 DD CC P16 DD CC N16 5V XRM 10146 Pinout AD 001201 UG ADM XRC 6T1 User Manual v0 1 31st May 2010 INDEX flash memory 8 9 FPGAIO 14 Target FPGAIO 10 Target FPGA 14 Voltage 1 XRM GPIO signals 14 XRM 10146 Pinout ALPHA DATA est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 AD 001201 UG Alpha Data Parallel Systems Ltd ALPHA DATA Page 29 ADM XRC 6T1 User Manual ALPHA DATA V0 1 31st May 2010 Revision History Nature of Change Date Revision 31 05 10 0 1 First Draft 16 06 10 1 0 First Issue 2010 Alpha Data Parallel Systems Ltd All rights reserved All other trademarks and registered trademarks are the property of their respective owners Address 4 West Silvermills Lane Address 2570 North First Street Suite 440 San Jose CA 95131 Edinburgh EH3 5BD UK Telephone 408 467 5076 General Telephone 44 131 558 2600
6. Fax 44 131 558 2700 408 916 5713 Sales 6 5524 email sales alpha data com Fax 408 43 website http Avww alpha datacteipue par TECHWAY www techway fr info tec 886 r82699566 toll frea 90 email sales alpha data com website http www alpha data com
7. 64 53 37 90 ALPHA DATA ADM XRC 6T1 User Manual v0 1 31st May 2010 CANCEL ARM NNN ANNE 13 GNR cU RECO 13 3 11 4 XRM I F High speed Serial Links 14 A Rear Connector PinOutsS r annunannunnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnennnnnennnnennnnennnnnennnnnnnnnnennnne 15 AT uar XMG Connector Ps ne del cet de ei ds 15 A 2 Secondary XMC Connector P 16 A 3 PMC Connector Pi 17 A 4 Rear MGT Connections to the Target FPGA sese 18 B Front XRM Connector Pinouts rrnnnnennnnnnnnnnnnnennnnnennnnnennnnnnnnnnnnvennnnnnennnnnennnnnunnnnn 20 B 1 XRM GONNECIOF EREECHEN 21 B2 XRM COMECON ME FIOO EE 22 B 3 XRM Connector CN1 Eed 23 B4 XRM COnneclor CN2 etm 24 C XRM 10146 PinOut aauunanuunannnnnunnnnnnnnnnnnnnnnnnnnnnvennnvennnnnnnunnnnnnnnvnnnnnennvnnnnnennnnnnnvennnnennnn 25 Tables Table NNN 1 Table 2 NENNE 3 DES NNN 4 Table 4 REFCLK200M Connections esee nennen nnn nnn nnn nena 6 Table 5 PCIEREFCLK Connections eene nnn nnn nnns 7 Table 6 REFOLR250M Connections caos ihtkuid vena uad yea agateda evade gara tes ead vas acute 7 Table 7 GCLK M2C Connections nr nnn nnn nnn nnn nna 7 Table 8 MGTCLK M2C Connections nennen nnne nennen 7 Table 9 Voltage and Temperature Monitors osse eese 9 Tapie 10 NE LIN Barre 10 Table 11 dae P OA IQ BING rer 10 Table 125 Jargal MGTLINKS sr 11 Table 13 XRM GPIO GrOUDS E 14 Table AT XMC Connector PN 15 Table A2 XMC Connector Pe 16
8. DATA Page 26 Signal DB PO DB NO DB P2 DB N2 DB P4 DB N4 DB P6 DB N6 DB P8 DB N8 DB P10 DB N10 DB P12 DB N12 DB P14 DB N14 SD 1 SD 2 5V FPGA W37 Y37 U39 V39 U37 U38 U32 U33 U42 U41 V33 W33 Y40 Y39 AA35 Y35 AG36 AJ36 ALPHA DATA est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 Samtec 35 33 63 61 67 65 71 69 75 73 17 79 83 81 87 85 105 107 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 13 14 15 16 Samtec 36 34 64 62 68 66 72 70 74 76 80 78 82 84 88 86 89 91 95 Alpha Data Parallel Systems Ltd FPGA W36 V36 V34 U34 W35 V35 V38 W38 V40 W40 V41 W41 W42 Y42 Y38 AA39 W32 Y33 AA36 Table C2 XRM 10146 Pinout pins 39 76 ADM XRC 6T1 User Manual V0 1 31st May 2010 Signal DB P1 DB N1 DB P3 DB N3 DB P5 DB N5 DB P7 DB N7 DB P9 DB N9 DB P11 DB N11 DB P13 DB N13 DB P15 DB N15 DB CC P16 DB CC N16 SB 0 XRM 10146 Pinout AD 001201 UG Signal DC PO DC NO DC P2 DC N2 DC P4 DC N4 DC P6 DC N6 DC P8 DC N8 DC P10 DC N10 DC P12 DC N12 DC P14 DC N14 SC 0 SC 1 5V XRM 10146 Pinout AD 001201 UG ADM XRC 6T1 User Manual v0 1 31st May 2010 FPGA AC36 AB36 AC41 AD41 AC34 AC33 AD42 AE42 AE33 AD33 AF42 AF41 AB32 AB33 AE40 AE39 AG38 AD36 Samtec 103 101 12
9. N3 MGT C2M P6 L1 25 26 L5 MGT M2C P6 MGT C2M N6 L2 27 28 L6 MGT M2C NG Table B4 XRM Connector CN2 Page 24 ALPHA DATA est distribu par TECHWAY www techway fr info techway fr 33 of 9E 4XRM Connector Pinouts Alpha Data Parallel Systems Ltd AD 001201 UG ADM XRC 6T1 User Manual V0 1 31st May 2010 ALPHA DATA Appendix C XRM 10146 Pinout The following tables detail the pin out of the Mictor connector on the XRM IO146 when fitted to an ADM XRC 6TL Signal FPGA Samtec Mictor Mictor Samtec FPGA Signal DA PO N38 3 1 2 6 P40 DA P3 DA NO N39 1 3 4 8 P41 DA N3 DA P2 U36 7 5 6 4 M38 DA P1 DA N2 T36 5 7 8 2 M39 DA N1 DA P4 L39 11 9 10 12 L41 DA P5 DA N4 L40 9 11 12 10 L42 DA N5 DA P6 T34 15 13 14 16 P42 DA P7 DA N6 T35 13 15 16 14 R42 DA N7 DA P8 R39 17 17 18 18 M41 DA P9 DA N8 P38 19 19 20 20 M42 DA N9 DA P10 N36 23 21 22 24 R40 DA_P11 DA_N10 P37 21 23 24 22 T40 DA_N11 DA P12 T39 27 25 26 26 N40 DA _ P13 DA N12 R38 25 27 28 28 N41 DA N13 DA P14 M36 31 29 30 30 T41 DA P15 DA N14 M37 29 31 32 32 T42 DA_N15 SA 0 N35 37 33 34 38 P36 DA CC P16 SA 1 R35 93 35 36 40 P35 DA CC N16 5V 37 38 90 AA34 SB_1 Table C1 XRM 10146 Pinout pins 1 38 XRM 10146 Pinout ALPHA DATA est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 Page 25 AD 001201 UG Alpha Data Parallel Systems Ltd ALPHA
10. available in the FF G 1759 package The card includes separate FPGA with a PCle bridge developed by Alpha Data Using a separate device allows high performance operation without the need to integrate proprietary cores in the user target FPGA The ADM XRC 6T1 is available in air cooled and conduction cooled configurations View the ADM XRC 6T1 specification at ADM XRC 6T1 Product Page on www alpha data com 1 1 Key Features Basic Features e Single width XMC compliant to VITA Standard 42 0 and 42 3 e Dedicated 4 lane Gen2 PCI Express interface with 4 high performance DMA controllers e Virtex 6 FPGA in FF G 1759 package e 4 independent banks of DDR3 800 SDRAM 256MB bank 1GB total 2GB option e Front panel XRM interface with adjustable voltage 146 free I O signals and 8 MGT links to user FPGA Rear panel XMC interface with 38 GPIO signals and 8 MGT links between user FPGA and P6 e 2MGT links between user FPGA and P5 e 2 additional MGT links switchable between user FPGA and P5 or P6 e Rear panel PMC interface with 64 GPIO signals between user FPGA and P4 optional e Voltage and temperature monitoring Section 3 7 Health Monitoring 1 2 References amp Specifications ANSI VITA 42 0 XMC Standard December 2008 VITA ISBN 1 885731 49 3 ANSI VITA 42 3 XMC PCI Express Protocol Layer Standard June 2006 VITA ISBN 1 885731 43 4 IEEE Standard for a Common Mezzanine Card CMC Family Oct
11. 1 123 127 125 129 131 135 133 137 139 141 143 147 145 92 94 17 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 103 105 107 109 113 102 104 106 108 110 112 114 Samtec 100 98 122 124 126 128 130 132 136 134 140 138 144 142 152 150 97 99 Alpha Data Parallel Systems Ltd FPGA AB37 AB38 AA42 AB42 AB39 AA40 AC40 AD40 AA41 AB41 AE38 AD38 AE37 AD37 AE34 AE35 AD32 AE32 Table C3 XRM 10146 Pinout pins 77 114 ALPHA DATA Signal DC P1 DC N1 DC P3 DC N3 DC P5 DC N5 DC P7 DC N7 DC P9 DC N9 DC P11 DC N11 DC P13 DC N13 DC P15 DC N15 DC CC P16 DC CC N16 5V ALPHA DATA est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 Page 27 ALPHA DATA Page 28 Signal DD PO DD NO DD P2 DD N2 DD P4 DD N4 DD P6 DD N6 DD P8 DD N8 DD P10 DD N10 DD P12 DD N12 DD P14 DD N14 SD 0 SD 3 45V FPGA AK38 AJ38 AJ42 AK42 AF37 AG37 AK40 AL40 AF35 AF36 AH39 AJ40 AG34 AF34 AF32 AG33 AG38 AH35 Samtec 149 151 153 155 159 157 161 163 167 165 171 169 175 173 179 177 96 106 Mictor 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 Mictor 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 Samtec 146 148 156 154 160 158 164 162
12. AT17 53 54 AU19 PN4 P28 PN4 N27 AU18 55 56 AT19 PN4 N28 PN4 P29 AV18 57 58 AY18 DNA P30 PN4 N29 AV19 59 60 AW18 PN4 N30 PN4 P31 BA19 61 62 BB18 PN4 P32 PN4 N31 AY19 63 64 BB19 PN4 N32 Table A3 PMC Connector P4 Rear Connector PInNoul ja DATA est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 Page 17 AD 001201 UG Alpha Data Parallel Systems Ltd ADM XRC 6T1 User Manual ALPHA DATA V0 1 31st May 2010 A 4 Rear MGT Connections to the Target FPGA In normal mode the target FPGA RearMGT lanes 3 0 are connected to the Bridge FPGA In Bridge Bypass Mode they are connected to P5 lanes 3 0 RearMGT Lanes 5 4 are connected directly to P5 lanes 5 4 In normal mode Lanes 7 6 are connector to P5 lanes 7 6 In VPX Mode they are connected to P6 lanes 9 8 The pin mappings are as follows in Table A4 Target RearMGT Mapping Signal Tgt FPGA P Pin Tgt FPGA N Pin RearMGT_TX lt 0 gt U1 U2 RearMGT TX 1 T3 T4 RearMGT TX 2 R1 R2 RearMGT TX 3 P3 P4 RearMGT TX lt 4 gt WI W2 RearMGT TX lt 5 gt AA1 AA2 RearMGT TX 6 AC1 AC2 RearMGT TX 7 AE1 AE2 RearMGT TX 8 AG1 AG2 RearMGT TX lt 9 gt AH3 AH4 RearMGT TX lt 10 gt AJ1 AJ2 RearMGT TX lt 11 gt AK3 AK4 RearMGT TX lt 12 gt AL1 AL2 RearMGT TX lt 13 gt AM3 AM4 RearMGT TX lt 14 gt AN1 AN2 RearMGT TX lt 15 gt AP3 AP4 RearMGT RX lt 0 gt W5 W6 RearMGT_RX l
13. B P2 U39 63 64 V34 DB_P3 DB N4 U38 65 66 V35 DB_N5 DB P4 U37 67 68 W35 DB P5 DB N6 U33 69 70 W38 DB N7 DB P6 U32 71 72 V38 DB P7 DB N8 U41 73 74 V40 DB_P9 DB P8 U42 75 76 W40 DB N9 DB P10 V33 77 78 W41 DB_N11 DB_N10 W33 79 80 V41 DB_P11 DB_N12 Y39 81 82 W42 DB P13 DB P12 Y40 83 84 Y42 DB N13 DB N14 Y35 85 86 AA39 DB N15 DB P14 AA35 87 88 Y38 DB P15 DB CC P16 W32 89 90 AA34 SB 1 DB CC N16 Y33 91 92 AC38 SC_0 SA 1 R35 93 94 AD36 SC 1 SB 0 AA36 95 96 AG38 SD_0 DC_CC_P16 AD32 97 98 AB38 DC_N1 DC CC N16 AE32 99 100 AB37 DC_P1 DC_NO AB36 101 102 AH34 DD_CC_P16 DC_PO AC36 103 104 AJ35 DD CC N16 SD 1A G36 105 106 AH35 SD 3 SD 2A J36 107 108 AF30 GCLK M2C N MGTCLK M2C P G10 109 110 AE30 GCLK M2C P MGTCLK M2C N G9 111 112 MGTCLK C2M N 113 114 MGTCLK C2M P 115 116 MGT C2M P7 K3 117 118 J5 MGT M2C P7 Table B2 XRM Connector CN1 Field 2 Page 22 ALPHA DATA est distribu par TECHWAY www techway ft info techway fr 33 0F nE XRM Connector Pinouts Alpha Data Parallel Systems Ltd AD 001201 UG ADM XRC 6T1 User Manual V0 1 31st May 2010 ALPHA DATA B 3 XRM Connector CN1 Field 3 Signal FPGA Samtec Samtec FPGA Signal DC P2 AC41 121 122 AA42 DC P3 DC N2 AD41 123 124 AB42 DC N3 DC N4 AC33 125 126 AB39 DC_P5 DC_P4 AC34 127 128 AA40 DC N5 DC P6 AD42 129 130 AC40 DC P7 DC N6 AE42 131 132 AD40 DC_N7 DC
14. IMPORTANT Connector P6 on the card is not compatible with the XMC 10 GPIO Standard In particular USB VCC must not be applied on this connector The ADM XRC 6T1 is compatible with either 5V or 12V on the VPWR power rail The power dissipation of the board is highly dependent on the Target FPGA application A power estimator spreadsheet is available on request from Alpha Data This should be used in conjunction with Xilinx power estimation tools to determine the exact current requirements for each power rail 2 2 3 Cooling Requirements t b d Page 2 ALPHA DATA est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 Installation Ipha Data Parallel Systems Ltd AD 001201 UG ADM XRC 6T1 User Manual v0 1 31st May 2010 3 Functional Description 3 1 Overview P5 P6 P4 Power Conversion Boot Ctl IPMI Config Ref Clocks CPLD EPROM Flash 250MHz 64MB 200MHz BRG_BYPASS PCle x4 VPX_MODE ALPHA DATA si MGT x2 MGT x8 Rear GPIO 38 bit Rear GPIO 64 bit XRM Bus Bridge Control FPGA LOL 125 M um 146 bit Virtexo LX130T EROS AB FFG484 Front MGT Front IO Y GTP x8 XRM I F 5Gb s x4 User FPGA Virtex 6 LXT SXT MGT x2 FFG1759 MGT x2 720 1 0 MGT x2 24 GTX MM ie LLLALL L
15. M Bank 2 U18 amp U25 U15 amp U28 Figure 7 DRAM Banks 3 11 XRM Interface and Front Panel UO The XRM interface provides a high performance and flexible front panel interface through a range of interchangeable XRM modules Further details of the XRM modules can be found on the Alpha Data website The XRM interface consists of two samtec connectors CN1 and CN2 3 11 1 XRM Connector CN1 Connector CN1 is for general purpose signals power and module control The connector is a 180 way Samtec connector with 3 fields The part fitted to the ADM XRC 6T1 is Samtec QSH 090 01 F D A K Full pinout information for this connector is listed in Appendix B1 ARM Connector CN1 Field 1 to Appendix B3 XRM Connector CN Field 3 3 11 2 XRM Connector CN2 Connector CN2 is for the high speed serial MGT links The part fitted to the ADM XRC 6T1 is Samtec QSE 014 01 F D DP A K Full pinout information for this connector is listed in Appendix B4 KRM Connector CN 2 3 11 3 XRM I F GPIO Functional Description pHA DATA est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 Page 13 AD 001201 UG Alpha Data Parallel Systems Ltd ALPHA DATA ADM XRC 6T1 User Manual v0 1 31st May 2010 The general purpose IO GPIO signals are connected in 4 groups to the Target FPGA Each group consists of 16 standard I O pairs a Regional Clock Capable pair and either 2 or 4 single ended signals The
16. N8 AD33 133 134 AB41 DC N9 DC P8 AE33 135 136 AA41 DC_P9 DC_P10 AF42 137 138 AD38 DC_N11 DC_N10 AF41 139 140 AE38 DC P11 DC P12 AB32 141 142 AD37 DC N13 DC N12 AB33 143 144 AE37 DC P13 DC N14 AES39 145 146 AL42 DD P1 DC P14 AE40 147 148 AM42 DD_N1 DD PO AK38 149 150 AE35 DC_N15 DD NO AJ38 151 152 AE34 DC_P15 DD P2 AJ42 153 154 AM41 DD N3 DD N2 AK42 155 156 AL41 DD P3 DD N4 AG37 157 158 AG41 DD N5 DD P4 AF37 159 160 AF40 DD P5 DD P6 AK40 161 162 AL39 DD N7 DD N6 AL40 163 164 AK39 DD P7 DD N8 AF36 165 166 AH41 DD N9 DD P8 AF35 167 168 AG42 DD P9 DD N10 AJ40 169 170 AJ41 DD N11 DD P10 AH39 171 172 AH40 DD P11 DD N12 AF34 173 174 AG39 DD N13 DD P12 AG34 175 176 AF39 DD P13 DD N14 AG33 177 178 AK37 DD N15 DD P14 AF32 179 180 AJ37 DD P15 Table B3 XRM Connector CN1 Field 3 Front XRM Connecter PIREUS est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 Page 23 AD 001201 UG Alpha Data Parallel Systems Ltd ADM XRC 6T1 User Manual ALPHA DATA vO 1 31st May 2010 B 4 XRM Connector CN2 Signal FPGA Samtec Samtec FPGA Signal MGT C2M PO J1 1 2 H7 MGT M C P MGT C2M NO J2 3 4 H8 MGT_M2C_NO MGT C2M P4 OM Ia 10 P7 MGT M2C P4 MGT COM N4 12 P8 MGT M2C N4 MGT_C2M_P5 M3 13 14 N5 MGT M2C P5 MGT_C2M_N5 M4 15 16 N6 MGT M2C N5 MGT C2M P2 G1 17 18 F7 MGT M2C_P2 MGT C2M N2 G2 19 20 F8 MGT M2C N2 MGT C2M P3 F3 21 22 E5 MGT_M2C_P3 MGT C2M N3 F4 23 24 E6 MGT M2C
17. OY ALPHA DATA ADM XRC 6T1 User Manual Revision 0 1 Date 31st May 2010 Contact www techway fr TECHWAY SAS 19 Avenue de Norv ge B t Oslo Villebon sur Yvette 91953 Courtaboeuf Cedex France T 33 0 1 64 53 37 90 F 33 0 1 64 53 17 74 ALPHA DATA est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 ALPHA DATA ADM XRC 6T1 User Manual v0 1 31st May 2010 2010 Copyright Alpha Data Parallel Systems Ltd All rights reserved This publication is protected by Copyright Law with all rights reserved No part of this publication may be reproduced in any shape or form without prior written consent from Alpha Address Telephone Fax email website Head Office 4 West Silvermills Lane Edinburgh EH3 5BD UK 44 131 558 2600 44 131 558 2700 sales alpha data com http www alpha data com Data Parallel Systems Limited US Office 2570 North First Street Suite 440 San Jose CA 95131 408 467 5076 General 408 916 5713 Sales 408 436 5524 866 820 9956 toll free sales alpha data com http www alpha data com ALPHA DATA est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 ADM XRC 6T1 User Manual V0 1 31st May 2010 ALPHA DATA Table Of Contents 1 node a ee re M GBE TC QUI S ea a Bg E D a T a oo 1 2 References amp Zpecifcaions suiscorisesn in E E 2 MAIN
18. Table A3 PMC Connector Pi 17 Table A4 Target RearMGT Mapping esee nennen nennen nnn nnn nnns 18 Table B1 XRM Connector CN1 Feld 21 Table B2 XRM Connector CN1 Field 2 essc eene nnn nnn 22 Table B3 XRM Connector CN1 Field 3 esses nnne nennen 23 Table B4 XRM Connector CN 24 Table C1 XRM 10146 Pinout pins 1 38 ns 25 Table C2 XRM 10146 Pinout pins 89 76 26 Table C3 XRM 10146 Pinout pins 77 114 ne 27 Table C4 XRM IO146 PINOUT pins 115 152 28 ALPHA DATA est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 ADM XRC 6T1 User Manual v0 1 31st May 2010 amp ALPHA DATA Figures Figure 1 ADM XHC 6T1 Block Diagram eene 3 Figure 2 JTAG Header J A 5 Figure 3 JTAG Boundary Scan Cham 5 Figure 4 Flash Memory Man 8 Me NTN 11 Figure 6 MGT EUCH an nie die chics ed ae 12 Figure 7 DRAM DA RS 13 ALPHA DATA est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 ADM XRC 6T1 User Manual ALPHA DATA v0 1 31st May 2010 Page Intentionally left blank ALPHA DATA est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 ADM XRC 6T1 User Manual V0 1 31st May 2010 ALPHA DATA 1 Introduction The ADM XRC 6T1 is a high performance AMC for applications using Virtex 6 FPGAs from Xilinx M This card supports all Virtex 6 LXT and SXT devices
19. WL E LLTL 4L BA 77 A A ip M M M MM M M M lie NETT Battery DDR3 DDR3 DDR3 DDR3 vends JTAG for AES SDRAM SDRAM SDRAM SDRAM keys 256MB 256MB 256MB 256MB Figure 1 ADM XRC 6T1 Block Diagram 3 1 1 Switch Definitions There is a set of eight DIP switches placed on the rear of the board Their functions are described in Table 2 Switch Definitions Note All switches are OFF by default All Factory Test and Reserved switches must be in the OFF position for normal operation Switch Ref Function ON State Off State Bridge FPGA is bypassed PCle lanes SW1 1 Bridge Bypass 3 0 are connected directly to the user au ARCA un POIG lanes 3 0 are connected to the bridge FPGA SW1 2 Factory Test Factory Test Mode Normal Operation Enable E Fuse programming voltage Disable E Fuse programming voltage PS Ese VccEFuse 2 5V VccEFuse OV SW1 4 XMC JTAG Connect JTAG chain to P5 Isolate JTAG chain from P5 P Target FPGA is cleared then configured SW1 5 One time Target FPGA is cleared then configured from flash at power up and after every Configuration from Flash at power up only board reset MRSTI Functional Description pHA DATA est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 AD 001201 UG Alpha Data Parallel Systems Ltd Table 2 Switch Defini
20. able clock parameters and configuration bitstreams for the Bridge and Target FPGAs The flash memory cannot be accessed by the target FPGA Host access is only possible through the FLCTL FLPAGE and FLDATA registers in the bridge FPGA Utilities for erasing programming and verification of the flash memory are provided in the ADMXRC SDK Write Protect The Flash Write Protect WP pin is connected to an inverted version of the MVMRO signal at the XMC interface When the MVMRO signal is active High all writes to the flash will be inhibited This state will be indicated by the Amber LED D9 Alternate Bridge FPGA Bitstream Default Bridge FPGA Bitstream Vital Product Data VPD LCLK Word 15 0 LCLK Word 31 16 reserved BO Length 7 0 Boot Flag 0 Bitstream 0 Length 23 8 reserved Default Target FPGA Bitstream Target Bitstream O B1 Length 7 0 Boot Flag 1 Bitstream 1 Length 23 8 reserved Alaternate Target FPGA Bitstream Target Bitstream 1 0x0000 0000 0x007F FFFE 0x0080 0000 OxOOFF FFFE 0x0100 0000 0x0100 03FE 0x0100 0400 0x0100 0402 0x0120 0000 WAU LA U002 0x0122 0000 0x028F FFFE 0x0290 0000 0x0290 0002 0x0292 0000 0x03FF FFFE Figure 4 Flash Memory Map 3 6 Configuration Page 8 ALPHA DATA est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 az dai C tional Description Ipha D
21. anual V0 1 31st May 2010 ALPHA DATA Appendix A Rear Connector Pinouts A 1 Primary XMC Connector P5 A B C D E F 1 PETOpO PETOnO 3 3V PETOp1 PETOn1 VPWR 2 GND GND XMC_TRST GND GND MRSTI 3 PETOp2 PETOn2 3 3V PETOp3 PETOn3 VPWR 4 GND GND XMC_TCK GND GND MRSTO 5 PETOp4 PETOn4 3 3V PETOp5 PETOn5 VPWR 6 GND GND XMC_TMS GND GND 12V 7 PETOp6 PETOn6 3 3V PETOp7 PETOn7 VPWR 8 GND GND XMC TDI GND GND 12V 9 VPWR 10 GND GND XMC TDO GND GND GAO 11 PEROpO PEROnO MBIST PEROp1 PEROn1 VPWR 12 GND GND GA1 GND GND MPRESENT 13 PEROp2 PEROn2 e PEROp3 PEROn3 VPWR 14 GND GND GA2 GND GND MSDA 15 PEROp4 PEROn4 PEROp5 PEROn5 VPWR 16 GND GND MVMRO GND GND MSCL 17 PEROp6 PEROn6 PEROp7 PEROn7 18 GND GND GND GND 19 REFCLK 0 REFCLK 0 WAKE ROOTO 1 PCle Channel 0 Lanes 3 0 are connected to the Bridge FPGA by default but can be routed to the target FPGA in Bridge Bypass Mode 2 PCle Channel 0 Lanes 7 4 are only connected to the Target FPGA This may be used as a second 4 lane channel if supported by the carrier card although this configuration is non standard Notes 3 PCle Channel 0 Lanes 7 6 are not available when the board is in VPX Mode 4 JTAG is unused XMC TDI is connected to XMC TDO 5 3 3V AUX is unused 6 VPWR can be either 5V or 12V Table A1 XMC Connector P5 Rear Connector Pinouts ja DATA est distribu par TECHWAY www techway fr inf
22. ata Parallel Systems Ltd AD 001201 UG ADM XRC 6T1 User Manual v0 1 31st May 2010 3 6 1 Power Up Sequence ALPHA DATA If valid data is stored in the flash memory the bridge will automatically set the programmable clock generator and configure the Target FPGA at power up This sequence can be inhibited by turning the Flash Boot Inhibit FBI switch SW1 6 to ON See Table 2 Switch Definitions Note If an over temperature alert is detected from the System Monitor the target will be cleared by pulsing its PROG signal See Section 3 7 1 Automatic Temperature Monitoring 3 Health Monitoring The ADM XRC 6T1 has the ability to monitor temperature and voltage to maintain a check on the operation of the board The monitoring is implemented using a National Semiconductor LM87 connected to control logic in the bridge FPGA using I2G The control logic scans the LM87 when instructed by host software and stores the measurements in a blockram This allows the values to be read without the need to communicate directly with the LM87 The following voltage rails and temperatures are monitored Monitor 1 0V 1 5V Purpose FPGA Core Supply VccINT DDR3 SDRAM Target FPGA memory I O 1 8V 2 5V XRM_VIO 3 3V 5 0V VPWR Flash Memory DC DC converters for GTX Supplies FPGA Auxiliary Supply VccAUX XRM Front Panel I O voltage Board Input Supply Internally generated 5V supply Board Input S
23. can be used to generate application specific clock frequencies using the PLLs within the Virtex 6 FPGA It is also suitable as the reference clock for the IO delay control block IDELAYCTRL Target FPGA Input IO Standard P pin N pin IO LO GC 24 LVDS 25 AE30 AF30 Signal REFCLK200M Table 4 REFCLK200M Connections 3 4 2 PCle Reference Clock PCIEREFCLK Page 6 ALPHA DATA est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 sAg4nCtional Description Alpha Data Parallel Systems Ltd AD 001201 UG ADM XRC 6T1 User Manual V0 1 31st May 2010 ALPHA DATA The 100MHz PCI Express reference clock is provided by the carrier card through the Primary XMC connector P5 at pins A19 and B19 This is multiplied to 250MHz and distributed to both the Bridge and Target FPGAs On the Target FPGA it is connected to GTX Quad 113 and 114 to allow its use as a reference for all the MGT links to the XMC connectors See Figure 6 MGT Clocks for details of the MGT reference clocks Signal Target FPGA Input IO Standard P pin N pin PCIEREFCLK 1 MGTREFCLK1 113 LVDS 25 AD8 AD7 PCIEREFCLK 2 MGTREFCLKO 114 LVDS 25 AB8 AB7 Table 5 PCIEREFCLK Connections 3 4 3 REFCLK250M The fixed 250 0MHz reference clock REFCLK250M is a differential clock signal using LVDS The clock is buffered and connected to three MGTREFCLKO inputs on the Target FPGA at GTX Quad 113 115 and 116 See Fi
24. gure 6 MGT Clocks Signal Target FPGA Input 1O Standard P pin N pin REFCLK250M 3 MGTREFCLKO 113 LVDS 25 f AF8 AF7 REFCLK250M_2 MGTREFCLKO 115 LVDS 25 V8 V7 REFCLK250M 1 MGTREFCLKO 116 LVDS 25 M8 M7 Table 6 REFCLK250M Connections 3 4 4 GCLK M2C The clock GCLK_M2C is a differential clock signal using LVDS It is provided by an XRM module through the XRM connector CN1 at pins 110 amp 108 It is connected to a Global Clock input on the Target FPGA Signal GCLK M2C Target FPGA Input IO Standard P pin N pin lO L1 GC 24 LVDS 25 W30 V30 Table 7 GCLK M2C Connections 3 4 5 MGTCLK M2C The reference clock MGTCLK M2C is a differential clock signal using LVDS The clock is provided by an XRM module through the XRM connector CN1 at pins 109 amp 111 It is connected to GTX Quad 117 on the Target FPGA for application specific frequencies line rates Functional Description pHA DATA est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 Page 7 AD 001201 UG Alpha Data Parallel Systems Ltd ADM XRC 6T1 User Manual ALPHA DATA V0 1 31st May 2010 IO Standard LVDS 25 G10 G9 Signal MGTCLK M2C Target FPGA Input MGTREFCLKO 117 p pin N pin Table 8 MGTCLK_M2C Connections 3 5 Flash Memory A 512Mb Flash Memory Intel Numonyx PC28F512P30EF is used to store board Vital Product Data VPD programm
25. l is unused and undriven 3 2 6 MPRESENT Module Present This output signal is connected directly to OV 3 3 JTAG Interface 3 3 1 On board Interface A JTAG boundary scan chain is connected to header J3 This allows the connection of the Xilinx JTAG cable for FPGA debug using the Xilinx ChipScope tools The JTAG Header pinout is shown in Figure 2 JTAG Header J2 lt 0 4 a4 4 O Zz O UO d 2 O O x OU o ee 0000 Figure 2 JTAG Header J2 The scan chain is shown in Figure 3 JTAG Boundary Scan Chan Header J3 VREF 2 5V Bridge FPGA Control CPLD Target FPGA XC6VLX130T XC2C64A XC6VLXxxxT wel XMC TDI HOR TDI FFG484 L CP56 wv FFG1759 gt ABA TEL Con Level Shift Level Shift Pn5 XMC_TDO 9 3 3V 2 5V HDR TDO 2 5V XRM VIO umm m G XRM_TDO En En lt lt VF i XMC_JTAG_EN zap i PRESENT Figure 3 JTAG Boundary Scan Chain If the boundary scan chain is connected to the interface at the XMC connector SW1 4 is ON Header J3 should not be used 3 3 2 XMC Interface Functional Description pHA DATA est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 Page 5 AD 001201 UG Alpha Data Parallel Systems Ltd ADM XRC 6T1 User Manual ALPHA DATA V0 1 31st May 2010 The JTAG interface
26. o techway fr 33 0 1 64 53 37 90 Page 15 AD 001201 UG Alpha Data Parallel Systems Ltd ALPHA DATA A 2 Secondary XMC Connector P6 ADM XRC 6T1 User Manual v0 1 31st May 2010 A B C D E F 1 P6 TXpO P6 TXnO GPIO 37 P6 TXp1 P6 TXn1 GPIO 38 2 GND GND GPIO 35 GND GND GPIO 36 3 P6 TXp2 P6 TXn2 GPIO 33 P6 TXp3 P6 TXn3 GPIO 34 4 GND GND GPIO 31 GND GND GPIO 32 5 P6 TXp4 P6 TXn4 GPIO 29 P6 TXp5 P6 TXn5 GPIO 30 6 GND GND GPIO 27 GND GND GPIO 28 7 P6 TXp6 P6 TXn6 GPIO 25 P6 TXp7 P6 TXn7 GPIO 26 8 GND GND GPIO 23 GND GND GPIO 24 9 P6 TXp8 P6 TXn8 GPIO 21 P6 TXp9 P6 TXn9 GPIO 22 10 GND GND GPIO 19 GND GND GPIO 20 11 P6 RXpO P6 RXnO GPIO 17 P6 RXp1 P6 RXn1 GPIO 18 12 GND GND GPIO 15 GND GND GPIO 16 13 P6 RXp2 Pe RXn2 GPIO 13 P6 RXp3 P6 RXn3 GPIO 14 14 GND GND GPIO 11 GND GND GPIO 12 15 P6 RXp4 P6 RXn4 GPIO 9 P6 RXp5 P6 RXn5 GPIO 10 16 GND GND GPIO 7 GND GND GPIO 8 17 P6 RXp6 P6 RXn6 GPIO 5 P6 RXp7 P6 RXn7 GPIO 6 18 GND GND GPIO 3 GND GND GPIO 4 19 P6 RXp8 P6 RXn8 GPIO 1 P6 RXp9 P6 RXn9 GPIO 2 Notes 1 MGT Lanes P6 TX 7 0 and P6 RX 7 0 are connected directly to the Target FPGA 2 MGT Lanes P6 TX 9 8 and P6 RX 9 8 are only available in VPX Mode 3 GPIO signals are single ended and 3 3V compatible Table A2 XMC Connector P6 Page 16 ALPHA DATA est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 ear Connecto
27. ober 2001 IEEE ANSI IEEE 1386 2001 ISBN 0 7381 2829 5 IEEE Standard Physical and Environmental Layers for PCI Mezzanine Cards PMC ANSV IEEE 19861 2001 October 2001 IEEE ISBN 0 7381 2831 7 ANSI VITA 20 2001 R2005 Conduction Cooled PMC February 2005 VITA ISBN 1 885731 26 4 Table 1 References Introduction ALPHA DATA est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 Page 1 AD 001201 UG Alpha Data Parallel Systems Ltd ADM XRC 6T1 User Manual ALPHA DATA V0 1 31st May 2010 2 installation 2 1 Software Installation Please refer to the Software Development Kit SDK installation CD The SDK contains drivers examples for host control and FPGA design and comprehensive help on application interfacing 2 2 Hardware Installation 2 2 1 Handling Instructions The components on this board can be damaged by electrostatic discharge ESD To prevent damage observe SSD precautions Always wear a wrist strap when handling the card Hold the board by the edges Avoid touching any components Store in ESD safe bag 2 2 2 Motherboard Carrier Requirements The ADM XRC 6T1 is a single width XMC 3 mezzanine with optional P6 and P4 connectors The motherboard carrier must comply with the XMC 3 VITA 42 3 specification for the Primary XMC connector J5 The Secondary XMC connector J6 has a pinout compatible with VITA 46 9 X38s X8d X12d mapping
28. on the XMC connector is normally unused and XMC TDI connected directly to AMC TDO The interface can be connected to the on board interface through level translators by switching SW1 4 ON See Section 3 1 1 Switch Definitions 3 3 3 JTAG Voltages The on board JTAG scan chain uses 2 5V The Vcc supply provided on J3 to the JTAG cable is 2 5V and is protected by a poly fuse rated at 350mA 3 3V signals must not be used at header J3 The JTAG signals at the XMC interface use 3 3V signals and are connected through level translators to the on board scan chain The JTAG signals at the XRM interface use the adjustable voltage XRM VIO 3 4 Clocks The ADM XRC 6T1 provides a wide variety of clocking options The fixed reference clocks on the board can be combined with the PLLs in the FPGA to suit the target application The on board clocks are detailed below Note Clock Termination The LVDS clocks do not have termination resistors on the circuit board On die terminations in the FPGA must be enabled by setting the attribute DIFF TERM TRUE This can either be set in the source code when instantiating the buffer or in the User Constraints File UCF See the Xilinx M Virtex 6 Libraries Guide and Constraints Guide for further details 3 4 1 REFCLK200M The fixed 200MHz reference clock REFCLK200M is a differential clock signal using LVDS It is connected to a Global Clock input on the Target FPGA at pins AE30 and AF30 This clock
29. r Pinouts Alpha Data Parallel Systems Ltd AD 001201 UG ADM XRC 6T1 User Manual V0 1 31st May 2010 ALPHA DATA A 3 PMC Connector P4 The PMC Connector P4 is fitted as standard but can be omitted if required 64 GPIO signals are connected between P4 and the target FPGA via FET bus switches By limiting the signal voltage at 2 5V these allow the use of 3 3V or 2 5V signalling levels to be used at P4 oignals may be used in single ended or as differential pairs Signal FPGA Pin P4 Pin P4 Pin FPGA Pin Signal PN4 P1 BA16 1 2 AV16 PN4 P2 PN4 N1 BA17 3 4 AW16 PN4_N2 PN4_P3 AY15 5 6 AR14 DNA P4 PN4_N3 AW15 7 8 AT14 PN4 N4 PN4 P5 AN14 9 10 AM13 PN4 P6 PN4 N5 AN13 11 12 AM12 DNA NG PN4 P7 AP11 13 14 AP13 PN4 P8 PN4 N7 AP12 15 16 AR13 DNA NG DNA P9 AR12 17 18 AU12 DNA P10 PN4 NO AT12 19 20 AU13 PN4 N10 PN4 P11 AV13 21 22 AW12 PN4 P12 PN4 N11 AV14 23 24 AW13 PN4 N12 PN4 P13 BB13 25 26 BB16 PN4 P14 PN4 N13 BB14 27 28 BB17 PN4 N14 PN4 P15 BA15 29 30 AV15 PN4 P16 PN4 N15 BA14 31 32 AU14 PN4 N16 PN4 P17 AJ16 33 34 AK18 PN4 P18 PN4 N17 AJ15 35 36 AJ18 PN4 N18 PN4 P19 AM17 37 38 AJ17 PN4 P20 PN4 N19 AM18 39 40 AK17 PN4 N20 PN4_P21 AL17 41 42 AK15 PN4_P22 DNA N21 AL16 43 44 AK14 PN4 N22 PN4 P23 AN18 45 46 AN16 DNA P24 DNA N23 AN19 47 48 AM16 DNA N24 PN4 P25 AP18 49 50 AP16 PN4 P26 DNA N25 AR19 51 52 AP17 PN4 N26 PN4 P27
30. re are no on board terminations on the pairs and any can be used in single ended modes To allow fast data transfer all of the GPIO signals within a group are delay matched to within 100ps All the XRM GPIO signals and FPGA IO banks share a common voltage XRM VIO that van be either 2 5V 1 8V or 1 5V The required voltage is stored within the platform management PROM on the XRM Group iis Name XRM DA 15 0 XRM DA CC 16 SA 1 0 XRM DB 15 0 XRM DB CC 16 SB 1 0 XRM DC 15 0 XRM DC CC 16 SC 1 0 XRM DD 15 0 XRM DD CC 16 SD 3 0 Function 16 diff Pairs 32 single ended Regional Clock GPIO pair 2 single ended 2 single ended GPIO 16 diff Pairs 32 single ended Regional Clock GPIO pair 2 single ended 2 single ended GPIO 16 diff Pairs 32 single ended Regional Clock GPIO pair 2 single ended 2 single ended GPIO 16 diff Pairs 32 single ended Regional Clock GPIO pair 2 single ended 4 single ended GPIO Table 13 XRM GPIO Groups 3 11 4 XRM I F High speed Serial Links Eight MGT links are routed between the Target FPGA and the XRM interface Lanes 6 0 are routed through the Samtec QSE DP connector CN2 Lane 7 is routed through the Samtec QSH connector CN1 Page 14 ALPHA DATA est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 sAg4nCtional Description Ipha Data Parallel Systems Ltd AD 001201 UG ADM XRC 6T1 User M
31. se the user application and possibly the host computer to hang 3 8 Local Bus A Multiplexed Packet Transport Link MPTL connects the Bridge and Target FPGAs It is capable of transferring data at up to 2GB s simultaneously in each direction The MPTL replaces the parallel local bus used in previous generations of the ADM XRC series Details of the link and example designs are given in the Software Development Kit SDK 3 9 Target FPGA 3 9 1 I O Bank Voltages The Target FPGA IO is arranged in banks each with their own supply pins The bank numbers their voltage and function are shown in Table 11 Target FPGA IO Banks Full details of the IOSTANDARD required for each signal are given in the SDK Voltage Purpose 0 24 25V Configuration JTAG LBus Control XMC i Control Target SelectMap Interface 33 34 2 5V Pn4 37 36 26 25 1 5V DRAM Banks 0 amp 1 27 1 5V DRAM Banks 0 XMC GPIO 13 12 1 5V DRAM Bank 2 XMC GPIO 23 32 22 1 5V DRAM Banks 2 amp 3 14 15 16 17 XRM VIO XRM Interface variable voltage Table 11 Target FPGA IO Banks continued on next page Page 10 ALPHA DATA est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 ggnctional Description Alpha Data Parallel Systems Ltd AD 001201 UG ADM XRC 6T1 User Manual V0 1 31st May 2010 ALPHA DATA Voltage Purpose 1 5V reserved IO Banks 21 28 38 Table 11 Targe
32. t 1 gt V3 V4 RearMGT_RX lt 2 gt U5 U6 RearMGT_RX lt 3 gt R5 R6 RearMGT_RX lt 4 gt Y3 Y4 RearMGT_RX lt 5 gt AA5 AA6 RearMGT_RX lt 6 gt AB3 AB4 RearMGT RX lt 7 gt AC5 AC6 RearMGT_RX lt 8 gt AD3 AD4 RearMGT_RX lt 9 gt AE5 AE6 RearMGT_RX lt 10 gt AF3 AF4 RearMGT RX lt 11 gt AG5 AG6 RearMGT RX lt 12 gt AJ5 AJ6 RearMGT RX lt 13 gt AL5 AL6 RearMGT RX lt 14 gt AM7 AM8 Table A4 Target RearMGT Mapping continued on next page Page 18 ALPHA DATA est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 ear Connector Pinouts Alpha Data Parallel Systems Ltd AD 001201 UG ADM XRC 6T1 User Manual v0 1 31st May 2010 ALPHA DATA Signal Tgt FPGA P Pin Tgt FPGA N Pin RearMGT RX lt 15 gt AN5 AN6 Table A4 Target RearMGT Mapping Rear Connector Pinouls ja DATA est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 AD 001201 UG Alpha Data Parallel Systems Ltd Page 19 ADM XRC 6T1 User Manual ALPHA DATA V0 1 31st May 2010 Appendix B Front XRM Connector Pinouts The XRM interface consists of two connectors CN1 and CN2 CN1 is a 180 way Samtec QSH in 3 fields It is for general purpose signals power and module control CN2 is a 28 way Samtec QSE DP for high speed serial MGT links General Purpose I O Clocks MGT Links Page 20 ALPHA DATA est distribu par TECHWAY www techway fr info techway fr
33. t FPGA 10 Banks 3 9 2 Target MGT Links There are a total of 24 Multi Gigabit Transceiver MGT links connected to the Target FPGA Links Width Connection Bridge FPGA for MPTL or XMC Connector FORMES P5 lanes 3 0 in Bridge Bypass Mode RearMGT 5 4 2 Direct link to XMC P5 lanes 5 4 Link to XMC P5 lanes 7 6 in default mode SAHA 2 connector P6 lanes 9 8 in VPX mode RearMGT 15 8 8 Direct link to XMC P6 lanes 7 0 FrontMGT 7 0 8 Direct link to XRM interface Table 12 Target MGT Links The connections of these links are shown in Figure 5 MGT Links aiu RU XRM I F Target FPGA PCle Bridge 4 Local 3 0 FPGA PCle 3 0 gt XMC P5 PCle 5 4 PCle 7 6 EyI aS O 88 M P6 9 8 TS 3 0 XMC VPX MODE BRG BYPASS P6 P6 7 0 Figure 5 MGT Links Functional Description pHA DATA est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 Page 11 AD 001201 UG Alpha Data Parallel Systems Ltd ADM XRC 6T1 User Manual ALPHA DATA V0 1 31st May 2010 Notes 1 The numbering in the Target FPGA refers to the GTX Quad number Each Quad contains a grouping of four GTXE1 Multi Gigabit Transceivers and two dedicated reference clock pairs REFCLK 250M MGTCLK M2C XRM I F
34. tions continued on next page Page 3 ALPHA DATA ADM XRC 6T1 User Manual v0 1 31st May 2010 Switch Ref Function ON State Off State Flash Boot Target FPGA is not configured from Target FPGA is configured from SW1 6 Inhibit onboard flash memory on board flash memory SW1 7 Reserved SW1 8 VPX Mode Connect Tgt RearMGT 7 6 to P6 Connect Tgt RearMGT 7 6 to P5 Table 2 Switch Definitions 3 1 2 LED Definitions There are eight LEDs placed on the rear of the board to indicate the status Comp Ref Function ON State Off State 1 0V 2 5V 1 8V and 1 5V power D10 Green Power Good HO eon Town Eo Owes supplies are not all on or all at their supplies are on correct levels D11 Green Bridge Done Bridge FPGA is configured Bridge FPGA is unconfigured D12 Green Target Done Target FPGA is configured Target FPGA is unconfigured D9 Amber MVMRO Inhibit writes to non volatile memories Enable writes to non volatile memories D14 Amber Bridge Bypass Bridge FPGA is bypassed PCle lanes 3 0 are connected directly to the user FPGA Bridge FPGA is used PCle lanes 3 0 are connected to the bridge D8 Amber D7 Amber D13 Red XMC JTAG VPX Mode Fault On board JTAG chain connected to P5 Tgt RearMGT 7 6 are connected to P6 Voltage or Temperature Fault Detected Table 3 LED Definitions 3 2 XMC Platform Interface 3 2 1 IPMI LC
35. upply either 5 0V or 12 0V Tempi Target FPGA on die temperature Temp2 LM87 on die temperature Table 9 Voltage and Temperature Monitors An example application that reads the system monitor sysmon is available on request 3 7 1 Automatic Temperature Monitoring Functional Description pHA DATA est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 Alpha Data Parallel Systems Ltd AD 001201 UG Page 9 ADM XRC 6T1 User Manual ALPHA DATA V0 1 31st May 2010 At power up the control logic sets temperature limits and enables the over temperature interrupting the LM87 If the One Time Configuration OTC function is disabled using SW1 5 see Table 2 Switch Definitions the limits and interrupt will be re set after a board reset MRSTI If OTC is enabled the limits and interrupt will only be set once at power up The temperature limits are shown in Table 10 Temperature Limits Target FPGA Board LM87 Min Max Min Max Commercial 0 C 85 C 0 C 70 C Industrial 40 C 100 C 40 C 85 C Table 10 Temperature Limits Important If any temperature limit is exceeded the Target FPGA is automatically cleared This is indicated by Green LED D13 Target DONE switching off and Red LED D14 Fault switching on The purpose of this mechanism is to protect the card from damage due to over temperature It is possible that it will cau

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