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M68040 User's Manual µ MOTOROLA

1. ROOTPOINER TASKA 5 3B W BIT SET TABLE 3B TABLE 15 ROOT POINTER 3 TASKB 2 W BIT CLEAR 15 00003000 01 FRAME ADDRESS ROOT LEVEL POINTER LEVEL PAGE LEVEL TABLES TABLES TABLES Page frame address shared by task A and B write protected from task A Figure 3 15 Translation Table Using Shared Tables 3 2 4 3 TABLE PAGING The entire translation table for an active task need not be resident in main memory In the same way that only the working set of pages must be allocated in main memory only the tables that describe the resident set of pages need be available Placing the invalid code 0 or 1 in the UDT field of the table descriptor that points to the absent table s implements this paging of tables When a task attempts to use an address that an absent table would translate the M68040 is unable to locate a translation and takes access error exception when the execution unit retries the bus access that caused the table search to be initiated The operating system determines that the invalid code in the descriptor corresponds to nonresident tables This determination can be facilitated by using he unused bits in the descriptor to store status information concerning the invalid encoding The M68040 does not interpret or modify an invalid descriptor s
2. ss s 25 s a o ss RR ES CI REI Eavan eck se 7 s s Hold Eu BCLK to Address SIZx TTx R W 25 Invalid Hold 45 MC68LC040 Assumes Bus Mastership A 12 M68040 USER S MANUAL MOTOROLA A31 A0 TRANSFER ATTRIBUTES TS TIP D31 D0 IN READ D31 D0 OUT WRITE TA TEA TCI TBI AVEC NOTE Transfer Attribute Signals UPAx SIZx TTx TMx TLNx R W LOCK LOCKE CIOUT MOTOROLA T Figure A 5 Read Write Timing M68040 USER S MANUAL A31 A0 TRANSFER ATTRIBUTES LOCK LOCKE TIP D31 D0 OUT WRITE BR lt gt 2 lt gt mr 0 gt 41 lt gt M NOTE Transfer Attribute Signals UPAx SIZx TTx TMx TLNx R W CIOUT Figure A 6 Bus Arbitration Timing M68040 USER S MANUAL MOTOROLA R W IN TS D31 D0 ALT MASTER 7 WRITE D31 D0 OUT ALT MASTER READ 65 TA OUT Figure 7 Snoop Hit Timing MOTOROLA M68040 USER S MANU
3. T T T T T T 1 I I A lt RETRY 39 RETRY CYCLE SIGNALED Figure 7 29 Retry Operation on Line Write 7 42 M68040 USER S MANUAL MOTOROLA 7 6 3 Double Bus Fault A double bus fault occurs when an access or address error occurs during the exception processing sequence e g the processor attempts to stack several words containing information about the state of the machine while processing an access error exception If a bus error occurs during the stacking operation the second error is considered a double bus fault The M68040 indicates a double bus fault condition by continuously driving PST3 PSTO with an encoded value of 5 until the processor is reset Only an external reset operation can restart a halted processor While the processor is halted negating BR and forcing all outputs to a high impedance state releases the external bus A second access or address error that occurs during execution of an exception handler or later does not cause a double bus fault A bus cycle that is retried does not constitute a bus error or contribute to a double bus fault The processor continues to retry the same bus cycle as long as external hardware requests it 7 7 BUS SYNCHRONIZATION The M68040 integer unit generates access requests t
4. Soo oo ooo ooo gt Oo Oo Oo Oo oo gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt SK gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt SL SL gt lt gt lt 56 gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt nc m l s NOR 00 O O QN CO lt LO O ODOT f LO CO 0 O SF LO Q N N QN LO 00 QN Q Q 7 e ei el el AAA AA el 4 el ALA el oi el el f ol ell el oj lt
5. 01 02 03 DATA 04 REGISTERS D5 D6 D7 3l 15 0 0 Al A2 ADDRESS A3 REGISTERS 4 5 A6 3 15 0 USER uae STACK POINTER 21 _ PROGRAM bo 7 0 CONDITION CODE E REGISTER Figure 2 3 Integer Unit User Programming Model 2 4 M68040 USER S MANUAL MOTOROLA 2 2 1 3 SYSTEM STACK POINTER 7 A7 is used as hardware stack pointer during stacking for subroutine calls and exception handling The register designation A7 refers to three different uses of the register the user stack pointer USP A7 in the user programming model and either the interrupt stack pointer ISP or master stack pointer MSP A7 or A7 respectively in the supervisor programming model When the S bit in the status register SR is clear the USP is the active stack pointer Explicit references to the system stack pointer SSP refer to the USP while the processor is operating in the user mode A subroutine call saves the program counter PC on the active system stack and the return restores it from the active system stack Both the PC and the SR are saved on the supervisor stack either ISP or MSP during the processing of exceptions and interrupts Thus the execution of supervisor level code is independent of user code and condition of the user stack Conversely user programs use the USP independently of supervisor stack requirements 2
6. C 6 1 1 EXTEST The external test instruction EXTEST selects the boundary scan register This instruction also activates one internal function that is intended to protect the device from potential damage while performing boundary scan operations EXTEST asserts internal reset for the MC68040V and MC68ECO40V system logic to force predictable benign internal state C 6 1 2 HIGHZ The HIGHZ instruction is an optional instruction provided as a Motorola public instruction to anticipate the need to backdrive output pins during circuit board testing The HIGHZ instruction asserts internal system reset selects the bypass register and forces all output and bidirectional pins to the high impedance state Holding TMS high and clocking TCK for at least five rising edges causes the TAP controller to enter the test logic reset state Using only the TMS and TCK pins and the capture IR and update IR states invokes the HIGHZ instruction This scheme works because the value captured by the instruction shift register during the capture IR state is identical to the HIGHZ opcode C 6 1 3 SAMPLE PRELOAD The SAMPLE PRELOAD instruction provides two separate functions First it provides a means to obtain a sample system data and control signal Sampling occurs on the rising edge of TCK in the capture DR state The user can observe the data by shifting it through the boundary scan register to output TDO using the shif
7. mu moe mami wa aF RESTORE TL C FSQRT jNewmsmeton ______ Po M68040 USER S MANUAL D 3 68020 MC68030 and MC68040 Instruction Set Extensions Continued Applies To MC68020 MC68030 MC68040 L T moveo Supports New Gamrat regses Supo azro L TL pk L T Prusa LE T T wna r T T j Suppons Progam Counter Addressing Modes nee D 4 M68040 USER S MANUAL MOTOROLA APPENDIX E FLOATING POINT EMULATION M68040FPSP The MC68040 is user object code compatible with the MC68030 and 68881 68882 The MC68040 floating point unit is optimized to directly execute the most commonly used subset of the extensive MC68881 MC68882 instruction set through hardware Special traps and stack frames for the unimplemented instructions and data types provide support for the remaining instructions These functions coupled with
8. 3 2 6 2 S DOTIVISOr ell P 3 2 6 3 Write Protectorin 3 3 Address Translation 3 4 Transparent 3 5 Address Translation 3 6 MMU Effect RSTI and 5 3 6 1 Effect of RSTI on the MMUS esses a nnne 3 6 2 Effect of MDIS on Address Translation 3 7 MMU Instructions cao eo ouest 3 7 1 EE 3 7 2 tees 3 7 3 ad os OH t EUN RM 3 7 4 Register Programming Considerations MOTOROLA M68040 USER S MANUAL Page Number vii TABLE OF CONTENTS Continued Paragraph Page Number Title Number Section 4 Instruction and Data Caches 4 1 Cache Operation MERERI CN 4 2 4 2 Cache 4 5 4 3 4 6 4 3 1 Gachable ACcesses d epu ean d D Uie tara Ute 4 6 4 3 1 1 WhrtesThrougl Mod siii e eL ERREUR RR 4 6 4 3 1 2 Copyback Mode aan yea 4 6 4 3 2 Cache Inhibited Accesses a a 4 7 4 3 3 Special Accesses 4 7 4 4 Cache Protocol adum ee
9. 4 7 4 4 1 Read MISSz on EE 4 8 4 4 2 4 8 4 4 3 Read e EET 4 8 4 4 4 Wrile Hita eno da ooa n Luc ME 4 8 4 5 Cache Coherency ct LU 4 9 4 6 Memory Accesses for Cache 4 11 4 6 1 Cache PIG debo o taa De 4 11 4 6 2 Cache Push S nua eec plar e I Utm 4 13 4 7 Cache Operation 4 13 4 7 4 14 4 7 2 Dallas uma HEP 4 15 Section 5 Signal Description 5 1 Address Bus A93 19A0 ssc oc rn Eee o s RUE C rH ERU dE 5 4 5 2 Data Bus ias dus ede ot ee ol ein 5 5 5 9 Transfer Attribute Signals eem aae e treo ee ventre 5 5 5 3 1 Transfer Type TT1 TTO 5 5 5 3 2 Transfer Modifier 2 0 5 6 5 9 3 Transfer Line Number TLN1 TLN0 5 6 5 3 4 User Programmable Attributes UPA1 5 7 5 3 5 Read Write RAN iuc nen trate 5 7 5 3 6 Transfer Size S Z1 SIZO 5 7 5 3 7 DOCK EGO DAD tot 5 7
10. N RSTI 1 1 1 1 1 1 1 1 1 1 1 I 1 l l l l l l 1 Z CDIS MDIS lt 2 0 BUS SIGNALS _ Figure 7 44 Initial Power On Reset Timing Once RSTI negates the processor is internally held in reset for another 128 clock cycles During the reset period all signals that can be are three stated and the rest are driven to their inactive state Once the internal reset signal negates all bus signals continue to remain in a high impedance state until the processor is granted the bus Afterwards the first bus cycle for reset exception processing begins In Figure 7 44 the processor assumes implicit bus ownership before the first bus cycle begins The levels on CDIS MDIS and IPL2 IPLO are used to selectively enable the special modes of operation when RSTI is negated These signals should be driven to their normal levels before the end of the 128 clock internal reset period 7 66 M68040 USER S MANUAL MOTOROLA For processor resets after the initial power on reset RSTI should be asserted for at least 10 clock periods Figure 7 45 illustrates timings associated with a reset when the processor is executing
11. 5 10 Reset oai Ltda MM AB OMEN ea 5 11 Reset Out BS TO iac 5 11 Interrupt Control Signals eret inne 5 11 Interrupt Priority Level 1 2 1 eene 5 11 Interrupt Pending Status 5 12 Auto vector das re IER ER URDU SD FRA UE 5 12 Status And Clock 5 12 Processor Status PST3 PST0 5 12 Bus Clock BCLK ote coches etg aS Sa 5 14 Processor Clock PCLK Not on MC68040V and MC68ECO040V 5 14 MMU Disable MDIS Not MC68EC040 5 14 Data Latch Enable DLE Only 68040 5 14 ie ats Pree 5 15 uie CRG cv 5 15 Test Mode Select TMS esses 5 15 Test Data In T T u eei reote bea doe eere etd 5 15 Data Our CT DO 5 15 Test Reset TRST Not on MC68040V and MC68ECO40V 5 15 Power Supply Connections 5 15 Signal Summary eu 5 16 Section 6 IEEE 1149 1 Test Access Port JTAG 6 2 Instruction
12. m m m m m m m m m m m en m en m s 6 19 M68040 USER S MANUAL MOTOROLA num cell port function safe ccell dsval 114 4 D 29 input X amp 115 4 0 30 input X amp 116 BC_4 D 31 input X amp 117 2 A 9 output3 X 150 0 2 amp 150 io ab 118 BC 4 9 input X amp 119 2 8 output3 X 150 0 2 amp 120 4 input X amp 121 2 7 output3 X 150 0 2 122 4 7 input X amp 123 2 A 6 output3 X 150 0 2 amp 124 4 input X amp 125 2 A 5 output3 X 150 0 2 amp 126 BC_4 A 5 input X amp 127 2 4 output3 X 150 0 2 128 4 A 4 input X amp 129 BC 2 output3 X 150 0 2 amp 130 4 A 3 input X amp 131 2 A 2 output3 X 150 0 2 amp 132 4 A 2 input X amp 133 2 1 output3 X 150 0 2 amp 134 4 A 1
13. E 4 MOTOROLA M68040 USER S MANUAL xxiii SECTION 1 INTRODUCTION MC68040 MC68040V MC68LC040 MC68EC040 and MC68bECOA0V collectively called M68040 are Motorola s third generation of M68000 compatible high performance 32 bit microprocessors All five devices are virtual memory microprocessors employing multiple concurrent execution units and a highly integrated architecture that provides very high performance in a monolithic HCMOS device They integrate an MC68030 compatible integer unit IU and two independent caches The MC68040 MC68040V and MC68LCO040 contain dual independent demand paged memory management units MMUs for instruction and data stream accesses and independent 4 Kbyte instruction and data caches The MC68040 contains an MC68881 MC68882 compatible floating point unit FPU The use of multiple independent execution pipelines multiple internal buses and a full internal Harvard architecture including separate physical caches for both instruction and data accesses achieves a high degree of instruction execution parallelism on all three processors The on chip bus snoop logic which directly supports cache coherency in multimaster applications enhances cache functionality The M68040 family is user object code compatible with previous M68000 family members and is specifically optimized to reduce the execution time of compiler generated code All five processors implement Motorola s lates
14. 5171 i i BYTE 5120 i N l TT1 TTO l l l 1 1 I I I I I I 1 1 1 1 1 I 2 0 1 1 1 I I I l l l 1 1 1 1 I 1 I I I 1 I 1 1 1 1 1 D31 D0 ss __ gt BREAKPOINT ACKNOWLEDGE lt lt wer stack Figure 7 25 Breakpoint Interrupt Acknowledge Bus Cycle Timing 7 6 BUS EXCEPTION CONTROL CYCLES The M68040 bus architecture requires assertion of TA from an external device to signal that a bus cycle is complete TA is not asserted in the following cases The external device does not respond e No interrupt vector is provided Various other application dependent errors occur External circuitry can provide TEA when no device responds by asserting TA within an appropriate period of time after the processor begins the bus cycle This allows the cycle to terminate and the processor to enter exception processing for the error condition TEA can also be asserted in combination with TA to cause a retry of a bus cycle in error 7 36 M68040 USER S MANUAL MOTOROLA To properly control termination of a bus cycle for a bus error or retry condition TA and TEA must be asserted and negated for the same rising edge of BCLK Table 7 5 lists the control signal combinations and the resulting bus cycle terminations Bus error and retry terminations during burst cycles operate as described in 7 4 2 Line Read Transfers and 7 4 4 Line Wr
15. B 14 B 7 6 Output AC Timing Specifications B 15 B 7 7 Input AC Timing Specifications B 16 Appendix C MC68040V and MC68EC040V C 1 Additional Signal S te u e IS RII UN dac C 1 C 1 1 Low Frequency Operation eee C 2 C 1 2 loss ot GIOCK TIO caret diee eoi S Pa e e e ue eter h idt 2 C 1 3 System Clock Disable 5 C 2 C 2 Low Power Stop esses C 3 C 2 1 Bus Arbitration and Snooping rri ng 5 2 2 Low Frequency Operation oen rece 5 C 2 3 Changing BOLK Frequency en cite 5 2 4 LPSTOP Instruction Summary C 6 C 3 Clocking During Normal Operation 2 C 7 C 4 Reset Operation lt Cette tote e S octet C 7 5 Power IY uq s rene 9 6 68040 MC68ECO040V JTAG Preliminary 10 C 6 1 Instruction Shift Register d spore re eet C 11 C 6 1 1 EX WES t qut bn o naa 12 6 1 2 tet butt e C 12 C 6 1 3 SAMPLE PRELOAD una od UNDE C 12 C 6 1 4 CLAMP Sese tepore On ded C 12 C 6 1 5 BYPASS
16. 8 9 8 2 6 ger D 8 10 8 2 7 8 11 8 2 8 Breakpoint Instruction Exception 8 12 8 2 9 Interrupt EXOODIOD 8 12 8 2 10 Reset EXGODIOD eet ees 8 17 8 3 Exception Priorities 8 19 8 4 From Exc ptiens e t e cen ena hdc 8 20 8 4 1 Four Word Stack Frame Format 0 8 21 8 4 2 Four Word Throwaway Stack Frame Format 1 8 21 8 4 3 Six Word Stack Frame Format 2 8 22 8 4 4 Floating Point Post Instruction Stack Frame Format 3 8 23 8 4 5 Eight Word Stack Frame Format 4 8 23 8 4 6 Access Error Stack Frame Format 7 8 24 8 4 6 1 Effective unu 8 24 8 4 6 2 Special Status Word SSW 8 24 8 4 6 3 Write Back Status 8 26 8 4 6 4 Fault AOOICSS vic n He 8 26 MOTOROLA M68040 USER S MANUAL TABLE OF CONTENTS Continued Paragraph Page Number Title Number 8 4 6 5 Write Back Address and Write Back Data
17. MODE 012 5 WRITE HIT SINK DATA SNOOP OPERATION INDICATES amp SIZE zLINE READ OR WRITE SNOOP CONTROL ENCODING Figure 4 6 Data Cache Line State Diagram 4 16 M68040 USER S MANUAL MOTOROLA Table 4 4 Data Cache Line State Transitions Current State Cache Operation Invalid Cases Valid Cases Dirty Cases CPU Read Miss Read line from V1 Read line from D1 Buffer dirty cache line memory supply data memory supply data read new line from to CPU and update to CPU and update memory supply data cache go to valid cache replacing old to CPU and update state line remain in current cache write buffered state dirty data to memory go to valid state CPU Read Hit Not Possible V2 Supply data to CPU D2 Supply data to CPU remain in current state remain in current state CPU Write Miss Read line from V3 Read line from D3 Buffer dirty cache line Copyback memory into cache memory into cache read new line from write data to cache replacing old line memory write data to set Dn bits of modified write data to cache cache and set Dn bits long words go to dirty and set Dn bits go to write buffered dirty state dirty state data to memory remain in current state CPU Write Hit Copyback Not Possible V5 Write data into cache D5 Write data in cache set Dn bits of modified set Dn bits of modified long words go to dirty long words remain in state curre
18. POLK Puse wan Hon 157 1050 7 s sss ess PUK Puse Low 157 1050 7 s sss 675 o s s ow Borse aaran a Ta Bork buy Coe measured rsv 4 oo oo Bouk Frequency Suy 109 1000 o9 pom ruesuksem _______ _ _ Specification value at maximum frequency of operation PCLK BCLK Figure 11 1 Clock Input Timing Diagram MOTOROLA M68040 USER S MANUAL 11 3 11 6 OUTPUT AC TIMING SPECIFICATIONS Figures 11 3 to 11 7 Characteristic BCLK to Address CIOUT LOCK LOCKE R W SIZx TLN TMx TTx 16 5 25 24 ns UPAx Valid 12 BCLK to Output Invalid Output Hold 13 BCLK to TS Valid 4 1 BCLK to Valid 24 184 BCLK to Data Out Valid BCLK to Data Out Invalid Output 2 Hold 203 4 BCLK to Output Low Impedance 215 BCLK to Data Out High Impedance 263 BCLK to Multiplexed 19 13 32 Address Valid 273 5 BCLK to Multiplexed 19 13 Address Driven 283 4 5 BCLK to Multiplexed Address 525 44 High Impedance 945 BCLK to Multiplexed 19 13 19 Data Driven 304 BCLK to Multiplexed Data Valid 19 BCLK to Address CIOUT LOCK LOCKE R W SIZx TS TLNx TMx 5 25 14 n UPAx
19. s SFC ALTERNATE SOURCE AND DESTINATION DFC FUNCTION CODE REGISTERS 31 0 2 CACR CACHE CONTROL REGISTER Figure 2 4 Integer Unit Supervisor Programming Model The supervisor programming model consists of the registers available to the user as well as the following control registers Two 32 Bit Supervisor Stack Pointers ISP MSP 16 Bit Status Register SR 32 Bit Vector Base Register VBR Two 32 Bit Alternate Function Code Registers Source Function Code SFC and Destination Function Code DFC 32 Bit Cache Control Register The following paragraphs describe the supervisor programming model registers Additional information on the ISP MSP SR and VBR registers be found in Section 8 Exception Processing 2 2 2 1 INTERRUPT AND MASTER STACK POINTERS In a multitasking operating system it is more efficient to have a supervisor stack pointer associated with each user task and a separate stack pointer for interrupt associated tasks The M68040 provides two supervisor stack pointers master and interrupt Explicit references to the SSP refer to either the MSP or ISP while the processor is operating in the supervisor mode All instructions that use the SSP implicitly reference the active stack pointer The ISP and MSP are general purpose registers and can be used as software stack pointers index registers or base address registers The ISP and MSP can be used for word and long
20. 5 4 6 1 M68040 Test Logic Block 6 2 6 2 Bypass o caste a to 6 6 6 3 Output batch Gell CES 6 7 6 4 petto 6 7 6 5 Output Control Cells iss dete e Du ts odes et oti era tue 6 8 6 6 General Arrangement of Bidirectional 6 8 6 7 Circuit Disabling IEEE Standard 1149 1 6 14 6 8 Clock Inpat Timing Diagram erer ences uno ee iio etat qae ect reo ee Ban emp ea 6 22 6 9 TRST Timing Diagrami aca rre Gee tar Dat 6 22 6 10 Boundary Scam Timing DIagE atri 6 23 6 11 Test Access Port Timing Diagram 6 23 7 1 Signal Relationships to 7 2 7 2 Internal Operand Representation 7 3 7 3 e 7 4 7 4 Byte Enable Signal Generation and PAL Equation 7 5 7 5 Example of a Misaligned Long Word Transfer 7 7 7 6 Example of a Misaligned Word Transfer 7 7 7 7 Misaligned Long Word Read Transfer Timing 7 8 7 8 Byte Word and Long Word Read Transf
21. BFEXTS BFEXTUb d ea ea ea Calculate Calculate Calculate An An d16 An d 16 PC xxx W xxx L lt gt dg An Xn dg PC Xn BR Xn bd BR Xn pd BR Xn pd BR Xn bd BR Xn od NOTES ees eee eee 1 J asr UC EGER AE az as Eum Sp 29 L9 as as I s 0 a Bitinstruction ea calculate and execute times T1 T2 apply to lt xxx gt Dn bit numbers b This instruction interlocks the ea calculate and execute stages c If the bit field spans long word boundary add ten and nine clocks to the ea calculate and execute times respectively Two memory addresses are accessed in this case d Ifthe bit field spans a long word boundary add two clocks to the execute time Two memory addresses are accessed in this case e Immediate count specified for both width and offset and width and or offset specified in register respectively MOTOROLA M68040 USER S MANUAL 10 15 10 6 INTEGER UNIT INSTRUCTION TIMINGS Continued BFINS 3C BFTST8 Addressing ea lt gt lt gt Calculate Calculate Calculate An An as 9 asr 9
22. ROOT LEVEL POINTER LEVEL PAGE LEVEL TABLES TABLES TABLES Figure 3 13 Example Translation Table Using the indirection capability single entries or entire tables can be shared between multiple tasks Figure 3 14 illustrates two tasks sharing a page using indirect descriptors When the M68040 has completed a normal table search it examines the PDT field of the last entry fetched from the page tables If the PDT field contains an indirect 2 encoding it indicates that the address contained in the highest order 30 bits of the descriptor is a pointer to the page descriptor that is to be used to map the logical address The processor then fetches the page descriptor from this address and uses the physical address field of the page descriptor as the physical mapping for the logical address The page descriptor located at the address given by the indirect descriptor must not have a PDT field with an indirect encoding it must be either a resident descriptor or invalid Otherwise the descriptor is treated as invalid and the M68040 creates an ATC entry with a signaled error condition R bit in MMUSR is clear MOTOROLA M68040 USER S MANUAL 3 17 LOGICAL ADDRESS ROOT INDEX POINTER INDEX PAGE INDEX PAGE OFFSET TABLE ENTRY 3B 15 01 ADDRESS OFFSET EC 54 04 TABLE 00 TABLE 00 TABLE 00 gt TABLE 3B TABLE 15 ROGTPOINTER TASKA 3B 00001800
23. D31 D0 OUT ALT MASTER READ 6 TA OUT 2 lt gt Figure C 15 Snoop Hit Timing C 26 M68040 USER S MANUAL MOTOROLA RAW IN 5 1 5 0 ___ ____ _ gt TS IN 3 lt gt id gt 403 lt gt a BB IN Figure C 16 Snoop Miss Timing MOTOROLA M68040 USER S MANUAL C 27 6 gt IPEND RSTO PST3 PSTO MDIS IP L2 IPLO NOTE on MC68EC040V Figure C 17 Other Signal Timing C 28 M68040 USER S MANUAL MOTOROLA 1 0 mm 8 gt mu X 5 5171 5170 X RN N Aj 2 A 4 LOCK LOCKE Lo v BR 557 C 39 N 2 N gt 015 00 lt PST3 PSTO 6 AN SCD N v ec BB IN gt 2 Figure 18 Going into LPSTOP with Arbitration MOTOROLA M68040 USER S MANUAL C 29 A31 A0 TT1 TTO TM2 TMO 5121 5120 RW D15 D0 TA PST3 PSTO SCD BB OUT BG BR 6 gt lt N N Figure C 19 LPSTOP no Arbitration CPU is Master 30 M68040 USER S MANUAL MOTOROLA P 124 wF 0 IPL2 IPLO X VALID INTERRUPT i SCD i um lt
24. POSSIBLE THE 040 LOCK IS INDETERMINATE ACTIVELY VIOLATED CONDITION OWNS THE BUS HERE indicates the alternate bus master Figure 7 31 Lock Violation Example In addition to the indeterminate condition the external arbiter s design needs to include the function of BR For example in certain cases associated with conditional branches the M68040 can assert BR to request the bus from an alternate bus master then negate BR without using the bus regardless of whether or not the external arbiter eventually asserts BG This situation happens when the M68040 attempts to prefetch an instruction for a conditional branch To achieve maximum performance the processor prefetches the instructions of both paths for a conditional branch If the conditional branch results in a branch not taken the previously issued branch taken prefetch is then terminated since the prefetch is no longer needed In an attempt to save time the M68040 negates BR If BG takes too long to assert the M68040 enters a disregard request condition The BR signal can be reasserted immediately for a different pending bus request or it can stay negated indefinitely If an external bus arbiter is designed to wait for the M68040 to assert BB before proceeding then the system experiences an extended period of time in which bus arbitration is locked Motorola recommends that an external bus arbiter not assume that there is a direct relationship between BR and BB or
25. ute ae RE eae 1 9 1 8 Addressing Capabilities 1 9 1 9 Notational Conventions 1 11 1 10 Instruction Set OVOIVIGW 1 13 Section 2 Integer Unit 2 1 Integer Unit PIBellhg astaun 2 1 2 2 Integer Unit Register Description 2222 2 4 2 2 1 Integer Unit User Programming 2 4 2 2 1 1 Data Registers D7 DO eese 2 4 2 2 1 2 Address Registers 6 0 2 4 2 2 1 3 System Stack Pointer A7 2 5 2 2 1 4 Program te be cbe 2 5 2 2 1 5 Condition Code Register i 2 5 2 2 2 Integer Unit Supervisor Programming Model 2 5 2 2 2 1 Interrupt and Master Stack Pointers 2 6 2 2 2 2 Status Register x i RE E 2 7 2 2 2 3 Vector Base 2 7 2 2 2 4 Alternate Function Code Registers 2 7 2 2 2 5 Cache Control 2 8 vi M68040 USER S MANUAL MOTOROLA TABLE OF CONTENTS Continued
26. E Denormaized J umomazed t 1 Data Format Type Supported by On Chip MC68040 FPU Hardware TData Format Type Supported by Software MC68040FPSP MOTOROLA M68040 USER S MANUAL 9 7 Table 9 3 Single Precision Real Format Summary Data Format 30 23 22 270879 052 255 01900 26 678 01 01900 01 00 255 01 04 7 Representation of Fraction Nonsignaling Signaling Nonzero Bit Pattern Created by User Fraction When Created by FPCP M68040 USER S MANUAL MOTOROLA Table 9 4 Double Precision Real Format Summary Data Format 63 02 52 51 5 Field Size in Bits Sign s Biased Exponent e Fraction f Total Interpretation of Sign Positive Fraction Negative Fraction Normalized Numbers Bias of Biased Exponent 1023 Range of Biased Exponent 0 e 2047 7FF Range of Fraction Zero or Nonzero Fraction 1 f Relation to Representation of Real Numbers C1 8 x 28 1023 x 14 Denormalized Numbers Biased Exponent Format Minimum 0 000 Bias of Biased Exponent 1022 Range of Fraction Nonzero Fraction 04 Relation to Representation of Real Numbers 1 1022 x 0 f Signed Zeros Biased Exponent Format Minimum 0 00 Fraction Mantissa Significand 0 f 0 0 Signed Infinities Biased Exponent Format Maximum 2047 7FF Fraction 0 f 0 0 Sign Biased
27. i sci tb b eio Ve B 18 M68040 USER S MANUAL MOTOROLA LIST OF ILLUSTRATIONS Continued Figure Page Number Title Number B 10 Snoop PIE TIMING dete 19 B 11 Snoop MISS TITIO suo iio coepere B 20 B 12 Other Signal aoc eee i B 21 C 1 MC68040V and MC68ECO040V Functional Signal Groups C 3 C 2 MC68040V and MC68ECO0A0V Initial Power On Reset Timing C 8 C 3 MC68040V and MC68ECO040V Normal Reset Timing C 9 C 4 MC68040V and MC68ECO040V Test Logic Block Diagram C 11 5 Bypass Register ba ees De ade C 13 C 6 Output Latch Cell O Latch t C 14 C 7 Input Pin Cell I Pin RAE C 14 C 8 Output Control Cells IO Ctl 4 4 C 15 C 9 General Arrangement of Bidirectional C 15 C 10 Circuit Disabling IEEE Standard 1149 1 C 17 C 11 Drive Levels and Test Points for AC Specifications C 18 C 12 Clock Input Timing Diagram oq ot RU cane doceo e ebrei C 21 13 Read Write TETUER C 24 14 Bus Arbitration C 25 C15 Snoop Ht T
28. j Deomaized Supported by M68040FPSP T Supported by the MC68040 FPU Supported by M68040FPSP after being converted to extended precision by the MC68040 FPU The M68040FPSP provides system designers with a simple path to port existing MC68881 MC68882 exceptions handlers to the MC68040 It also provides an entry point for the IEEE defined exception conditions listed in Table E 4 Table E 4 Exception Conditions The M68040FPSP is written 68000 family assembly code and comes with an installation guide Tape contains both Motorola syntax and UNIX as syntax Tape cartridge M68040FPSPT media is available in CPIO and TAR formats Also available is 9 track M68040FPSPP media in high or low density as well as CPIO and TAR formats A license is required to obtain rights to use and distribute the M68040FPSP License terms include the right to use and modify source code and redistribute resulting object code E 4 M68040 USER S MANUAL MOTOROLA INDEX Ac Access Control Unit 1 2 B 4 B 5 Access Control Unit Register B 5 Field Definitions B 6 B 7 Access Error 1 5 3 22 3 23 3 24 5 14 7 37 7 43 8 20 9 21 A 6 A 7 B 11 Access Fault 3 9 8 6 8 7 Access Serialization 7 44 Acknowledge Bus Cycle Breakpoint Operation 7 29 7 35 9 20 Interrupt Operation 5 12 7 31 7 29 7 35 8 2 Address Bus 7 1 Address Colli
29. A24 GND A30 027 GND D31 C O _ 221 00 02 Vcc GND GND Vcc GND Vcc GND Vcc GND Vcc 023 075 Vcc 028 B O O O O O 29 GND 01 GND Vcc GND 08 GND Vcc GND 016 018 GND Vcc GND 022 GND 076 A O O O A31 D3 04 05 06 07 9 010 011 012 013 014 015 017 019 020 D21 074 1 2 3 4 5 6 7 8 9 10 1 12 13 14 15 16 17 18 mew Go Xe O O Internal Logic C6 C7 C9 C11 C13 16 13 M16 C5 C8 C10 C12 C14 H16 J3 J16 116 R11 R13 S6 S10 T4 MS R5 R12 Output Drivers B2 B4 B6 B8 B10 B13 B15 B17 D2 D17 B5 B9 B14 C2 C17 G2 G17 M2 M17 R2 F2 F17 H2 H17 L2 L17 N2 N17 Q2 Q17 R17 S16 S2 515 517 12 4 M68040 USER S MANUAL MOTOROLA 12 2 4 68040 MC68ECO40V Pin Grid Array T NIC GND 2 IPLI 1 0 NC TCI AVEC SCO BG PSTO PST3 BB BR 5 O O O IPEND TDI TCK TMS WDIS RST Vcc GND GND TBI 5 1 TEA 5 GND Vcc GND LOCK R 13 TOUT vec RSTO GND ie GND BCLK Vcc 152 GND GND Vcc GND PST2 TP TS Vcc LOCKE Q UPAL GND UPAO MI GND TLNO P 10 TTO 5121 5120 N 12 GND RW GND TMO Ov
30. 2 1 SELECT ROUNDING MODE T us AND LSB 1 ROUND AND STICKY 0 OR INTERMEDIATE INTERMEDIATE GUARD 1 RESULT RESULT ROUND OR STICKY 1 ADD1TO LSB EXACT RESULT GUARD ROUND AND STICKY ARE CHOPPED OVERFLOW 1 SHIFT MANTISSA RIGHT 1 BIT Q ADD 1 TO EXPONENT GUARD 0 ROUND 0 STICKY EXIT EXIT Figure 9 8 Rounding Algorithm Flowchart The three additional bits beyond the extended precision format the difference between the intermediate result s 67 bit mantissa and the stored result s 64 bit mantissa allow the FPU to perform all calculations as though it were performing calculations using a float engine with infinite bit precision The result is always correct for the specified destination s data format before performing rounding unless an overflow or underflow error occurs The specified rounding operation then produces a number that is as close as possible to the infinitely precise intermediate value and still representable in the selected precision 9 14 M68040 USER S MANUAL MOTOROLA The following tie case example illustrates how the 67 bit mantissa allows the FPU to meet the error bound of the IEEE specification Result Integer 62 BitFraction Guard Round Sticky x 1 o 9 The least significant bit of the rounded result does not increment even though the guard b
31. Po po _ _ _ _ 10 5 MISCELLANEOUS INTEGER UNIT INSTRUCTION TIMINGS ABCD E Dx Ay Ax ADDX ap LI Branch Taken Branch Not Taken Branch Not Taken BSR offset 520 True False CMPM False Count gt 1 False Count 1 True EORI lt xxx gt CCR EORI lt xxx gt SR Word Long Word EXTB Long Word ILLEGAL A Line Unimplemented F Line Unimplemented MOVE USP USP An An USP MOVE16 9 Ax Ay xxx L An xxx L An xxx L An xxx L MOVECP MOVEP W Dn d16 An MOVEP L Dn d16 An MOVEP W d16 An Dn MOVEP L d16 An Dn e ANDI lt xxx gt 1 1 61 49 6 44 1 2 1 21 1 11 6 ej 1 6 1 10 M68040 USER S MANUAL 10 11 10 5 MISCELLANEOUS INTEGER UNIT INSTRUCTION TIMINGS Continued 10 12 PACK i lt gt lt gt RTE8 Stack Format 0 Stack Format 1 Stack Format 2 Stack Format 3 Stack Format 4 Stack Format 7 SWAP Not Taken UNPK pom 3 2L 3 13 1 3 11 11 27 11 25 21 5 2 4 2 3 2 4 1 3 1 3 1 3 NOTES a Times listed minimum This instruction interlocks the ea calculate and execute stages and synchronizes
32. m XN BG a AE AM BR l AM BG Autant MASTER gt gt PROCESSOR LONG WORD WRITE AM indicates the alternate bus master Figure 7 43 Snooped Long Word Write Memory Inhibited 7 10 RESET OPERATION An external device asserts the reset input signal RSTI to reset the processor When power is applied to the system external circuitry should assert RSTI for a minimum of 10 BCLK cycles after Vcc is within tolerance Figure 7 44 is a functional timing diagram of the power on reset operation illustrating the relationships among Vcc RSTI mode selects and bus signals The BCLK and PCLK clock signals are required to be stable by the time Vcc reaches the minimum operating specification The levels of the clocks MOTOROLA M68040 USER S MANUAL 7 65 should not exceed Vcc while it is ramping up RSTI is internally synchronized for two BCLKS before being used and must meet the specified setup and hold times to BCLK specifications 51 and 52 in Section 11 MC68040 Electrical and Thermal Characteristics only if recognition by a specific BCLK rising edge is required MI is asserted while the M68040 is in reset lt t210 gt lt 2 gt lt 128 gt CLOCKS CLOCKS CLOCKS LU e PLE ese T s ii dU e M 204000006001 do xs M
33. 8 26 8 4 6 6 Mende ES 8 27 8 4 6 7 Access Error Stack Frame Return From Exception 8 27 Section 9 Floating Point Unit MC68040 Only 9 1 Floating Point Unit Pipeline 9 1 9 2 Floating Point User Programming 9 2 9 2 1 Floating Point Data Registers 7 9 2 9 2 2 Floating Point Control Register FPCR 9 3 9 2 2 1 Exception Enable Byte 9 3 9 2 2 2 Mode Control Byte n cnin dee udis 9 3 9 2 3 Floating Point Status Register FPSR 9 4 9 2 3 1 Floating Point Condition Code Byte 9 4 9 2 3 2 Quotient emite ias 9 5 9 2 3 3 Exception Status 9 5 9 2 3 4 Accrued Exception Byte 9 5 9 2 4 Floating Point Instruction Address Register FPIAR 9 6 9 3 Floating Point Data Formats and Data 9 7 9 4 Gormpultatiorial ACCURACY oce ceo nes tt Fete ere hin nean dd 9 11 9 4 1 Intermediate 9 12 9 4 2 Rounding the Result enemies mirer rre tec 9 13 9 5 Post
34. ave o a az a lt gt NOTES a b C 10 16 This instruction interlocks the ea calculate and execute stages If the bit field spans a long word boundary add two clocks to the execute time Two memory addresses are accessed in this case If the bit field spans a long word boundary add seven clocks to both the ea calculate and execute times Two memory addresses are accessed in this case If the bit field spans a long word boundary add ten and nine clocks to both the ea calculate and execute times respectively Two memory addresses are accessed in this case M68040 USER S MANUAL MOTOROLA 10 6 INTEGER UNIT INSTRUCTION TIMINGS Continued Addressing ea ea ea Calculate Calculate Calculate USE ARE ANA ER eae eae oem TER TES BAX BR 5 a Bit instruction ea calculate and execute times T1 T2 apply to lt xxx gt Dn bit numbers b Times listed are typical This instruction interlocks the ea calculate and execute stages and synchronizes some portions of the processor before execution c This instruction interlocks the ea calculate and execute stages d Times listed are for Dn within bounds This instruction interlocks the ea calculate and execute stages MOTOROLA M68040 USER S MANUAL 10 17 10
35. 25MHz 33MHz e Characteristic c Hi Read Followed by Write Ezz ipw e ep ms vanoas zs TeivatsioBCuK Seu _______ sexes rex es MSIE e 25 vata How s a Re CRT Ed CI RE Eavan eck se 7 a feee e a BCLK to BB BG CDIS IPLx Invalid 25 Hold rir r EAT m E BON sn ESI NC 1 a ES BCLK to Address SIZx TTx R W SCx 25 Invalid Hold 47 mamon MC68EC040 Assumes Bus Mastership 16 M68040 USER S MANUAL MOTOROLA A31 A0 TRANSFER ATTRIBUTES TS TIP D31 D0 IN READ D31 D0 OUT WRITE TA TEA TCI TBI NOTE Transfer Attribute Signals UPAx SIZx TTx TMx TLNx R W LOCK LOCKE CIOUT MOTOROLA Figure B 8 Read Write Timing M68040 USER S MANUAL A31 A0 TRANSFER ATTRIBUTES LOCK LOCKE TIP D31 D0 OUT WRITE BR lt gt 2 lt gt mr 0 gt 41 lt gt M
36. This three state output is asserted to indicate that a bus transfer is in progress and is negated during idle bus cycles if the bus is still granted to the processor When the processor loses the bus TIPnegates after completion of the current transfer and goes to a high impedance state Note that TIPis kept asserted on back to back bus cycles 5 4 3 Transfer Acknowledge TA This three state bidirectional signal indicates the completion of a requested data transfer operation During transfers by the M68040 TA is an input signal from the referenced slave device indicating completion of the transfer During alternate bus master accesses TA is normally three stated to allow the referenced slave device to respond and the M68040 samples it to detect the completion of each bus transfer The M68040 can inhibit memory and intervene in the access to source or sink data in its internal caches by asserting TA to acknowledge the data transfer This capability applies to alternate bus master accesses that reference modified dirty data in the M68040 caches 5 4 4 Transfer Error Acknowledge TEA The current slave asserts this input signal to indicate an error condition for the bus transaction When asserted with TA this signal indicates that the processor should retry 5 8 M68040 USER S MANUAL MOTOROLA the access During alternate bus master accesses the M68040 samples TEA to detect completion of each bus transfer 5 4 5 Transfer Cac
37. c dtt e gv E NE Difesa ph Dii enda C 13 C 6 2 Boundary Scan soo rot esci C 13 C 6 3 PRECES 16 6 4 Disabling The IEEE Standard 1149 1A Operation C 16 C 6 5 MC68040V and MC68bECO040V JTAG Electrical Characteristics C 17 MOTOROLA M68040 USER S MANUAL XV TABLE OF CONTENTS Continued Paragraph Number Title C 7 MC68040V and 6 40 Electrical Characteristics C 7 1 Maximum Ratings EE Beto C 7 2 Thermal Characteristics C 7 3 DC Electrical Specifications C 7 4 Power Dissipation o 7 5 Clock AC Timing Specifications C 7 6 Output AC Timing C 7 7 Input AC Timing Specifications Appendix D M68000 Family Summary Appendix E Floating Point Emulation M68040FPSP Index xvi M68040 USER S MANUAL Page Number MOTOROLA LIST OF ILLUSTRATIONS Figure Page Number Title Number 1 1 Block DIagE alo uo ie cients 1 4 1 2 Programming aic ovas pint eid gee uut 1 7 2 1 Inte
38. han L eem qot uere e eer f an f qanm 1 1 queen eren x qa 85555925 4e ey w neon acoso en ao TET ba RI ad a Except for Dn and lt xxx gt cases add one clock to execute times for MOEA W b This instruction interlocks the ea calculate and execute stages c D and indicate the number of data and address registers respectively if no data registers specified the number one For MOVEM W lt ea gt lt list gt add N 2 and clocks to ea calculate and execute times respectively for N address registers specified MOTOROLA M68040 USER S MANUAL 10 23 10 6 INTEGER UNIT INSTRUCTION TIMINGS Oe lt gt ea MOVES lt gt lt gt ___ 5 lt gt cea Addressing ea ea ea Mode mr Tm ni em Oa ENS ERE NAT lt XXX gt Times listed are typical This instruction interlocks the ea calculate and execute stages and synchronizes some portions of the processor before execution 10 24 M68040 USER S MANUAL MOTOROLA 10 6 INTEGER UNIT INSTRUCTION TIMINGS Continued Addressing S m T
39. w w L TER TES xe eo eum uve IET CE 9 9 uso ba Multiply lt ea gt calculate and execute times T1 T2 apply to word long word operand size MOTOROLA M68040 USER S MANUAL 10 25 10 6 INTEGER UNIT INSTRUCTION TIMINGS Addressing lt ea gt lt ea gt lt ea gt An 416 416 ave Immediate count specified for shift count shift count specified in register respectively 10 26 M68040 USER S MANUAL MOTOROLA 10 6 INTEGER UNIT INSTRUCTION TIMINGS Addressing ea lt gt lt gt Calculate E Immediate count specified for shift count shift count specified in register respectively MOTOROLA M68040 USER S MANUAL 10 27 10 6 INTEGER UNIT INSTRUCTION TIMINGS ms Mode Calculate Calculate Calculate s poe ael code C j j An posu Any 3d M 16 pod 1 16PC ____ W xC Jj j r TUS RECEN 07 oe _ __ j T RJ ss T J 1 Times listed typical This instruction interlocks the ea calculate and execute stages
40. 2 so 22 5 29 2 so Ay 4 epp e seo ie 9 d MOTOROLA M68040 USER S MANUAL 10 35 10 7 3 Timings in the Floating Point Unit Continued eto T oponse emen comedor amati m z Dese 8 s ag FSQRT nes Norm Zero S o 10 36 M68040 USER S MANUAL MOTOROLA 10 7 3 Timings in the Floating Point Unit Concluded instruction Opclass Size Precision Operands Conversion Execution Normalization 9 39 HIS NETS a a a zozo a o o e e emt y M68040 USER S MANUAL 10 37 n 10 38 M68040 USER S MANUAL MOTOROLA SECTION 11 MC68040 ELECTRICAL AND THERMAL CHARACTERISTICS The following paragraphs provide information on the maximum rating and thermal characteristics for the MC68040 This section is subject to change For the most recent specifications contact a Motorola sales office or complete the registration card at the end of this manual 11 1 MAXIMUM RATINGS characterise vae ua Missis a Ne LES ed inputs are tied to an appropriate 11 2 THERMAL CHARACTERISTICS logic voltage level e g
41. 228 12 13 14 18 19 20 21 BCLK to Address LOCK LOCKE RW 517 TS TLNx TMx UPAx High Impedance BCLK to High Impedance BCLK to BR BB Valid 39 BB TIP Hi 40 BR BB Vali _ 5 Output timing is specified for valid signal measured at the pin Timing is specified driving an unterminated 30 Q transmission line with a length characterized by 2 5 ns one way propagation delay Buffer output impedance is typically 30 O the buffer specifications include approximately 5 ns for the signal to propagate the length of the transmission line and back 30 30 30 32 20 18 28 30 30 30 30 100 100 2 13 e 18 9 20 EN 2 Ho 48 c 22 M68040 USER S MANUAL MOTOROLA 7 7 Input AC Timing Specifications see Figures C 13 to C 21 PRELIMINARY __ PREMMNARY 0 6 _ 25MHz 33MHz m w siz i i E T BCLK to Data In High Read Followed by Write m presens 3 wees Ts Tu r revoca a muraria 2 Ls BCLK to AVEC Invalid Hold Ww LL sp s P ojx COIS Vali
42. END OF BURST 1 NEGATE TIP IF REQUIRED START NEXT CYCLE Figure 7 10 Line Read Transfer Flowchart 7 14 M68040 USER S MANUAL MOTOROLA i l A2 A0 1 UPAO X X 5171 5170 1 1 1 1 1 1 1 1 RW i i i i CIOUT i 5 V 4 i i i AT l l l l l 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 NOTE The selected device increments the value of A3 and A2 Figure 7 11 Line Read Transfer Timing Clock 1 C1 The line read cycle starts in C1 During the first half of C1 the processor places valid values on the address bus and transfer attributes For user and supervisor mode accesses that are translated by the corresponding memory unit the UPAx signals are driven with the values from the matching U1 and UO bits The TTx and TMx signals identify the specific access type The R W signal is driven high for a read cycle and the size signals SIZx indicate line size CIOUT is asserted for a 16 operand read if the access is identified as noncachable Refer to Section 3 Memory Management Unit MOTOROLA M68040 USER S MANUAL 7 15 Except 68 040 and MC68ECO40V for information on M68040 MC68LC040 memory units and Appendix MC68EC040 for information on the MC68EC040 memory unit The processor
43. 16 BR Xn bd BR Xn bd BR Xn od bd BR Xn bd BR Xn od aja a2 o 5 2 An An xxx W xxx L lt XXX gt 8 16 BR Xn bd BR Xn bd BR Xn od bd BR Xn bd BR Xn od ele ols 2 Z DESTINATION ea Calculate 12 12 4 M68040 USER S MANUAL Calculate 5 xxx W xxx L 10 9 10 4 MOVE INSTRUCTION TIMING Continued SOURCE 2 E An An gt 5 xxx o fo o lt gt 16 BR Xn bd BR Xn bd BR Xn od bd BR Xn bd BR Xn od 3183 Slelelelala 7 gt 5 gt 5 a 2 CIN 2 _ gt 5 I L lt XXX gt 8g An Xn y gt 5 5 16 BR Xn bd BR Xn bd BR Xn od bd BR Xn bd BR Xn od 10 10 dg An Xn ea Calculate 1 1 1 1 1 2 2 2 2 DESTINATION b16 An Xn ea Calculate 11 a E 16 17 M68040 USER S MANUAL bd An Xn lt ea gt Calculate 14 16 19
44. 21 input X 33 2 output3 X 150 0 Z 34 4 22 input X 35 2 23 output3 X 150 0 Z 36 4 A 23 input X 37 2 24 output3 X 150 0 2 38 4 A 24 input X 39 2 25 output3 X 150 0 7 40 4 A 25 input X 41 2 26 output3 X 150 0 2 42 4 26 input X 43 2 27 output3 X 150 0 Z 44 4 27 input X 45 BC 2 28 output3 X 150 0 7 46 BC 4 28 input X 47 2 A 29 output3 X 150 0 7 48 4 A 29 input X 49 2 30 output3 X 150 0 Z 50 4 30 input X 51 2 31 output3 X 150 0 2 52 4 31 input X 53 BC 2 000 output3 X 151 0 2 151 io db 54 2 D 1 output3 X 151 0 Z 55 BC 2 D 2 output3 X 151 0 Z 56 BC 2 003 output3 X 151 0 2 6 18 M68040 USER S MANUAL MOTOROLA ccell dsval safe function port cell num RnR
45. Lim ws 10 onm ws 102 Lim ws 10 we 1 im e O An 10 D 07 o 1 wx 1 4 4 5 5 6 6 7 7 8 8 9 9 0 0 1 1 3 A2 3 A2 3 A2 4 A2 4 A2 4 A2 4 A2 4 A2 4 A2 4 A2 4 A2 4 A2 4 5 5 5 5 5 D1 5 D2 5 D3 5 D4 5 D5 5 D7 6 6 6 10 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 70 71 72 73 MOTOROLA Table 6 2 Boundary Scan Bit Definitions Continued Pin Cell Cell Type Name Pin Type Ctrl Cell ouem vm 2 oran 10 e 10 oram 7 oran 65 10 7 7 oran ve 10 ve vo 7 7 Lim 0 m Lim e Lim im Lim 6 Lim os or n m 1 nf D2 D2 D2 D2 D2 D2 D2 D2 D2 D3 D3 D1 D2 D3 D4 D5 D7 100 74 75 76 77 78 79 81 82 83 84 85 87 88 91 92 93 94 95 7 9 D2 2 105 106 107 108 109 110 1 2 3 4 5 6 7 8 9 0 1 1 MOTOROLA M68040 USER S MANUAL Pin Cell Type Name Pin Type Ctrl Cell I Pin O Latch I Pin O Latch I Pin O Latch I Pin
46. MOTOROLA M68040 User s Manual Including the MC68040 MC68040V MC68LC040 MC68EC040 and MC68EC040V INC 1990 Revised 1992 1993 Motorola reserves the right to make changes without further notice to any products herein to improve reliability function or design Motorola does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part Motorola and the 4 are registered trademarks of Motorola Inc Motorola Inc is an Equal Opportuni
47. MOTOROLA M68040 USER S MANUAL 7 25 7 4 5 Read Modify Write Transfers Locked Transfers The read modify write transfer performs a read conditionally modifies the data in the processor and writes the data out to memory In the M68040 this operation can be indivisible providing semaphore capabilities for multiprocessor systems During the entire read modify write sequence the M68040 asserts the LOCK signal to indicate that an indivisible operation is occurring and asserts the LOCKE signal for the last transfer to indicate completion of the locked sequence The external arbiter can use the LOCK and LOCKE signals to prevent arbitration of the bus during locked processor sequences External bus arbitrations can use LOCKE to support bus arbitration between consecutive read modify write cycles A read modify write operation is treated as noncachable If the access hits in the data cache it invalidates a matching valid entry and pushes a matching dirty entry The read modify write transfer begins after the line push if required is complete however LOCK may assert during the line push bus cycle The TAS CAS and CAS2 instructions are the only M68040 instructions that utilize read modify write transfers Some page descriptor updates during translation table searches also use read modify write transfers Refer to Section 3 Memory Management Unit Except 68 040 and MC68ECO040V for information about table searches The
48. NOTE Transfer Attribute Signals UPAx SIZx TTx TMx TLNx R W CIOUT B 18 Figure B 9 Bus Arbitration Timing M68040 USER S MANUAL MOTOROLA R W IN TS D31 D0 ALT MASTER 7 WRITE D31 D0 OUT ALT MASTER READ 6 TA OUT Figure B 10 Snoop Hit Timing MOTOROLA M68040 USER S MANUAL B 19 RAW IN SC1 50 47 TS IN 3 lt gt j B gt 403 lt gt mL BB IN Figure B 11 Snoop Miss Timing B 20 M68040 USER S MANUAL MOTOROLA 60 lt gt IPEND RSTO PST3 PSTO CDIS IPL2 IPLO Figure B 12 Other Signal Timing MOTOROLA M68040 USER S MANUAL B 21 B 22 M68040 USER S MANUAL MOTOROLA APPENDIX MC68040V AND MC68bEC040V The MC68040V and MC68ECO040V are Motorola s 3 3 volt static versions of the MC68040 third generation M68000 compatible high performance 32 bit microprocessor They require a 3 3V power supply providing over 50 percent reduction in power consumption compared to a 5 0V device The maximum power used at 3 3 volts is 1 5 watts at an operating frequency of 33 MHz They also have a low power stop mode Once in this state both devices remain quiescent consuming less than 330 uW of power The low power usage of these microprocessors makes them an ideal choice for portable computing and power constrained applications The MC68040V progr
49. Paragraph Number Title Section 3 Memory Management Unit Except 68 040 and MC68bECO040V 3 1 Memory Management Programming 3 1 1 User and Supervisor Root Pointer Registers 3 1 2 Translation Control Register 3 1 3 Transparent Translation Registers 3 1 4 MMU Status Register ido cote cipe 3 2 Logical Address Translation 3 2 1 Translation 3 2 2 SSC rr cen Erb rixae 3 2 2 1 Table DescriplO S uera o exitum 3 2 2 2 Page eu cede dw qiue 3 2 2 3 Descriptor Field Definitions 3 2 3 Translation Table Example 2 3 2 4 Variations in Translation Table Structure 3 2 4 1 Indirect ACHON 3 2 4 2 Table Sharing Between 3 2 4 3 Table PAGING u us uq ore aeos 3 2 4 4 Dynamically Allocated Tables 3 2 5 Table Search 3 2 6 Address Translation Protection 3 2 6 1 Supervisor and User Translation Tables
50. 07 00 are selected by SIZ1 5120 1 and 0 Concurrently the selected device asserts TA At the end of C4 the processor samples the level of TA if TA is asserted the bus cycle terminates If TA is not recognized asserted at the end of C4 the processor appends a wait state instead of terminating the transfer The processor continues to sample the TA signal on successive rising edges of BCLK until it is recognized asserted 7 28 M68040 USER S MANUAL MOTOROLA When the processor recognizes at the end of a clock the bus cycle is terminated but TIP remains asserted if the processor is ready to begin another bus cycle Otherwise the processor negates TIP during the first half of the next clock The processor also three states the data bus during the first half of the next clock following termination of the write cycle When the last write transfer is terminated LOCKE is negated The processor also negates LOCK if the next bus cycle is not a read modify write 7 5 ACKNOWLEDGE BUS CYCLES Bus transfers with transfer type signals TT1 and TTO 3 are classified as acknowledge bus cycles The following paragraphs describe interrupt acknowledge and breakpoint acknowledge bus cycles that use this encoding 7 5 1 Interrupt Acknowledge Bus Cycles When a peripheral device requires the services of the M68040 or is ready to send information that the processor requires it can signal the processor to take an interrupt exception The i
51. 34 5 Pins x 14 8 mW per Pin 1 41 For the example b system with copyback caching assuming 85 cache hit rate P 29 8 Pins x 30 1 mW per Pin 34 5 Pins x 14 8 mW per Pin x 1 0 85 0 21 W 11 16 M68040 USER S MANUAL MOTOROLA d For the example system running the data bus small buffer mode with other outputs in large buffer mode terminated P Number of Pins Large Buffer High x Number of Pins Large Buffer Low x Pip Number of Pins Small Buffer High x P hsb Number of Pins Small Buffer Low P 19 1 Pins x 30 1 mW per Pin 23 8 Pins x 14 8 mW per Pin 10 7 Pins x 0 625 mW per Pin 10 7 Pins x 0 625 mW per Pin 0 94 W x 1 0 85 0 14 W 11 9 1 Still Air In this study a small sample of MC68040 packages was tested in free air cooling with no heat sink Measurements showed that the average was 22 8 C W with a standard deviation of 0 44 C W The test was performed with approximately 6 W of power being dissipated from within the package The test determined that decreases slightly for the increasing power dissipation range possible Therefore since the variance in within the possible power dissipation range is negligible it can be assumed for calculation purposes that is valid at all power levels Using the previous equations Table 11 2 lists the results of a maximum power dissipation at maximum with no heat sink or airflow see Ta
52. 6 Signal Descriptions 5 2 5 3 Sink Data 4 1 4 9 5 8 Small Output Buffer A 5 Snoop Controller 1 4 5 7 Snooping 4 1 5 9 Cache Coherency 4 10 Logic 1 1 1 5 Operation 5 9 Snoop Inhibited Operation 7 61 Snooped External Read 4 8 Source Data 4 1 4 8 4 10 5 8 Stack Frames Access Error 3 22 8 20 A 7 B 11 Fields Defined 8 24 8 27 Floating Point Post Instruction A 7 B 11 Format 0 8 21 Format 1 8 21 Format 2 8 22 9 21 9 22 Format 3 8 23 9 31 9 32 9 35 9 38 Format 4 8 23 A 5 B 11 Format 7 8 24 MC68L C040 5 MC68ECO040 B 11 SSW Field Format Defined 8 24 8 26 State Data 4 1 5 9 State Frames see Floating Point State Frames Sticky Bit 9 6 Supervisor Address Space 3 23 8 4 Supervisor Mode see Privilege Modes Synchronization 7 44 Synchronizer Circuit 7 58 T Table Descriptor see Descriptors Table Search 3 9 3 12 3 24 3 28 TAP Controller 6 1 6 2 6 6 6 13 Controller States 6 3 6 4 Tag Entry see Address Translation Cache Entry Thermal Management 11 29 11 30 11 31 MOTOROLA Thermal Resistance 11 29 Trace Exceptions 8 10 Trace Mode 2 7 Translation Table 1 4 3 2 3 3 3 6 3 7 3 12 3 16 3 32 Dynamically Allocated 3 21 Page Frame Address 3 9 Page Level Tables 3 7 3 8 Pointer Level Tables 3 7 Protection Mechanisms 3 23 Root Level Tables 3 7 Supervisor Root Pointer 3 23 Transparent Translation 3 5 Transparent Translation Registers
53. A 9 A 6 6 Output AC Timing A 11 A 6 7 Input AC Timing Specifications A 12 Appendix B MC68EC040 B 1 MC68EC040 Differences B 4 B 2 JTAG Scan 1 5 ACCESS Control 5 B 3 1 Access Control Registers rp c eR B 5 B 3 2 Address GompariSOl uuu E oed DO Ec B 7 B 3 3 Effect of RSTI on the B 8 xiv M68040 USER S MANUAL MOTOROLA TABLE OF CONTENTS Continued Paragraph Page Number Title Number B 4 special Modes Of Operation B 8 B 5 Exception PROCES SING lt lt rper 10 5 1 Unimplemented Floating Point Instructions and Exceptions B 10 B 5 2 MC68ECO040 Stack 11 6 Software Considerations 12 B 7 MC68ECO040 Electrical B 12 B 7 1 Maximum PARTIS x gas oct EGO ba Sae in B 12 B 7 2 Thermal Glardcterlsll6S u oce QS B 12 B 7 3 DC Electrical Specifications aa B 13 B 7 4 Power Dissipatigii uu uu m a 13 7 5 Clock AC Timing
54. CACHE SNOOP WRITE BACK WB3 CONTROLLER DATA MEMORY UNIT 1 I l l 1 1 1 1 L DATA MUX PUSH BUFFER CONTROL SIGNALS DATA CACHE Figure 2 2 Write Back Cycle Block Diagram MOTOROLA M68040 USER S MANUAL 2 3 2 2 INTEGER UNIT REGISTER DESCRIPTION The following paragraphs describe the IU registers in the user and supervisor programming models Refer to Section 3 Memory Management Unit Except 68 040 and 68 040 for details on the MMU programming model and Section 9 Floating Point Unit MC68040 Only for details on the FPU programming model 2 2 1 Integer Unit User Programming Model Figure 2 3 illustrates the IU portion of the user programming model The model is the same as for previous M68000 family microprocessors consisting of the following registers e 16 General Purpose 32 Bit Registers 07 00 7 0 32 Bit Program Counter PC 8 Bit Condition Code Register CCR 2 2 1 1 DATA REGISTERS 07 00 These registers are used as data registers for bit and bit field 1 to 32 bits byte 8 bit word 16 bit long word 32 bit and quad word 64 bit operations These registers may also be used as index registers 2 2 1 2 ADDRESS REGISTERS A6 A0 These registers can be used as software stack pointers index registers or base address registers The address registers may be used for word and long word operations
55. Calculate Calculate Calculate Addressing Timings are for an idle floating point unit 10 34 M68040 USER S MANUAL MOTOROLA 10 7 3 Timings the Floating Point Unit Times in parentheses are the total time that the stage uses to execute an instruction even though the stage can pass data to the next stage earlier So that 2 3 in the conversion stage means that the instruction takes two cycles to execute but this stage is actually o 4 o ORARE e A s D busy for three cycles n EX sN ma nomenon 2 29 o a zoo o o Aw nomz a 2 o oe s s H ze s Es se M gt sme o pom q 9 __ SD NomNom 292 5 29 SD aw 4 0 80 o __5__ 29 E j y px aep eq n sos 2 p G UN mI Lo Av mw 4 o reg
56. Fetch Stage 1 3 2 1 2 2 2 3 7 4 10 3 Decode Stage 2 1 2 2 Execute Stage 2 2 5 12 8 1 8 7 10 3 10 4 10 6 Write Back Stage 7 43 10 4 see also Write Backs Integer Unit Registers Address Registers 1 8 2 4 Cache Control Register CACR 1 8 2 8 4 5 8 17 Condition Code Register CCR 1 8 2 5 X Bit 2 5 Data Registers 2 4 Function Code Registers 1 8 2 7 Index Registers 1 8 Interrupt Stack Pointer ISP 8 4 Program Counter PC 1 8 2 5 8 4 Stack Pointer SP 1 8 2 5 Supervisor 2 6 Status Register SR 2 7 8 2 S Bit 1 5 M Bit 2 6 2 7 8 4 I Bits 7 29 8 13 Vector Base Register VBR 1 8 2 7 8 4 8 17 Intermediate Result 9 11 9 13 9 15 9 16 9 21 9 31 9 33 9 37 Format 9 12 Interrupt Exceptions 5 14 7 29 7 31 8 12 8 20 Interrupts 1 5 Acknowledged Bus Cycle 5 12 7 29 7 35 7 31 8 2 Pending Procedure 7 30 Priority Level 5 11 Priority Mask 7 29 8 2 Request 8 13 Vector Numbers 8 15 INDEX 4 M68040 USER S MANUAL _J JTAQ IEEE Standard 1149 1 5 15 6 1 Boundary Scan Control 6 6 6 9 BSDL Description 6 15 Disabling 6 13 Electrical And Timing Specifications 11 1 Instructions see JTAG Instructions JTAQ Instructions BYPASS 6 3 DRVCTL T 6 3 6 12 EXTEST 6 3 6 12 HI Z 6 3 6 12 PRIVATE 6 3 SAMPLE PRELOAD 6 3 SHUTDOWN 6 3 6 12 JTAG Output Drivers 6 4 6 5 JTAG Registers Boundary Scan Data Register 6 2 6 4 6 5 6 13 Instruction Shift Registe
57. T5 X MDIS 6 EGND 2 Q2 L2 H2 F2 D2 B2 B4 B6 B8 10 B13 B15 B17 017 F17 H17 L17 N17 017 517 515 EVDD R2 2 G2 C2 B9 B14 C17 G17 M17 R17 516 T4 L3 C7 C9 C11 K16 M16 R13 R11 810 IVDD R5 3 C8 C10 C12 L16 R12 CGND C6 C13 CVDD 93 C5 C14 H16 J16 PGND 59 R10 R6 PVDD Qo Qo Qo Qo Qo Qo Qo Qo RO Qo Qo Qo Qo Qo Qo Lo 92 Oo lt 2 Pin Maps here when documented attribute SCAN IN of TDlI signal is true attribute SCAN OUT of TDO signal is true attribute SCAN MODE of TMS signal is true attribute SCAN CLOCK of TCK signal is 10 066 BOTH attribute SCAN RESET of TRST signal is true attribute INSTRUCTION LENGTH of MC68040 entity is 3 attribute INSTRUCTION OPCODE of MC68040 entity is EXTEST 2 SAMPLE DRVCTLT SHUTDOWN 100 PRIVATE DRVCTLS BYPASS Qo Qo Qo Qo Qo Qo attribute INSTRUCTION CAPTURE of MC68040 entity is 001 attribute INSTRUCTION DISABLE of MC68040 entity is HI 2 attribute REGISTER ACCESS of MC68040 entity is BYPASS SHUTDOWN HI Z PRIVATE amp BOUNDARY DRVCTL DRVCTL S E attribute BOUNDARY CELLS of MC68040 entity is BC 2 BC 4 attribute BOUNDARY_LENGTH of MC68040 entity is 184 attribute BOUNDARY_REGISTER of MC68040 entity is MOTOROLA
58. The method used to process exceptions in the M68040 is significantly different from that used in earlier members of the M68000 processor family due to the restart exception model In general when multiple exceptions are pending the exception with the highest priority is processed first and the remaining exceptions are regenerated when the current instruction restarts Note that the reset operation clears all other exceptions except in the following circumstances As soon as the M68040 has completed exception processing for a condition when interrupt exception is pending it begins exception processing for the interrupt MOTOROLA M68040 USER S MANUAL 8 19 exception instead of executing the exception handler for the original exception condition For example if simultaneous interrupt and trap exceptions are pending the exception processing for the trap exception occurs first followed immediately by exception processing for the interrupt When the processor resumes normal instruction execution it is in the interrupt handler which returns to the trap exception handler Exception processing for access error exceptions creates a format 7 stack frame that contains status information that can indicate a pending trace floating point post instruction or unimplemented floating point instruction exception The RTE instruction used to return from the access error exception handler checks the status bits for one of these pending exceptions
59. Unlike the MC68020 and MC68030 processors the M68040 does not support dynamic bus sizing and expects the referenced device to accept the requested access width The MC68150 dynamic bus sizer is designed to allow the 32 bit M68040 68 040 MC68LC040 bus to communicate bidirectionally with 32 16 or 8 bit peripherals and memories It dynamically recognizes the size of the selected peripheral or memory device and then reads or writes the appropriate data from that location Refer to MC68150 D MC68150 Dynamic Bus Sizer for information on this device Blocks of memory that must be contiguous such as for code storage or program stacks must be 32 bits wide Byte and word sized ports that return an interrupt vector during interrupt acknowledge cycles must be mapped into the low order 8 or 16 bits respectively of the data bus The multiplexer takes the four bytes of the 32 bit bus transfer and routes them to their required positions For example byte would normally be routed to D31 D24 but it can also be routed to any other byte position supporting a misaligned data transfer The same is true for any of the other operand bytes The transfer size SIZO and SIZ1 and byte offset A1 and 0 signals determine the positioning of the bytes see Table 7 1 The size indicated on the SIZx signals corresponds to the size of the operand transfer for the entire bus cycle During an operand transfer A31 A2 indicate the long word base add
60. a MC68040 High Priorty Default Bus Master BB BR STATE STATE D AM_BG 040_BG 040_BR AM BG 040 BG 040 BR AM BR V AM BR A LOCK A LOCKE STATE B 040 gt AM BG 040 BG AM BR ALOCK ALOCKE V a A LOCK V BB A LOCK A LOCKE STATE A BB A LOCK A LOCKE Indicates the signal is asserted for that device b MC68040 Low Priorty Default Bus Master Figure 7 37 M68040 Synchronous DMA Arbitration 7 56 M68040 USER S MANUAL MOTOROLA 7 8 2 4 68040 ASYNCHRONOUS DMA ARBITRATION Figure 7 38 illustrates a sample synchronizer circuit Figure 7 39 illustrates how an M68040 can be implemented to simulate an MC68030 The synchronizer circuit has an output indicating whether or not a signal has been asserted for at least two consecutive rising edges of BCLK If the synchronizer circuit indicates that the input has not been stable for at least two clocks then the processor and alternate bus master stay in the current state Figure 7 37 duplicates the MC68030 implementation of the bus arbitration circuitry in which the M68040 is allowed to yield the bus only after the indeterminate condition has been eliminated Figure 7 37 b is similar to the MC68030 implementation except that the DMA device has lower priority and can only perform transfers when the M68040 is in the idle state In either case the M6804
61. either GND Characteristic Symbol Value Rating or V cC Thermal Resistance Junction to Case 3 C W PGA Package MOTOROLA M68040 USER S MANUAL 11 1 11 3 DC ELECTRICAL SPECIFICATIONS cc 5 0 voc 5 96 Characteristic Symbol min Max Uni votas _ v undeshot ___ v Input Leakage Current 0 5 2 4 V AVEC BCLK BG CDIS MDIS PCLK RSTI SCx 20 20 TBI TLNx TCI TEA Hi Z Off State Leakage Current 0 5 2 4 V An BB CIOUT Dn LOCK LOCKE SIZx ITSI 20 20 TLNx TS UPAx Signal Low Input Current VIL 0 8 V 44 0 18 TMS TDI TRST Signal High Input Current 2 0 V 0 94 0 16 TMS TDI TRST F ru mmn output Low Votage OL 6 mA Smal Buter Mode vo 95 output High 55 mA Large Buter Mode von v CS _ Capacitance is periodically sampled rather than 100 tested 11 4 POWER DISSIPATION mao sw Typical Values Vcc 5 V TJ 90 C This information is for system reliability purposes 11 2 M68040 USER S MANUAL MOTOROLA 11 5 CLOCK AC TIMING SPECIFICATIONS Figure 11 1 ome Eeay ofoperaton eC rumeme Ls rure Tu
62. 3 NOTE If the M68040FPSP unimplemented exception handler is used the above state frame information applies The CMDREG1B or fields of the state frame are modified as appropriate to encode the unimplemented instruction opcode It is the user exception handler s responsibility to use the E3 and E1 field encodings to recognize which state frame information applies When 1 and E1 1 takes priority and the state frame information for 1 must be used MOTOROLA M68040 USER S MANUAL 9 47 9 48 M68040 USER S MANUAL MOTOROLA SECTION 10 INSTRUCTION TIMINGS This section summarizes instruction timings for the M68040 The timings are divided into two groups integer unit and floating point unit instruction timings Each group is further subdivided to separate more complex instruction timings Each of these subdivided groups is in alphabetical order with no reference to mode Table 10 1 alphabetically lists instruction timings and their location in this section Table 10 1 Instruction Timing Index EET TT ADD 10 13 BSET 10 15 EORI 10 13 ADDA 10 13 BSR lt offset gt 10 11 EORI lt xxx gt CCR 10 11 ADDI 10 13 BTST 10 17 EORI lt xxx gt SR 10 11 ADDX 10 11 52 10 11 10 11 AND 10 13 CHK ea Dn 10 17 10 11 ANDI 10 13 CHK2 ea Rn 10 18 FABS 10 30 36 ANDI lt xxx gt CCR 10 11 CLR 10 18 FADD 10 30 35 ANDI lt xxx gt
63. DF ULUO S CM M WP ABBREVIATIONS PFA PAGE FRAME ADDRESS DF DESCRIPTOR FIELD WP ACCUMULATED WRITE PROTECTION STATUS 4 ASSIGNMENT OPERATOR EXIT TABLE SEARCH Figure 3 9 Detailed Flowchart of Table Search Operation 3 10 M68040 USER S MANUAL MOTOROLA DESCRIPTOR 6 UPDATE HISTORY AND STATUS PAGE OR POINTER TYPE INDIRECT FETCH DESCRIPTOR AT PA z TA INDEX 4 INDEX RI OR PGI FETCH DESCRIPTOR AT DESCRIPTOR ADDRESS IF SCHEDULED EXECUTE WRITE ACCESS U 4 1 FOR PREVIOUS DESCRIPTOR SEE NOTE OTHERWISE CRENTE ATE Ee sonia WITH R BIT CLEAR EXIT TABLE SEARCH TYPE Gp TYPE PAGE POINTER OR INDIRECT 77 INVALID RESIDENT RESIDENT RETURN WP WPV W WP WPV W SCHEDULE WRITE ACCESS 041 O U 0 amp SEE NOTE 0 0 WP 10 U 1 EXECUTE LOCKED RMW ACCESS 1 RETURN Q INVALID OR INDIRECT RETURN WRITE ACCESS U 1 amp M 21 WP 10RM 1 WP 0 amp M 0 EXECUTE WRITE ACCESS U41M41 Figure 3 10 Detailed Flowchart of Descriptor MOTOROLA M68040 USER S MANUAL NOTE DUE TO ACCESS PIPELINING A POINTER DESCRIPTOR WRITE ACCESS TO UPDATE CR THE U BIT OCCURS AFTER THE READ OF OTHERWISE THE NEXT LEVEL DESCRIPTOR ABBREVIATIONS NORMAL TERMINATION CREATE ATC ENTRY WP ACCUMULATED WRITE OF ALL
64. GND 20 20 1 1 0 16 Output High Voltage loH 5 mA 24 Output Low Voltage 5 mA Capacitance Vin 0 V f 1 MHz Capacitance is periodically sampled rather than 100 tested V V IL lin OH OL Cin 8 M68040 USER S MANUAL MOTOROLA 6 4 Power Dissipation ws Maximum Values 5 25 V TA 0 20 MHz 25 MHz 33 MHz Typical Values Vcc 5 V TA 25 C 20 MHz 25 MHz 33 MHz This information is for system reliability purposes A 6 5 Clock AC Timing Specifications see Figure 4 Dur Dic e c D Tu s buy Ovce measwedairsv s 525 57 5535 wan Hion 12 18 ss s 7 s ve POLK Pulse wath Low 12 18 ss s 7 s s s o co 0 Tee s 9 4 e Poue BOLK Frequency Sawy 1000 1000 froxiscxsew LTS e Specification value at maximum frequency of operation MOTOROLA M68040 USER S MANUAL 9 PCLK BCLK Figure A 4 Clock Input Timing Dia
65. If one is indicated the RTE changes the access error stack frame to match the pending exception and fetches the vector for the exception Instruction execution then resumes in the new exception handler If an access error trace and one of the two mutually exclusive floating point exceptions occur simultaneously the pending floating point exception is indicated in the access error stack and the trace exception flag is undefined The exception handler for the floating point exception must check the trace bits on the stack and call the trace handler directly after adjusting the stack frame to match the format for the trace exception e trace exception is pending at the same time an exception priority level or floating point post instruction exception is pending the trace exception is not reported and the exception handler for the other exception condition must check for the trace condition 8 4 RETURN FROM EXCEPTIONS After the processor has completed executing the exception handlers for all pending exceptions the processor resumes normal instruction execution at the address in the processor s vector table for the last exception processed Once the exception handler has completed execution if possible the processor must return the system context as it was prior to the exception using the RTE instruction If the internal data of the exception stack frames are manipulated M68040 may enter into an undefined state this applies s
66. O Latch I Pin O Latch I Pin O Latch I Pin O Latch I Pin O Latch I Pin O Latch I Pin O Latch I Pin O Latch O Latch O Latch O Latch O Latch O Latch I Pin O Latch I Pin O Latch O Latch 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 o TS Output SIZ1 1 02 D D D D D D Ti Ti Ti 27 28 29 30 31 A9 A9 A8 A8 A7 A7 A6 A6 A5 A5 A4 A4 A3 A3 A2 A2 A1 A1 0 0 M2 M1 MO Rw 6 11 Table 6 2 Boundary Scan Bit Definitions Concluded ar 28 E Cell Type Name Pin Type C Cell Type Name Pin Type Ctrl Cell 9o io 1 Note 4 Note 4 Output2 Note 3 Output2 Note 3 ote 4 212 gt 176 PCLK Input 177 BCLK Input ote 4 Note 4 102 O io 1 MI BR TS Output io 1 5 Output Note 3 Olath PST Output Note 3 NOTES 1 1 IO Ctl and O Latch are equivalent to the BSDL descriptions 4 2 and BC 2 respectively 2 Boundary scan register bit positions that are used during the drive control DRVCTL X instructions 3 These output only cells can be turned off high impedance by using the HIGHZ instruction 4 All of the control signals IO Ctl
67. Table 6 1 lists the three bits used in the instruction shift register to decode the instructions and their related encodings Note that the least significant bit of the instruction bit 0 is the first bit to be shifted into the instruction shift register Table 6 1 IEEE Standard 1149 1A Instructions ma instruction Selected Data Register Accessed emer o nz B Saweueactoad Boundary sean EN DRVCTL S Boundary Scan KAEA o o ESEA EXTEST HIGHZ DRVCTL T SHUTDOWN and PRIVATE have PCLK and BCLK restriction Failure to comply with this restriction results in potential internal damage to the device see 6 4 Restrictions Once the restriction is complied with SHUTDOWN EXTEST HIGHZ and DRVCTL T can be entered regardless of order The system clocks PCLK and BCLK must be kept running while in the SAMPLE PRELOAD DRVCLT S and BYPASS instructions Failure to do so could result in potential internal damage to the device 6 2 1 EXTEST The external test instruction EXTEST selects the 184 bit boundary scan register This instruction also activates two internal functions that are intended to protect the device from potential damage while performing boundary scan operations MOTOROLA M68040 USER S MANUAL 6 3 EXTEST asserts internal reset for the M68040 system logic to force a predictable benign in
68. USER STACK POINTER PRO GRAM COUNTER CONDITION CODE REGISTER USER PROGRAMMING MODEL 0 Z 3 7 5 AT MSP SR VBR SFC DFC CACR URP SRP TC DTTO ITTO MMUSR INTERRUPT STACK POINTER MASTER STACK POINTER STAT VECT US REGISTER OR BASE REGISTER SOURCE FUNCTION CODE DEST CACH USER SUPE INATION FUNCTION CODE E CONTROL REGISTER ROOT POINTER REGISTER RVISOR ROOT POINTER REGISTER TRAN DATA DATA SLATION CONTROL REGISTER TRANSPARENT TRANSLATION REGISTER 0 TRANSPARENT TRANSLATION REGISTER 1 INSTRUCTION TRANSPARENT TRANSLATION REGISTER 0 INSTRUCTION TRANSPARENT TRANSLATION REGISTER 1 MMU STATUS REGISTER SUPERVISOR PROGRAMMING MODEL Figure A 2 MC68LC040 Programming Model MOTOROLA M68040 USER S MANUAL A 3 ADDRESS BUS BUS 4 TRANSFER ATTRIBUTES MASTER TRANSFER 7j CONTROL SLAVE TRANSFER CONTROL SCO ET BUS SNOOP CONTROL EL AND RESPONSE Wi BR BG BUS ARBITRATION B CDIS RSTI PROCESSOR RSTO CONTROL MDIS PSTO PSTI PST2 STATUS AND PST3 CLOCKS gt 5 IPLO INTERRUPT CONTROL IPEND AVE Figure 3 MC68LC040 Functional Signal Groups M68040 USER S MANUAL MOTOROLA 1 MC68LC040 DIFFERENCES The following differences exist between the MC68L C040 and MC68040 e The MC68L C040 does not implement the small output buffe
69. alg OTHERWISE BUS ERROR VECTOR 1 b PC DOUBLE BUS FAULT PREFETCH 4 LONG WORDS rit BUS ERROR OR ADDRESS ERROR OTHERWISE BEGIN INSTRUCTION EXECUTION DOUBLE BUS FAULT HALTED STATE PST3 PSTO 5 EXIT Figure 8 5 Reset Exception Processing Flowchart rn 25 After the initial instruction is prefetched program execution begins at the address the PC The reset exception does not flush the ATCs or invalidate entries in the instruction or data caches it does not save the value of either the PC or the SR If an access fault or address error occurs during the exception processing sequence for a reset a double bus fault is generated The processor halts and the processor status PST3 PSTO signals indicate 5 Execution of the reset instruction does not cause a reset exception or affect 8 18 M68040 USER S MANUAL MOTOROLA any internal registers but it does cause the M68040 to assert the reset out RSTO signal resetting all external devices 8 3 EXCEPTION PRIORITIES When several exceptions occur simultaneously they are processed according to a fixed priority Table 8 4 lists the exceptions grouped by characteristics Each group has a priority from 0 7 with 0 as the highest priority Table 8 4 Exception Priority Groups Group Exception and Relative Priority Characteristics Priority Reset Aborts all processing instruction or exception and does not save old context 1 Data Access Er
70. definition since it is only set when a very small number is generated and accuracy has been lost when calculating that number The UNFL bit in the FPCR EXC byte implements the IEEE exception enabled definition since it is set any time a tiny number is generated 9 7 5 1 MASKABLE EXCEPTION CONDITIONS There are no conditions 9 7 5 2 NONMASKABLE EXCEPTION CONDITIONS When the UNFL bit of the FPSR is set the processor always takes an exception regardless of whether or not the user UNFL exception handler is enabled If the destination is a floating point data register the register is not affected and either a pre instruction or a post instruction exception is reported If the destination is a memory or integer data register then an undefined result is stored and a post instruction exception is taken immediately Exception processing begins with the M68040FPSP UNFL exception handler The M68040FPSP UNFL exception handler stores the result in the destination as either a denormalized number or zero Shifting the mantissa of the intermediate result to the right while incrementing the exponent until it is equal to the denormalized exponent value for the destination format accomplishes denormalization The denormalized intermediate result is rounded to the selected rounding precision if the destination is a floating point data register or rounded to the destination format in the case of an FMOVE OUT instruction For the instructions with forced rounding p
71. is the only user dependent parameter once a buffer output configuration has been determined Reducing the case to ambient thermal resistance increases the maximum operating ambient temperature Therefore by utilizing methods such as heat sinks and ambient air cooling to minimize Oca a higher ambient operating temperature and or a lower junction temperature can be achieved However an easier approach to thermal evaluation uses the following equations Ta Tyj Ppx80jJA where Thermal Resistance from the Junction to the Ambient Oca The total thermal resistance for a package Oja is a combination of its two components and Oca These components represent the barrier to heat flow from the semiconductor junction to the package case surface and Although is package related and the user cannot influence it is user dependent Good thermal management by the user such as heat sink and airflow can significantly reduce achieving either a lower semiconductor junction temperature or a higher ambient operating temperature 11 9 MC68040 THERMAL MANAGEMENT TECHNIQUES To attain a reasonable maximum ambient operating temperature the user must reduce the barrier to heat flow from The only way to accomplish this is to significantly reduce by applying thermal management techniques such as heat sinks and forced air cooling The following paragraphs discuss
72. specifying a number s format to be stored in the packed decimal format Fe Any Non Floating Poin 1 12 M68040 USER S MANUAL MOTOROLA Table 1 3 Notational Conventions Concluded SSP Supervisor or Interrupt Stack Pointer 1 10 INSTRUCTION SET OVERVIEW The instruction set is tailored to support high level languages and is optimized for those instructions most commonly executed The floating point instructions for the M68040 are a commonly used subset of the MC68881 MC68882 instruction set with new arithmetic instructions to explicitly select single or double precision rounding The remaining unimplemented instructions are less frequently used and are efficiently emulated in the M68040FPSP maintaining compatibility with the MC68881 MC68882 floating point coprocessors The M68040 instruction set includes 16 a new user instruction that allows high speed transfers of 16 byte blocks between external devices such as memory to memory or coprocessor to memory Table 1 4 provides an alphabetized listing of the M68040 instruction set s opcode operation and syntax Refer to Table 1 3 for notations used in Table 1 4 The left operand in the syntax is always the source operand and the right operand is the destination operand Refer to M68000PM AD M68000 Family Programmer s Reference Manual for details on instructions used by the M68040 MOTOROLA M68040 USER S MANUAL 1 13 Table 1 4 Instruction Set Summary Synta
73. the exception is executed again Therefore it is the responsibility of the user BSUN exception handler to prevent the conditional instruction from taking the BSUN exception again There are four ways to prevent taking the exception again 1 Incrementing the stored PC in the stack bypasses the conditional instruction This technique applies to situations where a fall through is desired Note that accurate calculation of the PC increment requires detailed knowledge of the size of the conditional instruction being bypassed 2 Clearing the NAN bit prevents the exception from being taken again However this alone cannot deterministically control the result s indication true or false that would be returned when the conditional instruction reexecutes 3 Disabling the BSUN bit also prevents the exception from being taken again Like the second method this method cannot control the result indication true or false that would be returned when the conditional instruction reexecutes 9 26 M68040 USER S MANUAL MOTOROLA 4 Examining the conditional predicate and setting the accordingly prevents the exception from being taken again This technique gives the most control since it is possible to pre determine the direction of program flow Bit 7 of the F line operation word indicates where the conditional predicate is located If bit 7 is set the conditional predicate is the lower six bits of the F line operation word Otherwise t
74. 1 0 UPA1 UPAO IPLO Miscellaneous Control Signals BB BR IPEND MI 5 0 TA TS NOTE High input level small buffers enabled low input level large buffers enabled MOTOROLA M68040 USER S MANUAL 5 11 5 8 2 Interrupt Pending Status IPEND This output signal indicates that an interrupt request has been recognized internally and exceeds the current interrupt priority mask in the status register SR External devices other bus masters can use IPEND to predict processor operation on the next instruction boundaries IPEND is not intended for use as an interrupt acknowledge to external peripheral devices Refer to Section 7 Bus Operation for bus information related to interrupts and to Section 8 Exception Processing for interrupt information 5 8 3 Autovector AVEC This input signal is asserted with TA during an interrupt acknowledge transfer to request internal generation of the vector number Refer to Section 7 Bus Operation for more information about automatic vectors 5 9 STATUS AND CLOCK SIGNALS The following paragraphs explain the signals that provide timing test control and the internal processor status 5 9 1 Processor Status PST3 PSTO These outputs indicate the internal execution unit s status The timing is synchronous with BCLK and the status may have nothing to do with the current bus transfer The PSTx signal is updated depending on the type of PST
75. 10 9 8 7 6 5 4 3 2 1 0 BSUN SNAN OPERR OVFL INEX2 INEX1 PREC tum ROUNDING MODE ROUNDING PRECISION INEXACT DECIMALINPUT INEXACT OPERATION DIVIDE BY ZERO UNDERFLOW OVERFLOW OPERAND ERROR SIGNALING NOT A NUMBER BRANCH SET ON UNORDERED Figure 9 2 Floating Point Control Register 9 2 3 Floating Point Status Register FPSR The FPSR see Figure 9 1 contains a floating point condition code byte a quotient byte a floating point exception status byte EXC and a floating point accrued exception byte AEXC The user can read or write to all bits in the FPSR Execution of most floating point instructions modifies this register The reset function or a restore operation of the null state clears the FPSR Floating point conditional operations are not guaranteed if the FPSR is written directly because the FPSR is only valid as a result of a floating point instruction 9 2 3 1 FLOATING POINT CONDITION CODE BYTE The FPCC byte see Figure 9 3 contains four condition code bits that are set at the end of all arithmetic instructions involving the floating point data registers These bits are sign of mantissa N zero Z infinity 1 and The FMOVE FPm ea FMOVEM FPm and FMOVE FPCR instructions do not affect the FPCC NOT A NUMBER OR UNORDERED INFINITY ZERO NEGATIVE Figure 9 3 FPSR Condition Code Byte To aid programmers of float
76. 2 FP3 FLOATING POINT EPA DATA REGISTERS 5 FP6 FP7 CE FLOATING POINT EXCEPTION MODE CONTROL ENABLE CONTROL REGISTER 3l 23 15 7 0 z FLOATING POINT CONDITION QUOTIENT EXCEPTION ACCRUED ess STATUS R CODE STATUS EXCEPTION 3l 0 FLOATING POINT INSTRUCTION FPIAR ADDRESS REGISTER Figure 9 1 Floating Point User Programming Model 9 2 1 Floating Point Data Registers FP7 FPO The floating point data registers are analogous to the integer data registers of the M68000 family The floating point data registers always contain extended precision numbers All external operands regardless of the data format are converted to extended precision values before being used in any calculation or stored in a floating point data register A 9 2 M68040 USER S MANUAL MOTOROLA reset or a restore operation of the state sets FP7 FPO to positive nonsignaling not a numbers 5 9 2 2 Floating Point Control Register FPCR The FPCR see Figure 9 2 contains an exception enable ENABLE byte that enables or disables traps for each class of floating point exceptions and a mode control MODE byte that sets the user selectable modes The user can read or write to the FPCR Motorola reserves bits 31 16 for future definition these bits are always read as zero and are ignored during write operations The res
77. 2 1 4 PROGRAM COUNTER The PC contains the address of the currently executing instruction During instruction execution and exception processing the processor automatically increments the contents of the PC or places a new value in the PC as appropriate For some addressing modes the PC can be used as a pointer for PC relative addressing 2 2 1 5 CONDITION CODE REGISTER The CCR consists of five bits of the SR least significant byte The first four bits represent a condition of the result generated by a processor operation The fifth bit the extend bit X bit is an operand for multiprecision computations The carry bit C bit and the X bit are separate in the M68000 family to simplify programming techniques that use them 2 2 2 Integer Unit Supervisor Programming Model Only system programmers use the supervisor programming model see Figure 2 4 to implement sensitive operating system functions control and MMU subsystems All accesses that affect the control features of the M68040 are in the supervisor programming model Thus all application software is written to run in the user mode and migrates to the M68040 from any M68000 platform without modification MOTOROLA M68040 USER S MANUAL 2 5 31 15 0 7 ISP INTERRUPT STACK POINTER 31 15 0 MASTER STACK POINTER 15 7 0 CCR SR STATUS REGISTER 31 0 VBR VECTOR BASE REGISTER 31 20 T Pra
78. 5 5 5 3 Normal and MOVE16 Access Transfer Modifier Encoding 5 6 5 4 Alternate Access Transfer Modifier Encoding 5 6 5 5 Output Driver Control Groups pt pe edere ha ripe tna 5 11 5 6 Processor Status Encoding te ee Rn 5 13 5 7 5 16 6 1 IEEE Standard 1149 1A Instructions 0 6 3 6 2 Boundary Scan Bit Definitions 2 6 10 7 1 Data Bus Requirements for Read and Write Cycles 7 4 7 2 Summary of Access Types versus Bus Signal Encodings 7 6 7 3 Memory Alignment Influence Noncachable and Write Through Bus Cycles sicco eet or den eee rade netus 7 9 7 4 Interrupt Acknowledge Termination 7 31 7 5 and TEA Assertion Results sss essere 7 37 7 6 M68040 Bus Arbitration States 7 48 8 1 Exception Vector 8 5 8 2 Tracing Control DEPTH RIPE 8 11 8 3 Interrupt Levels and Mask 5 8 12 8 4 Exception Priority Groups hac ss e t 8 19 xxii M68040 USER S MANUAL MOTOROLA LIST TABLES Continued Table Pag
79. 515 500003000 580000010 TABLE 7F TABLE 1F ROOT POINTER TASKB ROOT LEVEL POINTER LEVEL PAGE LEVEL TABLES TABLES TABLES FRAME ADDRESS Figure 3 14 Translation Table Using Indirect Descriptors 3 2 4 2 TABLE SHARING BETWEEN TASKS More than one task can share a pointer or page level table by placing a pointer to a shared table in the address translation tables The upper nonshared tables can contain different write protected settings allowing different tasks to use the memory areas with different write permissions In Figure 3 15 two tasks share the memory translated by the table at the pointer table level Task A cannot write to the shared area task B however has the W bit clear in its pointer to the shared table so that it can read and write the shared area Also the shared area appears at different logical addresses for each task Figure 3 15 illustrates shared tables in a translation table structure 3 18 M68040 USER S MANUAL MOTOROLA LOGICAL ADDRESS ROOT INDEX POINTER INDEX PAGE INDEX PAGE OFFSET 576543210 0 1 1 1 0 1 1 00 1 0 1 0 10 0 0 0 X X X X X X X X X X X X X TABLE ENTRY 3B 15 01 ADDRESS OFFSET EC 54 04 TABLE 00 TABLE 00 TABLE 00
80. 6 INTEGER UNIT INSTRUCTION TIMINGS SUN Addressing ea ea ea a im An An An 416 d16 PC lt gt An Xn dg PC Xn BR Xn bd BR Xn arte mass 7446 ae This instruction interlocks the ea calculate and execute stages Timing for Dn within bounds UB gt LB For UB lt LB add three clocks to ea calculate and execute times For Rn An add one clock to ea calculate and execute times 10 18 M68040 USER S MANUAL MOTOROLA 10 6 INTEGER UNIT INSTRUCTION TIMINGS Continued Addressing ea lt gt lt gt Calculate p lt XXX gt aa PC E listed are typical MOTOROLA M68040 USER S MANUAL 10 19 10 6 INTEGER UNIT INSTRUCTION TIMINGS Continued Mode Calculate Calculate Calculate pi p ce o cp d An 2 4 j s j An Se US o an ewe sz x o s s z v x frost Ga o o e THESE tmm ues u w menu ure 0 This instruction interlocks the ea calculate and execute stages Execution time fo
81. 7 gt jos lt IPEND N Figure C 20 Exiting LPSTOP with Interrupt NORMAL OPERATION m n AUS UA D Figure C 21 Exiting of LPSTOP with RESET MOTOROLA M68040 USER S MANUAL 31 32 M68040 USER S MANUAL MOTOROLA APPENDIX D M68000 FAMILY SUMMARY This appendix summarizes the characteristics of the microprocessors in the M68000 family The M68000PM AD M68000 Family Programmer s Reference Manual includes more detailed information on the M68000 Family differences Attribute MC68000 MC68008 MC68010 MC68020 MC68030 68040 MC68010 supports a three word cache for the loop mode Coprocessor Interface MC68000 MC68008 MC68010 Emulated in Software MC68020 68030 MC68040 Emulated in Software On Chip Floating Point Unit Word Long Word Data Alignment MC68000 MC68008 MC68010 Word Long Word Data Instructions and Stack Must Be Word Aligned MC68020 MC68030 MC68040 Only Instructions Must Be Word Aligned Data Alignment Improves Performance Control Registers MC68000 68008 MC68010 SFC DFC VBR MC68020 SFC DFC VBR CACR CAAR MC68030 SFC DFC VBR CACR CAAR CRP SRP TC TTO TT1 MMUSR MC68040 SFC DFC VBR CACR URP SRP TC DTTO DTT1 ITTO ITT1 MMUSR MOTOROLA M68040 USER S MANUAL 0 1 Stack Pointer MC68000 MC68008 MC68010 USP SSP MC68020 MC68030 MC680
82. 9 7 4 1 Byte Word and Long Word Read Transfers During a read transfer the processor receives data from a memory or peripheral device Since the data read for a byte word or long word access is not placed in either of the internal caches by definition the processor ignores the level on the transfer cache inhibit TCI signal when latching the data The bus controller performs byte word and long word read transfers for the following cases Accesses to a disabled cache Accesses to a memory page that is specified noncachable Accesses that are implicitly noncachable read modify write accesses and accesses to an alternate logical address space via the MOVES instruction Accesses that do not allocate in the data cache on a read miss table searches exception vector fetches and exception stack deallocation for an RTE instruction The first transfer of a line read is terminated with transfer burst inhibit TBI forcing completion of the line access using three additional long word read transfers Figure 7 8 is a flowchart for byte word and long word read transfers Bus operations are similar for each case and vary only with the size indicated and the portion of the data bus used for the transfer Figure 7 9 is a functional timing diagram for byte word and long word read transfers PROCESSOR EXTERNAL DEVICE ADDRESS DEVICE 1 SET RW TO READ 2 DRIVE ADDRESS ON A31 A0 3 DRIVE USER P
83. AND RTE SO THAT 101 5 THEN LEVEL 7 INTERRUPT LEVEL COMPARISON Figure 8 3 Interrupt Recognition Examples Note that a mask value of 6 and a mask value of 7 both inhibit request levels of 1 6 from being recognized In addition neither masks a transition to an interrupt request level of 7 The only difference between mask values of 6 and 7 occurs when the interrupt request level is 7 and the mask value is 7 If the mask value is lowered to 6 a second level 7 interrupt is recognized External circuitry can chain or otherwise merge signals from devices at each level allowing an unlimited number of devices to interrupt the processor When several devices are connected to the same interrupt level each device should hold its interrupt priority level constant until its corresponding interrupt acknowledge bus cycle ensures that all requests are processed Refer to Section 7 Bus Operation for details on the interrupt acknowledge cycle 8 14 M68040 USER S MANUAL MOTOROLA Figure 8 4 illustrates a flowchart for interrupt exception processing When processing interrupt exception the processor first makes an internal copy of the SR sets the mode to supervisor suppresses tracing and sets the processor interrupt mask level to the level of the interrupt being serviced The processor attempts to obtain a vector number from the interrupting device using an interrupt acknowledge bus cycle with the interrupt level number output on the tra
84. Appendix MC68040V and MC68ECO040V for more information on electrical characteristics for the MC68ECO40V This section is subject to change For the most recent specifications contact a Motorola sales office or complete the registration card at the end of this manual B 7 1 Maximum Ratings Characteristic Symbol Vale _ Unit Supply Voltage 0 3 to 7 0 This device contains protective circuitry against damage due to high static voltages or electrical fields however it is advised that normal precautions be taken to avoid application of any voltages higher than maximum rated voltages to this high impedance circuit Reliablity of operation is enhanced if unused inputs are tied to an appropriate logic voltage level e g either GND or V cC Maximum Operating Junction Temperature Minimum Operating Ambient Temperature Storage Temperature Range 55 to 150 B 7 2 Thermal Characteristics Characteristic Symbol Value Rating CC in TJ 110 TA Thermal Resistance Junction to Case 3 C W PGA Package B 12 M68040 USER S MANUAL MOTOROLA B 7 3 DC Electrical Specifications voc 5 0 vac 5 Characteristic Symbol Input High Voltage Input Low Voltage Undershoot Input Leakage Current 0 5 2 4 V AVEC BCLK BG CDIS IPLx PCLK RSTI SCx TBI H n TLNx TCI TCK TEA L Hi Z Off State Leakage Current 0 5 2 4 V Dn LOCK LOCKE R
85. BR and BG signals Figure 7 32 illustrates an example of the processor requesting the bus from the external bus arbiter During C1 the M68040 asserts BR to request the bus from the arbiter which negates the alternate bus master s BG signal and grants the bus to the processor by asserting BG during C3 During C3 the alternate bus master completes its current access and relinquishes the bus by three stating all bus signals Typically the BB and TIP signals MOTOROLA M68040 USER S MANUAL 7 49 require a pullup resistor to maintain logic one level between bus master tenures The alternate bus master should negate these signals before three stating to minimize rise time of the signals and ensure that the processor recognizes the correct level on the next BCLK rising edge At the end of C3 the processor recognizes the bus grant and bus idle conditions BG asserted and BB negated and assumes ownership of the bus by asserting BB and immediately beginning a bus cycle during C4 During C6 the processor begins the second bus cycle for the misaligned operand and negates BR since no other accesses are pending During C7 the external bus arbiter grants the bus back to the alternate bus master that is waiting for the processor to relinquish the bus The processor negates BB and TIP before three stating these and all other bus signals during C8 Finally the alternate bus master recognizes the bus grant and idle conditions at the end of C8 and is able to res
86. BUS WRITE BACK CACHEACCESSSNOOP KC CONTROL CONTROLLER SIGNALS y y DATA DATA ATC O CACHE OPERAND DATA BUS Figure 1 MC68LC040 Block Diagram The main features of the MC68LC040 include 22 MIPS Integer Performance at 25 MHz Independent Instruction and Data MMUs 4 Kbyte Physical Instruction Cache and 4 Kbyte Physical Data Cache Accessible Simultaneously 32 Bit Nonmultiplexed External Address and Data Buses with Synchronous Interface User Object Code Compatible with All M68000 Microprocessors Multimaster Multiprocessor Support Via Bus Snooping Concurrent Integer Unit MMU Bus Controller and Bus Snooper Operation Maximizes Throughput 4 Gbyte Direct Addressing Range Software Support Including Optimizing C Compiler and UNIX9 System V Port OUNIX is a registered trademark of AT amp T Bell Laboratories A 2 M68040 USER S MANUAL MOTOROLA With the exception of the floating point unit FPU and its registers the MC68LC040 programming model data formats and types instruction set except all instructions beginning with an caches and MMUs the same as those described in Section 1 Introduction for the MC68040 Figures A 2 and A 3 illustrate the programming model and functional signal groups for the MC68L C040 DATA REGISTERS ADDRESS REGISTERS 00 01 02 03 04 05 06 07 0 Al A2 A3 4 5 6 AT USP PC CCR
87. Bits for Field CU SAVEPC This field contains the PC for the FPU pipeline s conversion unit 1 set this bit indicates that an exception has been detected by the conversion unit pipeline stage All exception types are possible The exception handler first checks for an exception and processes it before checking and processing an E1 exception The E1 exception is processed if the E1 bit is set For the unimplemented instruction state frame the source operand s unsupported data type is packed if the E1 bit is set E3 If set this bit indicates that an exception has been detected by the WB pipeline stage Only OVFL UNFL and INEX2 exceptions on opclass 010 or 000 register to register and memory to register for FADD FSUB FMUL FDIV FSQRT can occur The exception handler must check for and process an E3 exception first ETS ETE ETM Oollectively these fields are referred to as the ETEMP register and normally contain the source operand converted to extended precision If the instruction specifies a packed decimal real source bits 63 0 of the operand reside in ETM 63 00 and the ETS and ETE fields are undefined FPIARCU This field contains the instruction address register for the FPU pipeline s conversion unit 9 42 M68040 USER S MANUAL MOTOROLA FPTS FPTM Oollectively these fields are referred to as the FPTEMP register and normally contain the destination operand for dyadic operations c
88. C8 C9 CH C s 1 8 e 1 12 1 Ee m NOTE Possible stalls in this stage MOTOROLA Figure 10 3 Interlocked Stages M68040 USER S MANUAL 10 7 10 3 AND CPUSH INSTRUCTION TIMING The following details the execution time for the CINV and CPUSH instructions used to perform maintenance of the instruction and data caches These two instructions sample interrupt request IPLx signals on every clock instead of at instruction boundaries While performing the actual cache invalidate operation the execution unit stalls to allow previous write backs and any pending instruction prefetches to complete The total time required to execute a cache invalidate instruction is dependent on the previous instruction stream Execution time for this instruction is independent of the selected cache combination The CINV instructions interlock operation of the ea calculate and execution stages to prevent a previous instruction from accessing the caches until the invalidate operation is complete Idle refers to the number of clocks required for all pending writes and instruction prefetches to complete Table 10 3 list the CINV timings Table 10 3 CINV Timing Execution Time CINVL 9 Idle CINVP 266 Idle CINVA 9 Idle Execution time
89. Descriptors 3 18 3 15 Translation Table Using Shared 3 19 3 16 Translation Table with Nonresident 3 20 3 17 Translation Table Structure for Two 3 24 3 18 Logical Address Map with Shared Supervisor and User Address Spaces 3 24 3 19 Translation Table Using S Bit and W Bit To Set Protection 3 25 9 2D ATC t ALME 3 26 3 21 ATG Entryand Tag dt eie eb ab Heber 3 27 3 22 Address Translation 3 32 3 23 MMU Status Interpretation e etti heo ace nete 3 35 4 1 Overview of Internal Caches 4 2 4 2 Cache Ling ote mis oto 4 3 4 3 Caching Operaatio M aeos iet cena aceti ce eti aea reete a mortc 4 4 4 4 Cache Control rre OLD ERAT CIO 4 5 MOTOROLA M68040 USER S MANUAL xvii LIST OF ILLUSTRATIONS Continued Figure Page Number Title Number 4 5 Instruction Cache Line State Diagram 4 14 4 6 Data Cache Line State 4 16 5 1 Functional Signal Groups sare eee eode obe SECO
90. Fault 3 9 8 6 8 7 Address Error 7 6 7 43 8 8 MOTOROLA Bus Error 3 22 3 30 4 12 7 37 7 42 7 43 9 21 Double Bus Fault 7 43 8 8 8 18 F Line A 6 B 10 Format Error 8 12 8 28 9 20 FTRAPcc 9 20 Illegal Instruction 8 9 Interrupt 5 14 7 29 7 31 8 12 8 20 Memory Management Unit 8 7 Priority 8 19 Privilege Violation 8 10 Reset 5 11 7 67 7 68 8 17 Trace 8 10 Trap 8 8 8 20 Unimplemented Floating Point Instruction 1 2 9 20 Unimplemented Instruction 8 9 Explicit Bus Ownership see Bus Arbitration States Extended Precision see Data Format External Bus Arbiter 5 7 5 10 7 45 7 46 7 50 7 53 7 55 7 58 EXTEST 6 3 6 12 F line A 6 B 10 Fetch Stage see Integer Unit Pipeline Floating Point Exceptions 1 8 9 3 Arithmetic 9 24 Branch Set on Unordered BSUN 9 18 9 25 9 27 Divide by Zero 9 36 Floating Point 9 5 Inexact Result INEX1 And INEX2 9 24 9 36 9 38 9 42 Multiple Exceptions 9 25 Operand Error OPERR 9 28 9 31 Overflow Exception OVFL 9 16 9 31 9 33 9 42 Round Off Error 9 11 SNAN Exception 9 27 9 28 Underflow UNFL 9 16 9 33 9 36 9 42 Floating Point Pipeline 9 1 9 26 Floating Point Registers Floating Point Status Register FPSR 1 8 9 4 9 15 AEXC Byte 9 5 Setting the AEXC 9 6 MOTOROLA EXC Byte 9 5 9 13 9 34 9 37 Floating Point Registers FPCC Byte 9 4 Quotient Byte 9 5 Floating Point Control Register FPCR 1 8 9 3 9 11 9 18 EN
91. Floating Point Unit 10 35 Section 11 68040 Electrical and Thermal Characteristics Maximum 11 1 Thermal Characteristics 11 1 DC Electrical Specifications eoe ente e teet situe 11 2 Power DissiIpallor soi ro E OH em e Ub 11 2 Clock AC Timing Specifications 11 3 Output AC Timing Specifications e HER Heaven 11 4 Input AC Timing 11 5 MC68040 Thermal Device Characteristics 11 12 MC68040 Die and Package 11 12 MC68040 Power Considerations 11 12 MC68040 Thermal Management Techniques 11 14 Sos cce rcu hsb aan ve owt ew Ne 11 17 Forced AD oa re 11 18 With Heat Sink 11 19 With Heat Sink and Forced 11 22 M68040 USER S MANUAL xiii TABLE OF CONTENTS Continued Paragraph Page Number Title Number Section 12 Ordering Information and Mechanical Data 12 1 Ordering Information ERE 12 1 12 2 ake nthe m eee 12 1 12 2 1 MC68040 Pi Grid ics csetera enu
92. High Impedance BCLK to BB 15 n High Impedance A 25 T 25 4 83 5 5 iss Output timing is specified for a valid signal measured at the pin Large buffer timing is specified driving a 50 Q transmission line with a length characterized by 2 5 ns one way propagation delay terminated through 50 Q to 2 5 V Large buffer output impedance is 4 12 resulting in incident wave switching for this environment All large buffer outputs must be terminated to guarantee operation 2 Small buffer timing is specified driving an unterminated 30 transmission line with a length characterized by a 2 5 ns one way propagation delay Small buffer output impedance is typically 30 Q the small buffer specifications include approximately 5 ns for the signal to propagate the length of the transmission line and back 3 Timing specifications 11 20 and 38 for address bus output timing apply when normal bus operation is selected Specifications 26 27 and 28 should be used when the multiplexed bus mode of operation is enabled 4 Timing specifications 18 and 19 for data bus output timing apply when normal bus operation is selected Specifications 28 and 29 should be used when the multiplexed bus mode of operation is enabled 5 Timing specifications 21 27 28 and 29 are measured from BCLK edges By design the MC68040 cannot drive
93. Instruction Exceptions For Opclass 000 and 010 Exception Instruction Command Word Source operand is converted to extended precision If format is packed ETM 63 0 contains bits 63 0 of the packed decimal operand Source operand tag undefined if format is packed FPTEMP Destination operand if any is converted to extended precision If format is packed 31 0 contains bits 95 64 of the packed decimal operand DTAG Destination operand tag if any Always 1 Alm m 2 gt gt m 9 Always 0 Unsupported Data For Opclass 000 and 010 Exception Instruction Command Word Source operand is converted to extended precision If format is packed ETM 63 0 contains bits 63 0 of the packed decimal operand Source operand tag undefined if format is packed FPTEMP Destination operand if any is converted to extended precision If format is packed FPTM 31 0 contains bits 95 64 of the packed decimal operand DTAG Destination operand tag if any Always 1 CMDREG1B STAG Always 0 Unsupported Data Type For Opclass 011 FMOVE Command Word Unrounded Source Operand from Floating Point Data Register Source Operand Tag Always 1 me g gt X ITI 9 Always 1 5 55 000 010 Exception Instruction Command Word ETEMP STAG Source Operand Tag Destination operand if any is converted to extended precision Source opera
94. Interrupt Acknowledge Termination Summary AVE Termination Condition Low Take Spurious Interrupt Exception Low High High Latch Vector Number D7 DO and Take Interrupt Exception Low Low Take Autovectored Interrupt Exception Low Retry Interrupt Acknowledge Cycle 7 5 1 4 INTERRUPT ACKNOWLEDGE BUS CYCLE TERMINATED NORMALLY When the M68040 processes an interrupt exception it performs an interrupt acknowledge bus cycle to obtain the vector number that contains the starting location of the interrupt exception handler Some interrupting devices have programmable vector registers that contain the interrupt vectors for the exception handlers they use Other interrupting conditions or devices cannot supply a vector number and use the autovector bus cycle described in 7 5 1 2 Autovector Interrupt Acknowledge Bus Cycle MOTOROLA M68040 USER S MANUAL 7 81 The interrupt acknowledge bus cycle is a read transfer It differs from normal read cycle in the following respects 1 TT1 and TTO 3 to indicate an acknowledged bus cycle 2 Address signals 1 0 are set to all ones FFFFFFFF TM2 TMO are set to the interrupt request level the inverted values of IPL2 IPLO The responding device places the vector number on the data bus during the interrupt acknowledge bus cycle and the cycle is terminated normally with TA Figures 7 21 and 7 22 illustrate a flowchart and functional timing diagram for an interrupt acknowledge cycle termi
95. M68040 USER S MANUAL 7 51 BCLK TRANSFER ATTRIBUTES PN 15 COEM r 4 T Me BUS OWNED BUS OWNED ALTERNATE ea ACTIVE AND IDLE gt MASTER PROCESSOR gt AM indicates the alternate bus master Undefined Figure 7 34 Implicit Bus Ownership Arbitration Timing 7 8 2 Bus Arbitration Examples The following paragraphs illustrate the behavior of the M68040 bus arbitration scheme and provide examples of how an external bus arbiter can be designed to keep the integrity of locked bus operations The examples include the previously mentioned indeterminate and disregard request conditions 7 8 2 1 DUAL M68040 FAIRNESS ARBITRATION The following state diagram illustrates a fairness algorithm using two MC68040s and assigning the least priority to the processor that owns the bus If both processors keep their respective BR signals asserted bus ownership alternates between the two processors so that each processor can run at least bus cycle during its tenure Each processor is allowed to own the bus without relinquishing it to maintain the integrity of locked transfers This example also illustrates 7 52 M68040 USER S MANUAL MOTOROLA how the LOCKE signal can be used to end locked sequence to yield the bus bus cycle earlier than is normally possible Figure 7 35 illustrates the state diagram of a hypothetical external
96. M68040 are optimized to support multimaster systems with the M68040 as the single caching master In systems MOTOROLA M68040 USER S MANUAL 4 9 implementing multiple 680405 as bus masters shared data should be stored write through pages This procedure allows each processor to cache shared data for read access while forcing a processor write to shared data to appear as an external write to memory which the other processors can snoop If shared data is stored in copyback pages only one processor at a time can cache the data since writes to copyback pages do not access the external bus If a processor accesses shared data cached by another processor the slave can source the data to the master without invalidating its own copy only if the transfer to the master is cache inhibited For the master processor to cache the data it must force invalidation of the slave processor s copy of the data by specifying mark invalid for the snoop operation and the memory controller must monitor the data transfer between the processors and update memory with the transferred data The memory update is required since the master processor is unaware of the sourced data valid data from memory or dirty data from a snooping processor and initially creates a valid cache line losing dirty status if a snooping processor supplies the data Coherency between the instruction cache and the data cache must be maintained in software since the instruction cache do
97. MC68040 Electrical and Thermal Characteristics for electrical specifications 5 9 3 Processor Clock PCLK Not on MC68040V and MC68ECO040V PCLK is used to derive all internal timing This clock is also TTL compatible and cannot be gated off Refer to Section 11 MC68040 Electrical and Thermal Characteristics for electrical specifications 5 10 MMU DISABLE 5 MC68EC040 The MMU disable signal dynamically disables the translation of addresses by the MMUs The assertion of MDIS does not flush the address translation caches ATCs entries become available again when is negated During a processor reset the level MDIS is latched and used to select the normal data latch mode high or DLE mode 5 low Refer to Section 3 Memory Management Unit Except MC68EC040 and 68 040 for a description of address translation and to Section 7 Bus Operation for information about DLE mode 5 11 DATA LATCH ENABLE DLE ONLY ON MC68040 This input signal is used in DLE mode to latch the input data bus on read transfers DLE mode can be used to support asynchronous memory interfaces by allowing the interface to specify when data should be latched instead of requiring data to be valid on the rising edge of BCLK 5 14 M68040 USER S MANUAL MOTOROLA 5 12 TEST SIGNALS The M68040 includes dedicated user accessible test logic that is fully compatible with the IEEE 1149 1 Standa
98. MMUSR appropriately and the program can branch to the appropriate code segment for the condition 3 34 M68040 USER S MANUAL MOTOROLA PTEST S 1 AND USER ACCESS INDICATED IN STACK FRAME OTHERWISE BRANCH TO SUPERVISOR VOILATION CODE OTHERWISE WRITE OR RMW ACCESS INDICATED IN STACK FRAME BRANCH TO BUS ERROR DURING TABLE SEARCH CODE aa OTHERWISE OTHERWISE MATCH TTR1 1 1 RMW ACCESS STACK BRANCH TO WRITE NOT MMU VIOLATION CODE Refers to either instruction or data transparent translation register BRANCH TO PAGE FAULT OR INVALID DESCRIPTOR CODE 0 OTHERWISE MATCH TTRO TTRO W 1 AND WRITE OR RMW ACCESS INDICATED IN Ce STACK FRAME OTHERWISE VIOLATION CODE ND WRITE OR INDICATED IN FRAME NOT MMU Figure 3 23 MMU Status Interpretation MOTOROLA M68040 USER S MANUAL 3 35 3 36 M68040 USER S MANUAL MOTOROLA SECTION 4 INSTRUCTION AND DATA CACHES NOTE Ignore all references to the memory management unit MMU when reading for the MC68EC040 and MC68EC040V The functionality of the MC68040 transparent translation registers has been changed in the MC68EC040 and MC68ECO40V to the access control registers Refer to Appendix B MC68EC040 for details The M68040 contains two independent 4 Kbyte on chip caches located in the physical address space Accessing instruction words and da
99. MOTOROLA M68040 USER S MANUAL 6 21 JTAG Timing Specifications All Operating Frequencies RS Boundary Scan Input Data Setup Time Boundary Scan Input Data Hold Time TCK to Output Data Valid TCK to Output High Impedance Figure 6 8 Clock Input Timing Diagram TCK Figure 6 9 TRST Timing Diagram 6 22 M68040 USER S MANUAL MOTOROLA DATA INPUTS INPUT DATA VALID DATA OUTPUTS OUTPUT DATA VALID lt O gt DATA OUTPUTS OUTPUT DATA VALID Figure 6 10 Boundary Scan Timing Diagram TCLK TDI TMS INPUT DATA VALID TDO OUTPUT DATA VALID TDO OUTPUT DATA VALID Figure 6 11 Test Access Port Timing Diagram MOTOROLA M68040 USER S MANUAL 6 23 6 24 M68040 USER S MANUAL MOTOROLA SECTION 7 BUS OPERATION The M68040 bus interface supports synchronous data transfers between the processor and other devices in the system This section provides a functional description of the bus the signals that control the bus and the bus cycles provided for data transfer operations Operation of the bus is defined for transfers initiated by the processor as a bus master and for transfers initiated by an alternate bus master which the processor snoops as a slave device Descriptions of the error and halt conditions bus arbitration and the reset operation are also included For timing specifications refer to Section 11 MC68040 Electrical and Thermal Characteristics NOTE
100. MOVE16 write fault WB1S is zero invalid 7 6 5 4 3 2 1 0 TM Transfer Modifier TT Transfer Type SIZE Transfer Size V Valid Write write back pending if set Figure 8 8 Write Back Status Format 8 4 6 4 FAULT ADDRESS The fault address FA is the initial address for the access that faulted The FA is a physical address only for cache pushes and a logical address for all other cases For a misaligned access that faults the FA field contains the address of the first byte of the transfer regardless of which of the two or three bus transfers for the misaligned access was faulted For a push fault the WB1A and FA addresses are the same 8 4 6 5 WRITE BACK ADDRESS AND WRITE BACK DATA Write back addresses WB3A WB2A WB1A are memory pointers that indicate where to place the write 8 26 M68040 USER S MANUAL MOTOROLA back data WB3D WB2D WB1D and WBSD correspond to the temporary holding register in the integer unit WB3 WB2A and WB2D correspond to the temporary holding register in the data memory unit WB2 prior to address translation WB1A and WB1D correspond to the temporary holding register in the bus controller WB1 which determines the external address and data bus bit patterns Refer to Section 2 Integer Unit for details on the operation of the integer unit pipeline The write back data in WB3D and WB2D is register aligned with byte and word data contained in the least significant byte and
101. Reset Out SC1 SCO High tow iw __ Snoop Control e T Transfer Acknowledge L Transfer Burst Inhibit Transfer Cache Inhibit Transfer Error Acknowledge n TLN1 TLNO High E D I W A I I A IP Transfer in Progress S S S S S S S S S Transfer Line Number S S Transfer Modifier W W W W W W W W W W W W W W W W W W Transfer Size 5 16 M68040 USER S MANUAL MOTOROLA Table 5 7 Signal Summary Continued _ L Ot n _ ms m n Tn mr m w _ 1 5 5 1 This signal is not available on the MC68LC040 68 040 2 These signals are different on power up for the MC68L C040 and 68 040 3 This signal is not available on the MC68EC040 MOTOROLA M68040 USER S MANUAL 5 17 5 18 M68040 USER S MANUAL MOTOROLA SECTION 6 IEEE 1149 1 TEST ACCESS PORT JTAG This section does not apply to the MC68040V and MC68ECO040V Refer to Appendix C MC68040V and 68 040 for details All references to M68040 in this section only refer to the MC68040 MC68LC040 and MC68EC040 The M68040 includes dedicated user accessible test logic that is fully compatible with the IEEE s
102. STOP If supervisor state STOP lt data gt then Immediate Data 2 SR STOP else TRAP S Destination Source e Destination SUB ea Dn SUB Dn ea MOTOROLA M68040 USER S MANUAL 1 19 Table 1 4 Instruction Set Summary Concluded SUBX Destination Source X e Destination SUBX Dx Dy SUBX SWAP Register 31 16 Register 15 0 SWAP Dn TAS Destination Tested c Condition Codes TAS ea 1 e bit 7 of Destination TRAP SSP 2 SSP Format Offset SSP TRAP lt vector gt SSP 4 e SSP PC e SSP SSP 2 eSSP SR SSP Vector Address 2 TRAPcc If cc TRAPcc then TRAP TRAPcc W lt data gt TRAPcc L lt data gt If V TRAPV then TRAP Destination Tested c Condition Codes e SP SP eAn SP 4 SP UNLK An Source Packed BCD adjustment Destination UNPACK Ax Ay t adjustment Unpacked BCD UNPACK Dx Dy adjustment 1 Where d is direction left or right 2 Available only on the MC68040 3 Wherer is rounding precision single or double precision 4 List refers to register 5 List refers to control registers only 6 Available only on the MC68040V and MC68bECO040V 7 16 ax ay is functionally the same as MOVE16 ax ay when ax ay The address register is only incremented once and the line is copied over itself rather than to the next line 8 Not available for MC68EC040 or MC68ECO040V 1 20 M68040 USER S MANUAL MOTOROLA
103. SUPERVISOR ONLY A second mechanism protects supervisor programs and data without requiring segmenting of the logical address space into supervisor and user address spaces Page descriptors contain S bits to protect areas of memory from access by user programs When a table search for a user access encounters an S bit set in a page descriptor the table search ends and an ATC descriptor corresponding to the logical address is created with the S bit set A subsequent retry of the user access results in an access error exception being taken The S bit can be used to protect one or more pages from user program access Supervisor and user mode accesses can share descriptors by using indirect descriptors or by sharing tables The entire user and supervisor address spaces can be mapped together by loading the same root pointer address into both the SRP and URP registers MOTOROLA M68040 USER S MANUAL 3 23 FOR TASK USER A LEVEL TABLE URP FOR TASK TRANSLATION r TABLE FOR TASK FOR TASK USER A LEVEL TABLE URP FOR TASK TRANSLATION TABLE FOR TASK POINTER SUPERVISOR A LEVEL TABLE COMMON SRP TRANSLATION TABLE FOR ALL SUPERVISOR ACCESSES Figure 3 17 Translation Table Structure for Two Tasks 3 2 6 3 WRITE PROTECT The M68040 provides write protection independent of other protection mechanisms All table and page descriptors contain W bits to protect areas of memory from
104. Shift Register coo roberto i re cb I E bp olet 6 3 EXTES saison tetas aae ADR ME rar aver 6 3 M68040 USER S MANUAL ix TABLE OF CONTENTS Continued Paragraph Page Number Title Number 6 2 2 HUGH 6 4 6 2 3 SAMPEE PREEDORD eee tes 6 4 6 2 4 S 6 4 6 2 5 SHUTDOWN cc 6 5 6 2 6 dall 2p 6 5 6 2 7 DRVOTE EO EA e 6 5 6 2 8 MC o 6 6 6 3 Boundary Scan pne 6 6 6 4 6 12 6 5 Disabling The IEEE Standard 1149 1 Operation 6 13 6 6 Motorola M68040 BSDL Description Version 2 2 6 15 6 7 MC68040 MC68LC040 MC68EC040 JTAG Electrical Characteristics 6 21 Section 7 Bus Operation 7 1 uuu o p 7 1 7 2 Data Transfer 7 3 7 3 Misaligned ONC FANGS uu uu uu dio dex uusha ss a 7 6 7 4 Processor Data 7 9 7 4 1 Byte Word and Long Word Read Transfers 7 10 7 4 2 Line Read RAN SION 7 12 7 4 3 Byte Word and Lo
105. Special Status Word Format 8 24 M68040 USER S MANUAL MOTOROLA CP Continuation of Floating Point Post Instruction Exception Pending CP is set for an access error with a floating point post instruction exception pending All pending accesses are allowed to complete after a trace condition is recognized If any of these accesses fault the resulting stack frame has the CT bit set and the effective address field contains the address of the instruction being traced The RTE fetches the appropriate floating point post instruction exception vector When post instruction exception occurs during tracing the post instruction exception takes precedence CP is set and 0 and can be traced The kernel must check for a trace condition using the stacked SH The effective address field contains the calculated effective address determined by the effective address field of the floating point instruction that caused the post instruction exception CU Continuation of Unimplemented Floating Point Instruction Exception Pending CU is set for an access error with a pending exception for an unimplemented floating point instruction Operation is the same as for the CP flag except the RTE fetches the F line exception vector The effective address field contains the calculated effective address determined by the effective address field of the unimplemented instruction When an unimplemented floating point instruction is traced the unimplemented exc
106. Supenisor Branch Not Taken End Current Instruction _ 1 1 Supenisor Branch Taken End Current Instruction 1 o Supenisor Table Search E Stopped State Supervisor Instruction i 1 1 RTE Executing 5 0 0 0 0 05050 000 NOTE MC68040V and MC68bECO040V only When a branch taken end current instruction is indicated it means that a change of instruction flow is pending Along with the following instructions an exception stacking encoding F sequence is ended with the supervisor branch taken end current instruction encoding as though it were a virtual JMP instruction This includes all the possible exceptions listed in the processor s vector table Instructions that cause a branch taken end current instruction encoding when they are executed are as follows ANDI to SR Taken MOVE to SR RTD Bcc Taken FBcc Taken MOVE USP RTE BRA FDBcc Always RTR BSR FMOVEM Rc MRn MOVES RTS CAS FMOVEM FPm MRn NOP STOP CAS2 FSAVE ORI to SR TAS CINV JMP PFLUSH CPUSH JSR PTEST The Bcc not taken and DBcc not taken are the only instructions that cause a branch not taken end current instruction encoding Note that the FBcc not taken is not included in this category The FBcc not taken instruction ends with an current instruction encoding All other instructions and conditions end with the end current instruction encoding For instance if the processor is runn
107. T Specification value at maximum frequency of operation PCLK BCLK Figure B 7 Clock Input Timing Diagram B 14 M68040 USER S MANUAL MOTOROLA B 7 6 Output AC Timing Specifications Figures 8 to B 12 Characteristic BCLK to Address CIOUT LOCK LOCKE 11 5 R W SIZx TTx UPAx Valid BCLK to Output Invalid Output Hold 11 5 i 5 o 5 5 o 5 n BCLK to Data Out High Impedance 11 5 25 BCLK to Address CIOUT LOCK LOCKE R W SIZx TS TLNx TMx TTx UPAx High Impedance 39 BCLK to BB High Impedance 23 5 5 5 5 o 3 3 3 3 5 o 11 12 13 14 18 19 20 1 2 5 o 5 o 3 co R BCLK to MI Valid BCLK to TA Valid 11 5 BCLK to IPEND PSTx RSTO Valid 11 5 Output timing is specified for a valid signal measured at the pin Timing is specified driving unterminated 30 0 transmission line with a length characterized by a 2 5 ns one way propagation delay Buffer output impedance is typically 30 O the buffer specifications include approximately 5 ns for the signal to propagate the length of the transmission line and back 0 BCLK to BR BB Valid 11 5 4 4 3 35 3 35 8 35 50 35 o MOTOROLA M68040 USER S MANUAL 15 7 7 Input AC Timing Specifications see Figures B 8 to 12
108. Test Reset Power Supply Ground NOTES Table 5 1 Signal Index Continued PCLK4 Clock input used for internal logic timing The PCLK frequency is exactly 2 x the BCLK frequency Clock signal for the IEEE P1149 1 Test Access Port TAP Selects the principle operations of the test support circuitry Serial data input for the TAP T Provides an asynchronous reset of the controller K S DI Serial data output for the TAP 4 C ND 1 This signal is only available on the MC68040 2 This signal is not available on the 68 040 and the MC68EC040V 3 These signals are different on power up for the MC68LC040 and MC68EC040 4 These signals are not available on the MC68040V and MC68bECO040V MOTOROLA M68040 USER S MANUAL 53 SCO BUS lt 7 AND RESPONSE BUS DD gt BR F 7 BG BUS ARBITRATION B m w MDIS PROCESSOR WD RSTI CONTROL RSTO TLNO TLN1 T _ TRANSFER Tm PLOS ATTRIBUTES PO UPAL IE INTERRUPT RAV 68040 FEND CONTROL 5170 5171 AVE LOCK LOCKE PSTO CIOUT PSTI PST2 STATUS AND PST3 CLOCKS MASTER 5 BR TRANSFER Tip CONTROL PCLK SLAVE TRANSFER ICI TEST CONTROL TBI TDO DLE TRST4 GNE POWER SUPPLY NOTES 1 This signal is only available on the MC68040 2 This signal is not available on the MC68EC040 and MC68EC040V 3 These signals ar
109. The M68040 memory management includes the following features Independent Instruction and Data Memory Management Units MMUs 32 Bit Logical Address Translation to 32 Bit Physical Address User Defined 2 Bit Physical Address Extension Addresses Translated in Parallel with Indexing into Data or Instruction Cache 64 Entry Four Way Set Associative Address Translation Cache ATC for Each MMU 128 Total Entries Global Bit Allowing Flushes of All Nonglobal Entries from ATCs Selectable 4K or 8K Page Size Separate Supervisor and User Translation tables Two Independent Blocks for Each MMU Can Be Defined as Transparent Untranslated Three Level Translation Tables with Optional Indirection Supervisor and Write Protections History Bits Automatically Maintained in Descriptors External Translation Disable Input Signal for Emulator Support Caching Mode Selected on Page Basis The MMUs completely overlap address translation time with other processing activities when the translation is resident in one of the ATCs ATC accesses operate in parallel with MOTOROLA M68040 USER S MANUAL 3 1 indexing into the on chip instruction and data caches The MMU 5 signal dynamically disables address translation for emulation and diagnostic support Figure 3 1 illustrates the MMUs contained in the two memory units one for instructions supporting instruction prefetches and one for data supporting all other accesses Each unit co
110. The data transparent translation registers DTTRO and DTTR1 and instruction transparent translation registers ITTRO and ITTR1 are 32 bit registers that define blocks of logical address space The TTRs operate independently of the E bit in the TCR and the state of the signal Data transfers to and from these registers are long word transfers The TTR fields are defined following Figure 3 5 which illustrates TTR format Bits 12 10 7 4 3 1 and 0 always read as zero 24 23 16 13 11 OSNEWS Figure 3 5 Transparent Translation Register Format Logical Address Base This 8 bit field is compared with address bits A31 A24 Addresses that match in this comparison and are otherwise eligible are transparently translated Logical Address Mask Since this 8 bit field contains a mask for the Logical Address Mask field setting a bit in this field causes the corresponding bit in the Logical Address Base field to be ignored Blocks of memory larger than 16 Mbytes can be transparently translated by setting some of the logical address mask bits to ones The low order bits of this field can be set to define contiguous blocks larger than 16 Mbytes E Enable This bit enables or disables transparent translation of the block defined by this register 0 Transparent translation disabled 1 Transparent translation enabled S Supervisor Mode This field specifies the way FC2 is used in matching an address 0
111. UPA1 5121 5120 TT1 TTO TM2 TMO D31 D0 lt WRITE STACK CYCLE gt Figure 7 26 Word Write Access Terminated with TEA Timing 7 39 M68040 USER S MANUAL MOTOROLA 1 1 ii l 1 1 1 1 A2 A0 5171 5170 oN TBI ENDS BURST 2 01 10 11 lt NO EXCEPTION NOTE The selected device increments the value on and A2 Figure 7 27 Line Read Access Terminated with TEA Timing 7 40 M68040 USER S MANUAL MOTOROLA 7 6 2 Retry Operation When an external device asserts both the TA and TEA signals during a bus cycle the processor enters the retry sequence The processor terminates the bus cycle and immediately retries the cycle using the same access information address and transfer attributes However if the bus cycle was a cache push operation the bus is arbitrated away from the M68040 before the retry operation and a snoop during the arbitration invalidates the cache push then the processor does not use the same access information Figure 7 28 illustrates a functional timing diagram for a retry of a read bus transfer 5171 5170 LONG WORD TT1 TTO RW CIOUT FEMA i E m 7 READ CYCLE RETRY RETRY SIGNA
112. Unit Support Timings Continued Addressing Byte Word and Long Word Single and Double Precision Extended Precision Mode ea ea ea Calculate Calculate Calculate An An lt gt d 16 An d 16 PC dg An Xn dg PC Xn Timings are for an idle floating point unit MOTOROLA M68040 USER S MANUAL 10 31 10 7 2 Integer Unit Support Timings Continued FMOVE FMOVEM to from FMOVEM lt list gt lt ea gt FScc Addressing 1 Control Register and lt ea gt lt list gt P Mode ea lt gt Calculate Calculate An An lt XXX gt 5 d 16 d16 PC dg An Xn dg PC Xn An Xn bd An Xn NOTES a Timings are for an idle floating point unit Same as FMOVE lt ea gt FPCR b Add three clocks to both lt ea gt calculate and execute times for each additional floating point register Add one clock to both lt ea gt calculate and execute times for dynamic register list 10 32 M68040 USER S MANUAL MOTOROLA 10 7 2 Integer Unit Support Timings Continued FSAVE lt gt __ Mou Short ea ea ea Calculate Calculate Calculate Addressing An An lt XXX gt 416 dg An Xn dg PC Xn Timings are for an idle floating point unit MOTOROLA M68040 USER S MANUAL 10 33 10 7 2 Integer Unit Support Timings Concluded FRESTORE lt gt ea ea ea
113. about the relationship of the arbitration signals to bus operation 5 6 1 Bus Request This output signal indicates to the external arbiter that the processor needs to become bus master for one or more bus transfers BR is negated when the M68040 begins an access to the external bus with no other accesses pending and BR remains negated until another access is required There are some situations in which the M68040 asserts BR and then negates it without having run bus transfers this is a disregard request condition Refer to Section 7 Bus Operation for details about this state 5 6 2 Bus Grant This input signal from an external arbiter indicates that the bus is available to the M68040 as soon as the current bus access completes BG must be asserted and BB must be negated indicating the bus is free before the M68040 assumes ownership of the bus 5 6 3 Bus Busy This three state bidirectional signal indicates that the bus is currently owned BB is monitored as a processor input to determine when a alternate bus master has released control of the bus must be asserted and BB must be negated indicating the bus is free before the M68040 asserts BB as an output to assume ownership of the bus The processor keeps BB asserted until the external arbiter negates BG and the processor completes the bus transfer in progress When releasing the bus the processor negates BB then sets it to a high impedance state for use again a
114. address and data simultaneously during multiplexed operations BCLK to BR BB Valid 2 5 o 42 39 40 43 48 50 11 4 M68040 USER S MANUAL MOTOROLA 11 INPUT AC TIMING SPECIFICATIONS see Figures 11 3 to 11 7 Characteristic ata In Valid to BCLK Setup CLK to Data In Invalid Hold Read Followed by Write 23 m 25 s 22 m BG Valid to BCLK Setup CDIS MDIS Valid to BCLK Setup Lx Valid to BCLK Setup 42 CLK to BB BG CDIS IPLx MDIS Invalid Hold 44a Address Valid to BCLK Setup 44b SIZx Valid to BCLK Setup 44c TTx Valid to BCLK Setup 44d R W Valid to BCLK Setup 44 SCx Valid to BCLK Setup 45 BCLK to Address SIZx TTx R W SCx Invalid Hold 46 TS Valid to BCLK Setup 47 BCLK to TS Invalid Hold BCLK to BB High Impedance MC68040 Assumes Bus Mastership RSTI Valid to BCLK CLK to RSTI Invalid ode Select Setup to RSTI Negated RSTI Negated to Mode Selects Invalid 5 a 3 o EF 5 o 5 5 o E O 512515 jojo o 5 5 o 42 3 24 _ gt KS 34 35 A olo 51515 a K gt o UJ 5 o 3 o 5 o 5 o 5 o gt 2 5 5 72 72 5 5 5 5 5 A c 5 o M68040 USER S MANUAL 11 5 DRIVE TO24
115. and 7 24 M68040 USER S MANUAL MOTOROLA MC68LC040 memory units and Appendix MC68EC040 for information the MC68EC040 memory unit The processor asserts TS during C1 to indicate the beginning of a bus cycle If not already asserted from a previous bus cycle the TIP signal is also asserted at this time to indicate that a bus cycle is active Clock 2 C2 During the first half of the first clock after C1 the processor negates TS and drives the data bus with the data to be written The selected device uses R W SIZ1 and SIZO to latch the data on the data bus Concurrently the selected device asserts TA and either negates or asserts TBI to indicate it can or cannot support a burst transfer At the end of the first clock after C1 the processor samples the level of TA and TBI If TA is asserted the transfer terminates If TA is not recognized asserted the processor inserts wait states instead of terminating the transfer The processor continues to sample TA and TBI on successive rising edges of BCLK until TA is recognized asserted If TBI was negated with TA the processor continues the cycle with C3 Otherwise if TBI was asserted the line transfer is burst inhibited and the processor writes the remaining three long words using long word write bus cycles Only in this case does the processor increment A3 and A2 for each write and the new address is placed on the address bus for each bus cycle Refer to 7 4 3 Byte Word and Long W
116. arbiter design BB A LOCK A LOCKE BB ALOCK V B LOCK A LOCKE STATEC STATE D BR1 ALOCK A LOCKE EET V BR1ALOCK BRI VBRIA LOCK ALOCKE BR2 V STATE B BR2 A LOCK A LOCKE BR2 A LOCK A LOCKE V BR2 ALOCK ALOCK V BB A STATE A K ALOCKE BB A LOCK A LOCKE NOTES 1 Because this example uses two MC68040s 1 and 2 refer to the processor and its signals 2 Indicates the signal is asserted for that device Figure 7 35 Dual M68040 Fairness Arbitration State Diagram Assuming that processor 1 currently owns the bus the external arbiter is in state A If processor 2 asserts BR2 then processor 1 behaves in one of three ways 1 If processor 1 is currently in the middle of a nonlocked bus access then the external arbiter proceeds to state B in which BG1 is negated and BG2 is asserted The external arbiter then proceeds to state C only when BB is negated signifying the end of the bus cycle 2 processor 1 is currently in the middle of a locked bus access then the external arbiter stays in state A until LOCKE is asserted Once LOCKE is asserted the external arbiter enters state B in which BG1 is negated and BG2 is asserted external arbiter proceeds to state C once BB is negated signifying the end of the bus cycle 3 If processor 1 is in one of the three boundary conditions then the external arbiter proceeds to state B During state B the external arbiter checks for the possibility of a
117. are cleared in the test logic reset state 5 Renamed JSO on the MC68LC040 and MC68EC040 6 Renamed JS1 on the MC68EC040 io 1 gt 6 4 RESTRICTIONS The test logic is implemented using static logic design can be stopped in either a high or low state without loss of data The system logic however includes considerable dynamic logic For this reason the system clocks PCLK and BCLK cannot be stopped or allowed to run slower than the specified frequency except when the EXTEST HIGHZ DRVCTL T or SHUTDOWN instructions have been properly invoked PCLK and BCLK must be kept running for two additional BCLK periods upon initial entry into any of the four instructions EXTEST HIGHZ DRVCTL T or SHUTDOWN This restriction is necessary to allow time for an internal reset to propagate through an internal synchronizer After this period the user has complete time domain freedom with the two system clock pins After any of the four instructions has been properly entered these instructions can be executed in any order without a time domain clocking restriction Entering any instruction other than one of these four requires that the system clocks be 6 12 M68040 USER S MANUAL MOTOROLA restarted and a proper reentry into any of the four instructions is again required before the system clocks can be stopped Control over the output enable signals using the boundary scan register and the EXTEST and HIGHZ
118. asserts TS during C1 to indicate the beginning of a bus cycle If not already asserted from a previous bus cycle TIP is also asserted at this time to indicate that a bus cycle is active Clock 2 C2 During the first half of the first clock after C1 the processor negates TS The selected device uses R W SIZ1 and SIZO to place the data on the data bus The first transfer must supply the long word at the corresponding long word boundary Concurrently the selected device asserts TA and either negates or asserts TBI to indicate it can or cannot support a burst transfer At the end of the first clock cycle after C1 the processor samples the level of TA TBI and TCI and latches the current value on the data bus If TA is asserted the transfer terminates and the data is passed to the appropriate memory unit If TA is not recognized asserted the processor ignores the data and inserts wait states instead of terminating the transfer The processor continues to sample TA TBI and TCI on successive rising edges of BCLK until TA is recognized asserted The latched data and the level on TCI are then passed to the appropriate memory unit If TBI was negated with TA the processor continues the cycle with C3 Otherwise if TBI was asserted the line transfer is burst inhibited and the processor reads the remaining three long words using long word read bus cycles The processor increments A3 and A2 for each read and the new address is placed on the addr
119. begin processing future instructions for conditional branches while the main pipeline is processing current instructions The ea calculate stage eliminates pipeline blockage for instructions with postincrement postdecrement or immediate add and load to address register for updates that occur in the ea calculate stage The write back stage can write data over the system bus to store a result in external memory or directly to on chip caches These write backs to memory can be deferred until the most opportune moment because of the M68040 bus interface Figure 2 1 illustrates the IU pipeline MOTOROLA M68040 USER S MANUAL 2 1 INSTRUCTION DATA FROM CACHE OR BUS CONTROLLER SHADOW INSTRUCTION FETCH Figure 2 1 Integer Unit Pipeline SHADOW FPU TO CACHE OR BUS CONTROLLER TO CACHE OR BUS CONTROLLER An instruction stream is fetched from the instruction memory unit and decoded on an instruction by instruction basis in the decode stage Multiple instructions are fetched to keep the pipeline stages full so that the pipeline will not stall The decoded instruction is then passed to the lt ea gt calculate stage to calculate the effective addresses that the instruction requires The lt ea gt calculate stage initiates additional fetches from the instruction stream to obtain the effective address extension words and performs the effective address calculation The initial execution of the instruction in
120. bus cycles Note that BB and TIP and TA if driven during a snooped access are negated before transitioning to a three state level lt t210 gt lt 2 gt lt 128 gt CLOCKS CLOCKS CLOCKS I RSTI ME TN B Jbh o qo gn pe i CDIS MDIS IPL2 IPL0 Bis EE EE SIGNALS TN TS N N I I I T T T Figure 7 45 Normal Reset Timing Resetting the processor causes any bus cycle in progress to terminate as if TA or TEA had been asserted In addition the processor initializes registers appropriately for a reset exception Section 8 Exception Processing describes exception processing When a RESET instruction is executed the processor drives the reset out RSTO signal for 512 BCLK cycles In this case the processor resets the external devices of the system and the internal registers of the processor are unaffected The external devices connected to the RSTO signal are reset at the completion of the RESET instruction An RSTI signal that is asserted to the processor during execution of a RESET instruction immediately resets the processor and causes the RSTO signal to negate RSTO can be logically ANDed with
121. bus transfer Transfer Start Indicates the beginning of a bus transfer Transfer in Progress Asserted for the duration of a bus transfer Transfer Acknowledge Asserted to acknowledge a bus transfer Transfer Error T Indicates an error condition exists for a bus transfer Acknowledge Transfer Cache Inhibit C Indicates the current bus transfer should not be cached Transfer Burst Inhibit Indicates the slave cannot handle a line burst access Data Latch Enable DL Alternate clock input used to latch input data when the processor is operating in DLE mode Snoop Control SC1 SCO Indicates the snooping operation required during an alternate master access Asserted by an arbiter to grant bus mastership to the processor Asserted by the current bus master to indicate it has assumed ownership of the bus Autovector AV Used during an interrupt acknowledge transfer to request internal generation of the vector number Processor Status PST3 PSTO0 Indicates internal processor status Bus Clock BCLK Clock input used to derive all bus signal timing T T T Memory Inhibit M Inhibits memory devices from responding to an alternate master access during snooping operations B B B Bus Request Asserted by the processor to request bus mastership S IP A EA T BI E I R G B EC 5 2 M68040 USER S MANUAL MOTOROLA Signal Name Processor Clock Test Clock Test Mode Select Test Data Input Test Data Output
122. can be 4 8 M68040 USER S MANUAL MOTOROLA avoided by pushing cache lines when page descriptor is changed and ensuring that alternate bus masters indicate the appropriate snoop operation for writes to corresponding pages i e mark invalid for write through pages and sink data for copyback pages If the access is copyback the cache controller updates the cache line and sets the D bit for of the appropriate long words in the cache line An external write is not performed and the cache line state changes to or remains in the dirty state An alternate bus master can drive the SCx signals for a write access with an encoding that indicates to the M68040 that it should sink the data inhibit memory and respond as a slave if the access hits in the cache The cache operation depends on the access size and current line state A snooped line write that hits a valid line always causes the corresponding cache line to be invalidated For snooped writes of byte word or long word size that hit a dirty line the processor inhibits memory and responds to the alternate bus master as a slave sinking the data Data received from the alternate bus master is written to the appropriate long word in the cache line and the D bit is set for that entry The cache controller invalidates a cache line if the snoop control pins have indicated that a matching cache line is marked invalid for a snoop write 4 5 CACHE COHERENCY The M68040 provides several different me
123. can be invalidated during the alternate bus master s access to memory or memory can be inhibited to allow the M68040 to respond to the access as a slave For an external write operation the processor can intervene in the access and update its internal caches sink data For an external read operation the processor supplies cached data to the alternate bus muster source data This prevents the M68040 caches from accumulating old or invalid copies of data stale data Alternate bus masters are allowed access to locally modified data within the caches that is no longer consistent with external memory dirty data Allowing memory pages to be specified as write through instead of copyback also supports cache coherency When a processor writes to write through pages external MOTOROLA M68040 USER S MANUAL 4 1 memory is always updated through an external bus access after updating the cache keeping memory and cached data consistent INSTRUCTION DATA BUS INSTRUCTION MEMORY UNIT CONVERT DECODE CALCULATE EXECUTE EA FETCH EXECUTE DATA MEMORY UNIT DATA WRITEBACK E gt MMU CACHE SNOOP CONTROLLER ADDRESS BUS Cn cw INSTRUCTION INSTRUCTION E TEES MMU CACHE SNOOP FETCH CONTROLLER 4 BUS CONTROL SIGNALS FLOATING POINT UNIT OPERAND DATA BUS Figure 4 1 Overview of Internal Caches 4 1 CACHE OPERATION Both fou
124. considers the read portion of read modify write transfers for TAS CAS CAS2 and some translation table updates a write This prevents both read and write accesses from occurring unless all pages touched by the instruction or table update are write enabled All accesses other than instruction prefetches go through the data memory unit and the M68040 treats the instruction and data address spaces as a single merged address space the exception is the presence of separate transparent translation registers The function codes for accesses such as PC relative operand addressing and MOVES transfers to function codes 2 and 6 user and supervisor instruction spaces in the MC68000 are converted to data references to go through the data memory unit and appear in the TM field of the access error stack frame as data references 8 28 M68040 USER S MANUAL MOTOROLA After the fault is corrected any pending write backs on the stack frame must be completed The write back status fields should be checked for possible write backs which the exception handler should complete in the following order write back 1 write back 2 and write back 3 For a push fault the push must be completed first followed by two potential write backs Completion of write back 1 should not generate another access error since this write back corresponds to the faulted access that has been corrected by the handler However write backs 2 and 3 can cause another bus error exception w
125. data and program accesses in the user and supervisor modes Some instructions use the alternate function code registers to specify the function codes for various operations The cache control register CACR controls enabling of the on chip instruction and data caches of the MC68040 The supervisor root pointer SRP and user root pointer URP registers point to the root of the address translation table tree to be used for supervisor and user mode accesses The translation control register TCR enables logical to physical address translation and selects either 4 or 8 Kbyte page sizes There are four transparent translation registers two for instruction accesses and two for data accesses These registers allow portions of the logical address space to be transparently mapped and accessed without the use of resident descriptors in an ATC The MMU status register MMUSR contains status information derived from the execution of a PTEST instruction The PTEST instruction searches the translation tables for the logical address specified by this instruction s effective address field and the DFC and returns status information corresponding to the translation The user programming model can also access the entire floating point programming model The eight 80 bit floating point data registers are analogous to the integer data registers A 32 bit floating point control register FPCR contains an exception enable byte that enables and disables traps fo
126. do not take the trace exception This mode also includes SR manipulations because the processor must prefetch instruction words again to fill the pipeline any time an instruction that modifies the SR is executed Table 8 2 lists the different trace modes 8 10 M68040 USER S MANUAL MOTOROLA Table 8 2 Tracing Control o o emas Trace Change of Flow Trace on Instruction Execution Any Instruction Undefined Reserved When the processor is in the trace mode and attempts to execute an illegal or unimplemented instruction that instruction does not cause a trace exception since the instruction is not executed This is of particular importance to an instruction emulation routine that performs the instruction function adjusts the stacked PC to skip the unimplemented instruction and returns Before returning the trace bits of the SR on the stack should be checked If tracing is enabled the trace exception processing should also be emulated for the trace exception handler to account for the emulated instruction Trace exception processing starts at the end of normal processing for the traced instruction and before the start of the next instruction As illustrated in Figure 8 1 the processor makes an internal copy of the SR and enters the supervisor mode It also clears the T1 and TO bits of the SR disabling further tracing The processor supplies vector number 9 for the trace exception and saves the
127. end of each transfer In some applications this mode can reduce the number of clocks required to perform line burst reads A logic zero on the MDIS enables this mode during a processor reset Figure 7 47 illustrates a conceptual block diagram of the logic used to latch the read data bus in DLE mode The DLE signal controls transparent latch A which allows data to be latched before the rising edge of BCLK Latch A operates transparently when DLE is negated and latches the level on the data bus when DLE is asserted Note that the DLE signal only controls latching of the read data and does not affect termination of the bus MOTOROLA M68040 USER S MANUAL 7 69 transfer Edge triggered latch is clocked by the rising edge of BCLK latches the data from latch A for use by internal logic T WRITE DATA EXTERNAL TRANSPARENT EDGE TRIGGERED DATA BUS LATCH A LATCH B LATCHED READ DATA DLE TERMINATION CONTROL Figure 7 47 DLE Mode Block Diagram Figure 7 48 illustrates the data read timing for both normal operation and DLE mode During normal operation i e DLE mode disabled latch A is always transparent and by the rising edge of BCLK read data is latched Data must meet setup and hold time specifications 15 and 16 in this case When the DLE mode is enabled the data can be latched by the rising edge of BCLK or the falling edge of DLE depending on the timing for DLE 7 70 M68040 USER S MANUAL MOTOR
128. first bus cycle for reset exception processing begins In Figure B 6 the processor assumes implicit ownership of the bus before the first bus cycle begins The levels on the CDIS 51 MDIS on the MC68040 and IPL2 IPLO signals are not sampled when RSTI is negated For processor resets after the initial power on reset RSTI should be asserted for at least 10 clock periods Figure B 6 illustrates timing associated with a reset when the processor is executing bus cycles Note that BB and TIP and TA driven during a snooped access are asserted before transitioning to a three state level Processor reset causes any bus cycle in progress to terminate as if TA or TEA had been asserted Also the processor initializes registers appropriately for a reset exception lt lt t210 2 128 CLOCKS CLOCKS CLOCKS BCLK RSTI BUS SIGNALS 15 jo s Figure B 6 MC68EC040 Normal Reset Timing When a RESET instruction is executed the processor drives the reset out RSTO signal for 512 BCLK cycles In this case the processor resets the external devices of the system and the internal registers of the processor are unaffected The external devices connected to RSTO are reset at the completion of the RESET instruction An RSTI signal that is asserted to the processor during execution of a RESET instruction immediately resets the processor and causes RSTO to negate RTSO can be logic
129. floating point unit FPU and their respective registers the MC68EC040 programming model data formats and types instruction set except all instructions beginning with an F PTEST and PFLUSH and caches are the same as described in Section 1 Introduction for the MC68040 Figures B 2 and B 3 illustrate the programming model and functional signal groups for the 68 040 2 68040 USER S MANUAL MOTOROLA DATA REGISTERS ADDRESS REGISTERS ATIUSP USER STACK POINTER PC PROGRAM COUNTER CCR CONDITION CODE REGISTER USER PROGRAMMING MODEL 0 AT ISP INTERRUPT STACK POINTER AT MSP MASTER STACK POINTER SR STATUS REGISTER VBR VECTOR BASE REGISTER SFC SOURCE FUNCTION CODE DFC DESTINATION FUNCTION CODE CACR CACHE CONTROL REGISTER DACRO DATA ACCESS CONTROL REGISTER 0 DACR1 DATA ACCESS CONTROL REGISTER 1 IACRO INSTRUCTION ACCESS CONTROL REGISTER 0 IACR1 INSTRUCTION ACCESS CONTROL REGISTER 1 SUPERVISOR PROGRAMMING MODEL Figure B 2 MC68EC040 Programming Model MOTOROLA M68040 USER S MANUAL 3 SCO ADDRESS BUS SNOOP CONTROL BUS a AND RESPONSE BUS m 7 BG BUS ARBITRATION m T iri RSTI L PROCESSOR RSTO CONTROL RSTO TLNO 2 TRANSFER _ IPLO ATTRIBUTES PO p 68 040 iPEND 5170 gt 7m AVEC LOCK LOCKE 5570 eot
130. for the CPUSH instruction is dependent on several factors such as the number of dirty cache lines and the size of the resulting push either long word or line the overlapping operations within the data cache and the bus controller the distribution of dirty cache lines and the number of wait states in the push access on the bus The interaction of these factors determines the total time required to execute a CPUSH instruction Since the distribution of dirty data within the cache is entirely dependent on the nature of the user s code it is impossible to provide an equation for execution time that works for all code sequences Table 10 4 provides baseline information indicating best and worst case execution times for the three CPUSH instruction variants Best case corresponds to a cache containing no dirty entries while the worst case corresponds to all lines dirty and requiring line pushes In Table 10 4 line refers to the number of clocks required in the user s system for a line transfer Idle refers to the number of clocks required for all pending writes and instruction prefetches to complete Table 10 4 CPUSH Best and Worst Case Timing CPUSHL 6 Line Idle CPUSHP 267 11 256 x Line CPUSHA 10 8 M68040 USER S MANUAL MOTOROLA 10 4 MOVE INSTRUCTION TIMING ea SOURCE Calculate 2 gt xxx L lt XXX gt
131. frames included for exception processing are four and six word stack frames a four word throwaway stack frame an access error stack frame and a new eight word unimplemented floating point stack frame The stack frame that the MC68040 can generate and the 68 040 can process is the floating point post instruction stack frame Refer to Section 8 Exception Processing for details about exception stack frames Eight Word Stack Frame Format 4 The MC68040 cannot Effective address field is SP gt STATUS REGISTER generate or read this stack the address of the faulted PROGRAM COUNTER instruction operand 4506 0100 VECTOR OFFSET 508 EFFECTIVE ADDRESS PC OF FAULTED 00 INSTRUCTION When the MC68EC040 writes or reads a stack frame it uses long word operand transfers wherever possible Using a long word aligned stack pointer greatly enhances exception processing performance The processor does not necessarily read or write the stack frame data in sequential order The system software should not depend on a particular exception generating a particular stack frame For compatibility with future devices the software should be able to handle any type of stack frame for any type of exception The MC68ECO040 does not generate the floating point post instruction stack frame The MC68040 cannot accept the eight word unimplemented stack frame The 68 040 can handle all MC68040 stack frame formats MOTOROLA M68040 USER S MA
132. go to invalid D11 No action go to invalid Snoop Control 10 state Invalidate Alternate Master Write Hit 112 Not Possible V12 No action go to invalid D12 Inhibit memory and Snoop Control 01 sink data set Dn bits Sink Data and of modified long Size Line words remain in current state Alternate Master Write Hit Not Possible V13 No action go to invalid D13 No action go to invalid Snoop Control 01 state Sink Data and Size Line 4 18 M68040 USER S MANUAL MOTOROLA SECTION 5 SIGNAL DESCRIPTION This section contains brief descriptions of the input and output signals in their functional groups see Figure 5 1 Each signal s function is briefly explained referencing other sections that contain detailed information about the signal and related operations Table 5 1 lists the signal names mnemonics and functional descriptions of the input and output signals for the M68040 Timing specifications for these signals can be found in Section 11 68040 Electrical and Thermal Characteristics MOTOROLA NOTES Assertion and negation are used to specify forcing a signal to a particular state Assertion and assert refer to a signal that is active or true Negation and negate refer to a signal that is inactive or false These terms are used independent of the voltage level high or low that they represent For the MC68040V MC68LC040 68 040 and MC68ECO40V ignore all referenc
133. input X amp 135 2 0 output3 X 150 0 2 amp 136 4 0 input X amp 187 BC_2 TM 2 output3 X 156 0 2 amp 156 io 0 138 2 1 output3 X 156 0 2 amp 139 BC 2 0 output3 X 156 0 2 amp 140 2 TLN 1 output3 X 156 0 2 amp 141 2 output3 X 156 0 2 142 2 510 output3 X 156 0 2 143 4 510 amp 144 2 RW output3 X 156 0 2 145 4 RW amp 146 2 LOCKE output3 X 156 0 2 amp 147 2 SIZ 1 X 156 0 2 148 4 511 amp 149 2 LOCK output3 X 156 0 2 amp 150 BC 2 controlr 0 io ab 151 BC 2 controlr 0 0 96 152 2 output2 X 153 2 output2 X 154 2 0 10 2 155 BC 2 controlr 0 io 1 156 BC 2 0 10 0 157 2 TS output3 X 156 0 2 amp 156 10 0 158 4 TS input X amp 159 2 BB output3 X 155 0 2 amp 155 io 1 160 4 BB input X amp 161 2 output3 X 155 0 2 155 io 1 162 2 PST 3 output2 X 63 BC 2 PST 2 X amp 164 2 PST
134. instructions requires a compatible circuit board test environment to avoid destructive configurations The user is responsible for avoiding situations in which the M68040 output drivers are enabled into actively driven networks The TRST signal provides the ability for an asynchronous reset of the test logic and requires no internal clocking to force the TAP controller into the test logic reset state This signal should be asserted during system power up to initialize the 1149 14 test interface and avoid the potential for board level bus conflicts Essentially the TRST signal provides the ability to prevent possible board level bus contention during power up due to the test logic having control of the pins The device has no internal power up reset circuit The TRST signal should be treated similar to the signal for board design considerations concerning power up conditions Negation of the TRST signal requires certain precautions to achieve a predictable TAP controller state The TMS signal is sampled on the rising edge of TCK and sequences the TAP controller If TMS is low and TRST is negated simultaneously with the rising edge of TCK the resultant TAP controller state is unpredictable but will be either test logic reset or run test idle To avoid this uncertainty either 1 the negation of TRST can be synchronized with the falling edge of TCK or 2 TMS can remain high until after TRST negation Alternatively holding TMS low for two or mo
135. is asserted if the access is identified as noncachable or if the access references an alternate address space Refer to Section 3 Memory Management Unit Except MC68EC040 68 040 for information on the M68040 and MC68LC040 memory units and Appendix MC68bECO040 for information on the MC68EC040 memory unit The processor asserts TS during C1 to indicate the beginning of a bus cycle If not already asserted from a previous bus cycle the TIP signal is also asserted at this time to indicate that a bus cycle is active MOTOROLA M68040 USER S MANUAL 7 21 Clock 2 C2 During the first half of the clock after C1 the processor negates TS and drives the appropriate bytes of the data bus with the data to be written All other bytes are driven with undefined values The selected device uses R W SIZ1 5120 1 0 and CIOUT to latch only the required information on the data bus With the exception of R W and CIOUT these signals also select any or all of the bytes 031 024 023 016 015 08 and 07 00 If the first clock after C1 is not a wait state then the selected peripheral device asserts the TA signal At the end of the first clock cycle after C1 the processor samples the level of TA terminating the bus cycle if TA is asserted If TA is not recognized asserted at the end of the clock cycle the processor ignores the data and inserts a wait state instead of terminating the transfer The processor continues to sample TA
136. is in memory or an integer data register then the rounding precision in the FPCR MODE byte is ignored and the given destination format defines the rounding precision If the instruction has a forced rounding precision e g FSADD FDMUL the instruction defines the rounding precision The M68040FPSP OVFL exception handler then checks to see if the user OVFL exception handler is enabled MOTOROLA M68040 USER S MANUAL 9 31 Table 9 12 Overflow Rounding Mode Values Rounding Mode Infinity with the sign of the intermediate result For positive overflow largest positive number for negative overflow infinity For positive overflow infinity for negative overflow largest negative number Largest magnitude number with the sign of the intermediate result a If the user OVFL exception handler is disabled the M68040FPSP OVFL exception handler checks for an INEX1 or INEX2 exception condition with the user INEX exception handler enabled If not the processor returns to normal instruction flow Otherwise the M68040FPSP OVFL exception handler restores the FPU to its exceptional state cleans up the stack to the conditions prior its execution and continues instruction execution at the user INEX exception handler No parameters are passed to the user INEX exception handler since the M68040FPSP OVFL exception handler provides the illusion that it never existed Otherwise the M68040FPSP OVFL exception handler returns the processor
137. is recognized asserted The data is then passed to the processor s appropriate memory unit When the processor recognizes TA at the end of a clock and terminates the bus cycle TIP remains asserted if the processor is ready to begin another bus cycle Otherwise the processor negates TIP during the first half of the next clock 7 4 2 Line Read Transfer The processor uses line read transfers to access a 16 byte operand for a MOVE16 instruction and to support cache line filling A line read accesses a block of four long words aligned to a 16 byte memory boundary by supplying a starting address that points to one of the long words and requiring the memory device to sequentially drive each long word on the data bus The selected device must internally increment A3 and A2 of the supplied address for each transfer causing the address to wrap around at the end of the block The address and transfer attributes supplied by the processor remain stable during the transfers and the selected device terminates each transfer by driving the long word on 7 12 M68040 USER S MANUAL MOTOROLA the data bus asserting TA A line transfer performed in this manner with a single address is referred to as a line burst transfer The M68040 also supports burst inhibited line transfers for memory devices that are unable to support bursting For this type of bus cycle the selected device supplies the first long word pointed to by the processor address and asserts
138. is stored as the result in the 16 bit extended precision format exponent For example if the data format and rounding mode is single precision RM and the result of an arithmetic operation overflows the magnitude of the single precision format the largest normalized single precision value is stored as an extended precision number in the destination floating point data register i e an unbiased 15 bit exponent of 00FF and a mantissa of If an infinity is the appropriate result for an underflow or overflow the infinity value for the destination data format is stored as the result i e an exponent with the maximum value and a mantissa of zero Figure 9 8 illustrates the algorithm that is used to round an intermediate result to the selected rounding precision and destination data format If the destination is a floating point data register either the selected rounding precision specified by the FPCR PREC bits or by the instruction itself determines the rounding boundary For example FSADD and FDADD specify single and double precision rounding regardless of the precision specified in the FPCR PREC bits If the destination is external memory or an integer data register the destination data format determines the rounding boundary If the rounded result of an operation is not exact then the INEX2 bit is set in the FPSR EXC byte MOTOROLA M68040 USER S MANUAL 9 13 ENTRY GUARD ROUND AND STICKY BITS 0
139. location containing the physical address Only a portion of the translation table for the entire logical address space is required to be resident in memory at any time specifically only the portion of the table that translates MOTOROLA M68040 USER S MANUAL 37 the logical addresses of the currently executing process Portions of translation tables can be dynamically allocated as the process requires additional memory ROOT POINTER FIRST ROOT LEVEL TABLES SECOND POINTER LEVEL TABLES THIRD PAGE LEVEL TABLES Figure 3 7 Translation Table Structure The current privilege mode determines the use of the URP or SRP for translation of the access The root pointer contains the base address of the translation table s root level table The translation table consists of tables of descriptors The table descriptors of the root and pointer levels can be either resident or invalid The page descriptors of the page level table can be resident indirect or invalid A page descriptor defines the physical address of a page frame in memory that corresponds to the logical address of a page An indirect descriptor which contains a pointer to the actual page descriptor can be used when two or more logical addresses access a single page descriptor The table search uses logical addresses to access the translation tables Figure 3 8 illustrates a logical address format which is segmented into four fields root index RI pointer inde
140. memory management on a demand page basis By translating logical to physical addresses using translation tables stored in memory the MMUs support virtual memory systems Each MMU stores recently used address mappings in an ATC reducing the average translation time Separate on chip instruction and data caches operate independently and are accessed in parallel with address translation The caches improve the overall performance of the system by reducing the number of bus transfers required by the processor to fetch information from memory and by increasing the bus bandwidth available for alternate bus 1 4 M68040 USER S MANUAL MOTOROLA masters in the system Both caches are organized as four way set associative with 64 sets of four lines Each line contains four long words for a storage capability of 4 Kbytes for each cache 8 Kbytes total Each cache and corresponding MMU is allocated separate internal address and data buses allowing simultaneous access to both The data cache provides write through or copyback write modes that can be configured on a page by page basis The caches are physically mapped reducing software support for multitasking operating systems and support external bus snooping to maintain cache coherency in multimaster systems The bus snoop logic provides cache coherency in multimaster applications The bus controller executes bus transfers on the external bus and prioritizes external memory requests from each cache The M
141. occurs By appropriately configuring an ACR flexible mappings can be specified For example to control access to the user address space the S field equals 0 and the ADDRESS MASK field equals FF in all four ACRs To control access to the supervisor address space 00000000 0FFFFFFF with write protection the BASE ADDRESS field 0X the ADDRESS MASK field equals 0F the W bit is set to one and the S field 1 The inclusion of independent ACRs in both the instruction ACU IACU and data ACU DACU provides an exception to the merged instruction and data address space allowing different access control for instruction and operand accesses Also since the instruction memory unit is only used for instruction prefetches different instruction and data ACRs can cause PC relative operand fetches to be translated differently from instruction prefetches Matching either of the ACRs in a corresponding ACU during an access to a memory unit completes the access with the ACU If both registers match the access uses the xACRO status bits Addresses are passed through without translation if there is no match in the ACRs and no table search occurs The MC68EC040 does not perform table searches MOTOROLA M68040 USER S MANUAL B7 B 3 3 Effect of RSTI on the ACU When the assertion of the reset input RSTI signal resets the 68 040 the E bits of the ACRs are cleared disabling address access control B 4 SPECIAL MODES OF OPERATION This pa
142. of table search and descriptor fetch operations A table search terminates successfully when a page descriptor is encountered The occurrence of an invalid descriptor or a transfer error acknowledge also terminates a table search and the M68040 takes an exception on the retry of the cycle because of these conditions The exception handler should distinguish between anticipated conditions and true error conditions The exception handler can correct an invalid descriptor that indicates a nonresident page or one that identifies a portion of the translation table yet to be allocated An access error due to a system malfunction can require the exception handler to write an error message and terminate the task MOTOROLA M68040 USER S MANUAL 3 9 CREATE ENTRY WITH R BIT CLEAR EXIT TABLE SEARCH ENTRY SELECT ROOT POINTER FC2 0 URP 1 SRP INITIALIZE ACCRUED STATUS WP 40 UPDATE 4 FALSE TYPE 4 POINTER FETCH ROOT DESCRIPTOR CHECK DESCRIPTOR TYPE INVALID RESIDENT FETCH POINTER DESCRIPTOR CHECK DESCRIPTOR TYPE i INVALID RESIDENT TYPE 4 PAGE FETCH PAGE DESCRIPTOR CHECK DESCRIPTOR TYPE RESIDENT ED INVALID INDIRECT TYPE 4 INDIRECT FETCH INDIRECT DESCRIPTOR CHECK DESCRIPTOR TYPE p ow OTHERWISE PHYSICAL ADDRESS FIELD OF DESCRIPTOR CREATE ATC ENTRY WITH R BIT SET ATC TAG 4 FC2 LA DF G ENTRY 4
143. on successive rising edges of BCLK until TA is recognized asserted The data bus then three states and the bus cycle ends When the processor recognizes TA at the clock edge and terminates the bus cycle TIP remains asserted if the processor is ready to begin another bus cycle Otherwise the processor negates TIP during the first half of the next clock The processor also three states the data bus during the first half of the next clock following termination of the write transfer 7 4 4 Line Write Transfers The processor uses line write bus cycles to access a 16 byte operand for a MOVE16 instruction and to support cache line pushes Both burst and burst inhibited transfers are supported Figures 7 16 and 7 17 illustrate a flowchart and functional timing diagram for a line write bus cycle 7 22 M68040 USER S MANUAL MOTOROLA PROCESSOR EXTERNAL DEVICE ADDRESS DEVICE SET R W TO WRITE DRIVE ADDRESS ON A31 A0 DRIVE USER PAGE ATTRIBUTES ON 1 UPAO DRIVE SIZE ON 5121 5120 LINE DRIVE TRANSFER TYPE ON TT1 TTO DRIVE TRANSFER MODIFIER ON 2 CIOUT BECOMES VALID ASSERT TS FOR ONE CLOCK ASSERT TIP gt SUPPLY DATA ACCEPT DATA 1 DRIVE DATA ON 031 00 1 DECODE ADDRESS FIRST TRANSFER ONLY 2 SAMPLETA 0000 2 LATCH DATA ON D31 D0 3 SAMPLE TBI AND TCI FOR FIRST TRANSFER 3 ASSERT UNTIL FOUR LONG WHEN FOUR LONG WORDS TRANSFERRED WOR
144. operand errors both native and not native to the MC68040 which the M68040FPSP unimplemented instruction 9 28 M68040 USER S MANUAL MOTOROLA exception handler can report When an operand error occurs the OPERR is set in the FPSR EXC byte Table 9 11 Possible Operand Errors Exceptions instruction Condition Causing Operand Error Native to MC68040 FADD FDIV FMOVE to B W or L FMUL FSQRT FSUB inf inf or inf inf inf inf or inf inf Nonnative to MC68040 FACOS FASIN FATANH FCOS FGETEXP FGETMAN FLOG10 FLOG2 FLOGN FLOGNP 1 FMOD FMOVE to P FREM FSCALE FSGLDIV FSGLMUL FSIN FSINCOS FTAN Source is inf gt 1 or 1 Source is inf gt 1 or 1 9 7 3 1 MASKABLE EXCEPTION CONDITIONS conditions apply as listed in Table 9 11 with the exception of the FMOVE to byte word or long word case a If the user OPERR exception handler is disabled an extended precision nonsignaling NAN with all mantissa bits set is stored in the destination floating point data register No exceptions are reported and instruction execution proceeds normally MOTOROLA M68040 USER S MANUAL 9 29 b If the user OPERR exception handler is enabled and the destination floating point data register is not modified an OPERR exception is posted The next floating point instruction that is encountered takes a pre instruction exception The OPERR entry in the processor s vector table p
145. restarted since it has not caused bus cycles that could retouch peripherals c Acache push physical bus error is normally considered a fatal error For these cases the FA field is a physical address not a logical address as in the other cases d Indicates that the data should not be written even though the V bit for it is set WB2 corresponds to a MOVE16 write e The exception handler must alter the stacked PC to point past the MOVE16 and predecrement and postincrement address registers f 1V must be 0 for push exceptions g The execution stage does not post write until the MOVE16 is in the integer unit MOTOROLA M68040 USER S MANUAL 8 31 8 32 M68040 USER S MANUAL MOTOROLA SECTION 9 FLOATING POINT UNIT MC68040 ONLY NOTE This section does not apply to the 68040 MC68L C040 68 040 68 040 Refer to Appendix A MC68LC040 and Appendix MC68EC040 for details Floating point math refers to numeric calculations with a variable decimal point location It is distinguished from integer math which deals only with whole numbers and fixed decimal point locations Historically general purpose microprocessors have had to depend on add on coprocessors and accelerators such as the MC68881 MC68882 for fast floating point capabilities The MC68040 features a built in floating point unit FPU Consolidating this important function on chip speeds up the overall processing and eliminates some interfacing overhea
146. result is the value closest to and no greater than the infinitely precise intermediate result possibly minus infinity The result is the value closest to and no less than the infinitely precise intermediate result possibly plus infinity The INEX1 and INEX2 exceptions are always maskable Therefore any INEX exception goes directly to the user INEX exception handler The M68040FPSP does not provide any special handling for the INEX exception When an INEX2 or INEX1 bit in the FPSR EXC byte is set the processor stores the rounded result listed in Table 9 15 to the destination The FPCR MODE byte determines the rounding mode and the PREC byte determines the rounding precision if the destination is a floating point data register Otherwise if the destination is memory or an integer data register the destination format determines the rounding precision If one of the instructions has a forced precision the instruction determines the rounding precision If the INEX2 or INEX1 condition exists and if the corresponding INEX bit in the FPCR ENABLE byte is set then the user INEX exception handler is taken a If the user INEX exception handler is disabled result is rounded and normal processing continues b If the user INEX exception handler is enabled the exception is taken The INEX entry in the processor s vector table points to the user INEX exception handler The user INEX exception handler must execute an FSAVE as its first floating
147. shifts one of six instructions which can either select the test to be performed or access a test data register or both Data is transferred from the instruction shift register to latched decoded outputs during the update IR state The instruction shift register is reset to all ones in the TAP controller test logic reset state which is equivalent to selecting the BYPASS instruction During the capture IR state the binary value 001 is loaded into the parallel inputs of the instruction shift register The 68040 and MC68EC040V IEEE standard 1149 1A implementations include three mandatory standard public instructions BYPASS SAMPLE PRELOAD and EXTEST two optional public standard instructions and one manufacturer s private instruction The five public instructions provide the capability to disable all device output drivers operate the device in a BYPASS configuration and conduct boundary scan test operations Table C 3 lists the three bits used in the instruction shift register to decode the instructions and MOTOROLA M68040 USER S MANUAL C 11 their related encodings Note that the least significant bit of the instruction bit 0 is the first bit to be shifted into the instruction shift register Table C 3 IEEE Standard 1149 1A Instructions ma Data Register Accessed Le p o Boundary Sean
148. some portions of the processor before execution Times listed are typical This instruction interlocks the ea calculate and execute stages and synchronizes some portions of the processor before execution This instruction interlocks the ea calculate and execute stages Successive in line MOVE16 instructions each add eight clocks to the ea calculate and execute times Typical measurement for three level table search with no descriptor writes no entries cached and four clock memory access times This instruction interlocks the ea calculate and execute stages For the exception taken this instruction also synchronizes some portions of the processor before execution times listed are minimum in this case M68040 USER S MANUAL MOTOROLA 10 6 INTEGER UNIT INSTRUCTION TIMINGS SUB TST ORI SUBI Mode Calculate Calculate Calculate NEN EN An Any d 16 d 16 xxx W xxx L lt XXX gt dg An Xn dg PC Xn MOTOROLA M68040 USER S MANUAL 10 13 10 6 INTEGER UNIT INSTRUCTION TIMINGS Continued asma Addressing lt gt lt gt lt gt METER a 91 31 51 TUS e s Immediate count specified for shift count shift count specified in register respectively 10 14 M68040 USER S MANUAL MOTOROLA 10 6 INTEGER UNIT INSTRUCTION TIMINGS Continued Addressing Mode BCHG BCLR BSET BFCHG BFCLR
149. space The following processing steps occur for an unimplemented floating point instruction 1 When an unimplemented floating point instruction is encountered the instruction is partially decoded and the effective address is calculated if required 2 The processor waits for all previous integer instructions write backs and associated exception processing to complete before beginning exception processing for the unimplemented floating point instruction Any access error that occurs in completing the write backs causes an access error exception and the resulting stack frame indicates a pending unimplemented floating point instruction exception The access error exception handler then completes the write backs in software and exception processing for the unimplemented floating point instruction exception begins immediately after return from the access error handler 3 The processor begins exception processing for the unimplemented floating point instruction by making an internal copy of the current SR The processor then enters the supervisor mode and clears the trace bits T1 and TO It creates a format 4 stack frame and saves the internal copy of the SR PC vector offset calculated effective address and PC value of the faulted instruction in the stack frame The effective address field of the format 4 stack frame contains the calculated effective address of the operand for the faulted floating point instruction using the addressing m
150. sss 13 0 e sow sow oo sso o wow sow soc e00 440 MC68L C040 and MC68EC040 o sw mo sow soc 5800 o sow wow sec aro o moo sow sec Sre 276 MOTOROLA M68040 USER S MANUAL 11 21 11 9 4 With Heat Sink and Forced Air In the specification provided by Thermalloy Inc a chart illustrates the air velocity versus thermal resistance This chart applies if airflow is used with the heat sink Table 11 6 lists the calculations based on this chart Table 11 6 Thermal Parameters with Heat Sink and Airflow Thermal Mgmt Defined Parameters Heatsink Calculated Technique Spec Airflow Velocity MC68040 200 LFM 110 3 C W 4 25 C W 7 25 C W 400 LFM 110 3 C W 2 30 C W 5 25 C W 600 LFM 110 3 C W 1 50 C W 4 50 C W 800 LFM 3 110 C 3 C W 1 25 C W 4 25 C W MC68LC040 and MC68EC040 11 22 M68040 USER S MANUAL MOTOROLA SECTION 12 ORDERING INFORMATION AND MECHANICAL DATA This section contains the ordering information pin assignments and package dimensions of the MC68040 MC68040V MC68LC040 MC68EC040 and MC68bECO040V The assignments depicted in this section for the MC68LCO040 also serve as the pin assignments for the MC68040V with a few differences as indicated 12 1 ORDERING INFORMATION The following tabl
151. stage is set to a logic zero on the rising edge of TCK following entry into the capture DR state Therefore the first bit to be shifted out after selecting the bypass register is always a logic zero Figure C 5 illustrates the bypass register SHIFT DR 0 FROM TDI TO TDO CLOCK DR Figure C 5 Bypass Register C 6 2 Boundary Scan Register The 188 bit boundary scan register uses the TAP controller to scan user defined values into the output buffers capture values presented to input pins and control the direction of bidirectional pins The instruction shift register cell nearest TDO i e first to be shifted out is defined as bit zero The last bit to be shifted out is bit 187 This register includes cells for all device signal pins and clock pins along with associated control signals The MC68040V MC68bECO040V boundary scan register consists of three cell structure types O Latch and IO Ctl that are associated with a boundary scan register bit All boundary scan output cells capture the logic level of the device output latch during the capture DR state Figures C 6 through C 9 illustrate these three cell types Figure 6 6 illustrates the general arrangement of these cells MOTOROLA M68040 USER S MANUAL C 13 1 AND CLAMP 0 OTHERWISE SHIFT DR TO NEXT CELL DATA FROM SYSTEM LOGIC TO OUTPUT BUFFER 1D FROM CLOCK DR UPDATE BSR LAST CELL Figure C 6 Out
152. standard requires to be defined and additional information specific to the MC68040V and MC68EC040V implementations For example the IEEE standard 1149 1A test access port TAP controller states are referenced in this section but are not described For these details and application information regarding the standard refer to the IEEE standard 1149 1A document The MC68040V MC68bECO040V implementations support circuit board test strategies based on the standard The test logic utilizes static logic design and is system logic independent of the device The MC68040V and MC68ECO040V implementations provide capabilities to a Perform boundary scan operations to test circuit board electrical continuity b Bypass the MC68040V and MC68ECO040V by reducing the shift register path to a single cell c Sample MC68040V and MC68bECO040V system pins during operation and transparently shift out the result d Disable the output drive to output only pins during circuit board testing NOTE The IEEE standard 1149 test logic cannot be considered completely benign to those planning not to use this capability Certain precautions must be observed to ensure that this logic does not interfere with system operation Refer to C 6 4 Disabling The IEEE Standard 1149 1A Operation Figure C 4 illustrates a block diagram of the MC68040V and MC68bECO040V implementations of IEEE standard 1149 14 The test logic includes a 16 state dedicated TAP contr
153. tan el 12 2 12 2 2 MC68LC040 Pin Grid Array anotar eec eee 12 3 12 2 3 MC68EC040 Pin Grid Array 12 4 12 2 4 MC68040V and MC68ECO40V Pin Grid Array 12 5 12 2 5 MC68LC040 Quad Flat 12 6 12 2 6 MC68ECO040 Quad Flat 12 6 12 2 7 MC68040V and 6 40 Quad Flat 12 7 12 3 Mechanical Date screen deitate diei 12 9 Appendix A MC68LC040 MC68LC040 Differences A 5 A 2 Interrupt Priority Level IPL2 IPLO A 5 A 3 JTAG SCAM SO satia eR e dpt Paco Ue RR UNE A 5 4 Data Latch And Multiplexed Bus 5 5 Floating Point Unit iuit tog erret 5 5 1 Unimplemented Floating Point Instructions and Exceptions A 6 A 5 2 MC68LC040 Stack Frames A 7 A 6 MC68LC040 Electrical Characteristics A 7 A 6 1 ters aues tede W ana en nana eons A 8 A 6 2 Thermal Characteristics danti t puedes A 8 A 6 3 DC Electrical Specifications oir PR proe DE A 8 A 6 4 Power Dissipation c isi deser eon eure nt d RE A 9 A 6 5 Clock AC Timing Specifications
154. the external signal driving RSTI to derive a system reset signal that is asserted for both an external processor reset and execution of a RESET instruction MOTOROLA M68040 USER S MANUAL 7 67 7 11 SPECIAL MODES OF OPERATION The MC68LC040 and MC68EC040 do not support the following three modes of operation which for the M68040 are selectively enabled during processor reset and remain in effect until the next processor reset Refer to Appendix MC68LC040 and Appendix B 68 040 for differences in the special modes of operation for the MC68LC040 and 68 040 7 11 1 Output Buffer Impedance Selection All output drivers in the M68040 can be configured to operate in either a large buffer mode low impedance driver or small buffer mode high impedance driver Large buffers have a nominal output impedance of 6 Q for both high and low drive resulting in minimum output delays Signal traces driven by large buffers usually require transmission line effects to be considered in their design including the use of signal termination Small buffers have a nominal impedance of 25 Q for high and low drive resulting in longer output delays and less critical board design requirements Refer to Section 11 MC68040 Electrical and Thermal Characteristics for further information on electrical specifications buffer characteristics and transmission line design examples The output drivers are configured in three groups Each group of signals i
155. the illusion that it never existed The user SNAN exception handler must execute an FSAVE as the first floating point instruction Table 9 16 lists the floating point state frame fields for SNAN pre instruction exceptions resulting from the execution of opclass 010 or 000 register to register or memory to register instructions and for SNAN post instruction exceptions resulting from the execution of opclass 011 register to memory instructions defined for the use by the supervisor exception handler A source or destination SNAN is stored in ETEMP or FPTEMP respectively with its SNAN bit set The user SNAN exception handler can overwrite the result to the specified destination The exception handler must be aware that it is possible for an INEX1 exceptional condition to co exist with an SNAN exception Since the SNAN exception has higher priority the INEX1 exception is hidden and it becomes the responsibility of the SNAN exception handler to detect and correct this if desired To return to normal execution the state frame is discarded prior to execution of the RTE of the user defined exception handler 9 7 3 Operand Error The operand error exception encompasses problems arising in a variety of operations including those errors not frequent or important enough to merit a specific exceptional condition Basically an operand error occurs when an operation has no mathematical interpretation for the given operands Table 9 11 lists the possible
156. the instruction completes execution allowing a debugging program to monitor execution of a program In general terms a trace exception is an extension to the function of any traced instruction The execution of a traced instruction is not complete until trace exception processing is complete If an instruction does not complete due to an access fault or address error exception trace exception processing is deferred until after execution of the suspended instruction is resumed If an interrupt is pending at the completion of an instruction trace exception processing occurs before interrupt exception processing starts If an instruction forces an exception as part of its normal execution the forced exception processing occurs before the trace exception is processed The T1 and TO bits in the supervisor portion of the SR control tracing The state of these bits when an instruction begins execution determines whether the instruction generates a trace exception after the instruction completes T1 and TO bit 1 causes an instruction that forces a change of flow to take a trace exception The following instructions cause a trace exception to be taken when trace on change of flow is enabled ANDI to SR CAS2 FBcc Taken JMP MOVES RTD Bcc Taken CINV FDBcc Always JSR NOP RTE BRA CPUSH FMOVEM MOVE to SR ORI to SR RTR BSR DBcc Taken FRESTORE MOVE USP PFLUSH RTS CAS EORI to SR FSAVE PTEST STOP Instructions that increment the PC normally
157. the push buffer an alternate bus master can snoop it but the execution units cannot access it After the bus transfer for the new line successfully completes the dirty cache line is copied back to memory and the push buffer is invalidated If the operation to access the replacement line is abnormally terminated or signaled as cache inhibited the line in the push buffer is copied back into its original position in the cache and the processor continues operation as described in the previous paragraphs The number of dirty long words in the line to be pushed determines the size of the push transfer on the bus minimizing bus bandwidth required for the push A single long word is written to memory using a long word push transfer if it is dirty A push transfer is distinguished from a normal write transfer by an encoding of 000 on the transfer modifier signals TM2 TMO for the push Asserting TA and TEA retries the transfer a bus error asserted TEA terminates it If a bus error terminates a push transfer the processor immediately takes an exception A line containing two or more dirty long words is copied back to memory using a line push transfer For a line push the bus controller requests a burst write transfer by indicating a line access with SIZ1 and SIZO The responding device sequentially accepts four long words of data If the responding device does not support the burst mode it should assert TBI for the first long word of the line acces
158. to ETEMP The destination operand in this case remains in the destination floating point register and can be either denormalized or unnormalized Figure 9 9 illustrates denormalized single a and double precision b operands stored in ETEMP field The exception handler uses the floating point state frame information to determine which operand or operands is the unsupported data type and which instruction attempted to use the offending operand The exception handler must provide the routines needed to complete the instruction and to store that instruction to the proper destination whether it be in a floating point data register integer data register or external memory Once the destination is written the floating point state frame is discarded and normal execution is resumed by using the RTE instruction This approach does not report floating point arithmetic exceptions that may have been generated Motorola recommends that the user utilize the M68040FPSP if a full exception reporting model is required Motorola does not provide any printed documentation other than what is embedded in the source code of the M68040FPSP MOTOROLA M68040 USER S MANUAL 9 23 31 30 2322 0 DENORMALIZED SINGLE PRECISION S _ 50 FRACTION 95 94 80 79 64 63 62 4039 0 FORMAT IN STATE FRAME 0 0 0 0 S MANTISSA a Single Precision 63 62 52 51 0 DENORMALIZED D
159. to normal processing b If the user OVFL exception handler is enabled the M68040FPSP OVFL restores the FPU to its exceptional state cleans up the stack to the conditions prior to execution and continues instruction execution at the user OVFL exception handler No parameters are passed to the user OVFL exception handler since the M68040FPSP OVFL exception handler provides the illusion that it never existed The user OVFL exception handler must execute an FSAVE as its first floating point instruction The destination contains the rounding mode values listed in Table 9 12 and the user OVFL exception handler can choose to modify these values The and E1 bits of the floating point state frame are examined to determine which fields on the floating point state frame are valid E3 always takes precedence and must be serviced first Table 9 16 lists the floating point state frame fields for OVFL exceptions with set or with clear and E1 set Note that it is possible for an FADD FSUB FMUL and FDIV to report a post instruction exception although these instructions normally generate a pre instruction exception The following example illustrates the reason why a post instruction exception is generated FADD FP2 FPO this instruction generates an overflow exception FMOVE FPO ea this instruction is executing when overflow occurs In this example assume that the FMOVE instruction starts once the FADD instruction generates an overflo
160. trace exception vector offset PC value and the internal copy of the SR on the supervisor stack The saved value of the PC is the logical address of the next instruction to be executed Instruction execution resumes after the required prefetches from the address in the trace exception vector When the STOP instruction is traced the processor never enters the stopped condition A STOP instruction that begins execution with the trace bits equal to 3 forces a trace exception after it loads the SR Upon return from the trace exception handler execution continues with the instruction following the STOP instruction and the processor never enters the stopped condition 8 2 7 Format Error Exception Just as the processor checks for valid prefetched instructions it also performs some checks of data values for control operations The RTE instruction checks the validity of the stack format code For floating point unit FPU state frames the FRESTORE instruction compares the internal version number of the processor to that contained in the state frame refer to Section 9 Floating Point Unit MC68040 Only This check ensures that the processor can correctly interpret internal FPU state information from the state frame If any of these checks determine that the format of the data is improper the instruction generates a format error exception This exception saves a stack frame generates exception vector number 14 and continues execution at the address i
161. word respectively of the field Write back data in WB1D is memory aligned and resides in the byte positions corresponding to the data bus lanes used in writing each byte to memory Table 8 5 lists the data alignment for each combination of data format and A1 and AO MU 8 5 Write Back Data Alignment Address Data Data Format WB2D WB3D Long Word NOTE For a line transfer fault the four long words of data in PD3 PDO are already aligned with memory Bits 31 0 of each field correspond to bits 31 0 of the memory location to be written to regardless of the value of the address bits A1 and 0 for the write back address 8 4 6 6 PUSH DATA The push data field contains an image of the cache line that needs to be pushed to memory 8 4 6 7 ACCESS ERROR STACK FRAME RETURN FROM EXCEPTION For the access error stack frame format 7 the processor restores the SR and PC values from the stack and checks the four continuation status bits in the SSW on the stack If these bits are not set the processor increments the active supervisor stack pointer by 30 words and resumes normal instruction execution If the MOVEM continuation bit is set the processor restores the calculated effective address from the stack frame increments the active supervisor stack pointer by 30 words and restarts the MOVEM instruction at a point after the effective address calculation All operand accesses for the MOVEM that occurred before the fau
162. word operations The M bit of the SR selects whether the ISP or MSP is active SSP references access the ISP when the M bit is clear putting the processor into the interrupt mode If an exception being processed is an interrupt and the M bit is set the M bit is cleared putting the processor into the interrupt mode The interrupt mode is the default condition after reset and all SSP references access the ISP The ISP can be used for interrupt control information and for workspace area as interrupt exception handling requires SSP references access the MSP when the M bit is set The operating system uses the MSP for each task pointing to a task related area of supervisor data space This 2 6 M68040 USER S MANUAL MOTOROLA procedure separates task related supervisor activity from asynchronous l O related supervisor tasks that can only be coincidental to the currently executing task The MSP can separately maintain task control information for each currently executing user task and the software updates the MSP when a task switch is performed providing an efficient means for transferring task related stack items The value of the M bit does not affect execution of privileged instructions Instructions that affect the M bit are MOVE to SR ANDI to SR EORI to SR ORI to SR and RTE The processor automatically saves the M bit value and clears it in the SR as part of the exception processing for interrupts 2 2 2 2 STATUS REGISTER The SR see Fig
163. x 120 30 1 mW Similar calculations for unterminated small buffers yield 5 mA by spec and 5 mA x 25Q 50 Phsb 0 625 mW 0 625 mW Assuming that the duty cycle of output j is driving a valid logic value instead of being three stated as given by then the following equation approximates total average power dissipation in the output buffers Number of Outputs Used DCj2 x j 1 lj 24 are calculated for every pin as illustrated above In practice the above summation is carried out by groups of pins instead of individual pins Motorola has calculated the values for DC for typical situations On an average clock there will be 37 8 pins high 41 5 pins low and 11 7 pins three stated The following examples demonstrate how to calculate the power dissipation that is added to small buffer power dissipation numbers assuming a termination as illustrated in Figure 11 18 a For the numbers listed in this section in a large buffer design with no caching P Number of Pins High x P nib Number of Pins Low x Pip 37 8 Pins x 30 1 mW per Pin 41 5 Pins x 14 8 mW per Pin 1 75 W b For a single bus master system in a large buffer design with no caching or snooping and only standard features i e TLN UPA BR BB LOCK LOCKE CIOUT MI TDO IPEND PST not used P Number of Pins High x Phib Number of Pins Low x Pip 29 8 Pins x 30 1 mW per Pin
164. 0 Match only if FC2 0 user mode access 01 Match only if FC2 1 supervisor mode access 1X Ignore FC2 when matching UO U1 User Page Attributes The user defines these bits and the M68040 does not interpret them UO and U1 are echoed to the UPAO and 1 signals respectively if an external bus transfer results from an access These bits can be programmed by the user to support external addressing bus snooping or other applications MOTOROLA M68040 USER S MANUAL 35 CM Cache Mode This field selects the cache mode and access serialization as follows 00 Cachable Write through 01 Cachable Copyback 10 Noncachable Serialized 11 Noncachable Section 4 Instruction and Data provides detailed information on caching modes and Section 7 Bus Operation provides information on serialization W Write Protect This bit indicates if the transparent block is write protected If set write and read modify write accesses are aborted as if the resident bit in a table descriptor were clear 0 Read and write accesses permitted 1 Write accesses not permitted 3 1 4 MMU Status Register The MMUSR is a 32 bit register that contains the status information returned by execution of the PTEST instruction The PTEST instruction searches the translation tables to determine status information about the translation of a specified logical address Transfers to and from the MMUSR are long word transfers The fields
165. 0 USER S MANUAL 3 21 Table 3 1 Updating U Bit and M Bit for Page Descriptors Previous Status Access Type n Write LE NOTE WP indicates the accumulated write protect status o o o ofn o o o o MERE 1 _ An alternate address space access is special case that is immediately used as a physical address without translation Because the M68040 implements a merged instruction and data space the integer unit translates MOVES accesses to instruction address spaces SFC DFC 6 or 2 into data references SFC DFC 5 or 1 The data memory unit handles these translated accesses as normal data accesses If the access fails due to an fault or a physical bus error the resulting access error stack frame contains the converted function code in the TM field for the faulted access Invalidation of the instruction cache line containing the referenced location to maintain cache coherency must precede MOVES accesses that write the instruction address space The SFC and DFC values and results are listed in Table 3 2 Table 3 2 SFC and DFC Values SFC DFC Vale 00 3 22 M68040 USER S MANUAL MOTOROLA 3 2 6 Address Translation Protection The M68040 MMUS provide separate translation tables for supervisor and user address spaces The translation tables contain both mapping and protection information Each table and page descriptor incl
166. 0 is the default bus master therefore if there are no pending requests from either device the external bus arbiter gives the bus to the M68040 ABR gt R CLK gt CLK Figure 7 38 Sample Synchronizer Circuit MOTOROLA M68040 USER S MANUAL 7 57 REARVAAK AAV R ARV RARVALOCK A V RV V RA LOCKE V LOCK 040 BG AM BG 62 55 pred LOCK A LOCKE _ NAVVAAAV ____ s R V RV V 040_BG 040_BG 040_BG R AR AM_BG AM_BG AM_BG RARVAAKA AV V AV V RV R ARV A AV S6 RV V RA V RARVAAAAV a MC68040 Low Priorty Default Bus Master R A RV A AF A AV VR ARV A 040 BR R ARVAAAAV V RV V RA R ARV A 040 BR 040 BR R ARV A 040 BR S5 52 R A RV A A A AV 040 BR R V RV V 040 BR 00 BG AM 8G 040 BG 040 86 R ARV AA AAV V RARVAA AAV S6 RV V RA V RARVAAAAV NOTES E s 1 It is assumed that the asynchronous device takes the bus only after or the MC68040 s BB is negated 2 Indicates the signal is asserted for that device b MC68040 High Priorty Default Bus Master Figure 7 39 M68040 Asynchronous DMA Arbitration 7 58 M68040 USER S MANUAL MOTOROLA 7 9 BUS SNOOPING OPERATION When required the M68040 can monitor alte
167. 040 USER S MANUAL MOTOROLA Table 1 4 Instruction Set Summary Continued NOT Destination e Destination NOT ea Source V Destination Destination OR ea Dn OR Dn ea Immediate Data V Destination 2 Destination ORI lt data gt lt ea gt ORI to CCR Source V CCR e CCR ORI lt data gt CCR ORI to SR If supervisor state ORI lt data gt SR then Source V SR e SR else TRAP PACK Source Unpacked BCD adjustment 2 PACK Ax Ay st adjustment Destination Packed BCD PACK Dx Dy adjustment PFLUSH8 If supervisor state PFLUSH An then invalidate instruction and data ATC entries PFLUSHN An for destination address PFLUSHA else TRAP PFLUSHAN PTEST8 If supervisor state PTESTR An then logical address status MMUSR PTESTW An entry 2 ATC else TRAP RESET If supervisor state RESET then Assert RSTO Line else TRAP ROL ROR Destination Rotated by count Destination ROd Rx Dy ROd lt data gt Dy ROXL ROXR Destination Rotated with X by count e Destination ROXd Dx Dy ROXd lt data gt Dy ROXd ea RT If supervisor state RTE then SP 2 SR SP 2 SP SP aPC SP 4 e SP restore state and deallocate stack according to SP else TRAP D E R SP CCR SP 2 SP R SP SP 4 SP H SP B Ax SBCD Destination10 Source 10 X Destination SBCD Dx Dy SBCD Ax Ay S Scc If condition true CC ea then 1s e Destination else 05 e Destination
168. 1 output2 X 65 2 PST 0 output2 X amp 66 2 TA output3 X 154 0 2 154 io 2 167 4 input X amp 168 4 TEA amp 69 _4 input X amp 170 4 SC 1 input X amp 6 20 M68040 USER S MANUAL MOTOROLA num cell port function safe dsval 171 4 SC 0 input X 172 4 TBI input X 173 4 AVEC input X 174 4 TCI input X 175 4 DLE input X 76 4 input X 177 4 input X 178 4 IPL O input 179 4 input 180 4 2 input 181 4 RSTI input X 182 4 CDIS input X 183 4 MDIS input x S attribute DESIGN WARNING of MC68040 entity is A non standard clocking protocol on BCLK and PCLK must be observed when entering Boundary Scan Test Mode 68040 6 7 MC68040 MC68LC040 MC68EC040 JTAG ELECTRICAL CHARACTERISTICS The following paragraphs provide information on JTAG electrical and timing specifications This section is subject to change For the most recent specifications contact a Motorola sales office or complete the registration card at the beginning of this manual JTAG DC Electrical Specifications Capacitance is periodically sampled rather than 10095 tested
169. 13 Vec SCD GND Vcc 1 L ALE GND GND MC68040V and MC68ECO40V PINOUT vcc GND A0 K BOTTOM VIEW 15 16 GND LOC 18 X 18 CAVITY DOWN GND TM2 1 J 17 A19 Vcc A2 A18 GND Vcc Vcc GND 4 G O C O 20 23 Vcc 5 F 21 GND A25 A9 GND 7 E O A22 26 A28 029 030 A8 D 60 A24 GND LFO 027 GND D3l C O 27 Wc DO D GND GND GND GND GND vec 023 025 Vcc 028 o 29 GND 01 GND GND D8 GND vec GND D16 D18 GND Wee GND D22 GND D26 A A31 D3 D4 D5 D6 D7 9 010 Di 012 013 014 015 D17 D19 D20 D21 D24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 NOTES 6 4 this pin is called JS1 All these pins in the JTAG scan chain On an MC68040 design JS2 GND on an MC68060 design JS2 CLK Internal Logic Output Drivers MOTOROLA S amp R amp RIO R6 R10 R8 Rs C6 C7 C9 C11 C13 16 L8 M16 R4 C5 C8 C10 C12 C14 H16 J3 J16 116 R11 R13 10 T4 M3 R5 R12 B2 B4 B6 B8 B10 B13 B15 B17 D2 D17 B5 B9 B14 C2 C17 G2 G17 M2 M17 R2 F2 F17 H2 H17 L2 L17 N2 N17 Q2 Q17 R17 S16 52 515 517 M68040 USER S MANUAL 12 5 12 2 5 MC68L C040 Quad F
170. 2 Low Power Stop Mode Instruction Format 16 CHO B R H 1 9 8 po 6 5 4 3 2 1 0 Rae r per pepe poc IMMEDIATE DATA Instruction Fields Immediate field Specifies the data to be loaded into the status register C 6 M68040 USER S MANUAL MOTOROLA CLOCKING DURING NORMAL OPERATION During normal operation of the processor the BCLK should be driven with a 5096 590 duty cycle refer to 7 MC68040V and MC68ECO40V Electrical Characteristics for details The frequency of BCLK can not be changed during normal operation Altering the BCLK frequency during normal operation the LFO signal is negated will result in unspecified operation In the event that the BCLK input is lost a processor reset is required Once the loss of BCLK is detected during normal operation the processor asserts LOC indicating a loss of clock External logic can then reset the processor to resume normal operation C 4 RESET OPERATION An external device asserts the RSTI to reset the processor When power is applied to the system external circuitry should assert RSTI for a minimum of 10 BCLK cycles after Vcc is within tolerance Figure C 2 is a functional timing diagram of the power on reset operation illustrating the relationships among Vcc RSTI and bus signals The BCLK signal is required to be stable by the time RSTI is negated The levels of any pin must not excee
171. 3 4 3 32 4 3 4 5 5 9 5 11 7 66 9 3 9 4 9 6 9 39 11 29 11 30 Retry Operation 4 12 7 41 7 42 7 55 Root Index Field RI 3 8 M68040 USER S MANUAL INDEX 5 Rounding Algorithm 9 14 Rounding Mode 9 3 9 13 9 16 9 24 9 37 Overflow And Underflow 9 16 9 30 Rounding Precision 9 3 9 13 9 33 9 37 9 16 Forced 9 31 9 34 c SAMPLE PRELOAD 6 3 Self Modifying Code 4 10 Shadow Registers 2 1 SHUTDOWN 6 3 6 12 Signals 1 0 7 1 AVEC 7 33 7 34 BB 7 45 7 58 BCLK 6 12 7 1 BG 7 45 7 58 BR 7 45 7 58 CDIS 4 5 5 4 5 5 7 67 7 69 CIOUT 4 7 031 00 7 1 DLE 1 1 1 2 5 5 A 5 B 5 IPEND 5 12 7 29 IPLx 7 2 7 29 7 34 7 67 5 11 6 5 8 12 10 8 A 5 B 8 JSO 1 1 1 2 A 5 5 B 8 JS1 1 2 B 5 B 8 LOCK 3 21 4 13 7 26 7 45 7 58 LOCKE 7 26 7 45 7 58 7 54 MDIS 1 2 3 1 3 5 3 32 5 5 7 67 B 5 B 8 MI 7 60 PCLK 6 12 7 1 PSTx 8 18 Relationship to System CLOCKS 7 2 RSTI 3 32 6 5 6 6 6 13 7 2 7 66 7 67 8 17 B 8 RSTO 8 18 SCx 4 3 7 60 Encodings 4 9 SIZx 4 13 7 3 7 7 Encodings 4 11 4 11 4 12 4 13 8 9 8 12 7 60 8 9 8 12 9 20 4 3 4 11 4 12 4 13 7 10 7 20 7 60 4 11 4 12 6 2 6 4 6 6 6 12 TDI 6 2 6 2 6 4 6 6 INDEX 6 M68040 USER S MANUAL TEA 4 12 4 13 7 60 8 6 8 7 8 9 8 12 9 20 TLNx Encodings 4 14 TMS 6 2 6 4 4 13 5 6 TRST 6 2 6 4 6 13 TS 7 60 3 5 3 15 3 28 7 60
172. 4 Input Pin Cell I Pin MOTOROLA M68040 USER S MANUAL 6 7 1 0 OTHERWISE SHIFT DR TO NEXT CELL OUTPUT CONTROL TO OUTPUT FROM SYSTEM LOGIC gt BUFFER 1 DRIVE FROM CLOCK DR RESET LAST CELL UPDATE DR Figure 6 5 Output Control Cells TO NEXT CELL A OUTPUT INPUT E h DATA Y FROM TO NEXT LAST CELL PIN PAIR Figure 6 6 General Arrangement of Bidirectional Pins 6 8 M68040 USER S MANUAL MOTOROLA All M68040 bidirectional pins include two boundary scan data cells an input and output One of five associated boundary scan control cells controls each bidirectional pin If these cells contain a logic one the associated bidirectional or three state pin will be configured as an output and enabled The cell captures the current value during the capture DR state All five control cells are reset i e logic zero in the test logic reset state The five bidirectional three state control cells and their boundary scan register bit positions are as follows Cell Name Table 6 2 lists the 184 boundary scan bit definitions The first column in the table defines the bit position in the boundary scan register The second column references one of the three cell types The third column lists the pin name for all pin related cells The fourth column lists the system pin type for convenience where TS Output indicates a three state outp
173. 4 2 Nonmaskable Exception Conditions 9 31 Xii M68040 USER S MANUAL MOTOROLA Paragraph Number 9 7 5 9 7 5 1 9 7 5 2 9 7 6 9 7 7 9 8 10 1 10 2 10 3 10 4 10 6 10 7 10 7 1 10 7 2 10 7 3 11 1 11 2 11 3 11 4 11 5 11 6 11 7 11 8 11 8 1 11 8 2 11 9 11 9 1 11 9 2 11 9 3 11 9 4 MOTOROLA TABLE OF CONTENTS Continued Page Title Number Baez u anu 9 33 Maskable Exception Conditions 9 34 Nonmaskable Exception Conditions 9 34 Divide by 9 36 Inexact E 9 36 Floating Point State 9 39 Section 10 Instruction Timings T e 10 3 Instruction Timing Examples erui nS 10 5 CINV and GPUSH Instruction TIMING ices ceive eoo been es 10 8 MOVE Instruction Timing 10 9 Miscellaneous Integer Unit Instruction Timings 10 11 Integer Unit Instruction Timings cludes weenie cate t 10 13 Floating Point Unit Instruction Timings 10 29 Miscellaneous Integer Unit Support Timings 10 29 Integer Unit Support Timings esses 10 30 Timings in the
174. 40 MC68LC040 and MC68EC040 QFP package dimensions Due to space limitation Figure 12 2 is represented by a general smaller package outline drawing rather than showing all 184 leads lt A PIN A1 INDICATOR MOTOROLA gt O O 6 gt lt OG 6 600 OOOOOOOOOOOOOOO OOO O O GO 1 23 4 5 67 8 91011 121314 15 16 17 18 D 179 PLACES 619030 76 9 T cd 9010 25 D T DIM MILLIMETERS INCHES MIN MAX MIN MAX A 46 74 41 15 1 840 1 880 B 46 74 41 15 1 840 1 880 C 2 79 3 05 0 110 0 140 D 041 051 0 016 0 020 G 2 54 BSC 0 100 BSC K 3 81 432 0 150 0 170 Figure 12 1 PGA Package Dimensions M68040 USER S MANUAL 12 9 Figure 12 2 QFP Package Dimensions M68040 USER S MANUAL MOTOROLA APPENDIX A MC68L C040 NOTE All references to MC68LCO040 also apply to the MC68040V Refer to Appendix MC68040V and MC68ECO40V
175. 40 USP SSP MSP ISP Status Register Bits MC68000 MC68008 MC68010 T 10 11 12 X N Z V C MC68020 MC68030 MC68040 TO T1 S M 10 11 12 X N Z V C Function Code Address Space MC68000 MC68008 FC2 FCO 7 Is Interrupt Acknowledge Only MC68010 MC68020 MC68030 MC68040 2 7 Is CPU Space 68040 User Supervisor and Acknowledge Indivisible Bus Cycles MC68000 MC68008 MC68010 Use AS Signal MC68020 MC68030 Use Signal MC68040 Use LOCK and LOCKE Signal Stack Frames Addressing Modes MC68020 MC68030 and MC68040 Extensions Memory indirect addressing modes scaled index and larger displacements Refer to specific data sheets for details D 2 M68040 USER S MANUAL MOTOROLA 68020 68030 MC68040 Instruction Set Extensions Applies To MC68020 MC68030 MC68040 e J Bit Field Instructions BCHG BFCLR BFEXTS BFFFO BFINS BFSET BFTST a m TL 1 U U U U C e oeda ox smesso O wen 3 ony E um suppers S E nummer rus ace _ O O xs Supers 54 j J 7 L _ me pone mw mex
176. 5 3 8 Lock End LOCKE bar Gic 5 7 5 3 9 Cache Inhibit Out 5 8 5 4 Bus Transfer Control SIgnals u o rera 5 8 5 4 1 Transiter Start TOLL dete hum hinaha ase 5 8 viii M68040 USER S MANUAL MOTOROLA Paragraph Number 5 4 2 5 4 3 5 4 4 5 4 5 5 4 6 5 5 5 5 1 5 5 2 5 6 5 6 1 5 6 2 5 6 3 5 7 5 7 1 5 7 2 5 7 3 5 8 5 8 1 5 8 2 5 8 3 5 9 5 9 1 5 9 2 5 9 3 5 10 5 11 5 12 5 12 1 5 12 2 5 12 3 5 12 4 5 12 5 5 13 5 14 6 1 6 2 6 2 1 MOTOROLA TABLE OF CONTENTS Continued Page Title Number Transfer in Progress nue UR ENS 5 8 Transfer Acknowledge 5 8 Transfer Error Acknowledge 5 8 Transfer Cache Inhibit a 5 9 Transfer Burst Inhibit TBI 5 9 Snoop Control Signals tenait nod 5 9 Snoop Control SC T SCO 5 9 Memory Inhibit MI el Au ORIS 5 9 Arbitration Signals vce nate cc eed PRU wee 5 10 Bus Request B e hu uti ee 5 10 Bus Grant BG ea ona Deed tae de 5 10 Bus BB 5 10 Processor Control Signals 5 10 Cache Disable
177. 54 M68040 USER S MANUAL MOTOROLA BB A BR2 STATE C STATE D BB STATE B BR2 A LOCK A LOCKE V BR2 ALOCK BB A LOCK V BB 6 LOCK A LOCKE STATE A BB ALOCK A LOCKE NOTES 1 Because this example uses two MC68040s 1 or 2 refers to the processor and its signals 2 Indicates the signal is asserted for that device Figure 7 36 Dual M68040 Prioritized Arbitration State Diagram 7 8 2 3 M68040 SYNCHRONOUS DMA ARBITRATION Figure 7 37 illustrates a system with an M68040 and a synchronous direct memory access DMA that contains an M68040 interface Figure 7 37 a illustrates that the DMA owning the bus only when the M68040 has no pending requests and Figure 7 37 b illustrates the DMA having higher priority than the M68040 causing the M68040 to yield the bus to the DMA at any time except when the M68040 is performing a locked bus operation In either case the M68040 is the default bus master if there are no pending requests from either device the external arbiter gives the bus to the M68040 Similar to the M68040 fairness arbitration example the restriction on using LOCKE applies to this example MOTOROLA M68040 USER S MANUAL 7 55 5 STATE D 040 BR AM BG 040 BG AM BG 040 BG 040 BR 040 BR V AM STATE B AM BG 040 BG gt 040 BG AM 040 BG BB A 040 BR STATE A BB A 040 BR
178. 6 CB C9 cl CH CH Le Le 2 ea FETCH E Ee Le leo 12 EXECUTE WRITE BACK NOTE Possible stalls in this stage Figure 10 2 Instruction Overlap with Multiple Clocks 10 6 M68040 USER S MANUAL MOTOROLA Instructions using the brief and extension word format addressing modes cause the ea calculate and execute stages to operate in an interlocked manner When these instructions wait to begin execution in the execution stage there is a similar increase in the ea calculate time Figure 10 3 illustrates this effect for an ADD instruction using a brief format extension word The ADD instruction stalls for two clocks waiting to enter the execution stage Since this time exceeds by one clock the ADD lead time the ADD instruction remains in the ea calculate stage for one additional clock If the ADD instruction was in the execution stage for two clocks the ABCD instruction would not have stalled in the ea calculate stage ea CALCULATE ea FETCH EXECUTE WRITE BACK ea LABEL INSTRUCTION CALCULATE EXECUTE P1 TRAPF 1 1 A ABCD 0021 3 3 B ADD L 4 A0D3 D2 5 1 4 N1 TRAPF 1 1 N2 TRAPF 1 1 CL C2 C4 C5 9 C7
179. 6 17 18 Gp Internal Logic C6 C7 C9 C11 C13 K3 K16 L3 M16 R4 C5 C8 C10 C12 C14 H3 H16 J3 J16 L16 R11 R13 S6 S10 T4 M3 R5 R12 Output Drivers B2 B4 B6 B8 B10 B13 15 17 D2 D17 B5 B9 B14 C2 C17 G2 G17 M2 M17 R2 F2 F17 H2 H17 L2 L17 N2 N17 Q2 Q17 R17 S16 S2 515 517 M68040 USER S MANUAL 12 3 12 2 3 MC68EC040 Pin Grid Array T O 9 TRST GND CDIS 2 0 JSO AVEC SCO PSTO PST3 BB 5 O O CA O O O O IPEND GND TDI TCK TMS 51 RSTI Vcc GND GND TBI 5 1 TEA 5 GND Vcc GND LOCK R O O CIOUT RSTO GND Vcc GND Vcc GND GND Vcc GND PST2 TIP TS Vcc LOCKE Q 1 GND MI GND P O 10 5171 SIZO A12 GND GND 0 M 13 Vcc GND Vcc L Al4 GND GND Vcc GND A0 elles 7 68 040 PINOUT FOE S 15 16 GND BOTTOM VIEW GND TM2 Al 3 A 18 X 18 CAVITY DOWN PGA A17 A19 Vcc 2 18 GND Vec GND 4 6 20 Vec 23 A6 Vcc 5 F A21 GND A25 A9 GND 7 E O A22 A26 A28 029 D30 A8 D
180. 68040 bus controller supports a high speed nonmultiplexed synchronous external bus interface supporting burst accesses for both reads and writes to provide high data transfer rates to and from the caches Additional bus signals support bus snooping and external cache tag maintenance The MC68040 contains an on chip FPU which is user object code compatible with the MC68881 MC68882 floating point coprocessors The FPU has pipelined instruction execution Floating point instructions in the FPU execute concurrently with integer instructions in the IU 1 5 PROCESSING STATES The processor is always in one of three states normal processing exception processing or halted It is in the normal processing state when executing instructions fetching instructions and operands and storing instruction results Exception processing is the transition from program processing to system interrupt and exception handling Exception processing includes fetching the exception vector stacking operations and refilling the instruction pipe caused after an exception The processor enters exception processing when an exceptional internal condition arises such as tracing an instruction an instruction results in a trap or executing specific instructions External conditions such as interrupts and access errors also cause exceptions Exception processing ends when the first instruction of the exception handler begins to execute The processor halts when it receiv
181. 7 only if the bus transfer is marked as snoopable the bus The protocols described in the following paragraphs assume that the data is cachable i e write through and copyback 4 4 1 Read Miss A processor read that misses in the cache causes the cache controller to request a bus transaction that reads the needed line from memory and supplies the required data to the IU The line is placed in the cache in the valid state Snooped external reads that miss in the cache have no affect on the cache 4 4 2 Write Miss The cache controller handles processor writes that miss in the cache differently for write through and copyback pages Write misses to copyback pages cause the processor to perform a bus transaction that writes the needed cache line into its cache from memory in the same manner as for a read miss The new cache line is then updated with the write data and the D bits are set for each long word that has been modified leaving the cache line in the dirty state Write misses to write through pages write directly to memory without loading the corresponding cache line in the cache Snooped external writes that miss in the cache have no affect on the cache 4 4 3 Read Hit The cache controller handles processor reads that hit in the cache differently for write through and copyback pages No bus transaction is performed and the state of the cache line does not change Physical address bit 3 selects either the upper or lower half lin
182. 7 Status Bits 3 34 Supervisor Root Pointer SRP 1 8 3 3 Translation Control Register TCR 1 8 3 4 Field Definitions 3 4 E Bit 3 33 P Bit 3 32 8 17 Transparent Translation Registers TTR 1 4 1 7 3 2 3 3 3 29 3 30 4 6 5 7 8 17 Field Definitions 3 5 User Root Pointer URP 1 8 3 3 Misaligned Access 4 3 4 11 10 3 Misaligned Operand 7 6 7 37 Multiplexed Bus Mode 1 2 5 4 5 5 7 69 A 5 Multiplexer 7 3 MOTOROLA see Data Types Normalized see Data Types Lyc Operand Size 1 9 Output Buffer Mode 1 2 7 69 11 29 Packed Decimal Real 9 22 Page Descriptor see Descriptors Page Index Field PGI 3 8 Page Size 3 4 3 12 8 17 4 Kbytes 3 9 3 29 B 4 8 Kbytes 3 6 3 9 3 29 Paged Memory 3 1 3 21 Page Offset Field 3 8 Page State Information 4 10 PDT Field 3 17 see also Descriptors Physical Address 3 2 3 8 3 9 3 29 4 3 Translation of see Address Translation Pointer Index Field 3 8 Power Dissipation 11 29 PRIVATE 6 3 Privilege Modes 1 5 User 1 6 2 7 Supervisor 1 6 2 7 3 3 4 5 Processing States 1 5 1 6 Push Bus Cycles see Bus Cycles R Range Control 9 13 Read Modify Write Bus Cycles see Bus Cycles Registers Floating Point Unit see Floating Point Unit Registers Integer Unit see Integer Unit Registers JTAG see JTAG Registers Memory Management Unit see Memory Management Unit Registers Replacement Algorithm 4 4 Reset Operation 2 8
183. A0 IN SIZx R W IN 5 1 5 0 D31 D0 ALT MASTER WRITE D31 D0 OUT ALT MASTER READ TA OUT MOTOROLA Figure 11 5 Snoop Hit Timing gt KO 9 lt gt des 2 gt M68040 USER S MANUAL UK R W IN 6 TSIN RES 03 Q2 lt gt TEA N Figure 11 6 Snoop Miss Timing 11 10 M68040 USER S MANUAL MOTOROLA 6 lt IPEND RSTO N PST3 PSTO pc m CDIS lt MDIS PT meu X 13 IPL2 IPL0 Figure 11 7 Other Signal Timing MOTOROLA M68040 USER S MANUAL 11 11 11 8 MC68040 THERMAL DEVICE CHARACTERISTICS The need to efficiently cool microprocessors is becoming more important as they become more complex and require more power In the past the M68000 family has been able to provide 0 70 ambient temperature part for speeds less than 40 MHz However the MC68040 MC68LC040 and MC68EC040 with a 50 MHz processor clock has a maximum power dissipation for a particular operating mode a maximum junction temperature and a thermal resistance from the die junction to the case This section provides a more accurate method of evaluating the environment taking into consideration both the airflow and ambient temperature This section also gives the user information to design a cooling method that meets both thermal performance requirements and constraints of
184. ABLE Byte 9 3 9 25 Encodings 9 3 MODE Byte 9 3 9 31 9 37 Floating Point Data Register 9 2 9 15 Floating Point Registers Floating Point Instruction Address Register FPIAR 1 8 9 6 9 32 9 35 9 38 Floating Point State Frames 7 38 9 39 Field Definitions 9 42 9 43 Floating Point Unit FPU 1 2 1 4 Exception Handler 9 5 Floating Point State Frame 7 38 Format 4 Stack Frame A 5 Integer Pipeline 10 29 Programming Model 9 2 Floating Point User Exception Handler BSUN 9 26 Divide by Zero 9 36 INEX 9 28 9 30 9 32 9 33 9 35 9 37 9 38 OPERR 9 29 9 30 OVFL 9 32 9 33 SNAN 9 28 UNFL 9 35 Floating Point Vector Numbers 9 20 Forced Rounding Precision 9 13 9 31 9 34 Format Error 8 12 8 28 9 20 Heat Sink 11 29 11 31 HIGHZ 6 3 6 12 IEEE Aware Tests see Conditional Tests IEEE Standard 1149 1 see JTAG Implicit Bus Ownership see Bus Arbitration States Indeterminate Condition see Bus Arbitration Indirect Descriptor see Descriptors Instruction Execution 2 5 Instruction Timing 10 1 10 36 Instruction Prefetches 4 13 M68040 USER S MANUAL INDEX 3 Instructions Forced Rounding Precision 9 13 9 31 9 34 Privilege Violation Generating 8 10 Trace Exception Generating 8 10 Integer Unit 1 4 2 1 7 3 Supervisor Programming Model 1 7 2 5 2 6 User Programming Model 1 6 2 4 Integer Unit Pipeline 1 3 2 1 2 3 10 5 ea Calculate Stage 1 3 2 1 2 2 10 3 10 4 10 6 ea
185. AGE ATTRIBUTES ON UPAO 4 DRIVE SIZE ON 5121 5170 BYTE WORD OR LONG WORD 5 DRIVE TRANSFER ON 1 TTO 6 DRIVE TRANSFER MODIFIER ON TM2 TMO 7 CIOUT BECOMES VALID 8 ASSERT TS FOR ONE CLOCK 9 ASSERT TIP PRESENT DATA 1 DECODE ADDRESS 2 PLACE DATA ON APPROPRIATE BYTES OF D31 D0 BASED ON SIZEx 0 AND A1 3 ASSERT TA ACQUIRE DATA lt 1 LATCH DATA TERMINATE CYCLE 1 REMOVE DATA FROM 031 00 START NEXT CYCLE 2 NEGATE TA Figure 7 8 Byte Word and Long Word Read Transfer Flowchart 7 10 M68040 USER S MANUAL MOTOROLA C2 C1 C2 CW C1 C2 C1 BCLK A31 A2 Al 0 UPA1 5171 5170 1 0 2 0 031 024 D15 D8 07 00 023 016 LONG WORD READ WITH WAIT BYTE READ gt WORD READ Figure 7 9 Byte Word Long Word Read Transfer Timing 11 M68040 USER S MANUAL MOTOROLA Clock 1 C1 The read cycle starts in C1 During the first half of C1 the processor places valid values on the address bus and transfer attributes For user and supervisor mode accesses which the corresponding memory unit translates the user programmable attribute signals UPAx are driven with the values from the matching user bits 01 and 00 The transfer type TTx and transfer modifier TMx signals identify the specific access type The read write R W signal is driven high for a read cycle Cache inhibit out CIOUT is asser
186. AL A 15 RAW IN SC1 50 47 TS IN De Wi E gt 403 TA PN E 7 BB IN Figure A 8 Snoop Miss Timing A 16 M68040 USER S MANUAL MOTOROLA 60 lt gt IPEND RSTO PST3 PSTO CDIS MDIS IPL2 IPLO Figure A 9 Other Signal Timing M68040 USER S MANUAL M68040 USER S MANUAL MOTOROLA APPENDIX B 68 040 All references to MC68EC040 also apply to the MC68ECO40V Refer to Appendix C MC68040V and MC68ECO40V for more information on the MC68ECO40V The MC68EC040 is Motorola s third generation of M68000 compatible high performance 32 bit microprocessors The MC68EC040 is an embedded controller employing a highly integrated architecture to provide very high performance in a monolithic HCMOS device The MC68ECO040 integrates an MC68040 compatible integer unit an access control unit ACU and independent 4 Kbyte instruction and data caches A six stage instruction pipeline multiple internal buses and a full internal Harvard architecture including separate caches for both instruction and data accesses provides a high degree of instruction execution parallelism The inclusion of on chip bus snooping logic which directly supports cache coherency in multimaster applications enhances cache functionality The MC68EC040 is user object code compatible with previous members of the M68000 family and is specifically o
187. AL MOTOROLA The DRVCTL T instruction is intended to be used test applications in conjunction with the EXTEST and SHUTDOWN instructions and not for system applications It therefore differs from DRVCTL S in that this instruction invokes the keep alive clock asserts the internal reset and the test logic not the system logic has control of the pins When the system logic has control of signal pin directions and levels the drive control latch is loaded from the IPL2 IPLO pins during the negation DRVCTL T overwrites this value with boundary scan data in the update DR state The selected output driver state remains unchanged if only the DRVCTL T EXTEST or SHUTDOWN instructions are invoked If an instruction other than one of these three is executed the system logic protocol regains control of the output driver state and overwrites the value that the DRVCTL T instruction previously defined Note that the output drive control state does not change while the 1149 1A instruction is one of the three instructions DRVCTL T EXTEST or SHUTDOWN If DRVCTL T changes the output driver state and then the test logic reset state is entered the instruction shift register is reset to BYPASS and the system logic can change the output driver state 6 2 5 SHUTDOWN This instruction provides an opcode for automatic test pattern generation ATPG programs to cope with the clocking protocol required to stop the system cloc
188. ANUAL MOTOROLA LIST OF ILLUSTRATIONS Continued Figure Number Title 7 26 Word Write Access Terminated with TEA Timing 7 27 Line Read Access Terminated with TEA Timing 7 28 Retry Bead Transfer Timing ee 7 29 Retry Operation on Line 7 30 M68040 Internal Interpretation State Diagram and External Bus Arbiter Circuit ec tec Urbe a ep ire ned 7 31 Lock Violation uoc iei Doe 7 32 Processor Bus Request Timing Reps uud 7 33 Arbitration During Relinquish and Retry Timing 7 34 Implicit Bus Ownership Arbitration Timing 7 35 Dual M68040 Fairness Arbitration State 7 36 Dual M68040 Prioritized Arbitration State Diagram 7 37 M68040 Synchronous DMA Arbitration 7 38 Sample Synchronizer CIFGUIL Peste o hae 7 39 M68040 Asynchronous DMA Arbitration 7 40 Snoop Inhibited Bus 422 111 7 41 Snoop Access with Memory 7 42 Snooped Line Read Memory 7 43 Snooped Long Word Write Memory Inhib
189. AP n execution of the new instruction flow clears the exception condition This also applies to the not taken branch for a conditional branch instruction even though both sides of the branch are decoded Processor accesses for either data or instructions can result in internal access faults Internal access faults must be corrected to complete execution of the current context Four types of internal access faults can occur 1 Push transfer faults occur when the execution unit is idle the integer unit pipeline is frozen the instruction and data cache requests are cancelled however writes are not lost and pending writes are stacked 2 Data access faults occur when the bus controller and the execution unit are idle A data access fault freezes the pipeline and cancels any pending instruction cache accesses Pending writes are stacked because the data cache is deadlocked until stacking transfers are initiated 8 6 M68040 USER S MANUAL MOTOROLA 3 Instruction access faults occur when the PC section is deadlocked because of the faulted data or another prefetch is required the copyback stage is empty and the data cache and bus controller are idle Since instruction access faults are reset they can be ignored 4 internal access fault also occurs when the data or instruction MMU detects that a successful address translation is not possible because the page is write protected supervisor only or nonresident Furthermore when an addres
190. AT 2 address error address is the reference address 1 ADDRESS 8 22 M68040 USER S MANUAL MOTOROLA 8 4 4 Floating Point Post Instruction Stack Frame Format 3 The processor restores the SR and PC values from the stack and increments the active supervisor stack pointer by C If another floating point post instruction exception is pending exception processing begins immediately for the new exception otherwise the processor resumes normal instruction execution Stack Frames Exception Types Stacked PC Points To 15 Floating Point Post Next Instruction ea is the SP STATUS REGISTER Instruction calculated effective address 02 for the floating point PROGRAM COUNTER n ahlo instruction 06 0011 VECTOR OFFSET EFFECTIVE ADDRESS 4508 FLOATING POINT POST INSTRUCTION STACK FRAME FORMAT 3 8 4 5 Eight Word Stack Frame Format 4 The MC68040V MC68LC040 MC68EC040 and MC68ECO40V use this stack frame for unimplemented floating point instructions The MC68040 does not generate or recognize this format stack frame Refer to Appendix A MC68LC040 and Appendix B MC68EC040 for further details about this stack frame MOTOROLA M68040 USER S MANUAL 8 23 8 4 6 Access Error Stack Frame Format 7 A 30 word access error stack frame is created for data and instruction access faults other than instruction address errors In addition to information about the current processor st
191. B 2 lt gt and Set Condition Codes CPUSH If supervisor state CPUSHL caches An then if data cache push selected dirty data CPUSHP caches An cache lines invalidate selected cache lines CPUSHA caches else TRAP DBcc If condition false DBcc Dn lt label gt then Dn 1 2 Dn If Dn z 1 then dn e PC DIVS DIVSL Destination Source Destination DIVS W ea Dn 32 16 16r 16q DIVS L lt ea gt Dq 32 32 2 324 DIVS L lt ea gt Dr Dq 64 32 32r 32q DIVSL L lt ea gt Dr Dq 32 32 32 32 DIVU DIVUL Destination Source Destination DIVU W ea Dn 32 16 2 16r 16q DIVU L lt ea gt Dq 32 32 23264 DIVU L lt ea gt Dr Dq 64 32 2 32r 32q DIVUL L lt ea gt Dr Dq 32 32 32r 32q Source Destination Destination EOR Dn ea EORI Immediate Data Destination Destination lt data gt lt ea gt EORI to CCR Source CCR e EORI lt data gt CCR EORI to SR If supervisor state EORI lt data gt SR then Source 6 SR e SR else TRAP MOTOROLA M68040 USER S MANUAL 1 15 Table 1 4 Instruction Set Summary Continued EXG Rx t e Ry EXG Dx Dy EXG Ax Ay Dx Ay EXG Ay Dx EXT Destination Sign Extended e Destination EXT W Dn extend byte to word EXTB EXT LL Dn extend word to long word EXTB LDn extend byte to long word 52 Absolute Value of Source e FPn FABS fmt ea FPn FABS X FPm FPn FABS X FPn FrABS lt fmt gt ea FPn3 FrAB
192. BI to detect normal bus error retry and burst inhibited terminations Note that for alternate bus master burst inhibited line transfers the M68040 snoops each of the four resulting long word transfers If snooping is disabled MI is negated and the M68040 counts the appropriate number of TA or TEA assertions before proceeding For example if the SIZx signals are pulled high the M68040 requires four TA assertions one TEA assertion or one retry termination before proceeding As a bus master the M68040 can be configured to request snooping operations on a page by page basis The UPAx signals are connected to the 5 inputs of the snooping processors Appropriately programming the user attribute bits in the corresponding page descriptor selects the required snooping operation for a page Refer to Section 3 Memory Management Unit Except MC68EC040 and 68 040 for details on configuring the caching mode and user attribute bits for each memory page for the M68040 and MC68LCO040 and refer to Appendix B MC68EC040 for the MC68EC040 In a system with multiple bus masters the memory unit must wait for each snooping bus master to negate MI before responding to an access A termination signal asserted before the negation of MI leads to undefined operation and must be avoided at all costs Also if the system contains multiple caching masters then each master must access shared data using write through pages that allow writes to the data to be s
193. BUS TRANSFERS WITH R BIT CLEAR PROTECTION STATUS V LOGICAL OR OPERATOR 4 ASSIGNMENT OPERATOR RETURN EXIT TABLE SEARCH Fetch Operation 3 11 Motorola highly recommends that the translation tables be placed in cache inhibited memory space Motorola also highly recommends table descriptors must not be left in states that are incoherent to the processor Future processors may treat these recommendations as mandatory The following paragraphs apply only to M68040 systems that cannot meet these recommendations The processor never allocates table descriptors in the data cache when the processor performs a table search Only normal accesses to the translation tables cause descriptors to be allocated in the data cache If table descriptors are allocated in the data cache and the cache is disabled the processor locks up trying to access a cached descriptor during a table search Ensuring that the data cache is invalidated before enabling the MMU or disabling the data cache and ensuring that the pages containing table descriptors are pushed and invalidated prevents lockup during table searches Table and page descriptors must not be left in a state that is incoherent to the processor Violation of this restriction can result in an undefined operation Page descriptors must not have an encoding of U bit 0 M bit 1 and PDT field 01 or 11 This encoding indicates that the page descriptor is resident not used and modified The processor s tabl
194. Branch 7 50 Conditional Tests 9 15 9 17 Floating Point IEEE Tests 9 17 9 18 9 25 Unordered Conditions 9 17 9 18 Control Signals 7 1 7 9 Copyback see Caching Modes 0 Data Bus 7 1 7 3 Data Format 1 9 9 7 Extended Precision 9 12 9 21 9 23 9 24 Floating Point Conversion of 9 12 Packed Decimal Real 9 22 INDEX 2 M68040 USER S MANUAL Data Latch Enable DLE Mode 1 2 5 5 5 14 7 70 A 5 Data Registers 2 4 Data Types 9 7 Denormalized Numbers 1 9 9 12 9 22 9 23 9 16 Infinities 1 9 NANS 1 9 9 17 Normalized Numbers 1 9 9 16 9 33 Unnormalized Numbers 9 12 9 22 9 23 Zeros 1 9 Decode Stage see Integer Unit Pipeline Demand Memory 3 1 Denormalized Numbers see Data Types Descriptors 3 8 3 12 CM Field 4 6 5 8 Field Definitions 3 13 Indirect 3 9 3 14 PDT Field 3 17 Invalid 3 9 3 14 M Bit 3 21 Page 3 12 3 13 3 17 3 23 3 24 4 5 Resident 3 14 S Bits 3 23 Table 3 12 3 13 3 24 UDT Field 3 19 U Bit 3 21 W Bits 3 24 Direct Memory Access DMA 7 56 Dirty Data 4 1 5 8 Disabling JTAG 6 13 Disregard Request Condition 7 55 Double Bus Fault 7 43 8 8 8 18 DRVCTL T 6 3 6 12 Dynamic Bus Sizing 7 3 zB Effective Address ea 2 3 Execute Stage see Integer Unit Pipeline Exception Handler 8 4 Exception Processing 1 6 2 5 7 36 7 37 7 43 A 6 Exception Vector 2 7 Table 8 1 8 4 Exceptions Access Error 1 5 3 23 3 24 5 14 7 37 7 43 9 21 A 6 Access
195. Bus Cycles Where the byte offset 1 and 0 equals this encoding The processor always prefetches instructions by reading a long word from a half line address 2 0 regardless of alignment When the required instruction begins at the second long word the processor attempts to fetch the entire half line two long words although the second long word contains the required instruction 7 4 PROCESSOR DATA TRANSFERS The transfer of data between the processor and other devices involves the address bus data bus and control signals The address and data buses are normally parallel nonmultiplexed buses supporting byte word long word and line 16 byte bus cycles Line transfers are normally performed using an efficient burst transfer which provides an initial address and time multiplexes the data bus to transfer four long words of information to or from the slave device Slave devices that do not support bursting can burst inhibit the first long word of a line transfer forcing the bus master to complete the access using three additional long word bus cycles All bus input and output signals are synchronous to the rising edge of the BCLK signal The M68040 moves data on the bus by issuing control signals and using a handshake protocol to ensure correct data movement The following paragraphs describe the bus cycles for byte word long word and line read write and read modify write transfers MOTOROLA M68040 USER S MANUAL 7
196. CINV and CPUSH instructions support cache management in the supervisor mode CINV allows selective invalidation of cache entries CPUSH performs two operations 1 any selected data cache lines containing dirty data are pushed to memory 2 all selected cache lines are invalidated This operation can be used to update a page in memory before swapping it out with snooping disabled or to push dirty data when changing a page caching mode to write through Because of the size of the caches pushing pages or an entire cache incurs a significant time penalty However these instructions are interruptable to avoid large interrupt latencies The state of the CDIS signal or the cache enable bits in the CACR does not affect the operation of CINV and CPUSH Both instructions allow operation on a single cache line all cache lines in a specific page or an MOTOROLA M68040 USER S MANUAL 4 5 entire cache and select one or both caches for the operation For line and page operations a physical address in an address register specifies the memory address 4 3 CACHING MODES Every IU access to the cache has an associated caching mode that determines how the cache handles the access An access can be cachable in either the write through or copyback modes or it can be cache inhibited in nonserialized or serialized modes The field corresponding to the logical address of the access normally specifies on a page by page basis one of these caching mode
197. CKE signal is set to a high impedance state LOCKE drives high before MOTOROLA M68040 USER S MANUAL 57 three stating Do not use LOCKE if it is possible to retry the last write of a read write modify operation 5 3 9 Cache Inhibit Out CIOUT This three state output reflects the state of the cache mode field in one of the address translation caches and is asserted for accesses to noncachable pages to indicate that an external cache should ignore the bus transfer When the referenced logical address is within an area specified for transparent translation the cache mode field of the appropriate transparent translation register controls the state of CIOUT Refer to Section 3 Memory Management Unit Except MC68EC040 and MC68ECO40V for more information about the address translation caches and transparent translation When the 68040 is not the bus master the CIOUT signal is set to a high impedance state 5 4 BUS TRANSFER CONTROL SIGNALS The following signals provide control functions for bus transfers Refer to Section 7 Bus Operation for detailed information about the relationship of the bus transfer control signals to bus operation 5 4 1 Transfer Start TS The processor asserts this three state bidirectional signal for one clock period to indicate the start of each transfer During alternate bus master accesses the processor monitors this signal to detect the start of each transfer to be snooped 5 4 2 Transfer in Progress
198. CO40V Table 5 2 Transfer Type Encoding o 1 Alternate Logical Function Code Access Acknowledge Access MOTOROLA M68040 USER S MANUAL 55 5 3 2 Transfer Modifier 2 These three state outputs provide supplemental information for each transfer type Table 5 3 lists the encoding for normal and MOVE16 transfers and Table 5 4 lists the encoding for alternate access transfers For interrupt acknowledge transfers the TMx signals carry the interrupt level being acknowledged for breakpoint acknowledge transfers and LPSTOP broadcast cycles on the MC68040V and MC68bECO040V the TMx signals are low When the M68040 is not the bus master the TMx signals are set to a high impedance state Table 5 3 Normal and MOVE16 Access Transfer Modifier Encoding o o bataCachePushaccess 1 o 1 UM Tane search bata o o MOVE16 accesses use only these encodings Table 5 4 Alternate Access Transfer Modifier Encoding o o o o O T c sea o Logica Function code _____________ 5 3 3 Transfer Line Number TLN1 TLNO These three state outputs indicate which line in the set of four data cache lines is being accessed for normal push and line data read accesses TLNx signal
199. DS TRANSFERRED TERMINATE CYCLE END OF BURST 1 NEGATE TA IF NECESSARY 1 REMOVE DATA FROM 031 00 2 INCREMENT ADDRESS BITS A3 A2 IF 2 NEGATE TIP IF REQUIRED NECESSARY Y UNTIL FOUR LONG WORDS TRANSFERRED START NEXT CYCLE Figure 7 16 Line Write Transfer Flowchart MOTOROLA M68040 USER S MANUAL 7 23 2 0 l l l l l 5171 5170 1 1 RW I I CIOUT 15 l l l l i l l l l l l l X X X NOTE The selected device increments the value of A3 and A2 Figure 7 17 Line Write Transfer Timing Clock 1 C1 The line write cycle starts in C1 During the first half of C1 the processor places valid values on the address bus and transfer attributes For user and supervisor mode accesses that are translated by the corresponding memory unit UPAx signals are driven with the values from the matching U1 and UO bits The TTx and TMx signals identify the specific access type The R W signal is driven low for a write cycle and SIZ1 and SIZO indicate line size CIOUT is asserted for a MOVE16 operand read if the access is identified as noncachable Refer to Section 3 Memory Management Unit Except 68 040 and MC68ECO40V for information on M68040
200. Designating the memory page containing the address of the device as serialized noncachable prevents multiple out of order accesses to devices sensitive to such accesses When the data memory unit detects an attempt to read an operand from a page designated as serialized noncachable it allows all pending write accesses to complete before beginning the external read access The definition of a page as noncachable versus serialized noncachable only affects read accesses When a write operation reaches the integer unit s write back stage all previous instructions have completed When read access to a serialized noncachable page begins only a bus error exception MOTOROLA M68040 USER S MANUAL 7 43 on the operand read itself can cause the instruction to be aborted preventing multiple reads It is important to note that when memory accesses are serialized noncachable FMOVE will cause two identical writes to the same location to occur if the next instruction prefetch receives a bus error Since write cycles can be deferred indefinitely many subsequent instructions can be executed resulting in seemingly nonsequential instruction execution When this action is not desired and the system depends on sequential execution following bus activity the NOP instruction can be used The NOP instruction forces instruction and bus synchronization because it freezes instruction execution until all pending bus cycles have completed A write operation of control i
201. E TRANSFER CONTROL TEST Vcc GND L POWER SUPPLY NOTE This signal is 51 on the MC68ECO40V Figure C 1 MC68040V and MC68ECO40V Functional Signal Groups C 2 LOW POWER STOP MODE The low power stop mode is a reduced power mode of operation that causes the MC68040V and MC68ECO040V to remain quiescent until either a reset or non masked interrupt occurs This mode of operation has four phases of operation and is triggered by the low power stop LPSTOP instruction 1 Perform a LPSTOP broadcast cycle 2 End integer unit IU instruction pipeline sequencing which is similar to the STOP instruction sequence IMM data SR at termination of the LPSTOP broadcast cycle MOTOROLA M68040 USER S MANUAL 3 Orderly shutdown of the clock circuitry culminating in the low power stop mode 4 Return to normal operation after the receipt of a non masked interrupt or reset when the clocks are restarted in an orderly manner Once the LPSTOP instruction has reached the execute stage of the IU pipeline and when all CPU and bus activity has completed the IU generates an LPSTOP broadcast cycle Table C 2 lists how the LPSTOP broadcast cycle drives the bus Table C 2 Bus Encodings During LPSTOP Broadcast Cycle TTO 031 016 XXXX Either TA or TEA terminates the LPSTOP broadcast cycle By withholding the assertion of TA or TEA external logic can extend the cycle controlling the beginning of the low
202. Exponent Format Maximum 255 7FF Fraction Representation of Fraction Nonsignaling Signaling Nonzero Bit Pattern Created by User Fraction When Created by FRCP M68040 USER S MANUAL 9 10 Table 9 5 Extended Precision Real Format Summary Data Format 95 94 8079 64 63 62 s u li f Field Size in Bits Interpretation of Unused Bits Output Interpretation of Sign Positive Mantissa Negative Mantissa Normalized Numbers Mantissa Explicit Integer Bit and Fraction Relation to Representation of Real Numbers Denormalized Numbers Signed Zeros Biased Exponent Format Minimum Mantissa Explicit Integer Bit and Fraction Signed Infinities Biased Exponent Format Maximum 32767 7FFF Explicit Integer Bit Mantissa Explicit Integer Bit and Fraction 1 16 Don t Care All Zeros 5 0 5 1 16383 0 lt lt 32767 7 Zero Nonzero 1 5 26 1 6383 0 50000 x14 16383 3FFF 1 M68040 USER S MANUAL Nonzero 5 2 16383 0 0000 x 000 0000 x 0 f MOTOROLA Table 9 5 Extended Precision Real Format Summary Continued Explicit Integer Bit Biased Exponent Format Maximum Representation of Mantissa Nonsignaling 1 Signaling Nonzero Bit Pattern Created by User X XXXXX Mantissa When Created by FPCP 1 11111 Table 9 6 Packed Decimal Real Fo
203. FPU implements single and double precision floating point data formats as defined by the IEEE 754 standard The FPU does not directly support packed decimal real format However by trapping as an unimplemented data format instead of as an illegal instruction software emulation supports the packed decimal format Additionally each data format has a special encoding that represents one of five data types normalized numbers denormalized numbers zeros infinities and not a numbers NANs Table 1 1 lists the data formats for both the IU and the FPU Refer to M68000PM AD M68000 Family Programmer s Reference Manual for details on data format organization in registers and memory Table 1 1 M68040 Data Formats operand Data Format Se Supponedin ferred rss memes sw um S sm sme umo 1 8 ADDRESSING CAPABILITIES SUMMARY The M68040 supports the basic addressing modes of the M68000 family The register indirect addressing modes support postincrement predecrement offset and indexing which are particularly useful for handling data structures common to sophisticated MOTOROLA M68040 USER S MANUAL 1 9 applications and high level languages program counter indirect mode also has indexing and offset capabilities This addressing mode is typically required to support position independent software Besides th
204. For the MC68040V MC68LC040 and MC68EC040 ignore all references to floating point For the MC68ECO040 and MC68ECO040V ignore all references to the memory management unit MMU Special modes of operation do not apply to these devices Refer to Appendix MC68LC040 and Appendix MC68EC040 for details 7 1 BUS CHARACTERISTICS The M68040 uses the address bus A31 A0 to specify the address for a data transfer and the data bus D31 D0 to transfer the data Control signals indicate the beginning and type of a bus cycle as well as the address space and size of the transfer The selected device then controls the length of the cycle by terminating it using the control signals The M68040 uses two clocks to generate timing a processor clock PCLK and a bus clock BCLK The PCLK signal is twice the frequency of the BCLK signal and is internally phase locked to BCLK PCLK is also distributed throughout the device to generate additional timing for additional edges for internal logic blocks and has no bearing on bus timing The use of dual clock inputs allows the bus interface to operate at half the speed of the internal logic of the processor requiring less stringent memory interface requirements Since the rising edge of BCLK is used as the reference point for the phase locked loop PLL all timing specifications are referenced to this edge Figure 7 1 illustrates the general relationship between the two clock signals and most input and output s
205. GND GND TLNO P O O O 10 TTO SIZ1 5170 A12 GND All RW GND TMO M O A13 Vcc GND Vcc 1 L 14 GND GND MC68040 PINOUT Vcc GND 0 K BOTTOM VIEW 15 16 GND 18 X 18 CAVITY DOWN GND TM2 Al J O A17 19 Vcc 2 5 O O O O A18 GND Vcc GND 4 G O O A20 23 6 Vcc AS Q A21 GND 25 A9 GND 7 E 2 A22 26 A28 029 030 A8 D A24 GND A30 027 GND 031 C O O O O O O O O O O O _ 27 DO D2 Vcc GND GND Vcc GND Vcc GND Vcc GND Vcc 023 025 Vcc 028 B O O O O O O O A29 GND 01 GND Vcc GND D8 GND Vcc GND 016 018 GND Vcc GND 022 GND D26 A A31 D3 04 D5 06 07 09 011 012 013 014 015 017 019 D20 021 024 1 2 3 4 5 6 7 8 9 10 11 1 13 14 15 16 17 18 Internal Logic C6 C7 C9 C11 C13 16 13 M16 C5 C8 C10 C12 C14 H16 J3 J16 116 R11 R13 S6 S10 T4 MS R5 R12 Output Drivers B2 B4 B6 B8 B10 B13 B15 B17 D2 D17 B5 B9 B14 C2 C17 G2 G17 M2 M17 R2 F2 F17 H2 H17 L2 L17 N2 N17 Q2 Q17 R17 S16 S2 515 517 12 2 M68040 USER S MANUAL MOTOROLA 12 2 2 MC68LC040 Pin Grid Array
206. IMIN sai canteen er rod dette edet C 26 16 cSnoopMISS TIRIDIO u a C 27 Cate Other Signal TIMING eid oce creo Ee P er Ud C 28 C 18 Going into LPSTOP with C 29 C 19 LPSTOP no Arbitration CPU is Master C 30 C 20 Exiting LPSTOP with Interruption deo eo n C 31 C 21 Exiting of LPSTOP with RESET s distat dx E HE roi ore C 31 MOTOROLA M68040 USER S MANUAL xxi LIST TABLES Table Page Number Title Number 1 1 M68040 Data o a datei bc se br deu a hu tac otc esha 1 9 1 2 Effective Addressing 1 10 1 3 Notational CONVENTIONS 1 11 1 4 Instruction Set Summary ect EO Poe ee ent 1 14 3 1 Updating U Bit and M Bit for Page 3 22 3 2 SFG arid DFO Malus oio dieit orae m erbe B 3 22 4 1 Snoop Control Encoeltig o io d Pee EE dto ia 4 9 4 2 IFEBPOETICDOIUIG ales esa 4 11 4 3 Instruction Cache Line State 2 4 15 4 4 Data Cache Line State Transitions 4 17 5 1 Signal Inde pico COL iue Ub tue Meet 5 2 5 2 Transfer Type ENC OG caa ceo aera at ratae ci tecta Re
207. INTERRUPT LEVEL 22 10 OR TRANSITION ON LEVEL 7 OTHERWISE ASSERT IPEND L W Figure 7 19 Interrupt Pending Procedure The M68040 asserts IPEND when an interrupt request is pending Figure 7 20 illustrates the assertion of IPEND relative to the assertion of an interrupt level on the IPLx signals IPEND signals external devices that an interrupt exception will be taken at an upcoming instruction boundary following any higher priority exception The IPEND signal negates after the processor recognizes the internal interrupt acknowledge and can precede the external interrupt acknowledge bus cycle sa pope o e oli PURO IPEND A IPLs RECOGNIZED gt gt ASSERT IPLs SYNCHRONIZED COMPARE REQUEST WITH MASK IN SR 3 lt Figure 7 20 Assertion of IPEND 7 30 M68040 USER S MANUAL MOTOROLA M68040 takes an interrupt exception for a pending interrupt within one instruction boundary after processing any other pending exception with a higher priority Thus the M68040 executes at least one instruction in an interrupt exception handler before recognizing another interrupt request The following paragraphs describe the various kinds of interrupt acknowledge bus cycles that can be executed as part of interrupt exception processing Table 7 4 provides a summary of the possible interrupt acknowledge terminations and the exception processing results Table 7 4
208. LA 00 Te 5144 1 1991 OWLS NOISH3A 1 15 2 vc TE T NOISWS3A 8121S INN vc TE G3NIJSON vc TE 9 41 M68040 USER S MANUAL MOTOROLA CMDREG1B This field contains the command word of the exceptional floating point instruction for an E1 exception which is an exception detected by the conversion unit CU in the floating point pipeline see Figure 9 1 For FSQRT CMDREG1B 6 0 mapped from 4 for the instruction to 5 in All other instructions map directly CMDREG3B This field contains the encoded instruction command word for exception which is an exception detected by the write back unit WB in the floating point pipeline see Figure 9 1 Figure 9 11 details the bit mapping between CMDREG1B and CMDREG3B For FSQRT bits CMDREG1B 6 0 are changed from 4 for the instruction to 5 for CMDREG1B and therefore map to 21 for 15 1312 10 9 16 0 SRC DST CMD CMDREGIB OPCLASS Rx Ry 10 9 16 0 DST CMD CMDREG3B Ry Figure 9 11 Mapping of Command
209. LED CYCLE Figure 7 28 Retry Read Transfer Timing The processor retries any read or write cycles of a read modify write transfer separately LOCK remains asserted during the entire retry sequence If the last bus cycle of a locked access is retried LOCKE remains asserted through the retry of the write cycle MOTOROLA M68040 USER S MANUAL 7 41 the initial cycle of a line transfer retry causes the processor to retry the bus cycle as illustrated in Figure 7 29 However the processor recognizes a retry signaled during the second third or fourth cycle of a line as a bus error and causes the processor to abort the line transfer A burst inhibited line transfer can only be retried on the initial transfer A burst inhibited line transfer aborts if a retry is signaled for any of the three long word transfers used to complete the line transfer Negating the bus grant BG signal on the M68040 while asserting both TA and TEA provides a relinquish and retry operation for any bus cycle that can be retried see Figure 7 31 BCLK 5121 5120 LINE 1 1 1 1 1 R W 1 l 1 8 CIOUT 15 ene 2 UD AE PEN I 1 1 i
210. Low Voltage IOL 5ma Capacitance Vin 0 V f 1 MHz Capacitance is periodically sampled rather than 10095 tested MOTOROLA M68040 USER S MANUAL C 17 DRIVE TO24V BCLK 20V 20 VALID VALID OUTPUTS 1 V OUTPUT OUTPUT n l c DRIVE gt 24V INPUTS 2 0 5V NOTES 1 This output timing is applicable to all parameters specified relative to the rising edge of the clock 2 This input timing is applicable to all parameters specified relative to the rising edge of the clock LEGEND A Maximum output delay specification B Minimum output hold time C Minimum input setup time specification D Minimum input hold time specification Figure C 11 Drive Levels and Test Points for AC Specifications C 18 M68040 USER S MANUAL MOTOROLA 7 MC68040V MC68bEC040V ELECTRICAL CHARACTERISTICS The following paragraphs provide information on the maximum rating and thermal characteristics for the MC68040V and MC68ECO040V This section is subject to change For the most recent specifications contact a Motorola sales office C 7 1 Maximum Ratings 42 This device contains protective Characteristic Symbol Unit circuitry against damage due to high Supply Voltage Input Voltage static voltages or electrical fields 0 3 to 3 6 however it is advised that normal precautions be taken to avoid 0 5 to 45 5 application of any voltages
211. M68040 USER S MANUAL 617 num cell port function safe ccel dsval 0 BC 2 RSTO output2 X 1 BC 2 IPEND output2 X 2 BC 2 CIOUT X 156 0 Z 156 10 0 3 2 UPA 0 output3 X 156 0 Z 4 BC 2 UPA 1 output3 X 156 0 Z 5 2 0 output3 X 156 0 Z 6 4 0 input X 7 2 1 output3 X 156 0 2 8 4 1 input X 9 2 10 output3 X 150 0 2 150 io ab 10 4 10 input X 11 2 11 output3 X 150 0 Z 12 4 11 input X 13 2 12 output3 X 150 0 Z 14 4 12 input X 15 2 13 output3 X 150 0 Z 16 4 13 input X 17 2 14 output3 X 150 0 Z 18 4 14 input X 19 BC 2 15 output3 X 150 0 Z 20 4 15 input X 21 2 16 output3 X 150 0 Z 22 4 16 input X 23 2 17 output3 X 150 0 Z 24 4 17 input X 25 BC 2 18 output3 X 150 0 Z 26 4 18 input X 27 2 A 19 output3 X 150 0 Z 28 4 19 input X 29 2 A 20 output3 X 150 0 Z 30 4 20 input X 31 2 A 21 output3 X 150 0 Z 32 4
212. Motorola s floating point software package M68040FPSP ensure complete user object code compatibility There are two versions of the M68040FPSP one for applications compiled for the MC68881 MC68882 kernel version and the other for applications compiled for the MC68040 library version System integrators can install the kernel version as part of an MC68040 based operating system The kernel version is used to execute preexisting user object code written for the MC68881 MC68882 as part of the operating system User applications need not be recompiled or modified in any way once the kernel version is installed The MC68040 compiler writer and system integrator use the library version which provides less overhead than the kernel version Overhead is reduced because the appropriate floating point exception routine is called directly rather than taking an unimplemented instruction trap The library is M68000 application binary interface ABI and IEEE exception reporting compliant it is not UNIX9 exception reporting compliant The M68040FPSP provides the following features Arithmetic and Transcendental Instructions IEEE Compliant Exception Handlers MC68040 Unimplemented Data Type and Data Format Handlers Can Reside in a 64 Kbyte ROM Code Is Reentrant The M68040FPSP satisfies the IEEE Standard 754 for Binary Floating Point Arithmetic The average 25 MHz performance of the transcendental function subroutines is equivalent to that o
213. N REGISTER 0 DATA TRANSPARENT TRANSLATION REGISTER 1 UCTION TRANSPARENT TRANSLATION REGISTER 0 UCTION TRANSPARENT TRANSLATION REGISTER 1 INSTR INSTR MMU STAT US REGISTER SUPERVISOR PROGRAMMING MODEL Figure 1 2 Programming Model M68040 USER S MANUAL 1 7 The user programming model includes eight data registers seven address registers and a stack pointer register The address registers and stack pointer can be used as base address registers or software stack pointers and any of the 16 registers can be used as index registers Two control registers are available in the user mode the program counter PC which usually contains the address of the instruction that the MC68040 is executing and the lower byte of the SR which is accessible as the condition code register CCR The CCR contains the condition codes that reflect the results of a previous operation and can be used for conditional instruction execution in a program The supervisor programming model includes the upper byte of the SR which contains operation control information The vector base register VBR contains the base address of the exception vector table which is used in exception processing The source function code SFC and destination function code DFC registers contain 3 bit function codes These function codes can be considered extensions to the 32 bit logical address The processor automatically generates function codes to select address spaces for
214. NUAL 11 6 SOFTWARE CONSIDERATIONS The following MC68EC040 instructions are different from the 68040 PTEST PFLUSH CPUSH CINV MOVEC and all floating point instructions The PTEST and PFLUSH instructions should not be executed Execution of the PTEST instruction causes random bus cycles to occur Execution of the PFLUSH instruction produces indeterminate results Neither instruction causes the MC68EC040 to generate an exception The CPUSH and CINV instructions require special consideration A page is defined as a 4 Kbyte block of external memory The CPUSH and CINV page instruction opcodes can be used to push or invalidate 4 Kbyte blocks of memory The MC68bECO040 does not support 8 Kbyte pages The MOVEC to URP and SRP instructions are not valid and will produce indeterminate results Each ACU has a status register and translation control register that replace the MMU status register and translation control register of the MC68040 The MMU status register opcode of the MOVEC instruction can modify the ACU status register The MC68ECO040 ACU status register does not provide additional functionality to the ACU and is only provided for compatibility with the ACU MC68ECO030 status register The ACU status register may not be implemented in future M6BECOXO products 7 MC68EC040 ELECTRICAL CHARACTERISTICS The following paragraphs provide information on the maximum rating and thermal characteristics for the MC68EC040 only Refer to
215. OLA DLE MODE DATA BUS TIMING CASE 1 CASE 2 BCLK A Z EN IE ANE DLE sobs D0 D31 IN ET READ z c 59 d NORMAL DATA BUS TIMING N _ gt 00 0311 READ O NEU Figure 7 48 DLE versus Normal Data Read Timing Case 1 If DLE is negated and meets setup time specification 35 to the rising edge of BCLK when the bus read is terminated latch A is transparent and the read data must meet setup and hold time specifications 36 and 37 to the rising edge of BCLK Read timing is similar to normal timing for this case Case 2 If DLE is asserted the data bus levels are latched and held internally D31 DO must meet setup and hold time specifications 32 and 33 to the falling edge of DLE and can transition to a new level once DLE is asserted D31 DO must still meet setup time specification 436 to BCLK but not hold time specification 437 since the data is internally held valid as long as DLE remains asserted low MOTOROLA M68040 USER S MANUAL 7 71 7 72 M68040 USER S MANUAL MOTOROLA SECTION 8 EXCEPTION PROCESSING Exception processing is the activity performed by the processor in preparing to execute a special routine for any condition that causes an exception In particular exception processing does not include execution of the routine itself This section describes the processing for each type of integer unit exception exception priorities
216. OUBLE PRECISION S 0 MANTISSA 9594 80 79 64 63 62 1110 0 FORMAT IN STATE FRAME 0 0 0 50 5 MANTISSA b Double Precision Figure 9 9 Format of Denormalized Operand in State Frame 9 7 FLOATING POINT ARITHMETIC EXCEPTIONS The following eight user floating point arithmetic exceptions are listed in order of priority The MC68040 generates the first seven exceptions in hardware and the eighth only in software Branch Set on Unordered BSUN Signaling Not A Number SNAN Operand Error OPERR Overflow OVFL Underflow UNFL Divide by Zero DZ nexact 2 INEX2 nexact 1 INEX1 INEX1 exception is the condition that exists when a packed decimal operand cannot be converted exactly to the extended precision format in the current rounding mode Since 9 24 M68040 USER S MANUAL MOTOROLA the MC68040 does not directly support packed decimal real operands the processor never sets INEX1 bit in the FPSR EXC byte but provides it as a latch so that emulation software can report the exception A floating point arithmetic exception is taken in one of two situations The first situation occurs when the user program enables an arithmetic exception by setting a bit in the FPCR ENABLE byte and the corresponding bit in the FPSR EXC byte matches the bit in the FPCR ENABLE byte as a result of program execution this is referred to as maskable exception conditions A user write operation to the FPSR which sets a bit in the EXC byte d
217. PST2 STATUS l bens CLOCKS MASTER TS BCLK TRANSFER TIP PCLK CONTROL TCK TA TMS SLAVE TEA TDI TRANSFER TCI TDO CONTROL TBI TRST TEST L 50 51 GND L POWER SUPPLY Figure B 3 MC68EC040 Functional Signal Groups B 1 MC68EC040 DIFFERENCES The following differences exist between the MC68EC040 and MC68040 Two independent access control units 5 replace the MC68040 MMUs The ACU has four corresponding registers access control registers that the MC68040 implements as data transparent translation registers The page size is fixed at 4 Kbytes PTEST and PFLUSH instructions cause an indeterminate result i e an undetermined number of bus cycles the user should not execute them on the 68 040 The MC68EC040 does not contain an FPU which causes unimplemented floating point exceptions to occur using a new stack frame format B4 M68040 USER S MANUAL MOTOROLA The DLE MDIS pin names have been changed to 50 and 51 respectively e The MC68bECO040 does not implement the DLE mode multiplexed or output buffer impedance selection modes of operation The MC68EC040 implements only the small output buffer mode of operation All timing and drive capabilities of the MC68EC040 are equivalent to those of the MC68040 the small buffer mode of operation 2 JTAG SCAN 51 50 The MC68040 MDIS and DLE pin names have been changed to JS1 and JSO respectively During nor
218. REQUIRED START NEXT CYCLE Figure 7 12 Burst Inhibited Line Read Transfer Flowchart M68040 USER S MANUAL MOTOROLA C8 C7 C6 C5 C4 C3 C2 Cl BCLK A31 A4 A3 A2 A1 A0 UPAO 5121 5120 1 0 2 0 TLNO RW CIOUT 5 031 00 LONG WORD LONG WORD LONG WORD READ gt lt READ gt lt READ Figure 7 13 Burst Inhibited Line Read Transfer Timing INHIBITED LINE READ 7 19 M68040 USER S MANUAL MOTOROLA 7 4 3 Byte Word Long Word Write Transfers During a write transfer the processor transfers data to a memory or peripheral device The level on the TCI signal is ignored by the processor during all write cycles The bus controller performs byte word and long word write transfers for the following cases Accesses to a disabled cache Accesses to a memory page that is specified noncachable Accesses that are implicitly noncachable read modify write accesses and accesses to an alternate logical address space via the MOVES instruction Writes to write through pages Accesses that do not allocate in the data cache on a write miss table updates and exception stacking The first transfer of a line write is terminated with TBI forcing completion of the line access using three additional long word write transfers Cache line pushes for lines containing a single dirty long word Figur
219. S X FPm FPn3 FrABS X FPn3 FADD Source FPn e FPn FADD fmt ea FPn FADD X FPm FPn FrADD fmt lt ea gt FPn3 FrADD X FPm FPn3 2 If condition true FBcc SIZE label then PC e PC 2 FCMP FPn Source FCMP fmt lt ea gt FPn FCMP X FPm FPn FDBcc If condition true FDBcc Dn lt label gt then no operation else Dn 1 e Dn if Dn z 1 then PC e PC else execute next instruction FDIV2 FPn Source e FPn FDIV fmt ea FPn FDIV X FPm FPn FrDIV lt fmt gt ea FPn3 FrDIV X FPm FPn3 FMOVE Source z Destination FMOVE lt fmt gt ea FPn FMOVE lt fmt gt FPM lt ea gt FMOVE P FPm lt ea gt Dn FMOVE P FPm lt ea gt k FrMOVE lt fmt gt lt ea gt FPn3 2 FMOVE Source Destination FMOVE L ea FPcr FMOVE L FPcr lt ea gt FMOVEM2 Register List 2 Destination lt list gt lt ea gt 4 Source Register List FMOVEM X Dn lt ea gt FMOVEM X lt ea gt lt list gt 4 FMOVEM X lt ea gt Dn FMOVEM2 Register List 2 Destination FMOVEM L lt list gt lt ea gt Source Register List FMOVEM L ea list 9 FMUL2 Source x FPn e FPn FMUL fmt ea FPn FMUL X FPm FPn FrMUL fmt ea FPn FrMUL X 1 16 M68040 USER S MANUAL MOTOROLA Table 1 4 Instruction Set Summary Continued FNEG Source e FPn FNEG fmt ea FPn FNEG X FPm FPn FNEG X FPn FrNEG fmt ea FPn3 FrNEG X FPm FPn3 FrNEG X FRESTORE If
220. SECTION 2 This section describes the organization of the M68040 integer unit IU and presents brief description of the associated registers Refer to Section 3 Memory Management Unit Except 68 040 and 68 040 for details concerning the memory management unit MMU programming model and to Section 9 Floating Point Unit MC68040 Only for details concerning the floating point unit FPU programming model 2 1 INTEGER UNIT PIPELINE The IU carries out logical and arithmetic operations using six separate subunits Each unit is dedicated to a different stage of the IU pipeline handling a total of six separate instructions simultaneously Pipelining is a technique that overlaps the processing of different parts of several instructions Pipelining simulates an assembly line with the IU containing a number of instructions in different phases of processing The IU pipeline consists of six stages 1 Instruction Fetch Fetching an instruction from memory 2 Decode Converting an instruction into micro instructions ea the instruction calls for data from memory the location of the data its memory address is calculated 4 ea Fetch Data is fetched from memory Execute The data is manipulated during execution 6 Write Back The result of the computation is written back to on chip caches or external memory The pipeline contains special shadow registers that
221. SR 10 11 CINV 10 29 ASL 10 14 10 18 10 30 37 ASR 10 14 2 10 19 10 29 10 11 CMPA L 10 19 10 30 35 BCHG 10 15 10 19 10 30 36 BCLR 10 15 CMPM 10 11 FMOVE FPn lt ea gt 10 31 BFCHG 10 15 CPUSH 10 8 FMOVE FMOVEM 10 32 to from CR MOTOROLA M68040 USER S MANUAL 10 1 Table 10 1 Instruction Timing Index Continued instruction Page Page MOVE lt ea gt cise 1020 reser 10 2 M68040 USER S MANUAL MOTOROLA 10 1 OVERVIEW Refer to Section 2 Integer Unit for information on the integer unit pipeline The ea fetch timing is not listed in the following tables because most instructions require one clock in the ea fetch stage for each memory access to obtain an operand An instruction requires one clock to pass through the ea fetch stage even if no operand is fetched Table 10 2 summarizes the number of memory fetches required to access an operand using each addressing mode for long word aligned accesses The user must perform his own calculations for ea fetch timing for misaligned accesses Table 10 2 Number of Memory Accesses Evaluate ea Evaluate ea And Fetch And Send To Addressing Mode Operand Execution Stage An An d 16 An d 16 PC xxx W xxx L lt XXX gt dg An Xn dg PC Xn BR Xn bd BR Xn bd BR Xn bd BR Xn od bd BR Xn od BR Xn o
222. SS OTHERWISE MATCHES WITH TTRO n d IR 0 OR Pi FRISW 21 AND TTROYW 1 AND WRITE OR RMW WRITE OR RMW W 21 AND WRITE OR RMW CYCLE ACCESS 7 7 ACCESS OTHERWISE EXCEPTION TAKE ACCESS ERROR M 0 AND OTHERWISE EXCEPTION WRITE OR RMW CYCLE OTHERWISE OTHERWISE PA 4 LOGICAL ADDRESS UPA 4 TTR1 U1 U0 CM 4 TTRI CM PA 4 LOGICAL ADDRESS UPA 4 TTRO U1 UO CM 4 TTRO CM N ABORT CYCLE TABLE SEARCH OPERATION 4 ATC ENTRY PA UPA 4 ATC ENTRY U1 U0 CM 4 ATC ENTRY CM Refers to either instruction or data transparent translation register Figure 3 22 Address Translation Flowchart 3 32 M68040 USER S MANUAL MOTOROLA 3 7 MMU INSTRUCTIONS The M68040 instruction set includes three privileged instructions that perform MMU operations The following paragraphs briefly describe each of these instructions For detailed descriptions of these instructions refer to M68000PR AD M68000 Family Programmer s Reference Manual 3 7 1 MOVEC The MOVEC instruction transfers data between an integer data register or memory location and any of the M68040 control and status registers The operating system uses the MOVEC instruction to control and monitor MMU operation by manipulating and reading the eight MMU registers 3 7 2 PFLUSH The PFLUSH instruction flushes or invalidates address translation descriptors in the PFLUSHA a version of the PFLUSH instruct
223. STER 3 0 f TRANSPARENT TRANSLATION REGISTER 0 3 0 DTTR1 DATA TRANSPARENT TRANSLATION REGISTER 1 3 3 HTRQ L INSTRUCTION TRANSPARENT TRANSLATION REGISTER 0 3 0 L INSTRUCTION TRANSPARENT TRANSLATION J REGISTER 1 3 0 MMUSR MMU STATUS REGISTER Figure 3 2 Memory Management Programming Model 3 1 1 User and Supervisor Root Pointer Registers The SRP and URP registers each contain the physical address of the translation table s root which the MMU uses for supervisor and user accesses respectively The URP points to the translation table for the current user task When a new task begins execution the operating system typically writes a new root pointer to the URP A new translation table address implies that the contents of the ATCs may no longer be valid A PFLUSH instruction should be executed to flush the ATCs before loading a new root pointer value if necessary Figure 3 3 illustrates the format of the 32 bit URP and SRP registers Bits 8 MOTOROLA M68040 USER S MANUAL 3 3 0 of an address loaded into the URP or the SRP must be zero Transfers of data to and from these 32 bit registers are long word transfers 3 9 8 0 7 0 x Suasana Figure 3 3 URP and SRP Register Formats 3 1 2 Translation Control Register The 16 bit TCR contains two control bits to enable paged address translation and to select page size
224. Support Timings FABS FADD FCMP FMOVE FMUL FSQRT FSUB FTST lt gt Addressing Byte and Word Long Word Single Precision Mode ea ea ea Calculate Calculate Calculate 2 mre li 2 5 916 416 xxx L lt XXX gt bd An Xn bd An Xn bd An Xn od bd An Xn bd An Xn od wes mes A sere 11 7 1L 10 11 10 11 11 1 11 12 z 3L 10 3L 10 Double Precision Extended Precision 2 11 5 Ea Oe S u 1 2 2 3 7 gt 015 x 5 ak N 7 11 12 12 1 13 1 1 1 2 a E ES r am a jt T pep An An NEC d 16 W sss PC xxx W xxx L lt XXX gt 3 3 1 4 SEN 7 12 bd An Xn bd An Xn od For BR PC add one clock to both ea calculate and execute times Timings are for an idle FPU gt 5 gt 5 a u gt 5 An Xn bd An Xn bd An Xn bd An Xn od 10 30 M68040 USER S MANUAL MOTOROLA 10 7 2 Integer
225. T O TRST GND CDIS 2 0 50 TCI AVEC SCO BG PS 573 BR 5 2 cO GND TDI TMS MDIS RSTI Vcc GND GND TBI 501 TEA 5 GND Vcc GND LOCK R CIOUT Vcc RSTO GND Vcc GND Vcc GND GND Vcc GND PST TS Vcc LOCKE Q O 1 GND GND TLNO P O O 0 TTO 5171 5170 N 12 GND All GND M Vcc Vcc GND Vcc L ade Alg MC68LC040 PINOUT VCC GND A0 K BOTTOM VIEW 15 16 GND 18 X 18 CAVITY DOWN PGA GND TM2 1 A17 A19 Vcc Vcc 2 H 18 GND Vcc GND 4 G 20 Vcc 423 A6 Vcc A5 F O O O O O O A21 GND A25 9 GND A22 26 A28 029 030 A8 24 GND A30 027 GND 031 C _ 27 00 02 Vcc GND GND Vcc GND Vcc GND Vcc GND Vcc 023 025 Vcc 028 B O O A29 GND 01 GND Vcc GND 08 GND Vcc GND 016 018 GND Vcc GND 022 GND 026 A A31 D3 04 D5 D6 07 09 010 011 012 013 014 015 017 019 020 021 074 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1
226. Table Using S Bit and W Bit To Set Protection MOTOROLA M68040 USER S MANUAL 3 25 3 3 ADDRESS TRANSLATION CACHES The ATCs in the MMUs are four way set associative caches that each store 64 logical to physical address translations and associated page information similar in form to the corresponding page descriptors in memory The purpose of the ATC is to provide a fast mechanism for address translation by avoiding the overhead associated with a table search of the logical to physical mapping of recently used logical addresses Figure 3 20 illustrates the organization of the ATC 3l 16 12 0 F PAGE FRAME PAGE OFFSET 2 L L 2 11 0 _ gt PAGE SIZE X PAGE SIZE 19 gt STATUS LINE SELECT HIT 3 gt E HIT 2 HIT 1 COMPARATOR HIT 0 0 Figure 3 20 ATC Organization 3 26 M68040 USER S MANUAL MOTOROLA Each entry consists of a physical address attribute information from a corresponding page descriptor and a tag that contains a logical address and status information Figure 3 21 which illustrates the entry and tag fields is followed by field definitions listed in alphabetical order a For 4 Kbyte page sizes this field uses address bits 31 12 for 8 Kbyte page sizes bits 31 13 Figure 3 21 ATC Entry and Tag Fields CM Cache Mode This field
227. The operating system must flush the ATCs before enabling address translation since the TCR accesses and reset do not flush the ATCs All unimplemented bits of this register are read as zeros and must always be written as zeros The M68040 always uses word transfers to access this 16 bit register The fields of the TCRs are defined following Figure 3 4 which illustrates the TCR 15 14 B D 1 1 9 8 7 6 5 4 3 2 1 0 NOTE Bits 13 0 are undefined reserved Figure 3 4 Translation Control Register Format E Enable This bit enables and disables paged address translation 0 Disable 1 Enable A reset operation clears this bit When translation is disabled logical addresses are used as physical addresses The MMU instruction PFLUSH can be executed successfully despite the state of the E bit PTEST results are undefined if the MMU is disabled and no table search occurs If translation is disabled and an access does not match a transparent translation register TTR the access has the following default attributes on the TTR the caching mode is cachable write through write protection is disabled and the user attribute signals UPA1 and UPAO are zero P Page Size This bit selects the memory page size 0 4 Kbytes 1 8 Kbytes A reset operation does not affect this bit The bit must be initialized after a reset 3 4 M68040 USER S MANUAL MOTOROLA 3 1 3 Transparent Translation Registers
228. V BCLK OUTPUTS 1 DRIVE 24V INPUTS 2 DRIVE TO 0 5 V 2 0V RSTI 3 F E iPLx 2 0V MDIS 0 8 V NOTES 1 This output timing is applicable to all parameters specified relative to the rising edge of the clock 2 This input timing is applicable to all parameters specified relative to the rising edge of the clock 3 This timing is applicable to all parameters specified relative to the negation of the RSTI signal LEGEND A Maximum output delay specification B Minimum output hold time C Minimum input setup time specification D Minimum input hold time specification E Mode select setup time to RSTI negated F Mode select hold time from RSTI negated Figure 11 2 Drive Levels and Test Points for AC Specifications 11 6 M68040 USER S MANUAL MOTOROLA A31 A0 TRANSFER ATTRIBUTES TS TIP D31 D0 IN READ D31 D0 OUT WRITE TA TEA TBI NOTE Transfer Attribute Signals UPAx SIZx TTx TMx TLNx R W LOCK LOCKE CIOUT Figure 11 3 Read Write Timing MOTOROLA M68040 USER S MANUAL A31 A0 TRANSFER ATTRIBUTES LOCK LOCKE D31 D0 OUT WRITE BR Bm lt gt 00 gt lt gt ez NOTE Transfer Attribute Signals UPAx SIZx TTx TMx TLNx R W CIOUT Figure 11 4 Bus Arbitration Timing M68040 USER S MANUAL MOTOROLA BCLK A31
229. W SIZx TIP TMx TLNx TS TTx UPAx Signal Low Input Current 0 8 V TMS TDI 5 Signal High Input Current 2 0 V TMS TDI TRST V V V V L H Output Low Voltage 2 5 mA L Capacitance Vin 0 V f 1 MHz Capacitance is periodically sampled rather than 10096 tested li j IH Output High Voltage loH 5 mA O B 7 4 Power Dissipation mex wh C Typical Values 5 V TA 25 C This information is for system reliability purposes MOTOROLA M68040 USER S MANUAL 2 GND 20 20 1 1 0 94 2 4 VC O 0 16 gt 3 2 3 3 B 13 B 7 5 Clock AC Timing Specifications see Figure 7 25MHz fm ___________ 1667 zo 1667 5 1667 s Tue POLK with Measueaattsv 12 os vs 7 s POLK Puse wan Low Measuevatisv 12 13 os os 7 _ o o Borse aaran L s Bork buy measa rsv e a s Bork Pulse 20 12 Bouk Frequency Suy t9 to ppm o rokeros T
230. Y 31 24 23 16 15 8 7 0 XXX XXX XXX BYTE1 BYTE 0 XXX XXX XXX Figure 7 6 Example of a Misaligned Word Transfer MOTOROLA M68040 USER S MANUAL 7 7 11111111117 ma X UPA1 5121 BYTE WORD BYTE T T 5170 TT1 TTO TM2 TMO R W CIOUT A F A 3 A A D31 D24 D23 D16 BYTE 1 WORD BYTE lt READ lt READ Figure 7 7 Misaligned Long Word Read Transfer Timing D15 D8 A _ E _ m 07 00 lt READ 7 8 M68040 USER S MANUAL MOTOROLA The combination of operand size and alignment determines the number of bus cycles required to perform a particular memory access Table 7 3 lists the number of bus cycles required for different operand sizes with all possible alignment conditions for read and write cycles The table confirms that alignment significantly affects bus cycle throughput for noncachable accesses For example in Figure 7 5 the misaligned long word operand took three bus cycles because the byte offset 1 If the byte offset 0 then it would have taken one bus cycle The M68040 system designer and programmer should account for these effects particularly in time critical applications Table 7 3 Memory Alignment Influence on Noncachable and Write Through
231. a page as supervisor only Only programs operating in the supervisor mode are allowed to access the portion of the logical address space mapped by this descriptor when the S bit is set If the bit is clear both supervisor and user accesses are allowed 3 14 M68040 USER S MANUAL MOTOROLA Page Table Address This field contains the physical base address of a table of page descriptors The low order bits of the address required to index into the page table are supplied by the logical address U Used The processor automatically sets this bit when a descriptor is accessed in which the U bit is clear In a page descriptor table this bit is set to indicate that the page corresponding to the descriptor has been accessed In a pointer table this bit is set to indicate that the pointer has been accessed by the M68040 as part of a table search The U bit is updated before the M68040 allows a page to be accessed The processor never clears this bit UO U1 User Page Attributes These bits are user defined and the processor does not interpret them UO and U1 are echoed to the UPAO and 1 signals respectively if an external bus transfer results from the access Applications for these bits include extended addressing and snoop protocol selection UDT Upper Level Descriptor Type These bits indicate whether the next level table descriptor is resident 00 or 01 Invalid These codes indicate that the table at the next level is not res
232. ach locked sequence of transfers 4 Refer to Section 5 Signal Description for definitions of the TMx signal encodings for normal MOVE16 and alternate accesses 7 3 MISALIGNED OPERANDS All M68040 data formats can be located in memory on any byte boundary A byte operand is properly aligned at any address a word operand is misaligned at an odd address and a long word is misaligned at an address that is not evenly divisible by 4 However since operands can reside at any byte boundary they can be misaligned Although the M68040 does not enforce any alignment restrictions for data operands including PC relative data addressing some performance degradation occurs when additional bus cycles are required for long word or word operands that are misaligned For maximum performance data items should be aligned on their natural boundaries All instruction words and extension words must reside on word boundaries Attempting to prefetch an instruction word at an odd address causes an address error exception Refer to Section 8 Exception Processing for details on address error exceptions The M68040 data memory unit converts misaligned operand accesses that are noncachable to a sequence of aligned accesses These aligned accesses are then sent to the bus controller for completion always resulting in aligned bus transfers Misaligned operand accesses that miss in the data cache are cachable and are not aligned before line filling Refer to Secti
233. ack frames a four word throwaway stack frame an access error stack frame and a new eight word unimplemented floating point stack frame The stack frame that the MC68040 can generate and the MC68LC040 can process is the floating point post instruction stack frame Refer to Section 8 Exception Processing for details about exception stack frames Eight Word Stack Frame Format 4 The MC68040 cannot Effective address field is SP gt STATUS REGISTER generate or read this stack the address of the faulted PROGRAM COUNTER instruction operand 4506 0100 VECTOR OFFSET 508 EFFECTIVE ADDRESS PC OF FAULTED 00 INSTRUCTION When the MC68LC040 writes or reads a stack frame it uses long word operand transfers wherever possible Using a long word aligned stack pointer greatly enhances exception processing performance The processor does not necessarily read or write the stack frame data in sequential order The system software should not depend on a particular exception generating a particular stack frame For compatibility with future devices the software should be able to handle any format of stack frame for any type of exception The MC68LC040 does not generate the floating point post instruction stack frame The MC68040 cannot accept the eight word unimplemented stack frame The MC68LC040 can handle all MC68040 stack frame formats A 6 MC68LC040 ELECTRICAL CHARACTERISTICS The following paragraphs provide information on the ma
234. ad modify write accesses are aborted as if the R bit in a table descriptor were clear Refer to 3 2 2 Descriptors for a description of table descriptors 0 Read and write accesses permitted 1 Write accesses not permitted B 3 2 Address Comparison The following description of address comparison assumes that the ACRs are enabled Clearing the E bit in each ACR independently disables access control causing the processor to ignore it When an ACU receives a physical address the privilege mode and the eight high order bits of the address are compared to the block of addresses defined by the two ACRs for the corresponding ACU Each block of address space for an ACR contains an S field a BASE ADDRESS field and an ADDRESS MASK field The S field allows for matching either user or Supervisor accesses or both Setting a bit in the ADDRESS MASK field causes the corresponding bit of the ADDRESS BASE to be ignored in the address comparison and privilege mode Setting successively higher order bits in the ADDRESS MASK field increases the size of the block of address space The address for the current bus cycle and an ACR address match when the privilege mode and address bits for each not including the masked bits are equal Each ACR specifies write protection for the block of address space Enabling write protection for a block of address space causes the abortion of write or read modify write accesses to the block and an access error exception
235. address as a physical address for the access If there is no match the MMU compares the logical address and privilege mode with the tag portions of the entries in the ATC and uses the corresponding physical address for the access when a match occurs When neither a TTR nor a valid ATC entry matches the MMU initiates a table search operation to obtain the corresponding physical address from the translation table When a table search is required the processor suspends instruction execution activity and at the end of a successful table search stores the address mapping in the appropriate ATC and retries the access The MMU creates a valid ATC entry for the logical address and the access is retried If an access hits in the ATC but an access error or invalid page descriptor was detected during the table search that created the ATC entry the access is aborted and a bus error exception is taken If a write or read modify write access results in an ATC hit but the page is write protected the access is aborted and an access error exception is taken If the page is not write protected and the modified bit of the ATC entry is clear a table search proceeds to set the modified bit in both the page descriptor in memory and in the ATC the access is retried The ATC provides the address translation for the access if the modified bit of the ATC entry is set for a write or read modify write access to an unprotected page if the resident bit is set indicating th
236. address using the upper 3 2 M68040 USER S MANUAL MOTOROLA logical address bits If the translation is resident the MMU provides the physical address to the cache controller which determines if the instruction or data being accessed is cached The cache controller uses the lower address bits to index into memory An external bus cycle is performed only when explicitly requested by the cache controller When the translation is not in the ATC the MMU searches the translation tables in memory for the translation information Microcode and dedicated logic perform the address calculations and bus cycles required for this search 3 1 MEMORY MANAGEMENT PROGRAMMING MODEL The memory management programming model is part of the supervisor programming model for the M68040 The eight registers that control and provide status information for address translation in the M68040 are the user root pointer register URP the supervisor root pointer register SRP the translation control register TCR four independent transparent translation registers ITTO ITT1 DTTO and DTT1 and the MMU status register MMUSR Only programs that execute in the supervisor mode can directly access these registers Figure 3 2 illustrates the memory management programming model 31 0 URP USER ROOT POINTER REGISTER 31 0 3 SRP SUPERVISOR ROOT POINTER REGISTER 15 0 _ TCR TRANSLATION CONTROL REGI
237. ally ANDed with the external signal driving RTSI to derive a system reset signal that is asserted for both an external processor reset and execution of a RESET instruction MOTOROLA M68040 USER S MANUAL 9 B 5 EXCEPTION PROCESSING MC68EC040 provides five different stack frames for exception processing and allows for a MC68040 specific stack frame Refer to Section 8 Exception Processing for details on exception processing 5 1 Unimplemented Floating Point Instructions and Exceptions All legal MC68040 and MC68881 MC68882 floating point instructions are defined as unimplemented floating point instructions on the 68 040 These instructions generate an eight word stack frame format 4 during exception processing before taking an F line exception These instructions trap as an F line exception and can be emulated in software by the F line exception handler to maintain user object code compatibility The MC68EC040 assists the emulation process by distinguishing unimplemented floating point instructions from other unimplemented F line instructions To aid emulation the effective address is calculated and saved in the format 4 stack frame This simplifies and speeds up the emulation process by eliminating the need for the emulation routine to determine the effective address and by providing information required to emulate the instruction on the exception stack frame in the supervisor address space However the fl
238. amming model data formats and types instruction set caches and the same as those described for the MC68L C040 in Appendix A MC68L C040 The MC68ECO040V programming model data formats and types and instruction set are the same as those described for the MC68EC040 in Appendix B MC68bECO040 However both devices contain additional features For the 68040 all differences that exist between the MC68L C040 and the 68040 as described in Appendix MC68L C040 also apply to the MC68040V For the MC68ECOA0V all differences that exist between the MC68EC040 and the MC68040 as described in Appendix 68 040 also apply to the MC68ECO40V Both devices operate to 0 Hz and can accept 3 3V or 5V input Both devices have a new processor status state low power stop mode indicated when 5 3 0 6 There is no PCLK or TRST pin on either device Both devices provide three new pins system clock disable SCD low frequency operation LFO and loss of clock LOC C 1 ADDITIONAL SIGNALS Table C 1 lists the additional signals and Figure C 1 illustrates the functional signal groups of the MC68040V and MC68ECO040V MOTOROLA M68040 USER S MANUAL C 1 Table 1 Additional MC68040V MC68bECO040V Signals Low Frequency LFO Used to enter the low frequency mode of operation Operation Loss of Clock Indicates loss of BCLK input a reset is required System Clock Disable SCD Indicates normal operation i
239. an example of snooping in which memory is allowed to respond Best case timing is MOTOROLA M68040 USER S MANUAL 7 61 illustrated which results in a memory access having the equivalent of two wait states Variations in the timing required by snooping logic to access the caches can delay the negation of MI by up to two additional clocks External logic must ensure that the termination signals negate at all rising BCLK edges in which MI is asserted Otherwise if one of the termination signals is asserted either the M68040 ignores all termination signals reading them as negated or the M68040 exhibits improper operation BCLK BR l l AM_BG ALTERNATE MASTER indicates the alternate bus master Undefined Figure 7 41 Snoop Access with Memory Response 7 62 M68040 USER S MANUAL MOTOROLA 7 9 3 Snoop Read Cycle Intervention Required If snooping is enabled for a read access and the corresponding data cache line contains dirty data the M68040 inhibits memory and responds to the access as a slave device to supply the requested read data Intervention in a byte word or long word access is independent of which long word entry in the cache line is dirty Figure 7 42 illustrates an alternate bus master line read that hits a dirty line in the M68040 data cache The processor asserts TA to acknowledge the transfer of data to the alternate bus m
240. and synchronizes some portions of the processor before execution 10 28 M68040 USER S MANUAL MOTOROLA 10 7 FLOATING POINT UNIT INSTRUCTION TIMINGS For floating point instructions in the MC68040 the integer pipeline passes the decoded instruction to the floating point unit for execution then supports the floating point unit by calculating effective addresses and transferring operands to and from this unit For these instructions the execution times listed in the integer unit timing section show the overhead required by the integer unit to support the floating point unit assuming the floating point unit is not busy with the previous floating point instructions Times in parentheses are the total time that that stage uses to execute an instruction even though the stage can pass data to the next stage early The order of operands is generally not significant for timing purposes Different rounding modes i e round to zero etc never incur time penalty Instructions with an S or D e g FSADD have the same effect as setting the rounding precision to S or D All FMOVEM instructions wait for the pipe to idle before starting Refer to Section 9 Floating Point Unit MC68040 Only for details on the operation of the floating point unit pipeline 10 7 1 Miscellaneous Integer Unit Support Timings FBcc Taken if 5 Not Taken FDBcc cc True 1 7 cc False E 9 FNOP FPU Idle MOTOROLA M68040 USER S MANUAL 10 29 10 7 2 Integer Unit
241. ars T1 and TO The processor generates a vector number according to the instruction being executed Vector 5 is for DIVx vector 6 is for and and vector 7 is for FTRAPcc TRAPcc and instructions For the TRAP n instruction the vector number is 32 plus n The stack frame saves the trap vector offset the PC and the internal copy of the SR on the supervisor stack The saved value of the PC is the logical address of the instruction following the instruction that caused the trap For all instruction traps other than a pointer to the instruction 8 8 M68040 USER S MANUAL MOTOROLA that caused the trap is also saved Instruction execution resumes at the address the exception vector after the required instruction is prefetched 8 2 4 Illegal Instruction and Unimplemented Instruction Exceptions An illegal instruction exception corresponds to vector number 4 and occurs when the processor attempts to execute an illegal instruction An illegal instruction is an instruction that contains any bit pattern that does not correspond to the bit pattern of a valid M68040 instruction An illegal instruction exception is also taken after a breakpoint acknowledge bus cycle is terminated either by the assertion of the transfer acknowledge TA or the transfer error acknowledge TEA signal An illegal instruction exception can also be a MOVEC instruction with an undefined register specification field in the first extension wo
242. ass 010 or 000 register to register or memory to register instructions and opclass 011 register to memory instructions defined for the use by the supervisor exception handler 9 30 M68040 USER S MANUAL MOTOROLA field of the floating point state frame be used to determine the instruction that caused of the OPERR exception Note that CMDREG1B could be any of the instructions listed in Table 9 11 If the destination is a floating point data register this exception handler needs to supply the contents If the destination is memory the effective address is supplied in the format 3 stack frame If the destination is an integer data register the FPIAR points to the F line instruction word that contains the integer data register number To exit the user OPERR exception handler the saved floating point frame need not be restored and can be discarded prior to execution of the RTE instruction 9 7 4 Overflow An overflow exception is detected for arithmetic operations in which the destination is a floating point data register or memory when the intermediate result s exponent is greater than or equal to the maximum exponent value of the selected rounding precision Overflow can only occur when the destination is in the single double or extended precision format all other data format overflows are handled as operand errors At the end of any operation that could potentially overflow the intermediate result is checke
243. aster and the data bus is driven with the four long words of data for the line The timing illustrated is for a best case response time Variations in the timing required by snooping logic to access the caches can delay the assertion of TA by up to two additional clocks 7 9 4 Snoop Write Cycle Intervention Required If snooping with sink data is enabled for a byte word or long word write access and the corresponding data cache line contains dirty data the M68040 inhibits memory and responds to the access as a slave device to read the data from the bus and update the data cache line The dirty bit is set for the long word changed in the cache line Figure 7 48 illustrates a long word write by an alternate bus master that hits a dirty line in the M68040 data cache The processor asserts TA to acknowledge the transfer of data from the alternate master and the processor reads the value on the data bus The timing illustrated is for a best case response time Variations in the timing required by snooping logic to access the caches can delay the assertion of TA by up to two additional clocks MOTOROLA M68040 USER S MANUAL 7 63 C9 C8 C7 C6 C5 C4 C3 C2 Cl BCLK TER x CL Eo A we ees Seem oO TESNE ERE WON eee PRSE E RAS o 72 9 at
244. at the M68040FPSP implements for the MC68040 New instructions have been added to the MC68881 MC68882 base instructions Table E 2 M68040FPSP Floating Point Instructions 25506 Epsum Eoo fo Seems _____ FADD FSADD t FDADD t FMUL FSMUL t FDMUL t FINT FABS FGETEXP FTST FREM FMOVE FDMOVE FSSQRT FMOD FDMOD gt dd Single Precision Add Double Precision Add Multiply Single Precision Multiply Double Precision Multiply Integer Part Absolute Value Get Exponent Test Operand IEEE Remainder Move FP Data Register Double Precision Move Single Precision Square Root Modulo Remainder Double Precision Modulo Remainder 2 o o 2 2 2 2 o 2 o The MC68040 provides these functions for all data formats except single double and extended denormalized data types and extended unnormalized data types The M68040FPSP provides the functions for the special data types TAdditional functions not provided by the MC68881 MC68882 MOTOROLA M68040 USER S MANUAL E 3 Table E 3 lists all the data formats and types supported by the MC68040 FPU Also included are the data formats and types that the MC68040 FPU does not support but that are supported by the M68040FPSP Table E 3 Support for Data Types and Data Formats Data Formats Data Types EXT Byte Long Word ecol t ot t
245. at the processor takes is undetermined because the processor can internally decide to perform another active bus cycle indeterminate condition External bus arbiters must consider this indeterminate condition when negating BG and must be designed to examine the state of BB immediately after negating BG to determine whether or not the processor will run another bus cycle A somewhat dangerous situation exists when the processor begins a locked transfer after the bus has been granted to the alternate bus master causing the alternate bus master to perform a bus transfer during a locked sequence To correct this situation the external bus arbiter must be able to recognize the possible indeterminate condition and reassert BG to the processor when the processor begins a locked sequence The indeterminate condition is most significant when dealing with systems that cannot allow locked transfers to be broken Figure 7 31 illustrates an example of an error condition that is a consequence of the interaction between the indeterminate condition and a locked transfer External bus arbiters must be designed so that all bus grants to all bus masters be nagated for at least one rising edge of BCLK between bus tenures preventing bus conflicts resulting from the above conditions 7 48 M68040 USER S MANUAL MOTOROLA 040 BG i A f 040 EX fs 1 1 1 040 TS N i l 040 N 040 LOCK N AM BB 1 75 N
246. ate result is checked for underflow rounded and checked for overflow before it is stored at the destination If an underflow occurs the UNFL bit is set in the FPSR EXC byte Even if the intermediate result is large enough to be represented as an extended precision number an underflow can occur The intermediate result is rounded to the selected precision and the rounded result is stored in extended precision format If the magnitude of the intermediate result is too small to be represented in the selected rounding precision an underflow occurs The IEEE 754 standard defines two causes of an underflow 1 when the absolute value of the number is less than the minimum number that can be represented by a normalized number in a specific data format 2 when loss of accuracy occurs while attempting to calculate such a number a loss of accuracy also causes an inexact exception The IEEE 754 standard specifies that if the underflow exception is disabled an underflow should only be signaled when both of these cases are satisfied i e the result is too small to be represented with a given format and there is a loss of accuracy during calculation of the MOTOROLA M68040 USER S MANUAL 9 33 final result If the exception is enabled the underflow should be signaled any time a very small result is produced regardless of whether accuracy is lost in calculating it The processor UNFL bit in the FPSR byte implements the IEEE exception disabled
247. ating point concepts i e the unordered condition An unordered condition occurs when one or both of the operands in a floating point compare operation is a NAN The inclusion of the unordered condition in floating point branches destroys the familiar trichotomy relationship greater than equal less than that exists for integers For example the opposite of floating point branch greater than FBGT is not floating point branch less than or equal FBLE Rather the opposite condition is floating point branch not greater than FBNGT If the result of the previous instruction was unordered FBNGT is true whereas both FBGT and FBLE would be false since unordered fails both of these tests and sets BSUN Compiler programmers should be MOTOROLA M68040 USER S MANUAL 9 17 particularly careful of the lack of trichotomy in the floating point branches since it is common for compilers to invert the sense of conditions When using the IEEE nonaware tests the user receives a BSUN exception whenever a branch is attempted and the NAN condition code bit is set unless the branch is an FBEQ or an FBNE If the BSUN exception is enabled in the FPCR the exception causes another exception Therefore the IEEE nonaware program is interrupted if an unexpected condition occurs Compilers and programmers who are knowledgeable of the IEEE 754 standard should use the IEEE aware tests in programs that contain ordered and unordered conditions Since the ordered or
248. ation Next the M68040FPSP OPERR exception handler checks to see if the user OPERR exception handler is enabled a If the user OPERR exception handler is disabled an exception causing INEX1 or INEX2 condition exists and the user INEX exception handler is enabled The M68040FPSP OPERR exception handler restores the FPU to its exceptional state cleans up the stack to the conditions prior to execution and continues instruction execution at the user INEX exception handler No parameters are passed to the user INEX exception handler since the M68040FPSP OPERR exception handler provides the illusion that it never existed Otherwise the M68040FPSP OPERR exception handler returns the processor to normal processing b If the user OPERR exception handler is enabled and the destination is a floating point data register then the M68040FPSP exception handler does not modify the register The M68040FPSP OPERR exception handler restores the FPU to its exceptional state cleans up the stack to the conditions prior to execution and continues instruction execution at the user OPERR exception handler No parameters are passed to the user OPERR exception handler since the M68040FPSP OPERR exception handler provides the illusion that it never existed The user exception handler must execute an FSAVE as its first floating point instruction Table 9 16 lists the floating point state frame fields for OPERR exceptions resulting from the execution of opcl
249. atus and the faulted access the stack frame also contains pending write backs that the access error exception handler must complete The following paragraphs describe in detail the format for this frame and how the processor uses it when returning from exception processing Stack Frames Exception Types Stacked PC Points To Data Instruction Access Next Instruction STATUS REGISTER Fault ATC Fault or Bus Error PROGRAM COUNTER 0111 VECTOR OFFSET EFFECTIVE ADDRESS EA SPECIAL STATUS WORD SSW 00 WRITE BACK 3 STATUS WB35 00 WRITE BACK 2 STATUS WB25 00 WRITE BACK 1 STATUS WB1S FAULT ADDRESS FA WRITE BACK 3 ADDRESS WB3A WRITE BACK 3 DATA WB3D WRITE BACK 2 ADDRESS WB2A WRITE BACK 2 DATA WB2D WRITE BACK 1 ADDRESS WB1A WRITE BACK 1 DATA PUSH DATA WB1D PD0 PUSH DATA LW 1 PD1 PUSH DATA LW 2 PD2 PUSH DATA LW 3 PD3 ACCESS ERROR STACK FRAME 30 WORDS FORMAT 7 8 4 6 1 EFFECTIVE ADDRESS The effective address contains address information when one of the continuation flags CM CT CU or CP in the SSW is set 8 4 6 2 SPECIAL STATUS WORD SSW The SSW information indicates whether an access to the instruction stream or the data stream or both caused the fault and contains status information for the faulted access Figure 8 7 illustrates the SSW format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Figure 8 7
250. ble 11 1 to calculate other power dissipation values The ambient temperature results illustrate the need to implement some type of thermal management to obtain a reasonable maximum ambient temperature Table 11 2 Thermal Parameters with No Heat Sink or Airflow m Defined Parameters Calculated Oca Ta Ty Pp xc 68040 ss s ze ws 02 ws ss ze 1s 2 s sc 26 ws o mo MC68LC040 and MC68EC040 uc zs wa MOTOROLA M68040 USER S MANUAL 11 17 11 9 2 Forced Air In this study a small sample of MC68040 packages was tested in forced air cooling in a wind tunnel with no heat sink The test was performed with approximately 6 W of power being dissipated from within the package As previously mentioned since the variance in within the possible power range is negligible it can be assumed for calculation purposes that is constant at all power levels Using the previous equations Table 11 3 lists the results of the maximum power dissipation at maximum with airflow and heat sink for the MC68040 and Table 11 4 lists the results for the MC68LC040 and 68 040 Refer to Table 11 1 for calculating other power dissipation values Table 11 3 Thermal Parameters with Forced Airflow and No Heat Sink for the MC68040 Thermal Mgmt Def Measured Calculated Tech
251. bus cycle Waiting for processor 2 to run a bus cycle can result in a temporary bus arbitration lockup This bus arbitration scheme is restricted if the system supports the relinquish and retry operation that can occur for the last write cycle of a locked transfer In this case LOCKE cannot be used Assuming that LOCKE is always negated excludes the need for LOCKE in an arbitration similar to this example The reason for this restriction is that the external bus arbiter gives up the bus to the other processor once LOCKE is asserted If a relinquish and retry operation were to occur then the next bus cycle would be from the other processor violating the integrity of the locked transfer 7 8 2 2 DUAL M68040 PRIORITIZED ARBITRATION This example is very similar to the dual M68040 fairness arbitration example except that one processor is assigned higher priority over the other Processor 2 can own the bus only if there are no processor 1 pending requests It is important to note that when the processor asserts the LOCK signal it also asserts BR1 This implementation replaces LOCK with BR because BR is more demanding than using LOCK Only when processor 2 is in the middle of a locked operation does it have higher priority than processor 1 Similar to the M68040 fairness arbitration example the restriction on using LOCKE applies to this example Figure 7 36 illustrates the state diagram for dual M68040 prioritized arbitration 7
252. chanisms to assist in maintaining cache coherency in multimaster systems Both write through and copyback memory update techniques are supported to maintain coherency between the data cache and memory Alternate bus master accesses can reference data that the M68040 caches causing coherency problems if the accesses are not handled properly The M68040 snoops the bus during alternate bus master transfers If a write access hits in the cache the M68040 can update its internal caches or if a read access hits it can intervene in the access to supply dirty data Caches can be snooped even if they are disabled The alternate bus master controls snooping through the snoop control signals indicating which access can be snooped and the required operation for snoop hits Table 4 1 lists the requested snoop operation for each encoding of the snoop control signals Since the processor and the bus snooper must both access the caches the snoop controller has priority over the processor for snoopable accesses to maintain cache coherency Table 4 1 Snoop Control Encoding Requested Snoop Operation SC1 SCO Alternate Bus Master Read Access Alternate Bus Master Write Access pgs Inhibit Snooping Inhibit Snooping Supply Dirty Data and Leave Dirty Data Sink Byte Word Long Long Word 50 Supply Dirty Data and Mark Line Invalid Invalidate Line Reserved Snoop Inhibited Reserved Snoop Inhibited The snooping protocol and caching mechanism supported by the
253. ck for multiple exceptions The address of the exception handler is derived from the vector number corresponding to the exception The following is a list of multiple instruction exceptions that can occur SNAN and INEX1 OPERR and INEX2 OPERR and INEX1 OVFL and INEX2 and or INEX1 UNFL and 2 and or INEX1 9 7 1 Branch Set On Unordered BSUN The BSUN exception is the result of performing an IEEE nonaware conditional test associated with the FBcc FDBcc FTRAPcc and FScc instructions when an unordered condition is present Refer to 9 5 2 Conditional Testing for information on conditional tests MOTOROLA M68040 USER S MANUAL 9 25 If floating point exception is pending from a previous floating point instruction a instruction exception is taken After the appropriate exception handler is executed the conditional instruction is restarted When the FPU pipeline is idle all previous floating point instructions have completed and no exceptions are pending the processor evaluates the conditional predicate and checks for a BSUN exception before executing the conditional instruction 9 7 1 1 MASKABLE EXCEPTION CONDITIONS A BSUN exception occurs if the conditional predicate is one of the IEEE nonaware branches and the FPCC NAN bit is set When the processor detects this condition it sets the BSUN bit in the FPSR EXC byte a If the user BSUN exception handler is disabled the floating point condition is evaluate
254. ction execution resumes after the required prefetches for the interrupt handler routine Most M68000 family peripherals use programmable interrupt vector numbers as part of the interrupt acknowledge operation for the system If this vector number is not initialized after reset and the peripheral must acknowledge an interrupt request the peripheral usually returns the vector number for the uninitialized interrupt vector 15 MOTOROLA M68040 USER S MANUAL 8 15 T1 TO 12 10 FETCH FROM INT DE IF NO VECTOR AUTOVECTOR 25 31 IF M 0 THEN VECTOR OFFSET PC AND SR b ACTIVE STACK FRAME VECTO ENTRY SAVE INTERNAL COPY OF SR 5 1 00 LEVEL OF INTERUPT VECTOR ERRUPTING VICE BUS ERROR SPURIOUS INTERRUPT VECTOR 224 OTHERWISE 0 VECTOR OFFSET PC AND SR THROWAWAY STACK FRAME ON BUS ERROR PREFETCH FOUR LONG WORDS OTH BEGIN IN EXEC ERN ERWISE STRUCTION UTION BUS ERROR OR ADDRESS ERROR EXIT Figure 8 4 Interrupt Exception Processing Flowchart 8 16 M68040 USER S MANUAL ISP DOUBLE BUS FAULT HALTED STATE PST3 PSTO 5 MOTOROLA 8 2 10 Reset Exception Asserting the reset in RSTI input signal causes a reset exception The reset exception has the highest priority of any exception it provides for system initialization and recovery from catastrophic failure Reset also aborts any
255. ction shift register TEST DATA REGISTERS 184 BIT BOUNDARY SCAN REGISTER 55 LATCHED DECODER Ao eoo 3 BIT INSTRUCTION SHIFT REGISTER TDI Figure 6 1 M68040 Test Logic Block Diagram 6 2 M68040 USER S MANUAL MOTOROLA 6 2 INSTRUCTION SHIFT REGISTER The M68040 IEEE standard 1149 1A implementation includes a 3 bit instruction shift register without parity The register shifts one of eight instructions which can either select the test to be performed or access a test data register or both Data is transferred from the instruction shift register to latched decoded outputs during the update IR state The instruction shift register is reset to all ones in the TAP controller test logic reset state which is equivalent to selecting the BYPASS instruction During the capture IR state the binary value 001 is loaded into the parallel inputs of the instruction shift register The M68040 IEEE standard 1149 1A implementation includes three mandatory public instructions BYPASS SAMPLE PRELOAD and EXTEST and four manufacturer s public instructions The four manufacturer s public instructions provide the capability to disable all device output drivers operate the device in a BYPASS configuration without a system clocking requirement and select one of two output drive capabilities on a pin by pin basis The M68040 implementation does not support the optional standard public instructions
256. d In the instruction timing tables the lt ea gt calculate column lists the number of clocks required for the instruction to execute in the lt ea gt calculate stage of the integer unit pipeline Dual effective address instructions such as ABCD require two calculations in the lt ea gt calculate stage and two memory fetches Due to pipelining the fetch of the first operand occurs in the same clock as the lt ea gt calculation for the second operand The execute column lists the number of clocks required for the instruction to execute in the execute stage of the integer unit pipeline This number is presented as a lead time and a base time The lead time is the number of clocks the instruction can stall when entering the execution stage without delaying the instruction execution If the previous instruction is still executing in the execution stage when the current instruction is ready to move from the lt ea gt fetch stage the current instruction stalls until the previous one completes For MOTOROLA M68040 USER S MANUAL 10 3 example if an execution time is listed as 21 1 the lead time is two clocks and the base time is one for a total execution time of three The instruction can stall for two clocks without delaying the instruction execution time The ea calculate and execute stages operate in an interlocked manner for all instructions using the brief and full extension word formats If an instruction usin
257. d TEA causes the bus controller to retry the bus cycle However a retry signaled during the remaining cycles of the line access either burst or pseudo burst is recognized as a bus error and the processor handles it as described in the previous paragraphs A cache inhibit or bus error on a line read can change the state of the line being replaced even though the new line is not copied into the cache Before loading a new line the cache line being replaced is copied to the push buffer if it is dirty the cache line is invalidated If a cache inhibit or bus error occurs on a replacement line read a dirty line is restored to the cache from the push buffer However the line being replaced is not restored in the cache if it was originally valid and the cache line remains invalid If the line 4 12 M68040 USER S MANUAL MOTOROLA read resulting from write miss copyback mode is cache inhibited the write access misses in the cache and writes through to memory 4 6 2 Cache Pushes When the cache controller selects a dirty data cache line for replacement memory must be updated with the dirty data before the line is replaced This occurs when a CPUSH instruction execution explicitly selects the cache and when a cache inhibit access hits in the cache To reduce the requested data s latency in the new line the dirty line being replaced is temporarily placed in a push buffer while the new line is fetched from memory When line is allocated to
258. d Vcc 2 5V RSTI is internally synchronized for two BCLKs before being used and must meet the specified setup and hold times to BCLK specifications 51 and 52 in C 7 MC68040V and MC68ECO40V Electrical Characteristics only if recognition by a specific BCLK rising edge is required MI is asserted while the MC68040V is in reset MOTOROLA M68040 USER S MANUAL C 7 210 gt lt 2 gt lt 128 gt CLOCKS CLOCKS CLOCKS CDIS MDIS IPL2 IPLO BUS i SIGNALS B 15 I N 1 1 Undefined NOTE Not on MC68ECO040V Figure C 2 MC68040V and MC68ECO40V Initial Power On Reset Timing Once RSTI negates the processor is internally held in reset for another 124 clocks maximum During the reset period all signals that can be are three stated and the rest are driven to their inactive state Once the internal reset signal negates all bus signals continue to remain in a high impedance state until the processor is granted the bus Afterwards the first bus cycle for reset exception processing begins Figure C 2 illustrates that the processor assumes implicit bus ownership before the first bus cycle begins For processor resets after the initial power on reset RSTI should be asserted for at least 10 clock periods The Figure C 3 illustrates timings a
259. d as if it were the equivalent IEEE aware conditional predicate No exceptions are taken b If the user BSUN exception handler is enabled the processor takes a floating point pre instruction exception A 0 stack frame is saved and vector number 48 is generated to access the BSUN exception vector The BSUN entry in the processor s vector table points to the M68040FPSP BSUN exception handler For MC68881 MC68882 compatibility the M68040FPSP updates the FPIAR by copying the PC value in the pre instruction stack frame to the FPIAR The M68040FPSP BSUN exception handler restores the FPU to its exceptional state cleans up the stack to the state prior to the M68040FPSP BSUN exception handler s execution and continues instruction execution at the user BSUN exception handler No parameters are passed to the user BSUN exception handler since the M68040FPSP BSUN exception handler provides the illusion that it never existed The user BSUN exception handler must execute an FSAVE as its first floating point instruction FSAVE allows other floating point instructions to execute without reporting the BSUN exception again although none of the state frame values are useful in the execution of the user BSUN exception handler The BSUN exception is unique in that the exception is taken before the conditional predicate is evaluated If the user BSUN exception handler does not set the PC to the instruction following the one that caused BSUN exception when returning
260. d for underflow rounded and then checked for overflow before it is stored to the destination If overflow occurs the OVFL bit is set in the FPSR EXC byte Even if the intermediate result is small enough to be represented as an extended precision number an overflow can occur The intermediate result is rounded to the selected precision and the rounded result is stored in the extended precision format If the magnitude of the intermediate result exceeds the range of the selected rounding precision format an overflow occurs 9 7 4 1 MASKABLE EXCEPTION CONDITIONS There are no conditions 9 7 4 2 NONMASKABLE EXCEPTION CONDITIONS When the OVFL bit is set in the FPSR EXC byte as a result of a floating point instruction the processor always takes a nonmaskable overflow exception If the destination is a floating point data register then the register is not affected and either a pre instruction or a post instruction exception is reported If the destination is a memory or integer data register an undefined result is stored and a post instruction exception is taken immediately Execution begins at the M68040FPSP OVFL exception handler The values defined in Table 9 12 are stored in the destination based on the rounding mode defined in the FPCR MODE byte The M68040FPSP OVFL exception handler rounds the result according to the rounding precision defined in the FPCR MODE byte if the destination is a floating point data register If the destination
261. d memory management subsystems This supervisor user distinction in the M68000 family architecture allows for the writing of application software that executes in the user mode and migrates to the MC68040 from any M68000 family platform without modification The supervisor programming model contains the control features that system designers need to modify system software when porting to a new design For example only the supervisor software can read or write to the transparent translation registers of the MC68040 The existence of the transparent translation registers does not affect the programming resources of user application programs DATA REGISTERS FLOATING POINT DATA REGISTERS ADDRESS REGISTERS MOTOROLA AT IISP AT MSP SR VBR SFC DFC CACR URP SRP TC DTTO 0 1 ITTO MMUSR FP INSTRUCTION ADDRESS REGISTER FP CONTROL REGISTER FP STATUS REGISTER USER STACK POINTER PROGRAM COUNTER CONDITION CODE REGISTER USER PROGRAMMING MODEL INTERRUPT STACK POINTER MASTER STACK POINTER STATUS REGISTER CCR IS ALSO SHOWN IN THE USER PROGRAMMING MODEL VECTOR BASE REGISTER SOURCE FUNCTION CODE DESTINATION FUNCTION CODE CACHE CONTROL REGISTER USER ROOT POINTER REGISTER SUPERVISOR ROOT POINTER REGISTER TRANSLATI ON CONTROL REGISTER DATA TRANSPARENT TRANSLATIO
262. d required for external accelerators The MC68040 FPU operates in parallel with the integer unit IU The FPU does the numeric calculation while the IU moves on to other tasks Like the IU the FPU has its own three stage pipeline overlapping operations such as integer to floating point conversion instruction execution and write back When used with the M68040FPSP the MC68040 FPU is fully compliant with IEEE floating point standards 9 1 FLOATING POINT UNIT PIPELINE Integer data from memory memory to register requires a pass through the FPU pipeline converting the data to the extended precision format for the FPU to use The result of this conversion is presented to the conversion stage of the FPU pipeline where the desired operation begins starting a second pass through the pipeline The IU is then released to execute other instructions once the data has been transferred to the FPU Floating point data to memory register to memory requires a complete pass through the FPU pipeline converting the data from the extended precision format to an integer data format Register to memory instructions are normally handled entirely by the conversion stage of the pipeline where the data move to memory operation completes The IU is not released until it has received the converted data during the last conversion unit cycle Like the IU the FPU has been optimized for the most frequently used instructions and data types to provide the highest possibl
263. d to BCLK eeu Rp Hold ru eee s bum z BCLK to Address SIZx R W SCx Invalid Hold a mamon Peet Processor Assumes Bus Mastership P RR change 5 _ PEND Px ___ o pulse width eama mode 10 IPO FET vad IFO change so so NOTE on the MC68ECO40V MOTOROLA M68040 USER S MANUAL C 23 A31 A0 TRANSFER ATTRIBUTES TS TIP D31 D0 IN READ D31 D0 OUT WRITE TA TEA TCI TBI NOTE Transfer Attribute Signals UPAx SIZx TTx TMx TLNx R W LOCK LOCKE CIOUT Figure C 13 Read Write Timing C 24 M68040 USER S MANUAL MOTOROLA 1 0 TRANSFER ATTRIBUTES LOCK LOCKE TIP D31 D0 OUT WRITE BR lt 6 gt 2 lt gt ce 00 41 lt gt M NOTE Transfer Attribute Signals UPAx SIZx TTx TMx TLNx R W CIOUT MOTOROLA Figure C 14 Bus Arbitration Timing M68040 USER S MANUAL 25 R W IN TS D31 D0 ALT MASTER 7
264. dd branch offset that is not taken A prefetch bus cycle is not executed and the processor begins exception processing after the currently executing instructions have completed If the completion of these instructions generates another exception the address error exception is deferred and the new exception is serviced After exception processing for the address error exception commences the sequence is the same as an access fault exception except that the vector number is 3 and the vector offset in the stack frame refers to the address error vector The stack frame is generated containing the address of the instruction that caused the address error and the address itself AO is cleared If an address error occurs during the exception processing for a bus error address error or reset a double bus fault occurs 8 2 3 Instruction Trap Exception Certain instructions are used to explicitly cause trap exceptions The TRAP n instruction always forces an exception and is useful for implementing system calls in user programs The TRAPcc FTRAPcc TRAPV CHK and CHK2 instructions force exceptions if the user program detects an error which can be an arithmetic overflow or a subscript value that is out of bounds The DIVS and DIVU instructions force exceptions if a division operation is attempted with a divisor of zero As illustrated in Figure 8 1 when a trap exception occurs the processor internally copies the SR enters the supervisor mode and cle
265. dentifies a modified page The M68040 sets the M bit in the corresponding page descriptor before a write operation to a page for which the M bit is clear except for write protect or supervisor violations The read portion of a read modify write access is considered a write for updating purposes The M68040 never clears this bit PDT Page Descriptor Type This field identifies the descriptor as an invalid descriptor a page descriptor for a resident page or an indirect pointer to another page descriptor 00 Invalid This code indicates that the descriptor is invalid An invalid descriptor can represent a nonresident page or a logical address range that is out of bounds All other bits in the descriptor are ignored When an invalid descriptor is encountered an ATC entry is created for the logical address with the resident bit in the MMUSR clear Resident These codes indicate that the page is resident Indirect This code indicates that the descriptor is an indirect descriptor Bits 31 2 contain the physical address of the page descriptor This encoding is invalid for a page descriptor pointed to by an indirect descriptor Physical Address This 20 bit field contains the physical base address of a page in memory The logical address supplies the low order bits of the address required to index into the page When the page size is 8 Kbyte the least significant bit of this field is not used S Supervisor Protected This bit identifies
266. des changed for SAMPLE SHUTDOWN and BYPASS New instructions DRVCTL T DRVCTL S and PRIVATE added New instructions DRVCTL T and DRVCTL S renamed to DRVCTL T and Register access specified for DRVCTL T DRVCTL 5 and PRIVATE instructions This BSDL is for the newer MC68040 mask sets of E26A and after roughly after the second half of 1992 It does not include the 0 8 um mask sets D43B D50D and D98D For MC68LC040 and 68 040 two pin names have changed To make the necessary modifications change all occurrences of DLE to JS0 and vi entity MC68040 is generic PHYSICAL PIN MAP string PGA 18x18 port TDI in bit TDO out bit TMS in bit TCK in bit TRST in bit RSTO buffer bit IPEND buffer bit CIOUT out bit UPA out bit vector O to 1 TT inout bit vector O to 1 A inout bit vector O to 31 D inout bit vector O to 31 LOCKE out bit LOCK out bit R W inout bit TLN out bit_vector 0 to 1 TM out bit_vector 0 to 2 SIZ inout bit_vector 0 to 1 buffer BR buffer TS inout bit BB inout bit TIP out bit PST buffer bit vector O to 3 TA inout bit TEA in bit BG in bit SC in bit vector O to 1 TBI in bit AVEC in bit TCI in bit MOTOROLA M68040 USER S MANUAL D IS to JS1 6 15 BCLK IPL RSTI CDIS MDIS EGND EVDD IGND IVDD CGND CVDD PGND PVDD in bit in bit in bit in bit vec
267. devices connected to the RSTO signal are reset at the completion of the RESET instruction An RSTI signal that is asserted to the processor during execution of a RESET instruction immediately resets the processor and causes the RSTO signal to negate RSTO can be logically ANDed with the external signal driving RSTI to derive a system reset signal that is asserted for both an external processor reset and execution of a RESET instruction It is necessary that the MC68040V and MC68bECO040V be powered up before other 5V devices because the two power supplies must be within 2 5V of each other C 5 POWER CYCLING In cases were power is cycled off then on with a duration of one second RESET must be asserted prior to removing power This allows for an orderly shutdown within the 68040 and enables circuitry for the subsequent power up MOTOROLA M68040 USER S MANUAL C 9 C 6 MC68040V AND MC68ECO40V JTAG PRELIMINARY The MC68040V and MC68ECO40V include dedicated user accessible test logic that is fully compatible with the IEEE standard 1149 1A Standard Test Access Port and Boundary Scan Architecture Problems associated with testing high density circuit boards have led to the standard s development under the sponsorship of the IEEE Test Technology Committee and the Joint Test Action Group JTAG The following paragraphs are to be used in conjunction with the supporting IEEE document and includes those chip specific items that the IEEE
268. driving bus MC68040V Typical Values Vcc 3 3 V Ty TBD C Normal Operation This information is for system reliability purposes C 20 M68040 USER S MANUAL MOTOROLA C 7 5 Clock AC Timing Specifications see Figure C 12 PRELIMINARY PRELIMINARY 0 1667MHz 25MHz 33MHz amp S aes _ 1667 1667 5 wer ss s sukmeawrame 2 s s a 5 5 ss s Puse wan High 15 285 22 1666 mz Buk Puse With Low Measwedat 285 22 es 1666 rs 1 NOTES 1 Rising and falling edges of BCLK must be monotonic 2 Specification value at maximum frequency of operation BCLK must not exceed 16 67 MHz for low frequency operation BCLK Figure C 12 Clock Input Timing Diagram MOTOROLA M68040 USER S MANUAL C 21 C 7 6 Output AC Timing Specifications see Figures 13 to C 21 PRELIMIINARY 0 16 67 MHz Characteristic BCLK to Address CIOUT LOCK LOCKE 11 PSTx R W SIZx TLNx TMx UPAx Valid w ojo NN BOLK io Data Out veld OupaHo Output Low impedance o BOLK EM
269. duas _ J 2 E ol ta MESS gt LLI gt lt n f z es 2 pon 2 5 z gt lt Cu m _ J Ale ole eX i Eee Ee iss HUI Rene DNI LL lt me TR 24 t emp ntm Pal e euma LL SC TENE SERM 4 oco 5 e ae Pie Riv SC Las waq at o lu p di E gt C c kuman 5 cd a x Q E a lt PROCESSOR ALTERNATE MASTER LINE READ M68040 USER S MANUAL lt indicates the alternate bus master Figure 7 42 Snooped Line Read Memory Inhibited 7 64 cs c BCLK l l RE 5121 5120 F 7 m TT TTO 1 MEMORY INHIBITED FROM RESPONDING 2 4 TA DRIVEN BY PROCESSOR TA 1 1 1 1 1 1 1 DATA WRITTEN BY ALTERNATE BUS MASTER 1
270. during processor reset which allows the data bus and address bus to be physically tied together for multiplexed bus applications The level on MDIS can select a data latch mode during processor reset which allows the memory interface to specify when the processor should latch input data through the DLE signal Section 7 Bus Operation provides detailed information about the relationship of the data bus to bus operation the multiplexed bus mode and the data latch mode Refer to Appendix MC68LC040 and Appendix 68 040 for details concerning the level and multiplexed bus mode 5 3 TRANSFER ATTRIBUTE SIGNALS The following paragraphs describe the transfer attribute signals which provide additional information about the bus transfer Refer to Section 7 Bus Operation for detailed information about the relationship of the transfer attribute signals to bus operation 5 3 1 Transfer Type TT1 TTO The processor drives these three state bidirectional signals to indicate the type of access for the current bus transfer During bus transfers by an alternate bus master the processor samples these signals to determine if it should snoop the transfer only normal and MOVE16 accesses can be snooped Table 5 2 lists the definition of the transfer type encoding The acknowledge access TT1 1 and TTO 1 is used for both interrupt and breakpoint acknowledge transfers and for LPSTOP broadcast cycles on the MC68040V and MC68E
271. e Number Title Number 8 5 Write Back Data Alignimelib ha ud 8 27 8 6 Access Error Stack Frame Combinations 8 31 9 1 Floating Point Control Register Encodings 9 3 9 2 MC68040 FPU Data Formats and Data 9 7 9 3 Single Precision Real Format 9 8 9 4 Double Precision Real Format 9 9 9 5 Extended Precision Real Format 9 10 9 6 Packed Decimal Real Format 9 11 9 7 Floating Point Condition Code Encodings 9 17 9 8 Floating Point Conditional 9 19 9 9 Floating Point Exception 9 20 9 10 Urnimplemented Instructions iit pr tem cer aee rane ets 9 21 9 11 Possible Operand Errors Exceptions 9 29 9 12 Overflow Rounding Mode Values 9 32 9 13 Underflow Rounding Mode 9 34 9 14 Possible Divide by Zero 9 36 9 15 Divide by Zero Rounding Mode 9 37 9 16 State Frame Field Info
272. e containing the required operand This half line is driven onto the internal bus If the required data is allocated entirely within the half line only one access into the cache is required Because the organization of the cache does not allow selection of more than one half line at a time misalignment across a half line boundary requires two accesses into the cache A snooped external read that hits in the cache is ignored if the cache line is valid If the snooped access hits a dirty line memory is inhibited from responding and the data is sourced from the cache directly to the alternate bus master A snooped read hit does not change the state of the cache line unless the snooped access also indicates mark invalid which causes the line to be invalidated after the access even if it is dirty Alternate bus masters should indicate mark invalid only for line reads to ensure the entire line is transferred before invalidating 4 4 4 Write Hit The cache controller handles processor writes that hit in the cache differently for write through and copyback pages For write through accesses a processor write hit causes the cache controller to update the affected long word entries in the cache line and to request an external memory write transfer to update memory The cache line state does not change A write through access to a line containing dirty data constitutes a system programming error even if the D bits for the line are unchanged This situation
273. e the effective address field in the format 3 stack frame is invalid The FMOVE OUT instruction generates a post instruction exception For this case the effective address field in the format 3 stack frame points to the destination memory location If the destination is an integer data register the FPIAR points to the F line word of the offending instruction and the F line word contains the integer data register number If the MC68040FPSP unimplemented instruction exception handler is used there can be some other cases in which an inexact exception is reported The user INEX exception handler examines the bit of the floating point state frame to exit from this exception handler If the E3 bit is set it must be cleared prior to restoring the floating point frame via the FRESTORE instruction If the E3 bit is clear and the E1 bit is set the floating point frame is discarded The RTE instruction must be executed to return to normal instruction flow NOTE The IEEE 754 standard specifies that inexactness should be signaled on overflow as well as for rounding The processor implements this via the INEX bit in the FPSR AEXC byte However the standard also indicates that the inexact exception should be taken if an overflow occurs with the OVFL bit disabled and the INEX bit enabled in the FPSR byte Therefore the processor takes the inexact exception if this combination of conditions occurs even though the INEX1 or INEX2 bit may n
274. e data MMU ITTO and ITT1 in the instruction MMU define four blocks of logical address space to be translated to physical address space These logical address spaces must be at least 16 Mbytes and can overlap or be separate Each TTR can be disabled and completely ignored The following description assumes that the TTRs are enabled When an MMU receives an address to be translated the privilege mode and the eight high order bits of the address are compared to the logical address spaces defined by the two TTRs for the corresponding MMU The logical address space for each TTR is defined by an S field logical base address field and logical address mask field The S field allows matching either user or supervisor accesses or both accesses When a bit in the logical address mask field is set the corresponding bit of the logical base address is ignored in the address comparison and privilege mode Setting successively higher order bits in the address mask increases the size of the physical address space The address for the current bus cycle and a TTR address match when the privilege mode and logical base address bits are equal Each TTR can specify write protection for the block When write protection is enabled for a block write or read modify write accesses to the block are aborted MOTOROLA M68040 USER S MANUAL 3 29 By appropriately configuring a TTR flexible transparent mappings be specified refer to 3 1 3 Transparent Translation Regis
275. e different on power up for the MC68LC040 and MC68EC040 4 These signals are not available on the MC68040V and MC68ECO040V Figure 5 1 Functional Signal Groups 5 1 ADDRESS BUS 1 0 These three state bidirectional signals provide the address of the first item of a bus transfer except for acknowledge transfers when the M68040 is the bus master When an alternate bus master is controlling the bus the processor examines snoops these signals to determine whether the processor should intervene in the access to maintain cache coherency The level on CDIS can select multiplexed bus mode during processor reset which allows the 5 4 address bus and data bus to be physically tied together for multiplexed bus M68040 USER S MANUAL MOTOROLA applications Refer to Section 7 Bus Operation for detailed information about the relationship of the address bus to bus operation and the multiplexed bus mode Refer to Appendix MC68LC040 and Appendix 68 040 for details concerning the level and multiplexed bus mode 5 2 DATA BUS 031 00 These three state bidirectional signals provide the general purpose data path between the M68040 and all other devices The data bus can transfer 8 16 or 32 bits of data per bus transfer During a burst transfer the data lines are time multiplexed to carry all 128 bits of the burst request using four 32 bit transfers The level on CDIS can select a multiplexed bus mode
276. e end of each arithmetic operation or move operation to a single floating point data register The condition code bits are consistently set based on the result of the operation Second the FPU supports 32 conditional tests that allow floating point conditional instructions to test floating point conditions in exactly the same way as the integer conditional instructions test the integer condition codes The combination of consistently set condition code bits and the simple programming of conditional instructions gives the MC68040 a very flexible high performance method of altering program flow based on floating point results While reading the summary for each instruction it should be assumed that an instruction performs postprocessing unless the summary specifically states that the instruction does not do so The following paragraphs describe postprocessing in detail MOTOROLA M68040 USER S MANUAL 9 15 9 5 1 Underflow Round Overflow During the calculation of an arithmetic result the FPU arithmetic logic unit ALU has more precision and range than the 80 bit extended precision format However the final result of these operations is an extended precision floating point value In some cases an intermediate result becomes either smaller or larger than can be represented in extended precision Also the operation can generate a larger exponent or more bits of precision than can be represented in the chosen rounding precision For these reasons eve
277. e format 4 stack frame contains the calculated effective address of the operand for the faulted floating point instruction using the addressing mode in which the effective address is calculated For immediate and register direct addressing modes this field is 0 The saved PC value is the logical address of the instruction that follows the unimplemented floating point instruction This value will be restored during RTE execution The vector offset format number 4 is used for this eight word stack frame Note that an MC68040 cannot correctly handle a stack format 4 The PC of the faulted instruction contains a long word PC of the floating point instruction that caused the trap to occur The information is provided so that the instruction is available for software emulation of floating point B 10 M68040 USER S MANUAL MOTOROLA instructions The processor generates exception vector number 11 for the unimplemented F line instruction exception vector fetches the address of the F line exception handler from the exception vector table and begins execution of the handler after prefetching instructions to fill the pipeline Refer to Section 8 Exception Processing for details about exception processing 5 2 68 040 Stack Frames When the processor executes an instruction it examines the stack frame on top of the active supervisor stack to determine if it is a valid frame and what type of context restoration it requires The set of stack
278. e lines to be in either the invalid or valid states For instruction prefetch requests that hit in the cache the half line selected by physical address bit 3 is multiplexed onto the internal instruction data bus When an access misses in the cache the cache controller requests the line containing the required data from memory and places it in the cache If available an invalid line is selected and updated with the tag and data from memory The line state then changes from invalid to valid by setting the V bit If all lines in the set are already valid a pseudo random replacement algorithm is used to select one of the four cache lines replacing the tag and data contents of the line with the new line information Figure 4 5 illustrates the instruction cache line state transitions resulting from processor and snoop controller accesses Transitions are labeled with a capital letter indicating the previous state followed by a number indicating the specific case listed in Table 4 3 I3 CINV CPUSH V1 CPU READ MISS V2 CPU READ HIT I1 CPU READ MISS V3 CINV CPUSH V5 SNOOP READ HIT V6 SNOOP WRITE HIT Figure 4 5 Instruction Cache Line State Diagram 4 14 M68040 USER S MANUAL MOTOROLA Table 4 3 Instruction Cache Line State Transitions Current State Cache Operation Invalid Cases Valid Cases replacing old line remain in CPU Read Miss Read line from memory Read line from memory supply supply data to CPU and data to CPU and
279. e on the tenth bus clock the MC68040V and 6 4 will begin normal reset processing C 6 4 Disabling The IEEE Standard 1149 1A Operation There are two considerations for non IEEE standard 1149 14 operation First does not include an internal pullup resistor and should not be left unconnected to preclude mid level inputs The second consideration is to ensure that the IEEE standard 1149 14 test logic remains transparent to the system logic by providing the ability to force the test logic reset state Figure C 10 illustrates a circuit to disable the IEEE standard 1149 14 test logic for the 68040 and MC68bECO40V C 16 M68040 USER S MANUAL MOTOROLA TV TDI TMS TCLK TDO NO CONNECTION Figure C 10 Circuit Disabling IEEE Standard 1149 1A C 6 5 MC68040V and MC68ECO40V JTAG Electrical Characteristics The following paragraphs provide information on JTAG electrical and timing specifications This section is subject to change For the most recent specifications contact a Motorola sales office or complete the registration card at the beginning of this manual JTAG DC Electrical Specifications PRELIMINARY Characteristic Input High Voltage Input Low Voltage Overshoot Input Leakage Current 0 5 2 4 V TDO Hi Z Off State Leakage Current 0 5 2 4 V Signal Low Input Current VIL 0 8 V TMS TDI Signal High Input Current 2 0 V TMS TDI Output High Voltage 5ma TDO Output
280. e performance To boost performance further the FMOVE instruction concurrently executes with arithmetic calculations and executes completely transparent to the user Instructions can execute nonsequentially as long as there are no register dependencies Refer to Section 10 Instruction Timings for details on floating point timings MOTOROLA M68040 USER S MANUAL 9 1 MC68040 FPU is compatible with the 68881 68882 The MC68040 performs basic math functions such as floating point addition and multiplication directly on dedicated circuitry and performs transcendental functions such as sine and cosine calculations by means of software routines Motorola offers the M68040FPSP a software package providing these routines The software functions are compatible with the MC68881 MC68882 refer to Appendix E Floating Point Emulation M68040FPSP 9 2 FLOATING POINT USER PROGRAMMING MODEL Figure 9 1 illustrates the floating point portion of the user programming model The following paragraphs describe the FPU portion of the user programming model for the MC68040 The model which is identical to the programming model for the MC68881 MC68882 floating point coprocessors consists of the following registers e Eight 80 Bit Floating Point Data Registers 7 16 Bit Floating Point Control Register FPCR 32 Bit Floating Point Status Register FPSR 32 Bit Floating Point Instruction Address Register FPIAR 0
281. e provides ordering information pertaining to the MC68040 MC68040V MC68LC040 MC68EC040 and MC68ECO040V package types frequencies temperatures and Motorola order numbers Package Type Frequency Maximum Junction Minimum Ambient Order Number Temperature Temperature Pin Grid Array 20 MHz 110 0 C MC68LC040RC20B RC Suffix MC68EC040RC20B Te MC68040RC25 2 25 MHz 110 C 0 C MC68LC040RC25B uffix MC68EC040RC25B MC68040RC25V MC68040RC33 ue 33 MHz 110 0 C MC68LC040RC33B uffix MC68ECO40RC33B MC68040RC33V 184 Pin QFP 410 C MC68LC040FE20B FE Suffix MC68ECO40FE20B MC68LC040FE25B 184 Pin QFP in Q 25 MHz 110 C 0 C MC68EC040FE25B FE Suffix MC68040FE25V MC68LC040FE33B 184 Pin QFP inQ 33 MHz 110 C 0 C MC68ECO40FE33B FE Suffix MC68040FE33V 12 2 PIN ASSIGNMENTS The following are the pin assignments for the MC68040 MC68040V MC68LC040 MC68ECO040 and MC68ECO040V package types MOTOROLA M68040 USER S MANUAL 12 1 12 2 1 MC68040 Pin Grid Array T O O O O O O O O 5 O TRST GND CDIS 2 IPLO DLE TCI AVEC SCO BG 570 PST3 BB BR S O GND TDI TMS MDIS RSTI Vcc GND GND TBI 5 1 TEA 1 GND Vcc GND LOCK R CIOUT Vcc RSTO GND Vcc GND PCLK GND GND Vcc GND PST2 TIP TS Vcc LOCKE Q UPA1
282. e read transfers The address of an instruction fetch will always be aligned to a half line boundary or XXXXXXX8 therefore compilers should attempt to locate branch targets on half line boundaries to minimize branch stalls For example if the target of a branch is a two word instruction located at 1000000C the following burst sequence will occur upon a cache miss 10000008 1000000C 10000000 then 10000004 The internal pipeline of the M68040 stalls until the second access of the burst the address of the instruction to be executed has completed Figures 7 10 and 7 11 illustrate a flowchart and functional timing diagram for a line read bus transfer MOTOROLA M68040 USER S MANUAL 7 13 PROCESSOR EXTERNAL DEVICE ADDRESS DEVICE SET R W TO READ DRIVE ADDRESS ON A31 A0 DRIVE USER PAGE ATTRIBUTES ON 1 UPAO DRIVE SIZE ON 5121 SIZO LINE DRIVE TRANSFER TYPE ON TT1 TTO DRIVE TRANSFER MODIFIER ON 2 0 CIOUT BECOMES VALID ASSERT TS FOR ONE CLOCK ASSERT TIP PRESENT DATA CO n gt 1 DECODE ADDRESS 2 PLACE DATA ON 031 00 3 ASSERT TA ACQUIRE DATA 1 LATCH DATA 2 SAMPLE TBI AND TCI FOR FIRST TRANSFER TERMINATE CYCLE 1 REMOVE DATA FROM D31 D0 2 NEGATE TA IF NECESSARY 3 INCREMENT ADDRESS BITS A2 IF NECESSARY WHEN FOUR LONG WORDS UNTIL FOUR LONG WORDS TRANSFERRED TRANSFERRED
283. e search algorithm never leaves a descriptor in this state This state is possible through direct manipulation by the operating system for this specific instance A table search for a MOVE16 write can corrupt the cache line being written if the table descriptors are marked copyback 3 2 2 Descriptors There are two types of descriptors used in the translation tables table and page Table and page level descriptors can be further divided into types of descriptors Root table descriptors are used in root level tables and pointer table descriptors are used in pointer level tables Descriptors in the page level tables contain either a page descriptor for the translation or an indirect descriptor that points to a memory location containing the page descriptor The P bit in the TCR selects the page size as either 4 or 8 Kbytes 3 2 2 1 TABLE DESCRIPTORS Figure 3 11 illustrates the formats of the root and pointer table descriptors Two descriptor formats are possible at the pointer level tables to support 4 Kbyte and 8 Kbyte page sizes 3 12 M68040 USER S MANUAL MOTOROLA 31 9 6 5 4 3 2 1 0 POINTER TABLE ADDRESS X ROOT TABLE DESCRIPTOR ROOT LEVEL 31 8 7 6 5 4 3 2 1 0 PAGE TABLE ADDRESS X 4K POINTER TABLE DESCRIPTOR POINTER LEVEL 3l 7 6 5 4 3 2 1 O PAGE TABLE ADDRESS 8K POINTER TABLE DESCRIPTOR POINTER LEVEL Figure 3 11 Table Descriptor Formats 3 2 2 2 PAGE DESCRIPTORS Figure 3 12 illustrates the page de
284. e table search for the entry completed successfully and if none of the TTRs instruction or data as appropriate match An ATC access error is not reported immediately if the last 16 bits of a page is either an A line illegal CHK or unimplemented instruction and the next page is non resident Instead the M68040 attempts to prefetch the next instruction on the missing page then the ATC access error exception is reported The stacked PC points to the exceptional 3 30 M68040 USER S MANUAL MOTOROLA instruction and the stacked points to the first longword in the missing page When ATC access error occurs while prefetching the next instruction on the non existant page after a change of flow instruction the exception should be cleared by execution of the new instruction flow Either avoid this scenario or have a dummy resident page following the exceptional instruction Figure 3 22 illustrates a general flowchart for address translation The top branch of the flowchart applies to transparent translation The bottom three branches apply to ATC translation 3 6 MMU EFFECT RSTI ANDMDIS The following paragraphs describe MMU effects on the RSTI andMDTS pins 3 6 1 Effect of RSTI on the MMUs When the M68040 is reset by the assertion of the reset input signal the E bits of the TCR and TTRs are cleared disabling address translation This reset causes logical addresses to be passed through as physical addresses allowi
285. e to the MC68EC040 and MC68ECO40V The organization of this manual is as follows Section 1 Introduction Section 2 Integer Unit Section 3 Memory Management Unit Except MC68EC040 and MC68EC040V Section 4 Instruction and Data Caches Section 5 Signal Description Section 6 IEEE 1149 1 Test Access Port JTAG Section 7 Bus Operation Section 8 Exception Processing Section 9 Floating Point Unit MC68040 Section 10 Instruction Timings Section 11 MC68040 Electrical and Thermal Characteristics Section 12 Ordering Information and Mechanical Data Appendix A MC68LC040 Appendix B MC68EC040 Appendix MC68040V and MC68EC040V Appendix D M68000 Family Summary Appendix E Floating Point Emulation M68040FPSP Index iv M68040 USER S MANUAL MOTOROLA M68040 USER S MANUAL TABLE CONTENTS Paragraph Page Number Title Number Section 1 Introduction 1 1 Bae fec RED 1 1 1 1 1 MC68040V and 681 040 1 1 1 1 2 MC68EC040 and MC68EC040V 1 2 1 2 EE 1 3 1 3 Extensions to the M68000 1 3 1 4 baee bead o pes 1 3 1 5 Processing 1 5 1 6 Programming Model cue deseri er anser 1 5 1 7 Data Format Summasry
286. ea this instruction is executing when underflow occurs In this example assume that the FMOVE instruction starts once the FADD instruction generates an underflow Given the register dependency on the destination of the FADD instruction FPO needs to be resolved prior to the FMOVE instruction execution For this example there is no choice but to have the FADD instruction report a post instruction exception immediately Note that for this case even though the T bit of the floating point state frame is set post instruction exception it does not imply an FMOVE OUT instruction Therefore the effective address field in the format 3 stack frame is invalid The FMOVE OUT instruction generates a post instruction exception For this case the effective address field in the format 3 stack frame points to the destination memory location If the destination is an integer data register the FPIAR points to the F line word of the offending instruction and the F line word contains the integer data register number If the M68040FPSP unimplemented instruction exception handler is used there can be some other cases in which an underflow is reported If an INEX2 or INEX1 exceptional condition exists and the user INEX exception handler is enabled it is the responsibility of the user UNFL exception handler to look for this situation The user UNFL exception handler examines the E3 bit of the floating point state frame to exit from this exception hand
287. each of the fields listed in alphabetical order NOTE The notation XX XX indicates the length of the field but does not indicate the field s actual location XX indicates that one bit of the field is located separately or termed differently from the other bits This notation is for convenience of explanation only For example WBTM 65 34 indicates that WBTM is 32 bits long and gives a reference to each bit in WBTM without giving its actual location in the state frame For the actual locations refer to Figure 9 10 MOTOROLA M68040 USER S MANUAL 9 39 10 19995 91215 1urod Duneo 4 070899 01 6 94n 14 9212156 sng oo Te WA ze 9 ALA sia OO T IALLdd ze 9 L ERA 99 qas Law 9915 NOUVIds t S9 ALLEM 00T simm 09 Tt 9r vc M68040 USER S MANUAL 9 40 Z 40 19945 91215 070899 01 6 1 15 p lu uu lduuiun p oo Te ALLA ze 9 AL
288. ed simply do no write backs and allow instruction to restart This is the only case in which the action to be taken depends on whether or not a double read can be tolerated MOTOROLA M68040 USER S MANUAL 8 29 Table 8 6 lists the possible combinations of write backs and the proper way to handle them The SSW RW column indicates a read or write cycle the SSW PUSH column indicates whether the fault is for a push TT 00 and TM 000 The WB1S WB2S and WB3S columns list the respective field s V bit and indicate a MOVE16 transfer type 01 The easy cleanup data written column lists the stack s field to be written out to memory if the user is not concerned with retouching peripherals The hard cleanup action column lists the action to be taken if the peripherals cannot be retouched by 16 if different from easy cleanup Note that if a push access error is reported and the size is long word all four long words PDO PD3 are still valid for the line The exception handler can either write PDO PD3 using the fault address with bits 3 0 cleared or write the PD corresponding to bits 3 2 of the address e g address 0000000C corresponds to PD3 Note that a MOVE16 is never reported the WB3S The SIZE field of WB3S is never a line After the bus error exception handler completes all pending operations and executes an RTE to return the RTE reads only the stack information from offset 0 D in the access error stack frame For a pe
289. eindexed with suppressed index bd BR Xn or od BR Xn od with Xn suppressed 2 All memory accesses hit in the caches no table searches occur as a result of ATC misses except for the operand accesses for the CAS CAS2 and TAS instructions These accesses are implicitly noncachable and force external bus accesses It is assumed that external memory has a zero wait state in this case and that the bus is granted to the M68040 The result increases access time equal to the number of clocks for the memory access first bus cycle if the operand access results in a line memory access if aligned accesses miss in the data cache As an approximation this time should be added to the execution time for each operand fetch generated by the instruction 3 All accesses are aligned to a byte boundary that is a multiple of the operand size For instance the timing for all long word accesses assumes that the operands are on long word boundaries 4 The integer execution times for floating point instructions assume that the floating point unit FPU is idle 10 4 M68040 USER S MANUAL MOTOROLA 10 2 INSTRUCTION TIMING EXAMPLES The following examples utilize the instruction timing information given in this section Figure 10 1 illustrates the integer unit pipeline flow for the simple code sequence listed The three instructions in the code sequence require only a single clock in each pipeline stage The TRAPF instructions are also single clock ins
290. emains asserted to indicate the bus is owned and the processor continuously drives the bus signals The processor negates BR when there are no pending accesses to allow the external arbiter to grant the bus to the alternate bus master if necessary MOTOROLA M68040 USER S MANUAL 7 45 In the second situation the processor samples until the external bus arbiter negates BB The processor drives its output pins with undetermined values and three states BB but does not perform a bus cycle This procedure called implicit ownership of the bus occurs when the processor is granted the bus but there are no pending bus cycles If an internal access request is generated the processor assumes explicit ownership of the bus and immediately begins an access simultaneously asserting BB BR TIP and TS If the external arbiter keeps BG asserted after completion of the bus cycle the processor keeps BB asserted and drives the bus with undefined values causing the processor to park In this case because BB remains asserted until the external arbiter negates BG the processor must assert BR TIP and TS simultaneously to enter an active bus cycle When it completes the active bus cycle and the external arbiter has not negated BG the processor goes back into park negating BR TIP and TS As long as BG is asserted the processor oscillates between park and active bus cycles The M68040 can be in any one of five bus arbitration states during bus operation id
291. en immediately depending on whether the faulted access specifically references data required by the execution unit or whether there are any other exceptions that can occur allowing the execution pipeline to idle An external access fault bus error occurs when external logic aborts a bus cycle and asserts the TEA input signal A bus error on a data write access always results in an access fault exception causing the processor to begin exception processing immediately A bus error on a data read also causes exception processing to begin immediately if the access is a byte word or long word access or if the bus error occurs on the first transfer of a line read Bus errors on the second third or fourth transfers for a data line read cause the transfer to be aborted but result in a bus error only if the execution unit is specifically requesting the long word being transferred For example if a misaligned operand spans the first two long words in the line being read a bus error on the second transfer causes an exception but a bus error on the third or last transfer does not unless the execution unit has generated another operand access that references data in these transfers Bus errors that occur during instruction prefetches are deferred until the processor attempts to use the information For instance if a bus error occurs while prefetching other instructions after a change of flow instruction BRA JMP JSR TRAP n etc BRA JMP JSR TR
292. ence of a dirty cache line implies that the page is not write protected and that writes to the page are in copyback mode system programming error occurs when page attributes are changed without flushing the corresponding page from the cache resulting in cache line states inconsistent with their page definitions Even with these inconsistencies the cache is defined and predictable 4 10 M68040 USER S MANUAL MOTOROLA 4 6 55 5 The cache controller in each memory unit performs all maintenance activities that supply data from the cache to the execution units The activities include requesting accesses to the bus interface unit for reading new cache lines and writing dirty cache lines to memory The following paragraphs describe the memory accesses resulting from cache fill operations by both caches and push operations by the data cache Refer to Section 7 Bus Operation for detailed information about the bus cycles required 4 6 1 Cache Filling When a new cache line is required the cache controller requests a line read from the bus controller The bus controller requests a burst read transfer by indicating a line access with the size signals SIZ1 SIZO and indicates which line in the set is being loaded with the transfer line number signals TLN1 TLNO TLN1 and TLNO are undefined for the instruction cache These pins indicate the appropriate line numbers for data cache transf
293. eported at the end of the emulated instruction The M68040FPSP not only emulates the instruction but in addition it ensures that if any floating point arithmetic exceptional conditions arise from the emulation of the unimplemented instruction and if the corresponding floating point arithmetic exception is enabled the M68040FPSP manipulates the stack and restores the stack back into the FPU in the desired exceptional state This effectively imitates the action of the MC68040 implemented instructions since the exception is not reported until the next floating point instruction is encountered This manipulation of the stack is rather complicated and is beyond the scope of this manual Motorola recommends that the user utilize the M68040FPSP if a full exception reporting model is required Motorola does not provide any printed documentation other than what is embedded in the source code of the M68040FPSP 9 6 2 Unsupported Floating Point Data Types An unsupported data type exception occurs when either operand to an implemented floating point instruction is denormalized for single double and extended precision operands unnormalized for extended precision operands or either the source or destination data format is packed decimal real These data types are unimplemented in the MC68040 and must be emulated in software 9 22 M68040 USER S MANUAL MOTOROLA In this manual all references to the unsupported floating point data types a
294. eption is enabled a If the user SNAN exception is disabled the M68040FPSP SNAN exception handler checks for an INEX1 or INEX2 exception condition and determines whether or not it needs to go to the user INEX exception handler If not the M68040FPSP returns to normal instruction execution Otherwise the M68040FPSP SNAN exception handler restores the FPU to its exceptional state cleans up the stack to the conditions prior to execution and continues instruction execution at the user INEX exception handler No parameters are passed to the user INEX exception handler since the M68040FPSP SNAN exception handler provides the illusion that it never existed b If the user SNAN exception handler is enabled the M68040FPSP SNAN exception handler checks to see if the destination is a floating point data register or in memory or an integer data register with single double or extended precision format If so the M68040FPSP SNAN exception handler determines which input operand is the SNAN sets the SNAN bit in the NAN data format and transfers the resulting nonsignaling NAN to the destination Once the destination has been written the M68040FPSP SNAN exception handler restores the FPU to its exceptional state cleans up the stack to the conditions prior to its execution and continues instruction execution at the user SNAN exception handler No parameters are passed to the user SNAN exception handler since the M68040FPSP SNAN exception handler provides
295. eption takes precedence CU is set and CT 0 The kernel must check for a trace condition using the stacked SH If this condition is true create the required stack frame and jump directly to the trace handler CT Continuation of Trace Exception Pending CT is set for an access error with a pending trace exception Operation is the same as for the CP flag When RTE is executed with CT set the M68040 will move the words on the stack an offset of 00 from the current SP to offset 30 3B adjusting the stack pointer by 30 The M68040 changes the stack frame format to 2 before fetching the trace exception vector and jumping directly to trace exception handling This stack adjustment creates the stack frame that normally would have been created for the trace exception had the pending access not encountered a bus error CM Continuation of MOVEM Instruction Execution Pending CM is set if a data access encounters a bus error for a MOVEM Since the MOVEM operation can write over the memory location or registers used to calculate the effective address the M68040 internally saves the effective address after calculation When MOVEM encounters a bus error a stack frame is created with CM set and the effective address field contains the calculated effective address for the instruction When RTE is executed MOVEM restarts using the effective address on the stack instead of repeating the effective address calculate operation if the address m
296. er Flowchart 7 10 7 9 Byte Word and Long Word Read Transfer 7 11 7 10 Line Head Transfer FIOWGHAIT sicut oen E onere aet 7 14 7 11 Line Read Transfer 7 15 7 12 JBurst Inhibited Line Read Transfer Flowchart 7 18 7 13 Burst Inhibited Line Read Transfer Timing 7 19 7 14 Byte Word and Long Word Write Transfer Flowchart 7 20 7 15 Long Word Write Transfer Timing 7 21 7 146 Line Write Transfer FIOWCHTE oto eaten 7 23 7 17 Line Write Transfer rn ense 7 24 7 18 Locked Transfer for TAS Instruction Timing 7 27 7 19 Interrupt Pending 42220 7 30 7 20 Assert Oi eur rent bns rab ed ot 7 30 7 21 Interrupt Acknowledge Bus Cycle Flowchart 7 32 7 22 Interrupt Acknowledge Bus Cycle 7 33 7 23 Interrupt Acknowledge Bus Cycle Timing 7 34 7 24 Breakpoint Interrupt Acknowledge Bus Cycle Flowchart 7 35 7 25 Breakpoint Interrupt Acknowledge Bus Cycle Timing 7 36 xviii M68040 USER S M
297. ered during the table search for this entry Setting a W bit in a table descriptor write protects all pages accessed with that descriptor When the W bit is set a write access or a read modify write access to the logical address corresponding to this entry causes an access error exception to be taken immediately For each access to a memory unit the MMU uses the four bits of the logical address located just above the page offset 16 1 13 for 8K pages LA15 LA12 for pages to index into the ATC The tags are compared with the remaining upper bits of the logical address and FC2 If one of the tags matches and is valid then the multiplexer choses the corresponding entry to produce the physical address and status information The ATC outputs the corresponding physical address to the cache controller which accesses the data within the cache and or requests an external bus cycle Each ATC entry contains a logical address a physical address and status bits When the ATC does not contain the translation for a logical address a miss occurs The MMU aborts the current access and searches the translation tables in memory for the correct translation If the table search completes without any errors the MMU stores the 3 28 M68040 USER S MANUAL MOTOROLA translation in the and provides the physical address for the access allowing the memory unit to retry the original access There are some variations in the logical to physical mappi
298. ernal state information from the stack during the execution of an RTE instruction a double bus fault occurs and the processor enters the halted state as indicated by the PSTS PSTO encoding 5 In this case the processor MOTOROLA M68040 USER S MANUAL 8 7 does not attempt to alter the current state of memory Only an external reset can restart processor halted by a double bus fault The supervisor stack has special requirements to ensure that exceptions can be stacked The stack must be resident with correct protection in the direction of growth to ensure that exception stacking never has a bus error or internal access fault Memory pages allocated to the stack that are higher in memory than the current stack pointer can be nonresident since an RTE or FRESTORE instruction can check for residency and trap before restoring the state A special case exists for systems that allow arbitration of the processor bus during locked transfer sequences If the arbiter can signal a bus error of a locked translation table update due to an improperly broken lock any pages touched by exception stack operations must have the U bit set in the corresponding page descriptor to prevent the occurrence of the locked access during translation table searches 8 2 2 Address Error Exception An address error exception occurs when the processor attempts to prefetch an instruction from an odd address This includes the case of a conditional branch instruction with an o
299. erns do not match either of the above two cases the processor takes an F line illegal exception F line illegal exceptions are discussed further in Section 8 Exception Processing The processor generates an exception with vector number 11 and pushes a four word stack frame format 0 on the system stack An illegal instruction exception is also reported when a breakpoint acknowledge bus cycle is run and terminated with either a transfer acknowledge TA or transfer error acknowledge TEA signal Since the unimplemented floating point 9 20 M68040 USER S MANUAL MOTOROLA exception and the F line illegal instruction share the same vector the exception handler uses the stack frame format 0 or 2 to distinguish between the two Table 9 10 Unimplemented Instructions scare When an unimplemented floating point instruction is encountered the processor waits for all previous floating point instructions to complete execution Pending exceptions are taken and handled prior to the execution of the unimplemented instruction Next the instruction is partially decoded to allow fetching of the memory source operand if required When the operand fetch begins all other read accesses for previous instructions are complete and only the execution and write back of results for previous integer instructions remains to be completed If an access error bus error occurs in fetching the operand or in completing any other access before beginning the
300. ers only Table 4 2 lists the definition of the TLNx encoding Table 4 2 TLNx Encoding The responding device sequentially supplies four long words of data and can assert the transfer cache inhibit signal TC1 if the line is not cachable If the responding device does not support the burst mode it should assert the TBI signal for the first long word of the line access The bus controller responds by terminating the line access and completes the remainder of the line read as three sequential long word reads Bus controller line accesses implicitly request burst mode operations from external memory To operate in the burst mode the device or external hardware must be able to increment the low order address bits as described in Section 7 Bus Operation The device indicates its ability to support the burst access by acknowledging the initial long word transfer with transfer acknowledge TA asserted and TBInegated This procedure causes the processor to continue to drive the address and bus control signals and to latch a new data value for the cache line at the completion of each subsequent cycle as defined by TA for a total of four cycles The bursting mechanism requires addresses to wrap around so that the entire four long words in the cache line are filled in a single operation When a cache line read is initiated the first cycle attempts to load the line entry corresponding to the instruction half line or data item requested by t
301. es 7 14 and 7 15 illustrate a flowchart and functional timing diagram for byte word and long word write bus transfers 7 20 PROCESSOR EXTERNAL DEVICE ADDRESS DEVICE SET R W TO WRITE DRIVE ADDRESS ON A31 A0 DRIVE USER PAGE ATTRIBUTES ON UPA1 DRIVE SIZE ON 5121 5170 BYTE WORD OR LONG WORD DRIVE TRANSFER TYPE ON TT1 TTO DRIVE TRANSFER MODIFIER ON TM2 TMO CIOUT BECOMES VALID ASSERT TS FOR ONE CLOCK ASSERT TIP DRIVE DATA ON APPROPRIATE BYTES OF ACCEPT DATA D31 D0 BASED ON SIZEx A1 AND A0 1 DECODE ADDRESS 2 LATCH DATA ON APPROPRIATE BYTES OF D31 D0 BASED ON SIZEx A1 AND A0 SERMINETE TRANEFER 3 ASSERT TRANSFER ACKNOWLEDGE 1 REMOVE DATA FROM 031 00 TERMINATE CYCLE 2 NEGATE TIP IF REQUIRED 1 NEGATE TA START NEXT CYCLE Figure 7 14 Byte Word and Long Word Write Transfer Flowchart M68040 USER S MANUAL MOTOROLA i 5171 SIZO LONG TT TTO toNG woRp gt _ WRITE Figure 7 15 Long Word Write Transfer Timing Clock 1 C1 The write cycle starts in C1 During the first half of C1 the processor places valid values on the address bus and transfer attributes For user and supervisor mode accesses which the corresponding memory unit translates the UPAx signals are driven with the values from the U1 and UO bits for the area The TTx and TMx signals identify the specific access type The R W signal is driven low for a write cycle CIOUT
302. es an access error or generates an address error while in the exception processing state For example if during exception processing of one access error another access error occurs the MC68040 is unable to complete the transition to normal processing and cannot save the internal state of the machine The processor assumes that the system is not operational and halts Only an external reset can restart a halted processor Note that when the processor executes a STOP instruction it is in a special type of normal processing state one without bus cycles The processor stops but it does not halt 1 6 PROGRAMMING MODEL The MC68040 programming model is separated into two privilege modes supervisor and user The S bit in the status register SR indicates the privilege mode that the processor MOTOROLA M68040 USER S MANUAL 1 5 uses IU identifies a logical address by accessing either the supervisor or user address space maintaining the differentiation between supervisor and user modes The MMUS use the indicated privilege mode to control and translate memory accesses protecting supervisor code data and resources from user program accesses Refer to Appendix B MC68EC040 for details concerning the MC68EC040 address translation Programs access registers based on the indicated mode User programs can only access registers specific to the user mode whereas system software executing in the supervisor mode can access all registers using the c
303. es not monitor data accesses Processor writes that modify code segments i e resulting from self modifying code or from code executed to load a new page from disk access memory through the data memory unit Because the instruction cache does not monitor these data accesses stale data occurs in the instruction cache if the corresponding data in memory is modified Invalidating instruction cache lines before writing to the corresponding memory lines can prevent this coherency problem but only if the data cache line is in write through mode and the page is marked serialized A cache coherency problem could arise if the data cache line is configured as copyback and no serialization is done To fully support self modifying code in any situation it is imperative that a CPUSHA instruction be executed before the execution of the first self modified instruction The CPUSHA instruction has the effect of ensuring that there is no stale data in memory the pipeline is flushed and instruction prefetches are repeated and taken from external memory Another potential coherency problem exists due to the relationship between the cache state information and the translation table descriptors Because each cache line reflects page state information a page should be flushed from the cache before any of the page attributes are changed The presence of a valid or dirty cache line implicitly indicates that accesses to the page containing the line are cachable The pres
304. es the push Write accesses to memory pages specified as write through by the data memory unit update the corresponding cache line before accessing memory If a bus error occurs during a memory access the cache line remains valid with the new data Figure 7 26 illustrates a functional timing diagram of a bus error on a word write access causing an access error exception Figure 7 27 illustrates a functional timing diagram of a bus error on a line read access that does not cause an access error exception A physical bus error during an FSAVE instruction results in corruption of the floating point state frame This is not a serious limitation since prior to writing the stack frame the M68040 ensures that the pages required for the floating point state frame are resident Therefore only a physical bus error can cause an access error during the stacking of the state frame In a normal application writes caused by the processor should not result in a physical bus error since the logical address space has already been translated and allocated Since there should be no parity errors caused by processor write accesses only spurious assertions of the TEA pin can cause physical bus errors Furthermore because FSAVE instructions usually place the state frame on the system stack the occurrence of a physical bus error when using the system stack indicates a serious hardware error 7 38 M68040 USER S MANUAL MOTOROLA C2 Cl C2 Cl BCLK A31 A0
305. es to the floating point unit FPU For the MC68EC040 and MC68bECO40V only ignore all references to the memory management unit MMU Some pin names are different on these parts please refer to the appropriate appendix in the back of this book for more information M68040 USER S MANUAL 5 1 Table 5 1 Signal Index Address Bus A31 A0 32 bit address bus used to address any of 4 Gbytes D31 DO 32 bit data bus used to transfer to 32 bits of data per bus transfer Transfer Type TT1 TTO Indicates the general transfer type normal MOVE16 alternate logical function code and acknowledge Transfer Modifier TM2 TMO Indicates supplemental information about the access Transfer Line Number TLN1 TLNO Indicates which cache line in a set is being pushed or loaded by the current line transfer User Programmable UPA1 UPAO User defined signals controlled by the corresponding user attribute bits from Attributes the address translation entry Read Write Identifies the transfer as a read or write Transfer Size SIZ1 SIZO Indicates the data transfer size These signals together with AO and 1 define the active sections of the data bus Bus Lock LOCK Indicates a bus transfer is part of a read modify write operation and the sequence of transfers should not be interrupted Bus Lock End Indicates the current transfer is the last in a locked sequence of transfers Cache Inhibit Out Indicates the processor will not cache the current
306. escriptors in copyback mode with the bit pattern U 0 M 1 and 1 in a page descriptor The M68040 table search algorithm will never leave this bit pattern for a page descriptor 31 30 16 15 14 0 UNDEFINED UNDEFINED DE Enable Data Cache IE Enable Instruction Cache Figure 4 4 Cache Control Register System hardware can assert the cache disable 5 signal to dynamically disable both caches regardless of the state of the enable bits in the CACR The caches are disabled immediately after the current access completes If CDIS is asserted during the access for the first half of a misaligned operand spanning two cache lines the data cache is disabled for the second half of the operand Accesses by the execution units bypass the caches while they are disabled and do not affect their contents with the exception of CINV and CPUSH instructions Disabling the caches with does not affect snoop operations CDIS is intended primarily for use by in circuit emulators to allow swapping between the tags and emulator memories Even if the instruction cache is disabled the M68040 can cache instructions because of an internal cache line register This happens for instruction loops that are completely resident within the first six bytes of a half line Thus the cache line holding register can operate as a small cache If a loop fits anywhere within the first three words of a half line then it becomes cached The
307. ese addressing modes the M68040 provides index sizing and scaling features An instruction s addressing mode can specify the value of an operand a register containing the operand or how to derive the effective address of an operand in memory Each addressing mode has an assembler syntax Some instructions imply the addressing mode for an operand These instructions include the appropriate fields for operands that use only one addressing mode Table 1 2 lists a summary of the effective addressing modes for the M68040 Refer to M68000PM AD M68000 Family Programmer s Reference Manual for details on instruction format and addressing modes Table 1 2 Effective Addressing Modes Addressing Modes Register Direct Data Address Register Indirect Address An Address with Postincrement An Address with Predecrement Address with Displacement d16 An Address Register Indirect with Index 8 Bit Displacement Base Displacement Memory Indirect Postindexed pd An Xn od Preindexed pd An Xn od Program Counter Indirect with Displacement Program Counter Indirect with Index 8 Bit Displacement dg PC Xn Base Displacement bd PC Xn Program Counter Memory Indirect Postindexed bd PC Xn od Preindexed bd PC Xn od Absolute Data Addressing Short xxx W Long xxx L 1 10 M68040 USER S MANUAL MOTOROLA 1 9 NOTATIONAL CONVENTIONS Table 1 3 lists the notation conventions used throughout this manual u
308. ess bus for each bus cycle Refer to 7 4 1 Byte Word and Long Word Read Transfers for information on long word reads If no wait states are generated a burst inhibited line read completes in eight clocks instead of the five required for a burst read Clock 3 C3 The processor holds the address and transfer attribute signals constant during C3 The selected device must increment A3 and A2 to reference the next long word to transfer place the data on the data bus and assert TA At the end of C3 the processor samples the level of TA and latches the current value on the data bus If TA is asserted the transfer terminates and the second long word of data is passed to the appropriate memory unit If TA is not recognized asserted at the end of C3 the processor ignores the latched data and inserts wait states instead of terminating the transfer The processor continues to sample TA on successive rising edges of BCLK until it is recognized The latched data is then passed to the appropriate memory unit Clock 4 C4 This clock is identical to C3 except that once TA is recognized asserted the latched value corresponds to the third long word of data for the burst 7 16 M68040 USER S MANUAL MOTOROLA 5 5 This clock is identical to C3 except that once TA is recognized the latched value corresponds to the third long word of data for the burst After the processor recognizes the last TA assertion and terminates the line read bus c
309. ess to be performed This MOTOROLA M68040 USER S MANUAL 3 27 procedure ensures that the first write operation to page sets the M bit in both the and the page descriptor in the translation tables even when a previous read operation to the page had created an entry for that page in the ATC with the M bit clear Physical Address The upper bits of the translated physical address are contained in this field R Resident This bit is set if the table search successfully completes without encountering either a nonresident page or a transfer error acknowledge during the search S Supervisor Protected This bit identifies a pointer table or a page as a supervisor only table or page Only programs operating in the supervisor privilege mode are allowed to access the portion of the logical address space mapped by this descriptor when the S bit is set If the bit is clear both supervisor and user accesses are allowed UO U1 User Page Attributes These user defined bits are not interpreted by the M68040 UO and U1 are echoed to the UPAO and 1 signals respectively if an external bus transfer results from the access V Valid When set this bit indicates the validity of the entry This bit is set when the M68040 loads an entry A flush operation by a PFLUSH or PFLUSHA instruction that selects this entry clears the bit W Write Protected This write protect bit is set when a W bit is set in any of the descriptors encount
310. est logic MOTOROLA M68040 USER S MANUAL 6 5 has control of the I O pins 1149 1 interface is transparent to system operation except for drive control selection during execution of this instruction When the system logic has control of the signal directions and levels the drive control latches are loaded from the 2 0 at the negation of the RSTI signal After RSTI has been negated and the 128 clock internal reset cycle has expired see Section 7 Bus Operation the DRVCTL S instruction is executed Each drive control latch is modified during the update DR state Any subsequent RSTI signal negation while in a system configuration i e system logic has control of the signal I O directions and levels can cause the drive control latches to be overwritten with new signal values The system bus can be suspended in a wait state while this function is being performed 6 2 8 BYPASS The BYPASS instruction selects the single bit bypass register creating a single bit shift register path from TDI to the bypass register to TDO The instruction enhances test efficiency when a component other than the M68040 becomes the device under test When the bypass register is initially selected the instruction shift register stage is set to a logic zero on the rising edge of TCK following entry into the capture DR state Therefore the first bit to be shifted out after selecting the bypass register is always a
311. et function or a restore operation of the null state clears the FPCR When cleared this register provides the IEEE 754 standard defaults 9 2 2 1 EXCEPTION ENABLE BYTE Each bit of the ENABLE byte see Figure 9 2 corresponds to a floating point exception class The user can separately enable traps for each class of floating point exceptions 9 2 2 2 MODE CONTROL BYTE The MODE byte see Figure 9 2 controls the user selectable rounding modes and precisions Zeros in this byte select the IEEE 754 standard defaults The rounding mode RND specifies how inexact results are rounded and the rounding precision PREC selects the boundary for rounding the mantissa The processor supports four rounding modes specified by the IEEE 754 standard These modes are round to nearest RN round toward zero RZ round toward plus infinity RP and round toward minus infinity RM The RP and RM modes are directed rounding modes that are useful in interval arithmetic Rounding is accomplished through the intermediate result Single precision results are rounded to a 24 bit boundary double precision results are rounded to a 53 bit boundary and extended precision results are rounded to a 64 bit boundary Table 9 1 lists the encodings for the FPCR Table 9 1 Floating Point Control Register Encodings RND Field PREC Field i D N RZ MOTOROLA M68040 USER S MANUAL 9 3 EXCEPTION ENABLE MODE CONTROL 15 14 13 12 11
312. etermine which translation table supervisor or user to search and which ATC data or instruction to create the entry in After executing this code sequence the handler can examine the MMUSR for the source of the fault The M68040 MMU instructions use opcodes that are different from those for the corresponding instructions in the 68030 and MC68851 MMU opcodes for the MOTOROLA M68040 USER S MANUAL 3 33 68030 and 68851 cause F line unimplemented instruction exceptions if executed in either supervisor or user mode by the M68040 3 7 4 Register Programming Considerations If the entries in the ATCs are no longer valid when a reset operation occurs as is normally expected an explicit flush operation must be specified by the system software The assertion of RSTI disables translation by clearing the E bits of the TCR DTTRx and ITTRx but it does not flush the ATCs Reading or writing any of the MMU registers URP SRP TCR MMUSR DTTRO DTTR1 ITTRO ITTR1 does not flush the ATCs Since a write to these registers can cause some or all the address translations to change the write should be followed by a PFLUSH operation to flush the ATCs if necessary The status bits in the MMUSR indicate conditions to which the operating system should respond In a typical access error exception handler the flowchart illustrated in Figure 3 23 can be used to determine the cause of an MMU fault The PTEST instruction sets the bits in the
313. f floating point operations A sticky bit is one that remains set until the user clears it 1 6 5 4 3 2 1 0 o om INEXACT DIVIDE BY ZERO UNDERFLOW OVERFLOW INVALID OPERATION Figure 9 6 FPSR Accrued Exception Byte Setting or clearing the AEXC bits neither causes nor prevents an exception The following equations show the comparative relationship between the EXC byte and AEXC byte Comparing the current value in the AEXC bit with a combination of bits in the EXC byte derives a new value in the corresponding AEXC bit These equations apply to setting the AEXC bits at the end of each operation affecting the AEXC byte AEXC Bit Bit IoP SNAN V OVFL V OVFL DZ INEX1 V 2 V OVFL 9 2 4 Floating Point Instruction Address Register FPIAR For the subset of the floating point instructions that generate exception traps the FPU loads the 32 bit FPIAR with the logical address of the instruction before executing the instruction Because the IU can execute instructions while the FPU executes floating point instructions and the FPU can concurrently execute two floating point instructions the PC value stacked by the MC68040 in response to a floating point exception handler cannot point to the offending instruction Therefore a floating point exception handler uses the address in the FPIAR to locate a floating point instruction that has caused an except
314. f the 33 MHz MC68881 MC68882 The error bound is equivalent to that of the MC68881 MC68882 OUNIX is a registered trademark of AT amp T Bell Laboratories MOTOROLA M68040 USER S MANUAL E 1 System designers integrate the M68040FPSP into the system so that the user object code runs unchanged and remains totally transparent to the end user The M68040FPSP can be installed into any operating system lt provides kernel routines to support unimplemented instructions and unsupported data types Unimplemented instructions for end user applications compiled for the MC68881 MC68882 are contained in a library for improved performance For all MC68040 floating point instructions the coprocessor ID field must be 001 Table E 1 lists the floating point functions implemented as instructions by the MC68040 Table E 1 MC68040 Floating Point Instructions Description Move to FPx or CR FDMOVE Single Precision Move FABS Branch Conditionally FTRAPcc Test Condition Decrement and Branch FSSUB Single Precision Add FSDIV FMOVE FSMOVE FCMP FSABS FTST FSNEG FADD FDIV FBcc FDBcc FSADD FSMUL FDADD FDMUL FSQRT FSAVE FMOVEM Compare Single Precision Absolute Value Test Single Precision Negate Add Single Precision Multiply Double Precision Add Double Precision Multiply Square Root Save Internal State Move Multiple Registers E 2 M68040 USER S MANUAL MOTOROLA Table E 2 list the arithmetic and transcendental instructions th
315. f the access faults again For data access faults the processor aborts current instruction execution If a data access fault is detected the processor waits for the current instruction prefetch bus cycle to complete then begins exception processing immediately As illustrated in Figure 8 1 the processor begins exception processing for an access fault by making an internal copy of the current SR The processor then enters the supervisor mode and clears T1 and TO The processor generates exception vector number 2 for the access fault vector It saves the vector offset PC and internal copy of the SR on the stack The saved PC value is the logical address of the instruction executing at the time the fault was detected This instruction is not necessarily the one that initiated the bus cycle since the processor overlaps execution of instructions It also saves information to allow continuation after a fault during a MOVEM instruction and to support other pending exceptions The faulted address and pending write back information is saved The information saved on the stack is sufficient to identify the cause of the bus error complete pending write backs and recover from the error The exception handler must complete the pending write backs Up to three write backs can be pending for push errors and data access errors If a bus error occurs during the exception processing for an access fault address error or reset or while the processor is loading int
316. ffer unterminated value MC68040 OUTPUT BUFFER 50QTL R 50 Q W T TYPICAL 20 4 12 LARGE TYPICAL 70 25 Q SMALL Figure 11 9 Typical Configuration for RC Termination Network 300 pF The following paragraphs describe how the large buffer terminated values were calculated The MC68040 termination network causes current flow through the output buffer of the MC68040 regardless of whether the MC68040 is driving a logic one or a logic zero The following equation gives the large buffer termination network power dissipation for a given pin Zo 5 P Rest is the effective average output resistance including typical pullup resistance typical pulldown resistance and a duty cycle average of how often the pin is high low or three stated Typical values for Zo are 6 O for large buffer low output 12 for large buffer high output and 25 for small buffer output Using these values and duty cycle assumptions based on sequential burst write cycles calculates to 7 7 Q for the MC68040 large buffer mode and 25 Q for the small buffer mode Maximum termination current in the large buffer mode occurs for output Low dg 2 5V 50 6Q 5 49 6 mA High lin 2 75 V 50 12 5b 50 8 mA MOTOROLA M68040 USER S MANUAL 11 15 Maximum power dissipation in the large buffer mode occurs for output Low 128 49 6 mA x 6 Q 14 8 mW High _ Pup 12 50 8 mA
317. fields except for the UDT field This MOTOROLA M68040 USER S MANUAL 3 19 interpretation allows the operating system to store system defined information in the remaining bits Information typically stored includes the reason for the invalid encoding tables paged out region unallocated etc and possibly the disk address for nonresident tables Figure 3 16 illustrates an address translation table in which only a single page table table 15 is resident all other page tables are not resident LOGICAL ADDRESS ROOT INDEX POINTER INDEX PAGE INDEX PAGE OFFSET 76543210 TABLE ENTRY 3B 15 01 ADDRESS OFFSET EC 54 04 SUPERVISOR TABLE 00 TABLE 00 TABLE 00 NONRESIDENT PAGED OR UNALLOCATED NONRESIDENT PAGED OR UNALLOCATED NONRESIDENT PAGED OR UNALLOCATED TABLE 3B TABLE 515 SRP UDT INVALID U VALID haa UDT INVALID U VALID EE 38 UDT RESIDENT 15 FRAME ADDRESS UDT INVALID UDT INVALID NONRESIDENT PAGED OR PAGED OR PAGED OR UNALLOCATED UNALLOCATED UNALLOCATED ROOT LEVEL POINTER LEVEL PAGE LEVEL TABLES TABLES TABLES Figure 3 16 Translation Table with Nonresident Tables 3 20 M68040 USER S MANUAL MOTOROLA VALID DT IN DT IN UDT RESIDENT DT IN UDT INVALID TABLE 7F NONRESIDENT TABLE 1F NONRESIDENT 3 2 4 4 DYNAMICALLY ALLOCATED TABLES Similar to paged tables a complete translation table need not exist fo
318. for more information on the MC68040V The MC68LC040 is Motorola s integer only version of the MC68040 third generation M68000 compatible high performance 32 bit microprocessor The MC68LC040 is a virtual memory microprocessor with a highly integrated architecture that provides very high performance in a monolithic HCMOS device On a single chip the MC68LC040 integrates an MC68040 compatible integer unit and fully independent instruction and data demand paged memory management units MMUs including independent 4 Kbyte instruction and data caches A high degree of instruction execution parallelism is achieved through the use of a six stage instruction pipeline multiple internal buses and a full internal Harvard architecture including separate physical caches for both instruction and data accesses The MC68L C040 also directly supports cache coherency in multimaster applications with dedicated on chip bus snooping logic The MC68LC040 achieves its high performance through the use of the MC68040 integer unit The six stage pipeline operates on up to six instructions concurrent with MMU cache and bus controller operations Multiple internal buses separate data and instruction caches and a sophisticated bus controller allow internal units to operate concurrently and decouple the MC68L C040 from the external bus The internal caches and the decoupling of the external bus allow for an external memory subsystem to be built from slower and less expen
319. g one of these formats is stalled for more than N clocks waiting to begin execution in the execute stage a similar increase in the ea calculate time will result For example if the execution time listed is 21 1 and the instruction stalls for three clocks then the ea calculate time increases by one clock 3 1 21 Write back times are not listed because they are system dependent and do not affect either ea calculate or execute stages of the pipeline Not all addressing modes listed in the following tables for an instruction are valid for all variations of the instruction For example the table for the integer ADD instruction lists times for both ADD lt ea gt Dn and ADD Dn lt ea gt All addressing modes listed are valid for ADD lt ea gt Dn For ADD Dn lt ea gt the following invalid modes should be ignored An d 16 PC xxx dg PC Xn and modes with BR PC Refer to the M68000PM AD M68000 Family Programmer s Reference Manual for a complete summary of valid instruction and addressing mode combinations The instruction timings are based on the following suppositions unless otherwise noted 1 All timings are related to BCLK cycles and are for BR An or suppressed For BR PC 1 and 1 clocks to the ea calculate and execution times unless otherwise noted For memory indirect postindexed with suppressed index bd BR Xn or pd BR Xn od with Xn suppressed times are the same as for memory indirect pr
320. ger Unit Pipeline s n tende 2 2 2 2 Write Back Cycle Block Diagram 2 3 2 3 Integer Unit User Programming 2 4 2 4 Integer Unit Supervisor Programming 2 6 2 5 Status R glslel etn poi ore e 2 7 3 1 Memory Management 3 2 3 2 Memory Management Programming 3 3 3 3 URP and SRP Register 440222 4 011 3 4 3 4 Translation Control Register Format 3 4 3 5 Transparent Translation Register 3 5 3 6 MMU Status Register cce dro 3 6 3 7 Translation Table 3 8 3 8 Logical Address Format 4 1 3 9 3 9 Detailed Flowchart of Table Search Operation 3 10 3 10 Detailed Flowchart of Descriptor Fetch Operation 3 11 3 11 Table Descriptor Formats iui te td er eb Ep rre eit 3 13 3 12 Descriptor 3 13 3 13 Example Translation Table 3 17 3 14 Translation Table Using Indirect
321. ghest priority becomes the bus master first 7 8 1 Bus Arbitration The M68040 bus controller generates bus requests to the external arbiter in response to internal requests from the instruction and data memory units The M68040 performs bus arbitration using the bus request BR bus grant BG and bus busy BB signals The arbitration protocol which allows arbitration to overlap with bus activity requires a single idle clock to prevent bus contention when transferring bus ownership between bus masters The bus arbitration unit in the M68040 operates synchronously and transitions between states on the rising edge of BLCK The M68040 requests the bus from the external bus arbiter by asserting BR whenever an internal bus request is pending The processor continues to assert BR for as long as it requires the bus The processor negates BR at any time without regard to the status of BG and BB If the bus is granted to the processor when an internal bus request is generated BR is asserted simultaneously with transfer start TS allowing the access to begin immediately The processor always drives BR and BR cannot be wire ORed with other devices The external arbiter asserts BG to indicate to the processor that it has been granted the bus If BG is negated while a bus cycle is in progress the processor relinquishes the bus at the completion of the bus cycle To guarantee that the bus is relinquished BG must be negated prior to the rising edge of t
322. gram M68040 USER S MANUAL MOTOROLA A 6 6 Output AC Timing Specifications see Figures 5 to A 9 Characteristic BCLK to Address CIOUT LOCK LOCKE PSTx RW SIZx TLNx TMx TTx UPAx Valid BCLK to Output Invalid Output Hold 11 5 BCLK to TS Valid 11 5 35 BCLK to TIP Valid 35 3 5 BCLK to Data Out Invalid Output Hold 11 5 BCLK to Output Low Impedance 11 5 BCLK to Data Out High Impedance 11 5 2 BCLK to Address CIOUT LOCK LOCKE R W SIZx TS TLNx TMx TTx UPAx High Impedance BCLK to BB TA TIP High Impedance id 2 id 12 13 14 18 19 20 21 Output timing is specified for a valid signal measured at pin Timing is specified driving unterminated 30 0 transmission line with a length characterized by a 2 5 ns one way propagation delay Buffer output impedance is typically 30 O the buffer specifications include approximately 5 ns for the signal to propagate the length of the transmission line and back ES EN 39 ES ES 39 40 43 48 50 MOTOROLA M68040 USER S MANUAL 11 A 6 7 Input AC Timing Specifications see Figures 5 to A 9 25MHz 33MHz Characteristic 12522 Followed by Write zz ms vanoas 5 zs TeivatsioBCuK Seu _______
323. h All Earlier M68000 Microprocessors 4 Gbyte Direct Addressing Range Software Support Including Optimizing C Compiler and UNIX System V Port The on chip FPU and large physical instruction and data caches yield improved system performance and increased functionality The independent instruction and data MMUs and increased internal parallelism also improve performance 1 3 EXTENSIONS TO THE M68000 FAMILY The M68040 is compatible with the ANSI IEEE Standard 754 for Binary Floating Point Arithmetic The MC68040 s FPU has been optimized to execute the most commonly used subset of the MC68881 MC68882 instruction sets and includes additional instruction formats for single and double precision rounding results Software emulates floating point instructions not directly supported in hardware Refer to Appendix E M68040 Floating Point Emulation MC68040FPSP for details on software emulation The MOVE16 user instruction is new to the instruction set supporting efficient 16 byte memory to memory data transfers 1 4 FUNCTIONAL BLOCKS Figure 1 1 illustrates a simplified block diagram of the MC68040 Refer to Appendix A MC68LC040 for information on the MC68LC040 s and MC68040V s functional blocks and Appendix 68 040 for information on the MC68EC040 s and MC68bECO040V s functional blocks The M68040 IU pipeline has been expanded from the MC68030 to include effective address calculation ea calculate and operand fetch ea fetch s
324. he BCLK in which the last TA or TEA is asserted Note that the bus controller considers the four bus transfers for a burst inhibited line transfer to be a single bus cycle and does not relinquish the bus until completion of the fourth transfer The read and write portions of a locked read modify write sequence are divisible in the M68040 allowing the bus to be arbitrated away during the locked sequence For system applications that do not allow locked sequences to be broken the arbiter can use LOCK to detect locked accesses and prevent the negation of BG to the processor during these sequences The processor also provides the LOCKE signal to indicate the last write cycle of a locked sequence allowing arbitration between back to back locked sequences See 7 4 5 Read Modify Write Transfers Locked Transfers for a detailed description of read modify write transfers When the bus has been granted to the processor in response to the assertion of BR one of two situations can occur In the first situation the processor monitors BB to determine when the bus cycle of the alternate bus master is complete After the alternate bus master negates BB the processor asserts BB to indicate explicit bus ownership and begins the bus cycle by asserting TS The processor continues to assert BB until the external arbiter negates BG after which BB is first negated at the completion of the bus cycle then forced to a high impedance state As long as BG is asserted BB r
325. he IU Subsequent transfers are for the remaining entries in the cache line In the case of a misaligned MOTOROLA M68040 USER S MANUAL 4 11 access in which the operand spans two line entries the first cycle corresponds to the line entry containing the portion of the operand at the lower address The cache controller temporarily stores the data from each cycle in a line read buffer where it is immediately available to the IU If a misaligned access spans two entries in the line the second portion of the operand is available to the IU as soon as the second memory cycle completes A new IU access that hits the cache line being filled is also supplied data as soon as the required long word has been received from the bus controller During the period required to fill the buffer other IU accesses that hit in the cache are supplied data This is vertical for a short cache inhibited code loop that is less than eight bytes in length Subsequent interactions of the loop hit in the buffer but appear to hit in the cache since there is no external bus activity associated with the reads The assertion of during the first cycle of a burst read operation inhibits loading of the buffered line into the cache but it does not cause the burst transfer or pseudo burst transfer if TBTis asserted with to be terminated early The data placed in the buffer is accessible by the IU until the last long word of the burst is transferred from the bus contro
326. he Inhibit TC 1 This input signal inhibits read data from being loaded into the M68040 instruction or data caches TCI is ignored during all writes and after the first data transfer for both burst line reads and burst inhibited line reads TCI is also ignored during all alternate bus master transfers 5 4 6 Transfer Burst Inhibit TBI This input signal indicates to the processor that the accessed device cannot support burst mode accesses and that the requested line transfer should be divided into individual long word transfers Asserting TBI with TA terminates the first data transfer of a line access which causes the processor to terminate the burst and access the remaining data for the line as three successive long word transfers During alternate bus master accesses the M68040 samples the TBI to detect completion of each bus transfer 5 5 SNOOP CONTROL SIGNALS The following signals control the operation of the M68040 on chip snoop logic Section 4 Instruction and Data Caches provides information about the relationship of the snoop control signals to the caches and Section 7 Bus Operation discusses the relationship of these signals to bus operation 5 5 1 Snoop Control SC1 5 0 These input signals specify the snoop operation to be performed by the M68040 for an alternate bus master transfer If the M68040 is allowed to snoop an alternate bus master read transfer it can intervene in the access to supply data from its da
327. he conditional predicate is the lower six bits of the instruction word which immediately follows the F line operation word Using the conditional predicate and the table for IEEE nonaware test in 9 5 2 Conditional Testing the condition codes can be set to return a known result indication when the conditional instruction is reexecuted Prior to exiting the user BSUN exception handler the exception handler discards the floating point state frame 9 7 1 2 NONMASKABLE EXCEPTION CONDITIONS There are no conditions 9 7 2 Signaling Not a Number SNAN An SNAN is used as an escape mechanism for a user defined non IEEE data type The processor never creates an SNAN as a result of an operation a NAN created by an operand error exception is always a nonsignaling NAN When an operand is an SNAN involved in an arithmetic instruction the SNAN bit is set in the FPSR EXC byte Since the FMOVEM FMOVE FPCR and FSAVE instructions do not modify the status bits they cannot generate exceptions Therefore these instructions are useful for manipulating SNANs 9 7 2 1 MASKABLE EXCEPTION CONDITIONS When an SNAN is encountered if the destination is a floating point data register or is in memory or an integer data register and the format is single double or extended precision the SNAN is maskable and may or may not take an exception a If the user SNAN exception is disabled the processor clears the SNAN bit in the NAN data format and the resulting non
328. he external request can be lowered to level 3 and then raised back to level 6 and a second level 6 interrupt is not processed However if the M68040 is handling a level 7 interrupt SR mask set to level 7 and the external request is lowered to level 3 and than raised back to level 7 a second level 7 interrupt is processed The second level 7 interrupt is processed because the level 7 interrupt is transition sensitive A level comparison also generates a level 7 interrupt if the request level and mask level are at 7 and the priority mask is then set to a lower level with the MOVE to SR or RTE instruction for example The level 6 interrupt request and mask level example in Figure 8 3 is the same as for all interrupt levels except 7 MOTOROLA M68040 USER S MANUAL 8 13 EXTERNAL INTERRUPT PRIORITY IPL2 IPLO MASK 12 10 ACTION 100 3 101 5 INITIAL CONDITIONS Y y IF 001 6 THEN 110 6 AND LEVEL 6 INTERRUPT LEVEL COMPARISON Y IF 100 3 AND STILL 110 6 THEN NO ACTION 5 001 56 AND STILL 110 6 THEN NO ACTION Y IF STILL 001 6 AND RTE SO THAT 101 5 THEN LEVEL 6 INTERRUPT LEVEL COMPARISON 100 3 101 5 INITIAL CONDITIONS Y y IF 000 7 THEN 111 7 AND LEVEL 7 INTERRUPT TRANSITION Y IF 100 3 AND STILL 111 7 THEN NO ACTION d 5 000 57 AND STILL 111 7 THEN NO ACTION TRANSITION Y IF STILL 000 7
329. he same operation in extended precision and storing the results in single or double precision format The FPU performs all floating point internal operations in extended precision It supports mixed mode arithmetic by converting single and double precision operands to extended precision values before performing the specified operation The FPU converts all memory data formats to extended precision before using it in a floating point operation or loading it in a floating point data register The FPU also converts extended precision data formats in a floating point data register to any data format and either stores it in a memory destination or in an integer data register If the external operand is a denormalized number the number is normalized before an operation is performed However an external denormalized number moved into a floating point data register is stored as a denormalized number If an external operand is an unnormalized number the number is normalized before it is used in an arithmetic operation If the external operand is an unnormalized zero i e with a mantissa of all zeros the number is converted to a normalized zero before the specified operation is performed The regular use of unnormalized inputs not only defeats the purpose of the IEEE 754 standard but also can produce gross inaccuracies in the results 9 4 1 Intermediate Result Figure 9 7 illustrates the intermediate result format The intermediate result s expone
330. hen the handler attempts to write to memory and should be checked before attempting the write to prevent nesting of exceptions if required by the operating system The following general bus fault examples indicate the resulting contents of the access error stack frame fields 1 All Read Access Errors SSW RW 1 TT 0 TM 1 or 5 The FA field contains the logical address of the fault The WB1S and WB2S fields are zero and only WB3S can indicate an additional write back 2 Cache Push Physical Bus Error SSW RW 0 TT 0 TM 0 The assertion of TEA causes this error when a cache push bus cycle is in progress The FA field contains the physical address of the fault and the WB1S field is ignored All four long words of the data for a push are contained in L W3 LWO regardless of the size of the transfer The size of the transfer is indicated in the SIZE field of the SSW and can be either a line or long word If a line is indicated all four long words need to be pushed out If a long word is indicated all four long words can be written out or bits 3 and 2 of the FA field can be evaluated to indicate which long words need to be written out to memory 3 2 1 and 0 indicate LW3 LW2 LW1 LWO respectively The WB2S and WBSS fields indicate up to two additional write backs If WB2S is valid and if it indicates a MOVE16 instruction no data should be written out for that write back slot 3 Normal Write Physical Bus Erro
331. higher than maximum rated voltages to this high impedance circuit Reliability of m operation is enhanced if unused inputs are tied to an appropriate logic voltage level e g either GND or Vcc Minimum Operating Ambient o C 7 2 Thermal Characteristics Characteristic Symbol Vale Rating Thermal Resistance Junction to Case JC 3 Thermal Resistance Junction to Case Surface Mount Package MOTOROLA M68040 USER S MANUAL C 19 C 7 3 DC Electrical Specifications cc 3 3 vac 10 w ee os v e ee P Input Leakage Current 0 5 2 4 V During Normal Operation Only AVEC BCLK BG CDIS MDIS IPLx RSTI SCx lin TBD TBD TBI TLNx TCI TEA Hi Z Off State Leakage Current 0 5 2 4 V During Normal Operation An BB CIOUT Dn LOCK LOCKE R W SIZx TA TDO ITSI TBD TBD TLNx TS TTx UPAx Signal Low Input Current 0 8 V HL TBD TBD mA TMS TDI Signal High Input Current 2 0 V TBD TBD mA TMS TDI Output High Voltage 5ma V opat 8 capactanced 1 There is MDIS on the 68 040 2 Capacitance is periodically sampled rather than 10096 tested C 7 4 Power Dissipation Worst Case Vcc 3 6 V TA 0 C LPSTOP Mode No output loads not
332. hips to Clocks Inputs to the M68040 other than the IPL2 IPLO and RSTI signals are synchronously sampled and must be stable during the sample window defined by tsu thi and tho see Figure 7 1 to guarantee proper operation The asynchronous IPLx and RSTI signals are also sampled on the rising edge of BCLK but are internally synchronized to resolve the input to a valid level before using it Since the timing specifications for the M68040 are referenced to the rising edge of BCLK they are valid only for the specified operating frequency and must be scaled for lower operating frequencies 7 2 M68040 USER S MANUAL MOTOROLA 7 2 DATA TRANSFER MECHANISM Figure 7 2 illustrates how the bus designates operands for transfers on a byte boundary System The integer unit handles floating point operands as a sequence of related long word operands These designations are used in the figures and descriptions that follow BYTE 3 BYTE2 BYTE1 BYTE 0 31 24 23 16 15 8 7 0 MOST SIGNIFICANT BYTE he ERR LEAST SIGNIFICANT BYTE LONG WORD OPERAND MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE WORD OPERAND Figure 7 2 Internal Operand Representation Figure 7 3 illustrates general multiplexing between an internal register and the external bus The internal register connects to the external data bus through the internal data bus and multiplexer The data multiplexer establishes the necessary connections for different combinations of address and data sizes
333. ialized or serialized then the access is cache inhibited The caching operation is identical for both cache inhibited modes If the CM field of a matching address indicates either nonserialized or serialized modes the cache controller bypasses the cache and performs an external bus transfer The data associated with the access is not cached internally and the cache inhibited out signal is asserted during the bus transfer to indicate to external memory that the access should not be cached If the data cache line is already resident in an internal cache then the data cache line is pushed from the cache if it is dirty or the data cache line is invalidated if it is valid If the CM field indicates serialized then the sequence of read and write accesses to the page is guaranteed to match the sequence of the instruction order Without serialization the IU pipeline allows read accesses to occur before completion of a write back for a previous instruction Serialization forces operand read accesses for an instruction to occur only once by preventing the instruction from being interrupted after the operand fetch stage Otherwise the instruction is aborted and the operand is accessed when the instruction is restarted These guarantees apply only when the CM field indicates the serialized mode and the accesses are aligned Regardless of the selected cache mode locked accesses are implicitly serialized The TAS CAS and CAS2 instructions use l
334. ide could also produce an inexact result and cause 2 to be set in the FPCR EXC byte Note that only one inexact exception vector number is generated by the processor If either of the two inexact exceptions is enabled the processor fetches the inexact exception vector and the user INEX exception handler is initiated INEX refers to both exceptions in the following paragraphs The 2 exception is the condition that exists when any operation except the input of a packed decimal number creates a floating point intermediate result whose infinitely precise mantissa has too many significant bits to be represented exactly in the selected rounding precision or in the destination data format If this condition occurs the INEX2 bit is set in the FPSR EXC byte and the infinitely precise result is rounded Table 9 15 lists these rounding mode values Table 9 15 Divide by Zero Rounding Mode Values Rounding Mode The representable value nearest to the infinitely precise intermediate value is the result If the two nearest representable values are equally near a tie then the one with the least significant bit equal to zero even is the result This is sometimes referred to as round nearest even The result is the value closest to and no greater in magnitude than the infinitely precise intermediate result This is sometimes referred to as the chip mode since the effect is to clear the bits to the right of the rounding point The
335. ident or that the logical address is out of bounds All other bits in the descriptor are ignored When an invalid descriptor is encountered an ATC entry is created for the logical address with the resident bit in the MMUSR clear 10 or 11 Resident These codes indicate that the page is resident UR User Reserved These single bit fields are reserved for use by the user W Write Protected Setting the W bit in a table descriptor write protects all pages accessed with that descriptor When the W bit is set a write access or a read modify write access to the logical address corresponding to this entry causes an access error exception to be taken X Motorola Reserved These bit fields are reserved for future use by Motorola MOTOROLA M68040 USER S MANUAL 3 15 3 2 3 Translation Table Example Figure 3 13 illustrates an access example to the logical address 76543210 while in the supervisor mode with an 8 Kbyte memory page size The field of the logical address 3B is mapped into bits 8 2 of the SRP value to select a 32 bit root table descriptor at a root level table The selected root table descriptor points to the base of a pointer level table and the PI field of the logical address 15 is mapped into bits 8 2 of this base address to select a pointer descriptor within the table This pointer table descriptor points to the base of a page level table and the PGI field of the logical address 1 is mapped into bits 6 2 of th
336. ignals The rising edge of the internally phase locked PCLK is aligned with the rising edge of BCLK and the two PCLK cycles corresponding to each BCLK cycle are divided into four states T1 T4 Most outputs change during state T4 whether transitioning between a driven and high impedance state or switching between assert and MOTOROLA M68040 USER S MANUAL 7 1 negate logic levels The exceptions to this rule are the and BB signals that transition between logic levels during T4 but transition from a driven state to a high impedance state during T1 The input setup time tsu input hold time output hold time tho and delay time tg illustrated in Figure 7 1 are described in the AC electrical timing specifications in Section 11 MC68040 Electrical and Thermal Characteristics INTERNALLY PHASE LOCKED n T T3 T4 n PCLK lt gt gt lt th tho OUTPUTS lt lt 50 tj INPUTS NOTES 1 tq Propagation delay of signal relative to BLK rising edge 2 14 Propagation delay of signal relative to PCLK falling edge td td 1 2 PCLK except for TIP TA BB when used as outputs 3 tho Output hold time relative to BCLK rising edge 4 tho Output hold time relative to BCLK rising edge tho th 1 2 PCLK 5 tsu Required input setup time relative to BCLK rising edge 6 thi Required input hold time relative to BCLK rising edge Figure 7 1 Signal Relations
337. illusion that it never existed Otherwise the M68040FPSP UNFL exception handler returns the processor to normal processing b If the user UNFL exception handler is enabled the M68040FPSP UNFL exception handler restores the FPU to its exceptional state cleans up the stack to the conditions prior to execution and continues instruction execution at the user UNFL exception handler Once the M68040FPSP UNFL exception handler recognizes the operand error as a maskable condition it does not modify the destination or pass control to the user UNFL exception handler The user UNFL exception handler must execute an FSAVE as its first floating point instruction At this point the destination contains the rounding mode values listed in Table 9 13 and the user UNFL exception handler can choose to modify these values The E3 and E1 bits of the floating point state frame need to be examined to determine which fields on the floating point state frame are valid E3 always takes precedence and must always be serviced first Table 9 16 lists the floating point state frame fields for OVFL exceptions with set or with clear and E1 set It is possible for an FADD FSUB FMUL and FDIV to report a post instruction exception although these instructions normally generate a pre instruction exception The following example illustrates why a post instruction exception is generated FADD FP2 FPO this instruction generates an underflow exception FMOVE
338. illustrating the relationship of these five states with an example of an external bus arbiter circuit Table 7 6 lists the five states and the conditions that indicate them 7 46 M68040 USER S MANUAL MOTOROLA BG ATSI A BBI BG A TSI A gt PROTOCOL VIOLATION BBO DRIVEN BY MC68040 THREE STATED BBI A AIBR A TSI BBI A ABR ATSI BG A TIP BG A ENDCYCLE A TIP IMPLICIT 86 f 880 DR NEN BY BG AIBR BBO DRIVEN BY BG A MC68040 THREE STATED BG A ENDCYCLE ENDCYCLE A BBI A BG ENDCYCLE A ENDCYCLE A A A IBR ENDCYCLE A BBI A BG A __ SNOOP BBO DRIVEN BY 68040 THREE STATED BBT lt BB ENDCYCLE IBR Internal bus request signal see schematic below BBO BBI Bus busy driven by alternate bus master TSI Transfer start as an input sampled by the MC68040 ENDCYCLE Whatever terminates a bus transaction whether it is normal bus error or retried Note im that false burst cycles are treated as a line IBR BR transaction False locked transactions are treated the same as any other bus cycle _____ __ __ 040 may not transition if an active bus gt cycle is terminated with a bus error and BG is asserted Indicates the signal is asserted for that device Figure 7 30 M68040 Internal Interpre
339. in normal processing During exception processing the processor changes from user to supervisor mode Exception processing saves the current value of the SR on the active supervisor stack and then sets the S bit forcing the processor into the supervisor mode To return to the user mode a system routine must execute one of the following instructions MOVE to SR ANDI to SR EORI to SR ORI to SR or RTE which execute in the supervisor mode modifying the S bit of the SR After these instructions execute the instruction pipeline is flushed and is refilled from the appropriate address space MC68040 integrates the functions of the IU FPU and MMU The registers depicted in the programming model see Figure 1 2 provide operand storage and control for these three units The registers are partitioned into two levels of privilege modes user and supervisor The user programming model is the same as the user programming model of the MC68030 which consists of 16 general purpose 32 bit registers and two control registers The MC68040 user programming model also incorporates the MC68881 MC68882 programming model consisting of eight 80 bit floating point data registers a floating point control register a floating point status register and a floating point instruction address register 1 6 M68040 USER S MANUAL MOTOROLA Only system programmers use the supervisor programming model to implement operating system functions I O control an
340. in a page level table Similarly for 4 Kbyte pages the six bits of the PGI field are multiplied by 4 shifted to the left by two bits and concatenated with the fetched pointer level descriptor s upper 24 bits to produce the physical address of the 4 Kbyte page descriptor The upper 20 bits of the page descriptor are the page frame s physical address There are 64 4 Kbyte page descriptors in a page level table Write protect status is accumulated from each level s descriptor and combined with the status from the page descriptor to form the ATC entry status The M68040 creates the ATC entry from the page frame address and the associated status bits and retries the original bus access Refer to 3 3 Address Translation Caches for details on ATC entries If the descriptor from a page table is an indirect descriptor the page descriptor pointed to by this descriptor is fetched Invalid descriptors can be used at any level of the tree except the root When a table search for a normal translation encounters an invalid descriptor the processor takes an access fault exception The invalid descriptor can be used to identify either a page or branch of the tree that has been stored on an external device and is not resident in memory or a portion of the translation table that has not yet been defined In these two cases the exception routine can either restore the page from disk or add to the translation table Figures 3 9 and 3 10 illustrate detailed flowcharts
341. in supervisor state FRESTORE lt ea gt then FPU State Frame Internal State else TRAP FSAVE If in supervisor state FSAVE ea then FPU Internal State State Frame else TRAP FScc If condition true FScc SIZE ea then 1s e Destination else 05 e Destination FSGLDIV FPn Source 2 FPn FSGLDIV fmt ea FPn FSGLDIV X FPm FPn FSGLMUL Source x FPn e FPn FSGMUL lt fmt gt ea FPn FSGLMUL X FPm FPn FSQRT Square Root of Source FPn FSQRT fmt ea FPn FSQRT X FPm FPn FSQRT X FPn FrSQRT lt fmt gt lt ea gt FPn3 FrSQRT FPm FPn3 FrSQRT FPn FSUB2 FPn Source FPn FSUB fmt ea FPn FSUB X FPm FPn FrSUB lt fmt gt ea FPn3 FrSUB X FPm FPn3 FTRAPcc If condition true FTRAPcc then TRAP FTRAPcc W lt data gt FTRAPcc L lt data gt FTST2 Condition Codes for Operand FPCC FTST lt fmt gt lt ea gt FTST X FPm ILLEGAL SSP 2 SSP Vector Offset SSP ILLEGAL SSP 4 SSP PC e SSP SSp 2 SSP SR SSP Illegal Instruction Vector Address 2 PC JSR SP 4 SP PC e SP JSR lt ea gt Destination Address 2 PC LINK SP 4 SP An e SP LINK An dn SP An SP d 25 MOTOROLA M68040 USER S MANUAL 1 17 Table 1 4 Instruction Set Summary Continued LPSTOP If supervisor state LPSTOP lt data gt immediate data SR SR broadcast cycle STOP else TRAP LSL LSR Destination Shifted by count 2 Destination LSd Dx Dy LSd lt data gt Dy LSd ea MOVE S
342. ing back to back single clock instructions the encoding end current instruction remains asserted for as many clock cycles as instructions MOTOROLA M68040 USER S MANUAL 5 13 The following examples are for PSTx encodings 1 An access error terminates an instruction such that the instruction execution stage is not reached In this case an end current instruction is not indicated Exception processing starts the exception stacking status is indicated and then the virtual JMP causes the supervisor branch taken end current instruction encoding 2 An FTRAPcc that does not take an exception ending with the end current instruction encoding The exception stacking status is indicated and then reaches the supervisor branch taken end current instruction encoding if the FTRAPcc ends in an exception 3 Two simultaneous interrupt exception processing sequences follow an ADD instruction The ADD instruction ends with end current instruction followed by exception stacking followed by branch taken end current instruction followed by exception stacking followed by branch taken end current instruction 4 An RTE instruction follows an ADD instruction The end current instruction is followed by RTE executing followed by a branch taken end current instruction 5 9 2 Bus Clock BCLK This input signal is used as a reference for all bus timing It is a TTL compatible signal and cannot be gated off Refer to Section 11
343. ing not to use this capability Certain precautions must be observed to ensure that this logic does not interfere with system operation Refer to 6 5 Disabling the IEEE Standard 1149 1A Operation MOTOROLA M68040 USER S MANUAL 6 1 6 1 OVERVIEW Figure 6 1 illustrates a block diagram of the M68040 implementation of IEEE standard 1149 14 The test logic includes a 16 state dedicated TAP controller These 16 controller states are defined in detail in the IEEE standard 1149 14 but only 8 are included in this section Test Logic Reset Run Test Idle Capture IR Capture DR Update IR Update DR Shift IR Shift DR The TAP controller provides access to five dedicated signal pins TCK A test clock input that synchronizes the test logic 5 test mode select input with an internal pullup resistor sampled on the rising edge of TCK to sequence the TAP controller TDI A test data input with an internal pullup resistor sampled on the rising edge of TCK TDO A three state test data output actively driven only in the shift IR and shift DR controller states that changes on the falling edge of TCK TRST An active low asynchronous reset with an internal pullup resistor that forces the TAP controller into the test logic reset state The test logic also includes an instruction shift register and two test data registers a boundary scan register and a bypass register The boundary scan register links all device signal pins into the instru
344. ing point subroutine libraries the MC68040 implements the four FPCC bits in hardware instead of only implementing the four IEEE conditions An instruction derives the IEEE conditions when needed For example the programmers of a complex arithmetic multiply subroutine usually prefer to handle special data types such as 9 4 M68040 USER S MANUAL MOTOROLA zeros infinities or NANs separately from normal data types The floating point condition codes allow users to efficiently detect and handle these special values 9 2 3 2 QUOTIENT BYTE The quotient byte see Figure 9 4 provides compatibility with the MC68881 MC68882 FPU This byte contains the seven least significant bits of the unsigned quotient as well as the sign of the entire quotient The quotient bits can be used in argument reduction for transcendentals and other functions For example seven bits are more than enough to determine the quadrant of a circle in which an operand resides The quotient field bits 22 16 remains set until the user clears it QUOTIENT SEVEN LEAST SIGNIFICANT BITS OF QUOTIENT SIGN OF QUOTIENT Figure 9 4 FPSR Quotient Byte 9 2 3 3 EXCEPTION STATUS BYTE The EXC byte see Figure 9 5 contains a bit for each floating point exception that can occur during the most recent arithmetic instruction or move operation The start of most operations clears this byte however operations that cannot generate floating point exceptions do not clear this b
345. ion Since the FMOVE to from the FPCR FPSR or FPIAR and FMOVEM instructions cannot generate floating point exceptions these instructions do not modify the FPIAR However 9 6 M68040 USER S MANUAL MOTOROLA they can be used to read the FPIAR an exception handler without changing the previous value A reset or a restore operation of the null state clears the FPIAR 9 3 FLOATING POINT DATA FORMATS AND DATA TYPES The M68000 floating point model MC68881 MC68882 MC68040 supports the following data formats single precision double precision extended precision and packed decimal The M68000 floating point model supports the following data types normalized zeros infinities denormalized numbers and NANs The MC68040 supports part of the M68000 floating point model in hardware Table 9 2 lists the data formats and data types supported by the MC68040 Tables 9 3 through 9 6 summarize the floating point data formats and data types details For further information on the data formats and data types refer to the M68000UM AD M68000 Family Programmer s Reference Manual Table 9 2 MC68040 FPU Data Formats and Data Types Data Formats Single Double Extended Packed Long Number Precision Precision Precision Decimal Byte Word Word Types Real Real Real Real Integer Integer Integer Normalized LT MEN NGC CUNT ES mer a NAN
346. ion flushes all entries The PFLUSH instruction flushes a user or supervisor entry with a specified logical address The PFLUSHAN and PFLUSHN instruction variants qualify entry selection further by flushing only entries that are nonglobal indicated by a cleared G bit in the entry 3 7 3 PTEST The PTEST instruction performs a table search operation for a specified function code and logical address and sets the appropriate bit fields in the MMUSR to indicate conditions encountered during the search PTEST automatically flushes the corresponding entry from the cache before searching the tables and loads the latest information from the translation tables into the ATC The exception routines of the operating system can use this instruction to identify MMU faults PTEST is primarily used in access error exception handlers For example if a bus error has occurred the handler can execute an instruction sequence such as the following sequence MOVE B A7 offset1 DO Copy transfer modifier field from stack frame MOVEC DO DFC into DFC register MOVEA L A7 offset2 A0 Copy fault address from stack frame into address register PTESTW 0 Test address in AO with function code in DFC registers The transfer modifier field copied into the destination function code DFC register indicates whether the faulted access was a supervisor or user mode access and whether it was an instruction prefetch or data access The PTEST instruction uses the DFC value to d
347. ion codes Function codes can be considered extensions of the 32 bit logical address that optionally provides as many as eight 4 Gbyte address spaces The processor automatically generates function codes to select address spaces for data and programs at the user and supervisor modes Certain instructions use the SFC and DFC registers to specify the function codes for operations MOTOROLA M68040 USER S MANUAL 2 7 2 2 2 5 CACHE CONTROL REGISTER The CACR contains two enable bits that allow the instruction and data caches to be independently enabled or disabled Setting an enable bit enables the associated cache without affecting the state of any lines within the cache A hardware reset clears the CACR disabling both caches 2 8 M68040 USER S MANUAL MOTOROLA SECTION 3 EXCEPT MC68EC040 AND 68 040 NOTE This section does not apply to the 68 040 and MC68ECO040V Refer to Appendix 68 040 for details All references to M68040 in this section only refer to the MC68040 68040 and MC68LC040 The M68040 supports a demand paged virtual memory environment Demand means that programs request memory accesses through logical addresses and paged means that memory is divided into blocks of equal size called page frames Each page frame is divided into pages of the same size The operating system assigns pages to page frames as they are required to meet the needs of the program
348. ions are transparent to system operation The user must provide some form of external synchronization to achieve meaningful results since there is no internal synchronization between TCK and BCLK The second function of the SAMPLE PRELOAD instruction is to initialize the boundary scan register output cells before selecting EXTEST which is accomplished by ignoring data being shifted out of TDO while shifting in initialization data The update DR state can then be used to initialize the boundary scan register and ensure that known data and output state will occur on the outputs after entering the EXTEST instruction 6 2 4 DRVCTL T The DRVCTL T instruction is a Motorola public instruction that provides the ability to select one of two output drivers on a pin by pin basis It is intended for use with EXTEST or SHUTDOWN to provide an IEEE compatible environment to select the output drivers for board level test environments This instruction allows data in the boundary scan register to select the output driver A logic zero in the appropriate boundary scan output cell see Table 6 1 selects the large buffer and a logic one selects the small buffer see Section 7 Bus Operation Data captured in the capture DR state for this instruction is identical to that captured during EXTEST output data cells for outputs and pin state for inputs Note that no data relevant to the drive control function is captured during the capture DR state 6 4 M68040 USER S MANU
349. is base address to select a page descriptor within the table 3 2 4 Variations in Translation Table Structure Several aspects of the MMU translation table structure are software configurable allowing the system designer flexibility to optimize the performance of the MMUS for a particular system The following paragraphs discuss the variations of the translation table structure 3 2 4 1 INDIRECT ACTION The M68040 provides the ability to replace an entry in a page table with a pointer to an alternate entry The indirection capability allows multiple tasks to share a physical page while maintaining only a single set of history information for the page i e the modified indication is maintained only in the single descriptor The indirection capability also allows the page frame to appear at arbitrarily different addresses in the logical address spaces of each task 3 16 M68040 USER S MANUAL MOTOROLA LOGICAL ADDRESS ROOT INDEX POINTER INDEX PAGE INDEX PAGE OFFSET 76543210 0 1 1 1 0 1 1 0 0 1 0 1 0 1 0 00 0 I X XX X X X X X X X X X X TABLE ENTRY 3B 15 01 ADDRESS OFFSET EC 54 04 TABLE 00 TABLE 00 TABLE 00 TABLE 3B TABLE 15 SUPERVISOR SRP MODE 5 5 538 500001800 15 500003000 01 FRAME ADDRESS TABLE 7F TABLE 1F
350. is enabled it is the responsibility of the user OVFL exception handler to look for this situation The user OVFL exception handler examines the E3 bit of the floating point state frame to exit from this exception handler If the E3 bit is set it must be cleared prior to restoring the floating point frame through the FRESTORE instruction If the bit is clear and the bit is set the floating point state frame is discarded The RTE instruction must be executed to return to normal instruction flow 9 7 5 Underflow An underflow exception occurs when the intermediate result of an arithmetic operation is too small to be represented as a normalized number in a floating point data register or memory using the selected rounding precision An arithmetic operation is too small when the intermediate result exponent is less than or equal to the minimum exponent value of the selected rounding precision Underflow is not detected for intermediate result exponents that are equal to the extended precision minimum exponent since the explicit integer part bit permits representation of normalized numbers with a minimum extended precision exponent Underflow can only occur when the destination format is single double or extended precision When the destination format is byte word or long word the conversion underflows to zero without causing either an underflow or an operand error At the end of any operation that could potentially underflow the intermedi
351. it is set in the intermediate result The IEEE 754 standard specifies that tie cases should be handled in this manner If the destination data format is extended and there is a difference between the infinitely precise intermediate result and the round to nearest result the relative difference is 2 64 the value of the guard bit This error is equal to one half of the least significant bit s value and is the worst case error that can be introduced when using the RN mode Thus the term one half unit in the last place correctly identifies the error bound for this operation This error specification is the relative error present in the result the absolute error bound is equal to 2 x 2 64 The following example illustrates the error bound for the other rounding modes Pesut integer G3BitFraction Guard Round Sticky Roundedto Nearest_ x The difference between the infinitely precise result and the rounded result is 2 64 2 65 2 66 which is slightly less than 2 63 the value of the least significant bit Thus the error bound for this operation is not more than one unit in the last place For all arithmetic operations the FPU meets these error bounds providing accurate and repeatable results 9 5 POSTPROCESSING OPERATION Most operations end with a postprocessing step The FPU provides two steps in postprocessing First the condition code bits in the FPSR are set or cleared at th
352. ite Transfers Table 7 5 TA and TEA eee Results Bus Error Terminate and Take Bus Error O Possibly Deferred Retry Operation Terminate and Retry Normal Terminate and Continue 7 6 1 Bus Errors The system hardware can use the TEA signal to abort the current bus cycle when a fault is detected A bus error is recognized during a bus cycle when TA is negated and TEA is asserted When the processor recognizes a bus error condition for an access the access is terminated immediately A line access that has TEA asserted for one of the four long word transfers aborts without completing the remaining transfers regardless of whether the line transfer uses a burst or burst inhibited access When TEA is asserted to terminate a bus cycle the M68040 can enter access error exception processing immediately following the bus cycle or it can defer processing the exception The instruction prefetch mechanism requests instruction words from the instruction memory unit before it is ready to execute them If a bus error occurs on an instruction fetch the processor does not take the exception until it attempts to use the instruction Should an intervening instruction cause a branch or should a task switch occur the access error exception for the unused access does not occur Similarly if a bus error is detected on the second third or fourth long word transfer for a line read access an access error exception is taken only if the execution unit i
353. ited 7 44 Initial Power On Reset 7 45 Normal Reset 0 7 46 Multiplexed Address and Data Bus Line 7 47 DLE Mode Block 7 48 DLE versus Normal Data Read 8 1 General Exception Processing Flowchart 8 2 General Form of Exception Stack Frame 8 3 Interrupt Recognition Examples seen 8 4 Interrupt Exception Processing Flowchartl 8 5 Reset Exception Processing 8 6 Flowchart of RTE Instruction for Throwaway Four Word Frame 8 7 Special Status Word Format oe E arenae un 8 8 Write Back Status Formal octo ra ba eei ue e 9 1 Floating Point User Programming 9 2 Floating Point Control Register 9 3 FPSR Condition Code 1 9 4 9 5 Exception Status Byte 9 6 Accrued Exception 9 7 Intermediate Result F
354. ith any other data type is unordered i e it is impossible to determine if a NAN is bigger or smaller than an in range number the compare instruction sets the NAN condition code bit when an unordered compare is attempted All arithmetic instructions also set the FPCC NAN bit if the result of an operation is a NAN The conditional instructions interpret the NAN condition code bit equal to one as the unordered condition The IEEE 754 standard defines four conditions equal to EQ greater than GT less than LT and unordered UN In addition the standard only requires the generation of the condition codes as a result of a floating point compare operation The FPU tests for these conditions and 28 others at the end of any operation affecting the condition codes For purposes of the floating point conditional branch set byte on condition decrement and branch on condition and trap on condition instructions the MC68040 logically combines the four FPCC bits to form 32 conditional tests The 32 conditional tests are separated into two groups 16 that cause an exception if an unordered condition is present when the conditional test is attempted IEEE nonaware tests and 16 that do not cause an exception IEEE aware tests The set of IEEE nonaware tests is best used when porting a program from a system that does not support the IEEE 754 standard to a conforming system or when generating high level language code that does not support IEEE flo
355. izes TA at the end of the last read transfer for the locked bus cycle it negates TIP during the first half of the next clock Clock Idle Cl The processor does not assert any new control signals during the idle clock states but it may begin the modify portion of the cycle at this time The R W signal remains in the read mode until C3 to prevent bus conflicts with the preceding read portion of the cycle the data bus is not driven until C4 Clock 3 C3 During the first half of C3 the processor places valid values on the address bus and transfer attributes and drives R W low for a write cycle The processor asserts TS to indicate the beginning of a bus cycle The TIP signal is also asserted at this time to indicate that a bus cycle is active LOCKE is asserted during C3 for the last write transfer of the locked sequence If multiple write transfers are required for misaligned operands or multiple operands LOCKE is asserted only for the final write transfer The external arbiter can use this indication to distinguish between two back to back locked bus cycles and allow arbitration between them Clock 4 C4 During the first half of C4 the processor negates TS and drives the appropriate bytes of the data bus with the data to be written All other bytes are driven with undefined values The selected device uses RAN 5171 SIZO A1 and AO to latch the information on the data bus Any or all of the bytes D31 D24 023 016 015 08
356. ks This instruction asserts internal system reset activates an internal keep alive clock and selects the bypass register Internal decoding of the instruction selects the bypass register and the test logic not the system logic has control of the I O ports Note that initializing the boundary scan data register and then selecting the SHUTDOWN instruction provides a clamping function The test logic controls the I O state and the bypass register is selected 6 2 6 PRIVATE Motorola reserves this instruction for manufacturing use The instruction does not change pin as defined for system operation 6 2 7 DRVCTL S The DRVCTL S instruction controls the output driver selection on a pin by pin basis This instruction allows data in the boundary scan register to select the output driver during the update DR state when the system logic has control of the signal directions and levels A logic zero selects the large buffer or driver a logic one selects the small buffer or driver see Table 6 1 The DRVCTL S instruction is intended to be used in system applications and not in test applications In system applications the system logic has control of the signal pin I O directions and levels whereas test applications the 1149 1 test logic has control of it It therefore differs from DRVCTL T in that this instruction does not invoke the internal keep alive clock it does not assert the internal reset and the system logic not the t
357. l data output from the TAP The TDO output can be placed in a high impedance mode to allow parallel connection of board level test data paths 5 12 5 Test Reset TRST Not on 68040 and 68 040 This input signal provides an asynchronous reset of the TAP controller 5 13 POWER SUPPLY CONNECTIONS The M68040 requires connection to a Vcc power supply positive with respect to ground The and ground connections are grouped to supply adequate current to the various sections of the processor Section 12 Ordering Information and Mechanical Data describes the groupings of and ground connections MOTOROLA M68040 USER S MANUAL 5 15 5 14 SIGNAL SUMMARY Table 5 7 provides a summary of the electrical characteristics of the signals discussed in this section Table 5 7 Signal Summary SigmalName Mnemonic Tnree state Lo Lo Lo Lo Lo Lo Lo Lo Lo Lo Lo Lo Lo Lo Lo Lo Lo Lo so ma Gem x T m sn cache Disable cs m Data Bus Data Latch Enable Ground Interrupt Pending D GN Ground Output Interrupt Priority Level Bus Lock Bus Lock End Memory Inhibit M Output MMU Disable Processor Clock Processor Status PST3 PSTO Output High Input Output High Low Read Write Reset In
358. lat Pack MC68LC040 TOP VIEW Internal Logic 5 8 10 27 28 33 55 68 95 108 121 162 9 32 56 69 81 94 100 109 122 136 149 130 135 174 161 175 Output Drivers 16 20 25 40 46 52 59 65 72 78 84 85 91 43 49 62 75 88 102 115 128 143 155 168 98 105 112 118 125 132 139 140 146 152 181 158 165 171 178 184 12 6 M68040 USER S MANUAL MOTOROLA 12 2 6 MC68EC040 Quad Flat Pack MC68EC040 TOP VIEW Internal Logic 5 8 10 27 28 33 55 68 95 108 121 162 9 32 56 69 81 94 100 109 122 136 149 130 135 174 161 175 Output Drivers 16 20 25 40 46 52 59 65 72 78 84 85 91 43 49 62 75 88 102 115 128 143 155 168 98 105 112 118 125 132 139 140 146 152 181 158 165 171 178 184 MOTOROLA M68040 USER S MANUAL 12 7 12 2 7 MC68040V MC68bECO040V Quad Flat Pack m 5149 A25 1150 gt gt MC68040V and MC68EC 040V 161 22162 VIEW gt A gt 5 6 4 this pin is called JS1 All these pins are in the JTAG scan chain On an MC68040 design JS2 GND on an 68060 design JS2 CLK 12 8 M68040 USER S MANUAL MOTOROLA 12 3 MECHANICAL DATA Figure 12 1 illustrates the MC68040 MC68LC040 and 68 040 PGA package dimensions Figure 12 2 illustrates the MC680
359. le snoop implicit ownership park and active bus cycle There are two characteristics that determine these five states whether the three state logic determines if the M68040 drives the bus and how the M68040 drives BB If neither the processor nor the external bus arbiter asserts BB then an external pullup resistor drives BB high to negate it Note that the relationship between the internal BR and the external BR is best described as a synchronous delay off BCLK The idle state occurs when the M68040 does not have ownership of the bus and is not in the process of snooping an access In the idle state BB is negated and the M68040 does not drive the bus The snoop state is similar to the idle state in that the M68040 does not have ownership of the bus The snoop state differs from the idle state in that the M68040 is ready to service snooped transfers Otherwise the status of BB and the bus is identical The implicit ownership state indicates that the M68040 owns the bus The M68040 explicitly owns the bus when it runs a bus cycle immediately after being granted the bus If the processor has completed at least one bus cycle and no internal transfers are pending the processor drives the bus with undefined values entering the park state In either case BG remains asserted The simultaneous assertion of BR TIP and TS allows the processor to leave the park state and enter the active bus cycle state Figure 7 30 is a bus arbitration state diagram
360. ler If the E3 bit is set it must be cleared prior to restoring the floating point frame through the FRESTORE instruction If the bit is clear and the 1 bit MOTOROLA M68040 USER S MANUAL 9 35 is set the floating point frame is discarded The RTE instruction must be executed to return to normal instruction flow 9 7 6 Divide by Zero This exception happens when a zero divisor occurs for a divide instruction or when a transcendental function is asymptotic with infinity as the asymptote Table 9 14 lists the instructions that can cause the divide by zero exception Note that only the FDIV and FSGLDIV instructions are native to the MC68040 The other conditions occur only if the M68040FPSP is used When a divide by zero is detected the DZ bit is set in the FPSR EXC byte The divide by zero exception only has maskable exceptional conditions therefore no M68040FPSP intervention is needed An exception is taken only if the DZ bit is set in FPSR EXC byte and the corresponding bit in the FPCR ENABLE byte is set a If the user divide by zero exception handler is enabled an infinity with the sign set to the exclusive OR of the signs of the input operands is stored in the destination floating point data register No exception is taken b If the user divide by zero exception handler is disabled the destination floating point data register is not modified and the exception is reported as a pre instruction exception when the next floating point i
361. ller after which the contents of the buffer are invalidated without being copied into the cache The assertion of is ignored during the second third or fourth cycle of a burst operation and is ignored for write operations A bus error occurring during a burst operation causes the burst operation to abort If the bus error occurs during the first cycle of a burst the data from the bus is ignored If the access is a data cycle exception processing proceeds immediately If the cycle is for an instruction prefetch a bus error exception is pending The bus error is processed only if the IU attempts to use either instruction word Refer to Section 7 Bus Operation for more information about pipeline operation For either cache when a bus error occurs on the second cycle or later the burst operation is aborted and the line buffer is invalidated The processor may or may not take an exception depending on the status of the pending data request If the bus error cycle contains a portion of a data operand that the processor is specifically waiting for e g the second half of a misaligned operand the processor immediately takes an exception Otherwise no exception occurs and the cache line fill is repeated the next time data within the line is required In the case of an instruction cache line fill the data from the aborted cycle is completely ignored On the initial access of a line read a retry indicated by the assertion of TA an
362. logic zero Figure 6 2 illustrates the bypass register SHIFT DR FROM TDI TO TDO CLOCK DR Figure 6 2 Bypass Register 6 3 BOUNDARY SCAN REGISTER The 184 bit boundary scan register uses the TAP controller to scan user defined values into the output buffers capture values presented to input pins and control the direction of bidirectional pins The instruction shift register cell nearest TDO i e first to be shifted out is defined as bit zero The last bit to be shifted out is bit 183 This register includes cells for all device signal pins and clock pins along with associated control signals The M68040 boundary scan register consists of three cell structure types O Latch and IO Ctl that are associated with a boundary scan register bit All boundary scan output cells capture the logic level of the device output latch during the capture DR state Figures 6 3 through 6 5 illustrate these three cell types Figure 6 6 illustrates the general arrangement of these cells 6 6 M68040 USER S MANUAL MOTOROLA 1 DRVCTL T AND SHUTDOWN TO OUTPUT 0 OTHERWISE SHIFT DR TONEXTCELL DRIVER SELECT DATA FROM SYSTEM LOGIC TO OUTPUT BUFFER FROM CLOCK DR UPDATE DR2 UPDATE DR1 LAST DRVCTL X DRVCTL X CELL Figure 6 3 Output Latch Cell O Latch TO NEXT CELL TO SYSTEM lt IN LOGIC CLOCK DR FROM SHIFT DR LAST CELL Figure 6
363. lso refer to the unimplemented data types in the M68040FPSP When the processor encounters an unsupported data type the procedure taken is identical to that used when an unimplemented instruction is taken Unsupported data types with operands that have opclass 010 or 000 register to register or memory to register instructions cause a pre instruction exception When an unsupported data type is detected for opclass 011 register to memory instructions a post instruction exception is generated immediately A format 0 for the pre instruction exception or format 3 for the post instruction exception stack frame is saved and vector number 55 is fetched A denormalized value generated as the result of a floating point operation generates a nonmaskable underflow exception instead of an unsupported data type exception Table 9 16 lists the floating point state frame fields for unsupported data type exceptions resulting from the execution of opclass 010 or 000 register to register or memory to register instructions and opclass 011 register to memory instructions defined for the use by the supervisor exception handler A denormalized or unnormalized extended precision source or destination operand is copied directly without modification to ETEMP or FPTEMP fields in the floating point state frame If a packed decimal real source operand is specified the upper 32 bits of the operand are copied to the FPTEMP field and the lower 64 bits are copied
364. lted access are repeated If a continuation bit is set for a pending trace unimplemented floating point instruction or floating point post instruction exception the processor restores the calculated effective address from the stack frame increments the active supervisor stack pointer by 30 words and immediately begins exception processing MOTOROLA M68040 USER S MANUAL 8 27 for the pending exception The processor sets only one of the continuation bits when the access error stack frame is created If the access error exception handler sets multiple bits operation of the RTE instruction is undefined If the frame format field in the stack frame contains an illegal format code a format exception occurs If a format error or access fault exception occurs during the frame validation sequence of the RTE instruction the processor creates a normal four word or an access error stack frame below the frame that it was attempting to use The illegal stack frame remains intact so that the exception handler can examine or repair the illegal frame In a multiprocessor system the illegal frame can be left so that when appropriate another processor of a different type can use it The bus error exception handler can identify bus error exceptions due to instruction faults by examining the TM field in the SSW of the access error stack frame For user and supervisor instruction faults the TM field contains 2 and 6 respectively see Figure 8 7 Since the
365. mal operation the JS1 and JSO pin cannot float they must be tied to GND or Vcc directly or through a resistor During board testing these pins retain the functionality of the JTAG scan of the MC68040 for compatibility purposes Refer to Section 6 IEEE 1149 1 Test Access Port JTAG for details concerning IEEE 1149 1 Standard Test Access Port and Boundary Scan Architecture B 3 ACCESS CONTROL UNITS The information in this section replaces the information in Section 3 Memory Management Unit Except 68 040 and 68 040 When reading Section 4 Instruction and Data Caches disregard any references to the MMU remember the functionality of the access control registers has replaced that of transparent translation registers The MC68EC040 contains two independent ACUS one for instructions and one for data Each ACU allows memory selections to be made requiring attributes particular to peripherals shared memory or other special memory requirements The following paragraphs describe the ACUs and the access control registers contained in them B 3 1 Access Control Registers Each ACU has two independent access control registers ACRs The instruction ACU contains the instruction access control registers IACRO and IACR1 The data ACU contains the data access control registers DACRO and DACR1 Both ACRs provide and control status information for access control of memory in the 68 040 Only programs that execute in the supervisor m
366. mented floating point exception to be taken with a new eight word stack frame format 4 The stack frame contains the status register SR program counter PC vector offset effective address of the operand where applicable and PC value of the unimplemented floating point instruction MOTOROLA M68040 USER S MANUAL A 5 5 1 Unimplemented Floating Point Instructions and Exceptions All legal MC68040 and MC68881 MC68882 floating point instructions are defined as unimplemented floating point instructions on the MC68LC040 These instructions generate a format 4 stack frame during exception processing before taking an F line exception These instructions trap as an F line exception and the F line exception handler can emulate them in software to maintain user object code compatibility The MC68LC040 assists the emulation process by distinguishing unimplemented floating point instructions from other unimplemented F line instructions To aid emulation the effective address is calculated and saved in the format 4 stack frame This simplifies and speeds up the emulation process by eliminating the need for the emulation routine to determine the effective address and by providing information required to emulate the instruction on the exception stack frame in the supervisor address space However the floating point instruction can reside in user space therefore the floating point unimplemented exception handler may need to access user instruction
367. mory unit if it is not busy If the second TRAPF instruction N2 in the ea fetch stage requires an operand fetch the write back for MOVE L C stalls in the write back stage since it is a lower priority MOTOROLA M68040 USER S MANUAL 10 5 The separation of calculation and execution in the ea calculate and execute stages allows instruction reordering during compile time to take advantage of potential instruction overlap Figure 10 2 illustrates this overlap for an instruction requiring multiple clocks in the execute stage and with an instruction with a long lead time The execution time for LEA 3 1 indicates that the instruction can be stalled three clocks without affecting execution When the LEA A instruction precedes the ABCD B instruction the execution stalls during C4 C6 equivalent to the LEA lead time while the instruction completes in the ea calculate and ea fetch stages The resulting execution time for the LEA A and ABCD B sequence is eight clocks However if the LEA C instruction follows the ABCD B instruction the LEA stalls in the ea fetch instead during 9 11 The LEA then executes a single clock in the execution stage The resulting execution time for the LEA C and ABCD B sequence is five clocks ea LABEL INSTRUCTION CALCULATE EXECUTE P1 TRAPF 1 1 LEA 24 P C A1 4 3 1 B ABCD 0 1 1 3 LEA 24 P C A1 4 3 1 N1 TRAPF 1 1 N2 TRAPF 1 1 C C5 C
368. n the format exception vector The stacked PC value is the logical address of the instruction that detected the format error MOTOROLA M68040 USER S MANUAL 8 11 8 2 8 Breakpoint Instruction Exception To use the M68040 in a hardware emulator the processor must provide a means of inserting breakpoints in the emulator code and performing appropriate operations at each breakpoint Inserting an illegal instruction at the breakpoint and detecting the illegal instruction exception from its vector location can achieve this However since the VBR allows arbitrary relocation of exception vectors the exception address cannot reliably identify a breakpoint Consequently the processor provides a breakpoint capability with a set of breakpoint exceptions 4848 484F When the M68040 executes a breakpoint instruction it performs a breakpoint acknowledge cycle read cycle with an acknowledge transfer type and transfer modifier value of 0 Refer to Section 7 Bus Operation for a description of the breakpoint acknowledge cycle After external hardware terminates the bus cycle with either TA or TEA the processor performs illegal instruction exception processing 8 2 9 Interrupt Exception When a peripheral device requires the services of the M68040 or is ready to send information that the processor requires it can signal the processor to take an interrupt exception using the active low IPL2 IPLO signals The three signals encode a value of 0 7 IPLO i
369. n to the low power mode of operation the MC68040V and MC68ECO40V provide a low frequency mode of operation This mode of operation can be entered one of in two ways directly from reset by asserting LFO prior to negating RSTI or by asserting LFO prior to generating the interrupt or reset when exiting the low power stop mode In the former case the BCLK input can be changed as long as the frequency is 0 16 MHz and the minimum pulse width constraints are met Normal operation can be resumed through the low power stop mode and deasserting LFO C 2 3 Changing BCLK Frequency The frequency of the BCLK input can be changed only during the low power stop or low frequency modes of operation Once in the low power stop mode and SCD is asserted BCLK can be disabled or its frequency can be changed Reducing the frequency or removing the BCLK input is not required for proper operation but is an additional power saving measure BCLK can be removed during the low power stop mode as an additional System power saving measure However it is not necessary for normal operation and has no effect on the MC68040V s MC68ECO040V s power consumption MOTOROLA M68040 USER S MANUAL 5 2 4 LPSTOP Instruction Summary Operation f Supervisor State Immediate Data SR SR Broadcast Cycle STOP Else TRAP Assembler Syntax LPSTOP lt data gt Attributes Privileged Word Sized Condition Codes Set according to the immediate operand Description See C
370. n vector table and an exception stack frame The following paragraphs describe the vector table and a generalized exception stack frame The M68040 uses a restart exception processing model to minimize interrupt and instruction latency and to reduce the size of the stack frame compared to the frame required for a continuation model Exceptions are recognized at each instruction boundary in the execute stage of the integer pipeline and force later instructions that have not yet reached the execute stage to be aborted Instructions that cannot be interrupted MOTOROLA M68040 USER S MANUAL 8 1 such as those that generate locked bus transfers or access serialized pages are allowed to complete before exception processing begins Exception processing occurs in four functional steps However all individual bus cycles associated with exception processing vector acquisition stacking etc are not guaranteed to occur in the order in which they are described in this section Figure 8 1 illustrates a general flowchart for the steps taken by the processor during exception processing During the first step the processor makes an internal copy of the status register SR Then the processor changes to the supervisor mode by setting the S bit and inhibits tracing of the exception handler by clearing the trace enable T1 and TO bits in the SR For the reset and interrupt exceptions the processor also updates the interrupt priority mask in the SR D
371. nals can be combined with the address decode logic Table 7 1 Data Bus Requirements for Read and Write Cycles Data Bus Sections D23 D16 D15 D8 EIN BYTEn BYTEn BYTEn BYTEn BYTEn BYTEn BYTEn BYTEn BYTEn BYTEn BYTEn BYTEn BYTEn BYTEn BYTEn 7 4 M68040 USER S MANUAL MOTOROLA i UPPER UPPER DATA SELECT D31 D24 UPPER MIDDLE DATA SELECT 023 016 LOWER MIDDLE DATA SELECT D15 D8 LOWER LOWER DATA SELECT 07 00 a Al 5120 5171 PAL16L8 U1 MC68040 Byte Data Select Generation Motorola Worldwide Marketing Training Organization 0 1 SIZO 6171 NC NC NC NC NC GND NC UUD UMD LMD LLD NC NC NC NC VCC UUD A0 A1 directly addressed any size SIZA SIZO enable every byte for long word size SIZ1 SIZO enable every byte for line size UMD A0 A1 directly addressed any size 1 SIZ1 word aligned size is word or line SIZ1 SIZO enable every byte for long word size SIZ1 SIZO enable every byte for line size LMD 1 directly addressed any size SIZ1 SIZO enable every byte for long word size SIZ1 SIZO enable every byte for line size LLD AO A1 directly addressed any size A1 SIZ1 word aligned word or line size SIZ1 SIZO enable every byte for long word size SIZA SIZO enable every byte for line size Figure 7 4 Byte Enable Signal Generati
372. nated with TA PROCESSOR EXTERNAL DEVICE ACKNOWLEDGE INTERRUPT REQUEST INTERRUPT IPEND RECOGNIZED WAIT FOR INSTRUCTION BOUNDARY SET R W TO READ DRIVE A31 A0 TO FFFFFFFF DRIVE UPA1 TO 0 SET SIZE TO BYTE SET TRANSFER TYPE ON TT1 TTO TO 3 PLACE INTERRUPT LEVEL ON 2 0 NEGATE CIOUT ASSERT TS FOR ONE CLOCK ASSERT TIP PROVIDE VECTOR INFORMATION 1 PLACE VECTOR NUMBER ON BYTE 07 00 2 ASSERT TRANSFER ACKNOWLEDGE TA ACQUIRE DATA 1 LATCH VECTOR NUMBER START NEXT CYCLE Figure 7 21 Interrupt Acknowledge Bus Cycle Flowchart Co O Un gt TERMINATE CYCLE 1 REMOVE DATA FROM 07 00 2 NEGATE TA 7 32 M68040 USER S MANUAL MOTOROLA 1 0 N l l l l l l l l l UPAL UPAO l l l l l l l 5171 1 1 1 1 5170 1 l TT1 TTO U i i 2 0 INTERRUPT LEVEL i i i i 1 1 I 1 RW i We E l l l CIOUT i i U l l l l l l l l l l l l l l l l l l l NE i 1 i i i 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 l l l l l l l AVEC D31 D8 VECTOR 4 07 00 lt wane STACK Figure 7 22 Interrupt Acknowledge Bus Cycle Timing 7 5 1 2 AUTOVECTOR INTERRUPT ACKNOWLEDGE BUS CYCLE When the interrupting device cannot s
373. nd is converted to extended precision 2 2 UJ 9 44 M68040 USER S MANUAL MOTOROLA Table 9 16 State Frame Field Information Continued Frame Field SNAN For Opclass 011 Destination operand if any is converted to extended precision OVFL FADD FSUB FMUL FDIV and FSQRT CMDREG3B Encoded Exception Instruction Command Word WBTEMP WBTS WBTE and WBTM equal the intermediate result with mantissa rounded to the correct precision WBTE15 Bit 15 of the intermediate result s 16 bit exponent 0 for overflow MOTOROLA M68040 USER S MANUAL 945 Table 9 16 State Frame Field Information Continued Frame Field OVFL FMOVE to Memory Exception Instruction Command Word UNFL FADD FSUB FMUL FDIV and FSQRT CMDREG3B Encoded Exception Instruction Command Word WBTEMP WBTS WBTE WBTM intermediate result sign biased 15 bit exponent and 64 bit mantissa prior to rounding WBTE15 Bit 15 of the intermediate result s 16 bit exponent 1 for underflow WBTM 1 WBTMO Guard round and sticky of intermediate result s 67 bit mantissa SBIT 9 46 M68040 USER S MANUAL MOTOROLA Table 9 16 State Frame Field Information Concluded Frame Field INEX FMOVE to Register FABS and FNEG WBTS WBTE and WBTM intermediate result sign biased 15 bit exponent and 64 bit mantissa prior to rounding WBTM 1 WBTMO Guard round and sticky of intermediate result s 67 bit mantissa SBIT
374. nding trace exception unimplemented floating point instruction exception or floating point post instruction exception the RTE adjusts the stack to match the pending exception and immediately begins exception processing without requiring the exception to reoccur 8 30 M68040 USER S MANUAL MOTOROLA Table 8 6 Access Error Stack Frame Combinations weis 825 WE3S EasyCleanup Hard Cleanup Main Case 1 1 2 16 3v Data Written Action All Read 1 x x 0 Access Errors 1 X X 1 WB3D Note b All other read cases are not possible PD3 0 PD3 0 WB3D PD3 0 WB2D Note b PD3 0 WB2D WB3D PD3 0 wB2D9 WB1D WB1D WB3D WB1D WB2D Note b WB1D WB2D WB3D WB1D 209 PD3 0 WB3D PD3 0 PD3 0 WB2D Note b PD3 0 WB2D WB3D PD3 0 wB2D9 WB2D WB2D WB3D Write PD3 0 WB2Dd Cache Push Physical Bus Error Normal Write Physical bus 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NOTES a The data memory unit stage is tied up until the bus controller passes the read back through the data memory unit and to the execution stage in the integer unit Therefore no pending write is possible in WB1 or WB2 WBS3 could hold a pending write that was deferred due to operand read or was generated after the read b If any kind of access error is reported and if a MOVE16 write is pending in the WB2 stage then that MOVE16 read must hit in the cache so the MOVE16 can be safely
375. ne 7 4 7 9 Line Write 7 22 Locked 5 7 7 49 7 53 7 55 8 8 Push 4 13 Read 7 4 7 10 7 12 7 32 Read Modify Write 3 21 7 26 7 41 7 45 see also Bus Cycles Locked Write 7 4 7 20 Bus Error 3 22 3 30 4 12 7 37 7 42 7 43 9 21 Bus Operations Access Serialization 7 44 Synchronization 7 44 Conditional Branch 7 50 Data Cache 7 44 Double Bus Fault 8 8 8 18 Exceptions 8 8 Interrupt Pending Procedure 7 30 Locked Transfer 8 8 Misaligned Access 4 3 4 11 10 3 Misaligned Operand 7 6 7 37 Relinquish and Retry 4 12 7 41 7 42 7 55 Reset 7 66 Bus Synchronization 7 44 BYPASS 6 3 Byte Enable Signals 7 4 PAL Equation 7 4 Byte Offset 7 3 M68040 USER S MANUAL INDEX 1 _C Cache 1 4 2 8 Burst Mode Operations 4 11 Data 2 3 2 8 3 1 3 12 7 44 8 7 8 18 Exceptions 8 7 8 18 Instruction Prefetches 4 13 Instruction 3 1 8 7 8 18 Misaligned Accesses 4 11 Page Descriptors 4 5 Replacement Algorithm 4 4 Retry Operation 4 12 Shared Data 4 9 4 10 Cache Coherency 4 10 Cache Controller 3 2 3 28 4 4 4 8 4 12 Cache Inhibited see Caching Modes Cache Line 4 3 D Bit 4 6 Dirty 4 3 Format 4 2 Invalid 4 3 Timing 10 8 V Bit 4 3 Valid 4 3 Caching Modes 4 6 Cache Inhibited 4 7 Copyback 4 6 7 60 Default 4 6 Nonserialized 4 6 Serialized 4 6 Write Through 4 6 Caching Operation 4 3 Calculate Stage see Integer Unit Pipeline CM Field 4 6 5 8 see also Descriptors Conditional
376. newly initiated locked bus access If it detects a locked bus cycle it returns the bus to processor 1 by entering state A Note that even though processor 1 recognizes BG1 is asserted it does not take the bus because processor 1 asserts BB whenever the boundary condition results in processor 1 performing another bus cycle The external arbiter stays in state A until LOCKE is asserted then proceeds to state B to MOTOROLA M68040 USER S MANUAL 7 53 give the bus to processor 2 The arbiter remains in state B until is negated signifying the end of the bus cycle Once state C is reached depending on whether or not processor 2 asserts BR2 and then negates BR2 because of a disregard request condition processor 1 may or may not actively begin a bus cycle If no other bus requests are pending by the time state C is reached processor 2 is in the implicit ownership state If processor 1 asserts BR1 then it is possible for state C to persist for only one clock In this case processor 2 does not have a chance to run any active bus cycles A null bus cycle tenure is better than having the external bus arbiter wait for processor 2 to perform at least one bus cycle before returning bus ownership to processor 1 even though this appears to be a waste of bus arbitration overhead Note that once processor 2 enters the disregard request condition processor 2 reasserts BR anywhere from one clock to an undetermined number of clocks before running another
377. nformation to an external register in which the external hardware attempts to control program execution based on the data that is written with the conditional assertion of TEA is one situation where the NOP instruction can be used to prevent multiple executions If the data cache is enabled and the write cycle results in a hit in the data cache the cache is updated That data in turn may be used in a subsequent instruction before the external write cycle completes Since the M68040 cannot process the bus error until the end of the bus cycle the external hardware cannot successfully interrupt program execution To prevent a subsequent instruction from executing until the external cycle completes the NOP instruction can be inserted after the instruction causing the write In this case access error exception processing proceeds immediately after the write before subsequent instructions are executed This is an irregular situation and the use of the NOP instruction for this purpose is not required by most systems Note that the NOP instruction can also be used to force access serialization by placing before the instruction that reads an device This practice eliminates the need to specify the entire page as serialized noncachable but does not prevent the instruction from being aborted by an exception condition 7 8 BUS ARBITRATION AND EXAMPLES The bus design of the M68040 provides for one bus master at a time either the M68040 or an ex
378. ng Word Write Transfers 7 20 7 4 4 Line Write Transfers 7 22 7 4 5 Read Modify Write Transfers Locked Transfers 7 26 7 5 Acknowledge Bus Cycles a 7 29 7 5 1 Interrupt Acknowledge Bus 7 29 7 5 1 1 Interrupt Acknowledge BUS Cycle Terminated Normally 7 31 7 5 1 2 Autovector Interrupt Acknowledge bus Cycle 7 33 7 5 1 3 Spurious Interrupt Acknowledge 7 34 7 5 2 Breakpoint Interrupt Acknowledge Bus 7 35 7 6 Bus Exception Control 7 36 7 6 1 BUS EIOS ca a Ban 7 37 7 6 2 Retry Operati r is TE 7 41 7 6 3 Double Bus Fall oed re dioere sene eee desde 7 43 7 7 Bus Synchronization suu suu uuu AORERE TE 7 43 7 8 Bus Arbitration And 7 44 7 8 1 Bus 7 45 7 8 2 Bus Arbitration 7 52 7 8 2 1 Dual M68040 Fairness Arbitration 7 52 7 8 2 2 Dual M68040 Prioritized Arbitration 7 54 x M68040 USER S MANUAL MOTOROLA TABLE OF CONTENTS Continued Paragraph Page N
379. ng an operating system to set up the translation tables and MMU registers as required After the translation tables and registers are initialized the E bit of the TCR can be set enabling paged address translation While address translation is disabled the attribute bits for an access that an ATC entry ora TTR normally supplies are zero selecting write through cachable mode no write protection and user page attribute bits cleared RSTI does not affect the P bit of the TCR A reset of the processor does not invalidate any entries in the ATCs or alter the page size A PFLUSH instruction must be executed to flush all existing valid entries from the ATCs after a reset operation and before translation is enabled PFLUSH can be executed even if the E bit is cleared 3 6 2 Effect of MDIS on Address Translation The assertion of MDIS prevents the MMUs from performing ATC searches and the execution unit from performing table searches With address translation disabled logical addresses are used as physical addresses MDIS disables the MMUs on the next internal access boundary when asserted and enables the MMUs on the next boundary after the signal is negated The assertion of this signal does not affect the operation of the transparent translation registers or execution of the PFLUSH or PTEST instructions MOTOROLA M68040 USER S MANUAL 3 31 ENTRY OTHERWISE LOGICAL ADDRESS MATCHES WITH a LOGICAL ADDRESS ATC MI
380. ng because of the two page sizes If the page size is 4 Kbytes then logical address bit 12 is used to access the ATC s memory the tag comparators use bit 16 and physical address bit 12 is an ATC output If the page size is 8 Kbytes then logical address bit 16 is used to access the ATC s memory and physical address bit 12 is driven by logical address bit 12 It is advisable that a translation always be disabled before changing size and that the ATCs are flushed before enabling translation again The M68040 is organized such that other operations always completely overlap the translation time of the ATCs thus no performance penalty is associated with searches The address translation occurs in parallel with indexing into the on chip instruction and data caches The MMU replaces an invalid entry when the ATC stores a new address translation When all entries in an ATC set are valid the ATC selects a valid entry to be replaced using a pseudo random replacement algorithm A 2 bit counter which is incremented for each ATC access points to the entry to replace when an access misses in the ATC hit rates are application and page size dependent but hit rates ranging from 9896 to greater than 99 can be expected These high rates are achieved because the ATCs are relatively large 64 entries and utilization efficiency is high with 8 Kbyte and 4 Kbyte page sizes 3 4 TRANSPARENT TRANSLATION Four independent TTRs DTTO and DTT1 in th
381. nique ined Parameters Velocity Po 100 LFM 12 7 C W 9 7 C W 250 110 11 0 C W 3 8 500 LFM 110 C 3 C W 9 9 C W 6 9 C W 3 6 E 1000 LFM 110 3 9 3 C W 6 3 C W 11 18 M68040 USER S MANUAL MOTOROLA 0 9 5 3 Table 11 4 Thermal Parameters with Forced Airflow and No Heat Sink for the MC68LC040 and 68 040 Thermal Mgmt Defined Parameters Measured Calculated Technique Airflow Velocity 98 C 59 2 100 LFM SW 110 C 3 C W 12 7 C W 9 7 C W 95 46 5 6 3W 91 1 C 29 9 C 98 C 66 C 250 LFM 110 C 3 C W 11 C W 8 C W 95 C 55 C 5 Su 91 1 40 70 C 98 70 4 500 LFM 110 C 3 C W 9 9 C W 6 9 C W 95 C 60 5 C xm 91 1 47 63 C 98 C 72 750 LFM 110 3 C W 9 5 C W 6 5 C W 95 C 62 5 C s 91 1 C 50 15 C 98 72 8 C 1000 LFM 110 C 3 C W 9 3 C W 6 3 C W 95 C 63 5 C M 91 1 C 51 41 Reviewing the maximum ambient operating temperatures illustrates that using an all small buffer configuration of the MC68040 with a relatively small amount of airflow 100 LFM achieves 0 70 C ambient operating temperature However depending on the output buffer configuration and available forced air cooling additional thermal management techniques may be required 11 9 3 With Heat Sink The designer must conside
382. nless otherwise specified Table 1 3 Notational Conventions z TRAP Equivalent to Format Offset Word SSP SSP 2 SSP g SSP SSP 4 SSP SR 2 SSP SSP 2 SSP Vector PC STOP Enter the stopped state waiting for interrupts lt operand gt 10 The operand is BCD operations are performed in decimal If lt condition gt Test the condition If true the operations after then are performed If the condition is false then operations and the optional else clause is present the operations after else are performed If the else operations condition is false and else is omitted the instruction performs no operation Refer to the Bcc instruction description as an example D Data register 07 00 used during update Dx Dy Source and destination data registers respectively Any Address or Data Register Rx Ry Any source and destination registers respectively Index Register An Dn or suppressed An MRn Any Memory Register n Xn MOTOROLA M68040 USER S MANUAL 1 11 Table 1 3 Notational Conventions Continued Data Format And Type inf Positive Infinity fmt Operand Data Format Byte B Word W Long L Single S Double D Extended X or Packed P B W L Specifies a signed integer data type twos complement of byte word or long word Double precision real data format 64 bits 1 twos complement signed integer 64 to 17
383. no invalid lines exist then a pseudo random replacement algorithm is used to select a valid line replacing it with the new line Each cache contains a 2 bit counter which is incremented for each access to the cache The instruction cache counter is incremented for each half line accessed in the instruction cache The data cache counter is incremented for each half line accessed during reads for each full line accessed during writes in copyback mode and for each bus transfer resulting from a write in write through mode When a miss occurs and all four lines in the set are valid the line pointed to by the current counter value is replaced after which the counter is incremented 4 4 M68040 USER S MANUAL MOTOROLA 4 2 Using the instruction the caches are individually enabled to access the 32 bit cache control register CACR illustrated in Figure 4 4 The CACR contains two enable bits that allow the instruction and data caches to be independently enabled or disabled Setting one of these bits enables the associated cache without affecting the state of any lines within the cache A hardware reset clears the disabling both caches however reset does not affect the tags state information and data within the caches The CINV instruction must clear the caches before enabling them It is not recommended that page descriptors be cached Specifically the M68040 does not support the caching of page d
384. nooped by other masters The copyback caching mode is typically used for data local to a processor because in a multimaster caching system only one master at a time can access a given page of copyback data The copyback caching mode also prevents multiple snooping processors from intervening in a specific access MOTOROLA M68040 USER S MANUAL 7 59 7 9 1 Snoop Inhibited Cycle For alternate bus master accesses in which the SCx signal encodings indicate that snooping is inhibited SCx 0 the M68040 immediately negates MI and allows memory to respond to the access Snoop inhibited alternate bus master accesses do not affect performance of the processor since no cache lookups are required Figure 7 40 illustrates an example of a snoop inhibited operation in which an alternate bus master is granted the bus for an access No matter what the values are on the SCx and TTx signals MI is asserted between bus cycles Because MI is asserted while a cache lookup is performed snooping inherently degrades system performance MI is asserted from the last TA of the current bus cycle if the M68040 owns the bus and loses it see Figure 7 40 If an alternate bus master has the bus and loses it there are two different resulting cases Usually an idle clock occurs between the alternate bus master s cycle and the MC68040 s cycle If so MI is asserted during the idle clock and negated from the same edge that the M68040 asserts the TS signal see Figure 7 40 If
385. nsfer modifier signals For a device that cannot supply an interrupt vector the autovector signal AVEC must be asserted In this case the M68040 uses an internally generated autovector which is one of vector numbers 25 31 that corresponds to the interrupt level number see Table 8 1 If external logic indicates a bus error during the interrupt acknowledge cycle the interrupt is considered spurious and the processor generates the spurious interrupt vector number 24 Once the vector number is obtained the processor saves the exception vector offset PC value and the internal copy of the SR on the active supervisor stack The saved value of the PC is the logical address of the instruction that would have been executed had the interrupt not occurred If the M bit of the SR is set the processor clears the M bit and creates a throwaway exception stack frame on top of the interrupt stack as part of interrupt exception processing This second frame contains the same PC value and vector offset as the frame created on top of the master stack but has a format number of 1 The copy of the SR saved on the throwaway frame has the S bit set the M bit clear and the interrupt mask level set to the new interrupt level It may or may not be set in the copy saved on the master stack The resulting SR after exception processing has the S bit set and the M bit cleared The processor loads the address in the exception vector into the PC and normal instru
386. nstruction is attempted The divide by zero entry in the processor s vector table points to the user divide by zero exception handler Table 9 14 Possible Divide by Zero Exceptions Instruction _ Operand Value FDIV Source operand 0 and floating point data register is not a NAN FLOG10 Source operand 0 An FSAVE must be the first instruction of the user divide by zero exception handler The user divide by zero exception handler must generate a result to store in the destination To assist the exception handler in this function the processor supplies the information listed in Table 9 16 which lists the floating point state frame fields for divide by zero exceptions that are defined for supervisor exception handler use To exit the user divide by zero exception handler the saved floating point frame is discarded and an RTE returns the processor to normal processing 9 7 7 Inexact Result The processor provides two inexact bits in the FPSR EXC byte to help distinguish between inexact results generated by emulated decimal input INEX1 exceptions and other inexact results INEX2 exceptions These two bits are useful in instructions where both types of inexact results can occur e g FDIV P 7E 1 FP3 In this case the packed decimal to extended precision conversion of the immediate source operand causes an 9 36 M68040 USER S MANUAL MOTOROLA inexact error to occur that is signaled as INEX1 exception Furthermore the subsequent div
387. nt for some dyadic operations i e multiply and divide can easily overflow or underflow the 15 bit exponent of the destination floating point register To simplify the overflow and underflow detection intermediate results in the FPU maintain a 16 bit twos complement integer exponent Detection of an overflow or underflow intermediate result always converts the 16 bit exponent into a 15 bit biased exponent before being stored in a floating point data register The FPU internally maintains the 67 bit mantissa for rounding purposes The mantissa is always rounded to 64 bits or less depending on the selected rounding precision before it is stored in a floating point data register 16 BIT EXPONENT H 63 BIT FRACTION E LSB OF FRACTION INTEGER BIT GUARD BIT OVERFLOW BIT ROUND BIT STICKY BIT Figure 9 7 Intermediate Result Format If the destination is a floating point data register the result is in the extended precision format and is rounded to the precision specified by the FPSR PREC bits before being stored All mantissa bits beyond the selected precision are zero If the single or double 9 12 M68040 USER S MANUAL MOTOROLA precision mode is selected the exponent value is in the correct range even if it is stored extended precision format If the destination is a memory location the FPSR PREC bits are ignored In this case a number in the extended precision format is taken from the source floating point data regi
388. nt state Not Possible V6 Write data to cache Write data into cache write data to memory no change to Dn bits remain in current state write data to memory remain in current state see note No action remain in V7 No action go to invalid No action dirty data CPU Write Hit Write through Cache Invalidate CINV current state lost go to invalid state Cache Push CPUSH No action remain in V8 No action go to invalid Write dirty data to current state memory go to invalid state Alternate Master Read Hit Snoop Control 01 Leave Dirty Not Possible V9 No action remain in current state Inhibit memory and source data remain in current state CPU Write Miss 4 Write data to memory V4 Write data to memory D4 Write data to memory Write through remain in current state remain in current state remain in current state see note NOTE Dirty state transitions D4 and D6 are the result of a system programming error and should be avoided even though they are technically valid MOTOROLA M68040 USER S MANUAL 4 17 Table 4 4 Data Cache Line State Transitions Continued Current State Cache Operation Invalid Cases Valid Cases Dirty Cases Alternate Master Read 110 Not Possible 10 No action go to invalid D10 Inhibit memory and Snoop Control 10 source data go to Invalidate invalid state Alternate Master Write Hit 111 Not Possible 11 No action
389. nt to avoid destructive configurations The user is responsible for avoiding situations in which the MC68040V and 6 40 output drivers are enabled into actively driven networks The 68040 and MC68ECOA0V include on chip circuitry to detect the initial application of power to the device Power on reset POR which is an internal signal the output of this circuitry is used to reset both the system and the IEEE 1149 14 logic The purpose of applying POR to the IEEE 1149 14 circuitry is to avoid the possibility of bus contention during power on The time required to complete device power on is power supply dependent However the TAP controller remains in the test logic reset state while POR is asserted The TAP controller does not respond to user commands until POR is negated The following restrictions apply 1 Leaving the TAP controller test logic reset state negates the ability to achieve the lowest power consumption during the LPSTOP instruction but does not otherwise affect device functionality 2 The TCK input is not blocked in LPSTOP mode To consume minimal power the input should be externally connected to VCC or ground 3 The TMS and TDI pins include on chip pull up resistors In LPSTOP mode these two pins should remain either connected to or ground to achieve minimal power consumption 4 The external system must assert RSTI within eight bus clocks of exiting from the EXTEST JTAG instruction or els
390. ntains an MMU main cache and snoop controller The corresponding MMUs contain two transparent translation registers which identify blocks of memory that can be accessed without translation The MMUs also contain control logic and corresponding address translation caches 5 in which recently used logical to physical address translations are stored The data memory unit contains a data write and data read buffer and the instruction memory unit contains an instruction line read buffer These buffers temporarily hold data until an opportune moment arises to write the data to external memory or read the operand instruction into the integer unit INSTRUCTION DATA BUS INSTRUCTION INSTRUCTION ATC CACHE Z t 4 INSTRUCTION ADDRESS INSTRUCTION FETCH MMU CACHE SNOOP CONTROLLER DECODE INSTRUCTION MEMORY UNIT CONVERT ADDRESS BUS EA CALCULATE EXECUTE EA FETCH 5 DATA MEMORY UNIT BACK DATA CONTROLLER DATA CACHE 20 4 2 BUS CONTROL SIGNALS FLOATING POINT UNIT DATA 7 OPERAND DATA BUS Figure 3 1 Memory Management Unit The principal MMU function is to translate logical addresses to physical addresses using translation tables stored in memory As the MMU receives a logical address from the integer unit it searches its ATC for the corresponding physical
391. nterrupt exception transfers control to a routine that responds appropriately The peripheral device uses the active low interrupt priority level signals IPL2IPLO to signal an interrupt condition to the processor and to specify the priority level for the condition Refer to Section 8 Exception Processing for a discussion on the IPLx levels and IPEND The status register SR of the M68040 contains an interrupt priority mask 12 10 bits The value in the interrupt mask is the highest priority level that the processor ignores When an interrupt request has a priority higher than the value in the mask the processor makes the request a pending interrupt IPL2 IPLO must maintain the interrupt request level until the M68040 acknowledges the interrupt to guarantee that the interrupt is recognized The M68040 continuously samples IPL2 IPLO on consecutive rising edges of BCLK to synchronize and debounce these signals An interrupt request that is held constant for two consecutive clock periods is considered a valid input Although the protocol requires that the request remain until the processor runs an interrupt acknowledge cycle for that interrupt value an interrupt request that is held for as short a period as two clock cycles can be recognized Figure 7 19 is a flowchart of the procedure for making an interrupt pending MOTOROLA M68040 USER S MANUAL 7 29 5 SAMPLE AND SYNCHRONIZE 3 4 IPL2 IPLO D
392. ntroller examines this signal when the processor is not the bus master 5 3 6 Transfer Size SIZ1 SIZO These bidirectional three state signals indicate the data size for the bus transfer The bus snoop controller examines this signal when the processor is not the bus master Refer to Section 7 Bus Operation for more information on the encoding of these signals 5 3 7 Lock LOCK This three state output indicates that the current transfer is part of a sequence of locked transfers for a read modify write operation The external arbiter can use LOCK to prevent an alternate bus master from gaining control of the bus and accessing the same operand between processor accesses for the locked sequence of transfers Although LOCK indicates that the processor requests the bus be locked the processor will give up the bus if the external arbiter negates the BG signal When the M68040 is not the bus master the LOCK signal is set to a high impedance state drives high before three stating Refer to Section 7 Bus Operation for information on locked transfers 5 3 8 Lock End LOCKE This three state output indicates that the current transfer is the last in a sequence of locked transfers for a read modify write operation The external arbiter can use LOCKE to support arbitration between unrelated locked transfer sequences while still maintaining the indivisible nature of each read modify write operation When the M68040 is not the bus master the LO
393. o Interrupt Next Instruction Format Error RTE or RESTORE Instruction STATUS REGISTER TRAP Next Instruction 4502 Illegal Instruction Illegal Instruction PROGRAM COUNTER 7 A Line Instruction A Line Instruction 4506 0000 VECTOR OFFSET F Line Instruction F Line Instruction Privilege Violation First Word of Instruction Causing Privilege Violation Floating Point Pre Floating Point Pre Instruction Instruction Exception FOUR WORD STACK FRAME FORMAT 0 8 4 2 Four Word Throwaway Stack Frame Format 1 If a four word throwaway stack frame is on the active stack and an RTE instruction is encountered the processor increments the active stack pointer by eight updates the SR with the value read from the stack and then begins RTE processing again as illustrated in Figure 8 6 The processor reads a new format word from the stack frame on top of the active stack which may or may not be the same stack used for the previous operation and performs the proper operations corresponding to that format In most cases the throwaway frame is on the interrupt stack and when the SR value is read from the stack the S bit and M bit are set In that case there is a normal four word frame on the master stack However the second frame can be any format even another throwaway frame and can reside on any of the three system stacks Stack Frames Exception Types Stacked PC Points To Created on interrupt stack Next Ins
394. o the instruction and data memory units to support integer and floating point operations Both the ea fetch and write back stages of the integer unit pipeline perform accesses to the data memory unit with effective address fetches assigned a higher priority This priority allows data read and write accesses to occur out of order with a memory write access potentially delayed for many clocks while allowing read accesses generated by later instructions to complete The processor detects a read access that references earlier data waiting to be written address collisions and allows the corresponding write access to complete A given sequence of read accesses or write accesses is completed in order and reordering only occurs with writes relative to reads Figure 2 1 in Section 2 Integer Unit illustrates the integer pipeline stages Besides address collisions the instruction restart model used for exception processing in the M68040 causes another potential problem After the operand fetch for an instruction an exception that causes the instruction to be aborted can occur resulting in another access for the operand after the instruction restarts For example an exception could occur after a read access of an device s status register The exception causes the instruction to be aborted and the register to be read again If the first read accesses clears the status bits the status information is lost and the instruction obtains incorrect data
395. oating point instruction can reside in user space therefore the floating point unimplemented exception handler may need to access user instruction space The following processing steps occur for an unimplemented floating point instruction 1 When an unimplemented floating point instructionis encountered the instruction is partially decoded and the effective address is calculated if required 2 The processor waits for all previous integer instructions write backs and associated exception processing to complete before beginning exception processing for the unimplemented floating point instruction Any access error that occurs in completing the write backs causes an access error exception and the resulting stack frame indicates a pending unimplemented floating point instruction exception The access error exception handler then completes the write backs in software and exception processing for the unimplemented floating point instruction exception begins immediately after return from the access error handler 3 The processor begins exception processing for the unimplemented floating point instruction by making an internal copy of the current SR The processor then enters the supervisor mode and clears the trace bits T1 and TO It creates a format 4 stack frame and saves the internal copy of the SR PC vector offset calculated effective address and PC value of the faulted instruction in the stack frame The effective address field of th
396. ocked accesses for operands in memory and for updating translation table entries during table search operations 4 3 3 Special Accesses Several other processor operations result in accesses that have special caching characteristics besides those with an implied cache inhibited access in the serialized mode Exception stack accesses exception vector fetches and table searches that miss in the cache do not allocate cache lines in the data cache preventing replacement of a cache line Cache hits by these accesses are handled in the normal manner according to the caching mode specified for the accessed address Accesses by the MOVE16 instruction also do not allocate cache lines in the data cache for either read or write misses Read hits on either valid or dirty cache lines are read from the cache Write hits invalidate a matching line and perform an external access Interacting with the cache in this manner prevents a large block move or block initialization implemented with a MOVE16 from being cached since the data may not be needed immediately If the data cache is re enabled after a locked access has hit and the data cache was disabled the next non locked access that results in a data cache miss will not be cached 4 4 CACHE PROTOCOL The cache protocol for processor and snooped accesses is described in the following paragraphs In all cases an external bus transfer will cause a cache line state to change MOTOROLA M68040 USER S MANUAL 4
397. ode dissipates more power than the small and higher frequencies of operation dissipate more power than the lower frequencies The MC68040 allows a combination of either large or small buffers on the outputs of the miscellaneous control signals data bus and address bus transfer attribute pins The large buffers offer quicker output times allowing for an easier logic design However they do so by driving about 10 times as much current as the small buffers The designer should consider whether the quicker timings present enough advantage to justify the additional consideration to the individual signal terminations the die power consumption and the required cooling for the device Since the MC68040 can be powered up in one of many output buffer modes upon reset the actual maximum power consumption for an MC68040 11 12 M68040 USER S MANUAL MOTOROLA rated at a particular maximum operating frequency is dependent upon the power up mode Therefore the MC68040 is rated at a maximum power dissipation for either the large or small buffers at a particular frequency This allows for control of some of the thermal management upon reset The following equation provides a rough method to calculate the maximum power consumption for a chosen output buffer mode Pp Poss x PINS PINSci where Pp Maximum Power Dissipation for Output Buffer Mode Selected Maximum Power Dissipation for Small Buffer Mode All Output
398. ode in which the effective address is calculated For immediate and register direct addressing modes this field is 0 The saved PC value is the logical address of the instruction that follows the unimplemented floating point instruction This value will be restored during RTE execution The vector offset format number 4 is used for this eight word stack frame Note that an MC68040 cannot correctly handle a stack format 4 The PC of the faulted instruction contains a long word PC of the floating point instruction that caused the trap to occur The information is provided so that the instruction is available for software emulation of floating point instructions The processor generates exception vector number 11 for the unimplemented F line instruction exception vector fetches the address of the F line exception handler from the exception vector table and begins execution of the handler after prefetching instructions to fill the pipeline Refer to Section 8 Exception Processing for details about exception processing A 6 M68040 USER S MANUAL MOTOROLA 5 2 MC68LC040 Stack Frames When the processor executes an RTE instruction it examines the stack frame on top of the active supervisor stack to determine if it is a valid frame and what type of context restoration it requires The MC68LC040 provides five different stack frames for exception processing and allows for an MC68040 specific stack frame The set of frames includes four and six word st
399. ode is PC relative mode 111 register 010 or 011 or indirect with index mode 110 MA Misaligned Access MA is set if an ATC fault occurs for second page access that spans two pages in memory MOTOROLA M68040 USER S MANUAL 8 25 Fault This bit is set for fault due to a nonresident entry bus error during table search or invalid descriptor encountered or privilege violation write protected or supervisor only It is cleared for a bus errored instruction data or cache line push access LK Locked Transfer Read Modify Write This bit is set if a fault occurred on a locked transfer it is cleared otherwise RW Read Write This bit is set if a fault occurred on a read transfer it is cleared otherwise X Undefined SIZE Transfer Size The SIZE field corresponds to the original access size If a data cache line read results from a read miss and the line read encounters a bus error the SIZE field in the resulting stack frame indicates the size of the original read generated by the execution unit TT Transfer Type This field defines the TT1 TTO signal encodings for the faulted transfer TM Transfer Modifier This field defines the TM2 TMO signal encodings for the faulted transfer 8 4 6 3 WRITE BACK STATUS These fields contain status information for the three possible write backs that could be pending after the faulted access see Figure 8 8 For a data cache line push fault or a
400. ode using the MOVEC instruction can directly access the ACRs The 32 bit ACRs each define blocks of address space for access control These blocks of address space can overlap or be separate and are a minimum of 16 Mbytes Three blocks are used with two user defined attributes cachability control and optional write protection The ACRs specify a block of address space as serialized noncachable for peripheral selections and as write through for shared blocks of address space in multi processing applications The ACRs can be configured to support many embedded control applications while maintaining cache integrity Refer to Section 4 Instruction and Data Caches for details concerning cachability Figure B 4 illustrates the ACR format MOTOROLA M68040 USER S MANUAL 5 31 4 2 1 15 14 13 12 1 10 mnsa 5 z Figure 4 MC68EC040 Access Control Register Format ADDRESS BASE This 8 bit field is compared with physical address bits A31 A24 Addresses that match in this comparison and are otherwise eligible are accessible ADDRESS MASK This 8 bit field contains a mask for the ADDRESS BASE field Setting a bit in the ADDRESS MASK field causes the processor to ignore the corresponding bit in the ADDRESS BASE field Setting some of the ADDRESS MASK bits to ones obtains blocks of memory larger than 16 Mbytes The low order bits of this field are normally set to define contigu
401. oes not cause an exception to be taken regardless of the value in the ENABLE byte When user writes to the ENABLE byte that enables a class of floating point exceptions a previously generated floating point exception does not cause an exception to be taken regardless of the value in the FPSR EXC byte The user can clear a bit in the FPCR ENABLE byte disabling each corresponding exception The second situation occurs when the processor encounters a nonmaskable SNAN OPERR OVFL and UNFL condition this is referred to as nonmaskable exception conditions This allows a supervisor exception handler to correct a defaulting result generated by the MC68040 that is different from the result generated by an MC68881 MC68882 executing the same code After correcting the result the supervisor exception handler calls a user defined exception handler if the exception has been enabled in the FPCR ENABLE byte or returns to the main program flow if the exception is disabled A single instruction execution can generate dual and triple exceptions When multiple exceptions occur with exceptions enabled for more than one exception class the highest priority exception is reported the lower priority exceptions are never reported or taken The previous list of arithmetic floating point exceptions is in order of priority The bits of the ENABLE byte are organized in decreasing priority with bit 15 being the highest and bit 8 the lowest The exception handler must che
402. of the MMUSR are defined following Figure 3 6 which illustrates the MMUSR 31 10 9 8 7 6 5 4 3 2 1 0 Pro or 5 Figure 3 6 Status Register Format Physical Address This 20 bit field contains the upper bits of the translated physical address Merging these bits with the lower bits of the logical address forms the actual physical address Bit 12 is undefined if a PTEST is executed with 8 Kbyte pages selected B Bus Error The B bit is set if a transfer error is encountered during the table search for the PTEST instruction If the B bit is set all other bits are zero G Global This bit is set if the G bit is set in the page descriptor U1 U0 User Page Attributes These bits are set if corresponding bits in the page descriptor are set 3 6 M68040 USER S MANUAL MOTOROLA S Supervisor Protection This bit is set if the S bit in the page descriptor is set Setting this bit does not indicate that a violation has occurred CM Cache Mode This 2 bit field is copied from the CM bits in the page descriptor M Modified This bit is set if the M bit is set in the page descriptor associated with the address W Write Protect This bit is set if the W bit is set in any of the descriptors encountered during the table search Setting this bit does not indicate that a violation has occurred T Transparent Translation Register Hit If the T bit is set then the PTEST address matches an instruc
403. oints to the M68040FPSP OPERR exception handler Once the M68040FPSP OPERR exception handler recognizes the operand error as a maskable condition it does not modify the destination or pass control to the user OPERR exception handler 9 7 3 2 NONMASKABLE EXCEPTION CONDITIONS If an FMOVE to byte word or long word has a source operand that is too large to be represented in the specified destination integer format integer overflow NAN infinity or if the source operand is equal to the largest negative integer representable in the specified destination integer format erroneous MC68040 condition the processor immediately takes a post instruction exception Instruction execution continues at the M68040FPSP OPERR exception handler If the M68040FPSP determines a nonmaskable erroneous MC68040 condition caused the exception it stores the largest negative integer representable in the given destination integer format 27 for byte 215 for word and 231 for long word The M68040FPSP OPERR exception handler then returns the processor to normal processing If an integer overflow or an FMOVE to byte word or long word with a source of infinity causes the exception then the destination is written with the largest positive or negative integer that can be represented in the given format If an FMOVE to byte of word or long word with a source of NAN causes the exception then the most significant 8 16 or 32 bits respectively are written to the destin
404. oller These 16 controller states are defined in detail in the IEEE standard 1149 14 but only 8 are included in this section Test Logic Reset Run Test Idle Capture IR Capture DR Update IR Update DR Shift IR Shift DR Four dedicated signal pins provides access to the TAP controller test clock input that synchronizes the test logic 5 test mode select input with an internal pullup resistor sampled on the rising edge of TCK to sequence the TAP controller C 10 M68040 USER S MANUAL MOTOROLA TDI A test data input with an internal resistor sampled on the rising edge of TCK TDO A three state test data output actively driven only in the shift IR and shift DR controller states that changes on the falling edge of TCK The test logic also includes an instruction shift register and two test data registers a boundary scan register and a bypass register The boundary scan register links all device signal pins into a chain that can be controlled by the 3 bit instruction shift register TEST DATA REGISTERS 188 BIT BOUNDARY SCAN REGISTER 5 J LATCHED DECODER 3 BIT INSTRUCTION 5 REGISTER TDI Figure 4 MC68040V and MC68ECO40V Test Logic Block Diagram C 6 1 Instruction Shift Register MC68040V and MC68ECO40V IEEE standard 1149 1A implementations include a 3 bit instruction shift register without parity The register
405. on All timing and drive capabilities on both devices are equivalent to those of the MC68040 in small output buffer impedance mode The MC68040V has an additional mode of operation the low power stop mode of operation The MC68040V and MC68LC040 do not contain causing unimplemented floating point exceptions to occur using a new stack frame format The 68040 is a 3 3 volt static microprocessor that operates down to 0 MHz For specific details on the MC68LC040 refer to Appendix A MC68L C040 For specific details on the MC68040V refer to both Appendix MC68LC040 and Appendix MC68040V and MC68ECO040V Disregard all information concerning FPU when reading the following subsections 1 1 2 MC68EC040 and 68 040 MC68EC040 and MC68ECO040V are derivatives of the MC68040 They implement the same IU as the 68040 but have no FPU or MMU which embedded control applications generally do not require The MC68ECO40 is pin compatible with the MC68040 The following differences exist between the MC68EC040 MC68bECO04A0V and the MC68040 The DLE and MDIS pin names have been changed to JS0 and JS1 respectively PTEST and PFLUSH instructions cause an undetermined number of bus cycles the user should not execute these instructions The access control unit ACU replaces the MMU The MC68EC040 and MC68ECO040V ACU has two data and two instruction registers that are called data and instruction transparent t
406. on 4 Instruction and Data Caches for details on line fill and the data cache 7 6 M68040 USER S MANUAL MOTOROLA Figure 7 5 illustrates the transfer of a long word operand from an odd address requiring more than one bus cycle For the first transfer or bus cycle the SIZx signals specify a byte transfer and the byte offset is 1 The slave device supplies the byte and acknowledges the data transfer When the processor starts the second cycle the SIZx signals specify a word transfer with a byte offset of 2 The next two bytes are transferred during this cycle The processor then initiates the third cycle with the SIZEx signals indicating a byte transfer The byte offset is now 0 the port supplies the final byte and the operation is complete This example is similar to the one illustrated in Figure 7 6 except that the operand is word sized and the transfer requires only two bus cycles Figure 7 7 illustrates a functional timing diagram for a misaligned long word read transfer DATA BUS 31 24 23 16 15 8 7 0 3 TRANSFER 1 2 1 t TRANSFER 2 BYTE 0 X TRANSFER 3 MEMORY 31 24 23 16 15 8 7 0 XXX BYTE 3 BYTE2 1 0 Figure 7 5 Example of a Misaligned Long Word Transfer DATA BUS 31 24 23 16 15 8 7 0 BYTE 1 I TRANSFER 1 BYTE 0 BYTE1 TRANSFER 2 MEMOR
407. on and PAL Equation A brief summary of the bus signal encodings for each access type is listed in Table 7 2 Additional information on the encodings for the M68040 signals can be found in Section 5 Signal Description MOTOROLA M68040 USER S MANUAL 7 5 Table 7 2 Summary of Access Types versus Bus Signal Encodings Data Cache Normal Table Bus Push Data Code Search MOVE16 Alternate Interrupt Breakpoint Signal Access Access Access Access Access Acknowledge Acknowledge 1 0 55 55 55 55 00000000 Address Address Address Address Address 1 UPAO MMU MMU Source 1 Source 5121 520 Biwititine Long Word Bw s s s s TM4 TM2 1 2 5 or 6 3 or 4 1 or 5 Function Int Level 1 7 Code TLN1 TLNO Cache Set Cache Set Undefined Undefined Undefined Undefined Undefined Entry Entry LOCK Negated Asserted Asserted Negated Negated Negated Negated LOCKE Negated Negated3 CIOUT Negated MMU Negated MMU Asserted Negated Negated Source Source 1 NOTES 1 The UPAO and CIOUT signals are determined by the U1 UO data and OM bit fields respectively corresponding to the access address 2 The TLNx signals are defined only for normal push accesses and normal data line read accesses 3 The LOCK signal is asserted during TAS CAS and CAS2 operand accesses and for some table search update sequences LOCKE is asserted for the last transfer of e
408. ontrol registers to perform supervisory functions User programs are thus restricted from accessing privileged information and the operating system performs management and service tasks for the user programs by coordinating their activities This difference allows the supervisor mode to protect system resources from uncontrolled accesses Most instructions execute in either mode but some instructions that have important System effects are privileged and can only execute in the supervisor mode For instance user programs cannot execute the STOP or RESET instructions To prevent a user program from entering the supervisor mode except in a controlled manner instructions that can alter the S bit in the SR are privileged The TRAP instructions provide controlled access to operating system services for user programs If the S bit in the SR is set the processor executes instructions in the supervisor mode Because the processor performs all exception processing in the supervisor mode all bus cycles generated during exception processing are supervisor references and all stack accesses use the active supervisor stack pointer If the S bit of the SR is clear the processor executes instructions in the user mode The bus cycles for an instruction executed in the user mode are user references The values on the transfer modifier pins indicate either supervisor or user accesses The processor utilizes the user mode and the user programming model when it is
409. onverted to extended precision If the instruction specifies a packed decimal real source bits 95 64 of the operand reside in FPTM 31 00 and the FPTS FPTE and FPTM 63 32 fields are undefined OPCLASS This field refers to bits 15 13 of CMDREG1B Note that CMDREG1B is identical to the second word of a floating point arithmetic instruction opcode STAG DTAG These 3 bit fields specify the data type of the source and destination operands respectively STAG is undefined for a packed decimal real source operand The encodings for STAG and DTAG are as follows 000 Normalized 001 Zero 010 Infinity 011 100 Extended Precision Denormalized or Unnormalized Input 101 Single or Double Precision Denormalized Input set this bit indicates that a post instruction exception has occurred Since only an opclass 3 instruction can indicate a post instruction exception this bit indicates that the exception is caused by an FMOVE OUT instruction WBTS WBTE 15 14 00 WBTM 66 65 02 01 00 SBIT These fields contain the exception operand in internal data format for E3 exceptions Collectively these fields are called the WBTEMP and an image of the intermediate result WBTM66 is the overflow bit WBTM1 WBTMO and SBIT are the guard round and sticky bits respectively MOTOROLA M68040 USER S MANUAL 9 43 Table 9 16 State Frame Field Information FSAVE State Frame Field Contents Unimplemented
410. operand fetch the unimplemented instruction is restarted after the processor returns from exception handling for the error Refer to Section 8 Exception Processing for more information on access errors The fetched source operand is passed to the FPU which converts the operand to extended precision and saves the intermediate result If the operand is an unsupported data type denormalized unnormalized or packed decimal real the unimplemented floating point exception takes precedence and the floating point instruction emulation routine must detect the unsupported data type The processor begins exception processing for the unimplemented floating point instruction by making an internal copy of the current SR The processor then enters the supervisor mode and clears the trace bits T1 TO The processor creates a format 2 stack frame and saves the vector offset PC internal copy of the SR and calculated MOTOROLA M68040 USER S MANUAL 9 21 effective address in the stack frame saved value is the logical address of the instruction that follows the unimplemented floating point instruction The processor generates exception vector number 11 for the unimplemented F line instruction exception vector fetches the address of the F line exception handler from the processor s exception vector table pushes the format 2 stack frame on the system stack and begins execution of the exception handler after prefetching instructions to fill the
411. ord Write Transfers for information on long word writes If no waits states are generated a burst inhibited line write completes in eight clocks instead of the five required for a burst write Clock 3 C3 The processor drives the second long word of data on the data bus and holds the address and transfer attribute signals constant during C3 The selected device increments A3 and A2 to reference the next long word latches this data from the data bus and asserts TA At the end of C3 the processor samples the level of TA if TA is asserted the transfer terminates If TA is not recognized asserted at the end of C3 the processor inserts wait states instead of terminating the transfer The processor continues to sample TA on successive rising edges of BCLK until TA is recognized asserted Clock 4 C4 This clock is identical to C3 except that the value driven on the data bus corresponds to the third long word of data for the burst Clock 5 C5 This clock is identical to C3 except that the value driven on the data bus corresponds to the fourth long word of data for the burst After the processor recognizes the last TA assertion and terminates the line write bus cycle TIP remains asserted if the processor is ready to begin another bus cycle Otherwise the processor negates TIP during the first half of the next clock The processor also three states the data bus during the first half of the next clock following termination of the write cycle
412. ormat essen 9 8 Rounding Algorithm MOTOROLA M68040 USER S MANUAL Page Number Xix LIST OF ILLUSTRATIONS Continued Figure Page Number Title Number 9 9 Format of Denormalized Operand in State 9 24 9 10 MC68040 Floating Point State Frames 9 40 9 11 Mapping of Command Bits for CMDREGSB 9 42 10 1 Simple Instruction Timing 10 5 10 2 Instruction Overlap with Multiple 10 6 10 3 ilnterlogGKed 10 7 11 1 Clock Input Timing iei rre eli al e Eee ns 11 3 11 2 Drive Levels and Test Points for AC Specifications 11 6 11 3 Read Write Timing 11 7 11 4 Bus Arbitration 2 11 8 1155 SOO Rt TIMING eR EA 11 9 11 6 Snoop MISS sonus eo speret sea ere p t Ec 11 10 ee Other Signal TIMING isere pu EE et DI REA atte 11 11 11 8 MC68040 Termination Network 11 15 11 9 Typical Configuration for RC Termination Network 11 15 11 10 Heat Sink with Adhesive esses 11 20 11 11 Heat Sink with 44412 11 11 21 12 1 PGA Package DImerslon
413. ormation on the MC68EC040 memory unit 7 26 M68040 USER S MANUAL MOTOROLA C3 C2 Cl BCLK A31 A0 UPA1 5121 5120 TT1 TTO TM2 TMO lt Ble je Je de v 2 L eh d ES N LOCKED TRANSFER Undefined Figure 7 18 Locked Transfer for TAS Instruction Timing 7 27 M68040 USER S MANUAL MOTOROLA Clock 2 C2 During the first half of the first clock cycle after C1 the processor negates TS The selected device uses R W 5121 SIZO A1 and 0 to place its information on the data bus With the exception of R W these signals also select any or all of the bytes D24 031 016 023 015 08 07 00 Concurrently the selected device asserts At the end of the first clock cycle after C1 the processor samples the level of TA and latches the current value on the data bus If TA is asserted the read transfer terminates and the latched data is passed to the appropriate memory unit If TA is not recognized asserted the processor ignores the data and appends a wait state instead of terminating the transfer The processor continues to sample TA on successive rising edges of BCLK until TA is recognized as asserted The latched data is then passed to the appropriate memory unit If more than one read cycle is required to read in the operand s C1 and C2 are repeated accordingly When the processor recogn
414. ot be set in the FPSR EXC byte In this case the INEX bit is set in the FPSR byte and the OVFL bit is set in both the FPSR EXC and AEXC bytes 9 38 M68040 USER S MANUAL MOTOROLA 9 8 FLOATING POINT STATE FRAMES All floating point arithmetic exception handlers must have FSAVE as the first floating point instruction any other floating point instruction causes another exception to be reported Once the FSAVE instruction has executed the exception handler should use only the FMOVEM instruction to read or write to the floating point data registers since FMOVEM cannot generate further exceptions or change the FPCR The FPU executes an FSAVE instruction to save the current floating point internal state for context switches and floating point exception handling When an FSAVE is executed the processor waits until the FPU either completes execution of all current instructions or is unable to perform further processing due to a pending exception that must be serviced Any exceptions generated during this time are not reported and are saved in the resulting busy state frame Four state frames can be generated as a result of an FSAVE instruction busy null idle and unimplemented floating point instruction When an unimplemented floating point exception occurs the FSAVE generates a 26 word unimplemented instruction state frame When an unsupported data type exception occurs the FSAVE generates a 50 word busy state frame All floating point a
415. ource Destination MOVE ea ea MOVEA Source e Destination MOVEA ea An MOVE CCR s Destination MOVE CCR lt ea gt from CCR MOVE to CCR Source e CCR MOVE ea CCR MOVE from SR If supervisor state MOVE SR lt ea gt then SR e Destination else TRAP MOVE to SR If supervisor state MOVE ea SR then Source SR else TRAP MOVE USP If supervisor state MOVE USP An then USP 2 An or An e USP MOVE An USP else TRAP 16 Source block e Destination block 16 Ax 7 16 xxx L 16 An xxx L 16 xxx L MOVEC If supervisor state MOVEC then Rc e Rn or Rn eRc MOVEC Rn Rc else TRAP MOVEM Registers 2 Destination MOVEM lt list gt lt ea gt 4 Source Registers MOVEM lt ea gt lt list gt 4 MOVEP Source Destination Dx dp Ay dn Ay Dx MOVEQ Immediate Data Destination MOVEQ lt data gt Dn MOVES If supervisor state MOVES lt gt then Rn e Destination DFC or MOVES lt ea gt Rn Source SFC Rn else TRAP MULS Source x Destination Destination MULS W lt ea gt Dn 16 x 16 232 MULS L lt gt 32 x 32 232 MULS L ea Dh DI 32x32 64 MULU Source x Destination Destination MULU W lt ea gt Dn 16 x 16 232 MULU L lt ea gt DI 32 x 32 232 MULU L lt ea gt Dh DI 32 x32 64 NBCD 0 Destination40 X e Destination NBCD ea NEGX 0 Destination X Destination NEGX ea 1 18 M68
416. ous blocks larger than 16 Mbytes although contiguous blocks are not required E Enable This bit enables and disables transparent translation of the block defined by this register Refer to Section 3 Memory Management Unit Except MC68EC040 and MC68ECO040V for details on transparent translation 0 Access control disabled 1 Access control enabled S Supervisor User Mode This field specifies the way FC2 is used in matching an address 00 Match only if FC2 0 user mode access 01 Match only if FC2 1 Supervisor mode access 10 11 Ignore FC2 when matching U1 UO User Page Attributes These two bits drive on the user page attribute signals UPA1 and If an external bus transfer results from the access UO and U1 are echoed to the UPAO and UPA1 signals respectively The user can program these bits to support extended addressing bus snooping or other applications The MC68EC040 does not interpret these bits CM Cache Mode This field selects the cache mode and access serialization for a page as follows 00 Cachable Write through Cachable Copyback 10 Noncachable Serialized 11 Noncachable Detailed information on caching modes is available in Section 4 Instruction and Data Caches and information on serialization is available in Section 7 Bus Operation 6 M68040 USER S MANUAL MOTOROLA W Write Protect This bit indicates if the transparent block is write protected If set write and re
417. pecifically to the SSW on the access error stack frame When the processor executes an instruction it examines the stack frame on top of the active supervisor stack to determine if it is a valid frame and what type of context restoration it requires If during restoration a stack frame has an odd address PC and an SR that indicates user trace mode enabled then an address error is taken The SR stacked for the address error has the SR S bit set For previous members of the M68000 family the S bit is clear When the M68040 writes or reads a stack frame it uses long word operand transfers wherever possible Using a long word aligned stack pointer greatly enhances exception processing performance The processor does not necessarily read or write the stack frame data in sequential order The system software should not depend on a particular exception generating a particular stack frame For compatibility with future devices the software should be able to handle any format of stack frame for any type of exception The following paragraphs discuss in detail each stack frame format 8 20 M68040 USER S MANUAL MOTOROLA 8 4 1 Four Word Stack Frame Format If a four word stack frame is on the active stack and an RTE instruction is encountered the processor updates the SR and PC with the data read from the stack increments the stack pointer by eight and resumes normal instruction execution Stack Frames Exception Types Stacked PC Points T
418. pipeline The exception handler emulates the unimplemented floating point instruction in software maintaining user object code compatibility Refer to Section 8 Exception Processing for details about exception vectors and format 2 stack frames The F line exception handler checks for the format 2 stack frame to distinguish an unimplemented floating point instruction from other F line unimplemented instructions When the exception handler for unimplemented floating point instructions executes an FSAVE a 26 word unimplemented instruction state frame is created see Figure 9 10 At this point an FSAVE instruction yields the information as listed in Table 9 16 Note that unless the instruction specifies a packed decimal real source the state frame contains both operands if required For packed decimal real data format the second operand is in the designated format of the destination floating point data register The exception handler uses the information provided in the state frame to determine the instruction that it needs to emulate and the input operands to that instruction Once the instruction has been emulated and the result is reached the exception handler moves the result into the appropriate destination floating point data register discards the unimplemented instruction state frame and returns to normal instruction flow using the instruction The limitation to this approach is that no floating point arithmetic exceptions can be r
419. planar concave curvature in the central regions of the heat sink results in poor thermal contact to the package Although there are several ways to attach a heat sink to the package it is easiest to use a demountable heat sink attachment called E Z attach for PGA packages see Figure 11 33 A steel spring clamps the heat sink and the package to a plastic frame Besides the height of the heat sink and plastic frame no additional height is added to the package The interface between the ceramic package and the aluminum heat sink was evaluated for both dry and wet interfaces in still air The thermal grease reduced the quite significantly about 2 5 C W in still air An attachment with thermal grease provided about the same thermal performance as if a thermal epoxy had been used 11 20 M68040 USER S MANUAL MOTOROLA SPRING HEAT SINK PIN GRID ARRAY FRAME Figure 11 11 Heat Sink with Attachment In the specification provided by Thermalloy Inc a chart illustrates the heat sink temperature rise above ambient versus heat dissipated This chart applies if no airflow is used with the heat sink Table 11 5 lists the calculations based on this chart Table 11 5 Thermal Parameters with Heat Sink and No Airflow Technique Spec adl e LE MC68040 o sw sie 26776 m o sow 9o2 234 3 o noo sow eec s 2 146 o 7419 sow reo
420. point instruction At this point the destination contains the rounding mode values as listed in MOTOROLA M68040 USER S MANUAL 9 37 Table 9 15 and the user exception handler can choose to modify these values and E1 of the floating point state frame bits need to be examined to determine which fields in the floating point state frame are valid E3 always takes precedence and must always be serviced first Table 9 16 lists the floating point state frame fields for INEX exceptions with set or with clear and E1 set It is possible for an FADD FSUB FMUL and FDIV to report a post instruction exception although these instructions normally generate a pre instruction exception The following example shows why a post instruction exception is generated FADD FP2 FPO this instruction generates an inexact exception FMOVE ea this instruction is executing when inexact occurs For this example assume that the FMOVE instruction starts once the FADD instruction generates an underflow Given the register dependency on the destination of the FADD instruction FPO needs to be resolved prior to the FMOVE instruction execution For this example there is no choice but to have the FADD instruction report a post instruction exception immediately Note that for this case even though the T bit of the floating point state frame is set post instruction exception it does not imply an FMOVE OUT instruction Therefor
421. power stop mode During this extension the processor is ready for bus arbitration Upon termination of the LPSTOP broadcast cycle the status register SR is updated with the data portion of the immediate operand updating the interrupt priority mask level The IU updates the processor status lines PST3 PSTO with the new status code of 6 and halts Then SCD is asserted signaling the beginning of the low power stop mode All instructions in the integer unit pipeline that followed LPSTOP remain in the pipeline during the low power stop mode The processor stays in the low power stop mode until a non masked interrupt or reset exception occurs A non masked interrupt exception is defined as a higher priority than the value in the interrupt priority mask bits of the SR while holding the interrupt priority level IPLx lines until IPEND is asserted IPLx are used in the low power stop mode to restart the clocks and return the processor to normal operation If an interrupt request has a priority higher than the value in the interrupt priority mask bits of the SR the clock control logic negates SCD and restarts the PLL If the pending interrupt has a lower priority than the interrupt priority mask bits the clock logic doesn t restart the PLL and the processor will not resume normal operation MC68040V and MC68ECO040V will enter low power mode regardless of any interrupts that are pending once the LPSTOP instruction starts Once the clock cont
422. processing Operation 9 15 9 5 1 Underflow Round Overflow 9 16 9 5 2 Gondilional EG DAN ERE BR EHE 9 16 9 6 Floating Point Exceptions aad one 9 20 9 6 1 Unimplemented Floating Point 9 20 9 6 2 Unsupported Floating Point Data Types 9 22 9 7 Floating Point Arithmetic Exceptions 9 24 9 7 1 Branch Set on Unordered BSUN 9 25 9 7 1 1 Maskable Exception 2 9 26 9 7 1 2 Nonmaskable Exception Conditions 9 27 9 7 2 Signaling Not a Number 5 9 27 9 7 2 1 Maskable Exception 9 27 9 7 2 2 Nonmaskable Exception Conditions 9 27 9 7 3 EITOD ios enda ber ete tette el recedet 9 28 9 7 3 1 Maskable Exception Conditions 9 29 9 7 3 2 Nonmaskable Exception Conditions 9 30 9 7 4 eue Ren EMPTORE TA 9 31 9 7 4 1 Maskable Exception 9 31 9 7
423. processing in progress when 5 is recognized processing cannot be recovered Figure 8 5 is a flowchart of the reset exception processing The reset exception places the processor in the interrupt mode of the supervisor privilege mode by setting the S bit and clearing the M bit and disables tracing by clearing the T1 and TO bits in the SR This exception also sets the processor s interrupt priority mask in the SR to the highest level level 7 Next the VBR is initialized to zero 00000000 and the enable bits in the cache control register CACR for the on chip caches are cleared The reset exception also clears the enable bit but does not affect page size in the translation control registers It clears the enable bit in each of the four transparent translation registers An interrupt acknowledge bus cycle is begun to generate a vector number This vector number references the reset exception vector two long words vector numbers 0 and 1 at offset zero in the supervisor address space The first long word is loaded into the interrupt stack pointer and the second long word is loaded into the PC Reset exception processing concludes with the prefetch of the first four long words beginning at the memory location pointed to by the PC MOTOROLA M68040 USER S MANUAL 8 17 ENTRY 5 T1 TO 12 10 VBR CACR DTTnIE bit ITTn E bit FETCH VECTOR 0 OTHERWISE BUS ERROR VECTOR 0 DOUBLE BUS FAULT FETCH VECTOR 1
424. processor allows all pending accesses to complete before reporting an instruction fault the stack frame for an instruction fault will not contain any pending write backs The bit of the SSW is used to distinguish between ATC faults and physical bus errors and the FA field contains the logical address of the instruction prefetch For faults the exception handler can execute a PTEST instruction using the FA and TM fields from the SSW to determine the specific cause of the address translation failure After the handler corrects the cause of the fault it executes an RTE instruction to restart execution of the instruction that contained the faulted prefetch For an address error fault the processor saves a format 2 exception stack frame on the stack This stack frame contains the PC pointing to the instruction that caused the address error well as the actual address referenced by the instruction Note that bit 0 of the referenced address is cleared on the stack frame Address error faults must be repaired in software For a fault due to a data ATC fault or bus error pending write backs are also saved on the access error stack frame and must be completed by the exception handler For the faulted access the fault address in the FA field combined with the transfer attribute information from the SSW can be used to identify the cause of the fault In identifying the fault the system programmer should be aware that the data memory unit
425. ptimized to reduce the execution time of compiler generated code The MC68EC040 is pin compatible with the MC68040 and MC68LC040 The MC68EC040 is implemented in Motorola s latest HCMOS technology providing an ideal balance between speed power and physical device size Figure B 1 provides a simplified block diagram of the 68 040 The main features of the MC68EC040 include MC68040 Compatible Integer Execution Unit 4 Kbyte Instruction Cache and 4 Kbyte Data Cache Accessible Simultaneously 32 Bit Nonmultiplexed External Address and Data Buses with Synchronous Bursting Interface User Object Code Compatible with All M68000 Microprocessors Concurrent Integer Unit ACU and Bus Controller Operation Maximizes Throughput Low Latency Bus Accesses for Reduced Cache Miss Penalty Multimaster Multiprocessor Support via Bus Snooping 4 Gbyte Direct Addressing Range MOTOROLA M68040 USER S MANUAL 1 INSTRUCTION DATA BUS INSTRUCTION CACHE 1 INSTRUCTION INSTRUCTION ADDRESS INSTRUCTION 5 5 EECH CONTROLLER INSTRUCTION ACCESS CONTROL UNIT B U ADDRESS 5 BUS EFFECTIVE ADDRESS CALCULATE EFFECTIVE N DATA ADDRESS T R 0 L ops DATA ACCESS CONTROL UNIT L DATA BUS 5 CACHE ACCESS SNOOP CONTROL CONTROLLER SIGNALS V OPERAND DATA BUS Figure B 1 MC68EC040 Block Diagram With the exception of the memory management unit MMU the
426. put Latch Cell O Latch TO NEXT CELL TO SYSTEM lt m LOGIC CLOCK DR FROM SHIFT DR Figure C 7 Input Pin Cell I Pin C 14 M68040 USER S MANUAL MOTOROLA 1 AND CLAMP 0 OTHERWISE SHIFT DR TO NEXT CELL OUTPUT CONTROL FROM SYSTEM LOGIC TO OUTPUT gt gt BUFFER 1 DRIVE FROM CLOCK DR RESET LAST CELL UPDATE BSR Figure C 8 Output Control Cells IO Ctl TO NEXT CELL A OUTPUT ENABLE i INPUT DATA FROM TO NEXT LAST CELL PIN PAIR Figure C 9 General Arrangement of Bidirectional Pins MOTOROLA M68040 USER S MANUAL C 15 All 68040 MC68ECO40V bidirectional pins include two boundary scan data cells an input and an output One of five associated boundary scan control cells controls each bidirectional pin If these cells contain a logic one the associated bidirectional or three state pin will be configured as an output and enabled The cell captures the current value during the capture DR state All five control cells are reset i e logic zero in the test logic reset state The five bidirectional three state control cells their boundary scan register bit positions and the 188 boundary scan bit definitions are not currently available C 6 3 Restrictions Control over the output enable signals using the boundary scan register and the EXTEST and HIGHZ instructions requires a compatible circuit board test environme
427. r DIV O exception taken and exception processing is approximately 16 ea calculate clocks For example DIV W 0 Dn takes approximately 24 clocks in both the ea calculate and execute times to execute the divide instruction perform exception stacking fetch the exception vector and prefetch the next instruction 10 20 M68040 USER S MANUAL MOTOROLA 10 6 INTEGER UNIT INSTRUCTION TIMINGS Addressing lt ea gt lt ea gt lt ea gt a 416 416 ba RET ba BRIN od TIT 10 M68040 USER S MANUAL 10 21 10 6 INTEGER UNIT INSTRUCTION TIMINGS Continued Addressing ea ea ea Calculate Calculate Calculate 1 2 2 An 416 d16 PC xxx W xxx L lt XXX gt dg An Xn dg PC Xn BR Xn bd BR Xn bd BR Xn ba Les NOTES a This instruction interlocks the lt ea gt calculate and execute stages b Times listed are minimum This instruction interlocks the lt ea gt calculate and execute stages and synchronizes some portions of the processor before execution 10 22 M68040 USER S MANUAL MOTOROLA 10 6 INTEGER UNIT INSTRUCTION TIMINGS Continued MOVEA L MOVEM list gt lt ea gt b c MOVEM L lt ea gt lt list gt b c Addressing lt ea gt lt ea gt lt ea gt Mode wr me s em in x r Jee ey ee L3 LLL s queis tm
428. r 6 2 6 6 Test Data Register 6 3 6 2 JTAG Scan A 5 B 5 Output Drivers 6 4 6 5 Registers see JTAG Registers System Clock Restriction 6 3 TAP Controller 6 1 6 2 6 6 6 13 Junction Temperature 11 29 11 30 L Line Filling 7 6 7 12 7 13 Line Bus Cycles see Bus Cycles Locked Bus Cycles see Bus Cycles Logical Address 2 3 2 7 3 29 4 3 3 2 3 4 Format 3 8 Space 1 8 Defined 3 29 M68040FPSP Exception Handler 9 23 BSUN 9 26 OPERR 9 30 OVFL 9 31 9 32 SNAN 9 27 9 28 Unimplemented Instruction 9 35 9 38 MOTOROLA 68 040 4 Kbyte Size 4 Access Control Registers see Access Control Unit Address Space B 5 DLE Mode 1 2 Electrical Characteristics 11 19 Exception Processing B 10 Multiplexed Bus Mode 1 2 Output Buffer Mode 1 2 Special Modes of Operation 1 2 B 5 Unimplemented Floating Point Instruction Exceptions 1 2 B 10 MC68LC040 DLE Mode 1 2 A 5 Electrical Characteristics 11 15 Exception Processing A 6 F Line Exception A 6 Main Features A 2 Multiplex Bus Mode 1 2 A 5 Output Buffers A 5 Special Modes of Operation 1 2 Unimplemented Floating Point Instruction Exceptions 1 2 A 5 Memory Controller 7 13 Memory Management Unit MMU 1 4 Cache Controller 3 2 Disable Dynamically 5 14 Memory Controller 7 13 Translation Tables 3 2 Memory Management Unit Registers 3 33 Initializing 3 32 MMU Status Register MMUSR 1 8 3 3 3 15 Field Definitions 3 6 3
429. r SSW RW 0 TT 0 TM 1 or 5 The assertion of TEA causes this error when a normal write bus cycle is in progress The FA field contains the logical address of the fault and the WB1S field indicates that it is valid The and WB1A are equivalent WB2S and WB3S fields indicate up to two additional write backs 4 MOVE16 Write Physical Bus Error SSW RW TT 1 The assertion of TEA causes this error during the write portion of a MOVE16 instruction The FA field contains the logical address of the fault and the WB1S field indicates that it is valid All four long words are contained in LW3 LWO and must be written out before using FA Software must ensure that address bits 1 and 0 are both clear if regular move instruction are to be used to write out to the destination 5 Page Fault SSW RW 0 WB1S V 0 The FA field contains the physical address of the faulted instruction WB1S 0 WB2S indicates that it is valid Only WB3S can indicate an additional write back If WB2S indicates a MOVE16 instruction and if the MOVE 16 instruction is used to read from a peripheral that cannot tolerate double reads then software must write the data contained in PDO out to memory and increment the stacked PC to take it beyond the MOVE16 instruction that caused the page fault Otherwise if the MOVE16 instruction is allowed to be restarted another read from the peripheral would occur If double reads can be tolerat
430. r an active task The operating system can dynamically allocate the translation table based on requests for access to particular areas As in demand paging it is difficult if not impossible to predict the areas of memory that a task uses over any extended period Instead of attempting to predict the requirements of the task the operating system performs no action for a task until a demand is made requesting access to a previously unused area or an area that is no longer resident in memory This technique can be used to efficiently create a translation table for a task For example consider an operating system that is preparing the system to execute a previously unexecuted task that has no translation table Rather than guessing what the memory usage requirements of the task are the operating system creates a translation table for the task that maps one page corresponding to the initial value of the program counter PC for that task and one page corresponding to the initial stack pointer of the task All other branches of the translation table for this task remain unallocated until the task requests access to the areas mapped by these branches This technique allows the operating system to construct a minimal translation table for each task conserving physical memory utilization and minimizing operating system overhead 3 2 5 Table Search Accesses The cache treats table search accesses that are not read modify write accesses as cachable write
431. r each class of floating point exceptions and a mode byte that sets the user selectable rounding and precision modes A floating point status register FPSR contains a condition code byte quotient byte exception status byte and accrued exception byte A floating point exception handler can use the address in the 32 bit floating point instruction address register FPIAR to locate the floating point instruction that has caused an exception Instructions that do not modify the FPIAR can be used to read the FPIAR in the exception handler without changing the previous value 1 8 M68040 USER S MANUAL MOTOROLA 1 7 DATA FORMAT SUMMARY The M68040 supports the basic data formats of the M68000 family Some data formats apply only to the IU some only to the FPU and some to both In addition the instruction set supports operations on other data formats such as memory addresses The operand data formats supported by the IU are the standard twos complement data formats defined in the M68000 family architecture plus a new data format 16 byte block for the 16 instruction Registers memory or instructions themselves can contain IU operands The operand size for each instruction is either explicitly encoded in the instruction or implicitly defined by the instruction operation Whenever an integer is used in a floating point operation the FPU automatically converts it to an extended precision floating point number before using the integer The
432. r impedance selection mode The DLE pin name has been changed to 50 e The MC68L C040 does not implement the data latch DLE or multiplexed bus modes of operation All timing and drive capabilities of the MC68LC040 are equivalent to those of the MC68040 in small output buffer impedance mode e The MC68L C040 does not contain an FPU which causes unimplemented floating point exceptions to occur using a new eight word stack frame format A 2 INTERRUPT PRIORITY LEVEL IPL2 IPLO The IPL2 IPLO pins do not have any affect on the selection of output buffer impedance A 3 JTAG SCAN JS0 The MC68040 DLE pin name has been changed to 50 During normal operation the 50 pin cannot float it must be tied to GND or Vcc directly or through a resistor During board testing this pin retains the functionality of the JTAG scan of the MC68040 for compatibility purposes Refer to Section 6 IEEE 1149 1 Test Access Port JTAG for details concerning IEEE 1149 1 Standard Test Access Port and Boundary Scan Architecture A 4 DATA LATCH AND MULTIPLEXED BUS MODES The MC68LC040 does not implement the data latch or multiplexed modes of operation The CDIS pin is ignored at the rising edge of reset All timing and drive capabilities of the MC68LC040 are equivalent to those of the MC68040 in small output buffer impedance mode A 5 FLOATING POINT UNIT FPU The FPU is not implemented on the MC68L C040 All floating point instructions cause unimple
433. r lines and replace the tag and data contents of the line with the new line information Before replacement dirty lines are temporarily buffered and later copied back to memory after the new line has been read from memory If a snoop access occurs before the buffered line is written to memory the snoop controller snoops the buffer and the caches Figure 4 6 illustrates the three possible states for a data cache line with the possible transitions caused by either the processor or snooped accesses Transitions are labeled with a capital letter indicating the previous state followed by a number indicating the specific case listed in Table 4 4 MOTOROLA M68040 USER S MANUAL 4 15 V7 CINV V1 CPU READ MISS V8 CPUSH V2 CPU READ HIT V10 SNOOP READ HIT INVALIDATE V4 CPU WRITE MISS WT V11 SNOOP WRITE HIT INVALIDATE V6 CPU WRITE HIT WT I4 CPU WRITE MISSIWT V9 SNOOP READ HIT LEAVE DIRTY 17 CINV V12 SNOOP WRITE HIT SINK DATA amp I8 CPUSH SIZE LINE V13 SNOOP WRITE HIT SINK DATA amp SIZE LINE I1 CPU READ MISS D7 CINV I3 CPU WRITE MISS CB V3 CPU WRITE 55 D8 CPUSH V5 CPU WRITE HIT CB D10 SNOOP READ HIT INVALIDATE D11 SNOOP WRITE HIT D1 CPU READ MISS INVALIDATE D13 SNOOP WRITE HIT SINK DATA amp SIZE LINE D2 CPU READ HIT D3 CPU WRITE MISS CB D4 CPU WRITE MISS WT pe D5 CPU WRITE HIT CB WT WRITE THROUGH MODE EAD IT LERVE DIRTY
434. r many factors in choosing a heat sink heat sink size and composition method of attachment and choice of a dry or wet i e thermal grease connection The following paragraphs discuss the relationship of these decisions to the thermal performance of the design noticed during experimentation The heat sink size is one of the most significant parameters to consider in the selection of a heat sink Obviously a larger heat sink provides better cooling Under forced air conditions as low as 100 LFM the difference between the is very small 0 4 C W or less This difference continues to decrease as the forced airflow increases The area of this example heat sink base perimeter is 1 8 x 1 8 with a height of 0 65 The heat sink used a pin fin i e bed of nails design composed of aluminum alloy Figure 11 32 illustrates the heat sink which can be obtained through Thermalloy Inc MOTOROLA M68040 USER S MANUAL 11 19 HEAT SINK PIN GRID ARRAY NOTE Do not cover up microprocessor markings with an adhesive mounted heat sink Figure 11 10 Heat Sink with Adhesive All pin fin heat sinks tested were made from extrusion aluminum products The planar face of the heat sink matting to the package should have a good degree of planarity if it has any curvature the curvature should be convex at the central region of the heat sink surface to provide intimate physical contact to the PGA surface This heat sinks meet this criteria Non
435. r way set associative caches have 64 sets of four 16 byte lines There are two formats that define each cache line an instruction cache line format and a data cache line format Each format contains an address tag consisting of the upper 22 bits of the physical address status information and four long words 128 bits of data The status information for the instruction cache line address tag consists of a single valid bit for the entire line The status information for the data cache line address tag contains a valid bit and four additional bits to indicate dirty status for each long word in the line Note that only the data cache supports dirty cache lines Figure 4 2 illustrates the instruction cache line format a and the data cache line format b 4 2 M68040 USER S MANUAL MOTOROLA a Instruction Cache Line C v u ws Ie w o w TAG 22 Bit Physical Address Tag V Line VALID Bit LW Long Word n 32 Bit Data Entry Dn DIRTY Bit for Long Word n b Data Cache Line Figure 4 2 Cache Line Formats The cache stores an entire line providing validity on a line by line basis Only burst mode accesses that successfully read four long words can be cached Memory devices unable to support bursting can respond to a cache line read or write access by asserting the transfer burst inhibit TBI signal forcing the processor to complete the access as a sequence of three long word accesses The cache recognizes burst acces
436. ranslation registers in the MC68040 The MC68EC040 and MC68bECO040V do not implement the DLE multiplexed or output buffer impedance selection modes of operation They only implement the small output buffer mode of operation All MC68EC040 and MC68bECOA0V timing and drive capabilities are equivalent to the MC68040 in small output buffer mode MC68EC040 and MC68ECO040V do not contain an FPU causing unimplemented floating point exceptions to occur using a new stack frame format The 68040 is 3 3 volt static microprocessor that operates down to 0 MHz Refer to Appendix B MC68EC040 for specific details on the MC68EC040 Refer to Appendix 68 040 and Appendix MC68040V and MC68ECO40V for specific details on the MC68EC040V Disregard information concerning the FPU and MMU when reading the following subsections 1 2 M68040 USER S MANUAL MOTOROLA 1 2 5 The main features of the M68040 are as follows 6 Stage Pipeline MC68030 Compatible IU MC68881 MC68882 Compatible FPU Independent Instruction and Data MMUs Simultaneously Accessible 4 Kbyte Physical Instruction Cache and 4 Kbyte Physical Data Cache Low Latency Bus Accesses for Reduced Cache Miss Penalty Multimaster Multiprocessor Support via Bus Snooping Concurrent IU FPU MMU and Bus Controller Operation Maximizes Throughput 32 Bit Nonmultiplexed External Address and Data Buses with Synchronous Interface User Object Code Compatible wit
437. rd Instruction word patterns with bits 15 12 equal to A do not correspond to legal instructions for the M68040 and are treated as unimplemented instructions A word patterns are referred to as an unimplemented instruction with A line opcodes When the processor attempts to execute an unimplemented instruction with an A line opcode an exception is generated with vector number 10 permitting efficient emulation of unimplemented instructions For instruction word patterns with bits 15 12 equal to F refer to Section 9 Floating Point Unit MC68040 Only Exception processing for illegal and unimplemented instructions is similar to that for instruction traps When the processor has identified an illegal or unimplemented instruction it initiates exception processing instead of attempting to execute the instruction The processor copies the SR enters the supervisor mode and clears T1 and TO disabling further tracing The processor generates the vector number either 4 or 10 according to the exception type The illegal or unimplemented instruction vector offset current PC and copy of the SR are saved on the supervisor stack with the saved value of the PC being the address of the illegal or unimplemented instruction Instruction execution resumes at the address contained in the exception vector It is the responsibility of the exception handling routine to adjust the stacked if the instruction is emulated in software or is to be skipped on re
438. rd Test Access Port and Boundary Scan Architecture Problems associated with testing high density circuit boards have led to the development of this standard under the IEEE Test Technology Committee and Joint Test Action Group JTAG sponsorship The M68040 implementation supports circuit board test strategies based on this standard However the JTAG interface is not intended to provide an in circuit test to verify M68040 operations therefore it is impossible to test M68040 operations using this interface Section 6 IEEE 1149 1 Test Access Port JTAG describes the M68040 implementation of the IEEE 1149 1 and is intended to be used with the supporting IEEE document 5 12 1 Test Clock TCK This input signal is used as a dedicated clock for the test logic Since clocking of the test logic is independent of the normal operation of the MC68040 several other components on a board can share a common test clock with the processor even though each component may operate from a different system clock The design of the test logic allows the test clock to run at low frequencies or to be gated off entirely as required for test purposes 5 12 2 Test Mode Select TMS This input signal is decoded by the TAP controller and distinguishes the principle operationas of the test support circuitry 5 12 3 Test Data In TDI This input signal provides a serial data input to the TAP 5 12 4 Test Data Out TDO This three state output signal provides a seria
439. re TCK periods following TRST negation ensures that the TAP controller is in the run test idle state 6 5 DISABLING THE IEEE STANDARD 1149 1A OPERATION There are two considerations for non IEEE standard 1149 14 operation First does not include an internal pullup resistor and should not be left unconnected to preclude mid level inputs The second consideration is to ensure that the IEEE standard 1149 14 test logic remains transparent to the system logic by providing the ability to force the test logic reset state Figure 6 7 illustrates disabling the IEEE standard 1149 1A operation through connecting TRST directly or through a resistor to ground or a suitable logic network Connecting TRST to RSTI while TCK is held either high or low meets the two considerations If a pulse asserts TRST the TAP controller is forced into the test logic reset state and can remain this state as long as a rising edge on the TCK signal does not occur when TMS is low MOTOROLA M68040 USER S MANUAL 6 13 TV TDI TCLK TDO NO CONNECTION Figure 6 7 Circuit Disabling IEEE Standard 1149 1A 6 14 M68040 USER S MANUAL MOTOROLA 6 6 MOTOROLA M68040 BSDL DESCRIPTION VERSION 2 2 Revision List No other changes to Version 2 1 BSDL DRVCTL 5 for syntax compatibility 6 No other changes to Version 1 0 BSDL Package Type 18x18 PGA LOCK and LOCKE controlled by io 1 vice 10 0 40980 Instruction opco
440. read modify write transfer for the CAS and CAS2 instructions in the M68040 differs from those used by previous members of the M68000 family If an operand does not match one of these instructions the M68040 still executes a single write transfer to terminate the locked sequence with LOCKE asserted For the CAS instruction the value read from memory is written back for the CAS2 instruction the second operand read is written back Figure 7 18 illustrates a functional timing diagram for a TAS instruction read modify write bus transfer Clock 1 C1 The read cycle starts in C1 During the first half of C1 the processor places valid values on the address bus and transfer attributes LOCK is asserted to identify a locked read modify write bus cycle For user and supervisor mode accesses which the corresponding memory unit translates the UPAx signals are driven with the values from the matching U1 and UO bits The TTx and TMx signals identify the specific access type R W is driven high for a read cycle CIOUT is asserted if the access is identified as noncachable The processor asserts TS during C1 to indicate the beginning of a bus cycle If not already asserted from a previous bus cycle the TIP signal is also asserted at this time to indicate that a bus cycle is active Refer to Section 3 Memory Management Unit Except 68 040 and 68 040 for information on the M68040 and MC68LC040 memory units and Appendix B 68 040 for inf
441. recision 0 FSADD and FDMUL the destination is rounded using the precision defined by the instruction If in the process of denormalizing the intermediate result all of the most significant bits are shifted off to the right the selected rounding mode determines the value to be stored at the destination Table 9 13 lists these values Once the result is stored in the destination the M68040FPSP UNFL exception handler checks to see if the user UNFL exception handler is enabled Table 9 13 Underflow Rounding Mode Values Rounding Mode j Zero with the sign of the intermediate result Zero with the sign of the intermediate result For positive overflow zero for negative underflow smallest denormalized negative number For positive overflow smallest denormalized positive number for negative underflow zero 9 34 M68040 USER S MANUAL MOTOROLA a If the user UNFL exception handler is disabled the M68040FPSP UNFL exception handler checks for an INEX1 or INEX2 exception condition with the user INEX exception handler enabled If not the processor returns to normal instruction flow Otherwise the M68040FPSP UNFL exception handler restores the FPU to its exceptional state cleans up the stack to the conditions prior to execution and continues instruction execution at the user INEX exception handler No parameters are passed to the user INEX exception handler since the M68040FPSP UNFL exception handler provides the
442. ress for the first byte of the operand to be accessed A1 and AO indicate the byte offset from the base For a burst inhibited line transfer A1 and AO for each of the four accesses the burst inhibited line transfer and three long word transfers are copied from the lowest two bits of the access address used to initiate the line transfer MOTOROLA M68040 USER S MANUAL 7 3 24 23 16 15 REGISTER MULTIPLEXER ROUTING t INTERNAL TO THE 68040 EXTERNAL DATA BUS D31 D24 D23 D16 D15 D8 07 00 ADDRESS XXXXXXX0 Figure 7 3 Data Multiplexing Table 7 1 lists the combinations of the SIZx A1 and AO signals collectively called byte enable signals that are used for each of the four sections of the data bus In the table BYTEn indicates the data bus section that is active the portion of the requested operand that is read or written during that bus transfer For line transfers all bytes are valid as listed and can correspond to portions of the requested operand or to data required to fill the remainder of the cache line The bytes labeled with a dash are not required they are ignored on read transfers and driven with undefined data on write transfers Not selecting these bytes prevents incorrect accesses in sensitive areas such as devices Figure 7 4 illustrates a logic diagram for one method for generating byte enable signals from the SIZx 1 and AO and the associated PAL equation These byte enable sig
443. rithmetic exceptions causes the FSAVE to generate either the 26 word unimplemented instruction state frame or the 50 word busy state frame For a hardware reset or an FRESTORE of a null state frame the FSAVE instruction generates a null state frame This null state frame is generated until the first nonconditional floating point instruction is executed conditionals include FNOP FBcc FDBcc FScc and FTRAPcc Floating point conditional instructions do not set an internal flag which changes the state frame from null to idle If these instructions are the only ones executed after a reset or an FRESTORE of a null state frame then when FSAVE is executed it stacks a null state frame instead of an idle state frame Note that this function is different from that of the MC68881 and MC68882 and software must be aware of this difference if compatibility with the MC68881 and MC68882 is desired Once nonconditional floating point instruction is executed an FSAVE generates an idle state frame The idle state frame is generated whenever the FPU has no exceptions pending An idle state frame is saved if no exceptions are pending and at least one instruction has been executed since the last hardware reset or FRESTORE of a null state frame A 26 word unimplemented floating point instruction state frame is saved if the last instruction was an unimplemented floating point instruction Figure 9 10 illustrates each of these state frames followed by definitions for
444. rmat Summary Data Type Y 3 Digit 1 Digit 16 Digit Fraction Exponent Integer ot 1 1 1 XXXX 00 00 0 o or x x sooo o on x x 5000 8059 000 899 85 9 4 COMPUTATIONAL ACCURACY Whenever an attempt is made to represent a real number in a binary format of finite precision there is a possibility that the number can not be represented exactly This is commonly referred to as a round off error Furthermore when two inexact numbers are used in a calculation the error present in each number is reflected and possibly aggravated in the result All FPU calculations use an intermediate result When the MC68040 performs an operation the calculation is carried out using extended precision inputs and the intermediate result is calculated as if to produce infinite precision After the calculation is complete the intermediate result is rounded to the selected precision and stored in the destination The FPCR encodings provide emulation for devices that only support single and double precision The execution speed of all instructions is the same whether using single or double precision rounding When using these two forced rounding precisions the MOTOROLA M68040 USER S MANUAL 9 11 MC68040 produces the same results as any other device that conforms to the IEEE 754 standard but does not support extended precision The results are the same when performing t
445. rmation 9 44 10 1 Instruction Timing Index te E mE 10 1 10 2 Number of Memory 10 3 10 3 GINV Timing aa retener eem xoc Econ m aure esu 10 8 10 4 CPUSH Best and Worst Case 10 8 11 1 Maximum Power Dissipation for Output Buffer Mode Configuration 11 13 11 2 Thermal Parameters with No Heat Sink or 11 17 11 3 Thermal Parameters with Forced Airflow and No Heat Sink for the 68040 11 18 11 4 Thermal Parameters with Forced Airflow and No Heat Sink for the MC68L C040 and MC68EC040 11 19 11 5 Thermal Parameters with Heat Sink and No Airflow 11 21 11 6 Thermal Parameters with Heat Sink and 11 22 C 1 Additional MC68040V and MC68ECO40V C 2 C 2 Bus Encodings During LPSTOP Broadcast Cycle C 4 C 3 IEEE Standard 1149 1A Instructions eR er er anrea C 12 E 1 MC68040 Floating Point E 2 E 2 MC68040FPSP Floating Point Instructions E 3 E 3 Support for Data Types and Data Formats E 4 E 4 EXCODHOfT Conditions dannsan as ce
446. rnate bus master transfers and intervene in the access to maintain cache coherency The encoding of the SCx signals generated by the alternate bus master for each bus cycle controls the process of bus monitoring and intervention called snooping Only byte word long word and line bus transfers can be snooped Refer to Section 4 Instruction and Data Caches for SCx encodings When the M68040 recognizes that an alternate bus master has asserted TS the processor latches the level on the byte offset SIZx TMx and R W signals during the rising edge of BCLK for which TS is first asserted The processor then evaluates the SCx signals to determine the type of access TTx 0 or 1 if it is snoopable and if So how it should be snooped If snooping is enabled for the access the processor inhibits memory from responding by continuing to assert the memory inhibit signal MI while checking the internal caches for matching lines During the snooped bus cycle the M68040 ignores all TA assertions while MI is asserted Unless the data cache contains a dirty line corresponding to the access and the requested snoop operation indicates sink data for a write or source data for a read MI is negated and memory is allowed to respond and complete the access Otherwise the processor continues to intervene in the access by keeping MI asserted and responding to the alternate bus master as a slave device The processor monitors the levels of TA TEA and T
447. rol logic negates SCD and the PLL is restarted a valid BCLK must be provided to the processor When the clocks are phase locked an interrupt a bus error or a reset exception begins The interrupt exception forces all instructions in the pipeline to be aborted that have not reached the execute stage while the reset exception aborts any processing in progress pre fetched instructions prior to entering low power stop mode and cannot be recovered C 4 M68040 USER S MANUAL MOTOROLA C 2 1 Bus Arbitration and Snooping Bus arbitration and snooping are not allowed during low power stop mode If an alternate bus master requires ownership arbitration must occur before the processor is allowed to enter low power stop mode This is achieved by externally decoding the LPSTOP broadcast cycle and negating the BG signal before the termination of the cycle allowing bus arbitration to complete at the end of the cycle If the MC68040V or the MC68bECO40V is the bus master during low power stop mode lowest power consumption cannot be achieved due to the DC loads on the processor output pins To achieve maximum power savings arbitrate bus mastership away from the processor during the LPSTOP broadcast cycle In a single bus master system the caches do not need to be shut down prior to the execution of LPSTOP In a multi master system the programmer is responsible for providing a shut down sequence for the caches C 2 2 Low Frequency Operation In additio
448. ror Aborts current instructions can have pending trace floating ATC Fault or Bus Error point post instruction or unimplemented floating point instruction exceptions Floating Point Pre Instruction Exception processing begins before current floating point instruction is executed Instruction is restarted on return from exception BKPT n CHK CHK2 Divide by Zero Exception processing is part of instruction execution FTRAPcc RTE TRAP n TRAPV Illegal Instruction Unimplemented A and Exception processing begins before instruction is executed F Line Privilege Violation Unimplemented Floating Point Instruction Exception processing begins after memory operands fetched and before instruction is executed 4 Floating Point Post Instruction Only reported for FMOVE to memory Exception processing begins when FMOVE instruction and previous exception processing have completed Address Error Reported after all previous instructions and associated exceptions have completed Trace Exception processing begins when current instruction or previous exception processing has completed Instruction Access Error Reported after all previous instructions and associated ATC Fault or Bus Error exceptions have completed Interrupt Exception processing begins when current instruction or previous exception processing has completed Refer to Section 9 Floating Point Unit MC68040 Only for details concerning floating point instructions
449. rt of the M68040 User s Manual does not apply to the 68 040 The MC68EC040 does not sample the IPL2 IPLO CDIS JSO DLE on the 68040 JS1 MDIS on the MC68040 pins on the rising edge of RSTI An external device asserts RSTI to reset the processor When power is applied to the system external circuitry should assert RSTI for a minimum of 10 BCLK cycles after V cc is within tolerance Figure B 5 is a functional timing diagram of the power on reset operation illustrating the relationships between Vcc RSTI and bus signals The BCLK and PCLK clock signals are required to be stable by the time Vcc reaches the minimum operating specification RSTI is internally synchronized for two BCLKS before being used and must meet the specified setup and hold times to BCLK specifications 51 and 52 in B 7 68 040 Electrical Characteristics only if recognition by a specific BCLK rising edge is required lt t210 gt lt 128 gt CLOCKS CLOCKS CLOCKS BCLK Undefined Figure B 5 MC68EC040 Initial Power On Reset Timing 8 M68040 USER S MANUAL MOTOROLA Once RSTI is negated the processor is internally held in reset for another 128 clock cycles During the reset period all three statable signals are three stated and the rest are driven to their inactive state Once the internal reset signal negates all bus signals remain in a high impedance state until the processor is granted the bus After this the
450. rupt Autovector 074 Level 5 Interrupt Autovector 078 Level 6 Interrupt Autovector 07C Level 7 Interrupt Autovector 32 47 080 0BC TRAP 40 15 Instruction Vectors 48 55 0C0 0DC Floating Point Exception Vectors see Note 56 0 0 Defined for MC68030 and MC68851 not used by 68040 0 4 Defined for MC68851 not used by 68040 0 8 Defined for MC68851 not used M68040 58 59 63 Unassigned Reserved 64 255 100 User Defined Vectors 192 NOTE Refer to Section 9 Floating Point Unit MC68040 Only 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 24 25 26 27 28 29 30 31 8 2 INTEGER UNIT EXCEPTIONS The following paragraphs describe the external interrupt exceptions and the different types of exceptions generated internally by the M68040 integer unit The following exceptions are discussed Access Fault Address Error Instruction Trap Illegal and Unimplemented Instructions Privilege Violation MOTOROLA M68040 USER S MANUAL 8 amp 5 Trace Format Error Breakpoint Instruction Interrupt Reset 8 2 1 Access Fault Exception An access fault exception occurs when a data or instruction prefetch access faults due to either an external bus error or an internal access fault Both types of access faults are treated identically and the access fault exception handler or a status bit in the access fault stack frame distinguishes them An access fault exception may or may not be tak
451. ry arithmetic instruction ends by rounding the result and checking for overflow and underflow At the completion of an arithmetic operation the intermediate result is checked to see if it is too small to be represented as a normalized number in the selected precision If so the UNFL bit is set in the FPSR EXC byte The MC68040 then takes a nonmaskable underflow exception and executes the M68040FPSP underflow exception handler denormalizing the result Denormalizing a number causes a loss of accuracy but a zero is not returned unless absolutely necessary If a number has grossly underflowed the M68040FPSP returns a zero or the smallest denormalized number with the correct sign depending on the rounding mode in effect If no underflow occurs the intermediate result is rounded according to the user selected rounding precision and rounding mode After rounding the INEX2 bit of the FPSR EXC byte is set accordingly Finally the magnitude of the result is checked to see if it is too large to be represented in the current rounding precision If so the OVFL bit of the FPSR EXC byte is set The M68040FPSP returns a correctly signed infinity or a correctly signed largest normalized number depending on the rounding mode in effect 9 5 2 Conditional Testing Unlike the integer arithmetic condition codes an instruction either always sets the floating point condition codes in the same way or it does not change them at all Therefore the instruction de
452. s Maximum Power Dissipation for Large Buffer Mode All Outputs Number of Pins Large Buffer Mode Number of Pins Capable of the Large Buffer Mode Table 11 1 lists the simplified relationship on the maximum power dissipation for eight possible configurations of output buffer modes Table 11 1 Maximum Power Dissipation for Output Buffer Mode Configurations Output Configuration Address Bus and Data Bus Transfer Attributes Control Signals Maximum Power Dissipation MC68LC040 and MC68EC040 only utilize this row of information To calculate the specific power dissipation of a design the termination method of each signal must be considered For example a signal output that is not connected would not dissipate any additional power if it were configured in the large rather than the small buffer mode Since the maximum operating junction temperature is specified as 110 C the maximum case temperature Tc in can be obtained from the following equation Tc Tj Pp x Gc where Tc Maximum Case Temperature Maximum Junction Temperature Pp Maximum Power Dissipation of the Device Thermal Resistance between the Junction of the Die and the Case MOTOROLA M68040 USER S MANUAL 11 13 In general the ambient temperature TA in C is a function of the following equation Ta Pp x x 0cA The thermal resistance from case to outside ambient
453. s roe oe ett vtt tro py aste 12 9 12 2 Package 12 10 A 1 MC68LC040 te eet edo b edt pde A 2 A 2 MC68LC040 Programming A 3 A 3 MC68LC040 Functional Signal Groups A 4 A 4 Clock Input Timing Diagram eer one aeta coe A 10 A 5 Read Write Timing RR EU A 13 A 6 Bus Arbitration Timing A 14 A 7 Snoop Hit MING 15 8 Snoop Miss TIMING asua q 16 9 Other Signal TIMING 17 1 68 040 Block 2 2 MC68ECO040 Programming B 3 B 3 MC68ECO040 Functional Signal B 4 B 4 MC68ECO040 Access Control Register Format B 6 B 5 MC68EC040 Initial Power On Reset B 8 B 6 MC68ECO040 Normal Reset B 9 B 7 Clock Input Timing Diagram el deb ee ae cae es B 14 B 8 Read Write TIMING dias baci 17 9 Bus Arbitration
454. s The bus controller responds by terminating the line access and completes the remainder of the line push as three sequential long word writes The first cycle of the burst can be retried but the bus controller interprets a retry for any of the three remaining cycles as a bus error If a bus error occurs in any cycle in the line push transfer the processor immediately takes an exception A dirty cache line hit by a cache inhibited access is pushed before the external bus access occurs If the access is part of a locked transfer sequence for TAS CAS or CAS2 operand accesses or translation table updates the LOCK signal is also asserted for the push access 4 7 CACHE OPERATION SUMMARY The instruction and data caches function independently when servicing access requests from the IU The following paragraphs discuss the operational details for the caches and present state diagrams depicting the cache line state transitions MOTOROLA M68040 USER S MANUAL 4 13 4 7 1 Instruction Cache The IU uses the instruction cache to store instruction prefetches as it requests them Instruction prefetches are normally requested from sequential memory locations except when a change of program flow occurs e g a branch taken or when an instruction that can modify the status register SR is executed in which case the instruction pipe is automatically flushed and refilled The instruction cache supports a line based protocol that allows individual cach
455. s The default memory access caching mode is nonserialized When the cache is enabled and memory management is disabled the default caching mode is write through The transparent translation registers and MMUs allow the defaults to be overridden In addition some instructions and IU operations perform data accesses that have an implicit caching mode associated with them The following paragraphs discuss the different caching accesses and their related cache modes 4 3 1 Cachable Accesses If a page CM field indicates write through or copyback then the access is cachable A read access to a write through or copyback page is read from the cache if matching data is found Otherwise the data is read from memory and used to update the cache Since instruction cache accesses are always reads the selection of write through or copyback modes do not affected them The following paragraphs describe the write through and copyback modes in detail 4 3 1 1 WRITE THROUGH MODE Accesses to pages specified as write through are always written to the external address although the cycle can be buffered keeping memory and cache data consistent Writes in write through mode are handled with a no write allocate policy i e writes that miss in a data cache are written to memory but do not cause the corresponding line in memory to be loaded into the cache Write accesses always write through to memory and update matching cache lines Specifying
456. s an input 5 7 PROCESSOR CONTROL SIGNALS The following signals control disabling caches and memory management units MMUs and support processor and external device initialization 5 7 1 Cache Disable CDIS CDIS dynamically disables the on chip caches on the next internal cache access boundary does not flush the data and instruction caches entries remain unaltered and become available after is negated The assertion of CDIS does not affect snooping During a processor reset the level is latched and used to select the normal bus mode high or multiplexed bus mode 5 low Refer to Section 4 Instruction and Data Caches for information about the caches and to Section 7 Bus Operation for information about the multiplexed bus mode Refer to Appendix E 5 10 M68040 USER S MANUAL MOTOROLA 68040 Floating Point Emulation MC68040FPSP for descriptions of emulator use of this signal 5 7 2 Reset In RSTI This input signal causes the M68040 to enter reset exception processing The signal is an asynchronous input that is internally synchronized to the next rising edge of the BCLK signal All three state signals are set to the high impedance state and all outputs except MI negated when is recognized The assertion of RSTI does not affect the test pins Refer to Section 7 Bus Operation for a description of reset operation and to Sec
457. s an interrupt and the M bit of the SR is set the processor clears the M bit and builds a second stack frame on the interrupt stack Figure 8 2 illustrates the general form of the exception stack frame SP STATUS REGISTER PROGRAM COUNTER FORMAT VECTOR OFFSET ADDITIONAL PROCESSOR STATE INFORMATION 2 OR 26 WORDS IF NEEDED Figure 8 2 General Form of Exception Stack Frame The last step initiates execution of the exception handler The processor multiplies the vector number by four to determine the exception vector offset It adds the offset to the value stored in the vector base register VBR to obtain the memory address of the exception vector Next the processor loads the program counter PC and the interrupt stack pointer ISP for the reset exception from the exception vector table entry After prefetching the first four long words to fill the instruction pipe the processor resumes normal processing at the address in the PC When the processor executes an RTE instruction it examines the stack frame on top of the active supervisor stack to determine if itis a valid frame and what type of context restoration it requires All exception vectors are located in the supervisor address space and are accessed using data references Only the initial reset vector is fixed in the processor s memory map once initialization is complete there are no fixed assignments Since the VBR provides the base address of the exception
458. s an operand fetch the write back stalls in the write back stage since it is at a lower priority The write back can stall indefinitely until either the data memory unit is free or another write is pending from the execution stage Figure 2 2 illustrates a write cycle which begins in the IU pipeline The IU stores the logical address and data for a write operation in a temporary holding register WB3 Write operation control passes from the IU to the data memory unit once the data memory unit is idle When the data memory unit receives the logical address and data from the IU it stores the logical address and data to a second temporary holding register WB2 The data memory unit then translates the logical address into a physical address If the address translation is successful the data memory unit either stores an address translation in the data cache write hit or passes it to the bus controller write through with write miss Once the bus controller is ready to execute the external write operation it multiplexes the data to the correct data byte lanes and stores the multiplexed data and physical address into a third holding register WB1 WB1 is used in the actual write operation seen on the address and data buses Appendix B MC68EC040 contains details on address translation in the MC68EC040 BUS INSTRUCTION CONTROLLER FETCH INSTRUCTION MEMORY UNIT DECODE ea CALCULATE ea FETCH PHYSICAL ADDRESS EXECUTE DATA MMU
459. s are undefined for all other accesses to instruction space and are placed in a high impedance state when the processor relinquishes the bus 5 6 M68040 USER S MANUAL MOTOROLA TLNx signals can be used high performance systems to build an external snoop filter with a duplicate set of cache tags The TLNx signals and address bus provide a direct indication of the state of the data caches and can be used to help maintain the duplicate tag store The TLNx pins do not indicate the correct TLN number when an instruction cache burst fill occurs 5 3 4 User Programmable Attributes UPA1 The UPAx signals are three state outputs If they match the logical address the user programmable attribute bits in the address translation entry or the transparent translation register determine the UPAx signal level These signals are only for normal code data and 16 accesses For all other accesses including table search and cache line push accesses which may result from a normal access the UPAx signals are zero If the transparent translation register and the memory management unit are disabled the UPAx signals are also zero When the M68040 is not the bus master these signals are set to a high impedance state 5 3 5 Read Write R w This bidirectional three state signal defines the data transfer direction for the current bus cycle A high level indicates a read cycle and a low level indicates a write cycle The bus snoop co
460. s configured depending on the corresponding IPLx signal level during processor reset see Table 5 5 7 11 2 Multiplexed Bus Mode The multiplexed bus mode changes the timing of the three state control logic for the address and data buses to support generation of a multiplexed address data bus When the M68040 is operating in this mode the address and data bus signals can be hardwired together to form a single 32 bit bus with address and data information time multiplexed on the bus This configuration minimizes the number of pins required to interface to peripheral devices without requiring additional discrete multiplexing logic This mode is enabled during a processor reset by a logic zero on the CDIS signal Figure 7 46 illustrates a line write with multiplexed bus mode enabled The address bus drivers are enabled during C1 and disabled during C2 Later in C2 the data bus drivers are enabled to drive the data bus with the data to be written The address bus is only driven for the BCLK rising edge at the start of each bus cycle 7 68 M68040 USER S MANUAL MOTOROLA BCLK 5121 5120 N l NOTE The selected device increments the value of A3 and A2 Figure 7 46 Multiplexed Address and Data Bus Line Write 7 11 3 Data Latch Enable Mode The data latch enable DLE mode allows read data to be latched by the assertion of the DLE signal instead of by the BCLK rising edge at the
461. s of four cache lines The four tags from the selected cache set are compared with the translated physical address bits 31 12 and bits 11 and 10 of the untranslated page offset If any one of the four tags matches and the tag status is either valid or dirty then the cache has a hit During read accesses a half line two long words is accessed at a time requiring two cache accesses for reads that are greater than a half line or two long words Write accesses within a cache line require a single cache access If a misaligned access crosses two pages then the partial access to the first page always happens twice even if the pages are serialized Consequently if the accesses span page boundaries misaligned accesses to peripherals are not possible unless the peripheral can tolerate double reads or writes MOTOROLA M68040 USER S MANUAL 4 3 LOGICAL ADDRESS PAGE OFFSET LINE 3 SUPERVISOR BIT PHYSICAL SET SELECT PA9 PA4 LA31 LA12 Y SET 0 1 11 10 63 DATA ADDRESS TRANSLATED INSTRUCTION TRANSLATION PA3I PA2 gt PHYSICAL ADDRESS CACHE PA31 PA10 LINE SELECT HIT 2 LOGICAL OR HIT 1 COMPARATOR 0 Figure 4 3 Caching Operation Both caches contain circuitry to automatically determine which cache line in a set to use for a new line The cache controller locates the first invalid line and uses it if
462. s specifically requesting that long word Otherwise the line is not placed in the cache and the processor repeats the line access when another access references the line If a misaligned operand spans two long words in a line a bus error on either the first or second transfer for the line causes exception processing to begin immediately A bus error termination for any write accesses or for read accesses that reference data specifically requested by the execution unit causes the processor to begin exception processing immediately Refer to Section 8 Exception Processing for details of access error exception processing When bus error terminates an access the contents of the corresponding cache can be affected in different ways depending on the type of access For a cache line read to replace a valid instruction or data cache line the cache line being filled is invalidated before the bus cycle begins and remains invalid if the replacement line access is terminated with a bus error If a dirty data cache line is being replaced and a bus error occurs during the replacement line read the dirty line is restored from an internal push MOTOROLA M68040 USER S MANUAL 7 37 buffer into the cache to eliminate an unnecessary push access If a bus error occurs during a data cache push the corresponding cache line remains valid with the new line data if the line push follows a replacement line read or is invalidated if a CPUSH instruction explicitly forc
463. s suspended and low power stop mode is active system logic may remove or change the frequency of the BCLK input C 1 1 Low Frequency Operation LFO When asserted this input signal allows the frequency of BCLK to be changed instantaneously 0 to 16 MHz providing minimum pulse width constraints are met see 7 MC68040V and MC68ECO40V Electrical Characteristics LFO is only recognized during low power stop mode and reset C 1 2 Loss of Clock LOC Whenever the internal clock circuitry detects either a phase lock error or a loss of BCLK this output signal is driven high only during normal mode of clocking operation LOC is also three stated during reset low power stop or low frequency operation There should be a pull down resistor on the system board to ground C 1 3 System Clock Disable SCD When asserted this output signal indicates when asserted that the BCLK input can be disabled or changed in frequency SCD is asserted upon termination of the LPSTOP broadcast cycle BCLK must be stable when SCD is negated in accordance with the specifications 7 MC68040V and MC68ECO40V Electrical Characteristics C 2 M68040 USER S MANUAL MOTOROLA ADDRESS BUS SNOOP CONTROL BUS 5 1 AND RESPONSE DATA BUS 4 BG BUS ARBITRATION MDIS PROCESSOR RSTI CONTROL TRANSFER ATTRIBUTES Inr INTERRUPT CONTROL MC68040V MC68EC040V E PST3 STATUS AND MASTER BCLK CLOCKS TRANSFER 7 CONTROL SLAV
464. s the least significant bit High levels on all three signals correspond to no interrupt requested level 0 Values 1 7 specify one of seven levels of interrupts with level 7 having the highest priority Table 8 3 lists the interrupt levels the states of IPL2 IPLO that define each level and the SR interrupt mask value that allows an interrupt at each level Table 8 3 Interrupt Levels and Mask Values Requested Control Line Status Interrupt Mask Level Interrupt Level Required for Recognition 0 0 0 0 0 2 3 4 5 ET When an interrupt request has a priority higher than the value in the interrupt priority mask of the SR bits 10 8 the processor makes the request a pending interrupt Priority level 7 the nonmaskable interrupt is a special case Level 7 interrupts cannot be masked by the interrupt priority mask and they are transition sensitive The processor recognizes an interrupt request each time the external interrupt request level changes from some lower level to level 7 regardless of the value in the mask Figure 8 3 shows two examples of interrupt recognitions one for level 6 and one for level 7 When the M68040 processes a 8 12 M68040 USER S MANUAL MOTOROLA level 6 interrupt the SR mask is automatically updated with a value of 6 before entering the handler routine so that subsequent level 6 interrupts and lower level interrupts are masked Provided no instruction that lowers the mask value is executed t
465. s translation cache ATC miss occurs the processor searches the translation tables in memory for the mapping and then retries the access If a valid translation for the logical address is not available due to a problem encountered during the table search an internal access fault occurs when the aborted access is retried The problem encountered could be either an invalid descriptor or the assertion of the TEA signal during a bus cycle used to access the translation tables A miss in the ATC causes the processor to automatically initiate a table search but does not cause an internal access fault unless one of the three previous conditions is encountered However this is not true if the memory management unit MMU is disabled When an exception is detected all parts of the execution unit either remain or are forced to idle at which time the highest priority exception is taken Restarting the instruction or a user defined supervisor cleanup exception handler routine regenerates lower priority exceptions on the return from exception handling Internal access faults and bus errors are reported after all other pending integer instructions complete execution If an exception is generated during completion of the earlier instructions the pending instruction fault is cleared and the new exception is serviced first The processor restarts the pending prefetch after completing exception handling for the earlier instructions and takes a bus error exception i
466. scriptions do not include floating point condition code settings The following paragraphs describe how floating point condition codes are set for all instructions that modify condition codes Refer to 9 2 3 1 Floating Point Condition Code Byte for a description of the FPCC byte The condition code bits differ slightly from the integer condition codes Unlike the operation type dependent integer condition codes examining the result at the end of the operation sets or clears the floating point condition codes accordingly The M68000 family integer condition codes bits N and Z have this characteristic but the V and C bits are set differently for different instructions The data type of the operation s result determines how the four condition code bits are set Table 9 7 lists the condition code bit setting for each data type The MC68040 generates only eight of the 16 possible combinations Loading the FPCC with one of the other combinations and executing a conditional instruction can produce an unexpected branch condition 9 16 M68040 USER S MANUAL MOTOROLA Table 9 7 Floating Point Condition Code Encodings Daatye __ z rNomalzedorDemomalized o o NemalzedorDemomaized 1 o o inclusion of the data type in the IEEE floating point number system requires each conditional test to include the NAN condition code bit in its Boolean equation Because a comparison of a NAN w
467. scriptors for both 4 Kbyte and 8 Kbyte page sizes Refer to Section 4 Instruction and Data Caches for details concerning caching page descriptors 31 2 11 10 9 8 1 6 5 4 3 2 1 0 PHYSICAL ADDRESS 4 PAGE DESCIPTOR PAGE LEVEL 31 13 2 1 10 9 8 7 6 5 4 3 2 1 0 8K PAGE DESCRIPTOR PAGE LEVEL 3l 2 1 0 DESCRIPTOR ADDRESS PDT INDIRECT PAGE DESCRIPTOR PAGE LEVEL Figure 3 12 Page Descriptor Formats 3 2 2 3 DESCRIPTOR FIELD DEFINITIONS The field definitions for the table and page level descriptors are listed in alphabetical order CM Cache Mode This field selects the cache mode and accesses serialization as follows 00 Cachable Write through 01 Cachable Copyback 10 Noncachable Serialized 11 Noncachable Section 4 Instruction and Data Caches provides detailed information on caching modes and Section 7 Bus Operation provides information on serialization MOTOROLA M68040 USER S MANUAL 313 Descriptor Address This 30 bit field which contains the physical address of a page descriptor is only used in indirect descriptors G Global When this bit is set it indicates the entry is global PFLUSH instruction variants that specify nonglobal entries do not invalidate global entries even when all other selection criteria are satisfied If these PFLUSH variants are not used then system software can use this bit M Modified This bit i
468. see Memory Management Unit Registers Trap Exceptions 8 8 8 20 U UDT field 3 19 see also Descriptors Unimplemented Data Type 9 22 9 23 D 2 Exception 9 20 9 39 Unimplemented Floating Point Instruction 9 21 A 6 D 2 Exception 1 2 9 20 9 39 MOTOROLA M68040 USER S MANUAL Unimplemented Instruction Exceptions see Exceptions Unnormalized see Data Types Unordered Condition 9 25 User Address Space 3 23 Unsupported Data Types see Unimplemented Data Type User Programmable Attribute Bits 5 7 Vector Number 7 31 7 33 7 34 8 2 Offset 8 15 Table see Exception Vector Table W Word see Data Format Write Buffer see Buffers Write Bus Cycles see Bus Cycles Write Back Stage see Integer Unit Pipeline Write Backs 2 1 2 3 Block Diagram 2 3 External Write 2 3 Write Through see Caching Modes INDEX 7 INDEX 8 M68040 USER S MANUAL MOTOROLA
469. selects the cache mode and accesses serialization as follows 00 Cachable Write through 01 Cachable Copyback 10 Noncachable Serialized 11 Noncachable Section 4 Instruction and Data Caches provides detailed information on caching modes and Section 7 Bus Operation provides information on serialization FC2 Function Code Bit 2 Supervisor User This bit contains the function code corresponding to the logical address in this entry FC2 is set for supervisor mode accesses and cleared for user mode accesses G Global When set this bit indicates the entry is global Global entries are not invalidated by the PFLUSH instruction variants that specify nonglobal entries even when all other selection criteria are satisfied Logical Address This 13 bit field contains the most significant logical address bits for this entry All 16 bits of this field are used in the comparison of this entry to an incoming logical address when the page size is 4 Kbytes For 8 Kbytes pages the least significant bit of this field is ignored M Modified The modified bit is set when a valid write access to the logical address corresponding to the entry occurs If the M bit is clear and a write access to this logical address is attempted the M68040 suspends the access initiates a table search to set the M bit in the page descriptor and writes over the old ATC entry with the current page descriptor information The MMU then allows the original write acc
470. ses as if the access were never inhibited detecting no difference A cache line is always in one of three states invalid valid or dirty For invalid lines the V bit is clear causing the cache line to be ignored during lookups Valid lines have their V bit set and D bits cleared indicating all four long words in the line contain valid data consistent with memory Dirty cache lines have the V bit and one or more D bits set indicating that the line has valid long word entries that have not been written to memory long words whose D bit is set A cache line changes from valid to invalid if the execution of the CINV or CPUSH instruction explicitly invalidates the cache line if a snooped write access hits the cache line and the line is not dirty or if the SCx signals for a snooped read access invalidates the line Both caches should be explicitly cleared after a hardware reset of the processor since reset does not invalidate the cache lines Figure 4 3 illustrates the general flow of a caching operation The corresponding memory unit translates the logical address of each access to a physical address allowing the IU to access the data in the cache To minimize latency of the requested data the lower untranslated bits of the logical address map directly to the physical address bits and are used to access a set of cache lines in parallel with the translation Physical address bits 9 4 are used to index into the cache and select one of the 64 set
471. signaling NAN is transferred to the destination No bits other than the SNAN bit of the NAN data format are modified although the input NAN is truncated if necessary Instruction execution continues without taking any exceptions b If the user SNAN exception handler is enabled the processor posts an exception and another floating point instruction is eventually encountered a pre instruction exception is reported at that time The SNAN entry in the processor s vector table points to the M68040FPSP SNAN exception handler Once the M68040FPSP SNAN exception handler recognizes the operand error as a maskable condition it does not modify the destination or pass control to the user SNAN exception handler 9 7 2 2 NONMASKABLE EXCEPTION CONDITIONS When an SNAN is encountered if the destination is either in memory or an integer data register and the format is byte word or long word a nonmaskable post instruction exception occurs and is taken immediately The SNAN entry in the processor s vector table points to the M68040FPSP SNAN exception handler MOTOROLA M68040 USER S MANUAL 9 27 M68040FPSP SNAN exception handler checks to see if the instruction is an to byte word or long word If one of these conditions is met the M68040FPSP SNAN exception handler stores the most significant 8 16 or 32 bits respectively of the SNAN mantissa with the SNAN bit set to the destination Next it determines whether or not the user SNAN exc
472. sions 7 43 Address Error 7 6 7 43 8 8 Address Registers 1 8 2 4 Addressing Modes 1 10 2 5 10 3 10 4 Brief Extension Word Format 10 7 Full Extension Word Format 10 7 Index Scaling 1 9 1 10 Index Sizing 1 9 1 10 Memory Indirect 2 2 Postincrement 1 9 Predecrement 1 9 Program Counter Indirect 1 9 1 10 Program Counter Relative 7 6 Register Indirect 1 9 1 10 Address Translation 3 1 Address Translation Cache 1 4 3 2 3 3 3 4 3 7 3 26 5 8 5 14 8 7 8 18 Address Translation Cache Entry 3 15 3 30 4 2 Field Definitions 3 27 3 28 Airflow 11 29 11 31 Alternate Bus Master 4 1 4 8 4 9 5 4 5 5 5 8 5 9 Arithmetic Floating Point Exceptions see Floating Point Exceptions Automatic Test Pattern Generation ATPG 6 5 Autovector 7 33 7 34 Boundary Scan Control 6 6 6 9 Breakpoint Operations 8 12 Bus Cycle 7 29 7 35 9 20 BSDL Description 6 15 MOTOROLA Buffer Selection 7 69 Burst Mode Operations 4 3 4 11 5 9 Burst Bus Cycles see Bus Cycles Burst Inhibited Bus Cycles see Bus Cycles Bus Arbitration 7 44 7 58 Disregard Request Condition 7 50 Indeterminate Condition 7 49 7 58 Bus Arbitration States 7 46 7 49 Explicit Bus Ownership 7 45 Implicit Bus Ownership 7 67 with Direct Memory Access 7 56 Bus Controller 1 5 7 6 7 10 7 13 7 20 7 45 8 7 10 8 Bus Cycles Burst 5 9 7 9 7 10 7 12 7 13 7 22 7 37 7 88 7 42 7 70 Burst Inhibited 7 13 7 22 7 42 7 45 7 60 Li
473. sive memories with minimal impact to the overall system performance The potential for a low cost system design with the price performance of the MC68LC040 makes it a good choice for embedded microprocessor applications as well as central processor applications MC68L C040 is user object code compatible with previous members of the M68000 family and is specifically optimized to reduce the execution time of compiler generated code The high level of performance is ideal for integer intensive applications The MC68LCO040 is implemented in Motorola s latest HCMOS technology providing an ideal balance between speed power and physical device size Independent data and instruction MMUs control the main caches and the address translation caches 5 The 5 speed up logical to physical address translations by storing recently used translations The bus snooper circuit ensures cache coherency in multimaster and multiprocessing applications The MC68LC040 is pin compatible with the MC68040 and the MC68ECO040 Figure A 1 illustrates a simplified block diagram of the MC68LC040 MOTOROLA M68040 USER S MANUAL 1 INSTRUCTION DATA BUS INSTRUCTION INSTRUCTION INSTRUCTION INSTRUCTION 5 FETCH CONTROLLER INSTRUCTION MEMORY MANAGEMENT UNIT B DECODE U ADDRESS 5 BUS EFFECTIVE ADDRESS C CALCULATE 0 EFFECTIVE N DATA ADDRESS T aus FETCH R 0 EXECUTE L DATA MEMORY MANAGEMENT UNIT L DATA
474. ssociated with a reset when the processor is executing bus cycles Note that BB and TIP and TA if driven during a snooped access are negated before transitioning to a three state level C 8 M68040 USER S MANUAL MOTOROLA lt t gt 10 gt lt 2 gt lt 128 gt CLOCKS CLOCKS CLOCKS BCLK RSTI x IPL2 IPLO m 5 ao SIGNALS eee TS l l l l l l l l l l l l l l l l l l l l l l a Lo EE l l l l l l l l l l l l l l l l l l l l l E d l l l l l l l NOTE Not on MC68ECO40V Figure MC68040V and MC68ECO40V Normal Reset Timing Resetting the processor causes any bus cycle in progress to terminate as if TA or TEA had been asserted In addition the processor initializes registers appropriately for a reset exception When a RESET instruction is executed the processor drives the reset out RSTO signal for 512 BCLK cycles In this case the processor resets the external devices of the system and the internal registers of the processor are unaffected The external
475. ster rounded to the destination format precision and then written to memory Depending on the selected rounding mode or destination data format in effect the location of the least significant bit of the mantissa and the locations of the guard round and sticky bits in the 67 bit intermediate result mantissa varies The guard and round bits are always calculated exactly The sticky bit is used to create the illusion of an infinitely wide intermediate result As the arrow illustrates in Figure 9 7 the sticky bit is the logical OR of all the bits in the infinitely precise result to the right of the round bit During the calculation stage of an arithmetic operation any non zero bits generated that are to the right of the round bit set the sticky bit to one Because of the sticky bit the rounded intermediate result for all required IEEE arithmetic operations in the RN mode is in error by no more than one half unit in the last place 9 4 2 Rounding The Result Range control is the process of rounding the mantissa of the intermediate result to the specified precision and checking the 16 bit intermediate exponent to ensure that it is within the representable range of the selected rounding precision format Range control ensures correct emulation of a device that only supports single or double precision arithmetic If the intermediate results exponent exceeds the range of the selected precision the exponent value appropriate for an underflow or overflow
476. t offset width BFFFO bit offset of Source Bit Scan Dn BFFFO lt ea gt offset width Dn BFSET 1s abit field of Destination BFSET lt ea gt offset width BFTST bit field of Destination BKPT Run breakpoint acknowledge cycle BKPT lt data gt TRAP as illegal instruction PC 2 BRA lt label gt BSET bit number of Destination Z BSET Dn lt ea gt 1 bit number of Destination BSET lt data gt lt ea gt SP 4 SP PC SP BSR lt label gt BFINS Dn c bit field of Destination BFINS Dn lt ea gt offset width BFTST lt ea gt offset width 1 14 M68040 USER S MANUAL MOTOROLA Table 1 4 Instruction Set Summary Continued BTST bit number of Destination 7 BTST Dn lt ea gt BTST lt data gt lt ea gt CAS CAS Destination Compare 2 cc CAS Dc Du lt ea gt if Z Update Operand Destination else Destination Compare Operand CAS2 CAS Destination 1 Compare 1 z cc CAS2 Dc1 Dc2 Du1 Du2 Rn1 Rn2 if Z Destination 2 Compare if Z Update 1 Destination 1 Update 2 Destination 2 else Destination 1 Compare 1 Destination 2 2 Compare 2 C If Dn 0 or Dn Source lt ea gt Dn then TRAP CHK2 If Rn LB or If Rn UB CHK2 ea Rn then TRAP CINV If supervisor state CINVL caches An then invalidate selected cache lines CINVP caches An else TRAP CINVA caches C HK CMP2 Compare Rn LB or Rn U
477. t DR state Both the data capture and the shift operations are transparent to system operation The user must provide some form of external synchronization to achieve meaningful results since there is no internal synchronization between TCK and BCLK The second function of the SAMPLE PRELOAD instruction is to initialize the boundary scan register output cells before selecting EXTEST or CLAMP which is accomplished by ignoring data being shifted out of TDO while shifting in initialization data The update DR state can then be used to initialize the boundary scan register and ensure that known data and output state will occur on the outputs after entering the EXTEST or CLAMP instruction C 6 1 4 CLAMP The CLAMP instruction allows the state of the signals driven from the MC68040V 68 4 pins to be determined from the boundary scan register C 12 M68040 USER S MANUAL MOTOROLA while the bypass register is selected as the serial path between TDI signals driven from the MC68040V and MC68ECO40V pins do not change while the CLAMP instruction is selected C 6 1 5 BYPASS The BYPASS instruction selects the single bit bypass register creating a single bit shift register path from TDI to the bypass register to TDO The instruction enhances test efficiency when a component other than the MC68040V and MC68EC040V becomes the device under test When the bypass register is initially selected the instruction shift register
478. t HCMOS technology providing an ideal balance between speed power and physical device size 1 1 DIFFERENCES Because the functionality of individual M68040 family members are similar this manual is organized so that the reader will take the following differences into account while reading the rest of this manual Unless otherwise noted all references to M68040 with the exception of the differences outlined below will apply to the MC68040 MC68040V MC68LC040 68 040 and MC68bECO04A0V The following paragraphs describe the differences of MC68040V MC68LC040 MC68EC040 and the MC68ECO040V from the MC68040 1 1 1 MC68040V and MC68LC040 The MC68040V and MC68LC040 are derivatives of the MC68040 They implement the same IU and MMU as the MC68040 but have FPU The MC68LC040 is pin compatible with the MC68040 The MC68040V is not pin compatible with the MC68040 and contains some additional features The following differences exist between the MC68040V MC68LCO040 and MC68040 MOTOROLA M68040 USER S MANUAL 1 1 The DLE name has been changed to JS0 on both the 68040 and MC68LC040 In addition the MC68040V contains three new pins system clock disable SCD low frequency operation LFO and loss of clock LOC The MC68040V MC68L C040 do not implement the data latch enable DLE multiplexed or output buffer impedance selection modes of operation They implement only the small output buffer mode of operati
479. ta cache when the memory copy is stale ensuring that the alternate bus master receives valid data Writes by an alternate bus master can also be snooped to either update the M68040 internal data cache with the new data or invalidate the matching cache lines ensuring that subsequent M68040 reads access valid data These signals are ignored when the processor is the bus master 5 5 2 Memory Inhibit MI This output signal prevents an alternate bus master from accessing possibly stale data in memory while the M68040 is unable to respond is asserted during reset preventing external memory from responding When the 5 signals indicate an access should be snooped the M68040 keeps asserted until it determines if intervention in the access is required If no intervention is required MI is negated and memory is allowed to respond to complete the access Otherwise MI remains asserted and the M68040 completes the transfer as a slave It updates its caches on a write or supplies data to the alternate bus master on a read is negated when the M68040 is the bus master During a snoop MOTOROLA M68040 USER S MANUAL 5 9 cycle the 68040 ignores all TA and TEA assertions while is asserted when is asserted is asserted 5 6 ARBITRATION SIGNALS The following control signals support requests to an external arbiter to become the bus master Refer to Section 7 Bus Operation for detailed information
480. ta simultaneously through separate caches increases instruction throughput The M68040 caches improve system performance by providing cached data to the on chip execution unit with very low latency Systems with an alternate bus master receive increased bus availability Figure 4 1 illustrates the instruction and data caches contained in the instruction and data memory units The appropriate memory unit independently services instruction prefetch and data requests from the integer unit IU The memory units translate the logical address in parallel with indexing into the cache If the translated address matches one of the cache entries the access hits in the cache For a read operation the memory unit supplies the data to the IU and for a write operation the memory unit updates the cache If the access does not match one of the cache entries misses in the cache or a write access must be written through to memory the memory unit sends an external bus request to the bus controller The bus controller then reads or writes the required data Cache coherency in the M68040 is optimized for multimaster applications in which the M68040 is the caching master sharing memory with one or more noncaching masters such as DMA controllers The M68040 implements a bus snooper that maintains cache coherency by monitoring an alternate bus master s access and performing cache maintenance operations as requested by the alternate bus master Matching cache entries
481. tages with commonly used effective addressing modes Conditional branches are optimized for the 9 UNIX is a registered trademark of AT amp T Bell Laboratories MOTOROLA M68040 USER S MANUAL 1 3 more common case of the branch taken and both execution paths of the branch fetched and decoded to minimize refilling of the instruction pipeline INSTRUCTION DATA BUS INSTRUCTION INSTRUCTION ATC CACHE me INSTRUCTION MMU CACHE SNOOP CONTROLLER INSTRUCTION MEMORY UNIT INSTRUCTION ADDRESS INSTRUCTION FETCH CONVERT EA CALCULATE EXECUTE E FETCH EXECUTE DATA MEMORY UNIT DATA WRITE ma MMU CACHE SNOOP BACK Cn cc ADDRESS BUS rm O O G CONTROLLER FLOATING y 15 POINT UNIT DATA DATA cache ATC BUS CONTROL SIGNALS OPERAND DATA BUS Figure 1 1 Block Diagram To improve memory management the M68040 includes separate independent paged MMUS for instruction and data accesses Each MMU stores recently used address mappings in separate 64 entry address translation caches ATCs Each MMU also has two transparent translation registers that define a one to one mapping for address space segments ranging in size from 16 Mbytes to 4 Gbytes each Two memory units independently interface with the IU and FPU Each unit consists of an MMU an ATC a main cache and a snoop controller The MMUs perform
482. tail floating point exceptions and how the MC68040 and M68040FPSP handle them Table 9 9 lists the vector numbers related to floating point exceptions Table 9 9 Floating Point Exception Vectors Vector Vector Offset Number Hex Floating Point Unimplemented Instruction also used for F line instruction Floating Point Branch or Set on Unordered Condition Floating Point Inexact Result Floating Point Divide by Zero Floating Point Underflow Floating Point Operand Error Floating Point Overflow Floating Point SNAN Floating Point Unimplemented Data Type The following paragraphs detail nonarithmetic floating point exceptions 9 6 1 Unimplemented Floating Point Instructions F line instructions are instruction word patterns with bits 15 12 that have an F encoding causing F line exceptions These instructions are termed unimplemented floating point instructions and cause an unimplemented floating point exception The MC68040 recognizes some F line instructions such as the FMUL and CPUSH which do not cause F line exceptions There are some F line instructions that the MC68040 recognizes as valid MC68881 MC68882 floating point instruction patterns but as floating point instructions that the processor cannot complete in hardware Table 9 10 lists the floating point instructions that are unimplemented and therefore cause an unimplemented instruction exception If the processor encounters an F line instruction and the instruction patt
483. tandard 1149 1A Standard Test Access Port and Boundary Scan Architecture Problems associated with testing high density circuit boards have led to the standard s development under the sponsorship of the IEEE Test Technology Committee and the Joint Test Action Group JTAG This section is to be used in conjunction with the supporting IEEE document and includes those chip specific items that the IEEE standard requires to be defined and additional information specific to the M68040 implementation For example the IEEE standard 1149 1A test access port TAP controller states are referenced in this section but are not described For these details and application information regarding the standard refer to the IEEE standard 1149 1A document The M68040 implementation supports circuit board test strategies based on the standard The test logic utilizes static logic design and is system logic independent of the device The M68040 implementation provides capabilities to a Perform boundary scan operations to test circuit board electrical continuity b Bypass the M68040 by reducing the shift register path to a single cell c Sample the M68040 system pins during operation and transparently shift out the result d Disable the output drive to output only pins during circuit board testing and e Select one of two output drivers on a pin by pin basis NOTE The IEEE standard 1149 1A test logic cannot be considered completely benign to those plann
484. tation State Diagram and External Bus Arbiter Circuit MOTOROLA M68040 USER S MANUAL 7 47 7 6 M68040 Bus dus States Negated Negated s L three states BB arbiter negates BG bus is not driven M68040 three states BB arbiter asserts Negated ated Assented Implicit Negated P BG bus is driven with undefined values M68040 asserts BB arbiter asserts BG Asserted Negated Active Bus Cycle bus is driven with defined values TIP is asserted M68040 asserts BB arbiter asserts BG Asserted Asserted Park bus is driven with undefined values TIP is asserted Alternate Bus Master Ownership M68040 three states BB arbiter asserts Asserted Asserted Mesa asserted Assorted and Snooped BG M68040 does not drive the bus The M68040 can be in the active bus cycle park or implicit ownership states when BG is negated Depending on the state the processor is in when BG is negated uncertain conditions can occur The only guaranteed time that the processor relinquishes the bus is when BG is negated prior to the rising edge of BCLK in which the last TA or TEA is asserted and the processor is in the active bus cycle state However if the processor is in either the active bus cycle park or implicit ownership states and BG is negated at the same time or after the last TA or TEA is asserted then from the standpoint of the external bus arbiter the next action th
485. ted since the access is identified as noncachable Refer to Section 3 Memory Management Unit Except 68 040 and 68 040 for information on the M68040 and MC68LC040 memory units and Appendix 68 040 for information on the MC68EC040 memory unit The processor asserts transfer start TS during C1 to indicate the beginning of a bus cycle If not already asserted from a previous bus cycle the transfer in progress signal is also asserted at this time to indicate that a bus cycle is active Clock 2 C2 During the first half of the clock after C1 the processor negates TS The selected peripheral device uses R W 5121 5120 1 and AO to place its information on the data bus With the exception of the R W signal these signals also select any or all of the operand bytes 031 024 023 016 015 08 07 00 If the first clock after C1 is not a wait state CW then the selected peripheral device asserts the transfer acknowledge TA signal At the end of the first clock cycle after C1 the processor samples the level of TA and latches the current value on the data bus the bus cycle terminates and the data is passed to the processors appropriate memory unit if TA is asserted If TA is not recognized asserted at the end of the clock cycle the processor ignores the data and inserts a wait state instead of terminating the transfer The processor continues to sample TA on successive rising edges of BCLK until TA
486. ternal device More than one device having the capability to control the bus can be attached to the bus An external arbiter prioritizes requests and determines which device is granted access to the bus Bus arbitration is the protocol by which the processor or an external device becomes the bus master When the M68040 is the bus master it uses the bus to read instructions and data not contained in its internal caches from memory and to write data to memory When an alternate bus master owns the bus the M68040 is able to monitor the alternate bus master s transfer and intervene when necessary to maintain cache coherency This capability is discussed in more detail in 7 9 Bus Snooping Operation Unlike earlier members of the M68000 family the M68040 implements an arbitration method in which an external arbiter controls bus arbitration and the processor acts as a slave device requesting ownership of the bus from the arbiter Since the user defines the functionality of the external arbiter it can be configured to support any desired priority scheme For systems in which the processor is the only possible bus master the bus can 7 44 M68040 USER S MANUAL MOTOROLA be continuously granted to the processor and no arbiter is needed Systems that include several devices that can become bus masters require an arbiter to assign priorities to these devices so that when two or more devices simultaneously attempt to become the bus master the one having the hi
487. ternal state and activates an internal keep alive clock to protect the device from potential internal damage This internal clock eliminates the requirement to keep the system clocks PCLK and BCLK running during EXTEST operations and allows these two system clock pins to be included in boundary scan testing 6 2 2 HIGHZ The HIGHZ instruction is an optional instruction provided as a Motorola public instruction to anticipate the need to backdrive output pins during circuit board testing The HIGHZ instruction activates an internal keep alive clock asserts internal system reset selects the bypass register and forces all output and bidirectional pins to the high impedance state Asserting TRST or holding TMS high and clocking TCK for at least five rising edges causes the TAP controller to enter the test logic reset state Using only the TMS and TCK pins and the capture IR and update IR states invokes the HIGHZ instruction This scheme works because the value captured by the instruction shift register during the capture IR state is identical to the HIGHZ opcode 6 2 3 SAMPLE PRELOAD The SAMPLE PRELOAD instruction provides two separate functions First it provides a means to obtain a sample system data and control signal Sampling occurs on the rising edge of TCK in the capture DR state The user can observe the data by shifting it through the boundary scan register to output TDO using the shift DR state Both the data capture and the shift operat
488. ters for field identification For instance to transparently translate the user address space the S field is set to 0 and the logical address mask is set to FF in both an instruction and data TTR To transparently translate supervisor accesses of addresses 00000000 0FFFFFFF with write protection the logical base address field is set to 0x the logical address mask is set to 0F the W bit is set to one and the S field is set to 1 The inclusion of independent TTRs in both the instruction and data MMUs provides an exception to the merged instruction and data address space allowing different translations for instruction and operand accesses Also since the instruction memory unit is only used for instruction prefetches different instruction and data TTRs can cause PC relative operand fetches to be translated differently from instruction prefetches If either of the TTRs matched during an access to a memory unit either instruction or data the access is transparently translated If both registers match the TTO status bits are used for the access Transparent translation can also be implemented by the translation tables of the translation tables if the physical addresses of pages are set equal to their logical addresses 3 5 ADDRESS TRANSLATION SUMMARY The instruction and data MMUs process translations by first comparing the logical address and privilege mode with the parameters of the TTRs If there is a match the MMU uses the logical
489. the board environment This section discusses the device characteristics and several methods for thermal management as well as an example of one method for cooling the MC68040 MC68LC040 and 68 040 The MC68040 MC68LC040 and 68 040 contain inherent characteristics that should be considered when evaluating a method for cooling the device The following paragraphs discuss these die package and power considerations for each of these parts NOTE All references to the MC68040 also include the MC68LC040 and MC68EC040 Note that the MC68LC040 and MC68EC040 only implement the small buffer mode 11 8 1 MC68040 Die and Package The MC68040 is in a cavity down alumina ceramic 179 pin PGA that has a worst case thermal resistance from junction to case of 3 C W The package differs from previous M68000 family PGA packages that are cavity up The cavity down design allows the die to be attached to the top surface of the package increasing the part s ability to dissipate heat through the package surface or an attached heat sink The system designer needs to determine the specific dimensions and design of the particular heat sink considering both thermal performance and size requirements 11 8 2 MC68040 Power Considerations The MC68040 has a maximum power rating which varies depending on the combination of output buffer mode and operating frequency Note that this section assumes large buffers terminated to 2 5 V The large buffer output m
490. the execute stage handles any data registers required for the calculation which passes the register back to the lt ea gt calculate stage The resulting effective address is passed to the lt ea gt fetch stage which initiates an operand fetch from the data memory controller if the effective address is for a source operand The fetched operand is returned to the execute stage which completes execution of the instruction and writes any result to either a data register memory or back to the lt ea gt calculate stage for storage in an address register For a memory destination the lt ea gt fetch stage passes the address to the execution stage The previously described sequence of effective address calculation and fetch can occur multiple times for an instruction depending on the source and or destination addressing modes For memory indirect addressing modes the lt ea gt calculate stage initiates an operand fetch from the intermediate indirect memory address then calculates the final 2 2 M68040 USER S MANUAL MOTOROLA effective address Also some instructions access multiple memory operands and initiate fetches for each operand The instruction finishes execution in the execute stage Instructions with write back operands to memory generate pending write accesses that are passed to the write back stage The write occurs to the data memory unit if it is not busy If the following instruction which is in the ea fetch stage require
491. the external logic typically returns the transfer error acknowledge signal TEA In this case the M68040 automatically generates the spurious interrupt vector number 24 18 instead of the interrupt vector number If TA and TEA are both asserted the processor retries the cycle 7 34 M68040 USER S MANUAL MOTOROLA 7 5 2 Breakpoint Interrupt Acknowledge Bus Cycle The execution of a breakpoint instruction BKPT generates the breakpoint interrupt acknowledge bus cycle An acknowledged access is indicated with TT1 and TTO 3 address A31 A0 00000000 and TM2 TMO 0 When the external device terminates the cycle with either TA or TEA the processor takes an illegal instruction exception Figures 7 24 and 7 25 illustrate a flowchart and functional timing diagram for a breakpoint interrupt acknowledge transfer PROCESSOR EXTERNAL DEVICE BREAKPOINT ACKNOWLEDGE SET R W TO READ DRIVE A31 A0 TO 00000000 DRIVE UPA1 UPAO 0 SET SIZE TO BYTE SET TRANSFER TYPE ON TT1 TTO TO 3 SET TRANSFER MODIFIER TM2 TMO TO 50 NEGATE CIOUT ASSERT TS FOR ONE CLOCK ASSERT INITIATE ILLEGAL INSTRUCTION EXCEPTION PROCESSING Un gt C ASSERT OR TERMINATE CYCLE 1 NEGATE TA OR TEA Figure 7 24 Breakpoint Interrupt Acknowledge Bus Cycle Flowchart MOTOROLA M68040 USER S MANUAL 7 35 BCLK 1 0 UPA1 UPAO
492. the return from an exception and bus fault recovery This section also describes the formats of the exception stack frames For details on floating point exceptions refer to Section 9 Floating Point Unit MC68040 Only NOTE For the MC68040V MC68LC040 MC68ECO040 and 6 ignore all references to floating point including any instructions that begin with an Also for the MC68EC040 and MC68ECO040V ignore all references to the memory management unit MMU and the instructions PFLUSH and PTEST The functionality of the MC68040 transparent translation register has been changed in the MC68EC040 and MC68bECO40V to the access control registers ACR Refer to Appendix MC68LC040 and Appendix B MC68EC040 for details 8 1 EXCEPTION PROCESSING OVERVIEW Exception processing is the transition from the normal processing of a program to the processing required for any special internal or external condition that preempts normal processing External conditions that cause exceptions are interrupts from external devices bus errors and resets Internal conditions that cause exceptions are instructions address errors and tracing For example the TRAP TRAPcc FTRAPcc CHK RTE DIV and FDIV instructions can generate exceptions as part of their normal execution In addition illegal instructions unimplemented floating point instructions and data types and privilege violations cause exceptions Exception processing uses an exceptio
493. there is no idle clock MI is not asserted MI is asserted during and after reset until the first bus cycle of the M68040 Even though snoop is inhibited all TA or TEA assertions while MI is asserted are ignored If a line snoop is started the M68040 still requires four TA assertions 7 60 M68040 USER S MANUAL MOTOROLA BCLK 5 1 5 0 E X C 1 5121 5120 X T T dy T T N MI 1 1 1 1 1 1 1 1 1 1 1 Ex I 1 1 I 1 1 1 1 1 1 031 00 J I RVUD S t xF r t l l BB iy ACER Nu M l l PROCESSOR PROCESSOR gt AM indicates the alternate bus master Undefined Figure 7 40 Snoop Inhibited Bus Cycle 7 9 2 Snoop Enabled Cycle No Intervention Required For alternate bus master accesses in which SCx 1 or 2 indicating that snooping is enabled the M68040 continues to assert MI while checking for a matching cache line If intervention in the alternate bus master access is not required MI is then negated and memory is allowed to respond and complete the access Figure 7 41 illustrates
494. thermal study results for the MC68040 that did not use thermal management techniques airflow cooling heat sink and heat sink combined with airflow cooling The MC68040 power dissipation values given in this section represent the sum of the power dissipated by the internal circuitry and the output buffers of the MC68040 The termination network chosen by the system designer strongly influences this last component of power Values listed in this section for large buffer terminated entries reflect a termination network as illustrated in Figure 11 8 and are consistent with specifications for the MC68040 For additional termination schemes refer to AN1051 Transmission Line Effects in PCB Applications or AN1061 Reflecting on Transmission Line Effects 11 14 M68040 USER S MANUAL MOTOROLA MC68040 OUTPUT 50 Q TLL 50 TYPICAL 70 24 12 LARGE 25V TYPICAL 70 25 Q SMALL Figure 11 8 MC68040 Termination Network If a designer uses alternative standard termination methods such as RC termination network see Figure 11 9 Th venin termination network not illustrated or no termination method at all which is not recommended then the power dissipation of the MC68040 will be significantly less than the large buffer terminated values For termination networks other than that illustrated in Figure 11 31 the designer must calculate the component of power dissipated in the output buffer and add this value to the small bu
495. through but do not allocate in the cache for misses Read modify write table search accesses required to update some descriptor U bit and M bit combinations are treated as noncachable and force a matching cache line to be pushed and invalidated Table search bus accesses are locked only for the specific portions of the table search that requires a read modify write access During a table search the U bit in each encountered descriptor is checked and set if not already set Similarly when the table search is for a write access and the M bit of the page descriptor is clear the processor sets the bit if the table search does not encounter a set W bit or a supervisor violation Repeating the descriptor access as part of a read modify write access updates specific combinations of the U and M bits allowing the external arbiter to prevent the update operation from being interrupted The M68040 asserts the LOCK signal during certain portions of the table search to ensure proper maintenance of the U bit and M bit The U bit and M bit are updated before the M68040 allows a page to be accessed or written As descriptors are fetched the U bit and M bit are monitored Write cycles modify these bits when required For a table descriptor a write cycle that sets the U bit occurs only if the U bit was clear Table 3 1 lists the page descriptor update operations for each combination of U bit M bit write protected and read or write access type MOTOROLA M6804
496. tion 8 Exception Processing for information about the reset exception 5 7 3 Reset Out RSTO The M68040 asserts this output during execution of the RESET instruction to initialize external devices Refer to Section 7 Bus Operation for a description of reset out bus operation 5 8 INTERRUPT CONTROL SIGNALS The following signals control the interrupt functions 5 8 1 Interrupt Priority Level 1 2 These input signals provide an indication of an interrupt condition and the encoding of the interrupt level from a peripheral or external prioritizing circuitry IP L2is the most significant bit of the level number For example since the signals are active low IPL2 IPLO 5 corresponds to an interrupt request at interrupt priority level 2 During a processor reset the levels on the lines are latched and used to select the output driver characteristics for three signal groups listed in Table 5 5 Refer to Section 8 Exception Processing for information on interrupts and to Section 11 MC68040 Electrical and Thermal Characteristics for information on driver characteristics Refer to Appendix A MC68LC040 and Appendix MC68ECO040 for how these signals different on power up Table 5 5 Output Driver Control Groups Output Buffers Controlled Data Bus D31 DO IPL1 Address Bus and Transfer Attributes 1 0 CIOUT LOCK LOCKE R w 5171 5170 TLN1 TLNO 2 0
497. tion or data TTR the R bit is set and all other bits are zero R Resident The R bit is set if the PTEST address matches an instruction or data TTR or if the table search completes by obtaining a valid page descriptor 3 2 LOGICAL ADDRESS TRANSLATION The function of the MMUs is to translate logical addresses to physical addresses The MMUS perform translations according to control information in translation tables The operating system creates these translation tables and stores them in memory The processor then fetches a translation table as needed and stores it in an ATC 3 2 1 Translation Tables The M68040 uses the ATCs in the instruction and data memory units with translation tables stored in memory to perform the translations from logical to physical addresses The operating system loads the translation tables for a program into memory No distinction is made in the translation of instruction accesses versus data accesses because the instruction and data MMUs access the same translation table for a specific privilege mode either user or supervisor This lack of distinction results in a merged instruction and data address space Figure 3 7 illustrates the three level tree structure of a general translation table supported by the M68040 The root and pointer level tables contain the base addresses of the tables at the next level The page level tables contain either the physical address for the translation or a pointer to the memory
498. tor O to 2 in bit in bit in bit linkage bit vector 1 to 23 linkage vector 1 to 12 linkage bit vector 1 to 12 linkage vector 1 to 7 linkage vector linkage bit vector 1 to 6 linkage bit vector 1 to 3 linkage bit vector 1 to 2 use STD 1149 1 1990 all attribute PIN MAP of MC68040 entity is PHYSICAL PIN MAP 18x18 PGA Pin Map 1to2 wa constant 18x18 PIN MAP STRING 6 16 TDI TDO TMS TRST RSTO IPEND CIOUT UPA TT LOCKE LOCK R_W TLN TM SIZ TS BB TIP PST TA TEA BG SC TBI AVEC 53 2 55 54 T3 R3 61 R1 Q3 Q1 P3 P2 L18 K18 J17 J18 H18 G18 G16 F18 E18 F16 P1 1 1 L1 H1 G1 F1 G3 D1 F3 E2 C1 E3 B1 D3 A1 B3 C4 2 4 5 A6 B7 AT 8 9 A10 A11 A12 A13 B11 A14 B12 A15 A16 A17 B16 C15 A18 C16 B18 D16 C18 E16 E17 D18 R18 S18 N16 Q18 P18 N18 M18 K17 P17 P16 Q16 T18 R16 T17 R15 T15 S14 R14 T16 T14 S13 T13 T12 S12 S11 T11 M68040 USER S MANUAL Qo Qo RO Qo Qo Qo Qo Qo Qo Qo Qo Qo Qo Qo Qo Qo Qo Qo Qo Qo Qo Qo Lo Qo Qo Qo Qo Qo Qo Qo QO Qo Qo MOTOROLA TCI DLE T9 PCLK P9 BCLK R7 IPL T8 T7 T6 RSTI 57 CDIS
499. transfer burst inhibit TBI with TA for the first transfer of the line access The processor responds by terminating the line burst transfer and accessing the remainder of the line using three long word read bus cycles Although the selected device can then treat the line transfer as four independent long word bus cycles the bus controller still handles the four transfers as a single line transfer and does not allow other unrelated processor accesses or bus arbitration to intervene between the transfers TBI is ignored after the first long word transfer Line reads to support cache line filling can be cache inhibited by asserting transfer cache inhibit TCI with TA for the first long word transfer of the line The assertion of TCI does not affect completion of the line transfer but the bus controller latches and passes it to the memory controller for use TCI is ignored after the first long word transfer of a line burst transfer and during the three long word bus cycles for a burst inhibited line transfer The address placed on the address bus by the processor for line transfers does not necessarily point to the most significant byte of each long word because for a line read A1 and 0 are copied from the original operand address supplied to the memory unit by the integer unit These two bits are also unchanged for the three long word bus cycles for a burst inhibited line transfer The selected device should ignore A1 and 0 for long word and lin
500. truction same as gt STATUS REGISTER during interrupt exception on master stack 02 processing when transition PROGRAM COUNTER from master state to 06 0001 VECTOR OFFSET interrupt state occurs THROWAWAY FOUR WORD STACK FRAME FORMAT 1 MOTOROLA M68040 USER S MANUAL 8 21 ENTRY a TEMP 4 SP READ FORMAT WORD E INVALID FORMAT OTHERWISE WORD SR 4 TEMP SP 4SP 6 FORMAT CODE 51 THROWAWAY FRAME OTHERWISE TAKE FORMAT ERROR EXCEPTION FORMAT CODE 50 OTHERWISE 4 WORD FRAME OTHER FORMATS PC 4 SP SP 4 SP 6 SR 4 TEMP Figure 8 6 Flowchart of RTE Instruction for Throwaway Four Word Frame 8 4 3 Six Word Stack Frame Format 2 If six word throwaway stack frame is on the active stack and an instruction is encountered the processor restores the SR and PC values from the stack increments the active supervisor stack pointer by C and resumes normal instruction execution Stack Frames Exception Types Stacked PC Points To CHK CHK2 TRAPcc Next Instruction address is STATUS REGISTER FTRAPcc Trace the address of the or Zero Divide instruction that caused the PROGRAM COUNTER exception VECTOR OFFSET Unimplemented Floating Next Instruction address is Point Instruction the calculated lt ea gt for the floating point instruction Address Error Instruction that caused the SIX WORD STACK FRAME FORM
501. tructions that function as nonsynchronizing NOPs C1 C2 C3 C4 C5 C6 C7 ea LABEL INSTRUCTION CALCULATE EXECUTE P1 TRAPF 1 1 MOVE L 1000 D0 1 1 ADDQ L 1 D0 1 1 MOVE L D0 1000 1 1 N1 TRAPF 1 1 N2 TRAPF 1 1 3 G C6 ea CALCULATE Pl A B N1 N2 lt ea gt FETCH EXECUTE WRITE BACK C Figure 10 1 Simple Instruction Timing Example The previous instruction P1 finishes in the ea calculate A starts in the ea calculate and requests an immediate extension word for its effective address MOVE L A starts in the ea fetch which fetches the operand at 1000 ADDQ L B starts in the ea calculate stage with the operand encoded in the instruction MOVE L A executes in the execute stage storing the fetched operand in register DO ADDQ L B starts in the ea fetch with no operation performed MOVE L C starts in the ea calculate requesting an immediate extension word for its effective address B executes in the execution stage incrementing DO by 1 MOVE L passes through the ea fetch with no operation performed The next instruction starts in the ea calculate stage MOVE L C executes in the execution stage generating a write of DO to the effective address The write to memory by MOVE L C occurs to the data me
502. turn from the exception handler 8 2 5 Privilege Violation Exception To provide system security some instructions are privileged An attempt to execute one of the following privileged instructions while in the user mode causes a privilege violation exception ANDI to SR FSAVE MOVEC PTEST CINV MOVE from SR MOVES RESET CPUSH MOVE to SR ORI to SR RTE EORI to SR MOVE USP PFLUSH STOP FRESTORE Exception processing for privilege violations is similar to that for illegal instructions When the processor identifies a privilege violation it begins exception processing before MOTOROLA M68040 USER S MANUAL 8 9 executing the instruction As illustrated Figure 8 1 the processor copies the SR enters the supervisor mode and clears the trace bits The processor generates vector number 8 saves the privilege violation vector offset the current PC value and the internal copy of the SR on the supervisor stack The saved value of the PC is the logical address of the first word of the instruction that caused the privilege violation Instruction execution resumes after the required prefetches from the address in the privilege violation exception vector 8 2 6 Trace Exception To aid in program development the M68000 family includes an instruction by instruction tracing capability The M68040 can be programmed to trace all instructions or only instructions that change program flow In the trace mode an instruction generates a trace exception after
503. ty Affirmative Action Employer INC 1992 The complete documentation package for the 68040 MC68040V MC68LC040 68 040 and MC68ECO40V collectively called M68040 consists of the M68040UM AD M68040 User s Manual and the M68000PM AD M68000 Family Programmer s Reference Manual The M68040 User s Manual describes the capabilities operation and programming of the M68040 32 bit third generation microprocessors The M68000 Family Programmer s Reference Manual contains the complete instruction set for the M68000 family The introduction of this manual includes general information concerning the MC68040 and summarizes the differences between the M68040 member devices Additionally three appendices provide detailed information on how these M68040 dirivatives operate differently from the MC68040 For detailed information on one of these M68040 dirivatives use the following table to determine which appendices to read in conjunction with the rest of this manual Appendices MC68040V Appendix A MC68LC040 and Appendix C MC68040V and MC68ECO40V MC68LC040 Appendix A MC68LC040 MC68EC040 Appendix B MC68EC040 MC68EC040V Appendix MC68EC040 and Appendix C MC68040V and 68 040 When reading this manual remember to disregard information concerning floating point in reference to the MC68040V and MC68LC040 and to disregard information concerning floating point and memory management in referenc
504. udes a write protect W bit that can be set to provide write protection at any level Page descriptors also contain a supervisor only S bit that can limit access to programs operating at the supervisor privilege level The protection mechanisms can be used individually or in any combination to protect Supervisor address space from accesses by user programs User address space from accesses by other user programs Supervisor and user program spaces from write accesses implicitly supported by designating all memory pages used for program storage as write protected One or more pages of memory from write accesses 3 2 6 1 SUPERVISOR AND USER TRANSLATION TABLES One way of protecting supervisor and user address spaces from unauthorized accesses is to use separate supervisor and user translation tables Separate trees protect supervisor programs and data from accesses by user programs and user programs and data from access by supervisor programs Access is granted to the supervisor programs that can accesses any area of memory with MOVES The translation table pointed to by the SRP is selected for all other supervisor mode accesses This translation table can be common to all tasks Figure 3 17 illustrates separate translation tables for supervisor accesses and for two user tasks that share the common supervisor space Each user task has an translation table with unique mappings for the logical addresses in its user address space 3 2 6 2
505. umber Title Number 7 8 2 3 M68040 Synchronous DMA 7 55 7 8 2 4 M68040 Asynchronous DMA Arbitration 7 57 7 9 BUS eaa iiaae 7 59 7 91 Snoop Inhibited 7 60 7 9 2 Snoop Enabled Cycle No Intervention Required 7 61 7 9 8 Snoop Read Cycle Intervention Required 7 63 7 9 4 Snoop Write Cycle Intervention Required 7 63 7 10 Faser Operil T e nua un uu 7 65 7 11 Special Modes of 7 68 7 11 1 Output Buffer Impedance Selection 7 68 7 11 2 Multiplexed Bus 7 68 7 11 3 Data Latch Enable 7 69 Section 8 Exception Processing 8 1 Exception Processing 8 1 8 2 Integer Unit 5 Sit eM 8 5 8 2 1 Access Fault Exception uem reae 8 6 8 2 2 Address u uuu puq usaha 8 8 8 2 3 Instruction Trap 8 8 8 2 4 Illegal Instruction and Unimplemented Instruction Exceptions 8 9 8 2 5 Privilege Violation Exception
506. ume bus activity during C9 BCLK TRANSFER ATTRIBUTES N 4 SA i UD cms ALTERNATE gt lt Processor gt ALTERNATE MASTER MASTER AM indicates the alternate bus master Figure 7 32 Processor Bus Request Timing 7 50 M68040 USER S MANUAL MOTOROLA Figure 7 33 illustrates a functional timing diagram for an arbitration of relinquish and retry operation Figure 7 34 is a functional timing diagram for implicit ownership of the bus In Figure 7 33 the processor read access that begins in C1 is terminated at the end of C2 with a retry request and BG negated forcing the processor to relinquish the bus and allow the alternate master to access the bus Note that the processor reasserts BR during C3 since the original access is pending again After alternate bus master ownership the bus is granted to the processor to allow it to retry the access beginning in C7 C1 C2 C3 C4 C5 C6 C7 C8 BCLK TRANSFER x ATTRIBUTES RW by p sss ALTERNATE gt gt processon gt MASTER PROCESSOR AM indicates the alternate bus master Figure 7 33 Arbitration During Relinquish and Retry Timing MOTOROLA
507. unordered attribute is explicitly included in the conditional test the BSUN bit is not set in the FPSR EXC byte when the unordered condition occurs Table 9 8 summarizes the conditional mnemonics definitions equations predicates and whether the BSUN bit is set in the FPSR EXC byte for the 32 floating point conditional tests The equation column lists the combination of FPCC bits for each test in the form of an equation 9 18 M68040 USER S MANUAL MOTOROLA Table 9 8 Floating Point Conditional Tests mnemonic Detmiion Equation Predicate aa S IEEE Aware Tests Z O __2 meri es Miscellaneous Tests Simamora NOTE All condition codes with an overbar indicate cleared bits all other bits are set M68040 USER S MANUAL 9 19 9 6 FLOATING POINT EXCEPTIONS There are two classes of floating point related exceptions nonarithmetic floating point exceptions and arithmetic floating point exceptions The latter relates to the handling of arithmetic exceptions caused by floating point activity and the former includes unimplemented floating point instructions and unsupported data types not related to the handling of arithmetic exceptions Format error and FTRAPcc exceptions may seem to be floating point related but are considered IU exceptions see Section 8 Exception Processing The following sections de
508. update cache update cache go to valid state current state CPU Read Hit 2 Not Possible Supply data to CPU remain in current state Alternate Master Read Hit Not possible not snooped Not possible not snooped Snoop Control 01 Leave Dirty Alternate Master Read Hit 5 Not Possible No action go to invalid state Snoop Control 10 Invalidate Alternate Master Write Hit Not Possible 6 No action go to invalid state Snoop Control 01 Leave Dirty or Snoop Control 10 Invalidate 4 7 2 Data Cache The IU uses the data cache to store operand data as it generates the data The data cache supports a line based protocol allowing individual cache lines to be in one of three states invalid valid or dirty To maintain coherency with memory the data cache supports both write through and copyback modes specified by the CM field for the page Cache Invalidate or Push 3 No action remain in action go to invalid state CINV or CPUSH current state 1 V2 3 V4 V5 V Read misses and write misses to copyback pages cause the cache controller to read a new cache line from memory into the cache If available an invalid line in the selected set is updated with the tag and data from memory The line state then changes from invalid to valid by setting the V bit for the line If all lines in the set are already valid or dirty the pseudo random replacement algorithm is used to select one of the fou
509. upply a vector number it requests an automatically generated vector autovector Instead of placing a vector number the data bus and asserting the device asserts the autovector AVEC signal with TA to terminate the cycle AVEC is only sampled with TA asserted AVEC can be grounded if all interrupt requests are autovectored The vector number supplied in an autovector operation is derived from the interrupt priority level of the current interrupt When the AVEC signal is asserted with TA during an interrupt acknowledge bus cycle the M68040 ignores the state of the data bus and internally MOTOROLA M68040 USER S MANUAL 7 33 generates the vector number which is the sum of the interrupt priority level plus 24 18 There are seven distinct autovectors that can be used corresponding to the seven levels of interrupts available with IPL2 IPLO signals Figure 7 23 illustrates a functional timing diagram for an autovector operation BCLK 4 A31 A0 UPA1 1 1 1 1 1 1 1 5171 570 i TT TTO N 2 0 INTERRUPT LEVEL 1 ACKNOWLEDGE gt INTERRUPT lt e were stack AUTOVECTORED Figure 7 23 Autovector Interrupt Acknowledge Bus Cycle Timing 7 5 1 3 SPURIOUS INTERRUPT ACKNOWLEDGE BUS CYCLE When a device does not respond to an interrupt acknowledge bus cycle with TA or AVEC and TA
510. ure 2 5 stores the processor status In the supervisor mode software can access the full SR including the CCR available in user mode see 2 2 1 5 Condition Code Register and the interrupt priority mask and additional control bits available only in the supervisor mode These bits indicate the following states for the processor one of two trace modes T1 TO supervisor or user mode S and master or interrupt mode M The term SSP refers to the ISP and MSP The M and S bits of the SR decide which SSP to use When the S bit is one and the M bit is zero the ISP is the active stack pointer when the S bit is one and the M bit is one the MSP is the active stack pointer The ISP is the default mode after reset and corresponds to the MC68000 MC68008 MC68010 and CPU32 supervisor mode USER BYTE SYSTEM BYTE CONDITION CODE REGISTER 15 14 B 1 1 10 9 8 7 6 5 4 3 2 1 0 TRACE ENABLE INTERRUPT PRIORITY MASK CARRY OVERFLOW ZERO NEGATIVE EXTEND SUPERVISOR USER STATE MASTER INTERRUPT STATE Figure 2 5 Status Register 2 2 2 3 VECTOR BASE REGISTER The VBR contains the base address of the exception vector table in memory The displacement of an exception vector is added to the value in this register to access the vector table Refer to Section 8 Exception Processing for information on exception vectors 2 2 2 4 ALTERNATE FUNCTION CODE REGISTERS The alternate function code registers contain 3 bit funct
511. uring the second step the processor determines the vector number for the exception For interrupts the processor performs an interrupt acknowledge bus cycle to obtain the vector number For all other exceptions internal logic provides the vector number This vector number is used in the last step to calculate the address of the exception vector Throughout this section vector numbers are given in decimal notation 8 2 M68040 USER S MANUAL MOTOROLA ENTRY SAVE INTERNAL COPY OF SR FETCH VECTOR NUMBER OTHERWISE SAVE CONTENTS TO STACK FRAME SEE NOTE OTHERWISE EXECUTE EXCEPTION HANDLER 4 LONG WORDS OTHERWISE BEGIN INSTRUCTION EXECUTION EXIT BUS ERROR BUS ERROR OR ADDRESS ERROR BUS ERROR DOUBLE BUS FAULT DOUBLE BUS FAULT DOUBLE BUS FAULT HALTED STATE PST3 PSTO 5 EXIT NOTE These blocks vary for reset and interrupt exceptions Figure 8 1 General Exception Processing Flowchart M68040 USER S MANUAL The third step is to save the current processor contents for all exceptions other than reset The processor creates one of five exception stack frame formats on the active supervisor stack and fills it with information appropriate for the type of exception Other information can also be stacked depending on which exception is being processed and the state of the processor prior to the exception If the exception i
512. ut pin and indicates a bidirectional pin The last column lists the name of the associated control bit of the boundary scan register for three state output and bidirectional pins The boundary scan description language BSDL type for each cell can be found in note 1 MOTOROLA M68040 USER S MANUAL 6 9 Table 6 2 Boundary Scan Bit Definitions E Cell Type Name Output Note 3 Output Note 3 io io io oam A eo Pin TT TT A A10 0 0 1 1 1 102 O 1 02 1 102 102 VO 1 02 O 102 I Pin A16 I Pin A17 7 1 02 1 02 1 02 1 02 Poach O 1 02 O 0 0 1 A2 A2 A2 A2 A2 A2 A2 2 s E EM 20 EEN 22 23 24 25 27 28 29 9 32 35 7 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 6 3 6 10 M68040 USER S MANUAL Pin Cell Cell Type Name Pin Type Ctrl Cell vo Lim Poach A 10 Lim s Poach ws 102 Lim ws 10 vo Lim rer Poach ws 10
513. vector table the exception vector table can be located anywhere in memory it can even be dynamically relocated for each task that an operating system executes The M68040 supports a 1024 byte vector table containing 256 exception vectors see Table 8 1 Motorola defines the first 64 vectors and reserves the other 192 vectors for user defined interrupt vectors External devices can use vectors reserved for internal purposes at the discretion of the system designer External devices can also supply vector numbers for some exceptions External devices that cannot supply vector numbers use the autovector capability which allows the M68040 to automatically generate a vector number 8 4 M68040 USER S MANUAL MOTOROLA Table 8 1 Exception Vector Assignments Vector Vector Offset Number s Hex 0 000 Reset Initial Interrupt Stack Pointer 004 Reset Initial Program Counter Access Fault 00C Address Error Illegal Instruction Integer Divide by Zero CHK 2 Instruction FTRAPcc TRAPcc Instructions Privilege Violation Trace Line 1010 Emulator Unimplemented A Line Opcode Line 1111 Emulator Unimplemented F Line Opcode Unassigned Reserved Defined for MC68020 and MC68030 not used by M68040 Format Error 03C Uninitialized Interrupt 040 05 Unassigned Reserved 060 Spurious Interrupt 064 Level 1 Interrupt Autovector 068 Level 2 Interrupt Autovector 06C Level 3 Interrupt Autovector 070 Level 4 Inter
514. w Given the register dependency on the destination of the FADD instruction FPO needs to be resolved prior to FMOVE instruction execution For this example there is no choice but to have the FADD instruction report a post instruction exception immediately Note that for this case even though the T bit of the floating point state frame is set post instruction exception it does not imply an FMOVE OUT instruction Therefore the effective address field in the format 3 stack frame is invalid The FMOVE OUT instruction generates a post instruction exception For this case the effective address field in the format 3 stack frame points to the destination memory location If the destination is an integer data register the FPIAR points to the F line word 9 32 M68040 USER S MANUAL MOTOROLA of the offending instruction and the F line word contains the integer data register number If the M68040FPSP unimplemented instruction exception handler is used there can be some other cases in which an overflow is reported In addition to normal overflow the exponential instructions can generate results that catastrophically overflow the 16 bit exponent used for intermediate results For these instructions FETOX FTWOTOX FSINH and FCOSH the intermediate result found in either FPTEMP or WBTEMP fields of the floating point state frame are invalid If an INEX2 or INEX1 exceptional condition exists and the user INEX exception handler
515. write through mode for the shared pages maintains cache coherency for shared memory areas in a multiprocessing environment The cache supplies data to instruction or data read accesses that hit in the appropriate cache misses cause a new cache line to be loaded into the cache replacing a valid cache line if there are no invalid lines 4 3 1 2 COPYBACK MODE Copyback pages are typically used for local data structures or stacks to minimize external bus usage and reduce write access latency Write accesses to pages specified as copyback that hit in the data cache update the cache line and set the corresponding D bits without an external bus access The dirty cached data is only written to memory if 1 the line is replaced due to a miss 2 a cache inhibited access matches the line or 3 the CPUSH instruction explicitly pushes the line If a write access misses in the cache the memory unit reads the needed cache line from memory and updates the cache When a miss causes a dirty cache line to be selected for replacement the memory unit places the line in an internal copyback buffer The replacement line is read into the cache and writing the dirty cache line back to memory updates memory 4 6 M68040 USER S MANUAL MOTOROLA 4 3 2 Cache Inhibited Accesses Address space regions containing targets such as devices and shared data structures in multiprocessing systems can be designated cache inhibited If a page descriptors CM field indicates nonser
516. write accesses of any kind including supervisor writes An ATC descriptor corresponding to the logical address is created with the W bit set after the table search is completed when a table search encounters a W bit set in any table or page descriptor The subsequent retry of the write access results in an access error exception being taken The W bit can be used to protect the entire area of memory defined by a branch of the translation table or protect only one or more pages from write accesses Figure 3 18 illustrates a memory map of the logical address space organized to use supervisor only and write protect bits for protection Figure 3 19 illustrates an example translation table for this technique SUPERVISOR AND USER SPACE THIS AREA IS SUPERVISOR ONLY READ ONLY THIS AREA IS SUPERVISOR ONLY READ WRITE THIS AREA IS SUPERVISOR OR USER READ ONLY THIS AREA IS SUPERVISOR OR USER READ WRITE Figure 3 18 Logical Address Map with Shared Supervisor and User Address Spaces 3 24 M68040 USER S MANUAL MOTOROLA 5 SUPERVISOR ONLY READ ONLY THIS PAGE SUPERVISOR ONLY READ WRITE EE THIS PAGE SUPERVISOR USER NODE READ ONLY MODE URP URP amp SRP POINT TO SAME A LEVEL TABLE 5 SUPERVISOR USER READ WRITE ROOT LEVEL POINTER LEVEL PAGE LEVEL TABLE TABLE TABLE NOTE X Don tcare Figure 3 19 Translation
517. x page index PGI and page offset The first three fields extracted from the logical address index the base address for each table level The seven bits of the logical address RI field are multiplied by 4 or shifted to the left by two bits This sum is concatenated with the upper 23 bits of the appropriate root pointer URP or SRP to yield the physical address of a root level table descriptor Each of the 128 root level table descriptors corresponds to a 32 Mbyte block of memory and points to the base of a pointer level table 3 8 M68040 USER S MANUAL MOTOROLA 31 25 24 18 17 131211 0 8K PAGE 8K PAGE 4K PAGE 4 PAGE ROOT INDEX FIELD POINTER INDEX FIELD PAGE INDEX FIELD PAGE OFFSET Rl PI PGI Figure 3 8 Logical Address Format The seven bits of a logical address PI field are multiplied by 4 shifted to the left by two bits and concatenated with the fetched root level descriptor s upper 23 bits to produce the physical address of the pointer level table descriptor Each of the 128 pointer level table descriptors corresponds to a 256 Kbyte block of memory For 8 Kbyte pages the five bits of the field are multiplied by 4 shifted to the left by two bits and concatenated with the fetched pointer level descriptor s upper 25 bits to produce the physical address of the 8 Kbyte page descriptor The upper 19 bits of the page descriptor are the page frame s physical address There are 32 8 Kbyte page descriptors
518. x ABCD BCD Source BCD Destination X e Destination ABCD Dy Dx ABCD AD Source Destination 2 Destination ADD ea Dn ADD Dn lt ea gt D ADDA Source Destination Destination ADDA ea An ADDI Immediate Data Destination Destination ADDI lt data gt lt ea gt ADDQ Immediate Data Destination 2 Destination ADDQ lt data gt lt ea gt D ADDX Source Destination X e Destination ADDX Dy Dx ADDX Ay Ax AN Source A Destination Destination AND ea Dn AND Dn ea ANDI Immediate Data A Destination Destination ANDI lt data gt lt ea gt ANDI to CCR Source A CCR e CCR ANDI lt data gt CCR ANDI to SR If supervisor state ANDI lt data gt SR then Source A SR 2 SR else TRAP ASL ASR Destination Shifted by count 2 Destination ASd Dx Dy ASd lt data gt Dy ASd lt ea gt Bcc If condition true Bcc label then PC e PC BCHG bit number of Destination 7 BCHG Dn lt ea gt bit number of Destination 2 bit number of BCHG lt data gt lt ea gt Destination BCLR bit number of Destination Z BCLR Dn ea 0 bit number of Destination BCLR lt data gt lt ea gt BFCHG bit field of Destination bit field of Destination BFCHG lt ea gt offset width BFEXTS bit field of Source Dn BFEXTS lt ea gt offset width Dn BFEXTU bit offset of Source 2 Dn BFEXTU lt ea gt offset width Dn i BFCLR 0 bit field of Destination BFCLR lt ea g
519. x encoding There are two classes of PSTx encodings The first class is associated with instruction boundaries and the second class indicates the processors present status Table 5 6 lists the definition of the encodings The encodings 0 8 4 5 C D E and F indicate the present status and do not reflect a specific stage of the pipe These encodings persist as long as the processor stays in the indicated state The default encoding 0 user or 8 supervisor is indicated if none of the above conditions apply The encodings 1 2 3 9 A and B belong to the first class of PSTx encoding This class indicates that the instruction is in its last instruction execution stage These encodings exist for only one BCLK period per instruction and are mutually exclusive 5 12 M68040 USER S MANUAL MOTOROLA Table 5 6 Processor Status Encoding Hex ests Pert o o o o user starvGontinue Current instruction o o t User End Current instruction o o t User Branch Taken End Current Instruction o o 1 1 User Branch Taken End Current Instruction o 1 o user tableSearch ____ so Halted State Double Bus Fault asp ses Low Power Stop Mode Supervisor Instruction o 0 Supenisor StarContinue Current Instruction _ 1 Supenisor End Current Instruction _ 1
520. ximum rating and thermal characteristics for the MC68LC040 This section is subject to change For the most recent specifications contact a Motorola sales office or complete the registration card at the end of this manual MOTOROLA M68040 USER S MANUAL A 7 A 6 1 Maximum Ratings This device contains protective Characteristic Symbol circuitry against damage due to high Supply Voltage Vi Input Voltage V static voltages or electrical fields 0 3 to 7 0 however it is advised that normal precautions be taken to avoid 0 5 to 7 0 application of any voltages higher than maximum rated voltages to this high impedance circuit Reliablity of operation is enhanced if unused Minimum Operating Ambient Temperature inputs are tied to an appropriate logic voltage level e g either GND Storage Temperature Range or Vcc CC in 6 2 Thermal Characteristics Thermal Resistance Junction to Case 3 6 3 DC Electrical Specifications 5 0 Vdc 5 LT HEN Input Leakage Current 0 5 2 4 V AVEC BCLK BG CDIS MDIS IPLx PCLK RSTI SCx TBI TLNx TCI TEA Hi Z Off State Leakage Current 0 5 2 4 V An BB CIOUT Dn LOCK LOCKE R W SIZx TA TDO ITSI TIP TMx TLNx TS TTx UPAx Signal Low Input Current 0 8 V TMS TDI TRST Signal High Input Current 2 0 V 0 94 TMS TDI TRST N gt 0 18 2
521. ycle TIP remains asserted if the processor is ready to begin another bus cycle Otherwise the processor negates TIP during the first half of the next clock Figures 7 12 and 7 13 illustrate a flowchart and functional timing diagram for a burst inhibited line read bus cycle MOTOROLA M68040 USER S MANUAL 7 17 PROCESSOR EXTERNAL DEVICE ADDRESS DEVICE 1 SET R W TO READ 2 DRIVE ADDRESS ON 1 3 DRIVE USER PAGE ATTRIBUTES ON 1 UPAO 4 DRIVE SIZE ON SIZ1 SIZO LINE 5 DRIVE TRANSFER TYPE ON 1 TTO 6 DRIVE TRANSFER MODIFIER ON TM2 TMO 7 CIOUT BECOMES VALID 8 ASSERT TS FOR ONE CLOCK gt PRESENT DATA 1 DECODE ADDRESS 2 PLACE DATA ON D31 DO 3 ASSERT TA AND TBI ACQUIRE DATA lt 1 1 0 0 2 SAMPLE TBI AND TCI 3 RECOGNIZE TBI ASSERTED TERMINATE CYCLE 1 REMOVE DATA FROM D31 D0 2 NEGATE gt ADDRESS DEVICE 1 INCREMENT ADDRESS BITS A3 A2 AND DRIVE NEW ADDRESS ON A31 A0 2 DRIVE SIZE ON 5121 5120 LONG WORD 3 ASSERT TRANSFER START TS FOR ONE CLOCK gt PRESENT DATA 1 DECODE ADDRESS 2 PLACE DATA ON D31 D0 3 ASSERT TA ACQUIRE DATA lt 1 LATCH DATA UNTILTHREE LONG WORDS TRANSFERRED TERMINATE CYCLE WHEN THREE LONG WORDS TRANSFERRED 1 REMOVE DATA FROM D31 DO Y 2 NEGATE TA END OF LINE TRANSFER 1 NEGATE TIP IF
522. yte An exception handler can use this byte to determine which floating point exception s caused a trap 15 14 13 12 11 10 9 8 BSUN SNAN OPERR OVFL UNFL INEX2 INEX1 BRANCH SET ON UNORDERED SIGNALING NOT A NUMBER INEXACT DECIMAL INPUT INEXACT OPERATION OPERAND ERROR DIVIDE BY ZERO OVERFLOW UNDERFLOW Figure 9 5 FPSR Exception Status Byte 9 2 3 4 ACCRUED EXCEPTION AEXC BYTE The AEXC byte contains five exception bits see Figure 9 6 that the IEEE 754 standard requires for exception disabled operations These exceptions are logical combinations of the bits in the EXC byte The AEXC byte contains the history of all floating point exceptions that have occurred since the user last cleared the AEXC byte In normal operations only the user clears this byte by writing to the FPSR however a reset or a restore operation of the null state can also clear the AEXC byte MOTOROLA M68040 USER S MANUAL 9 5 Many users elect to disable traps for all or part of the floating point exception classes The byte makes it unnecessary to poll the EXC byte after each floating point instruction At the end of most operations FMOVEM and FMOVE excluded the bits in the EXC byte are logically combined to form an AEXC value that is logically ORed into the existing byte This operation creates sticky floating point exception bits in the AEXC byte that the user needs to poll only once i e at the end of a series o

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