MimoTEL User Manual - IPHC
Contents
1. 8 3 5 1 Normal mod data format aaa pvxcuhu em Ms pus f su Heb sssk sasawan was 8 3 5 1 1 Format of the analogue ouput Asgl 3 see 8 3 5 1 2 Format of the analogue ouput Asgl 2 eeeeseeeeeenen ee 9 3 5 1 3 Format of the analogue ouput Asgl l15 eene 9 3 5 1 4 Format of the analogue ouput Asgl lt 0 gt 9 3 5 2 T est rtmod data format REN 9 36 MimoTEL Chreo sram ie u ance Kaas Roi n Deu DAE DEIN iN ur d MEE 9 3 6 1 eglise PET T 9 3 6 1 1 Alternate Mxfirst signal for normal readout eese 11 3 6 2 jb auae m 11 4 Pad RNg E EAEAN 11 4 1 MimoTEL Pad Ring and Floor Plan View treten eben etes 12 LU EE GNE ce rU I3 October 2006 MimoTEL User Manual 2 MimolH 1 Introduction MimoTEL the third version of the MimoStar family has been designed in C35B401 the AMS 0 35 um opto process Like MimoStar 1 and 2 it is a Monolithic Active Pixel Sensor prototype dedicated to vertex particle tracking in the EUDET telescope The matrix is composed by 256 x 256 pixels of 30 um pitch and based on self biased diode architectures It is organised in 4 matrices or subframes of 256 lines x 64 columns accessed in parallel during the2. Internal Simulation Resol Range Experimental 1 DAC Code DacInterna Output ution Code Code Name Code current value pA IKIMO 64 100 100 1V 10 mV From 0 up to 2 55 V 0 0 I4PIX 1E 30 30 30uA 1 uA From 0 up to 255 uA 1 1 V4TESTI C3 195 195 1 95 V_ 10 mV From 0 up to 2 55 V FA 250 V4TESTO B9 185 185 1 85 V 10 mV From 0 up to 2 55 V E6 230 V4REG 3 23 35 35 2 95 V 10 mV From 3 3 down to 0 75 V 80 128 V4REG 2 23 35 35 2 95 V 10 mV From 3 3 down to 0 75 V 80 128 V4REG 1 23 35 35 2 95 V 10 mV From 3 3 down to 0 75 V 80 128 V4REG 0 23 35 35 2 95 V 10 mV From 3 3 down to 0 75 V 80 128 I4REGI 21 33 33 33uA lHuA From 0 up to 255 uA 1 1 I4AMP 64 100 100 100uA 1 pA From 0 up to 255 pA 3 3 ISLOWBUFSE 64 100 100 100 uA 1pA From 0 up to 255 pA A 10 Note 1 The HRES ploysilicon used in the bias block is missing for this submission Experimental values correspond to the recalculated parameters that allow nevertheless the chip be operated A new submission of the chip is in progress Bias synthetic block diagram m a T I4PIX V ISLOWBUFSE V4REG I4AMP nz0 1 2 3 for 4 sub matrices V4TEST1 V4TESTO October 2006 MimoTEL User Manual 7 MimolHL Notel Vrefn VAREGn 1V 3 3 Setting the Readout Mode Register If the desired operating mode does not correspond to the default one set the Readout_Mode0 register following
3. Sync d CkLvds Ck20Mout RstMk SSync MxFirst LastCol LastRow L Asgl 1 36 1 15 850m Il 6 40 v 1 88 I 1 9 u 5 7 u 7 pau I I 1 sfrow readout Init 9 58u 11 4u 13 3u 15 2u 17 1u time s I l l I I Reseti Jtag access Idle Successive row readouts iLast row readout Figure 1 RstBr TCK l l Syri 1 1 I t l side dw a L LP LB ILLE Lucil i l Ck28Mout RstMk L 1 um SSync L 1 1 MxFirst z i Lasttal LastRow 1 36 Asgl lt 3 gt Marker lt 0 gt Ts Px lt 255 254 gt Px lt 255 248 gt l E l uM CLE pM RE asa 1 88 Px lt 255 255 gt Px lt 255 253 gt Px lt 255 249 gt Px lt 255 247 gt Ma kefr lt 1 gt 85eim l 1 4 2 u 4 48u 4 68u Initialisation phase 1 1 1 4 B u B5 J88u 5 28u 5 4gu 15 row readout phase CkLvds d Ck28Mout RstMkz tEh root L
4. MimoTEL User Manual C Colledani W Dulinski H Himmi Ch Hu I Valin Institut de Recherches Subatomiques IN2P3 CNRS ULP Strasbourg France CENTRE NATIONAL N 2 4 3 BZ Css Ez SCIENTIFIQUE EU UNIVERSIT LOUIS PASTEUR 1J INsrrrur NATIONAL pe Paysique NUCt AIRE BR STRASBOURG ET DE PHYSIQUE DES PARTICULES MimolHL Document histor October 2006 Based on MimoStar2 Version October 2006 MimoTEL User Manual DRIER GT sse DEP Red ond ci m muU tM M MER Dc EM Ou EP D EHE 3 2 scs Interface ERU 4 2 1 JTAG Instruction E qa 4 2 2 VETE irpo MET 5 221 nstr ction Register e 5 2 2 2 Bypass ici B ER em Sea en era me satu us a aS 5 2 2 3 Boundary Scan Register A a X RS M NOM Pr tm M eq EN Id TUUM 5 2 2 4 ID CODE ROB Oi d 3 2 4 5 DOMUI Cd i nal M 5 2 2 6 DIS RSEN Lc P S 6 2 2 7 LONE eS corro c n 6 3 R nning MIBOLEL z dee E ehledot otn HR a a t cele 7 3 1 AFET TESE va darticy T 7 3 2 Biasine MiImoTEL auqa 7 3 3 Setting the Readout Mode Reglster a 8 34 cus Mort uu amupas un u as anasu P 8 3 4 1 Signal Protocol ee Tc 8 3 4 2 Successive frames and resynchronisation 8 3 5 Analogue Data Format
5. G No pad 3 amp 5 This DAC value is not very sensitive for test DAC with positive slope 0 to 255 uA 1 uA step 15 8 DACI I4AMP Bias of column amplifier DAC with positive No pad slope 0 to 255 uA 1 uA step 7 0 DACO ISLOWBUFSE Bias of the single ended Output Buffers DAC No pad with positive slope 0 to 255 uA 1 uA step October 2006 MimoTEL User Manual 6 MimolHL 3 Running MimoTEL The following steps describe how to operate the ASIC 3 1 After reset On RSTB active low signal All BIAS registers are set to the default value i e 0 DIS_COL is set to 0 i e all columns are selected RO Mode is set to 0 JTAG state machine is in the Test Logic Reset state JTAG ID_CODE instruction is selected Then the bias register has to be loaded The same has to be done for the RO MODEO and DIS COL registers if the running conditions differ from defaults Finally the readout can be performed either in normal mode or in test mode 3 2 Biasing MimoTEL The BIAS DAC register has to be loaded before operating the chip The 11 DACs constituting this register are built with the same 8 bits DAC current generator which has a 1 uA resolution Specific interfaces like current mirror for current sourcing or sinking and resistors for voltages customise each bias output The following table shows the downloaded codes which set the nominal bias
6. 05 BSR JTAG mandatory instruction ID CODE OE ID register JTAG optional instruction BIAS_GEN OF BIAS register User instruction DIS_COL 10 Disable Columns User instruction NUI 11 Reserved Not Used NU2 12 Reserved Not Used NU3 13 Reserved Not Used NU4 14 Reserved Not Used NUS 15 Reserved Not Used NU6 16 Reserved Not Used NU7 17 Reserved Not Used NU8 18 Reserved Not Used NU9 19 Reserved Not Used NU10 1A Reserved Not Used NU11 1B Reserved Not Used NU12 1C Reserved Not Used RO MODEI 1D Read Out Model User instruction RO MODEO 1E Read Out ModeO User instruction BYPASS 1F BYPASS JTAG mandatory instruction October 2006 MimoTEL User Manual MimolHL 2 2 JTAG Register Set JT AG registers are implemented with a Capture Shift register and an Update register JTAG standard imposes that the last significant bit of a register is downloaded shifted first Register Name Size Access Notes INSTRUCTION REG 5 R W Instruction Register BYPASS 1 R Only BSR 9 R W ID_CODE 32 R Only Fixed pattern BIAS_GEN 11 DACs 88 R W Previous value shifted out during write DIS_COL 256 R W Previous value shifted out during write RO MODEI 8 R W Previous value shifted out during write RO MODEO 8 R W Previous value shifted out during write NUI NU12 0 Not implemented For future use 2 2 1 Instruction Register The Instruction register is a part of the Test Access Port Controller define
7. 2006 MimoTEL User Manual 12 MimollHL 4 2 PadList G snd Core logic and periphery cells supply AGNDALLP Ground periphery amp core 8 gnd Core logic and periphery cells supply AGNDALLP Ground periphery amp core O gnd Corelogic and periphery cells supply AGNDALLP Ground periphery amp core 35 October 2006 MimoTEL User Manual 13 MimolEl Core logic and periphery cells supply AGNDALLP Ground periphery amp core Core logic and periphery cells supply AGNDALLP Ground periphery amp core Pad ring segment 3 P L Pad General Function PadType Function for the chip LVDS Pad Ground AGNDALLP Ground for LVDS Pad CKRN LVDS In Full Custom Readout Clock Signal CKRP LVDS In LVDS Pad Supply AVDDALLP 3 3V for LVDS Pad Pad ring segment 2 PD2 GO gnd Pad supplying the output buffers GND3OP Grond GND3RP GND3RP 66 gnd Core logic and periphery cells supply GND3RP Ground 68 vdda Analogue Pad Supply AVDDALLP 33V 00 69 vdda Analogue Pad Supply AVDDALLP 33V 00 October 2006 MimoTEL User Manual 14
8. left hand side while column 0 is on the right hand side The organisation of the chip in 4 subframes of 64 columns has no matter to do with the DIS_COL register 255 Msb 0 Lsb DisCol lt 255 gt DisCol lt 0 gt 2 2 7 BIAS DAC Register The BIAS_DAC register is 88 bits large it sets simultaneously the 11 DAC registers As show bellow these 8 bit DACs set voltage and current biases After reset the register is set to 0 a value which fixes the minimum power consumption of the circuit The current values of the DACs are read while the new values are downloaded during the access to the register The image of the value of some critical biases can be measured on corresponding test pads Bit DAC DAC Internal DAC purpose Corresponding range Name Test Pad 87 80 DACIO IKIMO External circuit monitoring IKIMO 79 72 DACO HPIX Pixel source follower bias DAC with positive IPIX slope 0 to 255 uA 1 uA step 71 64 DAC8 V4TESTI Test Level emulates a pixel output DAC with No pad positive slope 0 to 2 55V 10 mV step 63 56 DAC7 V4TESTO Idem No pad 55 48 DAC6 V4REG3 Regulator voltage bias for the column amplifier VREGAMP Gain 3 amp 5 DAC with negative slope 3 3 to 0 75 V by step of 10 mV 47 40 DAC5 VAREG2 Idem No pad 39 32 DAC4 V4REGI Idem No pad 31 24 DAC3 V4REGO Idem No pad 23 16 DAC2 I4REGAMP Regulator current bias for column amplifier
9. output of the chip ID CODE register value is OXFFFF8001 2 2 5 RO Mode RegisterO The RO Mode registers are 8 bits large they allow the user to select specific features of the chip MimoTEL use only the RO Mode Register0 October 2006 MimoTEL User Manual 5 MimolHL Bit Bit Name Purpose Default value 7 Not Used 6 Not Used 5 DisLVDS Disable LVDS readout clock is not active 0 LVDS selected anymore 4 SelMux On MxFirst output pad select the MuxFirst 1 MuxFirst Signal active signal or the First Pixel of the Frame signal See 3 4 Readout 3 EnaGain3 Select gain 3 for the serial differential output O Gain 5 buffer 2 Not used 1 Not Used 0 EnaTstCol Test Mode Select the 2 Test Levels IVTESTI 0 Normal mode and IVTESTO which emulate a pixel output 2 2 6 DIS COL Register The DIS_COL register is 256 bit wide The purpose of this register is to disable the column current sources if a short circuit is suspected on a specific column During the readout even if a current source is disabled the corresponding column is selected i e no columns are skipped Obviously the signal of the corresponding pixel has no signification The default value of the DIS_COL register is 0 it means that all current sources can be activated by the readout logic Setting a bit to 1 disables the corresponding current source The column lt 256 gt is on the
10. 5 190 gt Px lt 255 128 gt Mk1 MkO Px lt 254 191 gt Px lt 254 190 gt Px lt 254 128 gt Mei MEO Ps 945 EX ols 2 o op P lt 1 126 gt Miki MeO Px lt 90 1905 Px 0 191s o op P lt 0 126 gt 3 5 1 3 Format of the analogue ouput Asgl lt 1 gt kl MkO Px lt 255 127 gt Px lt 255 126 gt gt ay Px 255 64 gt Mk1 MkO Px lt 254 127 gt Px lt 254 126 gt Px 254 64 gt Mk1 MkO Px 1 127 gt Px lt 1 126 gt Px 1 64 gt Mk1 MkO Px 0 127 gt Px lt 0 126 gt PX lt 0 64 gt 3 5 1 4 Format of the analogue ouput Asgl lt 0 gt Miki MEO IEsec255 635 Pxe lt 255 62255 o og ESS2595 0 Miki Me Px lt 254 3 9x 254 622 5 o op Pe lt 254 OF ed MIKO E 1 3 5Pe lt id 6255 4 of Exe do OF Miki MRO P lt O 635 Pk lt OW 625 56 s of PSS OF WF 3 5 2 Test mode data format During the test mode the pixel matrix is not anymore connected to the multiplexing electronic In place of it two test levels VATESTI V1 VATESTO VO are available They emulate two pixel level outputs Actually these levels correspond to those of Marker 1 and Marker 0 They are adjustable via 2 DACs Even and odd columns are alternatively connected to one of them This pattern allows seeing the output signal changing and emulates the readout shift from one column of pixel to the other column of pixel Thus the 4 parallel outputs generate respectively the following stream forma
11. an in the normal mode But it has to be noticed than the LastCol and LastRow makers are unavailable because the test mode has nothing to deal with the matrix and its line and column addressing registers For the same reason the MxFirst maker is unavailable in the First Pixel of frame mode but only continuous mode Sync u u r r u u CkLvds FUL UU LFU LFU UT ck2 Mout J UW UU UU UT TT RstMk SSync Write III LastCol s LastRow RESI a Asgl lt 2 gt 24 0 Asgl lt 0 gt v i WA Anne Asgl lt 1 gt 2 9 x Asgl lt 3 gt od Py WO 4 u 5 u time s 6 u 7 8 4 Pad Ring The pad ring of the chip is build with e Pads full custom designed for some of the analogue signals and power supplies e Pads from the AMS library for the digital signals and power supplies The pad ring is split in 6 functional independent parts Each part has its own supply pads October 2006 MimoTEL User Manual 11 MimolH 4 1 MimoTEL Pad Ring and Floor Plan View Dau npn i L ae aa le aaah Gill 1 PAM P D1 P_A2 PL P D2 P A3 75 Foundry submission information MimoTEL has been designed in AMS C35B401 CMOS 0 35 um The Process Design Kit V3 70 has been provided by CMP CAD tools are CADENCE DFII 5 0 with DIVA and ASSURA rules October
12. by the LVDS readout input clock CKRD It happens at the first rising edge of the 20MHz clock which follows the SYNC falling edge After a latency of 4 input clock cycles the analogue signals appear on the output buffers Digital maker outputs are available for the control of the readout process Pixels are sequentially read out in a specific order explained later in the document e Successive pixel frames are read until the readout clock is stopped A frame resynchronisation can be performed at any time by setting up the SYNC token again 2 Control Interface The control interface complies with the Boundary Scan JTAG IEEE 1149 1 Rev 1999 standard It allows the access to the internal registers of the chip like the bias register and the readout mode selection register On Power On Reset an internal reset for the control interface is generated The finite state machine of the Test Access Port TAP of the controller enters in the Test Logic Reset state and the ID register is selected 2 4 JTAG Instruction Set The Instruction Register of the JTAG controller is loaded with the code of the desired operation to perform or with the code of the desired data register to access Instruction 5 Bit Codes Selected Register Notes EXTEST 01 BSR JTAG mandatory instruction HIGHZ 02 BYPASS JTAG optional instruction INTEST 03 BSR JTAG optional instruction CLAMP 04 BYPASS JTAG optional instruction SAMPLE PRELOAD
13. d by the IEEE 1149 1 standard The Instruction register is 5 bits long On reset it is set with the ID CODE instruction When it is read the 2 last significant bits are set with the markers specified by the standard the remaining bits contain the current instruction X X X 1 0 2 2 2 Bypass Register The Bypass register consists of a single bit scan register It is selected when its code is loaded in the Instruction register during some actions on the BSR and when the Instruction register contains an undefined instruction 2 2 8 Boundary Scan Register The Boundary Scan Register according with the JTAG instructions tests and set the IO pads The BSR is 9 bits long and allows the test of the following input and output pads Bit Corresponding Pad Type Signal Notes 8 LVDS CkRdP CkRdN Input CkRd Resulting CMOS signal after LVDS Receiver 7 ASync Input Sync 6 SSync Output SSync 5 Ck5M Output Ck5M Internal only Not used 4 Ck20M Output Ck20M 3 RstMk Output RstMk 2 LastRow Output LastRow 1 LastCol Output LastCol 0 MxFirst Output MxFirst 2 2 4 ID CODE Register The Device Identification register is implemented is this third version It is 32 bits long and has fixed value hardwired into the chip When selected by the ID CODE instruction or after the fixed value is shifted via TDO the JTAG serial
14. ormed at any time by setting up the SYNC token again 3 5 Analogue Data Format Two types of signal can be generated e Normal pixel signal e Test signal 3 5 4 Normal mode data format In order to improve the readout speed MimoTEL is organized 4 subframes Each subframe has its own analogue serial output a single ended voltage output buffer running up to 20 MHz During the readout the 4 subframes are accessed in parallel For each subframe the addressing is done row by row each pixel is accessed sequentially from the left side to right side Each row contains 2 makers acting as dummy pixels and 64 active pixels One can use the adjustable level of the 2 makers as a pattern recogniser If the pixel coordinate format is specified as Px Line Column then for each subframe the upper left pixel is Px 255 63 gt while the lower right is Px 0 0 and the makers of each beginning row are named Mk1 and MKO Thus the 4 parallel outputs generate respectively the following stream formats 3 5 1 1 Format of the analogue ouput Asgl lt 3 gt Mk1 MkO Px lt 255 255 gt Px lt 255 254 gt Px lt 255 192 gt Mk1 MkO Px lt 254 255 gt Px lt 254 254 gt Px 254 192 Mk1 MkO Px 1 255 gt Px lt 1 254 gt Px 1 192 Mk1 MkO Px 0 255 gt Px lt 0 254 gt Px 0 192 October 2006 MimoTEL User Manual 8 MimolHL 3 5 1 2 Format of the analogue ouput Asgl lt 2 gt Mk1 MkO Px lt 255 191 gt Px lt 25
15. readout The individual pixel architecture should meet the radiation tolerance and the low leakage current requirements The addressing of each subframe is sequential and starts from the upper left pixel up to the lower right pixel The beginning of each subframe row is stamped by 2 dummy pixels acting as makers and having programmable levels Each subframe has its own analogue serial output a single ended voltage output buffer running up to 20 MHz which gives a readout time of 850us frame Digital Analog Supplies Supplies gnd vdd Vdd diode vdda gnd Bias Tests VREGAMP IPIX IKIMO ITEST Power Supplies OZROY m a2Z20 xor CMOS Signals apzo ct Ooz Szoo28 LVDS Signals a FF o Cr E rtoOWN o E E 55 POLES P Analogue Signals 2 2 Si lt lt MimoTEL functional view Does not correspond to the floorplan neither for the core neither for the pad ring October 2006 MimoTEL User Manual 3 MimolHL MimoTEL is very simple to operate e Power On Reset or Reset on the RSTB pad e Setup of the chip It is performed with programmable registers accessed via an embedded slow control interface It consists to e Load the DACs which bias the analogue blocks e If necessary load the ReadOut Register with a specific configuration The default setup on power on reset allows a normal readout once the biases have been set e Readout of the chip e The readout starts when the input SYNC token has its falling signal sampled
16. the 2 2 5 information 3 4 Readout 3 4 4 Signal protocol Ones JTAG registers have been loaded the readout of MimoTEL may initiate with the following signal protocol e The readout clock CKRD is started This allows the output pad CK20M to generate a 20 MHz clock This clock follows the input e The SYNC signal is set e The readout starts at the first rising edge of CKRD after SYNC signal disappears e Signal markers allow the monitoring of the readout and the analogue data sampling o RstMk maker confirms that the internal reset of the readout logic is done o SSync marker shows that the readout starts o 4 extra CKRD clock cycles after SYNC sampling are necessary before the analogue signal of the first pixel appears on the output pad o The MxFirst digital signal helps for a better sampling of the analogue output signals The way it acts is set by the RO Mode 4 bit A RO Mode 4 0 MxFirst is active during the duration of the first maker of the frame RO Mode 4 1 MxFirst is active on each pixel change on the analogue output i e it is a 20 MHz periodic signal o LastCol is active when the last column of the current row is selected o LastRow is active when the last row of the frame is selected o Ck20M output shows the internal clock running as long as input clock is running 3 4 2 Successive frames and resynchronisation Successive pixel frames are read until the readout clock is stopped A frame resynchronisation can be perf
17. ts Subframe 3 analogue ouput Asgl lt 3 gt V1 VO VO V1 V1 VO VO V1 Subframe 2 analogue ouput Asgl lt 2 gt VO V1 V1 VO VO V1 V1 VO Subframe 1 analogue ouput Asgl lt 1 gt V1 VO VO V1 Vi VO VO V1 Subframe 0 analogue ouput Asgl lt 0 gt VO V1 V1 VO VO V1 V1 VO 3 6 MimoTEL Chronogram The following chronograms describe typical access to the chip Reset JTAG download sequence and then the readout This one starts with the initialisation phase followed by the successive row readouts as showed in the zoom 3 6 1 Normal Readout Figure 1 show the beginning of a typical normal data readout mode After Reset and JTAG settings one can see the initialisation phase of the readout of the first pixel row The LastCol signal is active meanwhile the last pixel of a row is read The last row of the frame makes the LastRow signal to be active One of the 4 parallel analogue outputs is showed One can distinguish the 2 makers placed at the beginning of each row Figure 2 is the zoom of the readout of the first row Figure 3 is an enlargement of the transition from one row to the successive one Figure 4 show the alternate option of the MxFirst signal It is active only during the time the first maker appears i e just before the first pixel of the frame This option is set via the RoMode register October 2006 MimoTEL User Manual 9 MimolH RstB ij TCK L dM dae a a a n a na e a liri r ili rrr beris
18. u Lodi ru LU LU roo EU ith root LU Lo 1 Li SSync z EE MxFirst z vir y Li rood LLAI q ru n UL 1 t Li i Ed root r n ETE 1 LastCol L 1 L L L LastRow t icu ica 1 n Marker lt 0 gt 115 Px lt 255 191 gt Px lt 255 254 gt I l I 138 Asgl lt 3 gt I I I gt x f X f a E OT Px lt 255 192 gt Px lt 255 190 t Px 254 255 Px 255 253 TARA S m 1 Pe L i ka a L 2 7 r 1 00 Marker lt 1 gt 858m 1 1 l 1 L eal 7 Ou 7 2u 7 4u 7 6u 7 8u 8 u 8 2u I End of 1 st row readout 2 row readout Figure 3 October 2006 MimoTEL User Manual 10 MimolH 3 6 1 4 Alternate Mxfirst signal for normal readout Sync CkLvds Ck20Mout RstMk SSync i I 1 MxFirst 1 LastCol HHHH fl I LastRow EH ll l Winnnnnnnnnnnnnnnngu nn um nnm RISE ane ngnnnnnnnnnnnnnnnnnnngrn nn rn UNUU e it L l l h 1 n Ou 7 2Bu 19 8u 13 0u 16 u 19 time s Figure 4 3 6 2 Test mode readout The initialisation phase if the test mode is the same th
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