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SERVICE MANUAL - Matthieu Benoit

1. 166 Table 11 3 Input Instructions 2n x SE Fx bet eee E be 166 Table 11 4 Output Instructions 166 XI Table 11 5 Table 11 6 Table 12 1 Table 12 2 Table 12 3 Table 12 4 Table 12 5 Table 12 6 Table 13 1 Table 13 2 Table 13 3 Table 13 4 Table 13 5 Table 13 6 Parallel Port Registers Bits 7 4 E TR She dae 167 Parallel Port Registers Bits 3 0 I ete AU S RO Rate Reel ene oto 167 Status Register Bit Definition lt i esis eee Ped A TRAE SIUE 170 Input Port Bit Assignments oos ie erem 172 Output Port Bit Assipnmenls i254 3x hM YE SERT RA 172 Controller Commands 1 54 ove REV qp ob ges 173 Data Stream Bits etu ves epa tre sea paced 175 Format of Status Request Bytes E oC ped 181 Typical Filter Values for the Various Data Rates Assuming 6 Capture Range 196 Data Rates MFM Versus VCO Divide By Factor 196 Address Memory Map for DP8473 isi ao shea EE e euer cd LA e I m og 199 Truth Table for Drive Control Register is Gnd ee ene 200 Data Rate and Precompensation Programming Values 202 Maximum Time Allowed to Service an Interrupt or Acknowledge a Request in Execution P
2. 158 Table 10 10 Fixed Disk Type Byte 12H bah 084 be bab eves sede es 159 Table 10 11 Equipment Byte 14H 159 Table 10 12 Low and High Base Memory Bytes 15H and 16H 160 Table 10 13 Low and High Memory Expansion Bytes 17H and 18H 160 Table 10 14 Drive C Extended Byte 19H 160 Table 10 15 Drive D Extended Byte 161 Table 10 16 Feature Installed Byte 5 ecce sss 161 Table 10 17 CMOS RAM Checksum 2EH 2FH 161 Table 10 18 48 Parameters 20 27 162 Table 10 19 Shadow and Enter Setup 28H 162 Table 10 20 Low and High Extended Memory Bytes 30H and 163 Table 10 21 Date Century Byte 32H eee VA RR 163 Table 10 22 Setup Information 33H 163 Table 10 232 CPU Speed MH aes RII TC 164 Table 10 24 type 49 Parameters 35H 3CH 164 Table 11 1 Selection of Addresses and Interrupt Levels 165 Table 11 2 Port Address and Interrupt Levels
3. 109 INDEX08h I O Access Configuration 110 Identification Register 110 Optional Configuration 1 gale dosage 111 Optional Configuration 2 112 Optional Configuration 3 i e ue rab e ERR Rex UE RS 113 INDEXO9h Interrupt Acknowledge Configuration 114 IX Figure 8 17 INDEX10h DRAM Configuration 115 Figure 8 18 SINDEN IO kaa ayo es eC ASE 116 Figure 8 19 INDEX40h Clock Dividers Non TURBO Mode 116 Figure 8 20 INDEX41h Clock Dividers TURBO Mode 117 Figure 8 21 INDEX42h DMA and REFRESH Wait States 118 Figure 8 22 INDEX43h Serial Paralle and Mapper Select 119 Figure 8 23 INDEX43h Extended DMA 16 bit Page Mapping 120 Figure 8 24 INDEX45h EEPROM Control 121 Figure 8 25 INDEX47h Revision Identification 121 Figure 8 26 INDEX48h Mode Reconfigure m ERR e y ERA 122 Figure 8 27 Port 92 FAST_ RC and ALT PA20 Timing 123 Figure 8 28 FAST and ALT MUXPA20 Connections 124 Figure 8 29 INDEX49h Additional REFRESH Wait States 125 Figure 8 30 INDEX Port 92
4. NANE x 29 onnaa ShLAGHNAAPAANRAS SHIA RES Figure 7 2 HT133 Bus Bridge Interface Pinouts 91 GC133 Bus Bridge Interface 74 HT133 BUS BRIDGE INTERFACE PIN DESCRIPTIONS This section describes the pins of the HT133 Bus Bridge Interface The pin identification numbers correspond with those shown in Figure 7 2 Pinous HT133 Bus Bridge Interface Pin Pin Pin Description Symbol Number ADDRSEL 71 I Address Multiplexer Selector When LOW the HT133 places ROW addresses on the MA lines when HIGH the COLUMN addresses are on the MA lines to 147 to Backplane Address lines A latched version of the 19 148 PA2 to PA16 lines 95 to 100 amp 103 to 114 ATDO to 129 to vO AT Backplane Data lines 16 bit data lines derived from ATD15 139 amp the 32 bit processor data bus LD0 31 These lines drive 142 to the AT slots 146 BALE 121 I Bus Address Latch Enable When HIGH the addresses from the processor side PAs are driven through to the AT side ATAs The trailing edge of BALE holds the current value of the address on the AT side allowing the processor addresses to change for pipeline operation BBDIRO 116 I Bus Bridge Direction 0 Controls the direction of data for BBDIR1 117 the bridging action between 7 and ATD8 15 When HIGH data is bridged from lower to higher bytes on the AT side when
5. CHSNAEEYVOVPNVOARPO Ora DE DEQNZO AVON ARAOODIID 559 TIE gt 5 lt STE o ERNE E lt gt O Pr z z E Figure 5 2 HT131 Peripheral Controller Pinouts 432 80 79 78 77 76 75 74 73 72 71 70 68 67 66 65 64 63 62 61 60 59 58 56 55 53 52 51 50 49 48 47 46 45 44 43 42 41 VDD ATAO DACK7 IDACK6 IDACK5 IDACK3 IDACK2 IDACK1 IDACK0 DRQ7 DRQ6 DROS DRO3 DRQ2 DRO1 DRQ0 CPUHRQ TC VSS VSS VSS VDD REFRESH LBHE AEN2 AEN1 MASTER HLDA IOCHRDY IMEGATST TESTC TESTB RTCIRQ INT ATD7 ATD6 ATD5 ATD4 VDD GC131 Peripheral Controller 5 2 1 HT131 Peripheral Controller Pinouts The pin connections for the HT131 Peripheral Controller are shown in Figure 5 2 The pins are numbered sequentially in a counter clockwise direction from the index mark as viewed from the botton of the chip an ss T a CN xn mnnn a a 28888292222 Eq aa pP EEEFEEEEEPTEEPPEEPEER nl gt gt gt gt lt lt lt lt lt lt lt lt gt lt lt lt lt lt lt lt lt gt REE EO SON SS AS SOSSSESRRRRRERTTRSSESSTLIE VDD 121 LA24 122 LA25 123 LA26 124 LA27 125 LA28 126 LA29 127 LA30 128 LA31 129 FAST SLOW 130 ISYSRES 131 CONFIGAS 132 CONFIGDW 133 CONFIGDR 134 DOEEP 135 NMI 136 ILWR16MEG 137 B
6. Table 3 1 387 Numeric Coprocessor Data Types 20 Table 4 L ISA Bus Cycles Stents usuyoq ha 24 Table 5 1 I O Address Map I es Re RES DR US 54 Table 6 1 Memory Windows EPROM 27256 A Table 6 2 Memory Windows EPROM 27512 75 Table 9 1 Microcache Parameters 127 Table 9 2 A38202 Register Addresses 142 Table 9 3 Multiple Fetch Data Ordering iuste e bos edad iyd 145 Table 9 4 Register Values after Reset 147 Table 10 1 Real time Clock Address Map 151 Table 10 2 Time Calendar and Alarm Data Format 153 Table 10 3 Status Register A OAH eye Ver ehe Angus bade 154 Table 10 4 Status Register B OBH eR E ETSI EAS ER e ak S 154 Table 10 5 Status Register C OCH 156 Table 10 6 Status Register D ODPL 156 Table 10 7 Diagnostic Status Byte OEH 157 Table 10 8 Shutdown Status Byte OFH 158 Table 10 9 Floppy Disk Drive Type Byte 10H
7. 5 2 5 NMI Mask Register Address 70h Bit 7 1 Disable NMI Default setting on RESET Bit 7 0 Enable NMI 55 GC131 Peripheral Controller 5 26 DMA Memory Mapper Page Registers Mapping Mapping Address Address Operation Al6h 23h A24h 31h 87h 97h DACK1 83h 93h DACK2 81h 91h DACK3 82h 92h DACK5 8Bh 9Bh DACK6 89h 99h DACK7 8Ah 9Ah REFRESH 8Fh 9Fh Note Twenty three 8 bit registers between 80h and 9Fh can be written and read back e If 8 amp bit mapping is selected in the configuration register then A2h to A3h produce 00 and no access is allowed to the registers at 90h to 9Fh The mapping addresses are during DMA and REFRESH cycles driven on ATA16 to ATA19 and also on LA17 to LA31 56 GC132 CPU MEMORY CONTROLLER 6 1 INTRODUCTION This chapter describes the function and structure of GC132 CPU Memory controller 6 2 132 CPU MEMORY CONTROLLER OVERVIEW This powerful chip decodes the processor address and control lines and generates the RAS CAS and chip select signals required for memory management Both static and dynamic memories can be used The GC132 Controller features both paged and interleaved memory access techniques that improve overall system throughput The GC132 CPU Memory Controller block diagram Figure 6 1 shows the range of services provided by the chip These services which are used in the
8. Di por DRYIYP MEM Precomp Precomp Pin Pin kb s ns ns Enabled Level 0 0 X 500 125 125 FGND500 High 0 1 0 250 125 250 FGND250 Low 0 1 1 300 125 208 FGND250 Low 1 0 0 250 125 250 FGND250 Low 1 0 1 250 125 250 FGND250 Low 1 1 0 1000 83 83 None High 1 1 1 1000 83 83 None Low Normal values when PUMP PREN pin set low Alternate values when PUMP PREN pin set high DO and 01 are data Rate Control Bits 202 DP8473 Floppy Disk Controller 13 5 3 Drive Control Register Write Only D7 Motor Enable 3 This controls the Motor for drive 3 MTR3 When 0 the output is high when 1 the output is low Note this signal is not output to a pin on 48 pin DIP version D6 Motor Enable 2 Same function as D7 except for drive 2 s motor Note this signal is not brought out to a pin on DIP 05 Motor Enable 1 This bit controls the Motor for drive Ts motor When this bit is 0 the MTR1 output is high D4 Motor Enable 0 Same as D5 except for drive 0 s motor D3 Enable When set to a 1 this enables the DAK INT pins A zero disables these signals D2 Reset Controller This bit when set to a 0 resets the controller and when a 1 enables normal operation It does not affect the Drive Control or Data Rate Registers which are reset only by a hardware reset D1 D0 Drive Select These two pins are encoded for the four drive selects and are gated with the motor enable lines so that only one drive is sele
9. 23 42 2 Replying Agents 2 23 423 Configuring Bus Agents 24 424 Agent Functional Model 24 43 GENERAL ISA BUS ATTRIBUTES 25 44 SIGNAL GROUPS 2 he diy qued qus 25 44 1 Address Signal Group 25 442 Data Signal Group enn 27 443 Cycle Control Signal Group 2 27 444 Central Control Signal Group 29 445 Interrupt Signal Group 30 446 DMA Signal Group 31 447 Power Signal Group 31 45 KEY POINTS TIMING CHART Ua E Ege E eI 32 45 1 Interleaved Dram Timing 32 452 Interleaved Dram Timing 2 33 453 Non Interleaved Dram Timing 1 35 454 Non Interleaved Dram Timing 2 36 45 5 Bits Access to 16 Bits OFF BD Dram 37 456 Refresh Timing c e iade acd 38 457 Refresh Timing 2 reap ave oa peg aces aeg 39 458 Cache Hit
10. D L J SA30 A23 SA29 SA28 A22 CT SA27 21 SA26 A20GATE SA25 A20 SA24 A19 5 23 A18 SA22 GND sA24 17 20 A15 L u SA18 14 L SA17 C J SA16 A12 SA15 A GND Ato SA14 ag lL SA13 SA12 A7 L r SA1 A6 7 SA10 A5 5 9 A2 C L 4 SA6 GND C d Figure 9 9 POFP Pinout 148 10 1287 REAL TIME CLOCK RTC 10 1 INTRODUCTION The system board uses a 1287 real time clock RTC module for its real time clock and configuration memory The RTC module combines a complete time of day clock with alarm 100 year calendar a programmable periodic interrupt 50 bytes of low power user static random access memory SRAM and battery System provisions allow the RTC to operate in a low power mode and protect the contents of both the RAM and clock during system power up and power down The battery maintains clock and calendar information in RAM The system does not charge the battery If the battery fails the 1287 must be replaced Figure 10 1 illustrates the memory map An additional 14 bytes of CMOS RAM is used for the internal clock circuitry 10 2 RTC RAM I O OPERATIONS The sets the system time and data The RTC updates at one second intervals and automatically adjus
11. F 20 d Ts L ee HIS YU Ci TI III CC WW q q 2 EET L E8504 3 d3 35M58 3 EE ds PE 3 CoS 3 FE d E d BRAS d ek 2 d q EMAS d qd LI q EPDz3 q 9 d Os OPIC 3 q d BPD q 24 BPD d SAMSUNG ELECTRONICS rye 4322 q ECA d ST BERE g3 ss q 30 SIMM 269 LL LTT 22 gt CSBHACT I 21 lt EPDU0 EA au jasa 10 gt ee d29 EDE q d q d BPO iz d ad 2 2 d TIT q xx q x ZI q 4 OOVY a Q 21 gt 2 28 d 30 VOC 4 3 ETE EDR 3 3 SAMSUNG ELECTRONICS 270 aroro NS OcA ss aca TTT SSS ener ea cos pm ET aes VOC 1 SEET 1 11 d2 ign g 3d 3 34 a 6 a Jor lt dam I x 4 ee 18 a ra 17 ce is E lt 20 LYUUZu i 4 24 d e 4 50 a is s 16 rr r sx 1 d 8719 1 20 d SAMSUNG
12. tt Error Track 0 4FH L d Error Drive 0 1 74 Motor Speed Error 41 96 196 Time for one rotation us d Error Drive 0 1 A 125 Fixed Disk 8 80 Reset Error 9000 0000 0000 0000 d 81 Format Error dhhh htt tttt tttt L es t h d 82 R W Test Error same as Format 83 Seeking Error 1 OOtt tttt tttt 84 HDD ECC Error 224 Error Drive Error Track Error Head Error Drive Error Track Error Drive 0 1 0 1023 0 15 0 1 0 1023 0 1 Diagnostic A 12 6 Printer Port Test 9 90 Data Port R W Error Op xx same as below 91 Control Port R W Error Op xx Error Bit Set Error Port LPT 0 1 92 Loop Back Test Error Op xx l lll 00011111 Error Pin Combination 92 15 Error Port LPT 0 1 01 13 12 14 10 16 11 17 93 Interrupt Test Error Op xx No meaning Error Port LPT 0 1 94 Printing test Error A 127 RS2322 Port Test A0 Loopback Test Error xxxc tfpo L o Overrun Error p Parity Error f Framing Error t Timeout Error 0 1 stop bit c Error Port 1 2 stop bit COM 0 1 A1 Send Receive Error 10 7 bit data Sent ASCII 11 8 bit data A2 Modem Ctrl Port Error Op Error Port No Error bit set 235 bbbppsdd bbb 000 110 baud
13. 1287 Real time Clock RTC 10 5 1 Diagnostic Status Byte Table 10 7 Diagnostic Status Byte OEH Bit Function 7 chip battery power status 1 Power off 0 Power on 6 Configuration record checksum status indicator 1 Checksum not valid 0 Checksum valid 5 Incorrect configuration information Checks the equipment byte of the configuration record when the system powers up 1 Configuration information not valid 0 Configuration information valid 4 Memory size comparison 1 Memory size different from configuration record 0 Memory size the same as configuration record 3 Initial state of drive C or fixed disk drive controller 1 Wrong controller or drive C System cannot boot from drive C 0 Correct controller and drive The system boots from drive C 2 Time status indicator post checks 1 Time not valid 0 Time valid 1 0 Reserved Note In order for the configuration information to be valid power on check requires at least one floppy disk drive installed bit 0 of the equipment byte set to 1 and the display switch setting matches with the display controller installed 157 1287 Real time Clock RTC 10 5 2 Shutdown Status Byte 0FH When the CPU resets the shutdown status byte is set The reset code identifies the type of reset and signals the system what to do after the reset It also provides a method of resetting the system without losin
14. Enter Setup program at pre boot only AT32 I O enabled Video shadow disabled System BIOS shadow disabled WO U lt q Note Video BIOS alone cannot be shadowed It must be shadowed with the system BIOS 162 1287 Real time Clock RTC 10 5 14 Actual Low and High Extended Memory Bytes 30H and 31H The low and high extended memory bytes represent the total extended memory above 1M determined during system power up System interrupt 15H determnes extended memory size Table 10 20 Low and High Extended Memory Bytes 30H and 31H Bit Function 7 0 Address 30H low byte extended memory size Address 31H high byte extended memory size 0200H 512K RAM exttended 0400H 1024K RAM extended 0600 1536 RAM extended 3C00H 15360K RAM extended 10 5 15 Date Century Byte 32H The date century byte is the century part of the current date encoded in BCD format Table 10 21 Date Century Byte 32H Bit Function 7 0 BCD value for century BIOS sets and reads this value 10 5 16 Setup Information 33H Table 10 22 Setup Information 33H Bit Function 128K ROM expansion or 512 640K Reserved 7 6 Enable user message after initial setup 5 4 Copy of the 386 CRO ET bit will always be 1 regardless if a 387 is present or not 3 0 Reserved 163 1287 Real time Clock RTC RI e gt 105 17 CPU Spee
15. HHHHHHIHHIHHHH 5 d 1 LA b 11 12 I4 IS 16 17 19 Ii I1 HUXP ALI gt gt CALLRDY 12 OL p gt SAMSUNG ELECTRONICS 257 311 gt ep ii 104 gt CBPOCO 712 gt aca EFIE Q Gg 14 11 CAB VCC O SAB GND CBA GND O 44 SBA SAMSUNG ELECTRONICS itle DESKTOP 386 CACHE DATA BUFFERS Document Number 50840 07 0 4214 gt 72 CONNECT 1 2 FOR 64K CACHE WITH REV A AUSTEK CONNECT 2 3 FOR 128K CACHE OR REV B AUSTEK JIA gt CALD gt THESE RAMS ARE SURFACE MOUNTED TO THE BOARD Title 1 1 Hy Ojo aun iiili D SAMSUNG ELETRONICS DESKTOP 386 64K CACHE RAM 5 Document Number 50840 08 0HG D 9 230 259 POET Y 07 o9 10 11 12 13 14 15 CRL U gt CARO 454 gt NOTE THESE RAMS ARE SOCKETED ONTO THE BOARD SAMSUNG ELECTRONICS 260 itl DESKTOP 386 COPTIONAL 64K 128K CACHE RAM ee u 5 Bus Number 508640 09 0 amp amp 16 197 gt 211 gt CL
16. NC vss OUT AD 41 B432MHZ OSC SERIAL PORT 1 ON UA 27 IOR IOW DBO 087 225 69425 2 TX2 DI3A TX3 D DILA TX1 OI2A TX2 DI28 DI3A TX3 DI38 orsa 0148 NC NC i CTL1 NC 002 Rx2 cTL2 m RXZ m xc 204 Ne C199 lt 200 c201 202 1 205 204 8 6 6 6 6 6 680PF 680 680PF L C190 ci88 C1857 C184 220PFl 220PFi 220PFi 220PF GNOCOMO E Tusc DIR 187 gt C186 ay C183 220PF C192 C191 205 itle DESKTOP 386 CSERIAL PARALLEL LOGIC 276 WDATA WGATE TRKO PRT RDATA HO SEL DSKCHG RG MTR2 MTR3 DR2 ORS FILTER PUMP PREN ORV TYP FGNDSOO FGND250 SET CUR VECA FLOPPY CONNECTOR Lb 5D 7D 9 b 116 15 17 D 19 21 q 23D AT 426 255 otara 4 28 2 Tt 1 p n 4 32 G34 335 P lt HEADER i7x2 GND lt C172 1000PF SAMSUNG ELECTRONICS itle DESKTOP 386 FLOPPY DISK CONTROLLER Document Number 2840_26 0 lt 277 2 TD mz
17. 205 13 7 PROCESSOR SOFTWARE INTERFACE atte Ap DE E Ro ea ORA 206 13 71 Command Sequence 42s ones eru enn 206 137 2 DMA Mode duo CE doeet nece e ESTEE IET SN OEC Ide PURI Sd dA 207 1373 MnferrapteMOde ba Rico SERRE HANA EE Sun e RECO UE cs 207 1374 Software Polling 255 ou uer de d 208 CHAPTER 14 POWER SUPPLY DET OVERVIEW de ea igen edited aded osa 209 14 2 FUNCTIONAL DESCRIPTION aw paws we dE debite 209 14 2 1 Input Requirements 2042 ess asd ect ore e ON ea lk deae 209 VI 14 2 2 Output Characteristics Deb ede X EE ped 209 14 2 3 Voltage Adjustment 210 14 24 Over Voltage Protection 210 210 144 POWER SUPPLY CIRCUIT tween IAS 212 14 5 PS 27 SMPS COMPONENTS LAYOUT 213 146 SWITCHING POWER SUPPLY PS 27 PARTS LIST 214 APPENDIX A DIAGNOSTIC DIAGNOSTIC PROGRAM OVERVIEW 217 A 2 HOW TO BOOT THIS DIAGNOSTICS PROGRAM 217 ALI R n Diagnostics a sau ayes esa Vel Ld ca 217 ona Seral Number unuy delen buds Ets e ES emi eerste 218 A23 kuyuk t e aga y CUADRO odes 218 A 24 Prees lt F9 gt key to d
18. Diagnostic A 6 DESCRIPTION OF AUTOMATIC PROCEDURE EDITOR If you select to MAIN MENU the following text will be displayed Automatic Test Procedure Screen Editor Current Time 12 15 28 Copyright C SAMSUNG Electronics Co Ltd 1990 Elapsed Time 03 39 21 Automatic Test Procedure LABEL will be displayed Welcome Select Auto Test Procedure you want to edit NBI 6 1 If you select following text will be displayed Automatic Test Procedure Screen Editor Current Time 12 15 28 Copyright C SAMSUNG Electronics Co Ltd 1990 Elapsed Time 03 39 21 DIENEN R W Test Control Keys Ins Del t1 gt Esc Space Enter Select Item to Edit CURSOR is located which atributte is some different than others And now you ate in Ins Del Mode In this mode you can delete or insert test procedure by using Ins Del key 227 Diagnostic 1 Delete procedure Move CURSOR to position you want to delete and press Del key Notice When you delete one LABEL you can see following procedure LABEL s Name is changed strangely The reason is as below a The Structure of Auto Test procedure The procedure is defined as streams of scan code Actual value is lt F1 gt lt F8 gt
19. Then it tests all combination of Parity Data bits Stop Bits at 2400 baudrate 3 mode This mode tests whole installed port mode all combination of Parity Data bits Stop Bits at 9600 1200 150 baudrate 4 Returns back to MAIN MENU 2993 Diagnostic 5 DESVRIPTION OF AUTO TEST MODE If you select on MAIN MENU following text will be displayed Current Time 12 15 28 AT System Diagnostics Version 2 00X Elapsed Time 03 39 21 Copyright C SAMSUNG Electronics Co Ltd 1990 Pass Fail Video Adapter E Serial Port In this mode the test is performed continuously w o key input Its test procedure is stored in KEYIN DAT file A 5 1 Description of Each Test Procedure 1 test This test diagnoses whole systems In this test other Auto tests and is invoked as sub procedure 2 MONO test This performs test of BIOS ROM Additional System ROM I O Adapter ROM Base Extended RAM and CMOS RAM And above is repeated 224 Diagnostic 3 4 Dacca test It tests floppy disk driver according to System configuration Test items are FDD Reset FDD Reset Rw Test f Seeking and And repeats them continuously BB ME test It tests fixed disk driver according to System ration Test items are HDD Reset HDD Reset and 1 And above is repeated 5 test
20. O 5 Volts Ground Select Transparent or Latched Data When LOW the HT133 Bus Bridge lets data flow from transparently the processor to the AT bus When HIGH HT133 Bus Bridge presents the latched data on the next memory READ Factory test pin To be connected to ground Test Output Used for factory verification of chip integrity 95 CONFIGURATION REGISTERS OF THE GCK131 CHIP SET 8 1 INTRODUCTION This chapter describes and explains the uses of the configuration modules contained in GCK131 chip set 8 2 GENERAL DESCRIPTION The programmable configuration bit registers in each of the three chips allow the GCK131 chip set to be used in a wide variety of applications The registers are designed for use with software which as determined by the system designer allows the end user some flexibility in the way the system operates The programmable registers of each chip are The GC131 Peripheral Controller configuration registers are used to select the Backplane Refresh and DMA clock speeds divisions of the system clock timing are received by the GC131 Controller Mapping of the serial and parallel ports can be configured either by a register in the GC131 from EEPROM control lines The GC132 CPU Memory Controller configuration registers control the general bus timing relationship for RAM and I O the size of the RAM and ROM block which can be selected by registers in the GC132 Controller and lastl
21. Oscillator Frequency 14 31818MHz Four timer the color burst frequency to the backplane Keyboard Output Buffer Full Interrupt request from the 8042 Keyboard Controller This is used as IRQ to the 8259 Interrupt Controller in the HT131 Controller Redefined from PCSRPA On board Parallel Port Chip Select used when the HT16C452 Interface Mode that allows connection to discrete parallel ports of the HT16C452 Interface is enabled by setting Bit 0 of INDEX48h See TNDEX48h on Page 74 50 GC131 Peripheral Controller Pin Symbol Pin Number Pin Type Description PARIE PARITY PCSRPA PCSRPB PCSRPC PCSWPA PCSWPC PWRGOOD REFRESH RESET 5 148 103 104 105 106 107 17 58 157 I 51 Parallel Port Interrupt Enable from the printer control register implemented on the system board Note When using the HT16C452 Interface this pin must be tied to VCC The HT16C452 Interface Mode that allows connection to discrete parallel ports of the HT16C452 Interface is enabled by setting Bit 0 of INDEX48h See INDEX48h on Page 74 Parallel Port Interrupt Request from a printer A configuration register See INDEX43h on Page 68 allows enabling and the direction of this interrupt to either IRQ7 for Port 1 or IRQ5 for Port 2 Memory Parity Error from HT132 sampled one SYSCLOCK cycle after the MEMR command Par
22. This is an input used by the controller to enable the 300 kb s mode This enables the use of floppy drives with either dual or single speed spindle motors For dual speed spindle motors this pin is tied low When low and 300 kb s data rate is selected in the data rate register the PLL actually uses 250 kb s This pin is tied high for single speed spindle motor drives standard AT drive When this pin is high and 300 kb s is selected 300 kb s is used See also RPM LC pin An external resistor connected from this pin to analog ground programs the amount of charge pump current that drives the external filters The PLL Filter Design section shows how to determine the values 190 t awer DP8473 Floppy Disk Controller Symbol Function WGATE STEP RPM LC This active low open drain high drive output enables the write circuitry of the selected disk drive This output has been designed to prevent glitches during power up and power down This prevents writing to the disk when power is cycled This active low open drain high drive output will produce a pulse at a software programmable rate to move the head during a seek operation This high drive open drain output pin has two functions based on the selection of the DRVTYP pin 1 When using a dual speed spindle motor floppy drive DRVTYP pin low this output is used to select the spindle motor speed either 300 RPM or 360 RPM In this mode this o
23. Window Range Use 1 C0000h CFFFFh Video BIOS As noted in the next section this space can be further split into C0000h C7FFFh C8000h CFFFFh 2 E0000h FFFFFh Lower BIOS 3 FE0000h FFFFFFh Middle BIOS 4 FFFE0000h FFFFFFFFh Upper BIOS Table 6 2 Memory Windows EPROM Type 27512 Note The installed chip s type is signalled by the setting of INDEX01h General setup bits This as noted in Chapter 8 The Configuration Registers Bit 2 is to be set to 0 when EPROM Type 27256 is used and set to 1 with the 27512 6 3 5 Video BIOS Space in Window I can be Split 32K Video BIOS Feature Releases Space for RAM or Backplane Memory Useful in systems that need only 32K Video BIOS space the ATLAS Chip Set allows the allocation of either 32K or 64K space within Window 1 for Video BIOS Released space can be used for RAM or backplane memory Here s how it works INDEXOFh Bits 2 and 3 Adjust Video BIOS Space When 64K Video BIOS space is required INDEXOFh Bits 2 and 3 remain at their default setting of 0 For 32K Video space allocation Bit 3 is set to I and Bit 2 designates by its condition the region in which the system expects to find the 32K Video BIOS Bit 2 is set to 0 when the 32K chunk resides in the region bounded by C0000h C7FFFh Bit 2 is set to Y when the chunk resides in C8000h CFFFFh Notes 1 If Bit 3 if INDEXOFh is set to 0 the condition of Bit 2 is ig
24. 182 Keyboard and Mouse Controller SET DEFAULT F6H The set default command reinitializes the mouse to its power on default state The mouse power on default state is shown below Sampling rate 100 samples second Scaling Linear scaling Mode Stream mode Resolution 4 counts mm Transmissions Disabled RESEND FEH The resend command is issued by the system in response to transmission errors from the mouse The mouse responds to this command by retransmitting its last data packet RESET FFH The reset command instructs the mouse to run its internal self test routine This command puts the mouse into reset mode 1245 Mouse Io System Replies There are two mouse to system replies Both replies are related to command processing and are read by the system at port 60H ACKNOWLEDGE FAH The mouse replies with an acknowledge FAH whenever it receives a valid command from the system Unlike mouse serial data packets the acknowledge reply is not stored in a buffer in internal memory but is discarded immediately after it is transmitted If a new command is received while the mouse is in the acknowledge reply process the mouse discards the acknowledge reply and begins processing the new command immediately Note The reset wrap mode ECH and reset FFH commands are exceptions to mouse acknowledge response The mouse does not respond with an acknowledge to either of these commands RESEND FEH The mouse replies
25. GC132 CPU Memory Controller 6 63 Four Banks of DRAM As with the two banks of DRAM four banks of DRAM will interleave but this is not strictly speaking four way interleaving As shown in Figure 6 9 if the processor is accessing Location 0 the consecutive reads are BANKO BANKO BANK1 BANKO and so on This continues until at a much higher address the chip set switches to BANKS2 and 3 The interleaving then cycles in this manner BANK2 BANK3 BANK2 BANK3 and so on The change froM 1 to BANK2 BANK3 interleaving takes place at 2Mb for 256K RAMs and 8Mb for 1 RAMs 16 Mb BANKS 2 and 3 5 INTERLEAVE 2 3 2 8 Mb 1 f 8 Mb 0 1 0 4 Banks of DRAM Banks of DRAM installed at 2 Mb installed at 8 Mb Transition Boundary Transition Boundary BANKS 0 and 1 4 Mb BANKS INTERLEAVE 2 and 3 INTERLEAVE Mb BANKS 0 and 1 INTERLEAVE 1Mb 1Mb BANKS 640K BANKS 640K 0 and 1 0 and 1 INTERLEAVE 0 INTERLEAVE 0 4 Banks 4 Banks of 256K DRAMs of 1 Mb DRAMs Figure 6 9 The Effects of REMAP with Four Banks of RAM 82 GC132 CPU Memory Controller True four way interleaving requires the use of either four or eight banks Incidentally an example of true four way interleaving would follow the sequence BANKO BANK2 BANK3 BANK1 BANK2 BANK3 so on But for this to work properly the user s sy
26. SAMSUNG ELECTRONICS gt Tek dil lt 51 lt 4 lt 24 HATO 33 gt CBHES BRASS 22 50 5 4 BRAT 1 Rt F l it R2 L IL e 2 Dm UD RD RED EU E Ft S aaa sal YI L a s 8 2 150 5 4 SAMSUNG ELECTRONICS itle DESKTOP 586 4 5 BUFFERS Document Number 50840 15 0 1 555r 266 T n TW E mes 51 1112 gt CECASO C5 II lt BRASO lt ERED LEF Fe q 29 267 gt 8021 2 F sJ 98 122 4 L T 6 Cot d gep d SAMSUNG ELECTRONICS a q 5 31 gt CEES SEE SENA ES xm reins ss C C oe ee ee ee s 28 29 gt MM 268 j 9 1 wu 35 SAMSUNG ELECTRONICS gt TSS Ten ue Koc OEE a puram YI LE paier IHE lt EREZ P I ere 4 2 3 d MEI ETE 425 22 1 7 126 4 d 29 gt ES 9 41 HIM Een d 19
27. The reset wrap mode command resets the mouse to normal operation 181 Keyboard and Mouse Controller SET WRAP MODE This command sets wrap mode the mouse echo mode With the exception of the reset wrap mode ECH and reset mouse FFH commands the mouse will echo all data and commands received from the system SET REMOTE MODE F0H This command sets remote mode the mouse data can only be transmitted in reply to a read data command READ DEVICE TYPE F2H The read device type command reads the mouse ID byte The mouse returns a value of 00H to the read device command SET SAMPLING RATE F3H This command sets the sampling rate of the mouse The sampling rate is defined as the number of times per second that the system checks for mouse data This is a two byte command The set sampling rate command F3H must be followed by a second byte that represents the hex value of the sampling rate The allowable values are defined below Hex Value Sampling Rate OAH 10 samples second 14H 20 samples second 28H 40 samples second 3CH 60 samples second 50H 80 samples second 64H 100 samples second C8H 200 samples second ENABLE The enable command enables data transmissions if the mouse has been set to stream mode This command has no effect in remote mode DISABLE F5H The disable command disables data transmissions if the mouse has been set to stream mode This command has no effect in remote mode
28. 2 R5 91012 167 203 R CARBON SMD MCR18J203TA ROHM 1 R17 22 91018 167 000 R CARBON SMD 18 000 ROHM 6 R25 12 91018 167 000 CARBON SMD 18 000 ROHM 2 R26 49 91018 167 102 CARBON SMD MCR18J102TA ROHM RC3216J102CS SEM 2 R35 36 91018 167 102 R CARBON SMD MCR18J102TA ROHM RC3216J102CS SEM 2 R42 44 91018 167 102 CARBON SMD MCR18J102TA ROHM RC3216J102CS SEM 3 R58 91018 167 102 CARBON SMD MCR18J102TA ROHM RC3216 102CS SFM 1 R8 10 91018 167 103 CARBON SMD 18 103 ROHM RC3216 103CS SEM 3 R14 54 91018 167 103 R CARBON SMD MCR18J103TA 216 103 5 SFM 2 R31 32 91018 167 103 R CARBON SMD MCR18J103TA lt 3216103 5 SEM 2 R40 41 91018 167 103 R CARBON SMD MCR18J103TA ROHM RC3216 103CS SEM 2 R47 48 91018 167 103 R CARBON SMD MCR18J103TA ROHM RC3216J103CS SEM 2 R57 91018 167 103 CARBON SMD 8 ROHM RC3216J103CS SEM 1 R59 65 91018 167 103 R CARBON SMD MCR18J103TA ROHM RC3216 103CS SEM 7 R68 69 91018 167 103 R CARBON SMD MCR18J103TA ROHM RC3216 103CS SEM 2 R45 91018 167 330 R CARBON SMD MCR18J330TA ROHM 1 R70 71 91018 167 471 CARBON SMD 18 471 ROHM 2 R29 91018 167 472 CARBON SMD MCR18J472TA ROHM RC3216472CS SEM 1 R67 91018 167 472 R CARBON SMD 18 472 ROHM C3216 472CS SEM 1 R34 91018 167 473 R CARBON SMD MCR18J473TA ROHM RC3216J473CS S
29. BANKSEL1 BANKSELO ROMADDR ADS SPA20 MUXPA20 PA31 PA25 PA24 PA23 PA22 VDD NC 120 119 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 IOWS CLK646 SAB646 CONVAO 516 IIOCS16 AEN1 ATA0 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 CONFIGAS CONFIGDR CONFIGDW TESTOUT IENADDSTB PARDATO3 VSS STARTCYC ILOCAL VDD PARDATO2 IOCHRDY TESTRES PD31 ATA1 ATA3 PD30 PD29 PD28 PD27 PD26 PD25 PD24 PD23 PD22 PD21 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 GC132 CPU Memory Controller TINO FIN O b OD NC PA21 PA20 PA19 PA18 PA17 16 2 Figure 6 2 HT132 CPU Memory Controller Pinouts DC n WR HLDA FETEN N 13 14 15 16 17 18 19 20 LBS16 IPBEN0 PBEN2 PBEN3 18532 VSS 21 NC VDD RDY387 22 23 24 25 26 59 LBHE IMEMW 27 28 30 31 BALE 32 33 34 35 36 37 38 DBEN VSS SLOWCLK N C FASTCLK PD20 PD19 CLKIN PROCCLK PD18 PD17 39 40 PD16 TESTIN 81 VDD VDD PD15 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2
30. CHAPTER 13 DP8473 FLOPPY DISK CONTROLLER 13 1 INTRODUCTION adit guns Rata Pu ud aaa apuq ae assay e fada 185 133 FEATURES wit 25 eA gas 186 13 3 HEIN DESCRIPTIONS lt Reese Rape nae ale eg 188 134 FUNCTIONAL DESCRIPTIONS 193 134 1 765A Compatible Micro Engine 5222 na on vs SR 193 1342 Data Separator 193 134 3 PLL Diagnostic Modes 196 1344 Filter cote EE EHE 197 134 5 Write Precompensation LR RE 199 1346 PC AT and PC XT Logic Blocks 199 13 5 J REGISTER DESCRIPTION 201 135 11 Main Status Register Read 201 13 5 2 Data Register Read Write soa 202 1353 Drive Control Register Write Only casa 203 13 54 Data Rate Register Write Only a eer xe Rn EE a v 204 1355 Disk Changed Register Read 203 136 RESULT PHASE STATUS REGISTERS p24 204 136 1 Status Register ius ra cop PONS babe INDE bij 204 136 2 Status Register 50 1 p HERE YA 204 136 3 Status Register 2 812 acreano uhr rh ee hapas
31. INDEX40h Clock Dividers Non TURBO Mode 116 Configuration Registers of the GCK131 Chip Set Bit Description 5 4 The combination of Bits 5 and 4 select the following Clock divider for SLOW speed Divide incoming syscLk by one Divide incoming svsci by two Divide incoming syscLk by four Divide incoming syscLk by eight MO Reserved Always program to 0 Reserved Always program to 0 Figure 8 19 INDEX40h Clock Dividers Non TURBO Mode Note For information regarding TURBO mode See INDEX4Ih Indicated FAST SLOW Pin 130 of the GC131 Controller INDEX41h Clock dividers for high speed TURBO Default value 3Ah INDEX41h is available to program the desired clock rates for various functions of the GCK131 Chip Set when operating in TURBO mode The resultant clock rate is a division of the incoming signal at the syScLk input Bits 0 and 1 control the frequency of BUSCLOCK to t he backplane Bits 2 and 3 are used to select the desired REFRESH speed Similarly Bits 4 and 5 program the DMA speed while in TURBO mode Bit State Description 1 0 Bit 1 Bit 0 The combination of Bits 1 and 0 select the following Back plane BUSCLOCK clock divider for FAST speed 0 Divide incoming syscLk by one 1 Divide incoming syscLk by two 0 Divide incoming syscLk by four 1 Divide incoming svsci by eight 3 2 Bit 3 Bit 2 The combination of Bits 3 and 2 select th
32. IOCHROY IRe3 IROS 18 6 IRQ IRQ9 IRO10 IRQ11 IRQ12 TRQ1L4 IRQ15 MASTERN DACKON DACK2N DACKIN DACKSN DACKEN DACK N 817 FRSTRC SA1LB ALTMUXA20 LWLGMEGN CK8042 CK8042N CS8042N 5 CSEEP DOEEP RTCAS RICDS ite cose RT CRW amp PCSRPEN BFDIR PCSHPAN BFEN D 3 PCSHPCN LPTOEN PCSRPAN PARCSN 92 DIEEP PARIRG RTCIRQM PARIE OPTBUFFULL TURBO CLK28I REFRESHN PHRGOOD IORN SYSRESN IOWN MEGATSTN MEMRN TESTA SMEMRN TESTC SMEMWN TRITST SBHEN NOTSTOUT LSI LOGIC STEP III II 0 191 gt CATDIO 151 gt oct 214 CSPEAKER 22 In RT CER NS CLL E 15255 LIS ETE TURBO gt d 3 s RESET s APRI Cool ote S21 gt SAMSUNG ELECTRONICS 263 fae NER lt HALT Sy gt Toto 437 gt lt 97 CBRED j MALO 2 gt 50 5 4 BHA 5183 A IBHAT R 8 RE BH 3 SAMSUNG ELECTRONICS itle DESKTOP 386 CORAM 0 1 SUFFERS Document Number 08640_13 0WG 52 Tero 427 gt 5 5 4 33 E 1 HEZ 5 150 5 4 l aJ 5 5 4 33 8 ISO SIP4 A CSEMACG 31
33. IOCS16 114 I I O Chip Select is 16 Bits When asserted by a 16 bit device on the AT backplane the chip will not perform a 8 to 16 bit conversion cycle If it is inactive the HT132 will assume the I O cycle is to an 8 bit device Note This signal refers to the device responding to the cycle not the cycle itself 3632 GC132 CPU Memory Controller Pin Symbol Pin Pin Number Type Description NOW IRQ13 LBHE LBS16 ILOCAL LWEN IMEMCS16 MEMR 28 29 53 24 I 14 99 31 115 I 26 Read Normally an output see the output pin definitions but during DMA or MASTER mode it becomes in input driven by the DMA controller Write Normally an output See the Output Pin Definitions but during DMA or MASTER mode it becomes an input driven by the DMA controller Interrupt Request 13 When HIGH the coprocessor has detected an exception and has raised an interrupt Latched Bus HIGH Enable In Indicates when the upper 8 data bits of the 16 bit backplane is active Latched Bus Size 16 When active the HT132 is signalling the processor that the current cycle is inappropriate for 16 bit backplane operations and the processor will adjust its cycle or issue another Local Bus Access When LOW indicates that the current cycle is used for local bus access and not for the backplane See also FETEN Latched Write Enable When activ
34. ISA Bus Interface SRDY D SRDY Synchronous Ready is asserted by the replying agent to terminate the current bus cycle without any further wait states The absolute minimum command pulse width is nominally 1 SYSCLK period 125ns in length and is known as a zero wait state cycle SRAs are not required to support SRDY MEMREF I O MEMREF Memory Refresh is asserted during a DRAM refresh cycle By design only memory read cycles may occur while MEMREF is asserted The address present on A 7 0 is used by memory agents as the address of the row to be refreshed An SRA may if it is the current bus owner tri state its address command and data drivers and asserts MEMREF to force the PRA to conduct a refresh cycle SRAs must do this every 15us if they retain ownership of the ISAS bus or the contents of the system DRAM will be lost When a refresh cycle is initiated in this manner the PRA asserts A 7 0 and MEMR MWTC Refresh cycles occur at a period of 15ys Each of the 256 possible refresh addresses must therefore be refreshed at least once every 4 ms 444 Central Control Signal Group The central control group consists of special timing control and error signals The function of these signals is as follows SECMAST SECMAST Secondary Master is asserted by an SRA to gain control of the ISA bus after receiving the appropriate DACKn from the PRA When SECMAST is asserted all other requesting agents must tri s
35. MBSHADOW is a device used to implement a 32 bit version of BIOS called Middle BIOS located in memory at Window 3 MBSHADOW operates when the MBEN device is enabled VBSHADOW is a device used to implement a 32 bit version of Video BIOS a replacement of the 16 bit version in the memory region called Window VBEN is a device used to regulate the shadowing of Video BIOS When enabled the system takes the configuration established by VBSHADOW 70 GC132 CPU Memory Controller Memory Map 1 Mb 1 bank 256K RAMs 2 Mb 2 banks 256K RAMs 3 4 Mb 4 banks 256K RAMs 3 6 Mb 6 banks 256K RAMs 3 4 Mb 1 bank 1 Mb RAMs 8 Mb 2 banks 1 Mb RAMs 16 Mb 4 banks 1 Mb RAMs 24 Mb 6 banks 1 Mb RAMs 1 Absolute Addresses 16 8 4 18 10 Oh OFFFFh ___ 32 Bit on board RAM A0000h BFFFFh AT compatible RAM Video BIOS 2 AT compatible RAM Lower BIOS 2 Lower BIOS 2 32 Bit on board RAM FE0000h FEFFFFh FF0000h FFFFFFh e Upper BIOS 2 EPROM D AT compatible RAM Not used Notes 1 Banks 5 and 6 operate exactly as the other banks but they are configured by a separate register 2 Memory type in these locations is dependent upon the configuration registers and the EPROM type used 3 Interleaving is performed on A2 when more than one bank of memory is used 4 OBR On
36. PD1 PD0 PARDATO0 NC NC VSS PARDATO1 PARITY ERROR386 PEREQ386 BUSY386 IRQ STEN RESET387 ERROR387 PEREQ387 BUSY387 ICS287 CLKM RESET CLREXPTION FAST SLOW RC ISYSCLK GC132 CPU Memory Controller 6 2 2 HT132 CPU Memory Controller Pin Descriptions This section describes the pins of the HT132 CPU Memory Controller The pin idenification numbers correspond with those shown in Figure 6 2 Pinouts HT132 CPU Memory Controller 60 on Page 17 Pin Pin Pin Symbol Number Type Description ADDRSWT 130 O Address Select Selects either row or column addresses ADS 152 I Address Status This signal marks the start of each memory or I O cycle Indicates that a valid bus cycle definition and an address are available ADS is active LOW on the same clock pulse as the driven addresses ADS is not driven during a bus HOLD AEN1 113 I Address Enable Active during DMA but not during a MASTER access Indicates 8 bit DMA access ATAO 112 I AT Backplane Address 0 1 111 110 BALE 30 O Buffered Address Latch Enable When HIGH the addresses are transparent between the processor side to the backplane side On the falling edge the addresses are latched and held until another BALE BANKSELO 149 O Demultiplexer Select specifies which bank is BANKSEL1 148 to receive the CAS strobes BBENO to 124 Bus Bridge Data Enable BBENO 3 enable BBEN4 128 the data buffers bet
37. Port B register in the HT131 Controller SYSCLK 6 I Main HT131 System Clock Connects with the HT132 Controller s SYSCLK The ISYSCLK frequency is half that of the CPU ISYSRES 131 1 System Reset Derived from VCC and the RESET pushbutton SYSRES is LOW while VCC is LOW or while the pushbutton is pressed and goes HIGH after a debounce period The debounce period should not end while PWRGOOD is still LOW 52 GC131 Peripheral Controiler Pin Pin Pin Symbol Number Type Description TC 63 O Terminal Count from the DMA controllers in the HT131 Controller to the device on the channel that is doing the current DMA cycle indicating that this is the last transfer for this DMA channel TESTA 9 I Factory test pin Always connect to ground TESTB 49 I Factory test pin Always connected to ground TESTC 50 I Factory test pin Always connected to ground TRITST 15 I Factory test pin Always connected to ground VDD 22 41 5 volts 59 80 90 99 121 142 160 VSS 1 12 Ground 19 20 21 40 60 61 62 81 100 101 102 120 139 140 141 53 ISAGC131 Peripheral Controller 5 2 3 I O Address Map Table 5 1 Address Map Address range Device Operation Oh Fh Controller 1 8237 slave Read Write 20h 21h Interrupt controller 1 8259 master Read Write 24h Configuration register Address Write only 28h
38. RTC 104 3 Status Register 0CH Table 10 5 Status Register C Bit Function 7 IROF interrupt request flag Set to 1 when any of the conditions cause an interrupt is true and the interrupt enable for that condition is true 6 PF periodic interrupt flag Set to 1 when a transition selected by RS3 0 occurs in the divider chain This bit becomes active independent of the condition of the PIE control bit The PF bit generates an interrupt and sets if PIE 1 i 5 AF alarm interrupt flag Set to 1 when a match occurs between the time registers and alarm registers during an update cycle The flag is independent of the condition of the and generates an interrupt it AIE is true 4 UP update ended interrupt flag Set to 1 when an update ends This flag is also independent of the condition of the UIE and generates an interrupt it UIE is true 3 0 Reserved 1044 Status REgister D Table 10 6 Status Register D 0 Bit Function 7 Valid RAM and time VRT bit This read only bit determines the condition of the RTC internal battery 1 Battery operational 0 A low power sense Indicates a dead battery in the KIC 6 0 Reserved 105 CONFIGURATION BYTES The configuration bytes provide information on diagnostic status shutdown status equipment memory and other configuration parameters refer to Table 10 7 through 10 24 156
39. The ISA bus allows several different bus agents A bus agent is a physical unit which has an interface directly to the ISA bus A memory expansion board a LAN controller and a modem are all examples of bus agents The two basic types of bus agents are Requesting Agents and Replying Agents 4 2 1 Requesting Agents Requesting agents initiate an ISA bus cycle Requesting agents can be either a Primary Requesting Agent PRA or an SRA The PRA has immediate access to the ISA bus when control has been granted to an SRA The only PRA allowed is the system board The SRA is an optional Requesting Agent that normally does not have immediate control of the ISA bus Control of the bus is requested from the PRA Multiplex SRAs are allowed An SRA must have a 16 bit bus interface No 8 bit 5 are allowed on the ISA bus 4 2 2 Replying Agents A replying agent responds to ISA bus cycles when initiated by a requesting agent A replying agent cannot initiate ISA bus cycles ISA Bus Interface 4 2 3 Configuring Bus Agents The ISA bus services 11 agents via 8 bit and 16 bit portions of the bus The number of each agent type that is suported is as follows Agent 1 11 PRA 10 Requesting agent 1 10 PRA 9 PRA 1 PRA SRA 0 9 Replying agent 0 10 4 24 Agent Function Model Table 4 1 describes the types of ISA bus cycles in which ISA bus agents may participate Table 4 1 ISA Bus Cycles Type of Agent Agent s A
40. The main clock that drives the 80386 and 80387 and 80385 if fitted This signal can be buffered or even inverted since the HT132 Controller does not use this clock CLKIN is used to drive the internal state machines RASO to 144 O Row Address Strobe For the DRAMs 5 143 137 138 42 Processor Reset When active the 842 66 keyboard controller is requesting that the CPU be reset but NOT the system GC132 CPU Memory Controller Pin Symbol Pin Number Pin Type Description RDY387 READY REFRESH RESET RESET387 ROMADDR ROMEN SAB646 SLOWCLK SPA20 23 147 129 45 51 151 150 117 153 267 Ready from the 80387 When LOW the 80387 Coprocessor is terminating its cycle Ready to the 80386 Terminates the cycle REFRESH Indicates that the current DMA cycle is a REFRESH operation and the HT132 will not produce a CAS signal just a RAS RESET System When active the CPU and the entire system will be reset RESET 80387 A synchronous reset to the 80387 Coprocessor HIGH ROM Address Connects to A16 on a 27512 or VPP on a 27256 When the configuration bit is set for 27512 usage this line will follow a latched version of PA16 when set for a EPROM 27256 it will remain at VDD EPROM Enable Connects to the OE of the EPROM It indicates when the device should drive the data bus Select Latched or Transparent Data
41. When LOW the HT133 will on a READ allow un inhibited data flow from the backplane to the processor local bus When HIGH the HT133 will present the data latched by CLK646 to the lower byte on the local data bus This is used during an 8 to 16 bit read conversion cycle SLOW System Clock Frequency 14 318MHz Used for the system clock during slow speed the FAST SLOW signal is LOW Switched Processor Address 20 Normally this signal is an output that follows PA20 except when MUXPA20 is HIGH but during a DMA or MASTER mode SPA20 is the Address line 20 input GC132 CPU Memory Controller Pin Pin Pin Symbol Number Type Description STARTCYC 100 O Start a DRAM Cycle Useful when implementing a memory sub system external to the HT132 this signal indicates the start of a DRAM cycle Defined as RAS and CAS this signal helps with the problem of knowing when to initiate a CAS precharge during a page mode cycle See also FETEN STEN 52 O Connects to the STEN line of the 80387 Coprocessor ISYSCLK 41 System Clock Main clock for the HT131 equivalent to CLKIN divided by 2 TESTIN 39 I Test Mode Enable Used for fault coverage in the fabrication process Not user applicable TESTOUT 104 O Factory test pin Normally not connected TESTRES 108 I TEST Reset Used for fault coverage in the fabrication process Not user applicable WR 11 Write Read Status line from the 80386 VDD 22 40 5 volts 59 80 98 121 142
42. a Default Mode case VGA EXE option when booting Diagnostics Test items are and BIRET ONU And repeates them continuously b test Mode Test items are and 8190176 And repeates them 6 test It sounds Do Re Mi Fa Mi Re Do and frequency increases upto 1112Hz And repeates above test His procedure can be defined by User 8 Returns back to MAIN MENU 225 Diagnostic 5 2 How it Works 1 Once Automatic test is started it does not stop unless Press lt C gt key When test procedure comes to end it is wrap around to start and repeated from start If an automatic procedure contains Sub Automatic test procedure the Sub procedure Inner Auto procedure will be performed by on time And the Main procedure Outer Auto procedure is continued When Main procedure meet End of test it is repeated from the Start So Sub procedure will be invoked again Currently MAS test procedure invokes other Auto procedure and invoked procedure does not contain another Auto procedure But this program allows one more Sub Auto procedure to be invoked KEYIN DAT file contains definition of each Auto test procedure This file is initialized automatically if there is no KEYIN DAT file in current directory And it also be initialized at any time by Menu When KEYIN DAT is initialized each test procedure is adjusted properly according to current System Configuration 226
43. controlled oscillator VCO and a programmable divider The phase comparator detects the difference between the phase of the divider s output and the phase of the raw data being read from the disk This phase difference is converted to a current which either charges or discharges one of the three external filters The resulting voltage on the filter changes the frequency of the VCO and the divider output to reduce the phase difference between the input data and the divider s output The PLL is locked when the frequency of the divider is exactly the same as the average frequency of the data read from the disk A block diagram of the data separator is shown in Figure 13 4 193 DP8473 Floppy Disk Controller OSC DIVIDE PUMP DIVIDE BY 2 A 7 SECONDARY PLL 4 SETCUR RED DATA 1 4 PERIOD PHASE CHARGE DELAY LINE MUX COMPARATOR Ag pump T FILTERS FCR D GATE SPST Sass a E ALL DATA CALIBRATION CURRENT RATES SEE FIGURE IV I FGND250 FILTER SELECT V LOGIC FGND500 One NRZ NRZREAD DATA YNE LOSIC LOGIC T TO SERIALIZER ADDRESS AME MARK DETECT Figure 13 4 Block Diagram of DP8473 s Data Separator DP8473 DP8473 DP8473 FILTER SETCUR FILTER SETCUR FILTER SETCUR Ri R Ra R CATS FGND250 FGND500 FGND250 FGND500 a Single Data Rate b 250 500 kb s Filter 250 500 kb s and 1 Mb s Note For
44. equal to the number of groups in the cache implementation If there is only one group the cache is direct mapped if the number of groups equals the nuraber of tags the cache is fully associative With the A38202 each location in main memory can reside in up to two possible locations in the cache Cache Coherency The A38202 provides both software and hardware mechanisms to assure coherency of data in systems with other bus masters such as other processors or DMA devices The A38202 can purge any stale data by executing an invalidation instruction or by monitoring the system bus for invalidation cycles bus watching Write Buffer Support The A38202 Microcache on chip system bus controller has full support for the use of a write buffer to increase system performance The write buffer stores data output from the processor until the data can be written to main memory The processor may continue operation without waiting for the main memory write to complete thereby increasing processor performance 9 1 2 A38202 Programming The A38202 is capable of executing a set of instructions that manage the cache operating modes These cache control instructions are issued as I O instructions from the 80386 usually as part of the initialization process The A38202 may be programmed to perform the following control functions Enable or disable the cache for normal operation Define the current cache configuration Define up to three independent
45. must fetch a block from system memory Most system buses do not enable simple transfers of such a large number of bytes Therefore the block is viewed as 8 or 16 dependent on cache size subblocks of 4 or 16 bytes each Each entry in each group has a field which indicates the presence or absence of each individual subblock Depending on the cache configuration the A38202 fetches either 4 or 16 bytes from the system memory in one access The A38202 implements a read allocate cache For a read access if the data is not present in the cache then a block is allocated in the cache for the data fetched from system memory For a write access if the data is not in the cache then it is only written to system memory no space is allsocated in the cache for it 9 2 3 Cache Coherency Problems with cache coherency occur when another processor or bus controller writes data to a memory location which is stored in the cache This leaves the cache with stale data and the CPU may never be made aware of the new information The A38202 provides two mechanisms to solve the problem of cache coherency a software mechanism that requires the operating system to manage the sharing of data and a hardware mechanism to indicate cycles which should be treated as invalidation requests 132 Software Mechanisms for Coherency The software solution to coherency requires that no two bus masters in a system share the same section of writable memory at
46. 001 150 baud 010 300 baud 011 600 baud 100 1200 baud 101 2400 baud 110 4800 baud 111 9600 baud Diagnostic A3 RxD INT Test Error A4 TxD INT Test Error A5 Break INT Test Error DCD CTS INT Test Error A7 DSR RI INT Test Error 8 Overrun INT Test Error A9 Baud Test Error Op xx Op xx no meaning Error Port COM 1 2 no meaning L Arror Port COM 1 2 AA Port not attached Error AB loopback test timeout Error AC INT test timeout Error A 12 9 Ethernet Test C BO NIC I O Port not found Error B1 No Shared RAM found Error B2 RAM test Error 0000 test 1 B3 RAM test Error FFFFtest 2 B4 RAM test Error A55Atest 3 B5 RAM test Error inc test 4 B6 RAM test Error 0000 test 5 B7 Transmit has hung Error B8 Receive has hung Error B9 NIC Loopback test Error BA SNI Loopback test Error BB CRC mismatch Error BC CABLE not testminated Error BD Loopback test Error BE test Error 236 Diagnostic A 13 LOOPBACK PIN CONFIGURATION Printer Port Test Dee iy TT 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 RS232 Port Test 05 04 03 02 01 09 08 07 06 237 MESSAGES B 1 INTRODUCTION This chapter describes the various system screen messages and error beep codes Information is grouped as follows e POST and boot error messages POST and boot informational mess
47. 2KV 561 EA 1 SEMCO 1047 50V 104 EA 4 SEMCO HCYF2E472M 250V 472 EA 4 SEMCO HCYF2E222M 250V 222 Y EA 1 SEMCO CCYF1H103Z 50V 103 EA 1 SEMCO 50V 103 EA 1 CENTRAB 250V AC 2 2uF EA 1 SHINSHIN 50V 102 EA 2 DONGKUCK 100V 104 EA 1 DONGKUCK 100V 153 EA 1 DONGKUCK 100V 222 EA 1 DONGKUCK XG V 275V 47 2 XG V 275V 224 X EA 1 TEAPO CEGLX1H010 50V 1uF EA 1 SEMCO CEGLXIHAR7 50V 47uF EA 5 SEMCO CEGLX1C330 16V 33uF EA 1 SEMCO CEGLX1V470 35V 47uF EA 1 SEMCO CEGLX1A101 10V 100uF EA 1 SEMCO CEGLT1C221 16V 220uF EA 2 SEMCO CEGLT1C471 16V 470uF EA 1 SEMCO CEGLT1E471 25V 470uF EA 1 SEMCO CESMS2D681 200V 680uF EA 2 SEMCO 214 APPENDIX DIAGNOSTIC MESSAGES SCHIMETIC PART LIST EXPLODED VIEW mony gt 215 DIAGNOSTIC A 1 DIAGNOSTIC PROGRAM OVERVIEW There are six files for diagnostic program LOADER COM DIAG EXE VGA EXE KEYIN DAT HELP DAT ERROR REC 1 LOADER COM loads DIAG EXE main program and runs it 2 DIAG EXE is a main program 3 VGA EXE is a EGA VGA test program 4 KEYIN DAT has the information of the Auto Test procedure 5 HELP DAT contains Help Messages 6 ERROR REC contains Error informations during Test This diagnostic program runs in DOS environment Version 3 x Above A 2 HOW TO BOOT THIS DIAGNOSTICS PROGRAM A 2 1 Run Diagnostics Just type LOADER if EGA VGA Adapter is installed tyte LOADER VGA EXE and press Enter gt key Next time you can se
48. 3 Programmable Configuration Bits Allow RAM Shadowing 73 6 34 Four Memory Windows VR ne ya gan A 635 Video BIOS Space in Window I can Split ias Lo Sed gl SP NERONE 75 RAM SHADOWING WINDOWS 1 THROUGH 3 76 641 Window 1 Video BIOS Shadowing 76 642 Window 2 Lower BIOS uui n vast ax 77 64 3 Window 3 Middle BIOS x oA Rag efte et En 77 644 Window 4 Upper BIOS 77 USE THE REMAP FEATURE TO SAVE UNUSED RAM SPACE 78 MEMORY MAP OF THE DRAM SUBSYSTEM 79 601 One Bank OF RAM ass ls Qu PRO exce e dem a Rusia acd 80 662 JIwobBanksof DRAM dst ess ep POE s S Rex 8 663 Four Banks of DRAM 52 kot vs eet ell Hale tak een a Ini 82 6 64 Six Banks of DRAM 83 EMS HOLE SE anh D PR edet uM a 83 CONNECTING MULTIPLE BANKS OF DRAM TO THE 131 CHIP SET 84 DREAM REEFRESFL I aaa uyakuna uapa a sre 87 CHAPTER 7 GC133 BUS BRIDGE INTERFACE 7 1 7 2 73 7 INTRODUCTION slap hu ait he oh ken Oy 89 SEPARATION OF 32 BIT AND 16 BIT WORLDS 89 HT133 BUS BRIDGE INTERFACE PINOUTS
49. 3PIN 1 P8 93341 004 130 CONNECTOR HEADER SPS04 S04G WOO YOUNG 1 P20 22 93341 026 040 CONNECTOR HEADER SPS04 D26G WOO YOUNG 2 P15 93341 034 030 CONNECTOR HEADER SPS04 D34A4 WOO YOUNG 1 P18 93341 040 020 CONNECTOR HEADER SPS04 D40G WOO YOUNG 1 P19 93345 021 041 CONNECTOR HEADER SPS04 D04A WOO YOUNG 1 P16 17 93345 021 041 CONNECTOR HEADER SPS04 DO4A WOO YOUNG 2 P9 93345 021 050 CONNECTOR PIN HEADER SPS04 S5A4 WOO YOUNG 1 SM1 24 93345 039 600 CONNECTOR SIMM SOCKET 821885 2 AMP 12 J10 93345 051 000 JACK DIN LN 0508A 6A LIB SHFNG 1 14 93345 077 060 CONN HEADER PWR GTC6R 1 BURNDY 2 042 93354 124 010 SOCKET WSDIF 24 WOO YOUNG 1 U10 11 93354 124 280 SOCKET IC WSDIF 24N WOO YOUNG 2 U41 49 93354 128 010 SOCKET IC WSDIF 28P WOO YOUNG 2 U8 93354 132 040 SOCKET EMC 550 114 132 TEKCON 1 USO 93354 140 010 SOCKET IC WSDIF 40P WOO YOUNG 1 U2 4 93354 152 010 SOCKET IC 821551 1 PLCC 2 U14 15 93354 152 010 SOCKET IC 821551 1 PLCC AMP 2 U33 77 93354 168 060 SOCKET IC 68P 821689 1 AMP PLCC 2 5 1 93354 905 520 SOCKET EMC 550 113 121 TEKCON 1 L7 9 94049 903 160 FERRITE BEAD 2943666671 3 L10 24 94049 903 160 FERRITE BEAD 2943666671 2 L1 6 94049 903 941 FERRITE BEAD SMD 2743019447 F R 6 L11 23 94049 903 941 FERRITE BEAD SMD 2743019447 F R 13 Y3 94539 066 670 OSC NETWORK NSA0184 66 67MHz 1 Y4 94539 911 810 OSC CLOCK SCO 010K 24 0000 MHz SUNNY 1 Y1 94539 915 380 OSC
50. 4 5 506840 1 0 55055 gt ETE 152 gt 2 192 gt 221 Ci PI EC Q Bie Ft bye 3 SAMSUNG ELECTRONICS itle DESKTOP 386 I O CONNECTORS 6 7 DHG c 90 3 371 50 5 4 LE lt ra II RP 16 LLEENESZ Rt p cp 1 ES 82 deo rete as4 SEE CER Z by Ra ISO SIP4 IL R2 a J R2 Se H R3 LL BCA RIE TT ttt 82 pe eR 11 CASTS 6 PEE SG SN I 1 1 9 R a so RG 150 5 4 D CECAST 0 LL 150 5 4 pee PART LIST 285 PART LIST Location No Part No Description Specification Q ty 99112 840 000 ASSY MOTHER B D 33MHz SD840 STANDARD 1 R33 91012 165 030 R CARBON SMD 18 100 ROHM 1 R30 91012 165 031 R CARBON SMD MCR18J151TA ROHM 1 R46 91012 165 042 R CARBON SMD 18 680 ROHM 1 R3 4 91012 165 221 R CARBON SMD MCR18J221TA 3 R11 13 91012 165 221 CARBON SMD MCR18J221TA ROHM 2 R27 39 91012 165 221 R CARBON SMD MCR18J221TA ROHM 2 R35 56 91012 165 221 R CARBON SMD MCR18J221TA ROHM 2 R50 51 91012 165 221 R CARBON SMD MCR18J221TA ROHM
51. 500k C2B 0 015 250 300k C2A 0 033pF Filter Values when Using 250 300 and 500 kb s 500k C2B 00274F 5600 1000pF 5 6kQ 250 300k C2A 0 047uF 5600 Filter Using Only One Data Rate 1 0M C2 00124F 5600 510pF 5 6kQ 500k C2 00274F 5600 1000 5 6kQ 300 250k C2 00474F 5600 2000 5 6kQ These values are preliminary and thus are subject to change Table 13 2 Data Rates MFM Versus VCO Divide By Factor Data Rate N 1 Mb s 4 500 kb s 8 300 kb s 16 250 kb s 16 1343 PLL Diagnostic Modes In addition the DP8473 has two diagnostic modes to enable filter optimization 1 enabling the Charge Pump output signal onto the PUMP PREN pin and 2 providing external control of the Read Gate signal to the data separator Both modes are enabled in the last byte of the Mode Command The Pump output signal indicates when the charge pump is making a phase correction and hence whether the loop is locked or not The Read Gate function when enabled allows the designer to manually force the data separator to lock to the incoming data or back to the reference clock This enables easy verification of the lock characteristics of the PLL by monitoring the FILTER pin and the Pump signal 196 DP8473 Floppy Disk Controller OPERATION COMPLETED NOT WAITED 6 BITS NOT 3rd ADDRESS MARK PREAMBLE Figure 13 6 Read Algorithm State Diagram for Data 1344 PLL Filter Design This section provides
52. 8 bit mapping is selected the upper addresses produce a 0 and accesses are disallowed to I O locations 90h to 9Fh MO Ui Reserved Always program to 0 Reserved Always program to O Reserved Always program to 0 Figure 8 22 INDEX43h Serial Paralle and Mapper Select 119 Configuration Registers of the GCK131 Chip Set INDEX43h Extended DMA 16 bit page mapping Mapping Mapping Address Address Operation A16 23h 24 31 DACKO 87h 97h DACK1 83h 93h DACK2 81h 91h DACK3 82h 92h DACK5 8Bh 9Bh DACK6 89h 99h DACK7 8Ah 9Ah REFRESH 8Fh 9Fh All thirty two 8 bit registers between 80h and 9Fh can be written and read back If 8 bit mapping is selected in the Configuration Register then A24h to produce 00 and no access is allowed to the registers at 90h to 9Fh The mapped addresses are during DMA and REFRESH cycles driven on ATA16 to ATA19 and also on LAT7 to LA31 Figure 8 23 INDEX43h Extended DMA 16 bit Page Mapping INDEX44h Video external register strobe Default value 00h A WRITE to this port clocks data to an internal register of the GC131 Peripheral Controller It also strobes csvnEG The external strobe is intended to clock the data into the actual register and thus mimic the configuration switches on the video board When this port is read data inside the GC131 Controller is driven onto the data bus I
53. CAS active Six CAS active Eight CAS active H H Cc Four RAS precharge CLKINs Six RAS precharge Zero recovery time Two recovery CLKINs Figure 8 7 INDEX05h DRAM Timing for BANKS 4 and 5 105 Configuration Registers of the GCK131 Chip Set INDEXO06h to INDEX09h Tailor timing requirements The configuration registers INDEXO06h through 09h are available to tailor the timing requirements for various system commands Delays are given as CLKIN cycles On the following pages Figure 8 8 through 7m for configuration registers INDEX06h through 09h indicate various delays These delays are multiples of CLKIN cycles Figure 8 9 diagrams their relationships CLKIN IADS READY ICOMMAND Next Operation Command Command Recovery Delay Active Time Figure 8 8 Cycle Timing as Referenced in INDEXO6h to 09h 106 Configuration Registers of the GCK131 Chip Set An example Objective In this example we wish to match the I O timing of the GCK131 Chip Set operating at 25MHz with a generic system that uses the AT standard running at 8 2 At standards As a first step the generic I O timing values of the AT are used to give values useful in programming the GCK131 Chip Set Figure 8 9 illustrates these relationships BUSCLOCK ALE ADDRS CMD Recovery Time Figure 8 9 Generic AT System I O Timing 3 Wait States i Wit
54. CLOCK SCO 020K 32 0000 MHz SUNNY 1 Y5 94539 915 400 OSC CLOCK SCO 010W 1 8432 MHz SUNNY 1 Y2 94539 915 910 OSC CLOCK SCO 010T 28 63636 MHz SUNNY 1 1 94709 902 710 PICO FUSE 251004 LITTEL 1 96674 905 710 SPRING CONTACT KBD PBSP T0 6 1 99112 840 021 ASSY DRAM PART 4MB 1MB 4 SD840 1 92109 369 011 IC DRAM MODULE KMM591000A 08 SEC 4 289 Location No Part No Description Specification Q ty 97094 130 062 SCREW PH M356 FE FZW W WASHER 3 COVER 97094 970 610 BOLT SPECIAL SUM24L NI PLATED 4 BEZEL 97154 230 081 SCREW PH 25 3XB FE FZY W WASHER 8 97624 904 069 KNOB POWER ABS 94V0 AF 303 1447 SISA 1 90742 185 069 RESIN ABS AF 303 1447 94VO BEIGE 0 00305 97624 904 510 KNOB RESET ABS 94VO AF 303 1447 SISA 1 90742 185 069 RESIN ABS AF 303 1447 94VO BEIGE 0 00265 97654 900 910 LENS LED ACRIYL SEMI CLEAR WHITE 1 99111 840 004 ASSY BOTOM SD840 STANDARD 1 STAND 94544 901 910 PLATE STAND R SUS304 10 3 2 STAND 94544 901 920 PLATE STAND L SUS304 10 3 2 STAND 95104 901 010 SHAFT STAND SUM24L FZW 2 STAND 95104 901 110 BOLT STAND SUM24L FZW 2 CHASS 96011 900 310 COVER TOP ABS 94VO AF 303 1447 1 CHASS 96642 900 010 STAND R ABS 94VO AF 303 1447 2 CHASS 96642 900 020 STAND L ABS 94VO AF 303 1447 2 STAND 96674 902 010 SPRING POWER SUS WPA P10 5 ST 35 2 STAND 96674 904 310 SPRING STAND SUS WPA 10 5 4 MBOARD 97088 130 062 SCREW BH M3 6 FE FZW 8 97094 130 062 SCREW PH M3 6 FE
55. Cycle 39 459 Cache Hit Cycle 2 ae pr 40 45 10 Cache Miss Cycle 41 CHAPTER 5 GC131 PERIPHERAL CONTROLLER 5d INTRODUCTION SEU RS 42 52 PERIPHERAL CONTROLLER OVERVIEW 42 521 Peripheral Controller Pinouts 9 43 H 5 2 2 HT131 Peripheral Controller Pin Descriptions 44 523 JO Address Map eedem escuche qu etaed tes 54 5 24 Port 8255 PPI Register Address 61h ss 55 5 2 5 NMI Mask Register Address 70h 55 526 Memory Mapper Page Registers 56 CHAPTER 6 CPU MEMORY CONTROLLER 6 1 63 64 6 5 6 6 6 7 68 6 9 INIRODUC TION gt isis epa beads 57 GC132 CPU MEMORY CONTROLLER OVERVIEW 57 6 2 1 2 CPU Memory Controller Pinouts 59 6 2 2 2 CPU Memory Controller Pin Descriptions 60 PROGRAMMING THE CONFIGURATION REGISTERS 69 631 Reconfiguring the Memory Map 69 6 3 2 MBEN and Non DOS Operation 72 6 3
56. DESCRIPTORS Defines those memory addresses that are not be stored in the cache ENABLE DISABLE NONCACHED REGIONS Turns on and off the noncached regions of memory ENABLE DISABLE CACHE Enable Disable caching of data from any address not declared as noncachable ENABLE DISABLE DIAGNOSTIC MODE Enable the cache SRAM to be used as local RAM Also puts the cache into a mode where the contents of the tag RAMs can be read out SET CACHE OPERATING MODE Sets the current operating mode i e level of associativity cache size etc 94 1 Programming Overview The A38202 can execute a number of instructions To program the A38202 it is accessed as an device When I O cycle occurs with the IOCS input asserted the A38202 assumes that the cycle is a register read or write cycle The A38202 takes up 8 locations in the 80386 I O address space These locations are on a quadword 8 bytes boundary However only the first and fifth locations can actually be read or written within the 8 bytes This is because the data lines on the A38202 connect to only the low 8 bits of the 80386s data bus A2 is used to select between the high and low locations 141 Registers within the A38202 are accessed by a register indirect method First the address of the register to be read or written is written to the low I O location assigned to the A38202 i e IOCS is asserted and A2 is low Then the contents of that register can
57. EID xs CFTEY OS gt MERE gt 10K R63 10K 1 2 SELECT FLOPPY 3 4 SELECT IDE qi 4 2 k 5 0658 220 HEADER 2 HOD LED CTURES 1 bCLK c a 74 574 B gt SAMSUNG ELECTRONICS Title DESKTOP 386 CIDE HARD DISK INTERFACE Document Number SD840_27 DWG Q 278 Gore gs gt 491 gt Toro 417 gt IST gt lt 9 71 gt gt 2 20 gt gt 279 gt CARE JS gt RESTI wes gt CATAT T 131 gt SCE i e xal 42 222 gt CERCEI STI CERO 844 684 ci t sts 63 Q 0900000000 bi O O lt gt 21 gt CATER 131 gt i exa 221 beg RENG 1 IIIT 9 b Pai LLL A 46 r 74 gt CREO gt BACE gt gt lt esd gt CATALOG 131 gt COGO a4 URI III gt CERI gt 72 gt 8s 10 vt TL IL 1 UN 8 Q DEO lt 38 T wawan bed 4 s m m O O t tp D O D D O D i 60000000 0 SAMSUNG ELECTRONICS DESKTOP 386 CONNECTORS
58. ELECTRONICS gt 271 Ea ER A A k 3 gt Ny em EID E lt SBMALO 914 BPDLO 3 al lt ECASS TO PPE Pi lt ERASS J CES OBR ji q tt 3 5 a 5 BMA d 5 erie q TE d 82027 d OMA E BP 4 5 8 4 BPD 4 29 d 521126 Hur 928 CENA LT gt VCC O SAMSUNG ELECTRONICS 272 SAMSUNG ELECTRONICS 273 2N2222 CERI 191 et AED GIET SII gt ISI gt 771 gt 22 gt BL THUXAZQ gt SEO gt SPERKER P11 P12 Pia 5 P16 P1 P20 P21 P22 P23 P2470 P2571 P26 QR 27 SYNC KYBD LOCK POWER LED CRT SW 95 0 09 eno LED PWR JUMPER KEY GND KYBO INH GND ADER 5 47PF 47 3tURN BEAD 5 124 3TURN BEAD F1 SA PICO 274 C166 C16 47PF 47PF COPTEUPFFULL IET SAMSUNG ELECTRONICS HEADER 2x2 itle SE SUPPORT DESKTOP 386 KYBD MOUSE CONTROL gt OU 2 4 MOUSE INSTALLED Document Number MOUSE OISABLED 0840_23 0NG PuRGOODN gt EAT 0 221 gt CRTCIRSN RATOU 4j 051287 RS 10K SRMSUNG ELECTRONICS 275 gt 5 51 SERCS28 PARCS a
59. Elapsed Time 03 39 21 In Manual mode you can test every function manually MENU system has a hierachical structure Pass Fail System Board Fixed Disk Parallel Port Serial Port A 3 2 How to Select Each MENU The MENU has a hierachical structure ux At first CURSOR is located at position Now you can move this CURSOR position by using lt CURSOR LEFT RIGHT gt keys To enter SUB MENU press lt Enter key or PCURSOR DOWN gt key gt And also you can enter SUB MENU directly by pressing corresponding function key lt F1 gt lt F8 gt e To return previous MENU press lt Esc key lt CURSOR UP gt Key Select brings same effect 219 Diagnostic AA DESCRIPTION OF MANUAL TEST MODE If you select on MAIN MENU you can see next screen Current Time 12 15 28 Elapsed Time 03 39 21 AT System Diagnostics Version 2 00X Copyright C SAMSUNG Electronics Co Ltd 1990 Diagnoses ROM RAM CMOS RAM and Speaker end Pass Fail Parallel Port In this mode you can test every function manually If error detected during test error message will be displayed on screen If you want to save this eror status press Y If don t want press lt N gt or Esc key AGN Menu 1 HERO It tests Checksum of System BIOS ROM F000 0000 FFFF and Additional System B
60. ICI E 156 1051 Diagnostic Status Byte ER mete nnn 157 10 5 2 Shutdown Status Byte OFH 158 1053 Floppy Disk Drive Type Byte 10H 158 1054 Fixed Disk Type Byte 12H se vac ieee UW Rh sad 159 10 5 5 Equipment Byte 159 1056 Low and High Base Memory Bytes 15H and 16H 160 1057 Requested Low and High Memory Expansion Bytes 17 and 18 160 10 5 8 Drive C Extended Byte 19H e ae 160 1059 Drive D Extended Byte sss 161 10 5 10 Feature Installed Byte FH 161 105 11 CMOS RAM Checksum EH 2FH 161 10 5 12 48 Parameters 20H 27H 162 10 5 13 Shadow and Enter Setup 28H 162 10 5 14 Actual Low and High Extended Memory Bytes 30H and 31H 163 10 5 15 Date Century Byte 32H 163 10 5 16 Setup Information 33H 163 10517 CPU Speed MH 0 Raa e 164 10 5 18 Type 49 Parameters 5 164 CHAPTER 11 COMMUNICATION PORTS TT INTRODUCTION md X DESEAS mo As 165 11 2 SERIAL COMMUNICA
61. In case of Diskette the actual code sequence is lt F4 gt lt F1 gt lt F1 gt lt F8 gt lt F3 gt lt F1 gt which corresponds to diagram below FDD FDD Reset gt T EXE if you delete only test procedure will be as follow 1 oD l t 5 gt gt gt b So if you are to delete a test module you must delete upto LABEL 2 Insert procedure Move CURSOR to position you want to insert and press Ins key then undefined procedure like will be inserted Now you can define this LABEL as you want 29982 Diagnostic 6 2 How to Define or Change Procedure Already Defined 1 Move CURSOR with lt CURSOR KEY gt and select item you want to Edit 2 Press SPACE BAR 3 Then control key menu is changed as following Control Keys gt Select Item Space Enter Change Item Esc Exit 4 Move CURSOR to position and press SPACE BAR ENTER key 5 Then selected item will be changed 63 Exit Editor 1 Press Esc in Ins Del mode 2 If you want to save press lt Y gt key w LABEL is usd by system and cannot be deleted LABEL is used by system also and can be deleted This LABEL is used for adjust Auto procedure when Diagnostics is booting for example Kill Dry B test procedure when B is not installed But edited procedure is not adjusted automatically 229 Diag
62. It also isolates the operating system and enforces protection rules necessary for remaining task integratin a multitasking environment This is useful in a multitasking and multiuser environment where resources are shared Protected mode provides memory pasing I O protection virtual 8086 mode and a full 32 bit extended instruction set Protected mode provides source code compatibility with the 8086 8088 and 80286 allowing direct execution of 16 bit applications at higher speeds 3 3 3 Virtual 8086 Mode The virtual 8086 mode is an extention of the protected mode Under this mode the CPU provides compatibility with applications developed for the 8086 8088 while simultaneously peoviding a full 32 bit large linear address programming environment in its protected mode Virtual memory allows programs to overcome the limitation of physical memory The system divides virtual memory into amny different segments These segments are mapped into physical memory during virtual memory execution The memory management system transfers code and data between physical memory and disk 3 34 CPU Signals The following text defines the signal functions of the CPU A signal name followed by an T in parentheses indicates an input signal A signal name followed by an 0 in parentheses indicates an output signal A signal name followed by I O in parentheses indicates an input output signal For more detailed information on the CPU signal functions
63. LOW from upper to lower Bus Bridge Direction 1 Controls the direction of data flow from the processor side to the AT side When HIGH data flows from the processor to the AT data bus During an I O write BBDIR1 77 When LOW data flows from the AT side to the processor side During an read BBDIR1 407 BBENO to 154 I Bus Bridge Enable When active indicates the byte that BBEN3 151 the HT133 should drive where is the lowest order byte and the highest For example an byte READ from port 0 has BBENO active HT133 drives data onto the processor s data bus lower byte from the AT data bus lower byte 0 92 GC133 Bus Bridge Interface Pin Pin Symbol Number Pin Type Description BBEN4 150 CLK646 155 CONFIGAS 44 CONFIGDR 42 CONFIGDW 43 118 IEXRAS0 72 73 1 HLDA 70 IINTA 115 Bus Bridge Enable 4 When active enables the bridging buffer between ATD0 7 and ATD8 15 This routes the data from lower to upper bytes on the AT data bus and viceversa Clock LS646 Megafunction On the rising edge of this signal HT133 latches data on lines ATD0 7 and if the direction and SAB646 is correct presents the data to the processor s lower 8 bits Configuration Address Strobe The new configuration INDEX is strobed on the trailing edge of this signal Configuration Data Read If the INDEX is set within the range 10h to 1Fh
64. MONO CERAMIC SMD 12065C104KATO60R AVX 5 C76 79 91301 104 756 C MONO CERAMIC SMD 12065C104KATO60R AVX 4 C81 82 91301 104 756 C MONO CERAMIC SMD 12065C104KATO60R AVX 2 C84 92 91301 104 756 C MONO CERAMIC SMD 12065C104KATO60R AVX 9 C94 98 91301 104 756 C MONO CERAMIC SMD 12065C104KATO60R AVX 5 C100 9 91301 104 756 C MONO CERAMIC SMD 12065C104KATO60R AVX 10 C110 8 91301 104 756 C MONO CERAMIC SMD 12065C104KATO60R AVX 9 C123 9 91301 104 756 C MONO CERAMIC SMD 12065C104KATO60R AVX 7 C130 4 91301 104 756 C MONO CERAMIC SMD 12065C104KATO60R AVX 5 C136 9 91301 104 756 C MONO CERAMIC SMD 12065C104KATO60R AVX 4 C140 9 91301 104 756 C MONO CERAMIC SMD 12065C104KATO60R AVX 10 C150 9 91301 104 756 C MONO CERAMIC SMD 12065C104KATO60R AVX 10 C170 2 91301 104 756 MONO CERAMIC SMD 12065C104KATO60R AVX 3 C165 91301 104 756 C MONO CERAMIC SMD 12065C104KATO60R AVX 1 C168 9 91301 104 756 C MONO CERAMIC SMD 12065C104KATO60R AVX 2 C173 9 91301 104 756 C MONO CERAMIC SMD 12065C104KATO60R AVX 7 C180 2 91301 104 756 C MONO CERAMIC SMD 12065C104KATO60R AVX 3 171 91301 273 156 CERAMIC SMD 12065E2 3ZATO50R AVX 1 C186 7 91301 331 650 C CERAMIC SMD 12065A331JATOO50R AVX 2 C189 91301 331 650 C CERAMIC SMD 12065A331JATOO50R AVX 1 C191 2 91301 331 650 C CERAMIC SMD 12065A331JAT0050R AVX 2 194 5 91301 331 650 C CERAMIC SMD 12065A331JATOO50R AVX 2 C197 91301 331 650 C CERAMIC SMD 12065A331
65. Number Type FAST SLOW 130 I HLDA 53 I INT 46 IINTA 48 I IIOCHCK 4 I IOCHRDY 52 I 158 TOW 159 to 24 35 IRQZ IRQ9 to IRQIS FAST SLOW clock speed select from 8042 Keyboard Controller SLOW indicates a 7MHz clock speed and FAST indicates 33MHz Hold Acknowledge Indicates that the CPU is no longer driving the buses Used in the DMA controller section Interrupt Request to the CPU from the 8259 Interrupt controller in the HT131 Controller Interrupt Acknowledge Decoded from CPU STATUS by the HT132 Controller INTA instructs the HT131 Controller to place the interrupt vector to the CPU on the system data bus Channel Check When active the backplane is indicating that a PARITY check occurred on a backplane memory board Channel ready When LOW the current cycle is extended in multiples of the CLOCK signal until IOCHRDY is released IOCHRDY will extend CPU DMA and REFRESH cycles I O Read Normally an input except during a DMA but not a MASTER it is driven by the DMA Controller I O Write Normally an input except during a DMA but not a MASTER it is driven by the DMA controller Interrupt Requests Interrupts from the I O channel indicate that an external peripheral on the backplane is requesting service by the CPU These inputs are used by the 8259 Interrupt Controller in the HT131 Controller Priorities decrease from IRQ9 to IRQ15 and then from IRQ3 down to I
66. Optional Configuration 1 INDEX OEh Optional Configuration 2 INDEX OFh Optional Configuration 3 Registers of the HT133 Bus Bridge Interface INDEX 10h DRAM configurations INDEX 11h Reserved INDEX 12h Reserved INDEX 13h Revision identification Registers of the HT131 Peripheral Controller INDEX 40h Clock dividers for low speed INDEx 41h Clock dividers for high speed INDEX 42h DMA and REFRESH wait states INDEX 43h Serial parallel and mapper selections INDEX 44h Video external register strobe INpEx 45h EEPROM Control INDEX 46h Reserved INDEX 47h Revision identification INDEX 48h Reconfiguration INDEX 49h Additional REFRESH Wait states INDEX 92h Port Fast Rc and ALT PA20 99 Configuration Registers of the GCK131 Chip Set INDEX00h General setup bits Default value 00h The configuration bits of INDEXOOh are available for programming general system setup Coprocessor Bits 0 and 1 Bit 0 toggles to enable or disable the numeric coprocessor if installed The default Bit 0 0 applies if the system is not fitted with the device Use Bit 1 to indicate the device type The default Bit 1 0 indicates an 80387 device If an 80287 is fitted Bit 1 is set equal to T Parity check Bit 3 The default setting Bit 3 0 selects parity checking OFF DRAM banks 4 and 5 As required to match the installed devices use
67. REMAP LB VB MB ofRAM DRAM 0 1 2 3 4 5 Available SHADOW SHADOW SHADOW 1Mb 1Mb 256K _ _ _ _ Yes Yes Yes No 2Mb 2Mb 256K 256K _ _ _ _ Yes Yes Yes No 4Mb 3 64Mb 256K 256K 256K 256K _ _ No Yes Yes No 6Mb 5 64Mb 256K 256K 256K 256K 256K 256K No Yes Yes No 4Mb 4Mb 1Mb _ _ _ Yes Yes Yes No 8Mb 7 1Mb No Yes Yes No 16Mb 1564Mb 1Mb 1Mb 1Mb _ No Yes Yes Yes 24Mb 2364Mb IM 1Mb 1Mb 1Mb 1Mb 1Mb No Yes Yes Yes Figure 6 6 Summary of Available DRAM Configurations 79 GC132 CPU Memory Controller 6 6 1 One Bank of RAM This the single bank of installed RAM is a special case because it is the only situation in which interleaving does not occur At least two banks are required for interleaving The memory map for the single and double banks of installed RAM is illustrate in Figure 6 7 For clarity the RAM shadowing REMAP and the EMS hole features described later in this Chapter are disabled With 256K DRAMs the memory capacity is 1 but due to the definition of the AT memory map only the first 640K is reachable The rest is defined as backplane memory If nothing is done to change this situation the DRAM residing from 640K to 1Mb is wasted If IMb DRAMs are installed the memory capacity is 4Mb but again the 384K above 640K is wasted See the REMAP Section The ATLAS Chip Set has allotted within it two shadow regions between 640K and 1 These are described in the previous Se
68. Reserved 1BH Reserved 1CH Reserved 1DH Reserved 1EH Features installed reserved 1FH Drive type 48 parameters 20H 27H Options 1 28H Reserved 29H Reserved 2AH Options 2 2BH Options 3 2CH Reserved 2DH 2 byte CMOS RAM checksum 2EH 2FH Low expansion memory byte 30H High expansion memory byte 31H Date century byte 32H Setup information 33H CPU speed 34H Drive type 49 parameters 35H 3CH Reserved 3DH 3FH 10 3 1 Time Calendar and Alarm Bytes The CPU obtains time and calendar information by reading the appropriate locations in the RIC Writing to these locations initializes the time calendar and alarm information Information stored in these locations is in binary coded decimal BCD format Before initializing the internal registers the set bit in register B must be set to 1 to prevent RTC updates Once set the CU initializes the first 10 locations in BCD format and the set bit is cleared Once initialized and enabled the RIC performs clock calendar updates at a 1Hz rate During updates the 10 bytes of time calendar and alarm information are not available for reading or writing by the CPU for 2 ms Table 10 2 lists the format for the 10 clock calendar and alarm locations System software sets the RIC to BCD data mode 152 1287 Real time Clock RTC Table 10 2 Time Calendar and Alarm Data Format Function Index BCD Data Seconds 00 00 59 Seconds alarm 01 00 59 Minutes 02 00 59 Minute alarm 03 00 59 Ho
69. and the ability to use operating systems other than DOS Compatibility with the AT Design The AT design maintains upward compatibility with the earlier XT design In consequence the memory map of an XT system can be described as a sub set of an AT memory map Because the XT design is limited to a memory space of one megabyte only that amount the lower 1Mb of the AT s memory map must satisfy the needs of compatibility The remainder a further 15Mb is called backplane memory A small area of this upper memory is reserved for a mirror image of BIOS needed for the RESTART vector is located at the top of the four gigabytes of 80386 memory 68 GC132 CPU Memory Controller EPROM Memory Map The needs of compatibility require the EPROM BIOS or Lower BIOS at F0000h through FFFFFh and for system start Upper BIOS is located at FFFF0000h See Figure 6 3 But modifications can be made to the memory map as explained in the following pages using these tools MBEN is a device used to regulate the memory space associated with a copy of BIOS called Middle BIOS MBEN when disabled frees this memory space when operating systems non DOS do not require BIOS in this memory region MBEN acts within an area of memory described as Window 3 LBSHADOW is a device used to implement a 32 bit rather than a 16 bit version of BIOS called Lower BIOS located within an area of memory described as Window 2
70. be read or written by performing the appropriate read or write I O cycle to the high I O location i e IOCS is asserted and A2 is high Table 9 2 shows what value must be written to the address register to access each register within the A38202 Table 9 2 A38202 Register Addresses 5 Address Register 00H Control Register 04H Configuration Register 08H Status Register 10H Noncache Control Register 20H 22H Noncache D0 Buttom Register LSB to MSB 24H 26H Noncache D0 Top Register LSB to MSB 28H 29H Noncache D1 Bottom Register LSB to MSB 2CH 2DH Noncache D1 Top Register LSB to MSB 30H 31H Noncache D2 Bottom Register LSB to MSB 34H 35H Noncache D2 Top Register LSB to MSB All other addresses are reserved to Austek and should not be used Writing to those addresses may cause unpredictable results Note All bits in registers which are undefined are reserved to Austek and should always be written as 0 142 94 2 Control Register The control register shown in figure 9 4 determines the major operating modes of the A38202 The register contains 7 bits defined for control of operating modes Figure 9 4 Control Register The defined CONTROL REGISTER bits are described as follows D Enable disable diagnostic mode bit 0 If enabled 1 it forces the microcache to map the 32kB to 128kB of cache RAM into normal system memory addr
71. begins processing the new command immediately Note The reset wrap mode ECH and reset FFH commands are exceptions to mouse acknowledge response The mouse does not respond with an acknowledge to either of these commands RESEND FEH The mouse replies with a resend when it receives an invalid command from the system Two invalid commands in succession cause the mouse to send the error code FCH to the system A single isolated invalid command does not affect mouse processing in any way The mouse ignores single invalid commands and maintains its present operational state 183 DP8473 FLOPPY DISK CONTROLLER 13 1 INTRODUCTION This device is a derivative of the DP8472 4 Floppy Disk Controller which incorporates additional logic specifically required for an IBM PC PC XT PC AT or PS 2 design This controller is a full featured floppy disk controller that is software compatible with the PD765A but also includes many additional hardware and software enhancements This controller incorporates a precision analog data separator that includes a self trimming delay line and VCO Up to three external filters are switched automatically depending on the data rate selected This provides optimal performance at the standard PC data rates of 250 300 kb s and 500 kb s It also enables optimum performance at 1 Mb s MFM These features combine to provide the lowest possible PLL bandwidth with the greatest lock range and h
72. connected to this bus it is intended solely as a high speed interface The ATA and ATD Bus The ATA and ATD bus provides the address and data requirements of the XT AT expansion bus This bus a local to the GC131 Peripheral Controller the GC133 Bus Bridge Interface and the AT expansion bus has a data width of 16 bits and the 24 bits of addressing that is required for AT standards The upper address bits required for the AT expansion bus are supplied by buffering the PA17 to PA23 lines of the PA bus These with ATAO to ATA19 provide the necessary addresses for proper connection to the AT expansion bus The ATA and ATD bus which generally operates at a slower speed than the PA and PD bus allows the connection of all types of peripheral devices to the GCK131 supported AT system To transfer data between the high speed PD bus and the slower ATD bus the GC133 Bus Bridge Interface is used at appropriate times 89 GC133 Bus Bridge Interface ATA SAB646 PN E CLK646 Data IBBENO 4 buffer BBDIRO 1 a bus ATDO 15 bridge PD0 31 HLDA IINTA PBEN and low order BALE ATA LBHE generation IPBEN0 3 HLDA PA Address IMASTER 2 19 CONTROL Memory REFRESH address ADDRSEL MUX 11 IRAS0 3 EXRASO 1 PGVIOL Page mode violation detection latch 2 24 BALE 2 19 21 24 SPA20 CONFIGAS
73. controller Drive Control Register and Data Rate Register see Table 13 3 for the memory map using the same address map as is used in the XT AT or PS 2 The decoding is provided for A0 A2 so only a single address decoder connected to the chip select is needed to complete the decode The bus interface logic includes the 8 bit data bus and DRQ INT signals The output drive for these pins is 12mA Table 13 3 Address Memory Map for DP8473 A2 A1 A0 R W Register 0 0 0 X None Bus Tri State 0 0 1 X None Bus Tri State 0 1 0 W Drive Control Register 0 1 1 X None Bus Tri State 1 0 0 R Main Status Register 1 0 1 R W Data Register 1 1 0 X None Bus Tri State 1 1 1 W Data Rate Register 1 1 1 R Disk Changed Bit When this location is accessed only bit D7 is driving all others are head TRI STATE 199 DP8473 Floppy Disk Controller Drive Control Register This 8 bit write only register controls the drive selects motor enables enable and Reset See Register Description Reset Logic The reset input pin is active high and directly feeds the Drive Control Register and the Data Rate Register After a hardware reset the Drive Control Register is reset to all zeros and the Data Rate Register is set to 250 kb s data rate The controller is held reset until the software sets the Drive Control reset bit after which the controller may be initialized A software reset to the controller core can be issued by resetting then set
74. described in Table 10 11 Table 10 11 Equipment Byte 14H Bit Function 7 6 Number of floppy disk drives installed 00 1 drive 01 2 drives 10 Reserved 11 Reserved 5 4 Type of video display controller used 00 Extended functionality controller 01 Color graphic video display controller in 40 column mode 10 Color graphic video display controller in 80 column mode 11 Monochrome display controller 3 2 Not used 1 Presence of a numeric coprocessor 1 Numeric coprocessor installed 0 No numeric coprocessor 0 Presence of floppy disk drive 1 Floppy disk drive installed 0 No floppy disk drive 159 1287 Real time Clock RTC 10 5 6 Low and High Base Memory Bytes 15H and 16H Table 10 12 Low and High Base Memory Bytes 15H and 16H Bit Function 7 0 Address 15H low byte base size 7 0 Address 16H high byte base size 0100H 256K RAM 0200H 512K RAM 0280H 640K RAM 10 5 7 Requested Low and High Memory Expansion Bytes 17 and 18 This word indicates the total amount of expansion memory above 1M set by the system configuration program Table 10 13 Low and High Memory Expansion Bytes 17H and 18H Bit Function 7 0 Address 17H low byte expansion size 7 0 Address 18H high byte expansion size 0200H 512K RAM expansion 0400H 1024K RAM expansion 0600H 1536K RAM expansion 3C00H 15360K RAM expansion 10 5 8 Drive C Extended Byte 19H Tab
75. disk 2 Controller cannot read any Address Fields without a CRC error during Read ID command 3 Controller cannot find starting sector during execution of Read A Track command D1 Not Writable Write Protect pin is active when a Write or Format command is issued D0 Missing Address Mark If bit 0 of ST2 is clear then the disk controller cannot detect any Address Field Address Mark after two disk revolutions If bit 0 of ST2 is set then the disk controller cannot detect the Data Field Address Mark 13 6 3 Status Register 2 512 D7 Not Used 0 D6 Control Mark Controller tried to read a sector which contained a deleted data address mark during execution of Read Data or Scan commands Or if a Read Deleted Data command was executed a regular address mark was detected D5 CRC Error in Data Field Controller detected a CRC error in the Data Field Bit 5 ST1 is also set D4 Wrong Track Only set if desired sector not found and the track number recorded on any sector of the current track is different from that stored in the Track Register D3 Scan Equal Hit Equal condition satisfied during any Scan Command D2 Scan Not Satisfied Controller cannot find a sector on the track which meets the desired condition during Scan Command 205 DP8473 Floppy Disk Controller D1 Bad Track Only set if the desired sector is not found and the track number recorded on any sector on the track is different from that stored in the Track Regi
76. edge of the signal latch the data the INDEX pointer on the lower either data lines into the INDEX registers of each chip of the set CONFIGDW When the I O WRITE is made to port 28h CONFIGDW goes active high indicating that valid data is available on the lower eight bits of the data buses The target chip identified as having the INDEX register by the prescribed Region spaces noted earlier strobes the data to the appropriate configuration register on the falling edge of CONFIGDW CONFIGDR When the I O READ to port 28h occurs CONGIGDR goes active high and data will be presented to the lower eight bit of the data bus Only one chip responds the one whose INDEX register value matches with the proscribed range 98 Configuration Registers of the GCK131 Chip Set 83 THE INDEXES REGISTERS Summary of the INDEXES Registers of the HT132 CPU Memory Controller INDEx 00h General setup bits INDEX Olh General setup bits INpEx 02h High speed override bits INDEX 03h DRAM configuration INDEX 04h DRAM configuration Banks 0 1 2 3 INDEX 05h DRAM configuration Banks 4 5 INDEX 06h to INDEX 09h Tailoring timing requirements An Example AT standards INDEX 06h EPROM configuration INDEX 07h Channel RAM Configuration INDEX 08h access configurations INDEX 09h Interrupt acknowledge configurations INDEX Test registers INDEX Identification register INDEX ODh
77. features For more information contact your LSI Logic representative Bits State Description 7 to 0 02h Revision ID READ ONLY Figure 8 25 INDEX47h Revision Identification 121 Configuration Registers of the GCK131 Chip Set INDEX48h Mode reconfiguration Default value 00h The ATLAS Chip Set has enhanced features that allow the system designer an opportunity to redefine specific I O services at the Pin levels of the HT131 Peripheral Controller Bits State Description 0 0 Allow connection to discrete parallel ports When Bit 0 T When Bit 0 0 REDEFINED AS PCSRPA IPARCS IPCSWPA BFEN IPCSRPB BFDIR IPCSWPC IPCSRPC Not Connected PARIE To be strapped to VCC Enable direct connection with the 16C452 device or equivalent and provide on board I O buffer control signals 1 0 PORT92h functions disabled ENP92 0 When Bit 0 T When Bit 1 0 REDEFINED AS ATA17 FAST RC ATA18 TN ALT 20 ENP92 1 1 PORT92h functions enabled ENP92 Y NOTE Only MUXPA20 and FAST_RC are implemented See Timing Diagrams Figure 56 on the next page 2 0 CK8042 Pins Frequency 7 14MHz Nominal 1 CK8042 Pins Frequency 11 5MHz Nominal 3 0 16 bit I O decode selected 1 10 bit I O decode selected 4 56 7 0 Reserved Always program to 0 Figu
78. interrupt controllers PICs two 8237 direct memory access DMA controllers an integrated circuit containing three general purpose programmable interval timers PITs an LS612 and other devices The chip interfaces with an 8042 keyboard controller real time clock parallel ports serial ports speaker and the EEPROM used for power up configuration GC132 CPU Memory Controller This powerful chip decodes the processor address and control lines and generates RAS CAS and chip select signals required for memory management Both static and dynamic memories can be used The GC132 controller features both paged and interleaved memory access techniques that improve overall system throughput GC133 Bus Bridge Interface This chip links AT address and data buses the processor address and data buses and the memory bus 2 35 1051287 Real time Clock RTC The RTC provides 50 bytes of CMOS RAM and a battery backup power source for keeping system clock calendar and system configuration parameters in non volatile memory This protects the contents of both the RAM and the clock during system power up and power down 2 3 6 Input Output Expansion Slots The system has 8 I O expansion slots Two slots 7 J8 accept 8 bit expansion boards only Six slots J1 J2 J3 J4 J5 and J6 accept 16 bit or 8 bit expansion boards 237 Input Output Ports The system provides a parallel printer port configured as either LTP1 or LTP2 and serial communic
79. is 386 micro processor operationg at 33MHz with the speed of 30 3nS per clock cycle The CPU has seperate 32 bit data and address paths plus on chip memory management and protection The CPU supports multiuser and multitasking systems memory management virtual memory and task or memory isolation Refer to the rear of this manual for a list of Intel reference manuals that provide detailed information on the 386 microprocessor 134 Central Processing Core 3 3 1 Real Mode Architecture The CPU defaults to real mode upon reset Real mode is compatible with 8086 8088 and 80286 CPUs at the object code level and has the same capability and limitations In real mode addressable physical memory is limited to 1M via segment registers with 64K limitation on segment size Real mode does not provide memory protection features Real mode address are formed as in the 8086 by combining the base address from a segment register with the offset value procided by the instruction The CPU shifts the 16 bit base address value in the segment register left four bits and adds the 16 bit offset value forming 20 bit real address 3 3 2 Protected Mode Architecture Protected mode significantly increases the linear address space to 4 gigabytes and enables the running of virtual memory programs of almost unlimited size 64 terabytes In this mode the integrated memory management and protection mechanism tronslates virtual addresses to physical addresses
80. is the reset signal for the system This input signal suspends any operation in progress and places the 386 in a known reset state The 386 is reset by asserting RESET for 15 or more CLK2 periods 80 or more CLK2 periods before requesting self test When RESET os asserted all other pins are ignored RESET is level sensitive and must be synchronous to the CLK2 signal 3 3 5 Basic CPU Bus Operations The bus control unit manages all bus operations It generates the address data and command signals for external memory and I O operations The bus control unit also transfers instructions to the instruction pre fetch unit Instructions are stored in a 16 byte queue waiting for decoding and execution The execution unit does not need to wait for the completion of a bus cycle before accepting a new instruction This results in faster execution of instructions The instruction pre decode unit receives and decodes the instructions from the prefetch queue It places them in the decoded instruction queue for use by the execution unit The execution unit executes the basic processing functions It accepts the decoded instructions from the instruction pre decode unit and executes them It used the bus unit to fetch and store operands during the execution of instructions The address paging unit and segmentation unit provide memory management and protection services for the CPU These units also translate logical addresses into physical address for use the
81. of Available DRAM Configurations 79 The Effects of REMAP with One Bank of RAM 80 The Effects of REMAP with Two Banks of RAM 81 The Effects of REMAP with Four Banks of RAM 82 The EMS Holen uod dau a e HE SOS e 84 Connecting Four Banks of RAM 85 Connecting Six Banks of RAM 86 Connecting RAS Signals to the DRAMS 87 HT133 Bus Bridge Interface Block Diagram 90 HT133 Bus Bridge Interface Pinouts 91 gt INDEX001h General Setup Bits 100 INDEX01h General Setup Bis Continued 101 INDEX02h High Speed Override Bits 102 INDEX03h DRAM Configuration 103 DRAM Timing as Referenced in INDEX04 104 INDEX04h DRAM Timing 0 3 105 INDEX05h DRAM Timing for BANKS 4 5 105 Cycle Timing as Referenced in INDEX06h to 09h 106 Generic AT system I O Timing 3 Wait States 107 INDEX06h EPROM Configuration 108 INDEXOZh 16 Bit RAM Configuration
82. one PRA and up to a total of four SRAs and replying agents A PRA the 303 board itself is required in all implementations SRAs and replying agents are strictly optional 44 SIGNAL GROUPS The ISA bus contains seven groups of signals address data cycle control central control interrupt direct memory access DMA and power The bus signals can support a PRA which has an onboard DMA controller optional SRAs and replying agents providing DMA or I O memory expansion The input and output direction designations for each signal are referenced to the PRA 44 1 Address Signal Group The address signal group consists of signals driven by the requesting agent in order to specify both the addresses and data transfer width A 19 0 The A 19 0 Address bus signals are latched outputs driven by a requesting agent They represent the least significant 20 bits of a positive logic binary number defining a 1M address space A 19 0 become valid when BUSALE is asserted and they may be latched by replying agents on the falling edge of BUSALE A 19 16 are driven low during I O cycles During refresh cycles the PRA drives A 7 0 with the DRAM row address to be refreshed and drives A 19 8 to 0 25 ISA Bus Interface 23 17 The LA 23 17 Unlatched Address bus signals are driven by requesting agent These signals are not latched by the PRA However they are valid when BUSALE is asserted and they may be latch
83. overrides the previous command After the controller responds to the acknowledge code the keyboard initializes and performs the BAT After returning the completion code the keyboard defaults to scan code set 2 179 Keyboard and Mouse Controller 1244 System Io Mouse Commands The write to auxiliary device command D4H instructs the 8742 to transmit the next byte it receives to the auxiliary device All commands written to the mouse must be written must be preceded by the write to auxiliary device command to port 64H followed by the desired mouse command All mouse commands must be written to port 60H If the write to auxiliary device command to port 64H is not executed first all mouse commands will be directed to the keyboard RESET SCALING E6H The reset scaling command resets the scaling to 1 1 SET SCALING E7H The set scaling command sets the scaling to 2 1 This command can only be used when the mouse is in stream mode When in stream mode the current X Y coordinates values are converted to new values each time the sample period expires In 2 1 scaling the new relationship between the input and output values is as follows Input Output 0 0 1 1 2 1 3 3 4 6 5 9 gt 6 20xN SET RESOLUTION E8H The set resolution command is a two byte command The second byte also written to port 60H is interpreted as a resolution in counts per mm There are four possible resolutions The relationship between the
84. pet Hexen UNC 91094 409 3 6 Ul rid TT FOU AS 7 92 9 274 PETRE HO tj COVER e INCIDESCRIPTION 38 KNob POWLE 10 vel 291 INQIDESCRIPTION SEC CORD METERIAL OTY BRKT HDD 966 903 EGL 11 4 CHASSIS 96121 708 720 The 1 BRkT FDDO 96127 95 60 Eql Tho CHASSIS BACK 908 510 EGI Tiaj RKT PCE BE 6 21 905 410 EGI TIO CHASSIS CovER 9121 905 210 EGI Ti 2 BRETHOD BAN 16612 401 10 ERT BEZEL FRONT 4 414 40 ABS 164 ISMPS LAFOUT 7 747 94 4 1 2 3 4 5 10 HANDLE __ 2 990 016 DC A i 11 STAND IRA 96642 700 014 544 4 12 BRET NANOE 9668 EGITE 13 ANGLE 4 14 HOD BAR 4 409 610 EGL 510 ESI Ti z 15 BRXT Quibk 9 96612 408 430 EGETI gekr REAR got qio ESI Tual 37 cover rop 36ot 300 310 ABS 94 18 BRKT SPACER 96612 906 022 ERITI O BRKT Link q faz 951 39 GITIO gom ABST 1 9664 16 60 TI o 3 5 SHIELP RATE 14503 4 2 Qj
85. replying agents as two consecurtive 8 bit ISA bus cycles The PRA tri states D 15 00 during refresh operations 44 3 Cycle Control Signal Group The cycle control signals control the duration and type of cycles The group consists of six command signals two ready signals and three sinals which specify the cycle type The command signals define the address space memory or I O and the data direction read or write The ready signals modify the command pulse widths to lengthen or shorten the default cycle timings MEMR MRDC I O MRDC Memory Read Command is asserted when the requesting agent is ready for a replying agent to drive the data bus with the contents of the memory specified by LA 23 17 A 19 0 MEMR is identical in function to except that it is asserted only when the memory read access falls below 1M Eight bit agents will receive only MEMR The refresh circuity on the PRA asserts MEMR and MRDC during refresh cycles initiated by an SRA in control of the ISA bus 597 ISA Bus Interface MEMW MWTC MEMW Memory Write Command is asserted during a write cycle when the requesting agent is driving the data bus MEMW is identical in function to MWTC except that it is asserted only when the memory write access falls below 1M Eight bit agents receive only MEMW IORC IORC I O Read command is asserted when the requesting agent is ready for a replying agent to drive the data bus
86. same 765 compatible microcoded engine that is used in the DP8472 4 This engine consists of a sequencer program ROM and disk misc registers This core is clocked by either a 4MHz 4 8MHz 8MHz clock selected in the Data Rate Register Upon this core is added all the glue logic used to implement a or AT or PS 2 floppy controller as well as the data separator and write precompensation logic The controller consists of a microcoded engine that controls the entire operation of the chip including coordination of data transfer with the CPU controlling the drive controls and actually performing the algorithms associated with reading and writing data to from the disk This includes the read algorithm for the data separator Like the yPD765A this controller takes commands and returns data and status through the Data Register in a byte serial fashion Handshake for command status I O is provided via the Main Status Register All of the PD765A commands are supported as are many of the DP8472 superset commands 134 2 Data Separator The internal data separator consists of an analog PLL and its associated circuitry The PLL synchronizes the raw data signal read from the disk drive The synchronized signal is used to separate the encoded clock and data pulses The data pulses are de serialized into bytes and then sent to the P by the controller The main PLL consists of four main components a phase comparator a filter a voltage
87. should not be used 114 Configuration Registers of the GCK131 Chip Set INDEX10h DRAM configurations Default value 00h This configuration register is available for programming the number and type of DRAMs used the system See Note It is also used the enable or disable the REMAP and interleave options as programmed with Bit State Description 0 1 Bit 0 Bit 1 The combination of Bits 0 and 1 select the following 0 0 DRAMS are 256K BANKO through BANKS 0 l Reserved 1 0 Reserved 1 1 DRAMS are 1 Mb BANKO through BANKS 2 0 1 DRAM bank interleave OFF 1 2 4 or 6 banks of DRAM auto interleave ON 3 0 Disable 384K REMAP above 1 2 or 4 Mb 1 REMAP enable TC TTT lI Oo Reserved Always program to 0 Reserved Always program to 0 Reserved Always program to 0 Reserved Always program to 0 NO oe Figure 8 17 INDEX10h DRAM Configuration Note In conjunction with the setting of INDEX10h used to establish the use of either 256K or 1 Mb DRAMs INDEX03h must also be similarly programmed If not done the system will not operate properly INDEX11 RESERVED INDEX12 RESERVED 115 Configuration Registers of the GCK131 Chip Set INDEX13h Revision identification The contents of INDEX13h are available for use in programming when the objective is to determine the availability by reference
88. the 16 bit version The HT132 CPU Memory Controller arranges the READ and WRITE Operations in such a way that the ROM contents are duplicated in shadow RAM When the cloning operation is done the bootstrap routines switch the HT132 Controller into shadow mode The shadow memory windows are used in this manner During READ operations access is given to the shadow RAM During WRITE operations the HT131 Controller gives access to the ROMs but ROMEN the EPROM Enable signal remains inactive a technique to protect the shadow RAM All WRITE data operations are dumped into the proverbial bit bucket it s impossible to write to ROM 6 34 Four Memory Windows The ATLAS Chip Set accesses the system ROMs through four memory windows and as noted on the next page Window 1 can be split to accommodate either 32K or 64K Video BIOS Two variants of the four window definition are used one for each type of ROM chip used in the system The EPROMs canbe either Type 27256 Table 6 1 or Type 27512 Table 6 2 When EPROM Type 27512 is used Windows 2 3 and 4 are larger See Note Window Range Use 1 C0000h CFFFFh Video BIOS As noted in the next section this space can be further split into C0000h C7FFF7 C8000h CFFFFh 2 F0000h FFFFFh Lower BIOS 3 FF0000h FFFFFFh Middle BIOS 4 FFFF0000h FFFFFFFFh Upper BIOS Table 6 1 Memory Windows EPROM Type 27256 GC132 CPU Memory Controller
89. the controller s digital logic including all internal registers micro engine etc 189 DP8473 Floppy Disk Controller Symbol Function OSC2 CLOCK OSC1 GNDA FILTER FGND500 FGND250 DR3 RDATA DR2 PUMP PREN DRV TYP SETCUR One side of the external 24MHz crystal is attached here If a crystal is not used a TTL or CMOS compatible clock is connected to this pin One side of an external 24MHz crystal is attached here This pin is tied low if an external clock is used This pin is the analog ground for the data separator including all the PLLs and delay lines This pin is the output of the charge pump and the input to the VCO One or more filters are attached between this pin and the GNDA FGND250 and FNGD500 pins This pin connects the PLL filter for 500k MFM 250k FM b s to ground This is a low impedance open drain output This pin connects the PLL filter for 250k MFM 125k FM b s or 300k MFM 150k FM b s to ground This is a low impedance open drain output This is the same as DRO except for drive 3 The active low raw data read from the disk is connected here This is a Schmitt input This is the same as DRO except for drive 2 When the PU bit is set in Mode Command this pin is an output that indicates when the charge pump is making a correction Otherwise this pin is an input that sets the precomp mode as shown in Table VI If pin is configured as PUMP PREN is assumed high
90. this pin is refined as ALI MUXPA20 as described later in these Pin Descriptions See also PORT 92H on Page 78 AT Address Line 19 This line is driven only during DMA and REFRESH cycles and represent a copy of LA19 AT Data bus LOW byte The HT131 uses only 8 bit transfers for accessing its internal registers Buffered Address Latch Enable Connects with the HT132 BALE line Used to latch valid addresses and memory decodes from the CPU It indicates valid CPU or DMA address for the I O channel BALE is HIGH during Hold Acknowledge DMA REFRESH or MASTER cycles Redefined from PCSRPB On Board I O Data Buffer Directional Control used when the 16C452 Interface Mode that allows connection to discrete parallel ports of the 16C452 Interface is enabled by setting Bit 0 of INDEX48h See INDEX48h on Page 74 Redefined from PCSWPA On board I O Data Buffer Enable used when the 16C452 Interface Mode is enabled Bus Clock drives the backplane clock signal whose frequency is divided by the value set in the configuration register and output on this line See INDEX40h and INDEX41h on Page 65 GC131 Peripheral Controller Pin Symbol Pin Number Pin Type Description CK8042 CK8042 CKEEP CLK28I CONFIGAS CONFIGDR CONFIGDW CPUHRQ ICS287 146 145 151 14 132 134 133 64 153 Clock Driver Phase 1 Frequency 7 16 or 11 5 MHz Connec
91. two bytes 83ABH The keyboard responds to the read ID with ACK discontinues scanning and sends the two ID bytes The keyboard sends the low byte first followed by the high byte The keyboard resumes scanning following an output of the keyboard ID BAT COMPLETION CODE AAH Each time the system is powered up the keyboard performs a self test operation called the basic assurance test BAT The BAT consists of a keyboard processor test a checksum of the ROM and a RAM test Activity on the clock and data lines is ignored during BAT The keyboard sends an AAH command to the controller following satisfactory completion of the BAT Any other code indicates a keyboard failure BAT FAILURE CODE FCH If a BAT follure occurs the keyboard sends FCH discontinues scanning and waits for a controller response or reset ECHO EEH When the controller issues the echo command to the keyboard the keyboard sends EEH as a response to the controller ACKNOWLEDGE EAH The keyboard issues an acknowledge to any valid input other than an echo or a resend command If the keyboard is interrupted while sending an acknowledge it discards acknowleldge and responds to the new command RESEND FEH The keyboard sends the resend command when it receives an invalid input or any input with incorrect parity This command signals the controller to transfer the input again 176 Keyboard and Mouse Controller 124 3 Sending Data to the Key
92. update cycle Divider bits DV2 0 must not be cleared and the register B set bit must be cleared During an update the lower 10 registers are no available to the CPU The update cycle increments the clock calendar registers and compares them to the alarm registers An interrupt is issued if a match occurs between the two sets of registers with enabled allarm and interrupt control bits 103 RIC INTERNAL ADDRESSABLE LOCATIONS The 64 addressable locations in the RIC are divided into 10 bytes containing the time calendar alarm data four control and status bytes and 50 general purpose RAM bytes refer to Table 10 1 Table 10 1 also details the internal register RAM organization of the RTC Table 10 1 Real time Clock Address Map Function Index Seconds 00H Seconds alarm 01H Minutes 02H Minutes alarm 03H Hours 04H Hours alarm 05H Day of week 06H Date of month 07H Month 08H Year 09H Status register A OAH Status register B OBH Status register C OCH Status register D ODH Diagnostic status byte OEH Shutdown status byte OFH Floppy disk drive type bypte 10H Reserved 11H Fixed disk type byte 12H Reserved 13H Equipment byte 14H continued 151 1287 Real time Clock RTC Table 10 1 Real time Clock Address Map continued Function Index Low base memory byte 15H High base memory byte 16H Low expansion memory byte 17H High expansion memory byte 18H Drive C extended type byte 19H Drive D extended type byte 1AH
93. various memory translation and protection checks for each bus cycle see Figure 3 1 The CPU uses a 66 67MHz clock to control bus timing The CPU divided this clock by two producing the internal processing clock and determining the bus cycle speed 18 Central Processing Core SEGMENTATION UNIT PAGING UNIT BUS CONTROL ADDRESS EUS PI 32 Ti TEST UNIT s l INTERNAL CONTROL BUS 4 E 5 BARREL 8 SHIFTER ADDER STATUS 2 MULTIPLy FLAGS DIVIDE REGISTER c FILE ALU CONTROL CONTROL Figure 3 1 CPU Block Diagram 34 NUMERIC COPROCESSOR A 121 pin extended numeric coprocessor ENP socket installe on the system board accommodates either an Intel 80387 or Weitek 3167 numeric coprocessor Both use the same clock generator as the CPU and fully support signal double and extended precision operations The system board executes high speed methematical calculations logarithmic functions and trigonometric operations using the numeric coprocessors The numeric coprocessors operate syncronously with the CPU Both numeric coprocessors provide the CPU with additional data types register instructions and interrupts specifically designed to support high speed numeric coprocessing The register in the numeric coprocessor hold constants and temporary results generated during calculations These registers reduce memory access time and increase speed
94. with a resend FEH when it receives an invalid command from the system Two invalid commands in succession cause the mouse to send the error code FCH to the system A single isolated invalid command does not affect mouse processing in any way The mouse ignores single invalid commands and maintains its present operational state 183 Keyboard and Mouse Controller SET WRAP MODE This command sets wrap mode the mouse echo mode With the exception of the reset wrap mode ECH and reset mouse FFH commands the mouse will echo all data and commands received from the system SET REMOTE MODE F0H This command sets remote mode the mouse data can only be transmitted in reply to a read data command READ DEVICE TYPE F2H The read device type command reads the mouse ID byte The mouse returns a value of 00H to the read device command SET SAMPLING RATE F3H This command sets the sampling rate of the mouse The sampling rate is defined as the number of times per second that the system checks for mouse data This is a two byte command The set sampling rate command F3H must be followed by a second byte that represents the hex value of the sampling rate The allowable values are defined below Hex Value Sampling Rate OAH 10 samples second 14H 20 samples second 28H 40 samples second 3CH 60 samples second 50 80 samples second 64H 100 samples second C8H 200 samples second ENABLE The enable co
95. with the data available from the I O port specified by A 15 0 IOWC Write command is asserted during an I O write cycle when the requesting agent is driving the data bus and it is negated when a replying agent ust clock the data into the I O port specified by A 15 0 MCS16 I MCS16 16 bit Memory Cycle Select is asserted by a 16 bit memory agent to indicate to the requesting agent that a 16 bit cycle may be executed replying agents generate MCS16 based on a decode of LA 23 17 Timing requirements placed on MCS16 prevent use of the memory command signals MEMR MRDC MEMW MWTC is generation of MCS16 The requesting agent ignores MCS16 on I O cycles IOCS16 IOCS16 16 bit Cycle Select is asserted by a 16 bit I O agent to indicate to the requesting agent that a 16 bit cycle may be executed Replying agents generate IOCS16 based on a decode of A 15 0 Timing requirements placed on IOCS 16 prevent use of IOWC and IORC in generation of IOCS16 The requesting gent ignores IOCS16 on memory cycles IOCHRDY 1 IOCHRDY I O Channel Ready is an asynchronous ready signal from a replying agent It is negated to force the requesting agent to lengthen the bus cycle by inserting an integral number of wait states one half of an ISA bus SYSCLK period or 62 5us IOCHRDY must not be negated for longer than 1545 IOCHRDY is ignored by the PRA during zero wait state cycles 28 ee
96. 0 The Video BIOS can be copied to shadow RAM by writing it byte for byte back to itself the 32 bit version replaces the 16 bit When the cloning operation is complete high speed access of video BIOS routines in shadow RAM is activated by setting Bit 0 of INDEXOIh to T The physical memory used for shadowing the Video BIOS is located at CO000h CFFFEh See Video BIOS space in Window 1 can be split The system must have enough installed RAM to populate this region of the memory map 76 GC132 CPU Memory Controller 6 4 2 Window 2 Lower BIOS By default after startup the Window 2 memory space is a shadowed copy of the Window 4 address space Any READ operations cause access to the Window 4 space WRITE operations are directed to shadow RAM LBSHADOW Uses INDEX 00h Bit 6 In a manner similar to that of Video BIOS shadowing the bootstrap routine must copy the Lower BIOS back to itself the 32 bit version replaces the 16 bit When cloning is complete the program set Bit 6 of INDEXOOh to 1 that activates the use of the 32 bit Lower BIOS access The physical memory used for shadowing the Lower System BIOS is located at F0000h FFFFFh for Type 27256 EPROMs Location E0000h FFFFFh for Type 27512 EPROMs The system must have enough installed RAM to populate this region of the memory map 643 Window 3 Middle BIOS In a manner similar to the Video BIOS shadowing the bootstrap must copy the Middle BIOS ba
97. 02 to ignore 80387 and Weitek cycles not to buffer I O writes and to run in non pipelined mode The initial value of the configuration register 11H defines the caching mode to be a 2 way set associative 64kB cache The initial value of the noncache descriptors are set up to make 256kB from C0000H to FFFFFH of the 80386s address space noncachable descriptor D0 128kB from A0000H to BFFFFH descriptor D1 and 128kB from 80000H to 9FFFFH descriptor D2 Only descriptor D1 is enabled the initial value of the NONCACHE CONTROL REGISTER is 22H Table 9 4 Register Values after Reset Control Register Configuration Register Noncache Control Register 30H 22H 000COH OOOFFH 000 000BH 0008H 0009H Descriptor D0 Bottom Register Descriptor D0 Top Register Descriptor D1 Bottom Register Descriptor D1 Top Register Descriptor D2 Bottom Register Descriptor D2 Top Register 147 Ze S E EO E 5 5528 5259225 09032 00909 bolted 546 5 mmr 658952 55558050052 398286554 GND LOCAL NONCACHE COT BHOLD FLUSH L 23 BREADY CACHEFAULT 3 BURSTACK A31 L 23 PWRGOOD A30 lt CLKRESET A29 L 3 CLK2 A28 C O SMEMW A27 GNO A26 SAV 25 O 3 SA31
98. 160 VSS 20 33 Ground 60 101 141 68 GC132 CPU Memory Controller 63 PROGRAMMING THE CONFIGURATION REGISTERS This Section explains how the configuration bit registers can be used to optimise the EPROMs of an 80386 based personal computer system In this use the HT132 CPU Memory Controller s functions are particularly important The HT132 Controller operates in the 32 bit mode a to control the general bus timing relationships for RAM ROM and I O b to control the size of RAM and ROM blocks and c to adjust the system when using an 80287 or 80387 Coprocessor The configuration registers of the HT132 Controller are partitioned according to their duties One register set operates system timing another is concerned with system hardware and a third set configures the memory map Memory map reconfiguration Faster operation through shadowing plus the ability to establish either 32K or 64K Video BIOS space Startup configuration Multiple banks of DRAM Reclaim RAM with REMAPPING BIOS Patches Used to Implement Required Defaults A convenient method by which the defaults can be established for the 80386 Microprocessor and the computer system involves the use of a BIOS patch 63 1 Reconfiguring the Memory Map The memory map of the HT132 CPU Memory Controller is compatible with the AT specification And in addition the controller has features that allow greater memory capacity improved performance
99. 38 92109 542 444 IC TTL SMD 74F244SC NS 1 U43 45 92109 542 444 IC TTL SMD 74F244SC NS 3 U51 53 92109 542 444 IC TTL SMD 74 2445 NS 3 U60 62 92109 542 444 IC TTL SMD 74F244SC NS 3 L20 23 92109 553 741 TTL SMD SN74AS374 4 U26 29 92109 556 464 IC TTL SMD DM74AS646 NS 4 U77 92109 911 680 IC CUSTOM 170 PLCC 82C452A SIS 1 U64 68 92109 912 141 PAL PLCC PAL16ISACNL MMI 2 U9 92109 916 010 IC PAL PLCC PALI6L8 MMI 1 U10 11 92109 916 020 IC PAL 20LB ECN MMI 2 071 73 92109 921 190 IC DRIVER SMD SN75188D 2 U70 92109 923 010 IC RECEIVER SMD SN75189D 1 U75 76 92109 923 010 IC RECEIVER SMD SN75189D TI 2 Q1 92149 403 630 TRANSISTOR PN2222 SSI 1 D1 92169 210 071 DIODE SMD LLA148F ITF 1 93004 480 001 PWB MAIN 350 305 6LAYER 50840 1 JUMP 93340 502 230 CONNECTOR B JUMP 90059 0014 2P MOL KOR 12 288 Location No Part No Description Specification Q ty J7 8 93340 762 030 CONNECTOR CARD EDGE SQ 2500 62 LEADER 2 J1 6 93340 798 010 CONNECTOR CARD EDGE 645169 2 AMP DUAL 18 amp 31 9 93340 905 040 CONNECTOR DIN 57PC5PS SWITCHCRAFT 1 P2 3 7 93341 002 001 CONNECTOR HEADER SPS04 502 WOO YOUNG 3 P10 13 93341 002 001 CONNECTOR HEADER SPS04 502 WOO YOUNG 4 93341 002 100 CONNECTOR HEADER SPS04 S02G WOO YOUNG 3 93341 002 100 CONNECTOR HEADER 5 504 502 WOO YOUNG 4 1 93341 003 080 CONNECTOR HEADER SPS04 03 SINGLE
100. 86 systems 131 i Noncachable Address Comparators Certain regions of main memory may be declared noncachable to avoid data conflicts that can arise out of some DMA operations or memory remapping carried out by an external device These areas can be programmed into the A38202 by means of noncache descriptors The noncached comparators continually monitor the internal address bus to detect accesses to memory locations that have been designated noncachable The comparators signal the control unit when these accesses occur 9 2 2 Cache Organization The A38202 can be used to implement a number of varying cost performance cache solutions Cache size can be varied from 32kB to 128kB and associativity can be direct mapped or 2 way set associative There are 2 memory groups each accessed in parallel during a bus cycle Each group contains 256 entries consisting of a tag and cache data presence information 512 entries total Each entry is associated with a block of data in the cache data memory The block size varies from 64 bytes to 256 bytes as the cache size varies from 32kB to 128kB The cache data memory is implemented in external high speed RAM chips When the cache is accessed an 8 bit field from the 32 bit physical address called the set number is used to access each group Two tags are read and compared simultaneously to the tag field from the physical address If there is no match termed a cache miss then the cache
101. 9 HT133 BUS BRIDGE INTERFACE PIN DESCRIPTIONS 92 CHAPTER 8 CONFIGURATION REGISTERS OF THE GCK131 CHIP SET 81 INTRODUCTION Dek Ph ee s ome ee 97 82 GENERAL DESCRIPTION 97 83 THE INDEXES REGISTERS eee enn nn 99 CHAPTER 9 CACHE 91 DESCRIPTION 1 1 4 2 24 6 127 911 A38202 Microcache ERR aged Rea Ta rt tee ond 127 912 A38202 Programming 0 mnn 128 913 3 8202 Re 129 92 ARCHITECTURE 129 9 2 1 Internal Configuration 129 9 2 2 Cache Organization 2 132 923 Cache Coherency HH eene 132 924 Regions 133 93 A38202 SIGNALS hme 134 931 Timing and Processor Signals 135 932 Other Cycle Definition Signals 136 933 Cache Control Signals 137 934 A38202 Local Signals 138 935 Burst Mode Control Signals 2 139 936 Latch and Tr
102. A38202 and 80386 are always in phase with each other Address Bus A31 A2 BE3 BE0 and Cycle Definition Signals M IO D C W R LOCK The A38202 connects directly to these outputs of the 80386 The address bus signals are used by the A38202 to perform its tag RAM lookup to determine whether the data the 80386 has requested resides in the cache The cycle definition signals are decoded by the A38202 to determine the type of cycle the 80386 is executing 135 Address Strobe ADS ADS is asserted by the 80386 when new address and cycle definition signals are available It is used to keep track of the state of the 80386 Ready Input READYI READYI is an input to the A38202 that indicates the completion of an 80386 bus cycle It is used in conjunction with ADS to keep track of the 80386 state READYI should be connected to the 803865 READY input Next Address Request NA is asserted by the A38202 to request the 80386 to enter pipelined mode Note The A38202 must have exclusive control of the 80386 s NA signal Ready Output READYO and Bus Ready Enable BRDYEN The A38202 directly terminates three types of cycles with its READYO output These are Cache Read Hit Cycles Posted Write Cycles I O Accesses to the A38202 All other cycles are terminated by either devices on the 80386 local bus or the A38202 s system bus BRDYEN is asserted by the A38202 during syste
103. Bit 4 to enable or disable the use of DRAM Banks 4 and 5 Lower and Middle Bros As detailed in a previous chapter 6 3 Programming the configuration registers Use Bits 6 and 7 to enable the shadowing of the lower and or middle BIOS images of BIOs into DRAM Bit State Description 0 0 Coprocessor disabled 1 Coprocessor enabled 1 0 Coprocessor type 80387 1 Coprocessor type 80287 2 0 Reserved Should always be programmed to 0 3 0 Parity disabled 1 Parity enabled 4 0 DRAM Banks 4 and 5 disabled 1 DRAM Banks 4 and 5 enabled 5 0 cas Shift disabled 1 cas Shift enabled NOTE CAS will be delayed by one half Fast CLK cycle during a WRITE operation to accommodate slow processors 6 0 Lower BIOS Not shadowed 1 Lower Bios Shadowed into DRAM 7 0 Middle Bios Not shadowed 1 Middle Bios Shadowed into DRAM If present Figure 8 1 INDEX001h General Setup Bits 100 Configuration Registers of the GCK131 Chip Set INDEX01h General setup bits Default value 88h The configuration bits of INDEXOTh are also available for general system setup purposes As indicated below use Bit 0 to enable or disable the shadowing of Video Bios Use Bit 1 to control the use of PAGE mode The BIOS EPROM type is selected by Bit 2 Other Bits are used in this manner Use Bit to select the 80387 coprocessor CLOCK mode as either asynchronous or synchronous Video B
104. C 10 Pin Type Description 47 Chip Select for the 8042 Keyboard Controller Chip Select for EEPROM NVRAM Used to save the last selected configuration register values Video Configuration Register Write strobe See Index Address 44h on Page 70 Acknowledge When active indicates that the device requesting DMA now has service and can remove its DMA request DRQ Data Input for EEPROM Connects directly with the EEPROM data out line Data Output for the EEPROM NVRAM Requests Priorities descrease from DRQO to DRQ7 A request is generated by driving a DRQ line HIGH until the corresponding DACK line goes LOW DRQO to DRQ3 perform 8 bit transfers and DRQ5 to perform 16 bit transfers Enable Address Strobe on the Real Time Clock When active it prevents any accesses to or from the Real Time Clock Enable PORT 92h Used in conjunction with INDEX 48h Mode Reconfiguration Register Bit 1 the status of ENP92 when HIGH confirms that the PORT92h feature is enabled See also INDEX 48h and cicuitry shown on Page 76 Redefined from ATA17 Fast RC Reset is active HIGH 110 to 135s pulse to be gated externally with the RC line from the 8042 Keyboard Controller and presented to the HT132 CPU Memory Controller See also INDEX 48h and cicuitry shown on Page 76 GC131 Peripheral Controller Description Pin Pin Pin Symbol
105. CK GNDC DSKCHG RG INT 21 22 23 24 25 26 27 28 2 30 31 32 33 Figure 13 1 Connection Diagrams 13 2 FEATURES e Fully PD765A and IBM BIOS compatible Integrates all PCXT PCAT and most PS 2 Logic On chip 24MHz Crystal Oscillator DMA enable logic IBM compatible address decode of 0 2 12 mA bus interface buffers 40 mA floppy drive interface buffers Data rate and drive control registers Precision analog data separator Self calibrating PLL and delay line Automatically chooses one of three filters Intelligent read algorithm Two pin programmable precompensation modes DP8472 4 core with its enhancements Up to 1 Mb s data rate Implied seek up to 4000 tracks IBM or ISO formatting Low power CMOS with power down mode 186 DP8473 Floppy Disk Controller RD WR AD INTER FACE ADDR 2 DECODE D0 D7 55 c lt s 6 A RESET 2L2 e O BR 23 x DAE zg HDSEL DAK DRQ INT DMA AND 765A INTERRUPT COMPATIBLE ENABLE MICROENGINE AND TIMING O RPWILC CONTROL LOGIC INDEX DATA RATE DP5472 4 DRYTYP REG amp CLOCK PUMP PREN FILTER FILTERS FOR ALL DATA RATES pe FGND250 FGND500 CN SETCUR EXTERNAL NDE ENTERNAL FILTERS GNDC CURRENT SET NOTE BND WDATA E RESISTOR Note 1 The MTR2 MTR3 DR2 and DR3 are not availa
106. Configuration CONFIGDW registers CONFIGDR PDO 7 Figure 7 1 HT133 Bus Bridge Interface Block Diagram 90 GC133 Bus Bridge Interface 73 HT133 BUS BRIDGE INTERFACE PINOUTS The pin connections for the HT133 Bus Bridge are shown in Figure 7 2 The pins are numbered sequentially in a counter clockwise direction from the index mark as viewed from the botton of the chip x 1 EEE emnenXOULSSau e GRR 2A IODA lt lt lt lt lt lt 2200222224 lt gt 50 2 4 9920 O00 ae Zee Ree eee eee OV ECE 225525222 1 1 1 i 1 RBBRSDIDZISSERBSOZSHESSSRSESSUZSE RSDIOST BALE 121 80 VDD PBENO 122 79 vss 123 78 PBEN2 124 77 RAS3 PBEN3 125 76 RAS2 LBHE 126 75 RAS1 TESTIN 127 74 IRASO TSTOUT 128 73 EXRAS1 ATDO 129 72 EXRASO ATD1 130 71 ADDRSEL ATD2 131 70 HLDA ATD3 132 69 REFRESH ATD4 133 68 PA22 ATD5 134 67 PA21 ATD6 135 66 PA20 ATD7 136 65 19 ATD8 137 64 PA18 ATD9 138 GC133 63 17 ATD10 139 62 16 VDD 140 2 61 VDD vss 141 B d I rf VSS a Bus Bridge Interface E ATD12 143 58 14 ATD13 144 57 PA13 ATD14 145 56 12 ATD15 146 55 11 ATAO 147 54 10 1 148 53 PA9 SAB646 149 52 PA8 4 150 51 PAZ BBEN3 151 50 VSS BBEN2 152 49 PA6 153 48 5 iBBENO 154 47 PA4 CLK646 155 46 PA3 NC 156 45 157 44 CONFIGAS NC 158 43 CONFIGDW NC 159 e 42 CONFIGDR VDD 160 41 VSS
107. Configuration register Data Read Write 40h 43h Timer Counter 8254 Read Write 60h 64h Keyboard Controller 8042 Chip select 61h Port Bregister PPI 8255 Read Write 70h Real time Clock register Address NMI Mask Bit Write only 71h Real time Clock register Data Read Write 80h 8Fh DMA Memory Mapper Page registers Read Write 92h 93h 97h 99h DMA Memory Mapper Page registers Read Write 9Ah 9Bh 9Fh Interrupt controller slave 8259 Read Write COh controller 2 8237 master Read Write EOh FFh Numeric Coprocessor 80287 Chip select 278h 27Fh Parallel Port 2 Printer Read Write 2F8h 2FFh Serial Port 2 Chip select 378h 37Fh Parallel Port 1 Printer Read Write 3F8h 3FFh Serial Port Chip select Note Access to these devices is disabled for addresses above 1 Kb and during DMA operations 54 GC131 Peripheral Controller 5 24 Port B 8255 PPI Register Address 61h Data written Bit 3 1 Disable NMI for IOCHCK Bit 2 1 Disable NMI for Memory PARITY error Bit 1 Speaker data BitO 1 Enable Timer 8254 for speaker Data read back Bit 7 1 Memory PARITY error Bit 6 1 IOCHCK error Bit 5 Timer 2 8254 output Bit 4 REFRESH detect Bit 3 1 NMI disabled Bit 2 1 NMI disabled for memory PARITY error Bit 1 Speaker data Bit 0 1 Timer 2 8254 for speaker enabled Note The default setting on RESET is 00h
108. DE R10 12 R METAL OXIDE R34 R METAL OXIDE R6 7 R METAL OXIDE R2 R CEMENT R8 R CEMENT VR SEMI C18 19 30 31 41 C CERAMIC C42 C CERAMIC C12 C CERAMIC C23 28 29 38 C CERAMIC C5 6 7 43 C CERAMIC C45 C CERAMIC C60 C CERAMIC C35 C MONO CERAMIC C11 C POLYESTER C14 52 C POLYESTER C59 C POLYESTER C55 C POLYESTER C57 C POLYESTER C3 4 C POLYPROPYLENE C58 C POLYPROPYLENE C53 C ELECTROLYTIC C13 32 39 40 44 C ELECTROLYTIC C56 C ELECTROLYTIC C8 C ELECTROLYTIC C54 C ELECTROLYTIC C25 27 C ELECTROLYTIC C26 C ELECTROLYTIC C24 C ELECTROLYTIC C9 10 C ELECTROLYTIC Specification Unit Q ty Vender RD 1 4T 1 EA 5 ABCO RD 1 4T 1 8K F EA 1 ABCO RD 1 4T 10 EA 5 ABCO RD 1 4T 240 J EA 1 ABCO RD 1 4T 2K J EA 5 ABCO RD 1 4T 2K J EA 5 ABCO RD 1 4T 24K F EA 2 ABCO RD 1 4T 2 59K F EA 2 ABCO RD 1 4T 24K F EA 2 ABCO RD 1 4T 3K F EA 1 ABCO RD 1 4T 3 3K F EA 1 ABCO RD 1 4T 3 6K F EA 1 ABCO RD 1 4T 4 7 EA 1 ABCO RD 1 4T 470 J EA 1 ABCO RD 1 4T 4 7K F EA 4 ABCO RD 1 4T 4 7K F EA 2 ABCO RD 1 4T 470K F EA 2 ABCO RD 1 56 EA 1 ABCO RD 1 4T 5 6K F EA 1 ABCO RD 1 4T 680 J EA 1 ABCO RD 1 2 390K J EA 1 ABCO RD 1W 10 EA 4 ABCO RD 1W 10 J EA 2 ABCO RD 1W 33 EA 2 ABCO RD 1W 470 J EA 2 ABCO RD 1W 100 EA 2 ABCO RD 2W 47 EA 2 ABCO RD 5W 10 J EA 1 ABCO RD 5W 220 EA 1 ABCO 33235 1 2W 1K EA 1 COPAL HCYB3A102K 1KV 102 EA 5 SEMCO HCYB3A102K 1 102 EA 1 SEMCO HCYB3D561K
109. EARS Sis gt 741514 CBRL SI gt Celoj sfa FE B gt LAT CPYTO Ot PLES Exil 294 59 444 564 BancseL o pag pgp EXRASN O EXRASN RASN 00020002 INTON PARITYN CLREXPTION ERROR386M LBS16N NAN PEREQ386 PROCCLK STEM ATAO 3 SFRES RESETZ87 FAST SLOW 2 PEREQ387 MUXPA20 BUSY387N ERROR367N ROY387N PGVIOL TESTRES 5 20 TESTOUT NC NC NC NC 6152 CPU MEMORY CONTROLLER R40 vcco 22 40 59 80 98 121 142 160 20 33 60 100 101 141 STS8SCLK 08907544160 05195164 0 2211 REET I gt 51 gt 12 O O OGND JUMPER 261 19 40 61 80 92 102 120 140 160 2 121 gt 1 10 20 30 41 50 60 79 91 101 119 141 MALT 101 gt gt si gt CEPDIO L III 128 218 SOBRATO ee 54 ISO SIP4 33 RP 5 84 gt 5 f TSTOUT a4 TESTIN MASTERN ISO SIP4 33 NC 221 gt lt 2 71 gt Tor A31 gt SIT 262 20 gt 0 211 gt RECO aT SEARLE C ALTMUXAZQ j gt LO 431 gt lt 71 gt 22 41 59 80 90 99 121 142 160 1 12 19 20 21 40 60 61 62 81 100 101 102 120 159 140 141 C131 PERIPHERAL CONTROLLER Q ORQ ORQZ ORGS DROG ORO7 IOCHCKN
110. EED SLCTIN Enable int 166 Communication Ports Table 11 5 Parallel Port Registers Bits 7 4 REGISTER BIT7 BIT6 5 Read Port PD7 PD6 PD5 PDA Read Status BUSY ACK PE SELECT Read Control 1 1 1 IRQ ENB Write Port PD7 PD6 PD5 PD4 Write Control 1 1 1 IRQ ENB Table 11 6 Parallel Port Registers Bits 3 0 REGISTER BIT7 BIT6 BIT5 BIT4 Read Port PD3 PD2 PD1 PDO Read Status ERROR 1 1 1 Read Control SELECT INT AUTOFEED STROBE Write Port PD3 PD2 PD1 PDO WRITE Control SELECT INT AUTOFEED STROBE 11 3 2 Connector and Pinouts J13A is a 2x13 26 pin header connected to a DB25 connector Refer to Chapter 18 for pinout information on the parallel printer connector 167 KEYBOARD AND MOUSE CONTROLLER 12 1 INTRODUCTION The system board supports a 101 or 102 key enhanced keyboard and a three button mouse An Intel 8742 microcontroller controls the keyboard and mouse system interface see Figure 12 1 This chapter describes the keyboard and mouse interface through the 8742 microcontroller 12 2 KEYBOARD AND MOUSE CONTROLLER SYSTEM INTERFACE The keyboard and mouse controller communicates with the system through an 8 bit read only status register at I O address 64H a read only output buffer at I O address 60H and an input buffer The input buffer consists of two parts a data byte and a command byte written at addresses 60H and 64H respectively CLRCRT SLDCLK KEYCLK MGTES
111. EM 1 R28 91018 277 330 R CARBON RD 1 4T 33 1 RNI 2 91060 106 060 R NETWORK M06 1 103 BECKMAN 2 RN6 10 91060 106 060 R NETWORK M06 1 103 BECKMAN 2 RN16 91060 108 040 R NETWORK 1 RIK J BECKMAN 1 RN19 91061 102 101 R NETWORK M10 1 102J BECKMAN 1 RN3 5 91061 103 100 R NETWORK M10 1 103J BECK MAN 3 RN22 91061 151 182 R NETWORK M08 1 151J BACKMAN 1 RN7 9 91061 222 100 R NETWORK M10 1 222J BECKMAN 3 RN11 15 91061 222 100 R NETWORK M10 1 222 BECKMAN 5 RN17 18 91061 222 100 R NETWORK M10 1 222J BECKMAN 2 RN20 21 91061 222 100 R NETWORK 10 1 222 BECKMAN 2 RN23 24 91061 330 180 R NETWORK SIP M8 3 330 8P BECKMAN 2 27 91061 330 180 R NETWORK SIP 8 3 330 8P BECKMAN 27 RN25 91061 472 160 R NETWORK M6 1 472 BECKMAN 1 C163 164 91300 314 700 C CERAMIC SMD 12065A4 0JA1050R AVX 2 C166 167 91300 314 700 C CERAMIC SMD 12065A4 0JA1050R AVX 2 C172 91301 102 356 C CERAMIC SMD 12065C102KATO50R AVX 1 286 Location No Part No Description Specification Q ty C2 5 91301 104 756 C MONO CERAMIC SMD 12065C104KATO60R AVX 4 C7 8 91301 104 756 C MONO CERAMIC SMD 12065 104 AVX 2 C10 15 91301 104 756 C MONO CERAMIC SMD 12065C104KATO60R AVX 6 C17 25 91301 104 756 C MONO CERAMIC SMD 12065C104KATO60R AVX 9 C27 35 91301 104 756 C MONO CERAMIC SMD 12065C104KATO60R AVX 9 C37 68 91301 104 756 C MONO CERAMIC SMD 12065C104KATO60R AVX 32 C70 74 91301 104 756 C
112. EPTION FROM GC132 ra ES E rA 2 0 Ex GLUE CHIP CLK TESTRST SYSCLK RASON I386MCS16 RASIN RAS2N RASIN EXRASON EXRAS1IN MEMCS16N CPUHLDR SYSHLDA LWEON INTAN SMHNGCI MMHNGCI HULDA MWNSYS Q MASTERN SMWHNSYS CASAN PARITYON CASBN CASCN CASON LWEN BPMHNSYS NMI PARITYN CHIPHOLD CPUHOLD CLK2 ADSN ROYI8SOEN CPUMIO SMROYON HBS FALE WR PA RDY38SMN READYN I38ERDYN IOCS16IN I0CS160N CACHEMIO CLREXPI CLREXPOA CLREXPOB 8 PIM PLCC IGE CPARTTVGCT CEPMHNSYS CARIS CREL G I gt SAMSUNG ELECTRONICS DESKTOP 386 CGLUE ASIC Document Number 50840 04 6 255 20 gt PALO YL gt PREC 27 gt 42175 CNAX NONCACH gt AED Y gt 587 CACHCLEK gt R O ZRP TURBO gt 0 gt 017 Poo Si gt lal VCC 7 16 26 37 54 80 86 94 103 118 135 148 GNDz5 18 28 33 35 41 91 71 84 91 99 105 121 142 160 26 pero 4 E Peete es AZOGATE Pig BURSTREO MISS d BURSTACK CACHEF AULT CERTO 337 gt o gt 5 10 212 gt itle DESKTOP 386 CAUSTEK CACHE CONTOLLER gt Document Number 50840 05 0 PCO TID gt R3 R4 224 220 2117 gt JUMPER OUT 27256 EPROMS JUMPER IN 27512 EPROMS gt
113. FZW W WASHER 3 HANDLE 97094 970 520 BOLT HANDLE SUM24L NI PLATED 2 97154 230 081 SCREW TAP 25 3x8 FE W WASHER 8 CHASS 97408 140 121 SCREW TAPTITE PH 1B 4 12 FE FZY 5 TOP 97662 900 010 HANDLE ADC 12 COATING 1 STAND 98404 970 210 BALL STAND STEEL 16 4 2 99113 610 015 ASSY VIDEO BOARD GTI VGA 1 90469 100 006 SOLDER FLUXCORE WIRE P1 1 0 SN63 PB37 0 01000 KG 90469 100 007 FLUX KESTER 2331 0 50000 LT 90469 100 008 SOLDER WIRE SN63 PB37 30W WATER DONG YANG 0 50000 KG 90469 120 610 SOLDER SMD FC 70 FLUORINERT 3M 0 00230 KG 90519 900 310 WIRE WRAP BE03A040 26AWG BLU JUNKOSHA 0 30000 MT 90849 012 100 CLEAR PCB FLON 113 FREON 113 TES 0 02000 KG R2 91018 277 101 R CARBON RD 1 4T 100 J 1 R7 91018 277 102 R CARBON RD 1 4T 1K J 1 R1 91018 277 103 R CARBON RD 1 4T 10K J 1 R6 81018 277 361 R CARBON RD 1 4T 360 1 91018 377 333 R CARBON RD 1 2T 33K J 1 U04 08 91060 108 170 R NET 108 1 103 10K 8P BECK 2 U12 91061 103 100 R NETWORK M10 1 103 BECK MAN 1 RN5 91061 151 180 R NETWORK M8 3 151 BECK MAN 1 RN3 4 91061 333 100 R NETWORK M10 3 333 BECK MAN 2 U11 14 91061 333 180 R NETWORK 8 1 333 BECK MAN 2 290 EXPLODED VIEW SECTOR METERIALDTY q1623 Por 774 ABs w 39 knob da Abs ne AC Lens 91654 qo 49 acer Cui n SPRING RESET 94614 454 09 42 amid 88 CFE see ato o 1 FE
114. GC131 GC122 and GC133 in this book HT131 Peripheral Controller chip has the same function with GC131 HT132 CPU Memory Controller also has the same function with GC132 and HT133 Bus Bridge Interface does with GC133 System Specification 1 2 SYSTEM OVERVIEW The main unit enclosed with metal housing to comply with FCC regulations and safety standards has the following features 1 System motherboard running at 33MHz with 4MB DRAM 2 5 25 1 2MB formatted and a 3 5 1 44MB formatted floppy disk drives 3 Graphics adapter 4 Power supply 275 watts 5 A keylock switch to prevent your computer from any unauthorized access 6 Two cooling fans for system reliability installed in the power supply and the front of the chassis 7 Fixed disk drive option A 101 key keyboard comes with the computer and all IBM AT compatible peripherals such as monitor printer plotter and modem and allowed to be attached to the computer for your best applications 13 OVERALL SPECIFICATION 13 1 System Board CPU INTEL 80386 33MHz Full 32 bit data path INTEL iAPX 88 86 286 386 instruction set Real and Virtual address mode ATLAS Chip Set HT131 or GC131 Peripheral Controller HT132 or GC132 CPU Memory Controller 133 or GC133 Bus Bridge Interface Memory Onboard 4MB standard Expandable to 24MB Expansion Slots 8 I O slots 2 8 bit slots 6 16 bit slots System Specification Real Time Clock DS1287 real time clock CMOS
115. H 7FH Write internal RAM locations 21 3FH A7H Disable auxiliary device mouse A8H Enable auxiliary device A9H Auxiliary interface test AAH Self test ABH Keyboard test interface ADH Disable keyboard AEH Enable keyboard COH Read input port Poll input port low C2H Poll input port high Read output port D1H Write output port D2H Write keyboard output buffer D3H Write auxiliary output buffer D4H Write to auxiliary device Read test input port E1H EFH Set clear output pin FOH FFH Output pulse 173 Keyboard and Mouse Controller 124 KEYBOARD MOUSE INTERFACE The keyboard and mouse connect to the controller through bidirectional synchronous serial interface cables Refer to Appendix E for the pin assignments of the keyboard and mouse connectors The controller supplies the keyboard and mouse with DC power of 5 10 at a maximum current of 300mA The controller keyboard and mouse communicate using data and clock lines for synchronous serial communication Open collector drivers at both ends of the cable drive the data and clock lines At power up the keyboard scans the signals on the clock and data lines and establishes a line protocol A bidirectional serial interface in the keyboard converts the clock and data signals and transfers them to and from the keyboard through the keyboard cable Signals include keyboard control commands from the system and keyboard scan and acknowledgement codes transferred to the co
116. H CLOCK DIVIDED BY 4 WAIT STATE 38 4 5 7 Refresh Timing 2 State Timing Cancel Run Accumulate At tes s Div Delay Markers X to 0 Trig to x Trig to 0 1 00 us 0 Time 10 82 us 15 60 us 4 780 us 458 Cache Hit Cycle State Timing E Haveform Cancel Accumulate At ERE of EE s Div Delay Markers x toon Trig to X ig t 100 ns 0 s Time 100 ns 320 ns 2 Lk HB 4 5 9 Cache Hit Cycle 2 State Timing Waveform Cancel Accumulate At orf marker CLK2 Q Delau Markers X to X ton Trig to Trig toD 2 UEM ns Time 50 ns J E UL ns 240 ns 40 4 5 10 Cache Miss Cycle State Timing Waveform 1 Cancel Accumulate At Delay Narkers X to 0 Trig to X Trig to O 83 ns Time 560 ns 220 ns 140 ns f RUE GC131 PERIPHERAL CONTROLLER 5 1 INTRODUCTION This Chapter provides an overview of the GC131 Peripheral controller and describes the detailed function of all components which are contained in this chip 52 GC131 PERIPHERAL CONTROLLER OVERVIEW This single chip contains many components and effectively takes the place of them These components are as follows A 8254 programmable interval timer PIT Two 8259 programmable interrupt controllers PICs Two DMA controllers 5612 and other devices The GC121 Peripheral Controller block diagram Figure 5 1 shows t
117. HT133 will place the indexed register s value on the processor s data bus If the range is set within Oh to OFh HT133 does not drive the processor data bus at all INDEX indicates a value for the HT132 Controller If the range is within 40h to 4Fh HT133 lets the data come in from the AT data bus is driving the bus Configuration Data Write On the trailing edge of this signal data on the processor s data bus is written to the indexed register if within the range 10h to 1Fh Conversion Cycle A0 When this signal is active HT133 forces a T onto ATAO This is used during 8 to 16 bit conversion cycles RAS signals for Banks 4 and 5 HT133 uses these signals to latch the latest page value for the DRAMs Used in PGVIOL calculations Hold Acknowledge When the DMA controller or MASTER holds the bus and the processor has granted it this signal is active Controls the generation of A0 A1 and LBHE signals Interrupt Acknowledge When active HT 133 allows the interrupt vector flow from the AT data bus to the LOW byte on the processor bus 93 GC133 Bus Bridge Interface Pin Pin Pin Descrivti Symbol Number Type LBHE 126 Latched Byte High Enable When active indicates that valid data is on the high part of the 16 bit data lines to 78 82 O Multiplexed addresses DRAMs 9 90 IMASTER 94 I MASTER Mode Request When active and in conjunction with DMA indicates that
118. I signals when the upper banks are selected This is shown in Figure 6 12 Reference Application schematic 386 2 85 GC132 CPU Memory Controller In the drawing 386APP2 the NAND gate is required to ensure that only one bank can be selected at one time The individual RAS lines RASO RAS3 and EXRASO EXRASI are buffered by the 74F244 package for application directly to the corresponding bank See Drawing 386APP5 Figure 6 13 shows the recommended buffering and bank assignments BANKSELO BANKSEL1 From HT132 CASD BCAS A0 D0 To BANKO _ 2 BCASD3 To BANK1 BCAS A1 D1 BCAS A2 D2 BCASBO To BANK2 BCASBI BCASB2 BCASB3 BCASAO BCASA1 BCASA2 7 155 BCAS A3 D3 EXRASO BCAS A4 D4 EXRASI BCASD5 BCASA4 TO ywwn_BCASD4 BCASBA iun ICASD HT132 45V BCASD4 case ee Ground 12 7AF155 EXRASO EXRAS1 BEA BCASB4 n ICASB 5 E 5 5 5 97 5 A BCASA4 round To BANKS BCAS 5 5 74 155 Figure 6 12 Connecting Six Banks of RAM GC132 CPU Memory Controller BRASO BRAS1 IRAS0 RAS1 BRAS2 RAS3 From EXRASO BRASS HT132 EXRAS1 BEXRASO IBEXRAS1 Figure 6 13 Connecting RAS Signals to the DRAMs 69 DRAM REFRESH All DRAM require each memory cell to be refreshed at least once every four ms To meet this
119. Interleaved Dram Timing 2 State Timing E Waveform 1 cancel Accumulate At er s Div Delay Harkers to 0 Trig to 719 to 0 100 ns S Time 60 ns 90 ns 30 ns GC131 Peripheral Controiler SYSCLK FAST SLOW CLK281 CK8042 8042 BUSCLOCK OSC PWRGOOD SYSRES RESET INT OPTBUFFULL IRQ3 7 RTCIRQ IRQ9 15 SPKRDATA 17 31 BALE SMEMR ISMEMW 16 ATA0 16 ATD0 7 17 FAST RC ATA18 ALT_MUXPA20 19 PARITY NOCHCK NMI ENADDSTB RTCAS RTCDS RTCRW Figure 5 1 GC131 Peripheral Controller Block Diagram CONTROL Clock control Reset control Interrupt control 8259 INTR Control master 8259 INTR Control slave 8254 Timer Memory mapper Decoder buffer Bidirect buffers PARITY Port B Register RIC Control 5 D0 7 71 8237 E Control slave 8237 DMA j Control master Arbiter Refresh control Bus control Wait state generator Bi direct buffer Refresh counter HO Peripheral decode Configuration L_l Registers EEPROM Control DRQO 3 DACKQ 3 DRQ5 7 IDACK5 7 AEN1 2 TC CPUHRQ HLDA IOCHRDY MASTER ILBHE REFRESH MEMR MEMW AOW 58042 6287 PCSRPC BFDIR PCSWPA BFEN ENP92 PCSWPC LPTOE PCSRPA PARCS PARIE PARIRQ SERCS1 SERCS2 CONFIGA
120. JAT0050R AVX 1 C199 7 91301 681 756 C CERAMIC SMD 12065A681JATOO50R AVX 9 C183 5 91457 122 200 C MONO CERAMIC SMD 12061A221JATO60R AVX 3 C188 91457 122 200 C MONO CERAMIC SMD 12061A221JATO60R AVX 1 C190 91457 122 200 C MONO CERAMIC SMD 12061A221JATO60R AVX 1 C193 6 91457 122 200 C MONO CERAMIC SMD 12061A221JATO60R AVX 2 C198 91457 122 200 C MONO CERAMIC SMD 12061A221JATO60R AVX 1 C170 91457 122 530 C MONO CERAMIC SMD 12065C473KATO60R AVX 1 C1 6 91609 010 230 C ELECTROLYTIC SE04W 25 10 SAMHWA 2 C9 16 91609 010 230 C ELECTROLYTIC SE04W 25 10MF SAMHWA 2 C120 2 91609 010 230 C ELECTROLYTIC 5 04 25V 10 SAMHWA 2 C26 36 91609 010 230 C ELECTROLYTIC SE04W 25V 10MF SAMHWA 2 C69 91609 010 230 ELECTROLYTIC SE04W 25V 10MF SAMHWA 1 C119 91609 010 230 C ELECTROLYTIC SE04W 25V 10MF SAMHWA 1 C208 91609 010 230 C ELECTROLYTIC SE04W 25V 10MF SAMHWA 1 C75 80 91609 010 230 ELECTROLYTIC SE04W 25V 10MF SAMHWA 2 93 91609 010 230 C ELECTROLYTIC SE04w 25V 10MF SAMHWA 2 C99 91609 010 230 C ELECTROLYTIC SE04W 25V 10MF SAMHWA 1 C135 91609 010 230 ELECTROLYTIC SE04W 25V 10 SAMHWA 1 U41 49 92109 337 200 IC EPROM 2 C256 20 SIG 2 287 Location No Part No Description Specification Q ty 067 92109 350 082 IC SRAM PLCC 63 328 03 VITELIC 2 U18 19 92109 350 082 SRAM PLCC V63C328J03 VITELIC 2 U36 92109 400 020 IC CPU MFMORY CONTROLLER GC132C LSI L
121. M Timing as Referenced in INDEX04 Bit State Description 1 0 Bit 1 Bit 0 The combination of Bits 1 and 0 select the following 0 0 Zero RAS delay 0 1 One RAS delay 0 Two RAS delays 1 1 Three RAS delays 2 0 Two CAS delays measured from RAS in CLKIN 1 Three CAS delays 104 Configuration Registers of the GCK131 Chip Set Bit State Descriiption 6 3 Bit 6 Bit 3 The combination of Bits 6 and 3 select the following 0 0 Two CAS active CLKIN cycles 0 1 Four CAS active 1 0 Six CAS active 1 1 Eight CAS active 4 0 Four RAS precharge CLKIN cycles 1 Six RAS precharge 5 0 Zero recovery time 1 Two recovery CLKIN cycles Figure 8 6 INDEX04h DRAM Timing BANKSO 3 INDEXO05h DRAM configuration Banks 4 5 Default value FFh This configuration register is available to program the timing for RAS and 5 in Banks 4 and 5 HINT See 04 for more information about delay timing Bit 1 0 State x o H H H H A OS e Md H H H H Or Description The combination of Bits 1 and 0 select Zero RAS delays One nas delay measured in CLKIN cycles Two Ras delays Three RAS delays Two CAS delays measured from RAS in CLKINS Three CAS delays 6 3 H H H I The combination of Bits 6 and 3 select Two CAS active CLKINs Four
122. Middle BIOS EE 000h Lower BIOS FFFFh 1 Mb EE aH F0000h EO000h 5 Figure 6 4 EPROM Memory Map 222 GC132 CPU Memory Controller How to Use MBEN to Remove Middle BIOS MBEN is signalled by INDEXOIh See Chapter 8 General setup bits where Bit 6 is set to 0 to disable and T to enable MBEN 63 3 Programmable Configuration Bits Allow RAM Shadowing The ATLAS Chip Set has a built in shadowing feature that allows the copying of the BIOS EP ROMs to RAM for faster execution of ROM based code When a shadowed BIOS is accessed by the 80386 Microprocessor the data is fetched from high speed 32 bit RAM instead of the slower 16 bit ROM on the motherboard or even slower yet from 8 bit access through the expansion bus Shadow disabled Processor WRITE to DRAM is shadowed below the EPROM 32 Bit DRAM shadow enabled Processor WRITE to EPROM is now shadowed below DRAM Processor READ from DRAM EPROM 32 Bit DRAM 32 Bit DRAM Figure 6 5 RAM Shadowing 73 GC132 CPU Memory Controller How the RAM Shadow Feature Works The shadow RAM feature initially routes READ operations to the physical ROM and WRITE operations to the shadow RAM At system start a routine in the system BIOS makes a copy of the ROM modules to RAM by copying the BIOS back to itself a 32 bit copy replaces
123. NFIGURATION REGISTER bits are described as follows CS1 0 Cache Size bits 0 amp 1 The two C bits define the cache size as described below 00 32kB 01 64kB 10 128 11 Reserved to Austek S16 16 byte subblocks bit 3 When this bit is set it forces the A38202 to use 16 byte subblocks regardless of the cache size Normally the A38202 will only use 16 byte subblocks for 64kB and 128kB cache sizes AS1 0 Cache Associativity bits 4 amp 5 The A bits define the cache associativity as described below 00 Direct Mapped 01 2 way 10 Reserved to Austek 11 Reserved to Austek UL Interleaved Linear DRAM bit 7 The I L bit is used to change the order in which data is fetched during multiple fetch cycles or the order in which data is expected during burst fills This ordering is described in table 9 3 144 Table 9 3 Multiple Fetch Data Ordering Requested Address Linear DRAM Interleaved DRAM 0 1 2 3 0 3 2 1 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 1 0 3 2 3 0 1 2 3 0 1 2 3 944 Status Register As shown in figure 9 6 the STATUS REGISTER contains 2 bits defined to indicate the current status of the A38202 This register is read only Figure 9 6 Status Register The defined STATUS REGISTER bits are described as follows O Invalidation Overflow bit 0 When set indicates that invalidation requests occurred too frequently i e more than once every two T states to be processed
124. O ih LOCAL BURSTACK NONCACHE E 20 TN D7 0 LATCH AND TRANSCEIVER a MF CONTROL STATUS J CACHEFAULT AND FLUSH CONTROL pac BUS WATCHING Figure 9 3 A38202 Signals 134 Signal Naming Conventions The symbol is used at the end of a signal name to indicate that the signal is asserted when it is at a low voltage level The absence of the at the end of the signal name indicates that the signal is asserted when it is at a high voltage level Example READYO This signal is asserted when it is at a low voltage level CACHEFAULT This signal is asserted when it is at a high voltage level Individual signals from buses are indicated by appending the ordinal number of the signal in the bus to the name Example A31 to A2 93 1 Timing and Processor Signals The timing and processor signals interface the A38202 Microcache to the 80386 80386 A38202 Clock CLK2 CLK2 provides the fundamental timing for an 80386 A38202 system and should be connected to the same source that drives the 80386 CLK2 input 80386 A38202 Reset CLKRESET PWRGOOD The A38202 has two reset signals PWRGOOD and CLKRESET PWRGOOD should be sued as a power on reset to the A38202 It sets the A38202 to a known state see section 4 22 for details CLKRESET is used by the A38202 to synchronize its internal clock It should be connected to the RESET input of the 80386 This will ensure that the
125. OGIC 1 U33 92109 400 030 IC GLUE PLCC L4A8024 LSI LOGIC 1 05 92109 400 040 IC CACHE CONTROLLER A38202 33 AUSTEK 1 U42 92109 400 050 IC RTC DS1287 DALLAS 1 U37 92109 400 060 IC BUS BRIDGE INTERFACE GC133B LSI LOGIC 1 U30 92109 400 070 IC PERIPHERAL CONTROLLER GC131B LSI LOGIC 1 050 92109 401 070 IC 08742 IN SSI 1 08 92109 401 380 IC CPU 180386DX 33 PGA INTEL 1 U67 92109 406 130 IC FDC PLCC DP8473 PLCC NS 1 U67 92109 406 140 IC FDC PLCC DP8471 PLCC NS 0 U16 92109 502 404 IC TTL SMD 74AC1240 NS 1 U66 92109 510 061 IC TTL SMD SN7406 TI 1 U32 40 92109 520 81 IC TTL SMD SN74LS08 2 U34 92109 520 141 IC TTL SMD SN74LS14D TI 1 U63 78 92109 520 321 IC TTL SMD SN 4LS32 2 U65 92109 520 741 IC TTL SMD SN ALS74AD TT 1 U74 92109 522 441 IC TTL SMD SN74LS244D 1 U39 48 92109 522 451 IC TTL SMD SN74LS245D TD 2 U46 47 92109 522 451 IC TTL SMD SN74LS245D TD 2 U69 72 92109 522 451 IC TTL SMD SN74LS245D 2 U24 92109 540 044 IC TTL SMD 74F04 NS 1 U35 92109 540 084 IC TTL SMD 74F08 NS 1 11 3 92109 540 324 TTL SMD 74F 325 NS 2 056 57 92109 540 324 IC TTL SMD 74 325 NS 2 U79 92109 540 324 IC TTL SMD 74F 32SC NS 1 U13 92109 540 745 IC TTL SMD N74F74D SIG 1 U54 55 92109 541 385 IC TTL SMD N74F138D SIG 2 U58 59 92109 541 385 IC TTL SMD N74F138D SIG 2 031 92109 541 754 TTL 74F175SC NS 1 U
126. RAS delays 2 CAS delays 2 CAS active RECOVERY PAGE VIOLATIONS are always false 1 DRAM delay BANK 0 override OFF acts on the settings of INDEX04h and 05h 1 0 DRAM delay BANK 1 override ON 1 DRAM delay BANK 1 override OFF 2 0 DRAM delay BANK 2 override ON 1 DRAM delay BANK 2 override OFF 3 0 DRAM delay BANK 3 override ON 1 DRAM delay BANK 3 override OFF 4 DRAM delay BANK 4 override ON 1 DRAM delay BANK 4 override OFF 5 0 DRAM delay BANK 5 override ON 1 DRAM delay BANK 5 override OFF 6 0 Reserved Always program to 0 7 0 Reserved Always program to 0 Figure 8 3 INDEX02h High Speed Override Bits 102 Configuration Registers of the GCK131 Chip Set INDEX03h DRAM configuration Default value AOh This configuration register is used to match the number and type of DRAMs used in the system The selection of either 256K or 1 Mb prams is made within two groups namely Banks 0 1 and Banks 2 through 5 This arrangement does not allow the intermixing of DRAM types See the Note regarding INDEX10h Interleaving and EMs PAGE address settings are also configured using this configuration register Bit State Description 0 1 Bit 0 Bit 1 The combination of Bits 0 and 1 select the following 0 0 DRAMS 256K BANKO through BANKS 0 1 Reserved 1 0 Reserved 1 1 DRAMS are 1 Mb BANKO through BANKS 3 2 Bit 3 Bit 2 The
127. RQ7 An interrupt request is generated on the rising edge of an IRQ line which must be held HIGH until acknowledged by the interrupt service routine GC131 Peripheral Controller Pin Pin Pin Symbol Number Type Description LAT to 113 to LA31 119 and 112 to 129 LBHE 57 IO LPTOE 107 16 137 IMASTER 54 I MAGATST 51 I 49 Buffered unlatched Processor Address bus Used for memory and I O devices LAT7 to LA23 are used in AT implementation to provide addressing up to 16 Mb They are valid only when BALE is HIGH These signals are generated by the CPU or the DMA controller in the HT131 Controller or they may be driven by an external bus master on the I O channel In the AT implementation the unused addresses LA24 through LA31 must be connected through resistors to ground Bus High Enable When active LBHE indicates that data is valid on the upper half of the AT data bus Normally this signal is an input except during DMA when it is driven by the DMA controller but during MASTER cycles LBHE is driven from the back plane and is therefore an input Redefined from PCSWPC Line Printer Output Enable used when the HT16C452 Interface Mode that allows connection to discrete parallel ports of the HT16C452 Interface is enabled by setting Bit 0 of INDEX48h See TNDEX48h on Page 74 Lower 16 Mb Address This signal is not used in the AT implementation Indica
128. RUN TIME MESSAGES 246 B4 SYSTEM BOARD ERRORS 247 SCHIMETIC wince stead Ext onte 251 D PART LIST 285 VIII Figure 2 1 Figure 2 2 Figure 3 1 Figure 5 1 Figure 5 2 Figure 6 1 Figure 6 2 Figure 6 3 Figure 6 4 Figure 6 5 Figure 6 6 Figure 6 7 Figure 6 8 Figure 6 9 Figure 6 10 Figure 6 11 Figure 6 12 Figure 6 13 Figure 7 1 Figure 7 2 Figure 8 1 Figure 8 2 Figure 8 3 Figure 8 4 Figure 8 5 Figure 8 6 Figure 8 7 Figure 8 8 Figure 8 9 Figure 8 10 Figure 8 10 Figure 8 11 Figure 8 12 Figure 8 13 Figure 8 14 Figure 8 15 Figure 8 16 FIGURES System Board Component Layout 6 System Board Functional Diagram 7 CPU Block Diagram BAR ie C EE ACE 19 131 Peripheral Controller Block Diagram 34 HT131 Peripheral Controller Pinouts 43 GC132 CPU Memory Controller Block Diagram 58 132 CPU Memory Controller Pinouts 59 HT132 Memory Controller Memory Map 71 EPROM Memory Map 3x ved ea dem tetany eX 72 RAM Shadowing u sz eed ihn He Lagan Hawa seas 73 Summary
129. Rerun the Setup program and turn video BIOS shadow off Shutdown failure The keyboard controller or its associated logic has failed Contact your service representative Time of day clock stopped The intergral battery in the RTC is probably dead Contact your service representative Time of day not set Please run the Setup utility The date and time information is not set in the real time clock Run the Setup utility and set the date and time Timer chip counter 2 failed The timer chip on the system board may have failed Contact your service representative Timer or interrupt controller bad The PIT or the PICs on the system board may have failed Contact your service representative 244 Messages Message Possible Cause Solution Unexpected interrupt in protected mode The system received an interrupt when in protected mode probably while resting memory Contact your service representative B 2 2 Post and Boot Information Messages These messages do not indicate error conditions Message Meaning Message Meaning Message Meaning Message Meaning Message Meaning Hex value Base Memory Indicates the amount of base memory that has been tested successfully Hex value extended Indicates the amount of extended memory that has been tested successfully Decreasing available memory This message immediately follows any memory error message informating you that memory modules are f
130. S CONFIGDW CONFIGDR CSVREG CSEEP CKEEP DOEEP DIEEP 4 5 3 Non Interleaved Dram Timing 1 Stete Timing E Waveform 1 cancel Accumulate At Off X marker CLKIN 9 5 3 CLKINS CAS DELAY 3 CLKINS CAS ACTIVE 8 CEKINS RECOVERY TIME 2 CLKINS RAS PRECHARGE 8 CLKINS 35 4 54 Non Interleaved Dram Timing 2 State Timing Waveform Cancel j Accumulate At TM 0 orf X marker ELKIN s Div Delay Markers to 0 Trig to x Trig to 0 100 ns s Time 680 ns 400 ns 280 ns ELKIN 7805 BALE READY PA PBEN DBEN ze 01001 Te ee PAS ICAS E EET KM MENTEM a uha DPSHT PD11 0 36 4 5 5 16 Bits Access to 16 Bits OFF B D Dram State Timing E Cancel Run Accumulate At L Off X marker CLKIN l s Div Delay Markers X to 0 Trig to x Trig to 0 100 ns o s Time 170 ns 230 ns 400 ns SS L oNP rr s m COMMAND DELAY 7 CLKINS COMMAND ACTIVE 13 CLK INS RECOVERY TIME 6 CLKINS 4 5 6 Refresh Timing State Timing E Waveform Cancel Accumulate At s DIv Delay Markers X to D Trig to X Trig to 0 50 ns 508 ns Time 200 ns 410 ns 610 ns ADRSHT IRAS CAS LHEN REFRS SPEED FAST REFRES
131. SERVICE MANUAL MODEL SD840 SERIES TABLE CONTENTS CHAPTER 1 SYSTEM SPECIFICATION T17 INTRODUCTION Saya a Cm 1 2 SYSTEM OVERVIEW SURE VOR edhe PR ee ERI y L3 OVERALL SPECIFICATION a cetero RECS REESE 134 System Bo rd wore ori diodes pd Sy eu cag REESE EI pU gan 132 Poppy Disk DEVE S Ut OE E tp fg 133 Graphics Adapters oou uq reed a dd Toe PO a o o veut Dee aate Datur d atis Du eg L95 19 2 s p pev bd RU IS eu DEIN kot iA xs pde meme 136 Tsa AAT sae CHAPTER 2 BOARD OVERVIEW 2 1 INTRODUCTION yaa ms S geste pace cre e d up 2 2 OVERVIEW Coste ayama Ga a S aa s is 2 3 FEATURE SET DESCRIPTION 2 3 1 Central Processing Unit CPU scan S 232 Memory YS E SERE ey ER e 2397 ISA BUS terete hee a eed A 234 GKIGL Chip Set Greate RU BUS eee eC a 2 35 051287 Real time Clock RTC 236 Input Output Expansion Slots srren rrer 2937 DOrts i ani qe 238 842 Keyboard and PS 2 Mouse Controller Se eb 2 3 9 Interface Logic
132. T SSLDDAT D0 7 KBDCLKR MSECLKR 8742 MSEDAT ff MSEDAT Keyboard Buffer IOWC Controller MICCTCS LU MSEINTR 12 A2 Buffer 1 gt KEYL Figure 12 1 Keyboard Mouse Controller KBIRQ MSECLK MSECLK IOWR 169 Keyboard and Mouse Controller 12 2 1 Status Register The controller status register contains information about the state of the controller and system interface refer to Table 12 1 Table 12 1 Status Register Bit Definition Bit Function 0 Output buffer I O Address 60H full 0 No data from the keyboard in the output buffer DBBOUT 1 The keyboard controller loaded the output buffer with data This bit is set to 0 when the CPU reads it DBBIN 1 Input buffer I O Address 60H full 0 No data from the CPU in the input buffer 1 Data from the CPU in the input buffer This bit is set to 0 when the keyboard controller reads the buffer 2 System flag 0 Power on reset occurred 1 Self test successful 3 Command data 0 A data byte written port 60H 1 Acommand byte written port 64H 4 Front panel keylock status 0 Keyboard inhibited 1 Keyboard not inhibited 5 Auxiliary mouse device output buffer full 0 Output buffer is keyboard device data 1 Output buffer is auxiliary device data 6 General time out 0 Data reception from the keyboard auxiliary device terminated normally with
133. TION PORTS 165 112 1 CPU Interfacing ti Staa aduer Dons utet uet 165 11 2 2 Connectors and Pinouts 555 x x xad eu a Su Aog ecu gres 165 113 PARALLEL PRINTER PORT 166 11 3 1 Programming 23256 ceo ees Sie 166 11 32 Connector and 167 CHAPTER 12 KEYBOARD AND MOUSE CONTROLLER 12 1 INTRODUCTION sv crake sees pias eer u uska d Rata 169 12 2 KEYBOARD AND MOUSE CONTROLLER SYSTEM INTERFACE 169 12 21 Status Register o ay oe aut aN ued ie DINI dade sse eod 170 12 22 O tp t DUHEE Abr ap ST Coste x eer URV EE ME 4 171 1223 aput BUffer i i ed ihr Te ces ee poe eL AR E CR 171 12 24 Input and Output Ports EIU weg 171 123 CONTROLLER COMMANDS 2 173 124 KEYBOARD MOUSE INTERFACE 3333 0045055 05 ee EDO TES X ER ees 1 4 124 1 Keyboard Mouse Data Stream 175 1242 Receiving Data from the Keyboard 175 1243 Sending Data to the Keyboard 177 1244 System lo Mouse Commands oon ey ERR 180 1245 Mouse Io System Replies 183
134. TO BANK 0 TO BANK 1 TO BANK 2 TO BANK 3 TO BANK 4 TO BANK 5 requirement a system wide refresh cycle occurs every 15us The system board conducts the refresh cycle to both ISA bus memory and 32 bit memory simultaneously During the refresh cycle the CPU can still access cache An ISA bus secondary requesting agent SRA must initiate refresh cycle at appropriate intervals if it has control of the ISA bus for greater than 15us The system board executed the refresh cycle and then returns control to the SRA 87 GC133 BUS BRIDGE INTERFACE 7 1 INTRODUCTION This chapter provides an overview of the GC133 Bus Bridge Interface 72 SEPARATION OF 32 BIT AND 16 WORLDS For system implementation several buses are supported by the GCK131 Chip Set Of these the 32 bit processor address PA and data PD bus and the 16 bit address ADA and data ATD bus are particularly important to the system designer Figure 7 1 shows the functional block diagram of HT133 Bus Bridge Interface chip The PA and PD Bus The PA and PD bus is high speed address and data bus that interfaces with the 80286 Microprocessor and the 80287 or 80387 numerical coprocessor This bus also provides the local information path between all three chips of the GCK131 Chip Set The address and the data paths of this bus are 32 bit wide as required to handle the full range of address and data values In an AT system I O devices should not be directly
135. USCLOCK 138 C131 VSS 139 VSS 10 VSS e Peripheral Controller ISMEMW 143 ISMEMR 144 8042 145 042 146 ENADDSTB 147 PARITY 148 DIEEP 149 CSEEP 150 CKEEP 151 58042 152 1 5287 153 5 154 RICDS 155 RTCRW 156 RESET 157 HOR 15 HOW VDD 10 9 BAN NEYMUMOR 4 SR ARABS pi 4 ANANN Ea GO gt 226 756 2 OF g m z K Figure 5 2 HT131 Peripheral Controller Pinouts VDD ATAO DACK7 DACK6 IDACK5 IDACK3 2 IDACK1 IDACK0 DRQ7 DRQ6 DROS DRQ3 DRQ2 DRQ1 DRQ0 CPUHRQ TC VSS VSS VSS VDD REFRESH ILBHE AEN2 AEN1 iMASTER HLDA IOCHRDY MEGATST TESTC TESTB IRTCIRQ INT ATD7 ATD6 ATD5 ATD4 VDD GC131 Peripheral Controller 5 2 2 HT131 Peripheral Controller Pin Descriptions This section describes the pins of the HT131 Peripheral Controller The pin identification numbers correspond with those shown in Figure 5 2 HT131 Peripheral Controller pinouts Pin Pin Pin Symbol Number Type Description AEN1 55 O Address Enable DMA Controller 1 When active AEN1 indicates that the system is performing an 8 bit DMA transaction AEN2 56 O Address Enable DMA Controller 2 When active AEN2 indicates that the system is perfor
136. a peripheral board on the backplane is driving address commands refresh and data PA2 to PAI6 45 49 Processor Address Lower and Upper lines 2 22 These 51 59 lines are latched to form the AT Address lines They are 62 used to generate the MA lines for the DRAM PA17 to 63 to I PA22 68 PA23 39 I PA24 156 I PBENO to 122 to Processor Byte Enables Indicates the byte on which PBEN3 125 there is valid data Used to generate A0 LBHE and A1 Normally an input but during DMA is an output PDO to 2 9 Processor Data Lines PD31 11 18 21 29 31 37 PGVIOL 93 O Page Violation This signal is the result of a COMPARE of the current address row and the row latched into the DRAMs When HIGH it indicates that the two are different thus allowing the processor access beyond the page boundary RASO to 74 to I Row Address Strobe HT133 uses these signals to latch RAS3 77 the latest page value for the DRAMs Used in PGVIOL calculations REFRESH 69 I REFRESH Indicates that the current HLDA cycle is a DRAM refresh and the refresh addresses are on ATAO 11 RESET 38 I RESET Initializes all internal registers to a known value 94 GC133 Bus Bridge Interface Pin Symbol Pin Number Pin Type Description SAB646 TESTIN TSTOUT VSS 149 127 128 19 40 61 80 92 102 120 140 160 1 10 20 30 41 50 60 79 91 101 119 141
137. active low Schmitt input tells the controller that the head is at track zero of the selected disk drive INDEX This active low Schmitt input signals the beginning of a track WRT PRT This active low Schmitt input indicates that the disk is write protected Any command that writes to that disk drive is inhibited when a disk is write protected VCCA This pin is the 5V supply for the analog data separator circuitry This pin is the 5V supply the digital circuitry RESET Active high input that resets the controller to the idle state and resets all the output lines to the disk drive to their disabled state The Drive Control register is reset to 00 The Data Rate register is set to 250 kb s The Specify command registers are not affected The Mode Command registers are set to the default values Reset should be held active during power up To prevent glitches activating the reset sequence a small capacitor 1000 pF should be attached to this pin 188 DP8473 Floppy Disk Controller Symbol Function WR Active low input to signal a write from the microprocessor to the controller RD Active low input to signal a read from the controller to the microprocessor CS Active low input to enable the RD and WR inputs Not required during transfers This should be held high during DMA transfers AO A1 A2 Address lines from the microprocessor This determines which registers the microprocessor is accessing as shown in Tab
138. ages Run time messages System board errors Beep codes for fatal errors Beep codes for non fatal errors B 2 POST AND BOOT MESSAGES The POST displays messages to indicate errors in hardware software or firmware or to provide other information If the POST can display a message on the video display screen it will beep the speaker twice as the message appears However when an error occurs before the video display is initialized the POST cannot display messages on the screen POST sounds a series of beeps instead The next three sections provide a general grouping of messages with each group arranged in alphabetical order Each message is accompanied by a short paragraph describing the message and a recommended solution to the problem Italics indicate variable parts of a message such as memory addresses These variable parts at the message may differ at each occurrence 239 Messages B 2 1 Post and Boot Error Messages Message Possible Cause Solution Message Possible Cause Solution Message Possible Cause Solution Message Possible Cause Solution Message Possible Cause Solution Message Possible Cause CACHE memory failure Disabling CACHE Strike the F1 key to continue F2 to run the Setup utility The cache memory is defective Contact your service representative Diskette drive 0 seek failure Drive A has either failed or is missing Check that drive A is present
139. ailing Check that all SIMMs are installed correctly Check expansion board memory if installed and check the SIMM jumpers on the system board Memory test terminated by keystroke The spacebar was pressed during the memory test Reboot the system if you want to rerun the self test Strike the F1 key to continue F2 to run the Setup utility The self test detected an error prior to boot Pressing the F1 key lets the computer try to boot Pressing F2 runs the Setup utility 245 Messages 3 RUN TIME MESSAGES Run time messages are displayed if an error occurs after the boot process is complete Message Possible Cause Solution Message Possible Cause Solution Message Possible Cause Solution Message Possible Cause Solution card parity interrupt at address hex value 5 hut off NMI R eboot other keys to continue A peripheral board has failed Type S to shut off the nonmaskable interrupt NMI This will temporarily allow you to continue If the problem persists contact your service representative Memory parity interrupt at address hex value Type S hut off NMI R eboot other keys to continue One or more memory modules has failed Type S to shut off the nonmaskable interrupt NMI This will temporarily allow you to continue Check the installation of all SIMMs If the problem persists contact your service representative Unexpected HW interrupt at address he
140. all filter configurations 250 kb s and 300 kb s share the same filter Figure 13 5 Typical Configuration for Loop Filters for the DP8473 Showing Component Labels 194 DP8473 Floppy Disk Controller To ensure optimal performance the data separator incorporates several additional circuits The quarter period delay line is used to determine the center of each bit cell A secondary PLL is used to automatically calibrate the quarter period delay line The secondary PLL also calibrates the center frequency of the VCO To eliminate the logic associated with controlling multiple data rates the DP8473 supports the connection of three filters to the chip via the FGND250 and FGND500 pins filter ground switches The controller chooses which filter components to use based on the value loaded in the Data Rate Register If 500k MFM is being used then the FGND500 is enabled FGND250 is disabled If 250 or 300k MFM is being used the FGND250 pin is enabled and FGND500 is disabled For 1 Mb s MFM both FGND pins are disabled Figure 13 5 shows several possible filter configurations For a filter to cover all data rates Figure 13 5 the DP8473 has a 1 Mb s filter always connected and other capacitor filter components for the other data rates are switched in parallel to this filter The actual loop filter for 500 kb s is the parallel combination of the two capacitors C2C and C2B attached to the FGND500 pin and to ground The 250 300 kb s f
141. allel Port Printer Data Read strobe Parallel Port Printer Status Read strobe Parallel Port Printer Control Register Read strobe Parallel Port Printer Data Write strobe Parallel Port Printer Control Register Write strobe Power Good Indicates that the power levels are ready and stable The machine is held in reset until PWRGOOD is active This signal must become active before RESET goes inactive Refresh Cycle for DRAMs Indicates the cycle is actually a REFRESH cycle System Reset When active the system is in a reset state GC131 Peripheral Controller Pin Pin Pin Symbol Number Type Description RTCAS 154 Real Time Clock Address Write strobe RTCDS 155 Real Time Clock Data Read strobe 47 Real Time Clock Interrupt Request Used as IRQ8 to the Interrupt Controller in the HT131 Controller It is active LOW RTCRW 156 O Real Time Clock Data Read Write strobe ISERCS1 108 Chip Select for Serial Port 1 Implemented on the system board ISERCS2 109 O Chip Select for Serial Port 2 Implemented on the system board 144 Memory Read command for addresses within the low 1 Mb provided for the I O channel SMEMW 143 O Memory Write command for addresses within the low 1 Mb provided for the I O channel SPKRDATA 110 O Speaker Output signal to a transistor driving a speaker It is generated by Counter 2 of the 8254 Timer function and gated by bit 1 of
142. and Connector 2 3 10 847 Floppy Disk Controller and Connector 2 3 11 Special Board Interfaces 23 12 Firmware s e ra obo bend eee a ad SU Un n sad asuti CHAPTER 3 CENTRAL PROCESSING CORE 3 1 INTRODUCTION dis edd cds RE ted werdet eo nena S RAS C E RO eke 22 OVERVIEW ug duri reas po bs A ee Bo CPU PE UU STO retineo Pu inc 331 Real Mode Architecture cio looo EY 332 Protected Mode Architecture oe LED EUR dee 2993 Virtual 8086 Moe ode sre Pe Koss pa V A ERI 3 34 CPU Signals Yau sag l none da oe RACE cu Pi 335 Basic CPU Bus Operations iore ee p ie A did d eee lea Serge ns 34 NUMERIC COPROCESSOR 2 2 2 19 34 1 387 Data Types Henan de Vee 20 342 387 Programming Interface 20 343 Weitek 3167 System Level Considerations 21 35 CACHE MEMORY REP ROLL e ALPE A 22 36 DATA AND CONTROL BUFFERS he em snd toe Rade ea 22 CHAPTER 4 ISA BUS INTERFACE 44 INTRODUCTION ua ae Oe eed is Eds bh E reds SURE TAG e Dese 23 42 B S AGENTS 35 E 23 42 1 Requesting Agents
143. and bus availability Numeric coprocessor register space can be used as a stack or fixed register set 19 Central Processing Core 34 1 387 Data Types The 387 numeric coprocessor fully implements ANSI IEEE 754 standard for binary floating point arithmetic It works with seven data tupes word integer short integer long integer packed decimal single real double real and extended real refer to Table 3 1 The 387 directly extends the CPU instruction set Extending the instruction set includes trigonometric logarithmic exponential and arithmetic instructions for all data types Table 3 1 387 Numeric Coprocessor Data Types Data Type Bits Digits Approximate Range Word integer 16 4 32 768 lt x lt 32 767 Short integer 32 9 2x10 lt x lt 2 10 Long integer 64 18 9 108 lt x lt 9 1018 Packed decimal 80 18 9 99 lt x x 9 99 18 digits Single real 32 6 7 1 18 1038 lt x 340 10 Double real 64 15 16 2 23 10 308 lt x lt 180 10 8 Extended realt 80 19 330x10 92 lt x lt 1 21x10 Equivalent to double extended format of IEEE STD 754 34 2 387 Programming Interface The 387 functions as an I O device through the I O ports It uses hex addresses 8000FC for sending upcodes and operands and also receiving and storing results The CPU outputs address 8000F8 when writing a command or reading status and outputs address 8000FC when writing or reading data The CPU has three i
144. and the floppy disk is inserted properly Most importantly check that the cables are installed correctly If the drive floppy disk and cables appear to be satisfactory then drive A may have failed If the problem persists contact your service representative Diskette drive 1 seek failure Drive B has either failed or is missing Check that drive B is present and the floppy disk is inserted properly Most importantly check that the cables are installed correctly If the drive floppy disk and cables appear to be satisfactory then drive B may have failed If the problem persists contact your service representative Diskette read failure strike F1 to retry boot F2 for Setup utility A nonbootable or defective floppy disk or the drive heads may need cleaning Replace the floppy disk with a bootable floppy disk or another copy and try again Clean the floppy disk drive heads in necessary Diskette subsystem reset failed The floppy disk drive control cable has failed Check the floppy disk drive control cable If the problem persists contact your service representative Display adapter failed using alternate The monitor type jumper is set incorrectly or the primary monitor controller has failed 240 Messages Solution Message Possible Cause Solution Message Possible Cause Solution Message Possible Cause Solution Message Possible Cause Solution Message Possible Cause Solution M
145. ands FBH FCH and FDH instruct the Keyboard to set individual keys to typematic make break and make respectively The keyboard responds with an acknowledge clears its output buffer and prepares to receive key identification The controller identifies each key by its scan code value as defined in scan code set 3 Only scan code set 3 values are valid for key identification The type of each identified key is set to the value indicated by the command RESEND FEH The controller transfers the resend command when it detects an error in any transfer from the keyboard It requests the keyboard to resend a code that was detected as an error This command transfers only after a keyboard transfer and before the controller allows the next keyboard output When a resend command is received the keyboard transfers the previous output again If the previous output was resend the keyboard transfers the last byte before the resend command RESET FFH The controller issues the reset command to start a program reset and a keyboard internal self test The keyboard responds with an acknowledge code and ensures the controller accepts the acknowledge code before executing the command The controller raises the clock and data lines for a minimum of 500 us after receiving an acknowledge code from the keyboard The keyboard remains disabled from the time it receives the reset command until the controller responds to the acknowledge code or until another command
146. ansceiver Controls Signals 139 937 Status and Control Signals 140 938 Support Signals 140 94 PROGRAMMABLE REGISTERS ANDA INSTRUCTION SET 141 941 Programming Overview 141 942 Control Register 143 943 Configuration Register 144 944 Status Register 145 945 Registers 2 22 4 145 946 Initial Values es cheapie 147 CHAPTER 10 1287 REAL TIME CLOCK RTC 101 INTRODUCTION haces Fed o Y S Ra ede erbe RES 149 102 RTC OPERATIONS 149 103 RTC INTERNAL ADDRESSABLE LOCATIONS 151 10 3 1 Time Calendar and Alarm Bytes 152 104 STATUS REGISTERS tate hase uses 153 104 1 Status Register A OAH 154 104 2 Status Register OBH 154 1043 Status Register C OCH 156 1044 Status Register D ODH 156 105 CONFIGURATION BYTES 45 a
147. any one time with the exception of locked operations which always cause the cache to be transparent The operating system must ensure that no two bus masters have concurrent access to a region of memory When a region of memory is made available for access by the processor its cache must be cleared of potentially stale entries for that region Clearing this stale data can be performed by issuing an invalidate all instruction to the cache controller For example a DMA device in a multiprocessor system may be about to load a page of data from a disk after a request from the operating system The operating system must ensure that no other bus master MPU or DMA device has concurrent access to the physical page Once the transfer is complete the processor must have any potentially stale data removed from its cache Hardware Mechanism for Coherency The A38202 can also maintain coherency via bus watching also called snooping The A38202 monitors system bus cycles and when a write cycle by another bus master such as a DMA controller is detected the address on the system bus is sampled This address is then looked up in the cache directory and if present the entry associated with that address is invalidated This will force the A38202 to fetch data from main memory the next time that address is accessed ensuring that the 80386 gets the correct data from that address 9 24 Noncachable Regions The A38202 allows three separate areas of the 32 b
148. ate at 90 AC to 132V AC or 180V AC or 264V AC signal phase Input current will be less than 5 0 Ampares at full load output condition an minimum voltage 14 2 2 Output Characteristics DC Output Output Wire Tolerance Load Current Voltage Color Accuracy Minimum Maximum 5 RED 3 5 0 Adc 30 12 Vde YELLOW 5 0 5 Adc 10 0 Adc surge 14 0 Vdc 12 BLUE 9 0 0 5 5 9 0 Adc 0 5 5 5 POWER GOOD OPTION Note The wire color of GND line is BLACK 209 Power Supply AC Output Output Tolerance Load Current Voltage Accuracy Minimum Maximum 115 Vac 90 Vac 132 Vac 0 Aac 5 0 230 Vac 180 Vac 264 Vac 0 Aac 2 5 Aac 14 23 Voltage Adjustment The 5V DC output will be adjustable from 4 75V DC to 5 25V DC The 5 volts output at the power supply output connector should be adjusted to between 4 9 volts to 5 1 volts by the manufacturer for typical load operation 14 24 Over Voltage Protection This protection is effective on the 5V DC and 12V DC outputs If an overvoltage fault occurs internal to the power supply the power supply shall shutdown before 5V DC and 12V DC output exceeds 130 of its nominal value 143 PIN ASSIGNMENTS Disk Drive Connector Pin Connector Voltage V DC 1 12V DC 2 3 P5 P8 GND 4 5V DC 1 5V DC 2 3 P4 GND 4 12V DC DC Fan Connect
149. ation ports configured as COMI and COM2 Both serial ports are available on connector P20 and one parallel port is available on P22 Board Overview 2 38 8742 Keyboard and PS 2 Mouse Controller The keyboard connects to the system board through a bidirectional synchronous serial port The bidirectional serial interface converts signals and sands the data to and from 101 key keyboard A mouse can be connected via a mini DIN PS 2 style connector on the system board 2 39 IDE Interface Logic and Connector The system mother board contains IDE Intelligent Drive Electronic logic and support circuitry and connector designated as P18 23 10 8473 Floppy Disk Controller and Connector The system mother board contains DP8473 floppy disk controller unit and connector designated as P15 2 3 11 Special Board Interfaces The system board incorporates four special interfaces the keylock interface the speaker interface the reset interface and the diagnostic LED interface 23 12 Firmware The system board firmware consists of a power on self test POST a setup program and Phoenix Technologies basic input output system BIOS POST runs automatically and checks the CPU keyboard display and system memory each time the system is turned on a rebooted The setup program is contained in the ROM BIOS on the system board and is used to store configuration information The information can be changed at any time by running setup program The type o
150. bit cycle to N 2 5 SYSCLK periods where is the number of wait states that the accessed device requests Since the DMA controller operates off of a 4MHz clock DMA cycles are extended in multiples of 2 SYSCLK periods 8005 84 5 Oscillator Output is a 50 percent duty cycle clock signal with a frequency of 14 31818MHz 8405C is not synchronous to either SYSCLK or any other signals on the ISA bus so it must not be used in applications which require synchronization to the ISA bus 84OSC is intended to be used in timing or counting operations only 445 Interrupt Signal Group The interrupt signal group consists of a set of signals that can be used by a replying agent to obtain interrupt service from a requesting agent IRQ D Asserting the IRQ 15 14 12 09 07 03 Interrupt Request line requests an interrupt The line must remain asserted until the interrupt is acknowledged by the appropriate software interrupt service routine ISA Bus Interface 446 Signal Group These signals control DMA service and transfer of bus ownership from the PRA to an SRA DRQ I 7 5 3 0 Direct Memory Access Request signals are asynchronous channel requests used to gain either DMA service or control of the ISA bus from the PRA DMA service or bus control can be attained by asserting DRQ line and keeping it aserted until the corresponding DACKn line is aserted by the PRA When SRAs wish to gain control of the ISA b
151. ble on the 48 pin DIP DP8473N J versions Note 2 See Figure 4 for filter description Note 3 Total transistor count is 29700 approx Figure 13 2 DP8473 Functional Block Diagram 187 DP8473 Floppy Disk Controller 133 PIN DESCRIPTIONS Symbol Function MTR2 This is an ctive low motor enable line for drive 2 which is controlled by the Drive Control register This is a high drive open drain output GNDD This pin is the digital ground for the disk interface output drivers WDATA This is the active low open drain write precompensated serial data to be written onto the selected disk drive This is a high drive open drain output DIR This output determines the direction of the head movement low step in high step out When in the write or read modes this output will be high This is a high drive open drain output DR1 This is an active low drive select line for drive 1 that is controlled by the Drive Control register bits DO D1 The Drive Select bit is ANDed with the Motor Enable of the same number This is a high drive open drain output DRO This is an active low drive select similar to DR1 line except for drive 0 MTR1 This is an active low motor enable line for drive 1 Similar to MTR2 MTRO This is an active low motor enable line for drive 0 Similar to MTR2 HD SEL This output determines which disk drive head is active Low Head 1 Open high Head 0 This is a high drive open drain output TRKO This
152. board The controller transfers data to the keyboard in the same serial format used to receive data from the keyboard Before the controller transfers data to the keyboard it checks the keyboard and determines whether it is transferring data on not If the keyboard is transferring data but has not reached the tenth clock signal the controller overrides the keyboard output by setting the keyboard clock line inactive If the keyboard transfer is beyond the tenth clock signal the controller waits until the keyboard completes its transfer before transferring data If the controller overrides the keyboard output or if the keyboard is not transferring data the controller sets the clock line inactive for more than 60 us while preparing to transfer data When the controller transfers the start bit the clock line goes active Each controller command or data transmission to the keyboard requires a response before the controller its next output After the keyboard receives a controller command it returns an acknowledge code to the controller If the keyboard response is invalid or has a parity error FEH is placed in the controller output buffer and the transmit time out or parity error bits are set in the status register The controller sets a programmed time limit 20 ms to 25 ms for the keyboard to respond If the keyboard cannot complete the send out data process within this time period the controller places FEH in its output buffer and sets the tra
153. board 32 Bit RAM Figure 6 3 HT132 Memory Controller Memory Map 71 GC132 CPU Memory Controller s s J J 22 A Definition of Offboard Memory Offboard or backplane memory is that memory space where EPROM or DRAM is not located Conversely if it isn t EPROM or DRAM space then it is backplane memory space Backplane space includes all of the vast area above DRAM to the 4Gb top Backplane is assumed to be either eight or sixteen bits in width as determined by the status of the MEMCSI6 signal 63 2 MBEN and Non DOS Operation The ATLAS Chip Set has programmable configuration bits as described later in Chapter 8 The Configuration Registers Of these MBEN meaning Middle BIOS enable is used to alter the EPROM memory space when applications are run under operating systems other than DOS MBEN s purpose is to enable and disable the EPROM BIOS at memory space FF0000h This as shown in Figure 61 removes Middle BIOS from memory It s a useful feature When UNIX is used as the operating system and with 24Mb of DRAM in use middle BIOS is not needed When removed a contiguous DRAM space is made available Without the MBEN feature an inconvenient hole at FF0000h would otherwise exist o a FFFFFFFFh UPPerBIOS ip FFFFOO00h 4 Gb Esse This EPROM space is removed if MBEN is inactive The space is replaced with memory MS J FFFFFFh 16 Mb sss
154. by the A38202 M Multiple Match bit 2 Indicates that a multiple match error occurred in the tag RAMS 945 Noncache Registers Noncache Control Register This register contains 6 bits which control the enabling of each noncache descriptor for read or write access Note that setting a read enable bit forces the corresponding write enable bit to be set The format of the register is shown in figure 9 6 RIESE SEIES EVES Figure 9 7 Noncache Control Register 145 The defined NONCACHE CONTROL REGISTER as follows R2 0 Read Enables bits 2 0 These bits enable their corresponding noncache region descriptor for read accesses When one of these bits is set it forces the corresponding write enable to be set as well W2 0 Write Enables bits 6 4 These bits enable their corresponding noncache region descriptor for write accesses Noncache Region Descriptors There are three descriptors 00 D1 and D2 enabled by the corresponding bits in the noncache control register The noncache descriptors consist of two registers a bottom register and a top register see figure 9 7 These two registers define a region of addresses which is compared against the most significant bits of physical address For descriptors D1 and D2 these registers are 16 bits wide allowing the region to be positioned on any 64kB boundary Descriptor DOS registers are 20 bits wide allowing the region to be positione
155. characters per second Where C Binary value of bits 5 and 6 default equals 500 ms A Binary value of bits 2 1 and 0 B Binary value of bits 4 and 3 T Interval from one typematic output to the next ENABLE F4H When the keyboard receives the enable command it responds with an acknowledge code clears its output buffer clears the last typematic key and starts scanning 178 1287 Real time Clock RTC DEFAULT DISABLE F5H The default disable command resets all conditions to the power on default state The keyboard responds with an acknowledge code clears its output buffer sets the default key types and typematic rate delay and clears the last typematic key The keyboard stops scanning and waits for further instructions from the controller SET DEFAULT F6H The set default command is similar to default disable command F5H However the keyboard continues scanning instead of stopping and waiting for further instructions SET ALL KEYS F7H F8H F9H FAH The sets all keys commands F7H F8H F9H and FAH instruct the keyboard to set all keys to typematic make break make and typematic make break respectively The keyboard responds with an acknowledge code clears its output buffer sets all keys to the type indicates by the command and continues scanning Although these commands are sent using any scan code set they affect only scan code set 3 SET KEY TYPE FBH FCH FDH The set key type comm
156. chip with integral lithium battery Floppy Disk Controller 8473 Floppy disk controller supporting 3 5 and 5 25 drives Ports One parallel two serial ports and one PS 2 mouse port are embedded Numeric Coprocessor Socket A socket is provided for INTEL 80387 or WEITEK 3167 coprocessor 1 3 2 Floppy Disk Drive 5 25 FDD half height 1 2MB formatted 96 TPI Tracks Inch 3ms track to track access time 500 kbits sec transfer rate 35 FDD 1 H x4 W x5 9 D 144MB 720KB formatted 135 TPI Tracks Inch 6ms track to track access time 500 kbit sec transfer rate 1 44MB mode 250 kbit sec transfer rate 720KB mode 133 Graphics Adapter Monochrome Graphics Adapter supports monochrome graphics mode 32KB of video memory uses industry standard 9 pin D connector Text mode 720x340 resolution 7x9 cell characters in a 9x14 cell character block supports PC attributes underline reverse and highlight Graphics format 720x340 dot addressable pixels System Specification Enhanced Graphics Adapter supports enhanced color graphics mode 256KB of video memory uses industry standard 9 pin connector Text mode 80 charx25 lines resolution 8x14 character box Graphics format 640x350 dot addressable pixels 16 color graphics from a pallet of 64 colors Video Graphics Array All video modes available in the IBM Monochrome Display Adapter IBM Color Graphics Adapter and IBM Enhanced Graphics Adapter are suppor
157. ck to itself MBSHADOW Uses INDEX 00h Bit 7 When cloning is complete the program can set Bit 7 of INDEXOOh to T to activate high speed Middle BIOS access The physical memory used for shadowing the Middle BIOS is located at FF0000h FFFFFFh for Type 27256 EPROMs Location FE0000h FFFFFFh for Type 27512 EPROMs The system must have enough installed RAM to populate this region of the memory map It should be noted that the cloning of Lower BIOS has no effect on Middle BIOS nor does Middle effect Lower BIOS If both BIOS systems are to be executed from shadow RAM both Lower and Middle BIOS must be explicitly copied Caution The combined use of both the shadow RAM feature and the REMAP feature if Bit 5 of INDEXOTh is set to 1 may cause the chip set to lock up That very effectively crashes the host system 644 Window 4 Upper BIOS Shadowing of Window 4 is not possible 7 GC132 CPU Memory Controller ee 6 5 USE THE REMAP FEATURE TO SAVE UNUSED RAM SPACE In the standard AT memory map configuration address space from A0000h to FFFFFh is normally reserved for device and ROM usage See Figure 6 3 When more than 640K of memory is installed on an ATLAS Chip Set based system RAM that might otherwise be mapped into the device ROM region is blanked out and is not accessible For cost sensitive applications this represents an effective loss of up to 384K of expensive RAM memory This region o
158. combination of Bits 3 and 2 select the following 0 0 One bank of DRAM enabled interleave OFF 0 1 Two banks of DRAM enabled interleave ON 1 0 Not permitted 1 1 Four banks of DRAM enabled interleave ON 7 See EMS page The settings of Bits 7 through 4 specify a 64k 6 Descr hole of OFFBOARD RAM not DRAM starting at the 5 iption coded value The default settings are 4 Bit 7 1 Bit 6 0 Bit 1 Bit 0 meaning 71010 This translates to a 64k EMS hole that starts at Figure 8 4 INDEX03h DRAM Configuration Note In conjunction with the setting of INDEXO3h used to select the use of either 256K 1 Mb DRAMs INDEX10h must also be similarly programmed If not done the system will not operate properly 103 Configuration Registers of the GCK131 Chip Set INDEX04h DRAM configuration Banks 0 1 2 3 Default value FFh This configuration register is available to set up the timing of RAS and CAS signals to the DRAMS for Banks 0 through 3 The delays shown below are programmed as multiples of CLKIN cycles RAS delay is measured from the rising edge of CLKIN during aDs active The register settings as programmed with INDEx04h are used for Banks 0 through 3 of the system unless by INDEX02h overrides have been selected for or more banks CAS READY Next Operation RAS CAS Cas Recovery Delay Delay Active Time RAS Precharge Figure 8 5 DRA
159. control of the CPU and memory include timing synchronization addressing parity bus conversion and AT bus module 57 GC132 CPU Memory Controller SLOWCLK FASTCLK CLKIN SYSCLK PROCCLK RESET 387 PA BUS WR DC MIO 1 5287 SPA20 ADS RASO 3 EXRASO 1 READY INA PDO 31 PARDATOO 3 PARITY TIMING BUS Synchroniz ation Module i Address Module PP gi Timing Generator ee Parity Detect and Generate d CONTROL BUS 16 to 8 Bit Bus Conversion CAS Generator Coprocessor Interface Bus Module Registers Configuration STEN PEREQ386 ERROR386 MEMR MEMW TOW BALE DBEN LWEN CLK646 SAB646 CONVAO LBS16 BBDIRO 1 4 ICASA CASB ICASC CASD CONFIGAS CONFIGDW CONFIGDR PDO 7 Figure 6 1 GC132 CPU Memory Controller Block Diagram 58 GC132 CPU Memory Controller 6 2 1 132 CPU Memory Controller Pinouts The pin connections for the HT132 CPU Memory Controller are shown in Figure 6 2 The pins are numbered sequentially in a counter clockwise direction from the index mark as viewed from the botton of the chip VDD BDIRO BBDIR1 1 IBBEN2 BBEN3 IBBENA REFRESH ADDRSWT ICASD ICASB ICASA IEXRAS1 EXRASO RAS3 IRAS2 NC NC VSS VDD IRASI RASO PGVIOL INA READY
160. controller for Intel 80386 based systems The Microcache provides high levels of integration and functionality It interfaces directly to the 80386 no additional support logic is required Because of its 80386 like bus interface the A38202 can be added to existing 80386 based designs with a minimum of external logic The 80386 operating with the A38202 Microcache runs with zero wait states in a cache read hit cycle If the data is not present in the cache it is fetched from main memory by the Microcache controller Table 9 1 summarizes the cache parameters which are implemented for the A38202 Table 9 1 Microcache Parameters Parameter Value Cache size 32 64 or 128KB Block size 64 128 or 256 bytes Subblock size 4 or 16 bytes Number of groups 2 Number of tags 512 Cache Structure The A38202 Microcache memory consists of four to sixteen depending on cache configuration static RAMS that contain the cache code and data The A38202 has 18 kbits of static RAM on chip tag memory which is used as a directory of presence information for the code and data being held in the cache memory 127 Associativity The A38202 Microcache implements a cache which may be direct mapped or 2 way set associative Set associativity is a caching technique in which a number of possible locations exist in the cache memory for the block associated with any particular address The number of locations is
161. cted when it s Motor Enable is active See Table 13 4 13 54 Data Rate Register Write Only D7 D2 Not used D1 DO Data Rate Select These bits set the data rate and the write precompensation values for the disk controller After a hardware reset these bits are set to 10 250 kb s They are encoded as shown in Table 13 5 1355 Disk Changed Register Read Only D7 Disk Changed This bit is the latched complement of the Disk Changed input pin If the DSKCHG input is low this bit is high 06 00 These bits are reserved for use by the hard disk controller thus during a read of this register these bits are TRI STATE 203 DP8473 Floppy Disk Controller 136 RESULT PHASE STATUS REGISTERS The Result Phase of a command contains bytes that hold status information The format of these bytes are described below Do not confuse these register bytes with the Main Status Register which is a read only register that is always available The Result Phase status registers are read from the Data Register only during the Result Phase 13 6 1 Status Register 0 STO D7 D6 Interrupt Code 00 Normal Termination of Command 01 Abnormal Termination of Command Execution of Command was started but was not successfully completed 10 Invalid Command Issue Command Issued was not recognized as a valid command 11 Ready changed state during the polling mode D5 Seek End Seek or Recalibrate Command completed by the Controller Used durin
162. ction Primary Initiates Memory access Requesting agent access DMA access Global refresh Responds to Interrupt request DMA request Bus arbitration request Secondary Initiates Memory access Requesting agent access Responds to Global refresh Gains Bus Ownership by DMA request Assuming bus ownership on DMA grant Assuming responsibility for refresh initiation Replying agent Responds to Memory access I O access access Global refresh Seeks PRA serice through Interrupt request request 24 ISA Bus Interface 43 GENERAL ISA BUS ATTRIBUTES The ISA bus has several specific attributes as follows The memory address space is 24 bits long and the data path is 16 bits wide providing a 16M memory address space with 8 and 16 bit data transfers The I O address space is 16 bits long and the data path is 16 bits wide providing a 64K I O address space with 8 bit and 16 bit data transfers nterrupt lines suport signalling between agents on the bus and the PRA The DMA capability allows 8 bit or 16 bit data transfers between memory and I O agents without direct intervention of the CPU on the PRA The PRA refershes all agents with refresh cycles The PRA initiates refresh cycles at the request of an SRA that is in control of the bus in order to maintain integrity of the data in system DRAM Multiple agent support is provided The ISA bus Suports up to five agents including
163. ction as EPROM shadowing and Video shadowing 1 Mb lL FFFFh 640K 0 40 256 5 bank No shadowing No shadowing No REMAP No REMAP 1 384 Mb 1 640K 256K DRAMs One bank One bank No shadowing No shadowing REMAP ENABLED REMAP ENABLED Figure 6 7 The Effects of REMAP with One Bank of RAM 80 GC132 CPU Memory Controller 6 6 2 Two Banks of DRAM As soon as two banks of DRAM are recognized the ATLAS Chip Set starts interleaving Interleaving takes place on double word boundaries The memory map Figure 6 8 shows two configurations banks of 256K DRAMs and banks of IMb DRAMs Shadowing works as before but REMAP does not In order to allow the internal address decoder to be as simple as possible the REMAP feature is implemented only on smaller configurations For two banks of 1Mb DRAMs REMAP is not implemented It is however implemented for two banks of 256K DRAMs 8 Mb 7FFFFFh For either 256K 1 Mb the two banks interleave on double word boundaries 2 384 Mb 25FFFFh 1FFFFFh FFFFFh 2Mb FFFFFh 1Mb d FFFFFh 1 Mbt FFFFFh A0000h 640K AO0000h 640K A0000h 0 0 0 0 0 256K DRAMs 1 Mb DRAMs Two banks Two banks Two banks No shadowing No shadowing No shadowing No REMAP REMAP ENABLED REMAP ON or OFF In all cases INTERLEAVE is ACTIVE Figure 6 8 The Effects of REMAP with Two Banks of RAM 81
164. d 34H Table 10 23 CPU Speed 34H Bit Function 7 3 Reserved 2 0 CPU speed 105 18 FXD Type 49 Parameters 35H 3CH Table 10 24 FXD Type 49 Parameters 35H 3CH Bit Function 20H Cylinder low byte 35H Cylinder low byte 36 Cylinder high byte 37H Number of heads 38H Write pre compensation start cylinder low byte 39H Write pre compensation start cylinder high byte 3AH Landing zone cylinder low byte 3BH Landing zone cylinder high byte 3CH Sectors per track 164 11 COMMUNICATION PORTS 11 1 INTRODUCTION The chapter provides reference data for two RS 232C serial communication ports and one parallel printer port on the system board Included are all addresses and interrupt levels 11 2 SERIAL COMMUNICATION PORTS Two 82510 asynchronous serial controllers provide interfacing between the communication ports and the CPU Refer to Table 11 1 for selection of port addresses and interrupt levels Table 11 1 Selection of Addresses and Interrupt Levels Port Designation Address Interrupt 1 COM1 3F8 3FFH IRQ4 2 COM2 2F8 2FFH IRQ3 11 2 1 CPU Interfacing Two 82510 controllers provide the interfacing between the communication ports and the CPU The 82510 is a demultiplexed bus interface using a bidirectional buffered 8 bit data bus and a 3 bit address bus Thirty five registers divided into four banks control and configure the 82510 controllers 11 2 2 Connecto
165. d on any 4kB boundary The bottom register defines the lowest address which is to be made noncachable The top register defines the highest address which is to be made noncachable The processor address is compared against the contents of the two registers and any address which satisifies bottom lt address lt top is considered to be noncachable Thus setting the contents of the top register to be less than that of the bottom register effectively disables a descriptor 19 16 15 8 7 0 MSB D1 D2 Bottom Register 19 16 15 8 7 0 MSN MSB 00 D1 D2 LSB Register Figure 9 8 Noncache Descriptor Registers 146 To program the Noncache descriptors use the LOAD NONCACHE DESCRIPTOR instructions These instructions allow the processor to change the base addresses and lengths of the noncache spaces by loading data into the registers a byte at a time Note When loading the Noncache Descriptors caching should be temporarily disabled by clearing the C bit in the control register After the descriptors have been changed caching should be reenabled and an INVALIDATE ALL instruction should be issued to ensure that no cache coherency problems occur 94 6 Initial Values When the PWRGOOD input to the A38202 is asserted the internal registers have the values shown in Table 9 4 The initial value of the CONTROL REGISTER 30H tells the A382
166. d procedure will be saved into KEYIN DAT file 3 If you don t save you can use them after Power Off 8 FUNCTUIN 1 Error Rec It initializes or creats ERROR REC file and clear error record in memory 2 It initializes KEYIN DAT and adjsut according to System Configuration 9 FUNCTION 1 It displays error record on screen in following format example Error No Error Code Description Date Time 0001 12 00D4 BIOS ROM Checksum Error 1989 01 04 15 11 1 Error No Error number 2 Error Code 12 sort of error BIOS ROM Checksum Error 00D4 detail error condition refer to HELP 3 Description Describes the error briefly 4 Date Time Error occurred time and date A 10 11740349 ESMA FUNCTION It is toggled at every selection and updates DIAG EXE file according to current status If current status is when you re boot diagnostics it runs procedure w o key input It is useful to start burn in test by AUTOEXEC BAT file To switch to state press lt C gt key and press on MAIN MENU 231 Diagnostic A 11 FUNCTION Exit to DOS A 12 ERROR CODE DESCRIPTION A 12 1 System 1 10 System RAM 08 10H High Address Bus Short Error 20H Data Bus Short Error 30H Data Pattern R W Error 31H Parity Error 40H Even Odd Bank Access Error 50H Cell Test Data Error 51H Cell Test Address Error 08 0000H 08 FFFFH Error block in 64K unit 11 Cac
167. disk drive controller and connector Eight I O expansion slots two 8 bit six 16 bit Board Overview ROM based setup program BIOS and power on self test Reset interface Speaker interface Keylock interface Figure 2 1 illustrates the component layout of the system board Figure 2 2 shows a functional block diagram of the system board 38202 80387 LJ 80386 ud E co OOZ E 5 n M ME Floppy connector ROM EVEN 8742 IDE connector DRAM socket 16C452 Figure 2 1 System Board Component Layout Slot Power connector Keyboard connector Mouse connector PIO connector SIO connector Board Overview 27256 16 Bit AT Expansion Slots mm CPU GC131 RTC posse saM L Sere uy CLOCK 1 84MHz Parallel Port GC133 I O Port Bus Bridge Controller Controller 16C452 T Serial Port CLOCK 24MHz GC132 Floppy Disk FDD CPU Memory Controller Controller 8473 Keyboard Keyboard Mouse Controller Me PS 2 Mouse 32 Bit High speed 16 Bit low speed PA and PB Bus ATA and ATD Bus Figure 2 2 System Board Functional Diagram Board Overview 2 3 FEATURE SET DESCRIPTION This section gives a detailed description of the feature
168. e Description 0 0 Five command delays in CLKINs 1 Seven command delays 2 1 Bit 2 Bit 1 The combination of Bits 2 and 1 select the following 0 0 Seven command active times in CLKINs 0 1 Nine command active times 1 0 Eleven command active times 1 1 Thirteen command active times 4 3 Bit 4 Bit 3 The combination of Bits 4 and 3 select the following 0 0 Zero RECOVERY times in CLKINs 0 1 Two RECOVERY times in CLKINs 1 0 Four RECOVERY times in CLKINs 1 1 Six RECOVERY times in CLKINSs 5 1 Reserved Should always be programmed to 1 6 1 Reserved Should always be programmed to 1 7 1 Reserved Should always programmed to 1 Figure 8 10 INDEX07h 16 Bit RAM Configuration 109 Configuration Registers of the GCK131 Chip Set INDEX08h I O access configurations Default value FFh Configuration registers INDEX06h through 09h are available to tailor the timing requirements for various commands of the system An earlier example See INDEX09h to INDEXO9h Tailor timing requirements The timing indicated in the following Figure is related to CLKIN cycles Bit State Description 1 0 11 Bit 0 The combination of Bits 1 and 0 select the following Ten command delay times in CLKINs Twelve command delay times Sixteen command delay times Eighteen command delay times lI li 3 2 w N The combination of Bits 3 and 2 select
169. e following REFRESH Clock divider for FAST speed 0 Divide incoming syscLk by one 1 Divide incoming syscLk by two 0 Divide incoming syscLk by four 1 Divide incoming svsci by eight Figure 8 20 INDEX41h Clock Dividers TURBO Mode 117 Configuration Registers of the GCK131 Chip Set Bit State Description 5 4 Bit 5 Bit 4 The combination of Bits 5 and 4 select the following clock divider for FAST speed 0 Divide incoming syscLK by one 1 Divide incoming syscLk by two 0 Divide incoming syscLk by four 1 Divide incoming svsci by eight 0 Reserved Always program to 0 0 Reserved Always program to 0 NS Note For information regarding non TURBO mode See INDEX40h Indicated by FAST SLOW Pin 130 of the GC131 Controller INDEX42h DMA and REFRESH wait states Default value 00h This configuration register is available to program the number of wait states required in REFRESH and DMA operations In use programmers are to be advised that this index INDEX42h must be adjusted in a sequence after those of INDEX40h and INDEX41h When programming the REFRESH and DMA wait states this INDEX42h uses a four bit binary representation 0 15 of the number of desired wait states in multiples of the clock period programmed INDEX40h and INDEx41h Bit Description REFRESH wait states 3 A Bininary count of the number of wait states of REFRESH 2 c
170. e following message on center of screen Serial Number 1990 0101 0001 Press lt Enter to continue 217 Diagnostic A 2 2 Serial Number 1 2 3 4 Serial number is used to identify the system on testing If you don t want to edit Serial Number just press lt Enter gt If you want to edit you can use lt Cursor gt lt Numeric gt key Edited Serial Number will be saved on diskette 2 3 Caution 1 2 Now you can see following messages lt Notice for successful testing gt a All diskette must be formatted by this program for FDD R W test otherwise R W test will be Skipped b During HDD R W Test all data will be saved Press lt Enter gt to continue Diskette requirements a For FDD R W test all diskette should be formatted by this program b If you want format with option S system transfer first format target diskette by this program next transfer SYSTEM by SYS COM and then copy COMMAND COM on target diskette A 24 Press lt F9 gt key to display System Configuration and press lt 9 gt again for HELP message 2 5 Press lt Enter gt key to continue 218 Diagnostic A 3 DESCRIPTION OF SCREEN amp FUNCTION KEY USAGE A 3 1 Followings MAIN MENU AT System Diagnostics Version 2 00X Current Time 12 15 28 Copyright C SAMSUNG Electronics Co Ltd 1990
171. e output buffer and the typematic key if active When the controller sends the option byte the keyboard responds with another acknowledge code An option byte value of 01H selects scan code set 1 02H selects set 2 and 03H selects set 3 Byte value 00H causes the keyboard to respond with an acknowledge code and send a byte signaling the controller which scan code set is in use READ ID F2H The read ID command requests identification information from the keyboard The keyboard responds with an acknowledge code discontinues scanning and ends the two keyboard ID bytes The second byte must follow completion of the first byte within 500 us After the output of the second ID byte the keyboard resumes scanning SET TYPEMATIC RATE DELAY F3H This command sets the typematic rate and delay The keyboard responds with an acknowledge code stops scanning and waits for the controller to issue the rate delay value byte Once issued the keyboard responds with another acknowledge code sets the rate and delay to the values indicated and resumes scanning The contents of the rate delay value byte following the command determines the parameters for these two functions Bits 4 0 set the typematic rate bits 5 and 6 set the delay parameter and bit 7 is set to zero The following equations show the calculation for the delay and the typematic rate e Delay 1 250 ms 20 e Period T 8 28 x0 00417 seconds Typematic Rate 1 T 20 default is 10
172. e the current cycle is a write A latched version of WR Used to indicate a WRITE operation to the DRAMs Memory Chip Select is 16 Bits Indicates that the current cycle is addressing a 16 bit memory device and the HT132 Controller will not perform an 8 to 16 bit conversion cycle Memory Read Normally an output but during a DMA or MASTER mode cycle it becomes an input and is used for determining the direction and duration of the HT133 Bus Bridge buffers GC132 CPU Memory Controlier Pin Pin Pin Symbol Number Type Description MEMW 27 Memory Write Normally an output but during a DMA or MASTER mode cycle it becomes an input and is used for determining the direction and duration of the HT133 Bus Bridge buffers MIO 9 I Memory or I O status line derived from the 80386 MIO MUXPA20 154 I Multiplex Processor Address 20 When LOW the output SPA20 follows PA20 exactly When HIGH SPA20 is forced LOW INA 146 O Next Address When active the HT132 is requesting that the next cycles address and ADS be issued OWS 119 I Zero Wait State PA2 8 I Processor Address Line 2 Used to determine which bank of DRAM will be interleaved next PA15 to 7 2 I Processor Address Lines 15 Through 25 PA25 21 Used for memory map control 159 156 PA31 155 I Processor Address Line 31 Used for coprocessor interface and the restart vector PARDATOO to 63 Parity Data Out 0 Through 3 During PARDATO3 58 memory read these pin
173. ect directly to an F or AS series 74646 or similar device BDCP is used to latch data on its rising edge DOE controls the output enable on the transceivers DI R controls the direction of the transceivers When DT R controls the direction of the transceivers When DI R is high the transceivers drive the system bus When DT R is low the transceivers drive the 80386 bus 139 9 3 7 Status and Control Signals Cache Miss Indication MISS On a cachable read miss cycle this signal is asserted by the A38202 Its timing is the same as that of the other A38202 local bus cycle definition signals Cache Fault Indication CACHEFAUIT CACHEFAULT is asserted if the A38202 ever detects an internal error After it is asserted the A38202 will treat all accesses as if they were misses regardless of the state of the cache directory It can be cleared by resetting the cache via PWRGOOD executing an INVALIDATE ALL instruction or asserting the FLUSH input Cache Flush FLUSH The FLUSHf input provides a hardware method for making the A38202 execute an INVALIDATE ALL instruction After the directory has been cleared all accesses will be misses until it fills up again Chip Select IOCS This active low signal when asserted indicates to the A38202 that it has been selected in an I O cycle The A38202 will then load or store the currently selected internal register See section 5 2 for more details 9 38 Coherency Sup
174. ed on the falling edge of this signal LA 23 17 represent bits 17 through 23 of the memory address presented on the bus LA 23 17 should be used by 16 bit replaying agents in generation of SRDY 516 and IOCS16 The requesting agent drives LA 23 17 during any transfer cycle LA 23 17 are driven to 0 during I O cycles During Secondary requesting agent cycles LA 23 17 must be vaid throughout the entire transfer cycle and BUSALE is asserted by the PRA The PRA drives LA 23 17 to 0 during refresh cycles SBHE I O SBHE System Bus High Enable is asserted by a requesting agent to indicate a transfer of data on lines D 15 8 BUSALE O BUSALE Bus Address Latch Enable is an address strobe driven by the PRA LA 23 17 are valid when BUSALE is asserted and they may be latched on the falling edge of BUSALE A 19 0 are latched by the PRA on the leading edge of BUSALE during bus cycles initiated by the PRA All agents must be level sensitive with respect to BUSALE This means that although the address signal group signals or decodes generated from them may be latched by agents on the falling edge of BUSALE all agents must monitor the address signal group signals whenever BUSALE is asserted This is especially important during DMA cycles Secondary requesting agent cycles and refresh cycles For all DMA controller cycles including Secondary requesting agent cycles the PRA asserts BUSALE to allow the LA 23 17 address to
175. emory has been configured the chip set will be confused as to which REMAP option 1 2 or 3 to use This may result in erratic system operation 78 GC132 CPU Memory Controller More About REMAP Once the REMAP feature is turned ON 32 bit shadow RAM is not available and any user who attempts this may corrupt the memory map A feature associated with remapping modifies the earlier comment The DRAM located from 640K A0000h to 1Mb FFFFFh is remapped to a different location when REMAP is turned ON Thus there will be no DRAM available to shadow instead shadow will be to the backplane RAM By this process it is possible to use the backplane RAM for shadowing and still also activate the REMAP feature 6 6 MEMORY MAP OF THE DRAM SUBSYSTEM The DRAM control system is made complex by the variety with which the INDEX registers described later in Chapter 8 The Configuration Registers can alter configuration and effect the address space of the DRAMs used in the ATLAS Chip Set The chip set can accommodate 256K DRAMs 1Mb DRAMs From to six banks of page interleave DRAM can be configured And several options exist with respect to the use of address space A Summary of the Available DRAM Configurations A summary of the available DRAM configurations is listed in Figure 6 6 Total DRAM type for each bank Amount Usable
176. ence the widest window margin The controller includes write precompensation circuitry A shift register is used to provide a fixed 125ns early late precompensation for all tracks at 500k 300k 250 kb s 83ns for 1 MB s or a precompensation value that scales with the data rate 83ns 125ns 208ns 250ns for data rates of 1 0M 500k 300k 250 kb s respectively Specifically to support the and PC XT design the Floppy Disk Controller PLUS 2 includes address decode for the A0 A2 address lines the motor drive select register data rate register for selecting 250 300 500 kb s Disk Changed status dual speed spindle motor control low write current and DMA interrupt sharing logic The controller also supports direct connection to the bus via internal 12 mA buffers The controller also can be connected directly to the disk drive via internal open drain high drive outputs and Schmitt inputs In addition to this logic the DP8473 includes many features to ease design of higher performance drives and future controller upgrades These include 1 0 Mb s data rate extended track range to 4096 Implied seeking working Scan Commands motor control timing both standard IBM formats as well as Sony 3 5 ISO formats and other enhancements 185 DP8473 Floppy Disk Controller lt E Q BBE lt A lt 3 2 1 52 5150 49 48 47 PUMP PREN DR2 RDATA DR3 FGND250 FGND500 FILTER GNDA OSC1 OSC2 CLO
177. ess space beginning at address 40000H Enable disable cache bit 1 If C is set to zero the cache is disabled and all memory accesses are treated as noncachable If C is set to one then the cache is enabled BI O Buffer I O Writes bit 3 The bit defines whether I O write cycles should be buffered or not If it is set I O writes are buffered 1387 Ignore 80387 cycles bit 4 When the 1387 bit is set the A38202 will ignore any 80387 cycles i e I O cycles with A31 high IW Ignore Weitek cycles bit 5 When the IW bit is set the A38202 will ignore any Weitek 1167 3167 cycles i e cycles to memory addresses in the region C0000000H CO00FFFFH P Pipelined mode bit 6 The P bit defines whether the A38202 should run the 80386 in pipelined mode When set the A38202 requires the 80386 to run in pipelined mode to perform zero wait state read hits Invalidate all bit 7 When the I is set to one all valid data in the cache is effectively purged by invalidating all tags in the cache Note that setting the D and C bits at the same time is meaningless the C bit takes precedence and the effect is to enable caching 143 94 3 Configuration Register The CONFIGURATION REGISTER tells the A38202 what mode it is operating in Figure 9 5 shows the details of the configuration register E 51 x AS0 x S16 51 x CS0 1 Figure 9 5 Configuration Register The defined CO
178. essage Check to ensure that the monitor type jumper is set correctly Check the primary monitor controller If the problem persists contact your service representative Gate A20 failure The computer cannot switch into protected mode Contact your service representative Hard disk configuration error The specified configuration is incorrect Return the Setup program and enter the correct fixed disk drive type number If the problem persists contact your service representative Hard disk controller failure The drive controller board has failed Check the connections at both ends of the fixed disk control and data cables and reseat the drive controller If the problem persists contact your service representative Hard disk failure or Hard disk read failure strike F1 to retry boot F2 for Setup utility The fixed disk is defective Check the system configuration and drive type and return the Setup utility Check the connections at both ends of the fixed disk control and data cables and reseat the drive controller Check the fixed disk drive jumper and termination resistor If the problem persists contact your service representative Hex value optional ROM bad checksum hex value A peripheral board contains a defective ROM or its address conflicts with another board Replace the ROM or the peripheral board or correct the address confict If the problem persists contact your service representative Invalid confi
179. esult Phase The P reads a series of bytes from the data register These bytes indicate whether the command executed properly and other pertinent information The bytes are read in the order specified in the Command Description Table A new command may be initiated by writing the Command Phase bytes after the last bytes required from the Result Phase have been read If the next command requires selecting a different drive or changing the data rate the Drive Control and Data Rate Registers should be updated If the command is the last command then the software should deselect the drive Note as a general rule the operation of the controller core is independent of how the updates the Drive Control and Data Rate Registers The software must ensure that manipulation of these registers is coordinated with the controller operation During the Command Phase and the Result Phase bytes are transferred to and from the Data Register The Main Status Register is monitored by the software to determine when a data transfer can take place Bit 6 of the Main Status Register must be clear and bit 7 must be set before a byte can be written to the Data Register during the Command Phase Bits 6 and 7 of the Main Status Register must both be set before a byte can be read from the Data Register during the Result Phase If there is information to be transferred during the Execution Phase there are three methods that can be used The DMA mode is used if the syste
180. et update cycle SET bit 1 Abort the update cycle in progress Set to 1 for system initialization 0 Enable normal update cycle of one count per second 6 Periodic interrupt enable PIE bit This read write bit selects an interrupt occurring at a rate specified by the rate and divider selection bits in register A 1 Enable the generation of periodic interrupts 0 Disable the interrupt default Alarm interrupt enable AIE bit 1 Enable the alarm interrupt 0 Disable the alarm interrupt default continued 154 1287 Real time Clock RTC Table 10 4 Status Register B OBH continued Bit 4 Function Update ended interrupt enable UIE bit 1 Enable the update ended interrupt 0 Disable the update ended interrupt default Sequare wave enable SQWE bit 1 Enable the square wave frequency set by the rate selection bits in register A 0 Disable square wave frequency default Date mode DM bit Indicates whether the time and data calendar updates use binary or the BCD format 1 Select binary format 0 Select BCD format default 24 12 hour 24 12 bit Determines whether 24 hour mode or 12 hour mode is set in the hours byte 24 hour mode default 1 1 0 12 hour mode Daylight savings enabled DSE bit 1 Daylight savings time enabled 0 Daylight savings time disabled default 155 1287 Real time Clock
181. f configuration information maintained by the setup program is as follows Date and time Number and capacity of floppy disk drives Amount of base and type of fixed disk drives Availability and type of primary monitor controller 10 Board Overview Keyboard present Numeric coprocessor present e Shadow or do not shadow system BIOS and video BIOS Enable or disable cache memory speaker and preboot setup Onboard ROM consists of two 27256 EPROMs containing 64K of memory The EPROMs contain the ROM code for the BIOS Functions of the BIOS are as follows System initialization Power on diagnostics System configuration Disk bootstrap loading Character bit patterns of the ASCII character set Storage of frequently needed input and output routines If enabled in setup the BIOS initializes the DRAM shadowed BIOS option for increased system performance 11 CENTRAL PROCESSING CORE 3 1 INTRODUCTION This chapter describes the central processing core of the system board The 386 CPU the 387 numeric coprocessor cache memory cache tag memory and the data and control buffers are discussed For more information on these components refer to the Intel Microprocessor and Peripheral Handbook 3 2 OVERVIEW The central processing core contains the following components A 386 32 bit CPU A 387 numeric coprocessor Cache memory Cache tag memory Data and control buffers 33 CPU The CPU
182. f unused RAM can be reclaimed by activating the shadowing feature With up to 384K of memory becomes useful and is remapped into another section of the 80386 memory map With REMAP the user has the option of relocating this section of RAM memory to one of the address ranges shown below Option 1 Append to the first megabyte 100000h to 15FFFFh Used only when 1Mb of memory is populated with 256K DRAMs one bank installed Option 2 Append to the second megabyte 200000h to 25FFFFh Used only when 2Mb of memory is populated with 256K DRAMs two banks installed Option 3 Append to the fourth megabyte 400000h to 45FFFFh Used only when 4Mb of memory is populated with IMb DRAMs one bank installed The REMAP feature cannot be used with memory configurations other than those noted above Caution The combined use of both the shadow RAM feature and the REMAP feature if Bit 5 of INDEXOIh is set to 1 may cause the chip set to lock up That very effectively crashes the host system How to activate REMAP The REMAP feature is activated when these conditions are true l The Shadow RAM feature is turned OFE 2 The amount of memory in the system has been configured then 3 Bit 5 of the general setup register INDEXOIh is set to and 4 Bit of DRAM configuration register INDEX10h is set to 1 Caution If these three conditions are not true and especially if the register bits 01h and 10h are set before m
183. g Sense Interrupt command D4 Equipment Check After a Recalibrate Command Track 0 signal failed to occur Used during Sense Interrupt command D3 Not Used 0 D2 Head Address at end of Execution Phase D1 DO Drive Select at end of Execution Phase 00 Drive 0 selected 01 Drive 1 selected 10 Drive 2 selected 11 Drive 3 selected 13 6 2 Status Register 1 ST1 D7 End of Track Controller transferred the last byte of the last sector without the TC pin becoming active The last sector is the End Of Track sector number programmed in the Command Phase D6 Not Used 0 D5 CRC Error If this bit is set and bit 5 of ST2 is clear then there was a CRC error in the Address Field of the correct sector If bit 5 od ST2 is set then there was a CRC error in the Data Field D4 Over Run Controller was not serviced by the P soon enough during data transfer in the Execution Phase 204 DP8473 Floppy Disk Controller Table 13 6 Maximum Time Allowed to Service an Interrupt or Acknowledge a DMA Request in Execution Phase Data Rate Time to Service 125 62 0us 250 30 0 5 500 14 0 1000 6 0 Time from rising edge of DRQ or INT to trailing edge of DAK or RD or WR D3 Not Used 0 D2 No Data Three possible problems 1 Controller cannot find the sector specified in the Command Phase during the execution of a Read Write or Scan command An address mark was found however so it is not a blank
184. g previously stored data or returning the system to the real mode from protected mode Table 10 8 Shutdown Status Byte Bit Function 7 Reset information 00H Normal system reset 09H User software reset return from protected mode 01H 08H Used by hardware self test OAH FFH Used by hardware self test 1053 Floppy Disk Drive Type Byte 10H Table 10 9 Floppy Disk Drive Type Byte 10H Bit Function 7 4 First floppy disk drive type 0000 No floppy disk drive 0001 360K drive 5 25 inch 0010 1 2M high density drive 5 25 inch 0011 720K 3 5 inch drive 0100 3 5 inch drive 0101 1111 Reserved 3 0 Second floppy disk drive type 0000 No floppy disk drive 0001 360K drive 5 25 inch 0010 1 2M high density drive 5 25 inch 0011 720K 3 55 inch drive 0100 14M 3 5 inch drive 0101 1111 Reserved 158 1287 Real time Clock RTC 1054 Fixed Disk Type Byte 12H Table 10 10 Fixed Disk Type Byte 12H Bit Function 7 4 First fixed disk drive type drive C 0000 No fixed disk drive installed 0001 1110 Types 1 14 1111 Types 16 255 refer to extended byte 19H 3 0 Second fixed disk drive type drive D 0000 No fixed disk drive installed 0001 1110 Types 1 14 1111 Types 16 255 refer to extended byte 1AH 10 5 5 Equipment Byte 14H The hard ware self test uses the equipment byte The format of the equipment byte is
185. guration information please run the Setup utility 241 Messages Solution Message Possible Cause Solution Message Possible Cause Solution Message Possible Cause Solution Message Possible Cause Solution Message Possible Cause Solution Check the system configuration and return the Setup utility Keyboard clock line failure Either the keyboard or the keyboard cable connection is defective Check the keyboard connection If the connection is good the keyboard may have failed Try running the keyboard diagnostic test If the problem persists contact your service representative Keyboard controller failure The keyboard controller located on the system board has failed Contact your service representative Keyboard data line failure Either the keyboard or the keyboard cable connection is defective Check the keyboard connection If the connection is good the keyboard may have failed If the problem persists connect your service representative Keyboard is locked please unlock Strike the F1 key to continue F2 to run the Setup utility The system unit keylock is locked Unlock the keyboard and try again If the problem persists contact your service representative Keyboard struck key failure One or more keys are pressed or stuck Release the key or keys and try again If the key is still stuck there may be debris in the keyboard Try to shake it loose If the problem persists contac
186. h FAST__RC and ALT MUXPA2Q 125 Figure 9 1 A38202 Internal Configuration cesi ant nde ee e EUR 130 Figure 9 2 Tag RAM Organization 252255 edet S iib Ie ve d 131 Pigure 9 3 gt A38202 Signals cesser Grae rene Re estis qu atu Va aat at 134 Figure 94 Control Register acera c pA ror e Sv ER eee a 143 Figure 9 5 Configuration Register pp adsl 144 Figure 9 6 Status Register Seas DO US usa ER dH Ls a ds 145 Figure 9 7 Noncache Control Register 145 Figure 9 8 Noncache Descriptor Registers Dr mede eid EE 146 Figure 9 9 PQFP Pinout eA D irn dl us tret CS RA Need 148 Figure 10 1 RTC Memory Map 2643 sacs give mute etu EET AE M andas 150 Figure 12 1 Keyboard Mouse Controller 169 Figure 13 1 Connection Diagrams S Fares Mb 186 Figure 13 2 DP8473 Functional Block Diagram 187 Figure 13 3 DP8473 Typical Application eee dene bro vale band 192 Figure 13 4 Block Diagram of DP8473 s Data Separator 194 Figure 13 5 Typical Configuration of Loop Filters for the DP8473 Showing Component Labels Ne ke 194 Figure 13 6 Read Algorithm State Diagram for Data 197
187. h a BUsCLOCK frequency F of 8MHz the period T is 125ns ii With 4 wait states inserted the total I O command active time 4 5x125ns is 560ns 11 The command delay 1 5xT is 200ns iv The recovery time 1 5xT is 200ns The chip timing relationships of the CGK131 Controller are referenced as multiples of CLKIN which at 25MHz means the oscillator beats at 5 2 v The reciprocal t or 1 divided by 50MHz is 20ns Thus 107 Configuration Registers of the GCK131 Chip Set vi For a command active time of 560ns we require 28 CLKINs 560ns divided by 20ns For a command delay of 200ns we require 10 CLKINs 200ns divided 20ns ix For a recovery time of 200ns we require 10 CLKINs 200ns divided by 20ns To match the generic 8 Mhz timing for I O access and 4 wait states we program the INDEXO8h I O Access configuration register as follows a For a command delay of 10 CLKINs paragraph vii INDEXOS8h Bit 1 0 Bit 0 0 b For a command active period of 28 CLKINs paragraph vi INDEX08h Bit 3 1 Bit 2 0 c Fora recovery time of 10 CLKINs paragraph ix INDEXOBh Bit 5 0 Bit 4 1 With iNDEXO0Bh Bits 6 and 7 both programmed each as T the contents of INDEx08h equals d8h INDEX06h EPROM configuration Default value FFh Configuration registers INDEX06h through 09h are available to tailor the timing requirements for various commands of the sys
188. hase 205 XII SYSTEM SPECIFICATION 1 1 INTRODUCTION This system is a powerful computer that offers the high performance and power of 33MHz 80386 microprocessor designed into a compatible IBM AT architecture A socket is prepared for the numeric coprocessor Intel 80387 or Weitek 3167 for the specific applications which requier fast real time processing capability such as CAD system or engineering workstation With its 8 I O slots it provides an outstanding performance and features for your specific applications The performance is increased by three to four times over 8MHz 80286 based personal computers The system mother board is approximately 30 5 by 33 centimeters 12 6 by 13 inches and the board is a 8 layer PCB Printed circuit Board to maximize the system reliability while reducing the EMI Electro Magnetic Interfaces The system mother board contains the ATLAS Chip Set it is also called as GCK131 Chip Set GC131 132 and GC133 of three highly integrated HCMOS microchips which supports an 80386 microprocessor based computer system in AT compatible mode at speeds up to 33MHz This high performance three chip set allows the implementation of a powerful computer system with just these components an 80386 microprocessor a keyboard controller a real time clock six bipolar devices and up to 24M of memory Note ATLAS HT131 HT132 and HT133 the name of chip set is mingled with GCK131
189. he SRAM 0800H 08FFH Error Page No L xx Error Bit Set 12 BIOS ROM 002C byte checksum Error value 13 Extended BIOS ROM 002 byte checksum Error value socket on CPU board 14 I O Card 002C byte checksum Error value EGA Card BIOS amp etc 15 CMOS RAM R W Error 21 04 Ln 0100 Error Bit Set Error Address 21H Register 16 Speaker Error 00 00 l No meaning 17 PMS data line test Error 00 55 Error data 18 PMS back light test Error 19 PMS micro S W test Error 1A PMS battery charging test Error A 12 2 Keyboard 2 20 Keyboard Processor Reset Error 00 00 received code other than 21 Keyboard Scancode test Error 00 00 no meaning 22 Keyboard controller BAT Error 232 Diagnostic A 12 3 Video Adapter 3 CGA MGA Case Only 30 EGA VGA general Error 31 Video RAM test Error 32 Read mode 0 test Error 33 Read mode 1 test Error 34 Write mode 0 test Error 35 Write mode 1 test Error 36 Write mode 2 test Error 37 Write mode 3 test Error 38 Switch setting test Error 39 Reading inactive plane test Error 3A Reading active plane test Error 3B Rotation function test Error 3C Linear address test A0 A7 Error 3D Linear address test A9 A15 Error 3E Cursor address test A0 A7 Error 3F Cursor address test A8 A15 Error 40 Cursor address test A16 A17 Error 41 Bit mask function test Error 42 Latched data test Erro
190. he controller processes the data in the input buffer as a command byte 12 24 Input and Output Ports The input port consists of two signals to the controller driven by the keyboard and mouse and two signals indicating the keylock state and color monochrome bit setting The output port consists of eight signals driven by the controller to the keyboard mouse or system interface These ports are accessed by sending the appropriate read or write command to the controller Tables 12 2 and 12 3 list the input and output port bit assignments respectively 171 Keyboard and Mouse Controller Table 12 2 Input Port Bit Assignments Bit Function 7 Keylock lock 0 6 Color mono color 0 5 TEST enabled 0 4 2 Reserved 1 Mouse data in 0 Keyboard data in Table 12 3 Output Port Bit Assignments Bit Function 7 Keylock lock 0 6 Color mono color 0 5 MFG TEST enabled 0 4 2 Reserved 1 Mouse data in 0 Keyboard data in 172 Keyboard and Mouse Controller 123 CONTROLLER COMMANDS The CPU uses controller commands refer to Table 12 4 to control the operation of the controller and sense its status The CPU writes controller commands into the input buffer through I O port address 64H Table 12 4 Controller Commands Code Description 20H Read controller command byte 21H 3FH Read 8742 internal RAM locations 21 3FH 60H Write controller command byte 61
191. he keyboard transfers data to the controller only when both the clock and data signals are active At the end of a transfer the controller disables the interface until the system accepts the data byte If a parity check error occurs the controller signals the keyboard to transfer the data again If the controller does receive the data correctly after a set number of retires an FFH code is sent to the controller output buffer The parity bit in the status register is also set indicating a receive parity error The controller times each data byte transfer from the keyboard If a keyboard transfer does not end within 2 ms the controller sets the receive time out bit in the status register and writes an FFH code to its output buffer No retries are attempted on a receive time out error The following commands are sent from the keyboard to the controller 175 Keyboard and Mouse Controller OVERRUN OR KEY DETECTION ERROR 00H OR FFH If the keyboard uses scan code set 1 the code equals FFH For sets 2 and 3 the code equals 00H The conditions are as follows The keyboard sends a key detection error character if conditions in the keyboard make it impossible to identify a switwch closure When the buffer in the keyboard is full an overrun character replaces the last transmitted code in the buffer This code is sent to the controller when it reaches the top of the buffer queue KEYBOARD ID 83ABH The Keyboard ID consists of
192. he range of services provided by this chip The GC131 Controller is responsible for the AT controllers of the chip set supporting the system with INTERRUPT TIMER DMA REFRESH and services 42 GC131 Controller 5 2 1 HT131 Peripheral Controller Pinouts The pin connections for the HT131 Peripheral Controller are shown in Figure 5 2 The pins are numbered sequentially in a counter clockwise direction from the index mark as viewed from the botton of the chip VDD LA24 LA25 LA26 LA27 LA28 LA29 LA30 LA31 FAST SLOW SYSRES CONFIGAS CONFIGDW CONFIGDR DOEEP NMI LWRI6MEG BUSCLOCK VSS VSS VSS VDD ISMEMW 5 8042 CK8042 ENADDSTB PARITY DIEEP CSEEP CKEEP 58042 1 5287 5 RTCDS RTCRW RESET HOR NOW VDD ES ES Ac q 20zodz G lt Z gt gt gt gt lt lt lt lt lt lt lt lt gt lt lt lt lt lt lt lt lt gt I lt amp amp 29 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 5 139 140 2 Peripheral tro eripheral Controller 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 60 9 12 13 14 15 16 17 18 19 20 m c cN 05 sf io so OD
193. hrough C1FFFFFE Although addresses C0000000 to COOOFFFF are normally unused it is important that other components in the system do not conflict with the address space used by the 3167 Reading and writing to this address apace causes the 3167 to drive the data bus and execute instructions respectively i Central Processing Core 35 CACHE MEMORY The cache memory and cache tag memory implement a 2 way set associative 64K write through cache for the CPU The cache is located beside the CPU and holds information contained in the system memory for fast CPU access The cache contains 64K of memory organized into 16K words of 32 bits per word It also uses a 2 way set associative design with posted write through to main memory on all write cycles The CPU accesses cache memory information on reads at full speed with no wait states The CPU accesses write hits with one wait state Four 8Kx16 30ns SRAMs comprise the memory portion of the cache The SRAMs make up the 32 bit word for the bus and are addressed by the least significant 14 bits of the address bus 3 6 DATA AND CONTROL BUFFERS Bidirectional buffers transfer control data and address signals between the CPU bus and the ISA bus Four buffers transfer CPU data D 31 0 and four buffers transfer CPU addresses 27 02 ISA BUS INTERFACE 4 1 INTRODUCTION This chapter provides an overview of the ISA bus interface as implemented on the system board 4 2 BUS AGENTS
194. ilter is the parallel combination of the capacitors C2C and 2 attached to the FGND250 and ground If 1 Mb s need not be supported then the filter configuration of Figure 13 5 can be used This configuration allows more optimal performance for both 500k and 250 300 kb s Figure 13 5 is a simple filter configuration primarily for a single data rate or multiple data rates with a performance compromise Table II shows some typical filter values Other filter configurations and values are possible these result in good general performance While the controller and data separator support both FM and MFM encoding the filter switch circuitry only supports the IBM standard data rates The provide both FM and filters external logic may be necessary The controller takes best advantage of the internal data separator by implementing a sophisticated ID search algorithm This algorithm shown in Figure 13 6 enhances the PLLs lock characteristics by forcing the PLL to relock to the crystal any time the data separator attempts to lock to a non preamble pattern This algorithm ensures that the PLL is not thrown way out of lock by write splices or bad data fields 195 DP8473 Floppy Disk Controller Table 13 1 Typical Filter Values for the Various Data Rates Assuming 6 Capture Range C R2 Ci Ri bis Filter Values when Using All 3 Data Rates 1 0M C2c 0 0124F 5600 510 5 6kQ
195. in the programmed time out delay 1 Data from the keyboard auxiliary device did not terminate normally within the programmed time out delay 170 3 B Keyboard and Mouse Controller Table 12 1 Status Register Bit Definition continued Bit Function 7 Parity error 0 Last byte of data received from the keyboard auxiliary device had odd parity no error 1 Last byte of data received from the keyboad auxiliary device had even parity error 12 2 2 Output Buffer The controller output buffer is an 8 bit read only register at I O address 60H The controller sends keyboard scan codes command requested data bytes and mouse data to the system via the output buffer The significant data in the output buffer can be read only when the output buffer full bit bit 0 of the status register equals 1 12 23 Input Buffer The controller input buffer is an 8 bit write only register at I O addresses 60H and 64H Data can be written to the input buffer only if the input buffer full bit bit 1 of the status register equals 0 Writing to address 60H clears the command data bit bit 3 of the status register Once cleared the controller processes the data in the input buffer as a data byte Data written to address 60H is sent to the keyboard unless a system command instructs the controller to wait for a data byte Writing to address 64H sets the command data bit bit 3 of the status register to 1 Once set t
196. information to enable design of the data separator s external filter and charge pump set resistor This discussion is for a single data rate filter and can be easily extrapolated to the other filters of Figure 13 5 Table 13 1 shows some typical filter component values but if a custom filter is desired the following parameters must be considered R1 Charge pump current setting resistor The current set by this resistor is multiplied by the charge pump gain KP which is 2 5 Thus the charge pump current is IPUMP 2 5 1 2V R1 R1 should be set to between 3 12 kQ This resistor determines the gain of the phase detector which is KD IPUMP 27 C2 Filter capacitor in series with R2 With pump current this determines loop bandwidth R2 Filter resistor Determines the PLL damping factor C1 This filter capacitor improves the performance of the PLL by providing additional filtering of bit jitter and noise KVCO The ratio of the change in the frequency of the VCO output due to a voltage change at the VCO input 25 Mrad s V The VCO is followed by a divider to achieve the desired frequency for each data rate VCO center frequency is 4MHz for data rates of 1 Mb s 500 kb s and 250 kb s and is 4 8MHz for 300 kb s 197 DP8473 Floppy Disk Controller This is the gain of the internal PLL circuitry and is the product of VREF x KVCO x This value is specified in the Phase Locked Loop Characteristic
197. iome 10MF 10MF 10MF iowF liame 10 0 1 58 SAMSUNG ELECTORNICS 10MF one 5 VSS 525 L SND DESKTOP 386 POWER amp CLOCKS GNO CLREXPOA gt 4256 gt RN p Pee 3185 Pegs Ra NCCESE 8 SIPS 10K Ll gt PEO 222 gt C180 C181 T C182 eno o ane Ca EU a2 Lael of PPK pO lt 1819 444 1 CALLED Ye CBS iG lt SAMSUNG ELECTRONICS 253 Pos Rng gt Goi gt lt Pip S gt FETT 22 FT gt CALLRDY NOTE CONNECT LINK WHEN WYTECK NOT INSTALLED REMOVE LINK FOR WYTECK USAGE 4 4 ER LESTE 1 107 NERO HERI NS 2766 VSS OUT Kus is 029 ROY 030 TCB D31 MCS PRES INTR ERROR READYO PEREQ READY BUSY STEN PCLK2 RESET 387CLK2 CKM GNO vpo GNO M IO CEREZ VDD GND 42 gt GNO lt GND ETU os gt VDO GNO a VoD GNO lt 1410 427 GND GNO GND GND CNPUCLK J SAMSUNG ELECTRONICS itle DESKTOP 386 OPTIONAL 254 333 gt 212 gt KEI Tes gt CLEAR EXC
198. ios shadowing is selected either OFF or ON by Bit 4 Similarly Bit 5 controls the REMAP Bit 6 enables or disables the use of Middle Bios Bit State Description 0 0 Video BIOS Not shadowed into DRAM 1 Video BIOS Shadowed into DRAM 1 0 Page mode disabled 1 Page mode enabled 2 0 BIOS EPROM type 27256 1 BIOS EPROM type 27512 3 0 CLOCK mode 80387 asynchronous 1 CLOCK mode 80387 synchronous 4 0 Video BIOS shadowing disabled 1 Video BIOS shadowing enabled 5 0 REMAP above 1 2 or 4 Mb disabled 1 REMAP above 1 2 or 4 Mb enabled 6 0 Middle BIOS disabled 1 Middle BIOS enabled 7 0 Quiet bus disabled 1 Quiet bus enabled During high speed local access the commands are not issued to the backplane And BALE is kept HIGH during the cycle Figure 8 2 INDEX01h General Setup Bits Continued 101 Configuration Registers of the GCK131 Chip Set INDEX02h High speed override bits Default value FFh Use these configuration bits if high speed sRAMs are installed in preference to DRAMs in one or more banks of the system Each bank can be individually configured to optimize system performance When the override bit for a particular bank is ON the forced delays indicated in Figure 8c are used rather than the programmed values of INDEx04h and 05h Bit State Description 0 0 DRAM delay BANK 0 override ON forces these delays 0
199. isplay System Configuration and press lt F9 gt again for HELP message 218 A 2 5 Press lt Enter gt key to continue 218 A 3 DESCRIPTION OF SCREEN amp FUNCTION KEY USAGE A 3 1 Following are disagnostics MAIN MENU 219 A 3 2 How to Select Each MENU 219 A4 DESCRIPTION OF MANUAL TEST MODE AAT System MONIS ei coke e 220 A42 KBD MOI eun aaa M ics ar item ch 221 A434 Video JU MHIL e estes eem cr al E rS A 221 A44 FDD Meus s 129 Sed ata ay em 221 A45 HDD ades wea 222 AXE DPI 222 7 SIO Men cin Pos Sa Pos u Dea hal rette dtd ka 223 A 5 DESCRIPTION OF AUTO TEST MODE A 5 1 Description of Each Test Procedure 224 Bi HOW iE Works xay etn tists asta OE aah eye baeo d ah ah eun 226 A6 DESCRIPTION OF AUTOMATIC PROCEDURE EDITOR 227 A61 If you select Diskette following text will be displayed 227 62 How to Define 22 or Change Produce Already Defined 229 Exit Editor ab ad LM M t ie cit at 229 7 DESCRIPTION OF AUTOMATIC PROCEDURE DEFINE MODE 230 71 Description of Error Handling Option 230 VII 72 Starts to Defi
200. it address space to be designated noncachable Two of the regions are assignable on 64kB boundaries anywhere in the 4 GB physical address space of the 80386 The size of these region can range from 64kB up to 4GB The third region is assignable on a 4kB boundary and can range from 4kB up to 4GB The regions may be separate contiguous or overlapping These regions are suitable for ROM resident initialization routines memory mapped I O devices system control registers dual port memory or any other memory that should not be cached 133 9 3 A38202 SIGNALS This section describes the A38202 Microcache input and output signals refer to Figure 3 1 The signals are classified by the following functional groups Timing and processor signals System interface signals Clock Cycle definition Reset Bus control Processor address Chip select Bus control Write buffer control Cycle definition Bus Watching signals Status and control signals Snoop Address Snoop Status Cache control signals Cache memory address Cache enables CLK2 49 A312 PROCESSOR 32 prt ADDRESS BUS ADDRESS BE 3 0 x 18 BIT CACHE A ADDRESS PROCESSOR SRAM BUS READY CONTROL CONTROL READYO lt J pu o a WIR s BLOCK _ Mi MIIO icrocache BREADY PROCESSOR BHOLD SYSTEM CYCLE PIC 4 5 BUS DEFINITION LOCK BHLD INTERFACE A20GATE BURSTRE
201. k drives the entire chip on the rising edge This clock is the same as used by the 80386 Microprocessor Clocking Mode When LOW it selects the asynchronous clocking mode of the 80387 when HIGH the synchronous mode See INDEX 01h on Page 46 GC132 CPU Memory Controller Pin Pin Pin Symbol Number Type Description CLREXPTION 44 O Clear Exception Connects to the RESET of the 80386 Microprocessor This is a synchronous reset CONFIGAS 107 I Configuration Register Address Strobe The configuration register index is strobed in on the falling edge of this signal from the data bus LD0 Results from IOW to Address 24h CONFIGDR 106 1 Configuration Register Data Read Data is read from the configuration register addresses by the value written in by the CONFIGAS pulse This results from from Address 28h CONFIGDW 105 I Configuration Register Data Write Data is written on the falling edge into the register addressed by the Index latched by CONFIGAS CONVAO 116 Conversion Address 0 During an 8 to 16 bit conversion cycle the address 0 line must be forced to a Y during the second half This signal tells the HT133 when to force A0 to A1 on the backplane ICS287 47 I Chip Select 287 Coprocessor When LOW the processor is addressing an I O location between F0h FFh DBEN 32 O Data Bus Enable When LOW the local bus is expecting data from the HT133 when HIGH the HT133 should not put data
202. l has a value between 2 4V 5 5V logical 1 These voltages are measured between a signal source and the DC network ground 174 Keyboard and Mouse Controller 124 1 Keyboard Mouse Data Stream The 8 bit data steam transferred serially over the data line consists of one start bit eight data bits one odd parity bit and one stop bit refer to Table 12 5 A logic 1 indicates an active level and a logic 0 indicates an inactive level The parity bit is either 1 or 0 The 8 data bits plus the parity bit always have an odd number of 15 Table 12 5 Data Stream Bits Bit Function Start bit always 0 Data bit 0 LSB Data bit 1 Data bit 2 Data bit 3 Data bit 4 Data bit 5 Data bit 6 Data bit 7 MSB Parity bit odd parity Stop bit always 1 A QI gt Q N 124 2 Receiving Data from the Keyboard The keyboard transfers data to the controller in a serial format using an 11 bit frame The first bit is a start bit followed by 8 data bits an odd parity bit and a stop bit A clock supplied by the keyboard synchronizes the data transfer Before transferring data the keyboard checks for a transmission inhibit or controller RTS status on the clock and data lines If transmission is inhibited clock line imactive keycodes are transferred to the keyboard buffer During controller RTS data is also stored in the keyboard buffer while the keyboard receives controller data T
203. ld be configured so that the clock is input into the OSC2 pin and OSC1 is tied to ground Crystals Staytek CX1 SM1 24MHz B SaRonix SRX 3164 135 REGISTER DESCRIPTION This section describes the register bits for all the registers that are directly accessible to the uP Table 13 3 previous page shows the memory map for these registers Note that in the PC some of the registers are partially decoded this is not the case here registers occupy only their documented addresses 135 1 Main Status Register Read Only The read only Main Status Register indicates the current status of the disk controller The Main Status Register is always available to be read One of its functions is to control the flow of data to and from the Data Register The Main Status Register indicates when the disk contoller is ready to send or receive data It should be read before each byte is transferred to or from the Data Register except during a DMA transfer No delay is required when reading this register after a data transfer D7 Request for Master Indicates that the Data Register is ready to send or receive data from the P This bit is cleared immediately after a byte transfer and will become set again as soon as the disk controller is ready for the next byte D6 Data Direction Indicates whether the controller is expecting a byte to be written to 0 or read from 1 the Data Register D5 Non DMA Execution Bit is set only during the Execution Pha
204. le 10 14 Drive C Extended Byte 19H Bit Function 7 0 Addresses 00H 0FH reserved Addresses 10H FFH types 16 255 160 1287 Real time Clock RTC 1059 Drive D Extended Byte 1AH Table 10 15 Drive D Extended Byte 1AH Bit Function 7 0 Addresses 00H 0FH reserved Addresses 10H FFH types 16 255 105 10 Feature Installed Byte 1FH Table 10 16 Feature Installed Byte 1 Bit Function 73 Reserved 2 Floppy disk drive A installed 1 Video display installed 0 Keyboard BIOS installed 105 11 CMOS RAM Checksum 2EH and 2FH The CMOS RAM checksum is the sum of the values from addresses 10H through 2DH Table 10 17 CMOS RAM Checksum 2EH and 2FH Bit Function 7 0 Address 2EH high byte of checksum 7 0 Address 2FH low byte of checksum 161 1287 Real time Clock RTC 10 5 12 FXD Type 48 Parameters 20H 27H Table 10 18 FXD Type 48 Parameters 20H 27H Bit Function 20H Cylinder low byte 21H Cylinder high byte 22H Number of heads 23H Write pre compensation start cylinder low byte 24H Write pre compensation start cylinder high byte 25H Landing zone cylinder low byte 26H Landing zone cylinder high byte 27H Sectors per track 105 13 Shadow and Enter Setup 28H Table 10 19 Shadow and Enter Setup 28H Bit Function Cache disable ROM BIOS map address 1M and 16M Speaker off 512 640K enable
205. le IV in the Register Description Section Don t care during DMA transfers 20 04 Bi directional data lines to the microprocessor These are the lower 5 bits and have buffered 12 mA outputs GNDB This pin is the digital ground for the 12 mA microprocessor interface buffers This includes 00 07 INT and D5 D7 Bi directional data lines to the microprocessor These upper 3 bits have buffered 12 mA outptus DRQ Active high output to signal the DMA controller that a data transfer is needed This signal is enabled when D3 of the Drive Control Register is set DAK Active low input to acknowledge the DMA request and enable the RD and WR inputs This signal is enabled when D3 of the Drive Control Register is set TC Active high input to indicate the termination of a DMA transfer This signal is enabled when the DMA Acknowledge pin is active INT Active high output to signal that an operation requires the attention of the microprocessor The action required depends on the current function of the controller This signal is enabled when D3 of the Drive Control Register is set DSKCHG RG This latched Schmitt input signal is inverted and routed to D7 of the data bus and is read when address xx7H is enabled When the RG bit in the Mode Command is set this pin functions as a Read Gate signal that when low forces the data separator to lock to the crystal and when high it locks to data for diagnostic purposes GNDC This pin is the digital ground for
206. lock 1 Where Bits 3 2 1 0 0 represent 0 wait states 0 And Bits 3 2 1 0 1 represents 15 wait states DMA wait states 7 A Binary count of the number of wait states of 6 DMA clock 5 Where Bits 3 2 1 0 0 represent 0 wait states 4 And Bits 3 2 1 0 1 represents 15 wait states Figure 8 21 INDEX42h DMA and REFRESH Wait States 118 Configuration Registers of the GCK131 Chip Set INDEX43h Serial parallel and mapper selections Default value 00h The GCK131 Chip Set has built in decoding logic for I O devices including two serial ports and one parallel port Serial port 1 is mapped to COMI 3F8h 3FFh and serial port 2 is mapped to COM2 2F8h 2FFh The serial ports can be selected by Bits 0 and 1 of this iNpEx43h The parallel port decoding can be selected for either 378h 37Fh or LPT2 278h 27Fh by Bit 2 of this INDEX43h Bit State Description 0 0 Serial port 1 disable 1 Serial port 1 enable 1 0 Serial port 2 disable 1 Serial port 2 enable 2 0 Parallel port configure as LPT2 1 Parallel port configure as LPT1 3 0 Parallel port disable 1 Parallel port enable 4 0 standard AT 8 bit page mapping 1 Extended DMA 16 bit page mapping enabled NOTE The address for the PAGE MAPPER is the same as the AT standard but the additional 8 bits are mapped 10h addresses above the usual location See Figure 7t If
207. m bus cycles to gate BREADY to the 80386 Data Bus D7 D0 The data bus pins on the A38202 connect directly to the 80386 They are used to read write the A38202s internal registers 93 2 Other Cycle Definition Signals A20 Gate A20GATE This signal is used by the A38202 to determine whether it should use the value of A20 driven by the 80386 or force it to be low This is required for compatibility with some 8088 and 8086 code This input should be driven low when the 80386 is operating in real mode and high when the 80386 is operating in protected mode 27364 Local Access LOCAL This signal is used to tell the A38202 that the current bus cycle will be executed on the 80386s local bus When it is asserted the A38202 completely ignores the current cycle Noncachable Access This signal is used to tell the A38202 that the current bus cycle is an access to a noncachable region of memory It allows external decoding of noncachable regions in addition to those defined by the internal noncachable region descriptors 9 3 3 Cache Control Signals These A38202 signals interface directly to the cache SRAMS Cache Address Bus 15 0 The cache address bus connects from the A38202 to the external cache SRAMS Note that some of these signals may not be used depending on the size of the cache implemented Cache Output Enables OE1 OE0 OE0 and OE1 are active low signals which tie to
208. m has a DMA controller This allows the uP to do other things during the Execution Phase data transfer If DMA is not used an interrupt can be issued for each byte transferred during the Execution Phase If interrupts are not used the Main Status Register can be polled to indicate when a byte transfer is required 13 7 2 DMA Mode If the DMA mode is selected a DMA request will be generated in the Execution Phase when each byte is ready to be transferred To enable DMA operations during the Execution Phase the DMA mode bit in the Specify Command must be enabled and the DMA signals must be enabled in the Drive Control Register The DMA controller should respond to the DMA request with a DMA acknowledge and a read or write strobe The DMA request will be cleared by the active edge of the DMA acknowledge After the last byte is transferred an interrupt is generated indicating the beginning of the Result Phase During DMA operations the Chip Select input must be held high TC is asserted to terminate an operation Due to the internal gating TC is only recognized when the DAK input is low 1373 Interrupt Mode If the non DMA mode is selected an interrupt will be generated in the Execution Phase when each byte is ready to be transferred The Main Status Register should be read to verify that the interrupt is for a data transfer Bits 5 and 7 of the Main Status Register will be set The interrupt will be cleared when the byte is transferred to or from
209. memory regions as noncachable Enable or disable the noncachable memory regions Flush all of the cache contents Enable or disable cache RAM as local RAM 128 Creative use of the instruction set permits the system designer to achieve the full benefit of the A38202 Microcache capabilities 9 1 3 A38202 Packaging The A38202 Microcache is a 160 000 transistor VLSI device fabricated in 1 5 micron CMOS technology The Microcache is available in a 160 lead Plastic Quad Flat Pack POFD 9 2 ARCHITECTURE 9 2 1 Internal Configuration Circuitry on the A38202 Microcache comprises the following major functional units as seen in figure 9 1 1 Processor interface and control 2 Tag RAM groups 3 SRAM interface and control 4 System interface and control 5 Noncachable address comparators Processor Interface Control Unit The control unit monitors the operation of the 80386 and keeps track of the current processor state During read miss cycles the control unit instructs the system interface unit to fetch the appropriate number of words from main memory Tag RAMS The A38202 contains two tag RAM groups each with 256 entries Each entry consists of a tag and subblock presence information The information stored in the tag RAMs identifies individual blocks that correspond to memory locations currently present in the cache memory A set of high speed comparators within each tag RAM responds to the cu
210. meric underflow N Inexact result precision POST code in the system ROM enables the hardware interrupt It also sets the hardware interrupt vector pointing to a routine in ROM This routine clears the latch on the BUSY signal and generates IRQ13 interrupt While the CPU executes numeric programs in either real or protected mode interrupts report exception conditions Refer to the 80387 Programmers Reference Manual Intel order number 231917 001 for detailed descriptions of 387 interrupts and exceptions All communication between the CPU and the 387 is transparent to applications software The 387 operates whether the CPU executes instructions in real address mode protected mode of virtual 8086 mode The CPU handles all memory accesses The 387 operates on instructions and values passed to it by the CPU and is not aware of the processing mode of the CPU For complete information on programming the 387 refer to the 80387 Programmer s Reference Manual Intel order number 231917 001 343 Weitek 3167 System Level Considerations The Weitek 3167 is a memory mapped numeric coprocessor communicating with the CPU over the processor address bus Instructions are defined by the 14 least significant address bits A15 2 and three of the four byte enables BE2 0 Addresses A31 A25 and M IO select the 3167 Address bits A31 and A29 determine the 3167 operation requests The 3167 decodes memory addresses C0000000 t
211. ming a 16 bit DMA transaction ALI MUXPA20 11 Redfined from ATA18 When the PORT92h feature is enabled See PORT 92H on Page 78 this ALT MUXPA20 signal should be gated with the MUXPA20 signal from the 8042 Keyboard Controller to produce the final MUXPA20 signal that is sent to the HT132 Controller See also INDEX 48h and cicuitry shown on Page 76 ATAO to 79 I O Latched AT Address Bus Used for memory ATA16 82 89 and I O devices These addresses are gated 91 98 from the system bus when BALE is set HIGH and are latched on the falling edge of BALE These signals are generated by the CPU or DMA controller in the HT131 Controller or may be driven by an external bus master on the I O channel ATA17 10 O AT Address Line 17 Pin 10 can be redefined to either of two modes In I O Standard Mode the line ATA17 is driven only during DMA and REFRESH cycles and represent a copy of LA17 In I O PORT92h Mode Pin 10 is refined as FAST RC as described later in these Pin Descriptions See also PORT 92H on Page 78 GC131 Peripheral Controller Pin Type Pin Symbol Pin Number Description ATA18 11 O ATA19 13 ATDO to ATD7 36 39 42 45 BALE 112 I BFDIR 104 BFEN 106 BUSCLOCK 138 45 AT Address Line 18 Pin 11 can be redefined to either of two modes In I O Standard Mode the line ATA18 is driven only during DMA and REFRESH cycles and represent a copy of LA18 In PORT92h Mode
212. mmand enables data transmissions if the mouse has been set to stream mode This command has no effect in remote mode DISABLE F5H The disable command disables data transmissions if the mouse has been set to stream mode This command has no effect in remote mode 182 Keyboard and Mouse Controller SET DEFAULT F6H The set default command reinitializes the mouse to its power on default state The mouse power on default state is shown below Sampling rate 100 samples second Scaling Linear scaling Mode Stream mode Resolution 4 counts mm Transmissions Disabled RESEND FEH The resend command is issued by the system in response to transmission errors from the mouse The mouse responds to this command by retransmitting its last data packet RESET FFH The reset command instructs the mouse to run its internal self test routine This command puts the mouse into reset mode 124 5 Mouse Io System Replies There are two mouse to system replies Both replies are related to command processing and are read by the system at port 60H ACKNOWLEDGE FAH The mouse replies with an acknowledge FAH whenever it receives a valid command from the system Unlike mouse serial data packets the acknowledge reply is not stored in a buffer in internal memory but is discarded immediately after it is transmitted If a new command is received while the mouse is in the acknowledge reply process the mouse discards the acknowledge reply and
213. mpatible with Revision B chips 1 Enable the Quiet bus PARITY fix 6 0 Allows the software cO PROC reset 1 Blocks the software CO PROC reset 7 0 Compatible with Revision B chips REsET387 CLREXPTION 1 RESET387 CLREXPTION powerup only Figure 8 14 Optional Configuration 2 112 Configuration Registers of the GCK131 Chip Set INDEXOFh OPTCNFG3 INDEXOFh is READ WRITE register which at system power up defaults to a value of The register is available for programming as the means to use and adjust features of the Revision C chip Bit State Usage 0 0 BS16 is compatible with Revision chips 1 The BS16 signal is removed after each cycle 1 0 BS32 is compatible with Revision chips 1 The 532 blocks all but local accesses 2 0 Video BIOS resides in the lower 32Kb chunk in the range C0000h to C7FFFh See Video BIOS space in Window I can be split on Page 89 1 Video BIOS resides in the upper 32Kb chunk in the range C8000h to CFFFFh 3 0 Video BIOS is in size 64Kb 1 Video BIOS is in size 32Kb See Video BIOS space in Window I can be split on Page 89 4 0 Reserved Always program to 0 1 Illegal 5 0 Enables 1 extra clock cycle between ADDSEL and CAS during cycles 1 Disables the extra clock cycle between ADDSEL and CAS during DMA cycles 6 0 The LOCAL signal is latched Compatible wi
214. n effect the controller provides a shadow of the video configuration switches A READ to this port does not strobe CsvREG 120 Configuration Registers of the GCK131 Chip Set INDEX45h EEPROM Control Default value 00h This configuration register is available for programming to control EEPROM accesses It is possible to interface directly with an EEPROM device like the Monolithic Memories Type MC9306 device using suitable programming With this register INDEX45h interface signals of CLOCK DATA and CHIP SELECT can be controlled in order to READ WRITE the EEPROM Bit State Description 0 EEPROM data IN OUT When data is written it appears on pin DOEEP When read the data comes from pin DIEEP 1 EEPROM Clock Data written on this bit appears on pin CKEEP EEPROM chip select 2 0 Output pin CSEEP 0 1 Output pin 5 1 3 0 Reserved Always program to 0 4 0 Reserved Always program to 0 5 0 Reserved Always program to 0 6 0 Reserved Always program to 0 7 0 Reserved Always program to 0 Figure 8 24 INDEX45h EEPROM Control INDEX46h Reserved INDEX47h Revision Identification Default value 02h This contents of READ ONLY configuration register INDEX47h are available for use in programming where the objective is to determine by referencing the Revision Number the availability of certain ATLAS Chip Set
215. nals The A38202 presents an 80386 like interface to the system The signals discussed in this section are the A38202 equivalents of the 80386 signals Bus Address BA3 BA2 BA3 BA2 are the A38202 equivalent of the 80386s low two address bits They are driven from the A38202 when multiple fetch cycles are required Bus Byte Enables BBE3 BBE0 are the A38202 equivalent of the 80386 byte enables These signals reflect the state of the 80386 byte enables except during cache read miss cycles when the A38202 drives all of them low This ensures that a complete subblock is fetched to update the cache Bus Lock BLOCK is the A38202 equivalent of the 80386 LOCK signal When the 80386 executes sequence of locked cycles the A38202 executes the cycles on its local bus regardless of whether the locations accessed currently reside in the cache The A38202 will not allow another master to gain control of the bus while it is executing a sequence of locked cycles Bus Address Status BADS BADS is the A38202 equivalent of the 80386 ADS signal When asserted it indicates that valid address and cycle definition signals are available Bus Ready Input BREADY A38202 local bus cycles are terminated by the assertion of BREADY just as 80386 cycles are terminated by READY BREADY is also gated through to the 80386 by BRDYEN to terminate its cycle 2138 Bus Arbitration Signal
216. ne is to command the controller to switch to low power immediately The other method is to set the controller to automatically go into the low power mode 500ms after the beginning of the idle state based on a 500 kb s MFM data rate This would be invisible to the software The low power mode is programmed through the Mode Command The Data Rate Register and the Drive Control Register are unaffected by the power down mode They will remain active It is up to the user to ensure that the Motor and Drive select signal are turned off Table 13 4 Truth Table for Drive Control Register D7 D6 D5 D4 D1 DO Function X X X 1 0 0 Drive 0 Selected DRO 0 X X 1 X 0 1 Drive 1 Selected DR1 0 X 1 X X 1 0 Drive 2 Selected DR2 0 1 X X X 1 1 Drive 3 Selected DR3 0 200 DP8473 Floppy Disk Controller Crystal Oscillator The DP8473 is clocked by a single 24MHz signal An on chip oscillator is provided to enable the attachment of a crystal or a clock If a crystal is used a 24MHz fundamental mode parallel resonant crystal should be used This crystal should be specified to have less than 1500 series resistance and shunt capacitance of less than 7pF Typically a series resonant crystal can be used it will just oscillate in parallel mode 30 300 ppm from its ideal frequency If an external oscillator circuit is used it must have a duty cycle of at least 40 60 and minimum input levels of 24V and OAV The controller shou
217. ne Detail Procedure Step by Step 230 A73 How to Save Defined Procedure 231 AB Ini FUNCTION y sas Uode ioa dae exce pr ri e dala 231 9 Disp Err FUNCTION 231 A 10 Aging Off Aging On FUNCTION 231 3i 05 tennis cau 232 A 12 ERROR CODE DESCRIPTION 232 12 1 System 21 222 232 A 12 2 Keyboard 22 232 A 12 3 Video Adapter 37 CGA MGA Case Only 233 A 124 Floppy Disk 77 234 A 12 5 Fixed Disk 8 234 126 Printer Port Test 97 235 A 12 7 RS232 Port Test 1 0 2 6c eee IM 235 A 12 9 Ethernet Test 236 13 LOOPBACK PIN CONFIGURATION 237 B MESSAGES Bi INTRODUCTION 25 cie vos pes ee e 239 B 2 POST AND BOOT MESSAGES 239 B 2 1 Post and Boot Error Messages 240 B 2 2 Post and Boot Information Messages 245 B3
218. nored 2 If Bit 3 1 and Bit 2 0 the Video BIOS must reside between CO000h C7FFFh If Bit 3 Y and Bit 2 1 the Video BIOS must reside between C8000h CFFFFh 3 With the 32K Video BIOS feature enabled the unallocated 32K of memory space is available for RAM or backplane memory 75 1 2 CPU Memory Controller Video BIOS Both 32K and 64K Versions can be Shadowed As discussed next the Video BIOS in either 32K or 64K size can be shadowed 64 RAM SHADOWING WINDOWS 1 THROUGH 3 The ATLAS Chip Set supports shadowing for Windows 1 2 and 3 Access through Window 4 is always direct to the system BIOS ROMs Each window has its own special behaviour when shadowing 64 1 Window 1 Video BIOS Shadowing The Video BIOS window is reserved for ROM modules fitted to video adapter cards and similar devices By default after startup all READ and WRITE accesses to this window are directed to the 16 bit AT expansion bus The default mode for Window 1 accommodates unconventional usage of the video BIOS address range by network adapter cards and other devices that put dual ported RAM at this location In the default mode the cards function in the normal manner VBEN Uses INDEX 01h Bit 4 To use the Video BIOS memory window for the Video BIOS set INDEX01h Bit 4 to I All WRITE operations are thus routed to RAM and all READ operations are routed to the expansion bus VBSHADOW Uses INDEX 01h Bit
219. nostic A 7 DESCRIPTION OF AUTOMATIC PROCEDURE DEFINE MODE This mode is used to make new Auto test procedure and is more useful than mode when edit a lot of procedure 1 First select Auto test procedure to define 2 Enter new name of procedure and press Enter key 3 Then following MENU will be shown AT System Diagnostics Version 2 00X Current Time 12 15 28 Copyright C SAMSUNG Electronics Co Ltd 1990 Elapsed Time 03 39 21 TEES 42022 gt 6 7 TM While running Automatic Procedure all time delay loop for Manual Procedure will be passed 71 Description of Error Handling Option 1 MEDAY If selected during Auto test all time delay for user will be skipped to save time 2 Fail Stop If selected this diagnostics waits for user key input on error detection And asks you to save or not error condition If not selected error condition will be saved Automatically into ERROR REC file If not selected Video test will be passed w o user key input If selected waits for user key input Y N In case of key input is N then it assumes error be occurred 4 EULESS If selected it generates 10 times beep sound on error detection A 7 2 Starts to Define Detail Procedure Step by Step 230 Diagnostic 73 How to Save Defined Procedure 1 Press lt End gt key to terminate current job 2 If you want to save then press lt Y gt key then define
220. noted below is available for the selection of REFRESH wait states in number greater than 15 See INDEX42h for more information Bits Value Description 1 0 Additional REFRESH Wait States 0 0 Bits 1 0 0 represent up to 15 wait states available through iNDEX42h 0 1 Represent 16 to 31 REFRESH Wait States available through INDEX42h 1 0 Represent 32 to 47 REFRESH Wait States available through INDEXx42h 11 Represent 48 to 63 REFRESH Wait States available through INDEx42h 7 2 0 Reserved Always program to 0 Figure 8 29 INDEX49h Additional REFRESH Wait States PORT 92h Default value 00h This register is directly mapped into I O location PORT 92h Access to this register is enabled by programming INDEX48h Bit 1 to a value of 1 Once enabled this register PORT92h has the following definition Bit State Meaning 0 0 FAST_RC is selected OFF 1 Apply FAST RC See Note 1 0 Set ALT_MUXPA20 Pin to the LOW condition 1 Set ALT_MUXPA20 Pin to the HIGH condition 7 2 n a Reserved Figure 8 30 INDEX Port 92h FAST_RC and ALT_MUX PA20 Note FAST RC is a single 110 135ns positive pulse that occurs 67ys after setting Bit 0 of PORT92h to a value of TY Bit 0 must be programmed back to a value of 0 before another FAST RC pulse can be generated 125 9 1 DESCRIPTION 9 1 1 A38202 Microcache The Austek A38202 Microcache is a high performance cache
221. nput signals for controlling data transfer to and from the 387 numeric coprocessor BUSY PEREQ 387 request and These input signals connect to the corresponding 387 pins The BUSY signal informs the CPU that the 387 is executing an instruction and cannot accept another The CPU WAIT instruction informs the CPU to wait until the 387 finishes execution The PEREQ signal indicates the 387 needs to transfer data Because the 387 is never a bus owner all input and output data transfers are done by the CPU PEREQ always goes inactive before BUSY goes inactive The 387 asserts an ERROR signal after an instruction results in an error not masked by the 387 control register If an error occurs ERROR goes active As a result the CPU receives an interrupt If a higher priority does not exist the CPU services the interrupt 20 Central Processing Core The 387 detects six different classes of exception conditions that may occur during instruction execution If the proper execution mask is not set by the control register the 387 asserts an ERROR signal The signal generates a hardware interrupt BUSY holding the 387 in a busy state until cleared by the execution of an FNINIT instruction The numeric exception conditions recognized by the 387 are as follows Invalid operations stack fault or IEEE standard invalid operation Divide by zero Denormalized operand Numeric powerflow Nu
222. ns at both ends of the fixed disk control and data cables and reseat the drive controller If the problem persists contact your service representative No boot sector on hard disk strike F1 to retry boot F2 for the Setup utility The fixed disk does not contain an operating system Format the disk with the S option Caution this procedure will destroy data on the disk Refer to your MS DOS Operations Reference Manual for instructions No timer tick interrupt The timer chip on the system board may have failed Contact your service representative Not a boot diskette strike F1 to retry boot F2 for the Setup utility The floppy disk in drive A is not formatted as a system floppy disk 243 Messages Solution Message Possible Cause Solution Message Possible Cause Solution Message Possible Cause Solution Message Possible Cause Solution Message Possible Cause Solution Message Possible Cause Solution Message Possible Cause Solution Replace the floppy disk with a bootable system floppy disk and try again Shadow of System BIOS failed Executing from ROM Strike the F1 key to continue F2 to run the Setup utility The system RAM is difective Check the installation of the SIMMs Shadow of Video BIOS failed Executing from ROM Strike the F1 key to continue F2 to run the Setup utility The system RAM is defective or the video BIOS cannot be shadowed Check the installation of all RIMMs
223. nsmit and receive time out error bits in its status register No retries are attempted by the controller for any transmission error The following commands are sent from the controller to the keyboard SET RESET STATUS INDICATORS EDH The set reset status indicators command activates or deactivates the three LED indicators Num Lock Caps Lock and Scroll Lock on the keyboard The keyboard responds to the command byte with ACK discontinues scanning and waits for the option byte from the controller The contents of the option byte following the command determines the parameter for setting the LED mode Bits 0 1 and 2 of this byte control the Scroll Lock Num Lock and Caps Lock LEDs respectively Bits 3 through 7 are reserved If the bit for an indicator equals 1 the indicator turns on If the equals 0 the indicator turns off The keyboard responds to the option byte with an acknowledge code sets the indicators and resumes scanning ECHO EEH The echo command tests the keyboard command process When the keyboard receives this command it issues an EEH response and continues scanning INVALID COMMAND EFH AND F1H and F1H are invalid commands 177 Keyboard and Mouse Controller SELECT ALTERNATE SCAN CODES The select alternate scan codes command instructs the keyboard to select one of three sets of scan codes The keyboard acknowledges receipt of this command with an acknowledge code then clears both th
224. ntroller The serial data from the keyboard is called a scan code Each keyboard key has an associated 11 bit scan code Pressing and releasing a key generates a make or break scan code The keyboard detects all keys pressed and transfers each scan code in the correct sequence to the controller The controller receives serial data form the keyboard checks the parity of the data and translates the 8 bit scan code into system codes It also interrupts the CPU to transfer data to the system The controller interrupts the system when data is placed in its output buffer or waits for the system to poll its status register to determine when data is available The controller transfers various commands to the keyboard at any time When the controller transfers data to the keyboard it sets the data line to an inactive state and allows the clock line to go active This action serves as a request to send RTS and a start bit Setting the clock line to an inactive state inhibits keyboard transmission If the controller has to transfer data to the keyboard during a keyboard transfer the controller clamps the clock signal line to request a keyboard transfer half The clock line must remain low for at least 60 ms During the keyboard basic assurance test BAT or when no data transfer occurs the clock line remains active high The keyboard holds the data line active high An inactive signal has a value between OV and 0 7V logical 0 An active signa
225. ntroller configures this feature The startup default places the 64K hole at A0000h Figure 6 10 shows a sample memory map with the hole placed at 40000h 83 GC132 CPU Memory Controller 588 FFFFFh 0000 4FFFFh 40000h 0 256K DRAMs One bank No shadowing No REMAP EMS HOLE set to 4 See INDEX03h Figure 6 10 The EMS Hole 68 CONNECTING MULTIPLE BANKS OF DRAM TO THE HTK131 CHIP SET Up to Four Banks The recommended method by which up to four banks of DRAM can be connected is shown in Figure 6 11 Reference Application schematics 386APP 1 GC132 CPU Memory Controller BCAS A0 D0 2 BANKSELO 4 amm PCASD0 sone From BANKSEL1 3 5 BCASD1 HT122 BCASD2 BCASDO ICASD BCASD3 BCASA1 BCASB1 BANKSELO BCASCO From BANKSEL1 13 UE ICASC To BANK1 BCAS A1 D1 ALL RESISTORS 33 OHM BCASO BCAS A2 D2 BANK2 From BANKSEL1 BCASA2 HT132 BCASB2 BCASB 3 BCASC2 BCASD2 BANKSELO BCASAD BCASA3 From BANKSEL1 BCASB3 HT132 BCASA2 BCASC3 ICASA To BANK3 AE BCAS A3 D3 Figure 6 11 Connecting Four Banks of RAM Six Banks Since only two BANKSEL signals are available and when six banks of DRAM are installed Banks 4 and 5 must be selected in a manner different to that used for Banks 0 through 3 For Banks 4 and 5 the recommended system makes use of the EXRASO and EXRAS
226. oard ROM E000 0000 FFFF 2 gue e It tests Checksum of I O Adapter s ROM which is valid and test range is C000 0 D000 FFFF 3 917 It performs R W test of SYSTEM Accessible R W Memory It s test range is Base 640KB and Extend Memory up to 16MB 220 Diagnostic 4 It tests CMOS RAM and save original value 5 It tests speaker tone Numeric key 1 8 will sounds with corresponding frequency displayed Increases current frequency by 10Hz at every stroke Decreases current frequency by 10Hz at every stroke 6 Returns back to MAIN MENU 4 2 BSDE Menu 1 85559458 Sends RESET COMMAND to Keyboard Processor and waits completion code from Keyboard Processor 2 as It tests Make Break Code of every key This test cannot be terminated w o User key input 3 Returns back to MAIN MENU 43 Menu 1 BICIS It tests all Modes and functions on current Video Adapter Note If EGA monitor is attached to VGA adapter then it tests only possible display mode on EGA monitor 2 It tests EGA VGA registers Video RAM and external palette It also tests Read mode 0 1 Write mode 0 1 2 whether it works correctly or not BIDDE Menu 1 FDD Reset Reset FDD system On Manual operation it also does FDD surface scanning 2 Format diskette You must select diskette type as correc
227. on the local bus DC 10 I Data or Control Status line from the 80386 Microprocessor IENADDSTB 103 Enable Address Strobe When LOW the HT131 disables any access to the Real Time Clock This signal is LOW from reset to the first processor access 60 GC132 CPU Memory Controller Pin Pin Pin Symbol Number Type Description ERROR386 56 Error Coprocessor Signals the microprocessor that an error has occurred in the coprocessor ERROR387 50 I Error line from the 80387 Coprocessor EXRASO 136 Row Address Strobes for Banks 4 5 EXRAS1 135 FASTCLK 36 I Main Oscillator Clock Between 32MHz and 50MHz FAST SLOW 43 I Speed Switch When HIGH the output of the clock synchronization circuit PROCCLK is a buffered version of the FASTCLK input When LOW the signal is a buffered version of the SLOWCLK input This signal comes from the 8042 FETEN 13 I Feature Enable When HIGH the features associated with pins BS32 STARTCYL and LOCAL are enabled HLDA 12 I Hold Acknowledge When HIGH the processor has relinquished the address data and status bus when LOW the 80386 is the bus master IINTA 25 Interrupt Acknowledge Indicates that the interrupt vector should be read into the processor IOCHRDY 109 I Channel Ready A signal from the AT backplane requesting additional command active time When LOW the chip will add any number of wait states until the signal is released
228. or Pin Connector Voltage V 1 P9 12V DC 2 GND 210 Power Supply System Power Connector Pin Connector Voltage V DC 1 POWER GOOD Option 2 GND 3 12V DC 4 P1 P3 12V DC 5 8 GND 9 5V DC 10 12 5V DC 211 CLe x x NE M9 S JZ 7 4 APS SLY 748 JELY so NZ BLY 9717 M7 PE g9u sso 9717 PPL 701 AOS 652 39 c 971 7 lt 94 gst 2 XL 65 9 0 9 S O 9 O esnoo 145 5 27 SMPS COMPONENTS LAYOUT 3503 30 5NI1YH QNY 3NYS HIIM AINO 32Y1 QuYZYH 3513 L1SNIYOY 01123103 Q3NNILNOD M c su 21 OAE 3S8 Q3SB 213 146 SWITCHING POWER SUPPLY PS 27 PARTS LIST Location No Description R15 20 33 51 64 R METAL FILM R75 R METAL FILM R27 31 55 58 61 R METAL FILM R54 R METAL FILM R53 56 62 63 68 R METAL FILM R73 76 77 78 79 R METAL FILM R65 67 R METAL FILM R28 32 R METAL FILM 17 34 R METAL FILM R16 R METAL FILM R60 R METAL FILM R35 R METAL FILM R14 R METAL FILM R30 R METAL FILM R59 66 70 71 R METAL FILM R26 52 R METAL FILM R57 81 R METAL FILM R80 R METAL FILM RA R METAL FILM R13 R METAL FILM R1 R METAL FILM R18 19 21 22 R METAL OXIDE R24 25 R METAL OXIDE R9 11 R METAL OXI
229. pass through transparent address latches to the bus AEN AEN DMA Address Enable is asserted by the PRA when its CPU is in the hold mode and its controller has control of the ISA bus AEN is negated by the PRA when its CPU is in control of the ISA bus or when the DMA controller has granted the ISA bus to an SRA When AEN is asserted all agents other than the PRA must tri state their address signal group and cycle control signal group outputs to the ISA bus 26 ISA Bus Interface During DMA cycles the validity of LA 23 17 A 19 0 is indicated by the assertion of both AEN and BUSALE SRAs cannot conduct DMA cycles because only the PRA can drive the DACKn and AEN signals 44 2 Data Signal Group The data signal group consists of one set of 16 data bits Data transfers may occur over either of the two bytes independently of one another D 15 0 I O On the D 15 0 Data Bus D15 is the most significant bit and D0 is the least significant bit All 8 bit replying agents must connect only to the least significant eight data lines D 7 0 To support communication of 8 bit replying agents to 16 bit requesting agents both data swapping and transfer reformatting are supported by the PRA During odd byte transfers between a 16 bit requesting agent and an 8 bit replying agent the PRA drives the data appearing on D 7 0 onto D 15 8 Transfer reformatting is accomplished by the PRA when it formats 16 bit accesses to 8 bit
230. port Signals These signals form the A38202s bus watching interface The snoop bus connects to the system address bus if other bus masters exist at both the system and A38202 local bus level If masters exist only at the A38202 local bus level these signals connect to the A38202 local address bus In this case should be connected to the nand of BM IO BW R and BHLDA SMEMW should be connected to BADS Note These inputs may be asynchronous to CLK2 Snoop Address Bus SA31 SA6 These signals are the inputs for the lookup and compare circuitry that determines when a snoop hit has occurred 140 Snoop Bus Control SAV SMEMW SAV and are the snoop bus equivalent signals to the A38202s local bus status signals They are used to indicate to the A38202 when a valid cycle is present on th snoop bus When 5 is asserted and SAV is low indicating the snoop address is valid the A38202 performs a snoop invalidation cycle 94 PROGRAMMABLE REGISTERS AND INSTRUCTION SET Programming the A38202 will generally be carried out by the operating system as part of the initialization process Once the cache has been initialized few instances will arise where additional programming is necessary The following instructions can be executed by the A38202 Microcache INVALIDATE ALL Invalidates all tags in the Microcache effectively purging the cache of data SET NONCACHED REGION
231. r 43 Even Odd mode test Error 44 CRIC TS GDC ATC test Error 45 Internal REG test Error 46 Ext palette short test Error 47 Ext palette R W test Error 48 Translation ROM data test Error 49 EGA VGA Chip diagnostics Error 50 Color Attribute test Error 51 Character set test Error 52 80X25 mode test Error 53 40X25 mode test Error 54 80X60 mode test Error 55 320X200 palette 0 test Error 56 320X200 palette 1 test Error 57 640X200 2 color test Error 58 640X200 16 color test Error 59 640X350 16 color test Error 5A 640X480 16 color test Error 5B 800X600 16 color test Error 5C 1024X768 16 color test Error 5D 320X200 256 color test Error 5E 640X480 256 coloor test Error 5F 8 page change test Error 60 Text scrolling test Error 61 2 font display test Error 62 8 font display test Error 233 Diagnostic 63 Panning Split screen test Error 64 Smooth scroll test Error 65 Window Zoomming test Error 66 100X50 16 color test Error 67 720x512 16 color test Error 68 Video display test Error 69 Load amp Exec Error A 124 Floppy Disk 7 70 Reset Error 00 4 Error Drive 0 1 71 Format Error 00 00 no meaning 72 R W Test Error XX XX LL h00sssss s Error Sector 1 12H h Error Head 0 1 t Error Track 0 4 d Error Drive 0 1 73 Seeking Error dO tt
232. re 8 26 INDEX48h Mode Reconfigure Note The default initiated at system power up defines all pins to identical settings as those of Rev chips 122 Configuration Registers of the GCK131 Chip Set P92B0 6 7 ps Nominal 110 135 ATA17 FAST_RC ATA18 ALT MUX PA20 P92B1 Figure 8 27 Port 92 FAST_RC and ALT_MUXPA20 Timing 123 Configuration Registers of the GCK131 Chip Set On board connections of FAST RC and MUXPA20 OLD_MUXA20 From 8042 1 3 BOARD MUXPA20 Keyboard Controller 2 To HT132 CPU Memory Controller ALT_MUXPA20 From HT131 Peripheral Controller ENP92 FAST_RC 3 386 RC From HT131 To HT132 Peripheral Controller CPU Memory Controller RC From 8042 Keyboard Controller OLD MUXA20 1 From 8042 C Keyboard Cannel BOARD MUXPA20 To HT132 ALT_MUXPA20 CPU Memory Controller From HT131 Peripheral Controller ENP92 FAST_RC From HT131 Peripheral Controller 8 386 RC To HT132 CPU Memory Controller RC From 8042 Keyboard Controller Figure 8 28 FAST_RC and ALT_MUXPA20 Connections 124 1 i Configuration Registers of the GCK131 Chip Set INDEX49h Additional REFRESH Wait states Default value 00h This register extends the range in combination with the status of Bits 0 3 of INDEX42h to 63 programmable REFRESH wait states INDEX49h as
233. refer to the Intel Microprocessor and Peripheral Handbook 14 Central Processing Core CLK2 I CLK2 is the clock input pin CLK2 provides the fundamental timing for the 386 and is driven by a 66MHz crystal CLK2 is divided by two internally to generate the internal processor clock used for instruction execution D31 0 I O D31 0 are the data bus signals These tri state bidirectional signals provide the general purpose data path between the 386 and other devices A31 2 O A31 2 are the address bus sugnals These tri state outputs provide physical memory addresses or port addresses for the system BE3 0 O BE3 0 are the byte enable signals These signals directly indicate which bytes of the 32 bit data bus are involved with the current teansfer ADS O ADS is the address status signal This tri state output indicates that a valid bus cycle definition and an address W R D C and BE3 0 A31 2 is being driven at the 386 pins ADS is asserted during T1 and 2 bus states M IO is the memory or I O select signal This tri state signal distinguishes between memory and I O cycles D C O D C is the data or control select signal This tri state signal distinguishes between data and control cycles 15 Central Processing Core WIR O is the write or read select signal This tri state signal distinguishes between write and read cycles LOCK LOCK i
234. rogrammable 16 bit timing for Backplane accesses 2 1 Bit 2 Bit 1 0 0 7 CLKIN periods Command Active for 16 bit RAM 0 1 9 CLKIN periods 1 0 11 CLKIN periods 1 1 13 CLKIN periods 4 3 Bit 4 Bit 3 0 0 18 CLKIN periods Command Active for 16 bit I O 0 1 22 CLKIN periods 1 0 28 CLKIN periods 1 1 34 CLKIN periods 6 5 Bit 6 Bit 5 0 0 10 CLKIN periods Command Delay for 16 bit 0 1 12 CLKIN periods 1 0 16 CLKIN periods 1 1 18 CLKIN periods 7 0 Compatible with Rev B chips 1 Enables FAST page mode on board DRAM access Figure 8 13 Optional Configuration 1 111 Configuration Registers of the GCK131 Chip Set INDEXOEh 2 INDEXOEh is a READ WRITE register which at system power up defaults to a value of OOH The register is available for programming as the means to use and adjust features of the Revision C chip Bit State Usage 1 0 Bit 1 Bit 0 0 0 1 CLKIN period Command Advance for MEMW 0 1 2 CLKIN periods 1 0 3 CLKIN periods 1 1 1 CLKIN period 2 0 Compatible with Revision B chips 1 The RC signal is blocked until HLDa is inactive 3 0 Compatible with Revision B chips 1 The SHUTDOWN cycle begins after the DRAM cycle is completed 4 0 Compatible with Revision B chips 1 Enable the DRAM interleave fix 5 0 Co
235. rred to from memory by the 386 In response the 386 tranfers information between the coprocessor and memory Because the 386 has internally stored the coprocessor opcode being executed it performs the requested data transfer with the correct direction and memory address PEREQ is level sensitive and is asynchronous to the CLK2 signal BUSY D BUSY is the coprocessor busy signal This input signal indicates the coprocessor is executing an instruction and is not able to accept another When the 386 encounters any coprocessor instruction which operates on the numeric stack for example load pop or arithmetic operation or the WAIT instruction this input is automatically sampled until it is seen negated This sampling of the BUSY input prevents overrunning the execution of a previous coprocessor instruction The CPU program execution stops as long as the BUSY signal remains active BUSY is level sensitive and is asynchronous to the CLK2 signal ERROR D ERROR is the coprocessor error signal This input signal indicates the previous coprocessor instruction generated a coprocessor error of a type not masked by the coprocessor s control register This input is automatically sampled by the 386 when a coprocessor instruction is encountered and if asserted the 386 generated exception 16 to access the error handling software ERROR is level sensitive as asynchronous to the CLK2 signal xy Central Processing Core RESET D RESET
236. rrent internal address bus values and indicates when requested data is present signifying a cache read hit 129 Static RAM Controller The static RAM controller takes addresses from the internal address bus and performs read and write operations to the cache memory INVALIDATE STROBE INVALIDATION ADDRESS BUS PROCESSOR PROCESSOR SRAM CONTROL INTERFACE amp SRAM ADDRESS BUS CONTROLLER amp ENABLE PROCESSOR ADDRESS BUS INTERNAL CONTROL BUS PIPELINE REGISTER INTERNAL ADDRESS BUS SYSTEM INTERFACE NONCHCHED and WRITE BUFFER COMPARATORS CONTROLLER LATCH AND TRANSCEIVER CONTROLS SYSTEM BUS CONTROL Figure 9 1 A38202 Internal Configuration 130 VALID BITS ADDRESS TAGS SUBBLOCK PRESENCE FIELDS 10 256 a 256 16 4 PRESENCE BIT SELECTOR 8 13 6 SET NUMBER EE SUBBLOCK NUMBER BLOCK BL PRESENT SUBULO PRESENT ADDRESS BUS CONTROL BUS Figure 9 2 Tag RAM Organization System Interface Controller The system interface controller provides the handshaking and control signals to manage the system interface for any cycles which are not cache read hit cycles The system interface controller has been designed to resemble the 80386 bus interface thus simplifying the design of the A38202 into existing 803
237. rs and Pinouts System board header J13B provides signals for both ports and connects to two 9 RS 232 connectors COM1 and 2 Refer to Chapter 18 for pinout information of the serial communication connectors 165 Communication Ports 113 PARALLEL PRINTER PORT The system board uses one parallel printer port The parallel printer port provides a one way interface to a printer Onboard jumpers select the leading or trailing edge of printer acknowledge and enables interrupt generation Discrete logic provides interfacing between the parallel printer port and the printer Setting jumper on the system board selects the port addresses and interrupt levels refer to Table 11 2 Table 11 2 Port Address and Interrupt Levels Port Address Interrupt LPT1 0378 037FH IRQ7 LPT2 0278 027FH 5 11 3 1 Programming The system board uses the read write status and control signal registers to transmit data and status to and from the printer System software executes all printer controls Tables 11 3 and 11 4 list input and output instruction information Table 11 5 lists the parallel port registers Table 11 3 Input Instructions Input Instruction Port 1 Port 2 Data Read 0378H 0278H Status Read 0379H 0279H Control Signal Read 037AH 027AH Table 11 4 Output Instructions Output Port 1 Port 2 Function Instruction Write Data 0378H 0278 Character to Print Write 037AH 027AH STROBE Control INITIALIZE AUTO F
238. s BHOLD BHLDA BHOLD is an input from another master requesting usage of the system bus BHLDA is an output granting the bus to the requestor The functionality is identical to that of the 80386s HOLD and HLDA signals 9 3 5 Burst Mode Control Signals When the A38202 is operating with 16 byte subblocks four fetches are required to fill each subblock In this case the A38202 will request a burst fill by asserting BURSTREQ at the start of the bus cycle If the system bus is able to respond with a burst of data the signal BURSTACK should be asserted during any 2 T state before the first assertion of BREADY If BURSTACK is sampled asserted before BREADY th A38202 will expect to receive a burst of data to fill the subblock If BURSTACK is not simpled asserted before BREADY the A38202 will initiate three more read cycles to fill the subblock 9 3 6 Latch and Transceiver Control Signals The A38202 data bus is the system side of a latching transceiver and the A38202 address bus is the system side of a latching buffer The controls for these latches and transceivers are discussed in this section Latch Control Signals BACK AOE These signals are designed to connect directly to an F or AS series 71374 or similar device BACP is used to latch addresses from the 80386 on its rising edge AOE controls the output enable on the latches Transceiver Control Signals BDCP DOE and DT R These signals are designed to conn
239. s are inputs which 97 contain the parity data bit from the DRAM 102 These will be checke against a calculated version based on the LD0 31 lines If there is an error the PARITY signal will go active in the next bus cycle During a memory write these lines are outputs containing the calculated parity for each byte PARITY 57 O PARITY Check When active at the end of a memory read cycle it indicates a parity error on the DRAM 65 GC132 CPU Memory Controller Pin Pin Pin Symbol Number Type Description PBENO to 15 18 I Processor Byte Enable Indicates which of PBEN3 the four processor data bytes has valid data PDO to PD7 64 71 Processor or DRAM Data Lines Lower 8 bits are actually bi directional They are inputs during a configuration register WRITE or a memory READ for PARITY generation PD8 to 72 79 I Processor or DRAM Data Lines Always PD31 81 96 inputs used for calculating parity during memory reads PEREQ386 55 Processor Extension Request Connected to the PEREQ line of the 80386 Microprocessor PEREQ387 49 I Processor Extension Request Connected to the PEREQ line of the 80387 Coprocessor PGVIOL 145 I Page Violation During a memory operation the HT133 will constantly compare the current DRAM page strobed in by the RAS signal with the current page presented by the processor for the next cycle If the two pages are different this signal will go active PROCCLK 38 Processor Clock
240. s listed earlier 2 3 1 Central Processing Unit CPU The CPU incorporates multitasking support memory management address translation caches and a high speed 32 bit bus interface The CPU must runs at a clock speed of 33 3MHz resulting in a system speed of 30ns per clock cycle For applications requiring slower operation such as installing some copy protected software the system provides a deturbo slow mode reduces the effective system operating speed to 8MHz 2 3 2 Memory The system board contains three types of memory ROM cache memory fag memory and DRAM The system board contains 256K of ROM containing the BIOS power on self test POST and setup program The 64K direct mapped cache memory consists of eight static random access memory SRAM chips The cache provides zero wait state read performance and one wait state write performance during CPU accesses The cache tag memory consists of three SRAM chips and supplies 12 bit tag data for address comparison The system board contains 4M expandable 24M of DRAM 2 33 ISA Bus The system is compatible with the ISA bus I O expansion boards communicate with the system via ISA bus 234 GCK131 Chip Set GCK131 chip set consists of three chips GC131 Peripheral controller GC132 CPU Memory controller and GC133 Bus bridge interface EE Board Overview GC131 Peripheral Controller This single chip effectively replaces two 8259 programmable
241. s table on This is the bandwidth of the PLL and is given by KPLL 2rC2N R1 on where N is the number of VCO cycles between two phase comparisons The value of N for the various data rates are shown in Table 13 2 The damping factor is set to 0 7 to 1 2 and is given by wnR2C2 2 The trade off when choosing filter components is between acquisition time while the PLL is locking and jitter immunity while reading data To select the proper components for a standard floppy disk application the following procedure can be used 1 Choose FM or MFM and data rate Determine N from Table 13 2 Determine preamble length MFM 12 The PLL should lock within 1 2 the preamble time 2 Determine loop bandwidth wn required and set the charge pump resistor R1 3 Calculate C2 using KPLL 2zxR1Non2 4 Choose R2 using Bo anC2 6 Select C1 to be about 1 20th of C2 The above procedure will yield adequate loop performance If optimum loop performance is required or if the nature of the loop performance is very critical then some additional consideration must be given to choosing wn and the damping factor For a detailed description on how to choose wn and see AN 505 Floppy Disk Data Separator Design Guide for the DP8472 DP8473 and DP8474 198 DP8473 Floppy Disk Controller 134 5 Write Precompensation The DP8473 incorporates a single fixed 3 bit shift register This shift register outpu
242. s the locked bus selection signal This tri state output distinguishes between locked and unlocked bus cycles BS16 D BS16 is the bus size signal This signal allows the 386 to directly connect to 32 bit and 16 bit data buses Asserting this input constrains the current bus cycle to use only the lower half D15 0 of the data bus corresponding to BEO and or BE1 Asserting BS16 has no additional effect if only BEO are or BET are asserted in the current cycle However during bus cycles asserting BE2 or asserting BS16 will automatically cause the 386 to make adjustment ws for correct transfer of the upper bytes using only physical data signals D15 0 If the operand spans both halves of the data bus and BS16 is asserted the 386 will automatically perform another 16 bit bus cycle READY READY is the transfer acknowledge signal This input indicates the current bus cycle is complete and the active bytes indicated by BE3 0 and BS16 are accepted or provided When READY is sample asserted during a read cycle or interrupt acknowledge cycle the 386 latches the input data and terminates the cycle When READY is sample asserted during a write cycle the prodessor terminates the bus cycle HOLD D HOLD is the bus hold request signal This input indicates some device other than the 386 requires bus mastership The device must keep HOLD asserted as long as it is a bus master HOLD is level sensitive and is a synchronous inp
243. se of a command if it is in the non DMA mode In other words if this bit is set the multiple byte data transfer in the Execution Phase must be monitored by the P either through interrupts or software polling as described in the Processor Software Interface section 201 DP8473 Floppy Disk Controller D4 Command In Progress Bit is set after the first byte of the Command Phase is written Bit is cleared after the last byte of the Result Phase is read If there is no result phase in a command the bit is cleared after the last byte of the Command Phase is written D3 Drive 3 Seeking Set after the last byte of the Command Phase of a Seek or Recalibrate command is issued for drive 3 Cleared after reading the first byte in the Result Phase of the Sense Interrupt Command for this drive D2 Drive 2 Seeking Same as above for drive 2 D1 Drive 1 Seeking Same as above for drive 1 20 Drive 0 Seeking Same as above for drive 0 13 5 2 Data Register Read Write This is the location through which all commands data and status flow between the CPU and the DP8473 During the Command Phase the loads the controller s commands into this register based on the Status Register Request for Master and Data Direction bits The Result Phase transfers the Status Registers and header information to the P in the same fashion Table 13 5 Data Rate and Precompensation Programming Values Data Rate Normal Alternate FGND RPM LC
244. second byte and the resolution is as follows Byte Resolution 1 00H 1 count per mm 01H 2 counts per mm 02H 4 counts per mm 03H 8 counts per mm 180 ERN Keyboard and Mouse Controller STATUS REQUEST E9H The status request command generates a three byte status report The format of the mouse status request bytes is shown in Table 12 6 Table 12 6 Format of Status Request Bytes Byte Function 3 Sampling Rate Bit7 Most significant bit Bit 0 Least signficiant bit 2 Resolution Bit7 Most significant bit Bit 0 Least significant bit 1 Mouse status Bit7 Reserved Bit 6 0 Stream mode 1 Remote mode Bit 5 0 Disabled 1 Enabled Bit 4 0 Scaling 1 1 1 Scaling 2 1 Bit3 Reserved Bit 2 1 Left mouse button pressed Bit 1 Reserved Bit 0 1 Right mouse button pressed SET STREAM MODE EAH In set stream mode the mouse transmits data to the system each time a mouse button is pressed or released or each time the mouse detects a unit of movement the mouse data sample rate determines the maximum number of times per second that mouse data can be transmitted to the system If no button is pressed or if the mouse is not moved no data is transmitted The set stream mode command enables the stream mode READ DATA EBH The read data command forces the transmission of one mouse data packet The read data command is valid in both stream mode and remote mode RESET WRAP MODE ECH
245. senq ATLO 6 3RKT BLANK 2424 471 920 SPE WIS 27 BoLT SPECUL 4704 402 604 28 BOLT MAwDLE togu 410 bao 2 29 SPRING STAND 16614 20 BRKT TENSION 96614 9 6 IU 311 COLOR BARB 96954 9 0 PLATE STWO 99454 gt 90 90 SUSZONE 33 FAW 78709 i AE LOCK Hy Fen 340 35 screw 94294 30 042 FE Few if 6 BALL STAND 72484 770 2 STEEL i 4 37 SPEAKER pezos 32 70 1 ws d X 7 s a X AE m EXPLODED VIEW UN MD
246. ss 25H 3 2 4 Keyboard controller test failure 27H none Real time clock power failure or checksum failure 28H 248 Messages Table B 2 Beep Codes for Non fatal Errors Beep Code none 3 3 4 3 4 1 3 4 2 none none none none none Description of Error Contents of Port 80H Real time clock configuration 29H Screen memory test failure 2BH Screen initialization failure 2CH Screen retrace test failure 2DH Search for video ROM in progress 2EH Screen running with video ROM 30H Monochrome display operable 31H Color display 40 column operable 32H Color display 80 column operable 33H 249 SCHIMETIC 251 4 Y 4 ta NC 6 m our vss 5 BEAD 106 1MF 222 II506cLK 4 86 R17 33 821 33 R22 33 PUT 5136 aLUCLX gt R20 33 gt R19 33 e C134 CACHCLK gt 1MF vec N 1 1 L3 PLO BEAD RESET 3 ono z HEABTR 2 NC VCC R25 Yee vec 0 Zjvss_out IRD ves nas BEAD 28 63MHZ OSC 8 1N4148 R34 47K 2 2 10K U34A C93 y SYSRESET gt 74 514 744 514 EE NA d e R 92 406 PHRGOODN gt 1 IMF lt D 0 12 EEN C121 C122 Ov GND Lome 0 55 C119 C120 c C16 C26 C36 Ces REED 5 53 2 O 5V 7 10 Tome iomF t 10mMF 10MF 1 t
247. st is aborted while in progress 247 Messages Table B 1 Beep Codes for Fatal Errors Description of Error aie none 386 register test in progress 01H 1 1 3 Real time clock write read failure 02H 1 1 4 ROM BIOS checksum failure 03H 1 2 1 Programmable Interval Timer failure 04H 1 2 2 initialization failure 05H 1 2 3 DMA page register write read failure 06H 1 3 1 RAM refresh verification failure 08H none 1st 64K RAM test in progress 09H 13 3 1st 64K RAM chip or data line failure multi bit OAH 1 3 4 1st 64K RAM odd even logic failure OBH 1 4 1 1st 64K RAM address line failure OCH 1 4 2 1st 64K RAM parity test in progress or failure 2 1 1 Bit 0 Ist 64K RAM failure 10H 2 1 2 Bit 1 Ist 64K RAM failure 11H 2 1 3 Bit 2 1st 64K RAM failure 12H 2 1 4 Bit 3 1st 64K RAM failure 13H 2 2 1 Bit 4 1st 64K RAM failure 14H 2 2 2 Bit 5 1st 64K RAM failure 15H 2 2 3 Bit 6 1st 64K RAM failure 16H 2 2 4 Bit 7 1st 64K RAM failure 17H 2 3 1 Bit 8 1st 64K RAM failure 18H 2 3 2 Bit 9 Ist 64K RAM failure 19H 2 3 3 Bit A 1st 64K RAM failure 1AH 2 3 4 Bit 1st 64K RAM failure 1BH 2 4 1 Bit C 1st 64K RAM failure 1CH 2 4 2 Bit D 1st 64K RAM failure 1DH 2 4 3 Bit E 1st 64K RAM failure 1EH 2 4 4 Bit F 1st 64K RAM failure 1FH 3 1 1 Slave DMA register failure 20H 3 1 2 Master DMA register failure 21H 3 1 3 Master interrupt mask register failure 22H 3 1 4 Slave interrupt mask register failure 23H none Intrrupt vector loading in progre
248. stem must be fitted with an even multiples of four banks either 4 banks or 8 banks The user couldn t use this interleaving method with for example five banks of installed DRAMs The modified four way interleaving on the other hand which requires the use of paierd DRAMSs is less restrictive on the user s configuration 664 Six Banks of DRAM When the last two banks are added DRAM is treated in a different manner The fifth and sixth banks have their own ENABLE configuration bits INDEXOOh Bit 4 and their own set of timing configuration regsisters INDEX05h Typically no machine has more than four banks of DRAM on the main memory board due to the expense above this point in design plug in memory boards are used The plug in boards typically have buffered DATA ADDRESS and RAS CAS signals which would necessarily have timing that differs from those of the on board DRAM hence a new set of timing configuration registers are needed Once the banks are enabled they must be populated with the same DRAMs as Banks 2 and 3 This means that Banks 0 1 2 and 3 must be populated before Banks 4 and 5 are turned ON 67 EMS HOLE The ATLAS Chip Set can be configured to accommodate a 64K hole in the memory map below 640K This feature enables the use of EMS memory cards that need a 64K spot to position their memory within the range 256K to 768K The 64K hole appears to the system as offboard RAM INDEX03h in the HT132 Co
249. ster and the recorded track number is FF 00 Missing Address Mark in Data Field Controller cannot find the Data Field Address Mark during Read Scan command Bit 0 of ST1 is also set 13 64 Status Register 3 ST3 D7 Not Used 0 D6 Write Protect Status D5 Not Used 1 D4 Track 0 Status D3 Not Used 0 D2 Head Select Status D1 DO Drive Selected 00 Drive 0 selected 01 Drive 1 selected 10 Drive 2 selected 11 Drive 3 selected 13 7 PROCESSOR SOFTWARE INTERFACE Bytes are transferred to and from the disk controller in different ways for the different phases in a command 1371 Command Sequence The disk controller can perform various disk transfer and head movement commands Most commands involve three separate phases Command Phase The 4P writes a series of bytes to the Data Register These bytes indicate the command desired and the particular parameters required for the command the bytes must be written in the order specified in the Command Description Table The Execution Phase starts immediately after the last byte in the Command Phase is written Prior to performing the Command Phase the Drive Control and Data Rate Registers should be set Execution Phase The disk controller performs the desired command Some commands require the P to read or write data to or from the Data Register during this time Reading data from a disk is an example of this 206 DP8473 Floppy Disk Controller R
250. t your service representative Note The following seven messages have the same possible cause and solution Message Message Memory address line failure at hex value read hex value expecting hex value Memory data line failure at hex value read hex value expecting hex value 242 Messages Message Message Message Message Message Possible Cause Solution Message Possible Cause Solution Message Possible Cause Solution Message Possible Cause Solution Message Possible Cause Memory high address line failure at hex value read hex value expecting hex value Memory double word logic failure at hex value read hex value expecting hex value Memory odd even logic failure at hex value read hex value expecting hex value Memory parity failure at hex value read hex value expecting hex value Memory write read failure at hex value read hex value expecting hex value One of the SIMMs or associated circuitry has failed Check that all SIMMs are installed correctly No boot device available strike F1 to retry boot F2 for the Setup utility If booting from a floppy disk it is nonbootable or defective or the floppy disk drive is defective If booting from a fixed disk it may not be formatted as a system disk or is defective The problem could also be in the drive controller board Make sure that the floppy disk in drive A or the fixed disk contains an operating system Check the connectio
251. tate their address data and control signals After SECMAST is asserted the Secondary requesting agent must wait at least one SYSCLK period before driving the address and data group signals and it must wait at least two SYSCLK periods before driving the cycle control group signals If SECMAST is asserted for longer than 15y the SRA must initiate refresh cycles to maintain DRAM data integrity Note that only DMA channels programmed in the cascade mode may be used by SRAs wishing to gain control of the ISA bus IOCHCK D I O Channel Check may be asserted by any agent to signal an error condition that cannot be corrected such as a memory parity error IOCHCK must be asserted for at least 15 for the PRA to recognize that an error condition has occured 29 ISA Bus Interface RESETDEV O RESETDEV Reset is asserted by the PRA to initialize all agents on the ISA bus after power up or during a low voltage condition SYSCLK O SYSCLK System Clock has a frequency of 8MHz with 50 duty cycle and it is driven by the PRA Bus cycle times are directly proportional to the clock period All synchronous signals on the ISA bus are synchronous to SYSCLK Bus cycles are lengthened by IOCHRDY or shortened by SRDY in integer multiples of one half the SYSCLK period For example SRDY could be asserted during a 16 bit cycle to reduce the command pulse width to 1 5 SYSCLK periods Likewise IOCHRDY could lengthen a 16
252. ted regardless of which analog display is connected The new modes available are 640x480 graphics in both 2 and 16 colors 720x400 alphanumeric in both 16 color and monochrome 360x400 16 color alphanumeric 320x200 graphics with 256 colors 1 34 I O Ports Two serial and one parallel I O ports are built in on the mother board which can be disabled if necessary 1 35 PS 2 Mouse Port A PS 2 mouse port is provided on the system mother board 1 36 Software MS DOS version 4 01 and GW BISIC comes with the system Almost all of the softwares written for the IBM personal computers run on your computer with full compatibility but faster BOARD OVERVIEW 2 1 INTRODUCTION This chapter provides an overview of the system board Included in this chapter is a list of features a block diagram of the board and a description of the feature set 2 2 OVERVIEW The system board contains the fallowing components 33MHz 386 central processing unit CPU A numeric coprocessor socket Intel 80387 or Weitek 3167 64K cache memory Expandable up to 128K A 38202 cache controller Standard 4MB of random access memory DRAM Expandable up to 24M e 256K read only memory GCK131 Chip set made by LSI Logic e DS1287 real time clock calendar with integral lithium battery 16C452 port controller and ports 2 serial and 1 parallel 842 Keyboard Mouse controller and connectors DE interface logic and connector 8473 Floppy
253. tem An earlier example See INDEX06h to INDEX09h Tailor timing requirements On the following pages Figure 8 11 through 8 14 introduce various timing relationships that can be programmed into the system The relationships are multiples of CLKIN cycles Figure 8 9 diagrams the relationships Bit State Description 0 0 Three command delays in CLKINS 1 Five command delays 2 1 Bit 2 Bit 1 The combination of Bits 2 and 1 select the following 0 0 Eight command active times CLKINs 0 1 command active times 1 0 Twelve command active times 1 1 Fourteen command active times 4 3 Bit 4 Bit 3 The combination of Bits 4 and 3 select the following 0 0 Two RECOVERY times in CLKINS 0 1 Four RECOVERY times in CLKINS 1 0 Six RECOVERY times in CLKINS 1 1 Eight RECOVERY times in CLKINs 5 1 Reserved Always program to 6 1 Reserved Always program to 1 7 1 Reserved Always program to 1 Figure 8 10 INDEX06h EPROM Configuration 108 Configuration Registers of the GCK131 Chip Set INDEX07h I O Channel RAM configuration Default value FFh Configuration registers INDEx06h through 09h are available to tailor the timing requirements for various commands of the system An earlier example See to INDEXO9h Tailor timing requirements The timing indicated in the following Figure is related to CLKIN cycles Bit Stat
254. tes address is in the lower 16 Mb of memory Master Mode request When active the peripheral device on the backplane is requesting that it become the SYSTEM MASTER where it will drive the adress command refresh and data lines The device may drive REFRESH to request a REFRESH cycle Factory Test Pin Normally connected to VDD GC131 Peripheral Controller Pin Pin Pin Symbol Number Type Description MEMR 3 2 NDTSTOUT 8 NMI 136 OSC 18 OPTBUFFULL 23 I PARCS 103 O Memory Read Normally an input except during DMA when the DMA controller will drive it this signal is generated by the HT131 Controller for CPU bus cycles by the HT131 Controller for DMA cycles or by an external bus master on the I O channel It is also generated by the HT131 Controller for refresh cycles Memory Write Normally an input except during DMA when the DMA controller will drive it this signal is generated by the HT132 Controller for CPU bus cycles by the HT131 Controller for DMA cycles or by an external bus master on the I O channel Factory Test Pin To be left unconnected Non Maskable Interrupt to the 80386 A request to the CPU for immediate service This signal is generated by or It is enabled by bit 7 of the NMI Mask register PARITY and IOCHCK are individually enabled by bits in the Port B register of the HT131 Controller
255. th Revision chips 1 The LOCAL signal is allowed to flow through 7 0 Compatible with Revision B chips 1 BALE is held LOW during quiet bus local accesses Figure 8 15 Optional Configuration 3 113 Configuration Registers of the GCK131 Chip Set INDEXO09h Interrupt acknowledge configurations Default value FFh Configuration registers INDEX06h through 09h are available to tailor the timing requirements for various commands of the system An earlier example See iNDEX 6h to INDEX09h Tailor timing requirements The timing indicated in the following Figure is related to CLKIN cycles Bit State Description 0 0 Three command delay times in CLKIN cycles 1 Three command delay times in CLKINs 2 4 Bit 2 Bit 1 The combination of Bits 2 and 1 select the following 0 0 Five command active times in CLKINS 0 1 Seven command active times 1 0 Nine command active times 1 1 Eleven command active times 3 0 Two RECOVERY times in CLKINS 1 Four RECOVERY times in CLKINS Reserved Should always be programmed to 1 Reserved Should always be programmed to 1 Reserved Should always be programmed to 1 Reserved Should always be programmed to 1 S x ND Figure 8 16 INDEX09h Interrupt Acknowledge Configuration INDEXOAh through OFh are Test registers Indices 0Ah OBh ODh 0Eh and OFh are test registers and
256. the Data Register The xP should transfer the byte within the time alloted by Table 13 6 If the byte is not transferred within the time allotted an Overrun Error will be indicated in the Reset Phase when the command terminates at the end of the current sector 207 DP8473 Floppy Disk Controller An interrupt will also be generated after the last byte is transferred This indicates the beginning of the Reset Phase Bits 7 and 6 of the Main Status Register will be set and bit 5 will be clear This interrupt will be cleared by reading the first byte in the Result Phase 13 74 Software Polling If the non DMA mode is selected and interrupts are not suitable the P can poll the Main Status Register during the Execution Phase to determine when a byte is ready to be transferred In the non DMA mode bit 7 of the Main Status Register reflects the state of the interrupt pin Otherwise the data transfer is similar to the Interrupt Mode described above 208 14 POWER SUPPLY 14 1 OVERVIEW The POWER SUPPLY provides power every board installed in Main Board Floppy Disk Drive Hard Disk Drive and the Keyboard It also provides power for the monitor through its outlet This chapter describes the performance characteristics of a 275 Watts 4 outputs level switching mode power supply 14 2 FUNCTIONAL DESCRIPTION 14 2 1 Input Requirements The power supply can operate at a frequency of either 50 3Hz or 60 3Hz and it can oper
257. the cache SRAM output enables They respectively enable either bank 0 or bank 1 to drive the 80386 data bus For direct mapped caches both of these signals are active since there is only one bank of cache SRAM For 2 way set associative caches the state of these signals will reflect which set a match was found in Cache Write Enables W1 W0 W0 and W1 are active low signals which tie to the cache SRAM write enables They respectively enable either bank 0 or bank 1 to write data from the 80386 data bus For direct mapped caches both of these signals are active For 2 way associative caches only one will be active depending on which bank is to be updated Cache Chip Selects CS3 CS0 These active low signals connect to the cache SRAM chip selects and individually enable the four bytes of the 32 bit wide cache During read hits all four chip selects are enabled as the 80386 will ignore any data it does not require All four chip selects are enabled during a cache read miss cycle so as to update the entire subblock During write hit cycles these signals reflect the state of the 803865 byte enable signals BE3 BE0 137 Cache Transmit Receive CT R This signal can be used to control optional data transceivers between the cache and the 80386 data bus When high the transceiver should be driving the 80386 local bus when low the transceiver should be driving the cache SRAM data inputs 934 A38202 Local Bus Sig
258. the following Eighteen command active times in CLKINS Twenty two command active times in CLKINS Twenty eight command active times in CLKINS Thirty four command times in CLKINS I lI il 5 4 The combination Bits 5 and 4 select the following Eight RECOVERY times in CLKINS Ten RECOVERY times in CLKINS Fourteen RECOVERY times in CLKINS Sixteen RECOVERY times in CLKINS l H H l H Reserved Should always be programmed to 77 Reserved Should always be programmed to 1 I I Figure 8 11 INDEX08h I O Access Configuration INDEXOCh Identification register INDEXOCh is a READ ONLY register which at system power up defaults to a value of 02h It can be used if incorporated into BIOS routines to identify the revision of the installed HT132 Controller Bit Usage 7654 3210 0 7 0000 0010 Indicates the revision identification for BIOS programmers Figure 8 12 Identification Register 110 Configuration Registers of the GCK131 Chip Set INDEX0Dh IINDEXODh is a READ WRITE register which at system power up defaults to a value of The register is available for programming as the means to adjust the 16 bit timing features of the Revision C chip Bit State Usage 0 0 8 bit timing for Backplane accesses 1 Enables p
259. ting this bit A software reset does not reset the Drive Control Register or the Data Rate Register Data Rate Register and Clock Logic This is a two bit register that controls the data rate that the controller uses See Register Description This register feeds logic that selects the data rates by programming a prescaler that divides the crystal or clock input by either 3 5 or 6 This causes either 4MHz 4 8MHz and 8MHz to be input as the master clock for the controller core If the Drive Type pin is high and a 300 kb s data is chosen 4 8MHz is used to generate 300 kb s but when the DRVTYP pin is low and 300 kb s is selected 4MHz is used and the actual data rate is 250 kb s See Table 13 5 Low Power Mode Logic This logic is an enhancement over the standard XT AT PS 2 design In the Low Power Mode the crystal oscillator controller and all linear circuitry are turned off When the oscillator is turned off the controller will typically draw about 1004A The internal circuitry is disabled while the oscillator is off because the internal circuitry is driven from this clock The oscillator will turn back on automatically after it detects a read or a write to the Main Status or Data Registers It may take a few milli seconds for the oscillator to stabilize and the aP will be prevented from trying to access the Data Register during this time through the normal Main Status Register will be inactive There are two ways to go into the low power mode O
260. tly Formatted diskette can be used like the one of DOS Format But in this format R W region will be reserved on diskette it occupies ONE start TWO middle One last of Track each side So EIGHT will be appeared in FAT area 221 Diagnostic 3 4 991 5 6 It tests R W function of Drive not Media If R W error detected that sector is marked as BAD for not to test in next time This avoid the propagation of media error to drive error Performs seek test Checks the rotation speed of Spindle Motor at 10 times Estimated speed will be displayed in msec unit with maximum and minimum value Returns back to MAIN MENU 4 5 R W Test ET Performs HDD controller internal diagnostics Low level format of HDD At standard You can give factory BAD track map and interleave mode Performs R W test with original data saved On AGING ON mode whole track will be tested but on AGING OFF mode not whole Performs seek test Returns back to MAIN MENU A46 RYS Menu 1 connection dectection Before test loopback connector is to be installed in PIO port Refer to HELP for Loopback It performs internal data loop back test external control signal and Interrupt generation and Diagnostic 47 Menu 1 Like PIO test loopback should be installed properly 2 Select and loopback mode
261. to the revision number of the GCK131 Chip Set features This document is issued concurrently with the release of chips identified 01 in iNpEx13h Revised versions of the GCK131 Chip Set will be identified in INDEX13h in the sequence 02 03 For more information contact your G2 Incorporated representative Bit State Description 7 to 0 olh Revision ID Figure 8 18 INDEX13h INDEX40h Clock dividers for low speed non TURBO mode Default value 10h INDEX40h is available to program the desired clock rates for various functions of the GCK131 Chip Set when operating in non TURBO mode The resultant clock rate is a division of the incoming signal at the SYSCLK input Bits 0 and 1 control the frequency of BUSCLOCK to the backplane Bits 2 and 3 are used to select the desired REFRESH speed Similarly Bits 4 and 5 program the DMA speed while in non TURBO mode Bit State Description 1 0 Bit 1 Bit 0 The combination of Bits 1 and 0 select the following Back plane BUsCLOCK clock divider for sLow speed 0 0 Divide incoming syscLk by one 0 1 Divide incoming syscLk by two 1 0 Divide incoming syscLk by four 1 1 Divide incoming syscLK by eight 3 2 Bit 3 Bit 2 The combination of Bits 3 and 2 select the following REFRESH Clock divider for SLOW speed 0 Divide incoming syscLk by one 1 Divide incoming syscLk by two 0 Divide incoming syscLk by four 1 Divide incoming syscLk by eight Figure 8 19
262. ts are tapped and multiplexed onto the write data output The taps are selected by a standard precompensation algorithm This precompensation value can be selected from the PUMP PREN pin When this pin is low 125ns precomp is used for all data rates except 1 Mb s which uses 83ns When PREN is tied high the precompensation value scales with data rae at 250 kb s its 250ns at 300 kb s its 208ns at 500 kb s its 125ns and at 1 0 Mb s its 83ns These values are shown in Table 13 5 134 6 PC AT and PC XT Logic Blocks This section describes the major functional blocks of the PC logic that have been integrated on the controller Refer to Figure 13 2 the block diagram DMA Enable Logic This is gating logic that disables the DMA lines and the Interrupt output under the control of the DMA Enable bit in the Drive control register When the DMA Enable bit is 0 then the INT and DRQ are held Tri State and DAK is disabled Drive Output Buffers Input Receivers The drive interface output pins can drive 1500 10 termination registors This enables connection to a standard floppy drive A drive interface inputs are TTL compatible schmitt trigger inputs with typically 250mV of hysteresis The only functional differences between the 52 pin PLCC and the 48 pin DIP version are that the MTR2 and 3 and DR2 and 3 pins have been removed in order to accommodate the 48 pin package Bus Interface Address Decode The address decode circuit allows software access to the
263. ts at the end of months and leap years Writing the correspondig index address to I O port 70H allow reading and writing of the 64 locations in the The RTC address register latches the address and points to the specified byte in the RTC Values can be written to or real from all 64 bytes except for the following which are read only Status registers C and D e High order bit bit 7 of status register A e High order bit bit 7 of the seconds byte 149 1287 Real time Clock 50 Bytes Configuration Year Registers Register A Register B Register C Register D Figure 10 1 RTC Memory Map Perform the following two steps when writing data into the RTC RAM 1 Write the RAM address data 00H through 3HF into I O port address 70H 2 Write the data byte into I O port 71H 150 Binary or BCD Inputs 1287 Real time Clock RTC Perform the following two steps when reading data from the RTC RAM 1 Write the RAM address data 00H through 3FH into I O port address 70H 2 Read the data byte from I O port 71H Note I O port address 70H is also an output port for the NMI mask Data bus bit 7 connects to the NMI mask bit and bits 0 through 5 connect to the RTC RAM address lines During normal operation the performs an update cycle once every second Divider bits DV2 0 and the SET bit in register B determine the performance of an
264. ts with the Keyboard Controller clock input The signal on pin CLK281 is divided by four See TNDEX48h on Page 74 and the setting of Bit 2 that changes the frequency of CK8042 Clock Driver Phase 2 180 out of phase with CK8042 Clock for EEPROM NVRAM Clock 28 In Frequency 28 6363MHz At twice the Backplane OSC frequency the oscillator is used to drive the internal timers and the Keyboard Controller oscillator Configuration Registers Address Strobe On the triling edge of this signal data is latched into the HT131 HT132 and HT133 index registers Configuration Registers Data Read When active and selected by the INDEX value within an appropriate range and of the HT131 HT132 HT133 Controllers will output the indexed value onto the data bus Configuration Registers Data Write When active and selected by the INDEX value within an appropriate range one of the HT131 HT132 HT133 Controllers will latch in the data to the indexed register on the trailing edge of this signal CPU Hold Request Connects with the 80386 Microprocessor HOLD pin Chip Select for 80287 80387 When active CS287 indicates that the processor is accessing the coprocessor I O in the range FOh to FFh GC131 Peripheral Controller Pin Pin Symbol Number ICS8042 152 CSEEP 150 ICSVREG 111 DACKO to 72 78 DACK3 DACKS to DACK7 DIEEP 149 DOEEP 135 DRQO to 65 71 DRQ3 DRQ5 to DRQ7 ENADDSTB 147 ENP92 16 FAST R
265. urs 04 12 hour mode 01 12 AM 24 hour mode 00 23 Hours alarm 05 12 hour mode 01 12 AM 24 hour mode 00 23 Day of week 06 01 07 Date of month 07 01 31 Month 08 01 12 Year 09 00 99 Note The RTC does not affect the 50 bytes of RAM from index address 0EH to 3FH These bytes are accessible during the update cycle 104 STATUS REGISTERS The four control and status bytes status registers A D control the operation and monitor the status of the RTC These registers located at index addresses 0A 0DH are accessible by the CPU at all times refer to Tables 10 3 through 10 6 Note A setup program must initialize status registers A through D when setting the time and date 153 1287 Real time Clock RTC 104 1 Status Register A OAH Table 10 3 Status Register Bit Function 7 Update in progress UIP bit 1 The time update cycle in progress 0 The current date and time accessed 6 4 Divider selection DV2 0 bits These bits control the divider prescaler on the They specify the time base frequency in KHz used The system initializes to 010 specifying a time base of 32 768KHz 3 0 Rate selection RS3 0 bits These bits select the divider output frequency The system initializes to 0110 which selects a 1024Hz divider frequency and an interrupt rate of 976 562 10 4 4 Status Register D 0DH Table 10 4 Status Register B OBH Bit Function 7 S
266. us they must only use DMA channels that have been programmed to operate in the cascade mode DACK O DACK 7 5 3 0 DMA Request Acknowledge lines are driven by the PRA to acknowledge requests 7 5 3 0 repliers use DMA acknowledge signals for address selection during DMA cycles when AEN is asserted TC O TC Terminal Count is asserted by the PRA when any one of its DMA channels has reached its terminal count signalling the end of the pre programmed DMA transfer 44 7 Power Signal Group The ISA bus provides DC power at 5 volts 5 volts 12 volts 12 volts and 0 volts Ground 5 VOLIS Three pins supply current for 16 bit agents Two 2 pins supply current for 8 bit agents 5 VOLIS One pin supplies current 12 VOLIS One pin supplies currents 31 ISA Bus Interface 12 VOLTS One pin supplies current 0 VOLTS GROUND Four pins provide a return path for the current supplied by the other power pins for 16 bit agents Three pins provide this return path for 8 bit agents 45 KEY POINTS TIMING CHART 4 5 1 Interleaved Dram Timing 8 MB DRAM RAS O BANK RAS 1 BANK i pu CS Ga Cm Accumulate At x marker Delay Markers X to Trig to Trig to 0 500 ns Time 200 ns 600 400 ns RAS DELAY 1 CLKINS CAS DELAY 2 CLKINS CAS ACTIVE 2 CLKINS RAS PRECHARGE 4 CLKINS RECOVERY TIME O CLKINS 32 4 5 2
267. ut HLDA O HLDA is the bus acknowledge signal This output indicates the 386 has relinquished control of its local bus in response to HOLD being asserted and is in the bus hold acknowledge state In the bus hold acknowledge state HOLD is the only signal bring driven by the 386 The other output or bidirectional signals are in a high impedance state allowing the requesting bus master to control them 16 Central Processing Core INTR D INTR is the maskable interrupt request signal This input indicates a request for interrupt service which can be masked by the 386 flag register IF but When the 386 responds to the INTR input it performs two interrupt acknowledge bus cycles and at the end of the second latches an 8 bit interrupt vector on D7 0 to identify the source of the interrupt The CPU samples the INTR line at the beginning of each processing cycle INTR must be active at least two processing cycles before the current instruction ends or it will be serviced during the next cycle INTR is level sensitive and is asynchronous to the CLK2 signal NMI D NMI is nonmaskable interrupt request signal This input indicates a request for interrupt service that cannot be masked by software NMI has priority over all other interrupts NMI is rising edge sensitive and is asynchronous to the CLK2 signal PEREQ PEREQ is the coprocessor request signal This signal indicates a coprocessor request for a data operand to be transfe
268. utput goes low when 250 300 kb data rate is chosen in the data rate register and high when 500 kb s is chosen 2 When using a single speed spindle motor floppy drive DRVTYP pin high this pin indicates when to reduce the write current to the drive This output is high for high density media when 500 kb s is chosen This is an active low motor enable line for drive 3 191 DP8473 Floppy Disk Controller Typical Application ADDRESS DECODE ADDRESS BU 1 CHIP 74 15521 1000 n E lt A 2 DATA BUS p ortionay Vc OSCI INDEX DIR STEP OSC2 CLK HDSEL WGATE WDATA DSK CHG DRO 3 MTRO 3 WR WRT PRT CS PUMPIPREN FILTER D0 D7 DAK TC DRQ FGND500 GNDB CD I kEGND250 GNDA FILTERS FOR ALL DATA RATES SEE FIGURE IV PLL LOOP FILTERSV INDEX DIRECTION STEP HEAD SELECT WRITE ENABLE WRITE DATA DISK CHANGE DRIVE SEL 0 3 MOTOR 0 3 WRITE PROTECT REDUCED CURRENT TRACK 0 READ DATA CURRENT SET RESISTOR FLOPPY DISK DRIVE Figure 13 3 DP8473 Typical Application 192 DP8473 Floppy Disk Controller 134 FUNCTIONAL DESCRIPTIONS This section describes the basic architectural features of the DP8473 and many of the enhancements provided Refer to Figure 13 2 134 1 765A Compatible Micro Engine The core of the DP8473 is the
269. ween the processor and the backplane One signal per byte BBEN4 enables the buffer between the upper and lower bytes on the 16 bit backplane bus GC132 CPU Memory Controller Pin Symbol Pin Number Pin Type Description BBDIRO BBDIR1 BS32 BUSY386 BUSY387 CASA to ICASD CLK646 CLKIN CLKM 122 123 19 54 48 134 to 131 118 37 46 61 Bus Bridge Direction Indicators BBDIRO turns the direction of the buffer between ATDO0 7 and ATD8 15 When HIGH the buffer will drive from lower 8 bits to upper 8 bits The BBDIR1 signal indicates the data flow from processor to from backplane When HIGH the data will flow from the processor to the backplane when LOW the flow is in the opposite direction Bus Size 32 Bits When LOW this signal indicates that the current cycle is intended for local 32 bit access LBS16 is inactive and BBENs are in the OFF condition See also FETEN Busy 386 Connects to the BUSY line of the 80386 Microprocessor Busy 387 is connected to the BUSY line of the 80387 Coprocessor Column Address Timing Strobe for the 4 bytes These signals must be steered to the correct bank using BANKSEL or external logic for Banks 4 and 5 Clock the LS646 megafunction in the HT133 Interface The rising edge latches the data presented on the lower 8 bits of the backplane This is used on an 8 to 16 bit read conversion cycle Clock This cloc
270. x value Type R eboot other keys to continue This could be any hardware related problem Recheck all cables connections jumpers and boards If the problem persists contact your service representative Unexpected SW interrupt at addres hex value Type R eboot other keys to continue There is an error in the software utility Try turning the system off and then on again If the problem persists contact your software manufacturer representative 246 Messages B4 SYSTEM BOARD ERRORS If the POST finds an error and cannot display a message on the video display the POST issues a series of beeps indicating the error and places a value in I O port 80H For example a failure of bit 3 in the first 64K of RAM is indicated by a 2 1 4 beep code a burst of two beeps a single beep and a burst of four beeps In addition the POST writes a value to port 80H to enable debugging tools to identify the area of failure Table B 1 and B 2 list the beep codes and I O the values that the POST writes to I O port 80H when it encounters error conditions Table B 1 lists fatal errors errors that halt the system Table B 2 lists the non fatal errors errors that are not serious enough to half the system Both tables list other conditions that have no beep codes One beep code is not listed in Table B 1 or B 2 a long beep followed by one or more short beeps indicates a video adapter filure No beep code is sounded if a te
271. y through general setup bits control such functions as PARITY COPROCESSOR selection ROM SHADOWIN G and the REMAPPING features The GC133 Bus Bridge Interface has configuration bits that select the DRAM configuration control interleaving and REMAP and also identify the chip number from a READ ONLY register within the chip The revision number is important for system developers it provides a method of identifying the features available in the chip set The Configuration Registers are Partitioned The configuration registers of the chip set are partitioned into regions each is non overlapping and unique 197 Configuration Registers of the GCK131 Chip Set e I O address 24h is write only register within which is replaced a pointer to the required INDEX address 28h is read write port within which the data for the INDEX is placed How to Read or Write to the Registers It is a two step process to read from or write to the registers 1 Write the INDEX of the desired register to address 24h 2 Read Write the data from to address 28h Each chip has its own INDEX space or region as follows e The GC132 INDEX space resides from 00h to OFh The GC133 INDEX space resides from 10h to 1Fh The GC131 INDEX space resides from 40h to 4Fh Signals Associated with the Configuration Registers CONFIGAS When an I O WRITE is made to register 24h CONFIGAS goes active high and on the falling

SERVICE MANUAL - Matthieu Benoit

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