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X6-400M User's Manual

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1. eesessssss 108 Figure 32 XO AVON Block Digan ain ette tie died Ria 109 Figure 33 X6 400M A D Channel Front End cccsssssscssstcssccseccsesceseccsecccscessscssnssencesscsessenees 111 Figure 1 X6 400M DAC Output Circuitry iet eese ss 114 Figure 2 DAC5682Z Features courtesy Texas Instruments nennen 116 Figure 3 Sample Clock Generation and Distribution Block Diagram eee 119 Figure 4 SNAP Example Sample Clock Controls iie iae to ii 121 Figure 5 Clock Path Using External Reference Int ii trier er ortas 124 Figure 6 Clock Path Using External Clock Hip ut ue eade ias 125 Figure 7 Analog Triggering Dn oio erue Rec dn rea coven Miva RE d SERE E deque alias Eae du inde 127 Figure 8 X6 400M SNAP Example Triggering Controls sssssseseeeenenerenenn 129 Figure 9 X6 400M FrameWork Logic Data Flow eerte eterne eren tn eene nnn hende 131 Figure 10 Typical Performance Evaluation Setup nennen 136 Figure 11 Frequency Response for 5 MHz to 500 MHz span DC Coupled Output Fs 500 MSPS m H 147 Figure 12 Frequency Response for 5 MHz to 500 MHz span DC Coupled Output Fs 500 MSPS Dm 147 Figure 13 DC Coupled Output Signal Quality vs Fout Fs 500 MSPS 0 ce eeeeeeeseeeeneeeeeeeees 147 Figure 14 DC Coupled Output Signal Quality for Fout 270 1 MHz Fs 1GSPS
2. The module implements a PCI bus interface using PMC connectors JN1 and JN2 When the PCI interface is used the X6 module is compatible with PMC module sites The PCI interface is a 32 bit 66MHz interface capable of up to 264 MB s transfer rates and conforms to PCI Local Bus Specification X6 400M User s Manual 36 About the X6 XMC Modules Peripheral Features 3 0 Voltage standard is 3 3V with 5V IO tolerance The PCI Express interface is not available when PCI interface is being used Data transfers between the X6 and host employ the Velocia packet system This protocol automates the DMA transfers using a credit based flow control for the packet transfers with the host The ssytem is extensible through the use of virtual channels defined in the logic design A secondary command channel provides independent interface for control and status outside of the data channel that is extensible to custom applications XMC J16 or JN4 DIO Digital IO is provided that has direct connection to the FPGA The card can be configured so that these digital IO are available on either J16 or JN4 factory installed option J16 option 19 digital IO pairs 38 signals LVCMOS 2 5V or LVDS JN4 option 32 digital IO pairs 64 signals LVCMOS 2 5V or LVDS XMC P16 Communications Ports Eight high speed serial links GTX operating at up to 5 Gbps each are available The Framework Logic implements either Aurora ports for sys
3. 148 Figure 15 DC Coupled Output Signal Quality for Fout 100 1MHz Fs IGSPS 148 Figure 16 DC Coupled Output Signal Quality for Fout 160 1MHz Fs IGSPS 148 Figure 17 Frequency Response for 5 MHz to 500 MHz span AC Coupled Output Fs 500 MSPS NO SING CORRECTION 149 Figure 18 Frequency Response for 5 MHz to 500 MHz span AC Coupled Output Fs 500 MSPS NO SING GORRECTIO NN isiyo frets ae nl nta de ale epa pec E 149 Figure 19 AC Coupled Output Signal Quality vs Fout Fs 500 MSPS eese 149 Figure 20 AC Coupled Output Signal Quality for Fout 5 1MHz Fs IGSPS sssse 150 Figure 21 AC Coupled Output Signal Quality for Fout 70 1 MHz Fs IGSPS 150 Figure 22 AC Coupled Output Signal Quality for Fout 100 1 MHz Fs IGSPS 150 Figure 23 AC Coupled Output Signal Quality for Fout 160 1MHz Fs IGSPS 150 Figure 24 AC coupled Intermodulation Distortion Dual tones at Fout 69 5 MHz and 70 1 MHz Edac 200MBHZ 3 eee da ota ice eire a MET Le S 151 Figure 25 Front Panel SMA Connector Functions JS JlO ooooonncninccinocnnocononaconccononcnnncnnnnconcncnnnnnss 152 Figure 26 P15 XMC Connector Orrentatiotk s oeste eei eer dent a rese RUIN Ur Pere 153 Figure 27 P16 XMC Connector Orientation ai asocuoni eis ssaavsduvatieans rae PARSE eMe tien Gen NERIS V
4. ANSI VITA 42 3 XMC module with PCI Express Interface VITA www vita org Table 9 PCI PCI Express Standards Compliance Chapter 13 FPGA Integration with the PCI PCIe Host Data Path A data plane and control plane are implemented in the X6 family that use the PCI Express interface to communicate with the host The data plane uses the Velocia packet DMA channel and the control plane uses a Wishbone SOC bus The Velocia DMA channel automates the data transfers using a packet system achieving data rates up to 2000 MB s sustained transfer rates requires x8 Gen2 PCIe core This high speed path is complemented by the Wishbone SOC bus for system command control and status The Wishbone SOC provides a flexible system bus interconnecting the logic components Application Logic Interface Max Data Rate Typical Use Velocia Packet Interface 2000 MB s sustained to host memory x8 Gen2 PCle core Velocia packet system interface main path for data communications Wishbone SOC Bus 20 MB s sustained System On Chip bus for command control and status This bus is used to connect logic components in the FPGA Table 10 Interfaces from PCI Express to Application Logic Additional information is available in the X6 Framework Logic User Guide for each X6 module Chapter 14 Data Buffering and Memory Use There are four banks of memory attached to the application FPGA useful fo
5. Table 10 PLL Specifications Setting the Sample Rate in the SNAP Example The example software for the X6 400M illustrates the use of the sample clock controls and features The clock is selected internal PLL or external input A frequency should be specified even when an external clock is used because the software uses this to estimate the data rate and size buffers appropriately The external clock must be input on front panel connector J6 The PLL reference is also selected to be internal 10 to 1417 MHz reference or external For external reference the frequency must be exactly specified so that the PLL is programmed properly External reference connector is J6 on the front panel X6 400M User s Manual 120 X6 400M XMC Module X6 400M PCIe Module Snap Example C Ext Int 15 x Front Panel Frequency joa Frequency 400 0 MHz Alerts Velo Pkt Size Timestamp 10000 Software Temperature Active Channels Trigger vi Ch 0 Source Ext Trigger Srey Frame Mode Type Ch1 Software Size Unframed Level C Extemal PIG ox400 Iv Auto Retriager e Framed Edge Test Counter Decimation Enable Enable Saw Paced a Actual PLL Frequency 4e 08 Analog 1 0 started Stream Mode started Analog 140 Stopped Stream Mode S
6. Image JP1 Purpose Notes 0 none Application Logic 1 Short Backup Image Table 32 Logic Image Selection Jumper JP1 Chapter 39 Updating the Logic Configuration FLASH EEPROM Virtex 6 configuration data is stored in an onboard FLASH EEPROM which may be updated using software provided by Innovative Logic images may come as updates from Innovative or be generated by a user developing custom functionality The applet provided by Innovative VsProm exe programs the FLASH using a bit or exo image file generated by the Xilinx toolset X6 400M User s Manual 65 About the X6 XMC Modules ES Logic Programmer Board Driver Logic Image EMnnovativeNXB RXSHardwaresImagesNsRievAN B r amp routed bit J Update Logic Cpld Version 1 tog Leaving GOLDEN IMAGE Mode Driver opened ok Cpld Type 0x0 Cpld Rev Oxl Mode 0 M26EW Type ROM Detected Prom Query 0x510051 0x00510051 Prom Dev d 0x227e2239 Protected Bit 0x0 Unlock Bypass Capable Bit Oxl Image file parsed ok Firmware 0x102 Hardware 0x0 Id 0x0 Idle Figure 30 X6 Configuration FLASH Programmer The EEPROM application is straightforward to use a Target board is selected then a BIT file is selected for reprogramming The Target number tells the software which XMC module to program If you have multiple XMC modules in the system each has a unique Target number assigned by the software If you don t know which card is which ta
7. This is the event handler for the Packer In this case we just do a simple assignment to save the data for later use You can also add the buffer to a data structure or Send it at this time if the application is designed for that kind of I O ApplicationIo HandlePackedDataAvailable Packer Callback void Applicationlo HandlePackedDataAvailable Innovative VitaPacketPackerDataAvailable amp event WaveformPacket event Data X6 400M User s Manual 91 Developing Host Applications Chapter 52 Developing Host Applications Developing an application will more than likely involve using an integrated development environment IDE also known as an integrated design environment or an integrated debugging environment This is a type of computer software that assists computer programmers in developing software The following sections will aid in the initial set up of these applications in describing what needs to be set in Project Options or Project Properties Borland Turbo C BCB10 Borland Turbo C Project Settings When creating a new application with File New VCL Forms Application C Builder Change the Project Options for the Compiler Project Options Compiler bcc32 C Compatibility Check zero length empty base class Ve Check zero length empty class member functions Vx In our example Host Applications if not checked an access violation will occur when attempting to enter any
8. Figure 2 DAC5682Z Features courtesy Texas Instruments The operating modes are summarized in the following table The DAC5682Z datasheet provides details on the DAC modes filter characteristics and clock modes Configuring Special Modes All of the configuration modes are programmed by accessing the DAC over its SPI port to set the configuration registers During experimentation these registers are accessed from the WAVE example program using peeks and pokes to the DAC registers The SPI ports are accessed via memory mapped registers that the host computer can access Writing to these registers triggers a DAC SPI command X6 400M User s Manual 116 X6 400M XMC Module DAC Specific Registers WB WB Register Simulation Define R W Description Modules Base Address x 890 MR AFE DAC SPI CTRL R W 400M x 891 MR_AFE DAC SPI STAT R W 400M Table 4 X6 AFE DAC SPI Memory Map AFE DAC SPI Control MR AFE DAC SPI CTRL x 890 This is the DAC SPI interface register DAC SPI port is accessed via this interface Bits Field R W Default Description Modules 7 0 spi_wdata R W x 00 SPI write data 400M 15 8 20 16 spi_addr R W 0 DAC register address 400M 27 21 28 spi rd wrn R W 0 1 SPI read 0 SPI write 400M 31 29 Table 5 X6 AFE DAC SPI Control Register AFE DAC SPI Status MR AFE DAC SPI STAT x 891 This is the DAC SPI interfac
9. Table 2 AC Coupled DAC Conversion Codi iet A ba asi tdv ts 115 Table 3 SMA to BNC Coax Cable Part Number aee ce concolor cdas 115 Table 4 X6 AFE DAC SPI Memory Map iecofi cores sott etatis e nc go eSostbeets au tea Poeta bee Pr bo EE Oo inicias 117 Table 5 X6 AFE DAC SPI Control RE A pe a cance Mamet RAN TEE etra PED 117 Table 6 X6 AFE DAC SPI Status Register csscssscssscceeccceecesscsssccsssccseccssscesaccsescensaseessssacsones 117 Table 7 DAC 0 amp 1 SPI Interface 0x806 0x808 r w essent 117 Table 8 Script Commands sciopero esie ashe oce Re RON Qui vae bea ie iue eee dou FR e RYE e een 118 Table 9 Input Clock Reference Electrical Specifications 120 Table T0 PEL Specifications xi uni n t cert he OUS c Ree OPI aaa SUE el dee uu ie eue ed 120 Table 11 Sample Rate Generation Parameters vincia rim ia e t kg eR E ee ER en 122 Table 12 Steps to Configure the VCXO and PLL a ense eet teta eee a Rd en 122 Table 13 Effect of Sample Clock Jitter on Digitizing Accuracy Courtesy Analog Devices Inc 123 Table 14 External PLL Reference Additive Jitter and Delay sse 123 Table 15 External PLE Reference Requirements siiis egeo oetbe a Lo Ebert one eri Pate UR ei Lao 124 Table 16 External Clock Input Requirements ee tette te di iii 126 Table 17 PLL SPI interface 0x80 TL Y 39 u is vue aedi 126 Table 18 VCXO control and I2C register 0x801 r w ess
10. X6 400M User s Manual 111 X6 400M XMC Module 0 0 0x0000 0 6 0xC000 1 0 0x8000 Table 43 DC Coupled A D Conversion Coding Driving the A D Inputs The X6 400M has single ended inputs that are 50 ohm terminated The 50 ohm termination is used to match the input cable and connector characteristic impedance The source signal must be able to drive this input impedance to achieve the best signal quality over the input voltage range The signal source must be able to drive 30mA for a full scale input DC current limit is 30 mA Overrange Detection The high speed A D detects when an analog overrange occurs and generates an overrange flag The logic receives this overrange detection and can trigger a system alert to notify the application when this error condition has occurred The alert message shows when the overrange occurred in system time and which channels overranged Custom logic has access to the overrange bits in the A D interface component Each data sample indicates when an overrange occurs as part of its status byte appended to the data This allows implementation of automatic gain controls for auto ranging external front end signal conditioning D A Converters The X6 400M has two channels of 16 bit DAC capable of 500 MSPS update rate or one channel at 1 GSPS The DAC outputs are either DC coupled or AC coupled 50 ohm terminated with front panel SMA connectors Feature
11. Module Clock Reference ref Settings ReferenceClockSource Module Clock ReferenceFrequency Settings ReferenceRate 1e6 Route clock IX6ClockIo IIClockSource src IX6ClockIo csExternal IX6ClockIo csInternal Module Clock Source src Settings SampleClockSource Module Clock Frequency Settings SampleRate 1e6 Readback Frequency double freq actual Module Clock FrequencyActual std stringstream msg msg lt lt Actual PLL Frequency lt lt freq actual Log msg str X6 400M User s Manual 79 Writing Custom Applications The size of the data packets sent from the module to the Host during streaming is programmable This is helpful during framed acquisition since the packet size can be tailored to match a multiple of the frame size providing application notification on each acquired frame In other applications such as when an FFT is embedded within the FPGA the packet size can be programmed to match the processing block size from the algorithm within the FPGA Always preconfigure Stream Preconfigure In order to support modes where the clock is not disturbed from run to run some configuration notably clock configuration is performed in a preconfiguration step Here we call this step automatically to program the clock for the run Velocia Packet Size Module SetInputPacketDataSize Settings PacketSize The I O data can be replaced with
12. Prerequisites for Installation In order to properly use the baseboard example programs and to develop software using the baseboard some packages need to be installed before the actual baseboard package The Redistribution Package Group MalibuRed This set of packages contain the libraries and drivers needed to run a program using Malibu This group is called MalibuRed because it contains the packages needed to allow running Malibu based programs on a target non development machine Red is short for redistributable WinDriver 9 2 1 1586 rpm Installs WinDriver 9 2 release MalibuLinux Red ver rel 1586 rpm Installs Baseboard Driver Kernel Plugin intel ipp rti 5 3p x32 rpm Installs Intel IPP library redistributable files X6 400M User s Manual 25 Installation on Linux The installation CD or the web site contains a file called LinuxNotes pdf giving instructions on how to load these packages and how to install the drivers onto your Linux machine This file is also loaded onto the target machine by the the Malibu LinuxRed RPM These procedures need to be completed for every target machine Malibu To develop software for a baseboard the Malibu packages also must be installed Malibu LinuxPeriphLib ver rel 1586 rpm Installs Malibu Source Libraries and Examples Other Software Our examples use the DialogBlocks designer software and wxWidgets GUI library package for user interface code
13. TXP0 7 MGT transmit positive TXNO 7 MGT transmit negative RXP0 7 MGT receive positive RXNO 7 MGT receive negative DGND Ground FMC_CLKP N Sample clock input pair P N LVDS 100 ohm differential termination FMC_REFCLKP N GTX reference clock input pair LVDS 100 ohm differential termination H TRIGO 1 Trigger inputs H PPS PPS pulse per second input for trigger and timing controls F ADJ Reference voltage for DIO Px Nx inputs PMC JN1 Connector JN1 implements part of the PMC PCI interface as well as power inputs 1mm double row IEEE 1386 compatible vertical connector Connector Part Number Molex P N 71436 2864 X6 400M User s Manual 156 X6 400M XMC Module Figure 28 PMC JN1 Connector Schematic See PCI specification for detailed pin descriptions Table 36 X6 JN1 Connector Pinout X6 400M User s Manual Signal Direction Signal Direction DGND P INTA interrupt to host O 5V P DGND P 11 12 CLK I 13 14 L DGND P 15 16 GNT P 157 X6 400M XMC Module Signal Direction Pin Pin Signal Direction REQ O 17 18 5V 19 20 AD31 yo AD28 yo 21 22 AD27 yo AD25 yo 23 24 DGND DGND 25 26 CBE3 yo AD22 yo 27 28 AD21 yo AD19 yo 29 30 5
14. is to incorporate the Applicationlo class in its entirety directly into your custom app Applicationlo contains only portable code without any framework dependencies whatsoever It contains all of the essential hardware initialization code event handlers etc to support efficient communications with the board You ll likely need all of the features of Applicationlo in your application so why reinvent the wheel Many users are initially unclear on how Applicationlo can remain agnostic to the framework This is accomplished by factoring all functions used to relay information between framework specific code and the Applicationlo into a small separate class called UserInterface within the supplied examples The concrete UserInterface object derives from the pure abstract IUserInterface base class IUserInterface simply specifies the functions that must be supplied by a user application to provide a bridge to the stock features of the Applicationlo object X6 400M User s Manual 73 Writing Custom Applications Your application must create a UserInterface class and pass it to the constructor of the Applicationlo object but your implementation of the IUserInterface methods may degenerate to trivial no ops if desired The Main form of the application creates an Applicationlo to perform the work of the example The UI can call the methods of the Applicationlo to perform the work when for example a button is pressed or a control changed Somet
15. 15 pF parallel cap at A D device input DBinview dmclanetprajects xfxb 400m hardwaretrevattest datalplotOa bd Z Binview Numnctane projects x6 x6 400mMardwore reva est data plot0 bdd amp w n ure CO OF Time Fiewency rex Suma sever Magnitude vs Frequency 20K 40K 60K 80K 100K KHz 120K 140K 160K 180K 200K Mak S N dB SNIE Es Leap 1024 SINAD dE ENUE bis SFOR dB THD Pies 552 D 833 1002598 31 408 Sample mo y Anales Samples 944768 DC Coupled A D wideband signal quality Fin 5 1 MHz Fs 400 MHz onboard PLL Channel 0 15pF parallel cap at A D device inputs a warm MBR CO Y Q Tine Fisquenes Test Saves Server Magnitude vs Frequency 60K 80K 100K KHz 120K 140K 160K 180K 200K SIN GB SINAD 8 ENDE bis 103 SFOR eB THD 12748 730 0 002467 92 248 1024 x BinView Vdmclane projects x lt 6 x6 400m hardware reva test data plot0a bdd a Marh nre CO Y 0 Tine Frequency Text Summary Server 7036 2487 Magnitude vs Frequency KHz Max S N dB Leap Anayee Ch 7 Samples 948500 DC Coupled A D wideband signal quality Fin 70 1 MHz Fs 400 MHz onboard PLL Channel 0 15 pF parallel cap at A D device inputs SNB SINAD 8 FNOB is 542 639 103 SFOR BY Sample 878 1024 Leap mwr Frequency donain data dsplay Andyze Samples 948500 DC Coupled A D narrowband signal quality Fin 70 1 MHz Fs 400 M
16. 20 Windows Installation Registration Information User Name Fist Email Address Telephone Country Code Area Code Number Extension Fax Area Code Number Company Name Address City State Country Postal Code Product Board M6713 A 2 Help E Register Now Register Later Bus Master Memory Reservation Applet Reserve Memory for Dsp Combined DSP Board Usage Rsv Region Size MB Configuration Total physical memory MB 2047 Non paged pool size MB 256 Status Ok Update Help Exit Ready Figure 5 BusMaster configuration When you are ready to register click Start All Programs Innovative Board Name Applets Open the New User folder and launch NewUser exe to start the registration application The registration form to the left will be displayed Before beginning DSP and Host software development you must register your installation with Innovative Integration Technical support will not be provided until registration is successfully completed Additionally some development applets will not operate until unlocked with a passcode provided during the registration process It is recommend that you completely fill out this form and return it to Innovative Integration via email or fax Upon receipt Innovative Integration will provide access codes to enable technical support and unrestricted access to applets Figure
17. 3dB DC coupled input 15 pF filter cap at A D device inputs SFDR 69 dB 70 MHz sine input 95 FS Fs 400 MSPS S N 62 7 dB 70 MHz sine input 95 FS Fs 400 MSPS THD 58 dB 70 MHz sine input 95 FS Fs 400 MSPS ENOB 10 1 bits 70 MHz sine input 95 FS Fs 400 MSPS Channel Crosstalk lt 95 dB 101 MHz 2Vp p on opposite channels Noise Floor 97 dB Input Grounded Fs 400 MSPS 64K sample FFT non averaged Gain Error lt 0 2 of FS Calibrated Offset Error lt 500 uV Calibrated Table 29 X6 400M Analog Input Performance Summary DC coupled Inputs AC Coupled Inputs Parameter Typ Units Notes Analog Input Bandwidth 400 MHz 3dB DC coupled input 15 pF filter cap at A D device inputs SFDR 80 2 dB 70 MHz sine input 95 FS Fs 400 MSPS S N 68 4 dB 70 MHz sine input 95 FS Fs 400 MSPS THD 90 7 dB 70 MHz sine input 95 FS Fs 400 MSPS ENOB 11 bits 70 MHz sine input 95 FS Fs 400 MSPS Channel Crosstalk lt 95 dB 101 MHz 2Vp p on opposite channels Noise Floor 106 dB Input Grounded Fs 160 MSPS 32K sample FFT non averaged Gain Error lt 0 2 of FS Calibrated Offset Error lt 500 uV Calibrated Table 30 X6 400M Analog Input Performance Summary AC coupled Inputs X6 400M User s Manual 140 X6 400M XMC Module DC Coupled Analog Input Bandwidth 1 A Norm Fund amp dB Variation dB 1 10 Fin MHz X6 400M DC Coupled Input Bandwidth
18. Figure 5 Clock Path Using External Reference Input To use the external clock input as a reference the CDCE72010 reference must be set to secondary input This can be done using either a Malibu library function in software from a script in the example programs or set by the FPGA in custom logic Using An External Clock for Sample Clock The external clock input on J6 front panel can be used as a sample clock In this mode the sample clock is buffered and distributed with an option for clock division to the DAC devices and FPGA X6 400M User s Manual 124 X6 400M XMC Module J6 Ref CIk Input ADC Ref To FPGA DAC Ref To FPGA DAC CLK To FPGA To DAC To ADCO 1 To ADC2 3 HITI 12C Port 12C Port To MGT PLL Figure 6 Clock Path Using External Clock Input Configure the CDCDE72010 device to use the auxiliary clock input then program the dividers for each output clock These controls are mapped to the CDCDE72010 SPI port mapped to the PCI Express bus in the Framework Logic Custom logic implementations can control the PLL directly from the FPGA as well The Malibu libraries provide software functions for configuration of the CDCDE72010 device This software configures the device for the clock selection and programs the output dividers External Clock Requirements The external clock input has the following requirements This signal is an AC coupled input Larger input amplitudes usually result in bet
19. Typically most users will perform a Full Install by leaving all items in the Components to Install box checked If you do not wish to install a particular item simply uncheck it The Installer will alert you and automatically uncheck any item that requires a development environment that is not detected on your system 4 Click the Install button to begin the installation Note The default Product Filter setting for the installer interface is Current Only as indicated by the combo box located at the top right of the screen If the install that you require does not appear in the Product Selection Box 1 Change the Product Filter to Current plus Legacy Each item of the checklist in the screen shown above has a sub install associated with it and will open a sub install screen if checked For example the first sub install for Quadia Applets Examples Docs and Pismo libraries is shown below The installation will display a progress window similar to the one shown below for each item checked X6 400M User s Manual 19 Windows Installation Quadia Documentation Thank you for choosing Quadia Installing Documentation Figure 3 Progress is shown for each section Tools Registration At the end of the installation process you will be prompted to register If you decide that you would like to register at a later time click Register Later X6 400M User s Manual
20. data logging stimulus response and signal processing jobs are easily solved with Innovative Integration baseboards using the Malibu software There are a wide selection of peripheral devices available in the Matador DSP product family for all types of signals from DC to RF frequency applications video or audio processing Additionally multiple Innovative Integration baseboards can be used for a large channel or mixed requirement systems and data acquisition cards from Innovative can be integrated with Innovative s other DSP or data acquisition baseboards for high performance signal processing Why do I need to use Malibu with my Baseboard One of the biggest issues in using the personal computer for data collection control and communications applications is the relatively poor real time performance associated with the system Despite the high computational power of the PC it cannot reliably respond to real time events at rates much faster than a few hundred hertz The PC is really best at processing data not collecting it In fact most modern operating systems like Windows are simply not focused on real time performance but rather on ease of use and convenience Word processing and spreadsheets are simply not high performance real time tasks The solution to this problem is to provide specialized hardware assistance responsible solely for real time tasks Much the same as a dedicated video subsystem is required for adequate display performance
21. lt Baseboard gt Hardware Images folder on your default drive Version Unknown Opening target Finally click the Write button to program the firmware into the on board FLASH rom Programming typically takes about five minutes After rebooting the PC the new firmware will take effect X6 400M User s Manual 106 Applets for the X6 Family Baseboards TRGE epe ees The Finder is designed to help correlate board target numbers against PCI slot numbers in systems employing multiple boards Target Number Select the Target number of the board you wish to identify using the Target Number combo box Blink Click the Blink button to blink the LED on the board for the specified target It will continue blinking until you click Stop On OFF Use the On and Off buttons to activate or deactivate respectively the LED on the baseboard for the specified target When you exit the application the board s LED will remain in the state programmed by this applet X6 400M User s Manual 107 X6 400M XMC Module Chapter 63 X6 400M XMC Module Introduction The X6 400M is a member of the X6 XMC family that has two channels of 14 bit 400 MSPS A D conversion two channels of 16 bit 500 MSPS D A converters and an FPGA computing core on a PCI Express XMC module The X6 400M has a high performance computing core for signal processing data buffering and system IO is built around a
22. 1386 specification for single width mezzanine cards This specification is common to both PMC and XMC modules and specifies the size mounting mating card requirements for spacing and clearances There are several adapter cards that are used to integrate the XMC modules into other form factor PCI Express systems such as desktop systems There are also adapter cards to electrically adapter the PCI Express XMC modules in older PCI systems that use a bridge device between the two buses PCI is not electrical Host Type Bus Mechanical Adapter Required Example card Form factor XMC 3 module PCI Express 1 0a XMC single None Kontron CP6012 slot width www kontron com Diversified Technology CPB4712 http www diversifiedtechnology co m products cpci cpb4712 html Desktop PC PCI Express 1 0a PCI Express PCle XMC 3 adapter Innovative 80173 Plug in card x8 lane Desktop PC PCI 2 2 PCI Plug in card PCI XMC 3 adapter Innovative 80167 X6 400M User s Manual 62 About the X6 XMC Modules Host Type Bus Mechanical Adapter Required Example card Form factor Compact PCI PCI Express 1 0a 3U CPCI XMC 3 adapter Innovative 80207 Cabled PCI PCI Express 1 0a Cabled PCI Cable PCIe Adapter and Innovative 90181 Express Express to XMC 3 carrier remote IO Embedded PC PCI Express to 10x7x3 inches None Innovative 90200 or 90201 Host local PC core VPX VPX with PCI 3U VPX VPX 3U adapter I
23. 4 ToolSet registration form At the conclusion of the installation process ReserveMem exe will run except for SBC products This will allow you to set the memory size needed for the busmastering to occur properly This applet may be run from the start menu later if you need to change the parameters For optimum performance reserve at least 64 MB of memory for each Innovative board to be used simultaneously within the PC plus 32 MB for other system use For example if using two X5 400M modules reserve 2 64 32 MB 160 MB To reserve this memory the registry must be updated using the ReserveMem applet Simply type the desired size into the Rsv Region Size MB field click Update and the applet will update the registry for you If at any time you change the number of boards in your system then you must invoke this applet found in Start All Programs Innovative lt target board gt Applets Reserve Memory After updating the system exit the applet by clicking the exit button to resume the installation process At the end of the install process the following screen will appear X6 400M User s Manual 21 Windows Installation Installation The installation is complete Shut down your computer and install your board s then reboot your computer The drivers should load automatically and your board will become available Please referto your Hardware Software Manual for instructions on hardware installation priorto po
24. 8 Packet Data 1 9 Packet Data 2 10 Packet Data 3 X6 400M User s Manual 98 Vita Packet Format 11 Trailer Word The requirement of the Vita packet to remain aligned to a 4 word boundary conflicts with the need to dispatch a packet at once when events occur such as the trigger signal going off If the packet remains unsent part of the data will not arrive and even if it will eventually come in part of the packet will have occurred at one time and part at potentially a much later time To allow the packet to be sent in the absence of valid data the concept of Padding was added A field in the trailer can be set to indicate to the destination which bytes in the last 16 bytes are not valid data The application must ignore this data when processing the buffer So in the case a trigger ends in the middle of a 4 word block the packet can be padded to achieve alignment and the padding field in the trailer set to indicate this to the analysis routines The Access Datagram classes all recognize this padding value and reduce the size of the packet accordingly This means the applications must initialize the Padding field before attempting to fill a packet Chapter 59 Packet Header Format The above table shows the arrangement of the seven header words in the header The remainder of this section will describe the fields for each word VITA Header IF word S 8S 2 HX HE le fe 2 1928 e pak a ae pq
25. Application logic 1 Coolrunner II Configuration control Table 29 X6 JTAG Scan Path The JTAG connector JP3 pinout is shown in hardware chapter of this manual X6 400M User s Manual 61 About the X6 XMC Modules Chapter 34 FrameWork Logic Many of the standard X6 XMC features are implemented in the application logic The logic allows the card to be used for data acquisition and playback with supporting software for data analysis logging and controls The logic features include a data plane triggering features and application specific functions In this manual the FrameWork Logic features for each card are described in in general to explain the standard hardware functionality The X6 FrameWork Logic User Guide provides developers with the tools and know how for developing custom logic applications See this manual and the supporting source code for more information The X6 modules are supported by the FrameWork Logic Development tools that allow designs to be developed in HDL or MATLAB Simulink Standard features are provided as components that may be included in custom applications or further modified to meet specific design requirements Chapter 35 Integrating with Host Cards and Systems The X6 XMCs may be directly integrated PCI Express systems that support VITA 42 3 XMC modules The host card must be both mechanically and electrically compatible or an adapter card must be used The XMC modules conform to IEEE
26. Description Analog Outputs 2 Output Range 0 5V to 0 5V single ended DC Coupled 450 to 450 mV single ended AC Coupled Output Coupling DC P N 80270 0 AC P N 80270 4 Output Impedance 50 ohm DAC Devices Texas Instruments DAC5682Z Input Format 2 s complement 16 bit Number of DAC Devices 1 device which has 2 channels simultaneously updated X6 400M User s Manual 112 X6 400M XMC Module Feature Description Sample Rate 10 1000 MSPS Calibration Factory calibrated Gain and offset errors are digitally corrected in logic Non volatile EEPROM coefficient memory Table 44 X6 400M DAC Features Conversion clocking is provided by either a low jitter programmable clock source or an external clock input The clock buffering is designed to minimize jitter and maximum acquired signal quality See the clock discussion for more details DAC Analog Output The DAC outputs are either AC or DC coupled The output circuity is configured to to use either an AC coupled output through a transformer or a DC coupled path using active amplifiers The AC coupled output has lower harmonic distortion and better SFDR than the DC coupled output because of amplifier performance For the AC coupled output path the DAC drives a transformer The AC coupled output is not filtered allowing higher output analog bandwidth No gain adjustment is available in the AC coupled mode The transformer drives the output SMA connec
27. Fs The PLL analog loop filter is set for a phase comparator frequency of 100 kHz Therefore select R P B and A to satisfy these equations Frer R 100 kHz Fyco PB A 100 kHz where R 1 to 16383 P 1 2 2 3 4 5 8 9 16 17 32 33 or 3 A 0 to 63 Note R 100 for on card 10 MHz reference Table 12 Steps to Configure the VCXO and PLL Driver code in the Malibu support libraries implements these calculation steps to program the PLL and VCXO When these library functions are used the software checks to verify that all restrictions for VCXO and PLL programming are met and that the output frequency is as close as possible to the desired result Using An External PLL Reference The PLL can use an external clock input as its reference This allows the sample clocks to be synchronous with the external clock Many applications use this to synchronize multi channel systems to sample simultaneously Distributed applications can input time reference from GPS or other network time sources to synchronize systems The external clock must be low phase noise and stable to use as a PLL reference Phase noise on the reference will directly result in phase noise on the generated clock This means that the phase noise must be very low typically less than 200 fS X6 400M User s Manual 122 X6 400M XMC Module RMS to be clean enough not to influence the acquired signal The following graph shows the effect of jitter on the sample
28. Host Interface Host cards are usually either PCI Express or PCI not both For performance the PCI Express interface should be used The PCI interface is used primarily for compatibility to systems without PCI Express It is normal that some of the connectors will not have mates when the host is PCI Express only and is not harmful The choice of either PCI or PCI Express interface requires that a different logic image be used in each type This logic defines the interface type and must match the desired interface Host Interface Logic Image Notes PCI Express x8 Genl x5 400m bit Max data rate is 8GB s Genl Sustained rates 1GB s PCI x5 400m xl bridge bit Max data rate is 256MB s Sustained rates 1 80MB s PCI Express x8 Gen2 x5 400m x8 gen2 bit Max data rate is 8GB s Gen2 Sustained rates 2GB s Table 8 Logic Images for PCI and PCI Express Hosts Chapter 12 PCI and PCI Express Standards The following standards govern the PCI Express interface on the X6 XMC modules X6 400M User s Manual 40 About the X6 XMC Modules Standard Describes Standards Group PCI Express 2 1 PCI Express electrical and protocol standards 5 Gbps data rate per lane per direction PCI SIG http www picmg com PCI Local Bus 3 0 PCI Local Bus a 32 bit bus operating at up to 66 MHz PCI SIG http www picmg com ANSI VITA 42 XMC module mechanicals and connectors VITA www vita org
29. IdRom method to obtain a reference to the internally managed IUsesPmcEeprom object as shown below Open the module Innovative X6 RX Module Module Target 0 Module Open X6 400M User s Manual 43 About the X6 XMC Modules Create a 50 32 bit word section at offset zero in ROM user space PmcIdromSection Sectionl Module IdRom Rom PmcIdrom waUser 0 50 Create a 50 32 bit word section at offset 50 in ROM user space PmcIdromSection Section2 Module IdRom Rom PmcIdrom waUser 50 50 Write to ROM for int i 0 i lt 50 i Sectionl AsInt i i 2 Sectionl StoreToRom for int i 50 i 100 i Section2 AsFloat i static cast float i 2 Section2 StoreToRom Read from ROM Sectionl LoadFromRom for int i 0 i lt 50 1 int x Sectionl AsInt i Section2 LoadFromRom for int i 50 i lt 100 i float x Section2 AsFloat i Chapter 17 Digital I O The X6 series has a digital I O port accessible using the P16 or JN4 connector These bits are direct connections to the FPGA and are used in many custom applications for controls communications and status signals The digital IO bits use either LVDS or LVCMOS2 5 IO standards LVDS signaling is recommended for high speed and improved noise immunity Factory installed jumpers are used to route DIO pairs 0 18 to JN4 E DIO Pairs 0 18 38 wires DIO Pairs 19 31 26 wires DIO is route
30. In each case select Install this driver software anyway to continue gt Don t install this driver software You should check your manufacturer s website for updated driver software for your device Install this driver software anyway Only install driver software obtained from your manufacturer s website or disc Unsigned software from other sources may harm your computer or steal information v See details Figure 1 Vista Verification Dialog The Installer Program After launching Setup you will be presented with the following screen X6 400M User s Manual 18 Windows Installation Please select a r product to install J e LL ETE SLUT C Innovative Change Components to Install for Quadia Quadia Applets examples Docs and Pismo libraries Malibu Host libraries utilites Docs drivers amp DLLs BinView Data graphing and analysis tool CodeHammer JTAG support for Code Composer Studio Innovative Components C Builder Support Product Registration OE Using this interface specify which product to install and where on your system to install it Figure 2 Innovative Install Program 1 Select the appropriate product from the Product Menu 2 Specify the path where the development package files are to be installed You may type a path or click Change to browse for or create a directory If left unchanged the install will use the default location of C Innovative 3
31. Integration Web Site cisccccssiccssedeoncessdcscatssconsssdecsssevendsnccdssedeossicvsnneotadssoessadensdostessssdvascsdeed O Typographic CONVENTIONS m LO Chapter 2 Wimdows Installation 50 eue eese aen nott p erroe cin ted es L7 Host Hardware Requirements ates ee REIHE A A 7 Software Installation Mr Starting the Installation ias O Th Install er PLA E Tools RESTAN dci T Bus Master Memory Reservation AP As 22 Hardware Tostall o cA AMELIE eA Installation on Deployed Systems sccsissscsuccscsccacetusssssdcescanisdsovesdedeascoueaseouesddons coneasescoanndaadosdcoususeasadexecsensex Runnme VMaliboR eds chess dadenaiadaduaedavasedaudedocasscedeasaedsdeeuavesdousopesdgeosocssvenepenl 4 Chapter 1 Tnstallation EB AA Package File Names catione sta coeli tors vete das 26 Prerequisites for Installation e RR 20 The Redistribution Package Group MalibuRed eere e eee e eren eerte seen see ensseessseeeesssss2 20 A sieo eios a seoska sesono s ioatea ienes soros aaae sapeser anson s siaa ias Ms e hri oerte O sea O A Baseboard Package Installation Procedure ooooomomsmmsms_Zz Board PACKAGES ni uanostasanseusseasseaoueeoZO Unpacking the Package c e Creating Symbolic Lamks ceo ederet at Rn Qe tae ta cies eed in dis 28 Completing the Board Bistall 5 siesta aio Za DI A THEN A MU na Maus aula vse LEES SpED IDCM
32. Ohm SMA to BNC 1 meter Table 3 SMA to BNC Coax Cable Part Number DAC Data Modes and Special Features The DAC5682Z can accept data at 1 GSPS from the FPGA allowing 500 MSPS update rates on two simultaneous channels or GSPS update rate on a single channel The data can also be half rate and 1 4 rate and then interpolated by on board 2x or 4x FIR filters Each interpolation FIR is configurable in either Low Pass or High Pass mode allowing selection of a higher order output spectral image The DAC5682Z has two optional two coarse mixer CMIX blocks CMIX0 follows FIRO and CMIX1 follows FIR1 Each CMIX block provides mixing capability of fixed frequencies Fs 2 real or Fs 4 complex with respect to the output frequency of the preceding FIR block Since FIRO and CMIXO are only used in x4 interpolation modes the output is half rate relative to the DAC output frequency Therefore an Fs 4 mixing sequence results in FDAC 8 frequency shift at the DAC output X6 400M User s Manual 115 X6 400M XMC Module The DAC5682Z allows both complex or real output When CMIXO coarse Fs 4 mixer is used in complex mode the DAC provides coarse frequency upconversion and the dual DAC output produces a complex Hilbert Transform pair 12V Reference m Delay Lock Loop DLL LP HP Fs 4 Fs 4 CMIX1 DAC Delay 0 3 o i JE t 9 E g a o a RS Delay Value Sync amp Control
33. Stream Innovative VitaPacketParser Vpp Innovative TriggerManager Trig Innovative SoftwareTimer Timer MultiLoggerManager MLM Innovative StopWatch RunTimeSW Innovative DataLogger IntermediateLogr Innovative DataPlayer App State variables IntermediatePlayer bool Opened bool StreamConnected bool Stopped App Status variables double FBlockRate ii64 FWordCount int SamplesPerWord ii64 WordsToLog Innovative AveragedRate Time Innovative AveragedRate BytesPerBlock X6 400M User s Manual 74 Writing Custom Applications In Malibu objects are defined to represent units of hardware as well as software units The Modulelo object represents the board The VitaPacketStream object encapsulates supported board specific operations related to I O Streaming The VitaPacketParser object encapsulates capabilities to extract VITA49 packets from the native Velocia packets supplied by the board during streaming The MultiLoggerManager object provides file storage for each peripheral type parsed from the stream by the parser facilitating analysis of data received The Applicationlo object derives from type Ficllo FICL is an abbreviation for Forth Inspired Control Language A simple Forth interpreter is available within the module object which can be used as a simple scripting language for the purposes of performing hardware initialization during FPGA firmware development When the Open button is pressed
34. Under rare circumstances Windows will fail to auto install the device drivers for the JTAG and baseboards If this happens please refer to the TroubleShooting section X6 400M User s Manual 22 Windows Installation Installation on a Deployed System The above instructions install the complete development platform onto a system for the development of application software Often however a developed application needs to be installed on a system that will only be used to run the program In this instance installing the complete library is overkill To support this situation Innovative has a minimal installation program called MalibuRED This is short for Malibu Redistributable This install will install the driver software and support DLLs required to run a Malibu application Note Specific applications may have their own additional requirements that are not covered by MalibuRED For example NET applications require the NET libraries to be installed as well Installation programs for NET can be obtained from Microsoft over the Internet Running MalibuRed MalibuRED can be found on the installation CD in the Windows 32 Malibu subdirectory The name of the installation file is MalibuRED exe Running the program displays the setup screen for the installer Select your baseboard a XIAADA E Using the combo box select the appropriate baseboard to install support for In this case we are installing an X3 A
35. VPX XMC 3 adapter card P N 80260 Conduction cooled or Air cooled versions are offered e So gt 2 a lt I a lt a lt 2 s a x 30 Hardware Installation Figure 9 Innovative Single lane PCIe XMC 3 adapter card P N 80172 dara a 0 OJ INNOVATI INTEGRATION T MADE INNOVATIVE 6162 INTEGRATION A XMCe PCle ADAPTER ASSY 80195 Maiti anit X6 400M User s 31 Hardware Installation Figure 12 Innovative Compact PCI PXI XMC 3 x4 lanes adapter card P N 80207 0 Figure 13 eInstrument Node cabled PCI Express adapter x1 lane for XMC Modules II P N 90181 einstrument PC Figure 14 eInstrument PC embedded PC Windows Linux hosts two XMC modules II P N 90199 XMC systems should be be compatible with VITA 42 3 specification for P15 The P16 interface can only be used when the PCI Express interface is present and active The XMC P16 interface to the host may be customized in the Application Logic Host card support for P16 interfaces varies so this must be verified on a case by case basis to determine compatibility In the specific description of each module the P16 connection pinout is provided in this manual Innovative s adapter cards provide access to P16 IO for system integration Contact technical support if you need any assistance in checking compatibility with the X6 XMC P16 interface System Requirements X6 400M U
36. Xilinx Virtex 6 FPGA Supporting peripherals include IGBytes of LPDDR2 DRAM conversion timebase and triggering circuitry 64 bits of digital IO Aurora secondary data port and a host PCI or PCI Express interface Features for module rugged operation including thermal and power monitoring support the computing and IO functions The module format is a single slot XMC and is compatible with XMC 3 host sites 4 r PE gt 5 2 n ri 4 un n x Tu 5 2 a a jm E 1 E 4 RACWAn t r f sy E NDA q q i F se Figure 31 X6 400M Module heatsink and analog shield removed X6 400M User s Manual 108 X6 400M XMC Module Custom application logic development for the X6 400M is supported by the FrameWork Logic system from Innovative using VHDL and or MATLAB Simulink Signal processing data analysis and application specific algorithms may be developed for use in the X6 400M logic and integrated with the hardware using the Frame Work Logic Software support for the module includes host integration support including device drivers XMC control and data flow and support applets X6 400M Block Diagram Ext Clk Ref A DO AID1 Trigger AID2 AID3 Figure 32 X6 400M Block Diagram X6 400M User s Manual 109 X6 400M XMC Module Hardware Features A D Converters The X6 400M has two channels of 14 bit A D sampling at up to 400 MSPS Minimum sample rate is 1 MHz below which
37. ae ake pak ae dH uS rd es Se ere pt o 1 0 9 8 7 6 5 4 3 2 1 098 7 6 5 4 3 2 1 0 Packet Type C T R R TSI TSF Packet Count Packet Size 0001 111100 Packet type set to IF Data packet with Stream Id binary 0001 C bit 27 Optional Class field enabled T bit 26 Optional Trailer field enabled TSI bits 23 22 Timestamping format for integer seconds field configurable X6 400M User s Manual 99 Vita Packet Format TSF bits 21 20 Timestamping format for fractional seconds field configurable between 01 sample count or 11 free Table 37 Timestamp Integer Seconds Options running Packet count increments on each subpacket with the same Stream Id PDN It s allowed to roll over from 1111 to 0000 Packet size in 32 bit words including the header the packet size is always a multiple of 4 due to how the packets are TSI code Meaning 00 No Integer seconds Timestamp field included Not supported 01 UTC seconds elapsed since January 1 1970 GMT 10 GPS seconds elapsed since January 6 1980 GMT 11 Other seconds elapsed since some documented starting time Table 38 Timestamp Fractional Seconds Options TSF code Meaning 00 No Fractional seconds Timestamp field included Not supported 01 Sample count timestamp fractional seconds since last integer seconds e
38. and also makes finding out how the examples use the trigger easier to discover as well In this example if using a software trigger the trigger will be applied after the number of seconds given by the Trigger Delay period This gives the streaming engine time to deliver substantial data to the card before activating the analog If using an external trigger the software trigger will not be applied Trigger Configuration Frame Triggering odule Output Trigger FramedMode Settings Framed true false odule Output Trigger Edge Settings EdgeTrigger true false odule Output Trigger FrameSize Settings FrameSize Route External Trigger source IX6lIoDevice AfeExtSyncOptions syncsel IX6IoDevice essFrontPanel IX6IoDevice essP16 odule Output Trigger ExternalSyncSource syncsel Settings ExtTriggerSrcSelection Velocia Packet Size odule SetOutputPacketDataSize Settings PacketSize Output Test Generator Setup odule SetTestConfiguration Settings TestGenEnable Settings TestGenMode odule Output TestFrequency Settings TestFrequencyMHz 1e6 Set Decimation Factor int factor Settings DecimationEnable Settings DecimationFactor 0 odule Output Decimation factor This code sets up the trigger logic and routing the packet size decimation and the FPGA test generator This last calls down into the Modulelo object to handle any board specific cu
39. and ill formed FWordCount 0 unsigned int SamplesPerWord Module Input Info SamplesPerWord WordsToLog Settings SamplesToLog SamplesPerWord FBlockRate 0 The class variables above are used to maintain counts of blocks received reception rate and whether the module is currently triggered These values are initialized prior to each streaming run Disable triggers initially done by library Set external trigger Trig AtConfigure Channel Enables Module Input ChannelDisableAl1 for unsigned int i 0 i lt Module Input Channels i bool active Settings ActiveChannels i true false if active true Module Input ChannelEnabled i true The number of channels supported varies from board to board The code uses standard functions like Module Input Channels to obtain the max channel count from a board The Modulelo also has a standard function AnalogInChannels that can be used before the board is opened and other methods are valid The previous call to GetSettings populated the Settings object with the number of channels to be enabled on this run That information is used to enable the required channels via the Channels object within the Module Input object The clock source is also programmed using the associated methods within the Module object Route reference IX6ClockIo IIReferenceSource ref IX6ClockIo rsExternal IX6ClockIo rsInternal
40. be left in the data stream or extracted to notify the application The Velo Packet Size edit control specifies the size of the Velocia packets that the module will use to X6 400M User s Manual 71 Writing Custom Applications In the Channels section we can specify number of channels to activate Selecting a channel will flow data from that data source during streaming The Trigger group contains controls that affect the way that I O starts and stops Triggers act as a gate for I O no data flows until a trigger has been received Triggers may be initiated via software or hardware depending on the Trigger Source control If software the application program must issue a command to initiate data flow If hardware a signal applied to the external trigger connector controls data flow The external trigger line may also be routed from one of two sources either the front panel connector or the P16 clock signal line Triggers are modal depending on the Trigger Mode control In Unframed mode triggers are level sensitive and data flow proceeds while the trigger is in the high active state and stops while the trigger is in the low inactive state This mode is appropriate for conventional data acquisition applications In Framed mode triggers can be selected to be edge sensitive or level sensitive on the X6 Upon detection of each trigger Trigger Frame Count samples are acquired from all active channels then acquisition terminates until
41. class not a baseboard to allow quicker porting The Module Ref is the admittedly ugly way of getting a pointer to the internal Module pointer for connection Ref returns a reference and the address of operator amp turns this into a pointer Once connected the object is able to call into the baseboard for board specific operations during data streaming If an objects supports a stream type this call will be implemented Unsupported stream types will not compile Lastly we capture and display some information to the screen This includes the logic version PCI bus version information etc DisplayLogicVersion Similarly the Close method closes the hardware Inside this method first we logically detach the streaming subsystem from its associated baseboard using Disconnect method Malibu method Close is then used to detach the module from the hardware and release its resources Applicationlo Close Close Hardware amp set up callbacks void ApplicationIo Close X6 400M User s Manual 77 Writing Custom Applications if Opened return Stream Disconnect StreamConnected false Module Close Opened false UI gt Log Stream Disconnected Starting Data flow After downloading interface logic user can setup clocking and triggering options The stream button then can be used to start streaming and thus data flow void ApplicationlIo StartStreaming if StreamConn
42. data acquisition and DSP products allows you to incorporate leading edge technology into your system without the risk normally associated with advanced product development Your efforts are channeled into the area you know best your application Vocabulary Introduction What is X6 400M The X6 400M is a flexible IO module that integrates 400 MSPS digitizing and 500 MSPS signal generation with signal processing on a XMC PMC IO module The signal processing core has a Xilinx Virtex 6 FPGA with memory and a high performance PCI Express PCI host interface The X6 400M can sustain real time transfers to the host at over 2 GB s The X6 400M features two 14 bit 400 MSPS A Ds The sample clock is from either a low jitter PLL or external input Multiple cards can be synchronized for sampling using the triggering and clock features There are also two 16 bit 500 MSPS D A channels that can be used as one channel at 1 GSPS update rates Features for coarse mixing and interpolation in the D A devices expand the signal generation capabilities to Nyquist shifting and image control A Xilinx Virtex6 LX240T SX315 and SX475T available with 4 banks of 1GB DRAM provide a very high performance DSP core with over 2000 MACs SX315T The close integration of the analog IO memory and host interface with the FPGA enables real time signal processing at extremely high rates The X6 family power is less than 15W for typical operation VITA 20 conduction coolin
43. end up with one buffer containing all the data X6 400M User s Manual 90 Writing Custom Applications The first step is to set the output size to be considerably larger than the total amount of data we have Here I use a factor of 2 The real need is to have enough room for the packet data and the 8 words of header trailer data for each packet The rough doubling is good enough since we only will have the one packet Use a packer to load full VITA packets into a velo packet Make the packer output size so big we will not fill it before finishing VitaPacketPacker VPPk scratch pkt size 2 VPPk OnDataAvailable SetEvent this amp ApplicationIo HandlePackedDataAvailable Shove in our VITA packets for unsigned int i 0 i VitaQ size i VPPk Pack VitaQ i VPPk Flush outputs the one waveform buffer into Waveform At the end of the for loop above all the data is present in the packer with a large excess as well The packer has the ability to force the output of residual data by truncating the packet to exactly fit This Flush operation forces a final call to the OnDataAvaliable event which we have made sure is the only one we get Then we clean up and init the Waveform headers and we have a valid packet ready for sending when needed WaveformPacket is now correctly filled with data ClearHeader WaveformPacket InitHeader WaveformPacket make sure header packet size is valid
44. event function i e Access Violation OnLoadMsg Execute Load Message Event Because of statement Board gt OnLoadMsg SetEvent this Applicationlo DoLoadMsg Change the Project Options for the Linker Project Options Linker ilink32 Linking uncheck Use Dynamic RTL In our example Host Applications if not unchecked this will cause the execution to fail before the Form is constructed Error First chance exception at xxxxxxxx Exception class EAccessViolation with message Access Violation Process exe nnnn X6 400M User s Manual 92 Developing Host Applications Other considerations Project Options Compiler bcc32 Output Settings check Specify output directory for object files n release build Release debug build Debug Paths and Defines add Malibu Pre compiled headers uncheck everything Linker ilink32 Output Settings check Final output directory release build Release debug build Debug Paths and Defines ensure that Build Configuration is set to All Configurations add Lib Bcb10 change Build Configuration to Release Build add lib bcb10 release change Build Configuration to Debug Build add lib bcb10 debug change Build Configuration back to All Configurations Packages uncheck Build with runtime packages X6 400M User s Manual 93 Developing Host Applications Microsoft Visual Studio 2005 Microsoft Visual C 2005 version 8 Project Properties When
45. format of the data packets streamed to and from the card This chapter describes the format and the changes from previous use Chapter 55 X6 Velocia Packets Chapter 56 Packet Header Format Just as in the X5 data busmastered between the board and the application program is enclosed in a data packet For the most part this packet has not changed What has changed is that the packet header is now 4 words long rather than 2 Also the total packet size now must be divisible by 4 words rather than 2 as well This is a reflection of the new internal bus being made wider for increased efficiency Table 34 X6 Velocia Velo Packet Header 0 Velocia Header Word 1 reserved 2 reserved 3 reserved As before the first word in the header contains the information used to identify the packet and determine its size The Peripheral ID is a tag value used to identify the data source all packets with the same Peripheral ID are defined as making up a single stream of data The size allows the parsers to find the next header X6 400M User s Manual 97 Vita Packet Format Table 35 Velocia Header Word Se d x pm p x xq 198 510 ak jak pat ak 199 E E 5198 pH 499 Hp ux IS pep uo ih OS es foe mS dEEIS T9 108 HO IE HB mI HE eh ES EJ I Peripheral ID Packet size in 32 bit words In the Malibu library the
46. is common code While each compiler implements the GUI differently each version of the example project uses the same code file to interact with the hardware and acquire data Chapter 44 Program Design The Snap example is designed to allow repeated data reception operations on command from the host As mentioned earlier received data can be saved as Host disk files When using modest sample rates data can be logged to standard disk files However full bandwidth storage of multiple A D channels can require up more capacity so a dedicated RAIDO drive array for data storage may be required or data may have to be cached online and stored after stopping data flow The example application software is written to perform minimal processing of received data and is a suitable template for high bandwidth applications The example uses various configuration commands to prepare the module for data flow Parametric information is obtained from a Host GUI application but the code is written to be GUI agnostic All board specific I O is performed within the ApplicationIo cpp h unit Data is transferred from the module to the Host as packets of Buffer class objects Chapter 45 The Host Application The picture to the right shows the main window of an X6 example for the X6 RX This form is from the designer of the CodeGear Cbuilder 2007 version of the example but the Microsoft and Qt versions are similar It shows the layout of the controls of the Us
47. is padding Padding is a response to the need to be able to issue a Vita packet at any time To be send across the busmaster interface the packet must have a size that is divisible by 4 in 32 bit words Yet we need to be able to issue a Vita packet in cases such as when a trigger lowers that can happen at any time If we hold the data it will be issued at the wrong time To send it we need to pad the packet to an even 128 bit boundary The padding field is used to tell us which bytes in a packet are invalid pad bytes instead of actual data The datagrams check this field and reduce the size of the datagram to avoid using this dead space for reading or writing Copy Data to Vita for unsigned int idx 0 idx lt VitaDG size 1dx VitaDG idx ScratchDG offset idx Init Vita Header VitaHeaderDatagram VitaH VBuf VitaH StreamId 0 fix up loop counters words remaining VP size offset VP size save the buffer VitaQ push back VBuf Now that we have our array of Vita packets we can copy them into a large Velo packet for sending The VitaPacketPacker object was made to facilitate this operation You can set an output packet size and then as you Pack the packets in whenever a new packet is filled the OnDataAvailable event is called for you to process the Velo packet before continuing The expectation is that you would call Send in this function but in this case we will tweak the settings to make sure we
48. mezzanine module sites The card form factor is IEEE 1386 with XMC connectors P15 and P16 P15 is used for PCI Express while P16 is used as digital IO unique to the X6 modules The X6 modules mount 10mm from the host card and may use standoffs for mechanically securing the module to the host PCI Express Bus Type Requirement Standard PCI Express 1 0a Lanes 8 Bus Speed Genl 2 5 Gbps per lane per direction Gen2 5 Gbps per lane per direction Power Supplies 3 3V and VPWR 5V or 12V is required on all XMCs Table 1 X6 XMC Bus Requirements Note PCI Express interfaces supports Genl 2 5 Gbps or Gen2 5 Gbps operation For Gen2 the host system must support Gen2 operation in the installed site For Gen2 x8 the X6 module must be ordered with 2 FPGA speed grade or better Adapter cards for XMC modules shown below allow X6 XMC modules to be used in a desktop PCs with PCI Express or PC slots To get out of the PC chassis consider using either the eInstrument Node The eInstrument node can host one XMC using cabled PCI Express using a cable as long as 5 meters For an intelligent computing node the eInstrument PC provides an embedded PC running Windows or Linux disk drives and other PC peripherals with two XMC module sites X6 400M User s Manual 29 Hardware Installation Preferred for X6 Modules Figure 7 Innovative x8 lane PCIe XMC 3 adapter card P N 80259 a Figure 8 Innovative 3U
49. oul n e Species haces ILU Ded 29 BAT ates as ve e lo aay Ct a omit Nae iu cca a cans 29 Chapter 2 Hardware Installation nidad Aa US ERE I REP MER NONE S Ya a e REUS 30 Compatible Host cid oer sS 30 System RequiremeHts ee tei siste Ce Coe PEN REI PR see PeLe o EPE SEE EC REUS ERA Rene eue DQ OUR aee QUR Vbs MPO NEQNE TEPE S RED 33 Power SAEI RTT C T I 34 hulzvipiine lem inioriso rrr ads 35 Chapter 3 About the X6 XMC Modules 1 ee eee eee eee ee eee ee eere sette se tenes tenes estne sees set esa se eee enss sene 36 AD XMC ArClBItCCUIEG o caches done ado oap itn da ii 36 KO Computing eto 38 X6 PCI PCI Express TWtert ae rational 39 PCI Express Inter tac een sssi s E E 40 PCT TMC GRBAC ca A T I NEOR T 40 Co fis ring The Host IMtertace sis cisiecsscssccssacacecsavssiensaecidghoadcsdousdedsdensesusseccancadeunsvcedacsdedssvevesessenasivesed 41 PCI and PCI Express Standards seoesoesssosesocesoesssoessocsssosesoessoeessosssoesssosssocsssosssoeessosssosssoesssosssoes 41 FPGA Integration with the PCI PCIe Host Data Path eeseesoesoessoesoesoeesoesoesoeesoesoesoessoeeseosesssoeeee 42 Data Buffering and Memory rc 42 DRAM Devicos onto adi 43 DRAM Connections 16 EPA a 43 Data Butter DRM ode erroe ioa da 43 Serial FLASH Mtera Cens TT TIU D DI TEES 44 FLASH Memory Desc pi rere re exon cal ne At an 44 Digital O emer aoa
50. power down Feature Voltage Supply Power Notes Consumption W Aurora Ports VPWR 0 13 W per port GTX at 2 5 Gbps no load A D VPWR 1 1W per A D Power enables are provided to each A D device with software control device 2 channels LPDDR2 VPRW 0 4W per device 2 devices are not used for baseline functionality Software controls are X6 400M User s Manual 137 X6 400M XMC Module Table 27 X6 400M Power Consumption for IO Features It has also been shown that running VPWR at 5V saves power about 600 mW Surge currents occur initially at power on and after application logic initialization The power on surge current lasts for about 10 ms at several amperes on both 3 3V and 12V This surge is due primarily to charging the on card capacitors and the startup current of the FPGAs After initial power up the logic configuration will also result in a step change to the current consumption because the logic will begin to operate In our testing and measurements this has not been a surge current as much as a just a step change in the power consumption Power consumption varies and is primarily as a function of the logic design Logic designs with high utilization and fast clock rates require higher power Since calculating power consumption in the logic requires many details to be considered Xilinx tools such as XPower are used to get the best estimates It is important that any custom logic design have a substantial safety margin for t
51. severely degraded performance occurs The X6 400M has AC or DC coupled 50 ohm terminated inputs through front panel SMA connectors Feature Description Inputs 2 Input Range AC Coupled 2 2Vpp DC Coupled 2 0Vpp Maximum Input Current 30 mA Input Coupling AC coupled or DC Coupled Input Impedance 50 ohm A D Devices Texas Instruments ADS5474 Output Format 2 s complement 14 bit Number of A D Devices 2 simultaneously sampling Sample Rate 1 MHz to 400 MHz Calibration Factory calibrated Gain and offset errors are digitally corrected in logic Non volatile EEPROM coefficient memory Table 41 X6 400M A D Features Conversion clocking is provided by either a low jitter programmable clock source or an external clock input The clock buffering is designed to minimize jitter and maximum acquired signal quality See the clock discussion for more details A D Front End Front end circuitry for the A D converters includes a 50 ohm terminated SMA input connector followed by a transformer for AC coupled version or amplifier for the DC coupled A D inputs Impedance matching networks are used to provide the 50 ohm input For the AC coupled version the capacitors after T1 are installed and resistors after the amplifier R455 R460 are removed Amplifiers are not installed on AC coupled version For the DC coupled version the capacitors after T1 are removed and resistors after the amplifier R455 R
52. temperature sensor on the card monitors the FPGA die temperature This gives a good indication of the card temperature since the FPGA is usually the hottest device and is located in the center of the card vas EEE ELO E H i 1 i 3 ONCN AE m S n Figure 24 Temperature Sensor Location Temp Sensor Range Accuracy Monitor IO Bus Software Functions FPGA Die 125C to 125C 1 5C FPGA on die transistor SMB bus via Temperature junction LM96193 monitor readback and thresholds Table 24 X6 Temperature Sensor Chapter 29 Software Support for Temperature Monitoring Software support tools provide convenient access to the temperature and thermal controls These should be used in application programming configure and monitor the temperature as illustrated below X6 400M User s Manual 55 About the X6 XMC Modules Open the module Innovative X6 RX Module Module Target 0 Module Open Create reference to thermal management object on module const LogicTemperatureIntf amp Temp Module Thermal Read current temperature float t Module LogicTemperature Read write current warning temperature float t Module LogicWarningTemperature Mod
53. used with the supporting software allows the X6 400M to act as a data acquisition card with 1GB of data buffering and high speed data streaming to the host PCI PCI Express The example software for the X6 400M demonstrates data flow control logic loading and data logging Other Cards VITA Packets emerge from AFE Velocia Packets to from PCIe 2 devices PCle VITA Packets sent toAFE E 2 devices Wishbone connection to logic Figure 9 X6 400M FrameWork Logic Data Flow The data flow is driven by the data acquisition process Data flows from the A D devices into the A D interface component in the FPGA as controlled by the triggering The data is then corrected for gain and offset errors associated with the analog inputs After error correction the data is formed into VITA packets and sent to the VFIFO the data buffer The data buffer implements a data queue in the DRAM The packetizer pulls data from the queue creates Velocia data packets of the programmed size and sends those to the PCIe interface logic or out the host link From here the Velocia packet system controls the flow of data to the host Data packets flow into host memory for consumption by the host program The D A channels have essentially the inverse of the A D data flow data is fetched from the host system using the Velocia DMA controller on PCIe Velocia packets are dissembled then stored in VFIFO VITA packets to the DAC then
54. void neri Eon css essed betta de bab ones um abt ea AM E IRA Gees 103 Context Packet COM co oci ote aa tte EOS 103 Padding istas suit od ul s ae a tbe tu ce ie dots stet ose vct teo A ead UM 103 Chapter 6 ADDIGISs nica otii d exon ote Pe rocosa A Aa 104 Common AP Pl Cts MT D c 104 Registration Utility NewWUSEM 6X iccsisecssssossesescossocessosonenstensnsssnesseoussseonbsseeasesenssadsosseseesensessoeseeaie 104 Reserve Memory Applet ReserveMemDsp exe csccscsscssssssssssecsssessscssccscssesscsssssssesescsssseess 105 D ta Analysis A atarsan eas tessneissao erres E iRise eiae SSpS NOS e tes d orots EasS 105 Binary File Viewer Utility BinView exe ooooomsmssss 105 Chapter 7 Applets for the X6 Family Baseboard ccsscccsscsscsscssssscsssssccsssccsssccsssssssssceesssscees 106 Logic Update Utility VSPFOMEXO c xisseccasisscascscsseassdtsecdscsssenescstsnceceossescsedonscbscvcsanccocbsaceseedtbeanssecestes 106 Fido M M 107 Chapter 8 X6 400M XMC Module cueca nds acia 108 TOO UCI MR 108 Hardware Features co 110 E OI 110 A D Front En occ iaa 110 Input Range and Conversion Codes ssccissccsssssccassssvecosensncectsascsasisncvestsnacsdetaaseaecsscudaudesscecenentsccssdowene 111 Driving the A D Tes eer 112 Overrange Detectar seins GE rosera oes oos eris e EE Lua Ue aaea ESS aesa Sesen sse SEOs 112 IE Wednzcai e 112 Ives vrin
55. 0 Default Digital IO Configuration Chapter 20 Notes on Digital IO Use The digital I O on X6 modules as supported using the standard FrameWork Logic is intended for low speed bit I O controls and status Application logic can implement much higher speed and sophisticated interfaces by modifying the interface to the pins to construct higher speed data transfers controls and timing signals as required by the application The X6 FrameWork Logic user Guide details logic supporting the digital IO port and gives the pin information for customization Chapter 21 P16 Communication Ports The X6 series implement a high speed communication ports on the XMC P16 connector used as a secondary data path on the module These ports are Aurora protocol for the Framework Logic The high speed serial ports are connections to the FPGA GTX ports and can be used for other protocols or custom implementations The P16 connections on the X6 are compatible with the VITA 42 0 secondary connector specification and provide eight transmit and receive pairs implemented using Virtex 6 GTX links A programmable clock reference is provided on board for the GTX links X6 400M User s Manual 47 About the X6 XMC Modules The P16 connector pinout is shown in the hardware chapter Chapter 22 GTX Connections to P16 Pinouts for the P16 connector showing the transmit and receive pair locations are given in the Connectors section The following table gives the Rock
56. 0 Table 37 X6 JINX Connector Pino tits sais O ee Io ER CRI Gea vel Nutt cease votare ips 163 Table 38 X6 JN2 Connector Pinot sitas 166 Table 39 X6 400M JP3 Xilinx JTAG Connector Pinout essent nnne 168 Table 40 X6 400M JP1 Boot Image Select eee cn ladra 168 List of Figures Figure 1 Vista Verification DISIQR oo eodeni te RUE RS epe S Ee Eder earn aon a eas 18 Figure 25 Innovative Install Programi aa 19 Figure 3 Progress is shown for each section site ederet Reese dpa tt Repas OR Y HR REY EE Se VEO E Ye Ne 20 Figure 4 ToolSet registration TOO uus ert exte a ipie do NOH ERU EUN AE UT MB quel dave pM 22 Figures BusMaster con SUE TO aso ote ede A toa 22 Figure 6 Installation COMPITE A TEE deas 23 Figure 7 Innovative x8 lane PCIe XMC 3 adapter card P N 80259 sss 31 Figure 8 Innovative 3U VPX XMC 3 adapter card P N 80260 sse 31 Figure 9 Innovative Single lane PCIe XMC 3 adapter card P N 80172 sss 22 Figure 10 Innovative PCI 64 66 XMC 3 4x lanes adapter card P N 80167 0 32 Figure 11 Innovative x8 Lane PCI Express XMC 3 8x lanes adapter card P N 80173 0 32 Figure 12 Innovative Compact PCI PXI XMC 3 x4 lanes adapter card P N 80207 0 33 Figure 13 eInstrument Node cabled PCI Express adapter x1 lane for XMC Modules II P N AOS 33 Figure 14 eInstrument PC embedded PC Windows Li
57. 1 Boot Image Select Mechanicals The following diagrams show the X6 400M connectors and physical locations The XMC conforms to IEEE 1386 form factor 75mm x 150mm The spacing to the host card is 10 mm and consumes a single slot in desktop and Compact PCI PXI chassis An EMI shield is normally installed over the analog section Detailed drawings for mechanical design work are available through technical support X6 400M User s Manual 164 X6 400M XMC Module JP3 JTAG JP5 JTAGis M25 TH 4 PL _ J7 A D 0 CEO J9 D A 0 J10 D A 1 1 JP1 Boot JP4 Connect M2 TH 13 PL Image Select VPWR to PCI 5V Figure 33 X6 400M Mechanicals Top View Rev A hec ss curo ow o X6 400M rev A e wm CE Cy wh CHIEN CT QU M2 ASSY 80270 qe d ape E Tw PCB 715266 Rev A He MADE IN U S A mcm S 88 ao 0 0 m R325 MR S20 y E2U mun e e m m Sem an Beane gar c AA NNI maou mm SE IZ B E Bee stn 3 Lu H o EN mixes zr A5 _ mos CSS cus cy Sn a R30 aa M E E es oe CD RS zs MO LS Ree i ess ER iii Fi EU n s d ga mie Sens 8 B8 8D m B Jj M y D TT E 263 5 dimi Obit ie m IBS coma Cr TT EET BS EMI TS Bo ES zl p07c270 02 u37 Figure 34 X6 400M Mechanicals Bottom View Rev A X6 400M User
58. 10 Interfaces from PCI Express to Application Logic 42 Table 11 X6 DRAM Devil cotes teens ted oro ia 43 Table 12 Buffer Memory Bandwidlbi ios ioo eor id tU Ee n 44 Table E3 X6 Seta MED ASIE DEVICE sca i orit id DURO OS 44 Table 14 DIO Connector Comm Sur ations ss iro edes rrr ti aiU qd epo va Pe Rech neh eabesdtvedsles 46 Table 15 LVCMOS 2 5 Digital IO Bits Electrical CharacterlstiCS oooconnciccnnninncnncnnocononconnnonanononnnnanos 46 Table 16 LVDS2 5 Digital IO Bits Electrical CharacterisStiCS oococonncnncnnnnnncionnoccnonononcnrncnnccnnnnanannnno 47 Table 17 IU sesDioPort Class Oper ors aieo re out ts pii br eR ege ores enar ei NP IR Arcs ed 47 Table 18 P16 GTX Assignments and Use os oto epe eb oe o RONDE Ie es eU prin 49 Table 19 GTX Signal Electrical Characteristics pias euni ee code tet b C e pee e ve te cados 50 Table 20 GTX PLL Reference Clock Characteristics mirada Cose ett tuto gets Ie reet utar unes 50 Table 21 GTX Alternate Reference Clock Input Characteristics esses 5 Table 22 System Integration Signals on P16 Connector sss enne 54 Table 23 X6 Temperature Threshold and Limits nerd centre Iota aene ri eus thx e C In eie dou 55 Table 24 X6 Temperature SensOEb qi otiosi pst Rer aao Fen e te DOR Ve e Ru RE Re CA NO a de OB Vv RYE iaaa ians 56 Table 25 X6 Conduction Cooling Hardware sss eene enne 59 T3ble 26 Xo Power Control Des paid i na QUE d n odd Od as
59. 35 Getting Good Analog AA A OE asa tieu EIS CKUS 136 Power REGUERA AAA CE P MR UR 137 Power SupDli S siseses isasi eeen tobia cue de RA a ac MAPA E CER EIE 137 Power Consuniptlon 2o eiae oca odias cubaseea Coo ena ori Cu SAO eQN LS EN Yee OE NOR Ue 137 Mi erc T 139 Performance Data pp o soian 141 Analog Input Performance SumMary cisccsnsssccesssicecssessvsscsossseesssnovenssensssdovensecnsssesdecsronssessasascoadecsdes 141 WII ON 145 COMME COONS cR CDU EN 152 Front Panel Connectors JS J VQ ss scsiccucssscssdescsticcevcsccescsesevescsessseduntattecsesatebeuassiensiesonsconsseisesusasvendnses 152 XMC PIS Pri LOK e T NR 153 XMC PIO Gru deo Ein t REN 156 AMIA O OEE ST 159 PNCINZ CONNOR Rda olaaa 162 PMC JN4 COM ds 165 AA A D 167 FLASH Boot Image Selects nica aia iii ii 168 A ON 168 List of Tables Table 1 X6 XMC Bus Requirements cuo istoc lt apr AU rS queri P eta A 30 Table 2 Required PCIe Resource ALO Caio eto eec a e 34 Table 3 AMC Mo nting Hat Watt abl eed tu Obr rera a eril Sos e ea FERE FS pee equ 35 Table 4 X6 MCFan a 31 Table X6 MIC Pal AA NS 37 Table 6 X6 XMC Family Perle Sa oer Pea ERE mae ee E RE eo Poe os e RS 38 Table 7X6 Comp tine Core Device 38 Table 8 Logic Images for PCI and PCI Express Hosts ccccccecssessseceseceseeeeeeeeeeceessaeecenseeeeeeeeeeees 41 Table 9 PCI PCI Express Standards Compliance oooocoonocononanonnnnonannnnonancnonccnoncconconorconacononcaconononconos 42 Table
60. 400M PCIe Module Snap Example O army Configure Setup E EEProm Debug Debug Logs Dij ie Streaming Auto Stop Intermediate Log Logging Enable Plot Enable Enable Y Enable v Ch D Cho Samples v Ch1 Ch 1 80000000 Post Process Count MSamples Rate MB s Temp C PLL Locked yent Log Be sure to read the help file for info on this program located in the root of the this example folder System wordset loaded ficl Version 3 03 Apr 5 2011 gt 6_400M specific wordset loaded ok No devices detected Module Device Open Failure Target board not found Module Device Open Failure Target board not found L Chapter 47 Host Side Program Organization The Malibu library is designed to be built in numerous different host environments Borland CodeGear Embarcadero CBuilder Microsoft Visual Studio under Windows or QtCreator under Windows Linux Because the library is built using and identical source code base in all environments the code that interacts with Malibu is identical regardless of the toolchain used Within examples the portion of the code which interacts with Malibu is factored into a class Applicationlo in the files Applicationlo cpp and h This class acts identically on all frameworks and OS platforms It is very important to realize that the most expedient method to create a custom application regardless of the framework type used NET VCL Qt wx Widgets or console mode
61. 400M User s Manual 16 Windows Installation chapter 2 Windows Installation This chapter describes the software and hardware installation procedure for the Windows platform WindowsXP Vista and Windows 7 Do NOT install the hardware card into your system at this time This will follow the software installation Host Hardware Requirements The software development tools require an IBM or 100 compatible Pentium IV class or higher machine for proper operation An Intel brand processor CPU is strongly recommended since AMD and other clone processors are not guaranteed to be compatible with the Intel MMX and SIMD instruction set extensions which the Armada and Malibu Host libraries utilize extensively to improve processing performance within a number of its components The host system must have at least 1 GB of memory 2 GB recommended 1 GB available hard disk space and a DVD ROM drive Most versions of Windows released after Win2000 including XP Vista or Windows 7 referred to herein simply as Windows or later is required to run the developer s package software and are the target operating systems for which host software development is supported Software Installation The development package installation program will guide you through the installation process Note Before installing the host development libraries VCL components or MFC classes you must have Microsoft MSVC Studio version 9 or later CodeGear
62. 460 are installed X6 400M User s Manual 110 X6 400M XMC Module AGND 7AYCPZ JT j 901143 R452 rus Aa R457 301 A a as css RH iz AN o R453 5 575 1 4 4 jur AIN R458 P AGND mi ca EDEN 6 DNP i E MCMO R451 40 9 VREI Ls A A A 2 1 cM alk SUM 0 CKP cri ce AGND TERN 1 CHE AGND i R462 R463 D 8 127 127 5V_0 ese EX R464 324 0 1uF R465 332 n ADCO CLKP p AGND ADCO_CLKN AF 3 R466 R467 R408 84 5 845 20K DNP OAIN AGND AGND T AGND 4 cvv TCT 1 13M OAIN N P AGND Figure 33 X6 400M A D Channel Front End The other analog input is identical Input bandwidth measurement is shown in the data section of this chapter Input Range and Conversion Codes A D input range and coding is shown for the AC and DC coupled versions The input is single ended with 50 ohm input impedance Other input ranges may be custom ordered Data output codes from the high speed A D channels are 2 s complement 14 bits The following table gives the transfer function Input voltage V High Speed A D Conversion Code hex 1 1 Ox7FFF 0 6 Ox3FFF 0 0x0000 0 6 0xC000 1 1 0x8000 Table 42 AC Coupled A D Conversion Coding Input voltage V High Speed A D Conversion Code hex 1 0 Ox7FFF 0 6 Ox3FFF
63. 4D4 board If support for multiple cards is needed the program must be run to completion once for each type of board This is required because parts of the installation such as baseboard device drivers may be different for different board types After selecting the board press Go to begin installation The window changes to display the progress of the install X6 400M User s Manual 23 Windows Installation Minted ones M Thank you for choosing X3 A4D4 Installing Malibu Redistributable Libraries After completing the installation reboot the system to allow Windows to recognize the new drivers Then proceed with the Hardware Installation as in the development system installation above X6 400M User s Manual 24 Installation on Linux Chapter3 Installation on Linux This chapter contains instruction on the installation of the baseboard software for Linux operating systems Software installation on Linux is performed by loading a number of packages A Package is a special kind of archive file that contains not only the files that are to be installed but also installation scripts and dependency information to allow a smooth fit into the system This information allows the package to be removed or patched Innovative uses RPM packages in its installs Package File Names A package file name such as Malibu LinuxPeriphLib 1 1 3 1586 rpm encodes a lot of information Malibu Linux PeriphLib 1 1 3 1586 rpm
64. A connectors The cards are connected using SATA cables that connect the transmit port of each card to a the receiver on another card Each cable carries two lanes so two cables are required per link the Aurora port is x4 lanes in each direction Other topologies can be easily implemented by rearranging the cables X6 400M User s Manual 51 About the X6 XMC Modules pl E um EN J Link 1 2 Key Link Tx Rx 4 lanes per link Figure 22 X6 Module Cluster Using Aurora The modules can communicate at speeds up to 900 MB s full duplex in this topology using 2 5 Gbps lanes The cables limit the lanes to a maximum of 3 125 Gbps in this configuration Chapter 26 System Timing Features on P16 System integration features include timing signals on P16 for system synchronization and coordination These features allow the use of system wide clocks triggers and timing events to generate local sampling and control signals X6 400M User s Manual 52 About the X6 XMC Modules Signal P16 Pin Description Notes H PPS D19 Pulse per Second timing input This signal is often LVCMOS2 5 IO standard from GPS or other timing source H_TRIGO A19 Trigger input 0 used for system coordination LVCMOS2 5 IO standard H TRIGI B19 Trigger input 0 used for system coordination LVCMOS2 5 IO standard FMC CLKP N A9 B9 Sample clock input This signal can be used as a LVDS 2 5 IO standard sample clock or PLL r
65. C some cards use 2 Memory LPDDR2 DRAM 4x Micron MT42L256M32D4KP 25 IT The X6 FPGA computing core connects the IO peripherals host communications and support features Each IO device on the X6 modules directly connects to the application FPGA providing tight coupling for high performance real time IO The FPGA logic implements an interface to each device that connects them to the controls and data communications features on X6 400M User s Manual 37 About the X6 XMC Modules the module Support features such as sample triggering and data analysis are implemented in the logic to provide precise real time control over the data acquisition process The X6 module architecture is really defined by the features in the logic that connect the IO devices to data plane and system interfaces The data plane connects the IO and computing elements using a high speed packet network Data from IO devices such as A Ds is made into data packets conforming to ANSI VITA 59 specification and enters the data plane for routing to other devices or logic elements This packet architecture provides the X6 modules with a flexible and extensible data architecture that grows to meet application requirements Data transmissions to or from the host PCIe interface use the Velocia packet system to communicate with the host The Velocia packet system implements an automated DMA transfer with the host sytem over the PCIe interface The Velocia packet system provides b
66. Current 12mA FPGA can be reconfigured for custom designs for other drive currents Input Logic 1 gt 1 7 VDC Thresholds 0 0 7 VDC Input Impedance gt 1M ohm 15 pF Excludes cabling Table 15 LVCMOS 2 5 Digital IO Bits Electrical Characteristics X6 400M User s Manual 45 About the X6 XMC Modules LVDS 2 5 Pins The LVDS signal pairs support high speed signaling All pairs are routed as 100 ohm differential impedance 50 ohm single ended All LVDS pairs must be terminated to 100 ohms For inputs designers should instantiate on chip termination in the Virtex 6 logic For outputs the signal destination must have 100 ohm termination impedance Warning the LVDS 2 5 DIO pins are NOT 3 3V or 5V compatible Input voltage must not exceed 2 8V during normal operation Undershoot and overshoot must be limited see the Xilinx Virtex 6 User Guide for details Parameter Value Notes Input common 1 2V typical For differential input voltage mode voltage 0 3V min 2 2V max 350 mV Input 1000mV max 100 ohm differential load Differential 100mV min Voltage Output High 1 765V max 100 ohm differential load Voltage PorN Output Low 0 715V max 100 ohm differential load Voltage PorN Output 840mV max 100 ohm differential load Differential 350mV min Voltage Table 16 LVDS2 5 Digital IO Bits Electrical Characteristics Chapter 19 Software Support The Framework Logic configur
67. D channel 1 J9 D A channel 0 J10 D A channel 1 J5 Trigger J6 Sample Reference Clock Input Figure 25 Front Panel SMA Connector Functions J5 J10 X6 400M User s Manual 150 X6 400M XMC Module XMC P15 Connector P15 is the XMC PCI Express connector to the host XMC pin header 0 05 in pin spacing vertical mount Number of Connections 114 arranged as 6 rows of 19 pins each Connector Part Number Samtec ASP 105885 01 Figure 26 P15 XMC Connector Orientation X6 400M User s Manual 151 X6 400M XMC Module Table 32 X6 400M XMC Connector P15 Pinout Column Row A B C D E F 1 PETOpO PETOnO 3 3V PETOp1 PETOn1 VPWR 2 GND GND GND GND MRSTI 3 PETOp2 PETOn2 3 3V PETOp3 PETOn3 VPWR 4 GND GND GND GND MRSTO S PETOp4 PETOn4 3 3V PETOpS PETOn5 VPWR 6 GND GND GND GND 12V 7 PETOp6 PETOn6 3 3V PETOp7 PETOn7 VPWR 8 GND GND GND GND 12V 9 VPWR 10 GND GND GND GND GAO 11 PEROpO PEROnO MBIST PEROpI PEROn1 VPWR 12 GND GND GA1 GND GND MPRESENT 13 PEROp2 PEROn2 3 3VAUX PEROp3 PEROn3 VPWR 14 GND GND GA2 GND GND MSDA 15 PEROp4 PEROn4 PEROp5 PEROnS VPWR 16 GND GND MVMRO GND GND MSCL 17 PEROp6 PEROn6 PEROp7 PEROn7 18 GND GND GND GND 3 3V 19 PEX REFCLK PEX REFCLK WAKE ROOT rane o Note All unlabeled pins are not used by
68. Directories Innovative Lib Vc8 If anything appears to be missing view any of the example sample code Vc8 projects X6 400M User s Manual 95 Developing Host Applications DialogBlocks DialogBLocks Project Settings under Linux Project Options Configurations Compiler name GCC Build mode Debug Unicode mode ANSI Shared mode Static Modularity Modular GUI mode GUI Toolkit your choice wxX11 wxGTK 2 etc gt Runtime linking Static or Dynamic we use Static to facilitate execution of programs out of the box Use exceptions Yes Use ODBC No Use OpenGL No Use wx config Yes Use insalled wxWidgets Yes Enable universal binaries No Debug flags ggdb DLINUX Library path INNOVATIVE Lib Gcc Debug WINDRIVER lib Linker flags AUTO WI PROJECTDIR Example lcf IncludePath I INNOVATIVE Malibu I INNOVATIVE Malibu LinuxSupport AUTO Paths INNOVATIVE usr Innovative WINDRIVER usr Innovative WinDriver WXWIN usr wxWidgets 2 8 7 provided that this is the location where you have installed wxWidgets Summary Developing Host and target applications utilizing Innovative DSP products is straightforward when armed with the appropriate development tools and information X6 400M User s Manual 96 Vita Packet Format Chapter53 Vita Packet Format Chapter 54 Overview The X6 family of baseboards introduces a new form of data streaming that changes the
69. FPGA generated test data by enabling one of the test modes This is useful when developing custom logic The code snippet below applies the test mode stored in the Settings TestGenMode variable to the hardware Input Test Generator Setup Module SetTestConfiguration Settings TestCounterEnable Settings TestGenMode I O samples can be decimated using a feature within the stock firmware The code snippet below applies the specified decimation factor to the hardware Set Decimation Factor int factor Settings DecimationEnable Settings DecimationFactor 0 Module Input Decimation factor The streamed data is logged without change to an intermediate file that can be analyzed with BinView If this logging is enabled this starts the logger if Settings IntermediateLogEnable IntermediateLogr Start The code below applies the user specified trigger and and alert configuration settings to the hardware Frame Triggering and other Trigger Config Module Input Trigger FramedMode Settings Framed Module Input Trigger Edge Settings EdgeTrigger Module Input Trigger FrameSize Settings FrameSize Module ConfigureAlerts Settings AlertEnable Trig AtStreamStart Samples will not be acquired until the channels are triggered Triggering may be initiated by a software command or via an external input signal to the Trigger SMA connector The module supports framed tr
70. Hz onboard PLL Channel 0 15 pF parallel cap at A D device inputs X6 400M User s Manual 141 X6 400M XMC Module Binview Wdmelane praiectsx6 x6 400mhardware reva test data plot1 bdd elk E RinView Weimelane prajectst lt lx6 400mihardware revaltest data plat4 hdd a Md hh DBE CO d Or a Marh DBE CO Or Time Frequency Text Summary 5 Tine Frequency Tont Summay 5 Magnitude vs Frequency Magnitude vs Frequency l Y 110 F 97K 98K 99K 100K 101K 102K 103K 104K KHz KHz 0 20K 40K 60K 80K 100K 120K 140K 160K 180K Ku pl Max S N eB SN SINAD dB ENOB bis SFR EB THD 12 48 Max S N dB SN SINAD d8 ENDB bis SFR EB THD 12 48 850 622 EN 38 DE 8 850 622 61 4 33 AS nu db Sample 977 ua Ande 0 7 Sample 998 Leap 1024 Ande CO Y Samples 942572 Samples 942572 DC Coupled A D wideband signal quality Fin 101MHz Fs 400 MHz onboard DC Coupled A D narrowband signal quality Fin 101 MHz Fs 400 MHz onboard PLL Channel 0 15 pF parallel cap at A D device inputs PLL Channel 0 15 pF parallel cap at A D device inputs Leap DC Coupled Signal Quality vs Input Level 80 70 SNR 1 SFDR Vp p DC Coupled A D signal quality vs input level Fin 70 1 MHz Fs 400 MHz onboard PLL Channel 0 15 pF parallel cap at A D device inputs X6 400M User s Manual 142 X6 400M XMC Module AC Coupled A
71. If you wish to rebuild the example programs you will have to install this software as well wxWidgets wxWidgets http www wxwidgets org DialogBlocks Anthemion http www anthemion co uk org dialogblocks Baseboard Package Installation Procedure Each baseboard installation for Linux consists of one or more package files containing self extracting packages of compressed files as listed in the table below Note that package version codes may vary from those listed in the table Each of these packages automatically extract files into the usr Innovative folder herein referred to as the Innovative root folder in the text that follows For example the X5 400 RPM extracts into usr Innovative X5 400 ver A symbolic link named x5 400 is then created pointing to the version directory to allow a single name to apply to any version that is in use X6 400M User s Manual 26 Installation on Linux Board Packages X5 400M Malibu LinuxPeriphLib ver rel 1586 rpm Board files and examples X5 210M X5 210M LinuxPeriphLib ver rel 1586 rpm Board files and examples X3 10M X3 10M LinuxPeriphLib ver rel i586 rpm Board files and examples X3 25M X3 25M LinuxPeriphLib ver rel i586 rpm Board files and examples X3 A4D4 X3 A4D4 LinuxPeriphLib ver rel 1586 rpm Board files and examples X3 SD X3 SD LinuxPeriphLib ver rel 1586 rpm Board files and examples X3 SDF X3 SDF LinuxPe
72. Innovative Integration X6 400M User s Manual X6 400M User s Manual The X6 400M User s Manual was prepared by the technical staff of Innovative Integration on April 19 2011 For further assistance contact Innovative Integration 2390 A Ward Ave Simi Valley California 93065 PH 805 578 4260 FAX 805 578 4225 email techsprt innovative dsp com Website www innovative dsp com This document is copyright 2011 by Innovative Integration All rights are reserved VSS Distributions A X6 400M Documentation Manual X6 400MMaster odm FXXXXXX Revision Date Author Notes 1 0 04 15 11 DPM Initial release Table of Contents A a a a a a a a E EIN 8 PASTOR Figure Sits ns oed voee E E E E kitcar tna eet ne dM Seen ad oae 10 Chapter LIO OCHO CORTE M 2 Real Time Solo fa os icsesscccvedsacsevesedessseasncssdencsinediescussescoulesccndsncneuexssesshespueseaxonossiedsuaseevesoasncasecsussceneonsenl 2 Rich lbieden rt ccc le WhatisXGA00M dida 13 W Hat aS MAIDEN o cane 13 Mhatis C Build uiscera et E db tai daca na as rore arvo vac QU a d Dees 13 Mat 15 Micros MS VG aetas ri dete A uaa QURE DNE UOTE aan TIERE pA Cue 15 What kinds of applications are possible with Innovative Integration hardware 15 y AS A I Innovative Integration Technical Support ccscccscscccssscscsssccccsscssssccssssscscssscssssssscssscsssscssseeees LO Innovative
73. MHz VBW 1 0 kHz Sweep 603 s 1001 pts Res BW 1 0 kHz CEE 100 1MHz Fs 1GSPS SENSE INT PNO Far Trig Free Run IFGain Low Atten 30 dB VBW 220 Hz Res BW 220 Hz Figure 24 AC coupled Intermodulation Distortion Dual tones at Fout 69 5 MHz and 70 1 MHz Fdac 200MHz X6 400M User s Manual ECO Figure 22 AC Coupled Output Signal Quality for Fout F igure 23 AC Coupled Output Signal Quality for F out SENSEINT AIGNAUTO D305254M A Avg Type Log Pwr TR Free Run Res BW 1 0 kHz Auto Man Video BW 1 0 kHz Auto Man VBW 3dB RBW 10 Auto Man Span 3dB RBW 106 Auto Man O E E E ERE Control Gaussian 3 dB Stop 500 0 MHz Sweep 603s 1001 pts Res BW 1 0 kHz VBW 1 0 kHz 160 1MHz Fs 1GSPS ALIGN AUTO 12 46 52 AM 14 2011 Avg Type Log Pwr TRACE TYPE Select Marker Span 10 00 MHz Sweep 249 s 1001 pts 149 X6 400M XMC Module Connectors Front Panel Connectors J5 J10 J5 J10 connectors are positioned on the front panel for analog input clock and trigger signals to be connected to the module Connector Type Number of Connections Connector Part Number Mating Connector Cable SMA 50 ohm 1 per signal Amphenol 901 143 Amphenol 901 9511 3 or equivalent Innovative part number 67048 SMA to BNC cable Connector Function J7 A D channel 0 J8 A
74. Max S N eB SNE SINAD 68 ENOB bis SFDR dB THD 2 48 6 53 684 14 3 90 848 Sample 120 Leap 1024 Andge ChO y Samples 929596 AC Coupled A D narrowband signal quality Fin 70 1 MHz Fs 400 MHz onboard PLL Channel 0 15 pF parallel cap at A D device inputs iG BinView dmelane projects x6 x6 400m handware revaltest data plot10 bdd a Marh BRA CO g O Tine Frequency Te Summary Server Magnitude vs Frequency 60K 80K 100K KHz 120K 140K 160K 180K 200K a BinView Ndmelane projects x6 x6 400m handware reva test data plot10 bdd a Marh BRA CO d O Tine Frequency Tex Summary Server Magnitude vs Frequency 100K KHz 101K Mas S N dB 85 0 Sample WEN Leap 1024 S N eB 728 SINAD 48 ENDB bis SFDR d8 708 11 4 832 THD 2 48 0 005860 84 698 Anaze Ch Y Samples 949892 X6 400M User s Manual Mas S N dB 85 0 S N dB 721 SINAD 48 ENDB bis SFDR d8 703 11 4 383 THD e a 0 005993 84 48 120 1024 Sample cho y Frequency domsin data display Leap Analyze Samples 949892 X6 400M XMC Module AC Coupled A D wideband signal quality Fin 101MHz Fs 400 MHz onboard PLL Channel 0 15 pF parallel cap at A D device inputs AC Coupled A D narrowband signal quality Fin 101 MHz Fs 400 MHz onboard PLL Channel 0 15 pF parallel cap at A D device inputs E BinView Wdmelane projects x6 x6 400m hardware reva t
75. R Vet PRA NR 156 Figure 28 PMC JNI Connector Schematics iste eire pre tras toria 159 Figure 29 PMC JN Connector SChematig a te iet URGERE erg t ires 162 Figure 30 PMC JNA4 Connector SCHOMANIC su osi eid tom n MSS RO PORC Fa esed x cr a vr rd 165 Figure 31 X6 400M JP3 Orientation board face view nennen 167 Figure 32 X6 400M JP3 Orientation board top edge view 167 Figure 33 X6 400M Mechanicals Top View Rev As ioco tore a neidd 169 Figure 34 X6 400M Mechanicals Bottom View Rev Au cceccccsscesseeeseceeeeeseeeeeeceseeeeeeseeeneeeeeeneas 169 Chapter 1 Introduction Real Time Solutions Thank you for choosing Innovative Integration we appreciate your business Since 1988 Innovative Integration has grown to become one of the world s leading suppliers of DSP and data acquisition solutions Innovative offers a product portfolio unrivaled in its depth and its range of performance and I O capabilities Whether you are seeking a simple DSP development platform or a complex multiprocessor multichannel data acquisition system Innovative Integration has the solution To enhance your productivity our hardware products are supported by comprehensive software libraries and device drivers providing optimal performance and maximum portability Innovative Integration s products employ the latest digital signal processor technology thereby providing you the competitive edge so critical in today s global markets Using our powerful
76. RAD Studio 2007 2009 Embarcadero Rad Studio 2010 or QtCreator installed on your system depending on which of these IDEs you plan to use for Host development If you are planning on using these environments it is imperative that they are tested and known operational before proceeding with the library installation If these items are not installed prior to running the Innovative Integration install the installation program will not permit installation of the associated development libraries However drivers and DLLs may be installed to facilitate field deployment You must have Administrator Privileges to install and run the software hardware onto your system refer to the Windows documentation for details on how to get these privileges X6 400M User s Manual 17 Windows Installation Starting the Installation To begin the installation start Windows Shut down all running programs and disable anti virus software Insert the installation DVD If Autostart is enabled on your system the install program will launch If the DVD does not Autostart click on Start Run Enter the path to the Setup bat program located at the root of your DVD ROM drive i e E Setup bat and click OK to launch the setup program SETUP BAT detects if the OS is 64 bit or 32 bit and runs the appropriate installation for each environment It is important that this script be run to launch an install When installing on a Vista OS the dialog below may pop up
77. SPS X6 400M User s Manual DC Coupled DAC Output Amplitude vs Fout 5 Amplitude Variation dB IN Power normalized to 5 1 MHz 10 100 1000 Fout MHz Figure 12 Frequency Response for 5 MHz to 500 MHz span DC Coupled Output Fs 500 MSPS 145 X6 400M XMC Module DC Coupled Signal Quality vs Fout 90 4 80 70 60 e 50 ES SNR dB a SFDR dB THD dB dB un 40 30 20 10 MHz Figure 13 DC Coupled Output Signal Quality vs Fout Fs 500 MSPS TiAgilent Spectrum Analyzer Swept SA Lone RBW 1 0 kHz T Agilent Spectrum Analyzer Swept SA Eye c SES TL ACIGNAUTO 07 35 20 8M Apr OB 2011 Avg Type Log Pur Trace IEEE Tee Peak Search Start 0 Hz Stop 500 0 MHz Res BW 1 0 kHz VBW 1 0 kHz Sweep 603 s 1001 pts Start 0 Hz Stop 500 0 MHz Res BW 1 0 kHz VBW 1 0 kHz Sweep 603 s 1001 pts 5 Start SE m TA E RL DB 712m Figure 14 DC Coupled Output Signal Quality for Fout Figure 15 DC Coupled Output Signal Quality for Fout 70 1MHz Fs 1GSPS 100 1MHz Fs 1GSPS CE tm Tiagi Ana X6 400M User s Manual 146 X6 400M XMC Module TlAgilent Spectrum Analyzer Swept SA me Marker 1 160 000000000 MHz Input RF PNO Fa IFGain L Stop 500 0 MHz VBW 1 0 kHz Sweep 603 s 1001 pts 4 Start s 8m TI Agi amp ADE 750 Figure 16 DC Coupled Output Sig
78. Signal Direction DGND P 3 3V P DGND P AD29 vO AD26 vO 3 3V P AD23 vO AD20 vO DGND P CBE2 vO 3 3V P STOP vO DGND P SERR O DGND P ADI3 vO ADIO vO 3 3V P DGND P 3 3V P 160 X6 400M XMC Module PMC JN4 Connector JN4 implements digital IO connections Figure 30 PMC JN4 Connector Schematic X6 400M User s Manual 161 X6 400M XMC Module Table 38 X6 JN2 Connector Pinout Signal Direction DIO PO yo DIO NO yo DIO P2 yo DIO N2 yo DIO P4 yo DIO N4 yo DIO P6 yo DIO N6 yo DIO P8 yo DIO N8 yo DIO_P10 Vo DIO_N10 yo DIO P12 yo DIO N12 yo DIO P14 yo DIO_N14 yo DIO_P16 yo DIO N16 yo DIO P18 yo DIO N18 yo DIO P20 yo DIO N20 yo DIO P22 yo DIO N22 yo DIO P24 yo DIO N24 yo DIO P26 yo DIO N26 yo DIO P28 yo DIO N28 yo DIO P30 yo X6 400M User s Manual Pin 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 Pin 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 Signal Direction DIO P1 vO DIO N1 vO DIO_P3 vO DIO_N3 vO DIO P5 vO DIO N5 vO DIO_P7 vO DIO_N7 vO DIO_P9 vO DIO_N9 vO DIO P11 vO DIO N11 vO DIO_P13 vO DIO N13 vO DIO P15
79. Start Synchronize Module OnAfterStreamStop SetEvent this amp ApplicationIo HandleAfterStreamStop Module OnAfterStreamStop Synchronize HandleBeforeStreamStart HandleA fterStreamStart and HandleAfterStreamStop handle events issued on before stream start after stream start and after stream stop respectively These handlers could be designed to perform multiple tasks as event occurs including displaying messages for user These events are tagged as Synchronized so Malibu will marshal the execution of the handlers for these events into the main thread context allowing the handlers to perform user interface operations The hooking of alerts are factored into a method within the Module object since different modules may provide different alert capabilities Alerts Module HookAlerts This code attaches alert processing event handlers to their corresponding events Alerts are packets that the module generates and sends to the Host as packets containing out of band information concerning the state of the module For instance if the X6 400M User s Manual 75 Writing Custom Applications analog inputs were subjected to an input over range an alert packet would be sent to the Host interspersed into the data stream indicating the condition This information can be acted upon immediately or simply logged along with analog data for subsequent post analysis Configure Stream Event Handlers Stream OnVeloDataAva
80. V P 31 32 ADIT yo FRAME yo 33 34 DGND P DGND P 35 36 IRDY yo DEVSEL yo 37 38 5V P DGND P 39 40 LOCK yo E 41 42 PAR yo 43 44 DGND P i 45 46 ADIS vO ADI2 yo 47 48 ADII yo AD9 yo 49 50 5V P DGND P 51 52 CBEO yo AD6 yo 53 54 ADS yo AD4 yo 55 56 DGND yo 57 58 AD3 yo AD2 yo 59 60 ADI yo ADO yo 61 62 5V P DGND 63 64 a PMC JN2 Connector JN2 implements part of the PMC PCI interface as well as power inputs X6 400M User s Manual 158 X6 400M XMC Module Figure 29 PMC JN2 Connector Schematic See PCI specification for detailed pin descriptions Table 37 X6 JN2 Connector Pinout Signal Direction 12V P Direction X6 400M User s Manual 159 X6 400M XMC Module Signal Direction DGND P RST I 3 3V P AD30 yo AD24 yo IDSEL I DGND P 3 3V P AD118 yo ADI6 yo DGND P TRDY yo DGND P PERR O 3 3V P CBE1 yo ADI4 yo M66EN O AD8 yo AD7 yo 3 3V P DGND P DGND P X6 400M User s Manual Pin 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 Pin 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64
81. X6 modules but may defined in VITA42 and VITA42 3 specifications Note LED_N FAN and FAN_TACH are special purpose pins that support Innovative adapter card functions These are reserved pins on the VITA42 3 specification X6 400M User s Manual 152 X6 400M XMC Module Signal Description PETOpx PETOnx PCI Express Tx PEROpx PEROnx PCI Express Rx PEX REFCLK PCI Express reference clock 100 MHz MRSTI Master Reset Input active low MRSTO Master Reset Output active low GAO Geographic Address 0 GA1 Geographic Address 1 GA2 Geographic Address 2 MBIST Built in Self Test active low MPRESENT Present active low MSDA PCI Express Serial ROM data MSCL PCI Express Serial ROM clock MVMRO PCI Express Serial ROM write enable WAKE Wake indicator to upstream device active low ROOT Root device active low LED N Host LED control output active low May be used with eInstruments FAN Host fan control May be used with eInstruments FAN TACH Host fan tachometer feedback May be used with eInstruments Table 33 P15 Signal Descriptions XMC P16 Connector P16 is the XMC secondary connector to the host and is used for digital IO data link and triggering functions X6 400M User s Manual 153 X6 400M XMC Module XMC pin header 0 05 in pin spacing vertical mount Number of Connections 114 arranged as 6 rows of 19 pins eac
82. a iiir e bases sosesko deseta saos ass iproseso besas e sosa tsss issis sasa 113 Output Range and Conversion Codes eesseesseessoesssosssoessoesssoessoesssosesoessoessoosssoesssoessssssssesssssssssse 114 DAC O tp t Loads Me 115 DAC Data Modes and Special Features 4 eee e eee e eee eee ee eee een setenta netta as eee tna sess eese ena asse eoe 115 AFE DAC SPI Control MR AFE DAC SPI CTRL x 890 ssssssssssseseseeeeeeene 117 AFE DAC SPI Status MR AFE DAC SPI STAT x 80leooocconnccconnconnnconcncnoonncnnononcnccnanonannnos 117 Sample Rate Generation and Clocking Controls eee eee e eee e eee e ee eee eee enne nee eee tnn asse eoe 118 External Clock Refer nce Input escisiones coran 119 Sample Rate occi M ssis ose 120 Setting the Sample Rate in the SNAP Example 4 eeeeeeee eene seen eene netta aset asse tta sse ens sess eno 120 Controlling the ul e Boe uc 121 How To Set the Sample Rate Generator to a Specific Frequency eeeeeeeeeeeeee eene 121 Using An External PLL Reference sicccisisesestscscseceitssvesastsssesconssvesuissccedssensvdsesessveneveneuassouassestapevenssiies 122 Using An External Clock for Sample Cl0cK ssccsssscssssccssssecscccesscsccsscsecsscsscsccssesscsssscsesoseees 124 External Clock Requirements ccssvscsassiecassccassssexsancsdsncsovedocnaadedeavosesaseso
83. accuracy and noise level INPUT MHz 100 16 BITS 90 N 14 BITS 80 a 2 r4 Z 12 BITS 70 10 BITS 60 50 3 10 1000 E Table 13 Effect of Sample Clock Jitter on Digitizing Accuracy Courtesy Analog Devices Inc The PLL reference clock multiplexer device also adds jitter to the input reference clock This noise must be root sum squared RSS with the reference clock jitter Parameter Worst Additive Jitter 100 fs in 10kHz to 20MHz range Delay 450 ps max Table 14 External PLL Reference Additive Jitter and Delay The external clock must also be stable within the tracking range of the PLL VCXO This requirement limits the amount of low frequency wander and drift that external clock can have without making the PLL lose lock External Reference Clock Parameter Limit Frequency Stability 3000 PPM Jitter 200 fs RMS recommended for analog input signals with 500 MHz bandwidth X6 400M User s Manual 123 X6 400M XMC Module Table 15 External PLL Reference Requirements The following diagram shows the clock path when an external reference is used The reference clock multiplexer is configured to select the external clock input as the reference to the CDCE72010 device J6 Ref CIk Input ADC Ref To FPGA DAC Ref To FPGA DAC CLK To FPGA To DAC To ADCO 1 To ADC2 3 LITT 12C Port 12C Port To MGT PLL
84. ah to Ne tas os 60 Table 27 X6 Power Supply Control sas ener arro rro rd nd tas 61 Table 28 299 DBD Indie alr sas A RES 62 Table 29 X6JTAG Scan Pat uote edo bota b ean ded tf o C fb Seo sd 62 Table 30 XMC Adapters and HO A tere gie o SI vel ondes 64 Table 31 X6 FPGA Logic Image Sizes and Configuration Times eee 66 Table 32 Logic Image Selection Jumper JP D tetti rrr HB Ced e eb eren eerie oae hoe 66 Table 33 Development Tools for the Windows Snap Example 69 Table 34 X6 Velocia Velo Packet Flea Gti s oce e ore o Oe axe Cbr To d dia VER Une 98 Table 35 Velocia Header Word oou a toby Ie NEST taba sac 99 Table 36 Vita Packet Formal e pas s ket puis mda Ai ia 99 Table 37 Timestamp Integer Seconds Options eee tree eene etel ecce eres 101 Table 38 Timestamp Fractional Seconds Options essen 101 Table 39 Padding Example ta cebat dea utes so depo ut ede dune o ie d Apa bc des db edd us 103 Table 40 Maximum Padding for X6 Boards 4e eade erar tren didas 103 Table 41 X6 400M A D Heat ire ory caressa ie ee uti ee cu erbe SED ERIS YET ES SPIEREYEINCE UR cena 110 Table 42 A C Coupled A D Conversion Coding i oa eet reete A Yee ee Uu Ges ee ped 111 Table 43 DC Coupled A D Conversion Coding sess 112 Table 44 X6 400M DAC Features eeeesesseseesssssesssssssesesssssssssssssssesesssesecceseeuauescceseuaunescss 113 Table 1 DC Coupled DAC Conversion Coding nennen nennen 115
85. andler When the output stream needs additional data the Data Required event is signalled The Wave application uses this call to send the template block to the output via the SendOneBlock method void Applicationlo HandleDataRequired PacketStreamDataEvent Event SendOneBlock Event Sender const int HeaderTagValuePostPacketizer 0x00000000 const int HeaderTagValueOriginal HeaderTagValuePostPacketizer void ApplicationIo SendOneBlock PacketStream PS ShortDG Packet _DG WaveformPacket X6 400M User s Manual 88 Writing Custom Applications Calculate transfer rate in kB s double Period Time Differential if Period FBlockRate Packet DG SizeInBytes Period 1 0e6 i No matter what channels are enabled we have one packet type to send here PS gt Send 0 WaveformPacket FBlockCount For speed the packet is created on the first call only After that the same data wave is sent to all channels Note that it is allowed to send more than one output packet per notification If no packets are sent however it is possible that further notifications may stop until the application starts sending data again This decoupling of notification from sending allows different models of data generation to exist in Malibu An application may send packets asynchronously and not handle notifications at all FillWaveformBuffer The Application section of the Malibu library has a waveform ge
86. are provided for programming this device Module Rated Programmed Programmed Default Alert Default Maximum Notes Environm Operating Alert Critical Threshold Critical Allowable C ent Rating Temperature Threshold C Threshold C O Threshold C C LO 0 to 50C 50 85 85 110 85 Commercial temperature device L1 40 to 85 65 100 85 110 100 Industrial temperature FPGA L2 20 to 65 65 100 85 110 100 Industrial temperature FPGA L3 40 to 70 65 100 85 110 100 Industrial temperature FPGA L4 40 to 85 65 100 85 110 100 Industrial temperature FPGA Table 23 X6 Temperature Threshold and Limits X6 400M User s Manual 54 About the X6 XMC Modules When the alert threshold is e exceeded the monitor alert signal to the FPGA is fired This temperature alert is passed to the system through the packet system Host software is therefore notified of the temperature alert and can take appropriate action When the critical threshold is exceeded the temperature module disables power In the event of an over temperature condition the logic memory interface and analog power supplies are disabled shutting down power to most of the X6 module The host system must re enable power to start the module again In the event that the temperature threshold must be ignored the software can reprogram temperature monitor to set the threshold to maximum 255C Chapter 28 Temperature Readout The
87. are routed to the DAC interface in the AFE X6 400M User s Manual 131 X6 400M XMC Module The Board Basics and Host Communications chapters of this manual discuss the use of the packet data system used on the X6 module family The X6 400M module FrameWork Logic connects the data from A D interface to the packet system by forming the data into 32 bit words of consecutive enabled channels Status indicators for the A Ds are integrated with the alert log to provide host notifications of important events for monitoring the data acquisition process some of which are unique to the X6 400M The complete description of the FrameWork Logic is provided in the X6 400M FrameWork Logic User Guide including the memory mapping register definitions and functional behavior This logic is about 5 of the available logic in the application FPGA Virtex6 LX240T SX315T device In many custom applications unused logic functions can be deleted to free up gates for the new application Alert Log Overview X6 modules have an Alert Log that can be used to monitor the data acquisition process and other significant events The application can use Alerts to create a time history of the data acquisition process that shows when important events occurred and mark the data stream to correlate system events to the data This provides a precision timed log of all of the important events that occurred during the acquisition and playback for interpretation and correlation
88. aximum Allowable Noise Derived from Supplies these Range V Voltage V Allowed Devices Current A 3 3V 3 125 to 3 3V 15 20 mV Direct connect to the PCIe FPGA clock 3 465 host through P15 controls and analog power supplies VPWR 4 5 to 14V 12V 4 100 mV Direct connect to the PCIe FPGA host through P16 VPWR pins Table 25 X6 400M Power Supply Requirements The allowable noise allows the module to function but may not give the best performance Spectral content of the noise may affect analog performance Power Consumption The X6 400M requires the following power for typical operation with when using the FrameWork Logic This typical number assumes a 200 MHz system clock rate and 160 MSPS A D sample rates for the application logic Voltage Maximum Allowed Current Typical Current Required A Typical Power W A 3 3V 15 VPWR 12V 4 Total Power Table 26 X6 400M Baseline Power Consumption This power consumption is the baseline power The baseline configuration uses a modified version of the FrameWork Logic that has all 4 analog channels sampling at 400 MSPS and streaming data to the host PCIe using x4 lanes There are no Aurora ports 2 DRAM devices are powered down unused clocks are powered down This baseline power consumption is the minimum functionality to use the card as a data acquisition card Enabling other features will consume more power provided for
89. be observed X6 RX 3W to insure analog performance Analog Sample Clock 1 5W The sample clock PLL and VCXO may be powered down The PLL is most of this power consumption and can be powered down through the PLL control registers Table 26 X6 Power Control Features Another major factor in power consumption is the FPGA clock rate and size of the FPGA design Designers should use the lowest practical clock rate to save power The power savings can be dramatic for large designs with many Watts saved from one design to another The Xilinx FPGA design tools include Power Analyzer which gives a detailed report for each FPGA design This tool should be used to optimize the design for lower power by identifying the portions of the design that consume the most power X6 400M User s Manual 59 About the X6 XMC Modules Chapter 32 Power Supply Controls Individual power enables are provided on X6 modules that can selectively power down portions of the card not in use Each module has unique power supplies for its IO and special functions that must be considered so that core functions required for the module to wake up from low power mode Both channels on or off only to 20mW in power down Does not include output amp for DC coupled version Module Power Affected Subsystem Subsystem Power Consumption Notes Controls X6 RX 1 1V DDC ASIC Up to SW DDR_VTT LPDDR DRAM banks 1W Affe
90. c to a full replacement host user interface The applets provided with this release are described in this chapter Shortcuts to these utilities are installed in Windows by the installation To invoke any of these utilities go to the Start Menu Programs lt lt Baseboard Name gt gt and double click the shortcut for the program you are interested in running X6 400M User s Manual 103 Applets Common Applets Registration Utility NewUser exe Some of the Host applets provided in the Developers Package are keyed to allow Innovative to obtain end user contact information These utilities allow unrestricted use during a 20 day trial period after which you are required to register your package with Innovative After the trial period operation will be disallowed until the unlock code provided as part of the registration is entered into the applet After using the NewUser exe applet to provide Innovative Integration with your registration information you will receive The unlock code necessary for unrestricted use of the Host applets A WSC tech support service code enabling free software maintenance downloads of development kit software and telephone technical hot line support for a one year period X6 400M User s Manual Registration Information User 2 Help E Register Now Ok r Name ri IB Last Henderson r Emait Address Telephone _ County Code A
91. calibration values are used by the logic to correct the analog errors on the A D inputs and DAC outputs Each channel has offset and gain calibration coefficients that are loaded by the software at initialization All factory calibrations limit gain correction to 5 and offset to 2 mV All test voltages are measured as part of the procedure with NIST traceable equipment Production calibration is performed at room temperature 24C with the module operating temperature at about 65C Under normal circumstances the calibration is accurate for one year For recalibration the module can be sent to Innovative or re calibrated using a similar test procedure Updating the Calibration Coefficients A software applet for writing the calibration coefficients to the EEPROM is provided EEPROM exe New coefficients are simply typed into the offset and gain field for each channel Calibration coefficients for gain should not be outside the range of 0 9 to 1 1 and offset should not be outside the range of 3000 counts for the A Ds If the calculated coefficients are larger than this they are either wrong or the channel is damaged Using the X6 400M Where to start The best place to start with the X6 400M module is to install the module and use the SNAP example to acquire some data This program lets you log data from the module and use all the features like triggering clocks alerts and calibration ROM You can use this program to acquire
92. cation The conduction cooling method allows the module heat to be conducted to the chassis X6 400M User s Manual 57 About the X6 XMC Modules Cooling Area 1 Io EEE m EL ul 205 E E Nu O Ai NE uw Op me 13 ee esu EN m Bo o Tel I 19 f A Em caca OU f CiU gm NR e E Cooling n Onn e n JE Li e Area 3 TUE Cooling Area 2 Figure 26 X6 Conduction Cooling Thermal Connection Areas Hardware Description II P N Notes Rear cooling bar Aluminum bar with M2 screw holes 10mm 61122 For cooling area 3 mounting height for X3 X6 modules Side cooling bar Aluminum bar with M2 5 screw holes 61121 For cooling areas 1 amp 2 10mm mounting height for X5 X6 modules Screws M2xS pan head 63167 10 total per module Screws M2 5x5 pan head 63130 12 total per module Table 25 X6 Conduction Cooling Hardware Chapter 30 X6 FPGA Heat Spreader The X6 cards have a heat spreader for the FPGA that spreads the heat across a large surface area and also conducts heat to the thermal plane This heat spreader helps to conduct heat from the FPGA to the therma
93. creating a new application with File New Project with Widows Forms Application New Project Project types Templates Visual C Visual Studio installed templates ATL CLR ASP NET Web Service class Library General BR Console Application DECR Empty Project MFC ESQ Server Project A Windows Forms Application Smart Device A Windows Forms Control Library windows Service Win32 Other Languages My Templates Other Project Types Search Online Templates A project For creating an application with a Windows user interface Enter name Location C isome Folder v Solution Create new Solution Create directory For solution Add to Source Control X6 400M User s Manual 94 Developing Host Applications Project Properties Alt F7 Configuration Properties E Project Defaults Configuration Type Application exe Use of MFC Use Standard Windows Libraries Use of ATL Not Using ATL Minimize CRT Use in ATL No Character Set Use Unicode Character Set Common Language Runtime support Common Language Runtime Support clr Whole Program Optimization No Whole Program Optimization C General Additional Include Directories Malibu PlotLab Include for graph scope display Code Generation Run Time Library Multi threaded Debug DLL Mda Precompiled Headers Create Use Precompile Headers Not Using Precompiled Headers Linker Additional Library
94. cted The trigger source is level sensitive for the continuous mode or edge triggered for the framed mode triggering The A D and DAC channels use the same external trigger in the standard FrameWork Logic The Malibu software tools provide trigger source configuration and methods for software triggering re triggering in framed mode and trigger mode controls Trigger Source Connector Pin Signal Standard Notes Front Panel J5 center pin AC coupled DC input 20V max Vin 100 mV min 1 5V max Termination 50 ohms H_TRIGO P16 pin A19 LVCMOS2 5 DC coupled Vin 3 6V max 3V min 13 3K termination to ground H TRIGI P16 pin B19 LVCMOS2 5 DC coupled Vin 3 6V max 3V min 13 3K termination to ground H PPS P16 pin D19 LVCMOS2 5 DC coupled Vin 3 6V max 3V min 13 3K termination to ground Table 20 X6 400M Trigger Sources Front Panel External Trigger Input Requirements The front panel external trigger input has the following requirements This signal is an AC coupled single ended input on connector J6 X6 400M User s Manual 128 X6 400M XMC Module a 200 IU nc SS Input a IM z 1000 MHz patios dP mS Table 21 External Trigger Input Requirements Framed Trigger Mode Framed trigger mode is useful for collecting data sets of a fixed size each time the input trigger is fired In framed mode the trigger goes false once the programm
95. cts all DRAM banks No DRAM can be used if this is off 1 2V LPDDR DRAM banks and Up to 2W This power is also cascaded to DDC the 1 1V supply so if it is off then the 1 1 V must be off also GTX All GTX s used for PCIe 2W These supplies can only be turned PCI and P16 GTX off if no GTX are required such interfaces as in standalone operation A D A D channels one enable 750mW per channel pair Allow 1s warm up time after per channel pair 0 1 and power up for stabilization 2 3 X6 RX DDR_VTT LPDDR DRAM banks 1W 1 2V LPDDR DRAM banks and Up to2W This power is also cascaded to DDC the 1 1V supply so if it is off then the 1 1V must be off also GTX All GTX s used for PCIe 2W These supplies can only be turned PCI and P16 GTX off if no GTX are required such interfaces as in standalone operation A D A D channels one enable 2 5W per channel Dissipates 350 Allow 1s warm up time after per channel mW per channel in power down power up for stabilization mode Does not include output amp for DC coupled version D A D A channels one enable 1 4W for both channels Reduces Allow 1s warm up time after power up for stabilization Table 27 X6 Power Supply Controls These power supply control bits are accessed through writes to the CPLD control registers Consult technical support for information on use of this feature X6 400M User s Manual About the X6 XMC Modules Led Indicators The X6 modules have two LEDs for use by a
96. d Receive RX lanes to the X6 must be AC coupled at the transmitter Transmit lanes are AC coupled on the X6 IO standard is CML X6 400M User s Manual 48 About the X6 XMC Modules Parameter Value Notes Differential pk to pk Input Voltage 175 mV min AC coupled externally 0 3V min 2 2V max 2000 mV max Absolute Input Voltage 400 mV min DC coupled Common Mode Input Voltage 800mV Typical Differential pk to pk Output Voltage 1000 mV max Programmed to maximum swing output Common Mode Output Voltage 800mV typical 1000mV max Lock Time 1 ms Max Input common mode voltage 1 2V typical For differential input voltage 350 mV Input Differential Voltage 2000mV max 800mV typ 210mV min 100 ohm differential termination Differential Resistance 90 to 120 ohms 100 ohms nominal input and output Table 19 GTX Signal Electrical Characteristics GTX Reference Clocks The X6 ports on P16 have an on card programmable reference clock PLL This PLL is capable of generating a wide range of frequencies to support many standards The reference for the PLL a 10 MHz 1ppm 0 28 ppm optional reference clock This very stable reference allows the GTX to meet stability requirements for many communications standards such as Serial Rapid IO Ethernet and SONET Parameter Units Notes Frequency Range 0 16 to 350 MHz LVDS Tuning 1 ppm Resolution Stability 1 ppm U
97. d as 100 ohm differential pairs supporting LVDS single ended LVCMOS2 5 is also supported X6 400M User s Manual About the X6 XMC Modules Figure 19 X6 Digital IO Block Diagram Digital IO Connections The digital bits are configured at the factory to use either to P16 or JN4 The default configuration is to use JN4 for the digital IO connections Pinouts for each connector or shown in the hardware section of this manual DIO Pairs Connctor Notes 0 18 JN4 factory default All pairs are connected to JN4 as a factory default P16 optional configuration Optional configuration removes jumpers for P16 19 31 JN4 Table 14 DIO Connector Configurations Chapter 18 Digital IO Electrical Characteristics The digital IO bits are usable as either LVDS or LVCMOS 2 5 This IO standard is chosen in the logic design The FrameWork Logic for X6 uses LVDS for all digital IO connections Caution Voltages above 2 6V will damage the Virtex 6 device Do NOT connect 3 3V or 5V logic directly to the digital pins as damage may occur LVCMOS 2 5V Pins Warning the LVCMOS DIO pins are NOT 3 3 or 5V compatible Input voltage must not exceed 2 8V during normal operation Undershoot and overshoot must be limited see the Xilinx Virtex 6 User Guide for details Parameter Value Notes Input Voltage Max 2 8V Exceeding these will damage Min 0 3V the FPGA Output Voltage 1 gt 2 1V 0 lt 0 4V Output
98. dding 1 Datan Data n 1 Data n 2 Padding 5 Padding 4 Padding 3 Padding 2 Padding 9 Padding 8 Padding 7 Padding 6 Trailer Padding Field Value 9 The above table shows an example of padding The logic had accumulated the data in grey when the trigger was disabled seven bytes of data The packet can not be sent because the data would not be properly aligned The logic therefore adds the nine byte remainder to the packet as padding and loads the value 9 into the padding field of the trailer Analysis routines that check the padding value will properly limit themselves to reading the valid data and ignore the padding bytes Table 40 Maximum Padding for X6 Boards Source FIFO parallel samples Event size bits Maximum Padding bytes 1x16 RX 16 14 2x16 400M 32 12 4x8 GSPS 32 12 8x8 GSPS DES 64 8 The above table shows the maximum expected padding value for a particular X6 board The RX which has one 16 bit sample per packet for each period could possibly have to pad 14 of 16 bytes in a 4 word block Devices which send more data per sample period will have smaller maximum padding values X6 400M User s Manual 102 Applets Chapter 61 Applets The software release for a baseboard contains programs in addition to the example projects These are collectively called applets They provide a variety of services ranging from post analysis of acquired data to loading programs and logi
99. dedicated hardware for real time data collection and signal processing is needed This is precisely the focus of our baseboards a high performance state of the art dedicated digital signal processor coupled with real time data I O capable of flowing data via a 64 bit PCI bus interface The hardware is really only half the story The other half is the Malibu software tool set which uses state of the art software techniques to bring our baseboards to life in the Windows environment These software tools allow you to create applications for your baseboard that encompass the whole job from high speed data acquisition to the user interface Finding detailed information on Malibu Information on Malibu is available in a variety of forms e Data Sheet http www innovative dsp com products malibu htm e On line Help nnovative Integration Technical Support nnovative Integration Web Site www innovative dsp com Online Help Help for Malibu is provided in a single file Malibu chm which is installed in the Innovative Documentation folder during the default installation It provides detailed information about the components contained in Malibu their Properties Methods X6 400M User s Manual 15 Introduction Events and usage examples An equivalent version of this help file in HTML help format is also available online at http www innovative dsp com support onlinehelp Malibu Innovative Integration Technical Support Innova
100. demonstrates the triggering modes and controls for the X6 400M The trigger controls on the SETUP tab select the trigger source mode and decimation Figure 8 X6 400M SNAP Example Triggering Controls X6 400M User s Manual 129 X6 400M XMC Module X6 400M PCIe Module Snap Example loj x Configure Setup Steam EEProm Debug TabSheetl Reference Clock Ext Clock Src y Communications Source Source Alerts C Ext Int C Ex ing P16 Velo Pkt Size Timestamp l 10000 Software Frequency Frequency p 100 MHz 4000 mhe is Trigger Source Est Trigger Srey Frame Mode Type Software Size Unframed C Level 0x400 loe amed e Edge L IL Test Counter Decimation Enable Enable Saw Paced Eventi Actual PLL Frequency 4e 08 Analog 140 started Stream Mode started Analog 1 0 Stopped Stream Mode Stopped automatically Elasped 0 733 Starting Post Processing Ending Post Processing The trigger source is either external or software The front panel external trigger input is on connector J5 In external trigger mode the data collection begins on rising edges If you are in framed mode then the number of points collected is set by the Frame Size number you enter In unframed mode the data is collected until t
101. e differs from the PCI interface in both implementation and performance The PCI Express interface directly communicates from the host bus to the FPGA using high speed serial lanes GTX Each lane consists of one transmit and one receive wire so that the interface is full duplex The lanes can be used in x1 x4 or x8 configurations as negotiated by the host system at boot up as part of the port initialization The interface always seeks the highest performance first starting with x8 lanes at 2 5 Gbps Gen1 or 5GBs for Gen2 If the host machine cannot support this interface the highest possible rate is negotiated degenerating to a x1 2 5 Gbps interface at worst RESETn Packet Out x8 Lanes Packet In Wishbone SOC 32b Figure 16 PCI Express Interface Block Diagram Chapter 10 PCI Interface The PCI bus is a 32 bit 66MHz interface compatible with most PMC sites The X6 uses a bridge from the PCI bus to the FPGA that translates the PCI bus to a single lane x1 PCI Express interface The bridge device Pericom PI7C9X111SLBFDE is non intelligent and simply provides connectivity to the FPGA In this way the PCI and PCI Express interfaces are symmetric to the FPGA design both appearing as PCI Express to the designer X6 400M User s Manual 39 About the X6 XMC Modules RESETn WAKE PRESENTn Packet Out cket In 32b 66MHz Fam Wishbone SOC 32b Figure 17 PCI Interface Block Diagram Chapter 11 Configuring The
102. e status register DAC SPI data is read back using this register as well as status information Bits Field R W Default Description Modules 7 0 spi rdata R SPI read data 400M 23 8 24 spi sdo R DAC status 400M 29 25 30 spi rdy R SPI is ready for use 400M 31 spi rdata valid R SPI read data is valid 400M Table 6 X6 AFE DAC SPI Status Register Table 7 DAC 0 amp 1 SPI Interface 0x806 0x808 r w Some of the registers in the DAC5682Z have multiple functions defined by the bits so a read modify write procedure is used For example CONFIG2 register controls the CMIXO and 1 modes the FIR2x4x mode and data format mode Scripts can further automate this configuration process by performing a series of accesses that the WAVE example program can play before start to configure the DAC5682Z The script language provides reads writes and waits X6 400M User s Manual X6 400M XMC Module Command Syntax Example Store anl 0x1 OxFF Store X FF to register 1 Fetch al 0x5 1 Fetch from register 5 Displays in console window on example application software Wait n ms 10 ms Wait for 10 ms Table 8 Script Commands Here is a script example to write to DAC SPI register 0x890 0x000020E4 1 This access writes to DAC register 2 a value of 0xE4 This would configure the DAC for 2 s complement data dual DACs 4x interpolation high pass m
103. ecialized clock circuitry The sample clocks fr both A D and DAC are copied to the FPGA with separate copies go to each device Programmable controls for the clock circuitry are mapped to the FPGA accessed in the Framework Logic by the host Custom FPGA implementations can control the clocks without host involvement by commandeering these interfaces External Clock Reference Input The external clock reference input at connector J6 is on the front panel and has the following electrical requirements for the clock input Characteristic Description Connector J4 Front Panel Input Impedance 50 ohm Input Coupling AC X6 400M User s Manual 119 X6 400M XMC Module Input Connector SMA Minimum Input Amplitude 200mVp p 20 8 dBm Maximum Input Amplitude 2 0Vp p 0 8 dBm DC input range 20V max Maximum Frequency 500 MHz Input waveform Sine or square Table 9 Input Clock Reference Electrical Specifications This signal can be used as either a sample clock or as a PLL reference Functions in the Malibu library provide controls for selecting the clock and reference sources Sample Rate Generation The PLL is used to generate sample clocks on the X6 400M using either an on card programmable reference clock or an external reference input Parameter Specification PLL Clock Range 1 to 1417 MHz PLL Output Clock Resolution 100kHz PLL Output Jitter lt 200 fs RMS
104. ected Log Stream not connected Open the boards return Set up Parameters for Data Streaming First have UI get settings into our settings store Ul gt GetSettings Before we start streaming all necessary parameters must be checked and loaded into option object UI gt GetSettings loads the settings information from the UI controls into the Settings object within the Applicationlo class if Settings SampleRate 1 e6 Module Input Info MaxRate Log Sample rate too high StopStreaming UI gt AfterStreamAutoStop return We insure that the sample rate specified by the GUI is within the capabilities of the module if Settings Framed Granularity is firmware limitation int framesize Module Input Info TriggerFrameGranularity o if Settings FrameSize framesize std stringstream msg msg lt lt Error Frame count must be a multiple of lt lt framesize Log msg str UI gt AfterStreamAutoStop return X6 400M User s Manual 78 Writing Custom Applications The module supports both framed and continuous triggering In framed mode each trigger event whether external or software initiated results in the acquisition of a fixed number of samples In continuous mode data flow continues whenever the trigger is active and pauses while the trigger is inactive The code above issues a warning if the trigger mode is framed
105. ed number of points N have been collected Start triggers that occur during a frame trigger are ignored The maximum number of points per frame is 16 777 216 2 24 points while the minimum number of points is 8 Frame size must be a multiple of 8 on the X6 400M Data flow to the host is independent of the framed triggering mode In most cases packet sizes to the host are selected to be integer sub multiples of the frame size to allow the entire data set to flow to the host That way the entire data frame can be moved immediately to the host without waiting for the next trigger frame Decimation The data may be decimated by a programmed ratio to reduce the data rate This mode is usually used when the data rate 1s less than the minimum master clock rate of the A D A D performance is not specified and will degrade sometimes with unpredictable results 1f the converter is operated below its minimum sample rate The decimation simply discards M points for every point kept no averaging or filtering is used When decimation is true the number of points captured in the framed mode is the number of decimated points in other words the discarded points do not count Maximum decimation rate is 1 4095 When decimation is used in the framed trigger mode the number of points captured is after decimation The frame count is always the actual number of points inserted into the FIFO Trigger Controls in SNAP Example The SNAP example application
106. eference FMC_VADJ E19 Reference voltage input for the JN4 P16 digital IO This voltage must never exceed 2 5V This reference voltage allows the DIO to be used with Current requirement is lt 100 mA different IO standards including 2 5V 1 8V and 1 5V Table 22 System Integration Signals on P16 Connector The H_PPS and FMC CLKP N signals can be used to integrate the X6 module with system timing signals from a GPS or other time reference Many timing references such as GPS IEEE 1588 LAN timing and ARINC include both a PPS signal and reference clock The PPS is generally used as an arming signal for system timing while the reference clock is used to generate synchronous sampling clocks Chapter 27 Thermal Protection and Monitoring The X6 includes a temperature monitor for the Virtex6 device This monitor connects directly to the FPGA temperature diode connections so that the FPGA die temperature is directly measured The temperature monitor does not use the FPGA logic or system monitor for this measurement so that it can protect the FPGA in case of failure X6 400M User s Manual 53 About the X6 XMC Modules Fan PWM Fan Speed Figure 23 X6 Temperature Monitoring Over temperature The monitor watches the FPGA die temperature and compares it to a critical and alert threshold These thresholds are programmed into the temperature monitor device to override the defaults Software functions in Malibu software
107. ensing for the standard commercial modules Extended temperature versions of many modules are available with conformal coating if the environment is more demanding During operation the module temperature should be monitored to prevent unexpected shutdown If the module temperature exceeds 85C LO rating the module will deactivate on board power supplies to avoid overheating Please refer to the section on thermal properties for more details PCI Express slots are rated for their power capability Each installation should be reviewed to verify that the host card plus the module do not exceed the rated power of the slot The power consumption for each module is provided in the specific discussion of that module Most slots support 15W in desktop systems and provide 3 3V and 12V Some XMC modules require 12V which must be provided by the host card X6 400M User s Manual 33 Hardware Installation Mechanical Considerations The X6 modules conform to IEEE1386 CMC specification and ANSI VITA 42 0 specifications except as specified on individual modules These specifications define the size of the module and mounting requirements In short the modules are 75 x 150 mm and mount 10 mm from the host card This allows the XMC modules to fit in one slot in desktop PC or compact PCI systems For ruggedness the modules should be mounted to a host card using the mounting screws and standoffs The host bracket should securely hold the XMC front brack
108. er Interface Chapter 46 User Interface This application has five tabs Each tab has its own significance and usage though few are interrelated All these tabs share a common area which displays messages and feedback throughout the operation of the program Configure Tab As soon as the application is launched the Configure tab is displayed In this tab a combo box is available to allow the selection of the device from those present in the system All XMC family devices of whatever type share a sequence of target number identifiers The first board found is Target 0 the second Target 1 and so on X6 400M User s Manual 69 Writing Custom Applications 13 Capture Example Configure Setup Stream EEProm Debug TabSheet1 Driver Busmaster Size MB Target H 32 Open Close Click the Open button to open the driver To change targets click the Close button to close the driver select the number of the desired target using the Target combo box then click Open to open communications with the specified target module The order of the targets is determined by the location in the PCI bus so it will remain unchanged from run to run unless the board is moved to a different slot or another target is installed Setup Tab This tab has a set of controls that hold the parameters for transmission These settings are delivered to the target and configure the target accordingly This tab has several sections The contr
109. er ZBROJ Q files or a resident in shared DSP memory Please see the Time Frequency Text Summary Server Dl xl on line BinView help file in your Binview installation X Zombu ZoomiIn gt gt gt directory TM Amplitude vs Offset Counts e9 e e 0 10 20 30 40 50 Offset 60 70 80 90 100 Span 100 Analyze ChO 7 X6 400M User s Manual Samples 4096 105 Applets for the X6 Family Baseboards Chapter 62 Applets for the X6 Family Baseboards Logic Update Utility VsProm exe The Logic Update Utility applet is designed to allow field upgrades of the logic firmware on the X6 module The repe a x utility permits an embedded firmware logic update file to T o a reprogrammed into the baseboard Flash ROM which stores luda el the personality of the board SEF DEE 3 Note that this utility should only be used after firmware development and debugging has been completed During the development cycle it is much more efficient to download and debug firmware using the Xilinx Bit Blaster JTAG cable GOLDEN IMAGE Update Logic Cpld Version 0 GOLDEN BOOT Log To use the applet select the instance of the X6 module to be updated This will be target zero in single target installations Then click the browse button to select the logic bit file image containing the updated firmware image Typically this is located in the z Innovative
110. ere 127 Table 19 Trigger MOS i a eec ott E Het en E A eb Ve e a a pea t 127 Table 20 X6 400M Trigger SOUEGGS s ubera epit ar A Ux Hn cul apu IR eR EA ERE DH 128 Table 21 External Trigger Input Requirements eri dci 129 Table 22 Alert PIES ical ardua dite sn un DR teen ale pne an calasof m AU DUE onere eli seo Chee 133 ABLE APP Tor dro RA ida 133 JTable 24 Alert Packet Formats iie aee dtf oret eb dedu n MEHR vets ain aetna ace 134 Table 25 X6 400M Power Supply Requirements sssesssseeseeeeenennee eene eene enne 137 Table 26 X6 400M Baseline Power Consumption sess enne 137 Table 27 X6 400M Power Consumption for IO Features oooocnncnnnncnnonnnonncoonnconccnnnocancconn conan ncccnnnnno 138 Table 28 X6 400M Environmental Lis iii Ee ehh en t aV aee dn ledvensteneorice lewd ne dad 139 Table 29 X6 400M Analog Input Performance Summary DC coupled Inputs 141 Table 30 X6 400M Analog Input Performance Summary AC coupled Inputs 142 Table 31 X6 400M Analog Performance Summary nennen 146 Table 32 X6 400M XMC Connector P15 Pino t neri ettet iaa 154 Table 33 P15 Signal DOSCPIDUOGEPSS cut ocn AB vies teaistes diete sco tea besser aa 155 Table 34 X6 400M XMC Secondary Connector P16 Pinout sse 157 Table 35 P l6 Signal Descriptions dl e Rama Do ERE ROO Ed e VERE SUR Ceo NU NOE SS 158 Table 36 246 INL Connector Pinta 16
111. es share a common architecture and many features such as the PCI PCI Express interface data buffering features the Application Logic and other system integration features This allows the X6 XMC modules to utilize common software and logic firmware while providing unique analog and digital features X6 Family Block Diagram Ext Clk Ref Front Panel Connectors Trigger X6 400M User s Manual 35 About the X6 XMC Modules Figure 15 X6 XMC Family Block Diagram The X6 XMCs have a variety of analog and digital IO front ends suited to many applications Table 4 X6 XMC Family X6 XMC Features Applications X6 RX 4 A D channels 16bit 160 MHz integrated 4 channel IF digitizing and receivers DDC X6 400M 2 channels 14 bit 400 MSPS A D and 2 channels 16 bit Wireless transceiver IF digitizing RADAR 500 MSPS DAC single channel at 1 GHz Electronic Warfare X6 COP 2 10Gb Ethernet ports SFP support fiber optic Sensor networks Ethernet monitoring remote connections radio heads coprocessing X6 TX 4 DAC channels 16 bit 1 GSPS each pattern generation Arbitrary waveform generation mode for DRAM communications waveform generation X6 GSPS 2 A D channels 12 bit at 1 8GSPS or single channel at RADAR communications receivers pulse 3 6 GPSP digitizing X6 COP SX315T SX475T LX550T FPGA and 6GB memory Coprocessing Table 5 X6 XMC Family The X6 XMCs feature a Xilinx Virtex 6 SX315T SX475
112. es these bit I O connections as a simple port that has programmable bit direction and data by the host The port is configured and accessed directly from the PCI Express host The digital I O hardware is controlled by the IUsesDioPort class Its properties Table 17 IUsesDioPort Class Operations DioPortConfig Configures banks of bits for input or output DioPortData Broadside Read Write to low order 32 bits of DIO Typical use of the digital IO port involves first configuring the port using the Config operator This sets the byte direction and the clock mode The port is then ready for read write configurations to each port For instance Open the module X6 400M User s Manual 46 About the X6 XMC Modules Innovative X6 RX Module Module Target 0 Module Open All bits input Module Config 0x0 Read the state of the port volatile short x Module DioPortData All bits output Module Config 0x3 Toggle the state of all output bits while 1 Module DioPortData Module DioPortData FrameWork Logic Digital IO Implementation Digital I O port activity is controlled by the digital I O data register in the Framework Logic The digital IO can be used for simple bit IO in this mode Data written to bits 31 16 of the register are output data read from the register in bits 0 15 are the inputs Pairs IO Standard Function 15 0 LVDS Input 31 16 LVDS Output Figure 2
113. escription A serial FLASH memory on the X6 modules is used for a variety of purposes including program memory for embedded processors module information and calibration data For X6 modules one sector of the FLASH is dedicated to module information and calibration data consuming 1 64 of the memory Sectors may be protected in the device for data security Memory Size Device U32 32MB Microchip SST25VF032B 80 41 S2AF Table 13 X6 Serial FLASH Device The interface to the serial FLASH is an SPI bus that is controlled by the PCI logic device The SPI bus is relatively slow about 10Mb s so the data is usually read out of the FLASH at initialization time by the application software and written into memory or registers in the application logic for real time use Calibration values for the analog are an example of this use where the calibration coefficients are read from the FLASH then written into the error correction logic for real time data correction The FLASH has a write cycle limit of 100K cycles so it should only be written to when calibration is performed or configuration information changes Once the write cycle duration limit is exceeded the device will not reliably store data any more Caution As delivered from the factory the serial FLASH contains the calibration coefficients for the analog and is pre programmed at factory test Do not erase these coefficients or calibration will be lost Use the baseboard
114. est data plott 1 bdd Sa Mapeh ure CO Y OF Tine Frequency Text Summar Serve Magnitude vs Frequency 80K 140K 160K 180K 200K 100K 120K KHz ie Binl iew dmolane projects x6 x6 400m hardware reva test dataWlot11 bdd a narh BR CO Y 97 Time Frequency Test Summar Server Magnitude vs Frequency 144K 145K 146K 147K 148K 149K KHz 150K 151K 152K 153K J al Max S N dB Max S N eB SNIE SINAD 68 ENDE bis SFDR 28 THD IE 6 55 ES 107 n 2 002978 20 548 Sample ET Leap 1024 Analyze Ch0 7 AC Coupled A D wideband signal quality Fin 251 MHz Fs 400 MHz onboard PLL Channel 0 15 pF parallel cap at A D device inputs SNe SINAD ENOB bis SFDR E THD IE 665 56 107 27 0 002586 S1 7dB Sample 120 Leap 1024 cho T Frequency domain data display AC Coupled A D narrowband signal quality Fin 2511 MHz Fs 400 MHz onboard PLL Channel 0 15 pF parallel cap at A D device inputs Analyze Samples 925960 Analog Output A summary of the analog performance follows for the X6 400M module All tests performed at room temperature with no forced air cooling unless noted Test environment was PCIe adapter card in PC running testbed software using FrameWork Logic Table 31 X6 400M Analog Performance Summary Test Group Parameter Output Measured Units Test Conditions Coupling Analog Impedance AC or DC 50 Ohms nominal Output Ou
115. et I O pin allocations on the Virtex 6 that connect to each of the P16 signals Link Lane P16 Pins P16 Signal Virtex 6 FG1156 Pin Virtex 6 GTX Signal Identifier Number 0 0 A1 B1 TXPO NO AP1 AP2 GTXTXP0_112 GTXTXNO 0 0 ATI BII RXP0 NO APS AP6 GTXRXPO 112 GTXRXNO 0 1 D1 El TXP1 N1 AN3 AN4 GTXTXP1_112 GTXTXN1 0 1 D11 E11 RXP1 N1 AMS AM6 GTXRXP1_112 GTXRXN1 0 2 A3 B3 TXP2 N2 AM1 AM2 GTXTXP2_112 GTXTXN2 0 2 A13 B13 RXP2 N2 AL3 AL4 GTXRXP2_112 GTXRXN2 0 3 C3 D3 TXP3 N3 AKI AK2 GTXTXP3 112 GTXTXN3 0 3 D13 E13 RXP3 N3 AJ3 AJ4 GTXRXP3_112 GTXRXN3 1 0 AS B5 TXP4 NO AHI AH2 GTXTXPO 113 GTXTXNO 1 0 A15 B15 RXP4 NO AG3 AG4 GTXRXPO 113 GTXRXNO 1 1 DS ES TXPS N1 AFI AF2 GTXTXP1_113 GTXTXN1 1 1 D15 E15 RXPS N1 AFS AF6 GTXRXP1_113 GTXRXN1 1 2 A7 B7 TXP6 N2 AD1 AD2 GTXTXP2_113 GTXTXN2 1 2 A17 B17 RXP6 N2 AE3 AE4 GTXRXP2 113 GTXRXN2 1 3 C7 D7 TXP7 N3 ABI AB2 GTXTXP3 113 GTXTXN3 1 3 D17 E17 RXP7 N3 AC3 AC4 GTXRXP3_113 GTXRXN3 Table 18 P16 GTX Assignments and Use Chapter 23 GTX Electrical Characteristics The GTX lanes are high speed serial port connections to the Virtex 6 These are specialized serial ports intended for use as communications ports and include many advanced features for data transmission and reception at speeds up to 5 Gbps They are generally not useful for any other purpose The GTX lanes must be AC couple at the transmitter en
116. et so that the module is snug in the bracket opening This reduces mechanical strain on the XMC connectors from the front panel cable attachments The card may be secured to the host card with two standoffs and four screws as shown The Digikey number is provided www digikey com for convenience many suppliers have these standard screw and standoff sizes For high vibration applications screws should be mounted with locking compound such as Loctite 222 Table 3 XMC Mounting Hardware Description Quantity Digikey Part Number Metric pan head screw M3X6 3mm x 5mm 5 H742 ND Threaded Standoff 10mm with 3mm thread 3 4391K During the logic and firmware design process some modules require access to JTAG connectors for use with the development tools This may require greater access space than the final installation A variety of engineering tools are available to assist the designer during the development process such as PCIe to XMC adapters A cabled version allows the module to operate outside the chassis An open chassis may also be required to get access to the XMC during the development process so that the cables are easily accessible X6 400M User s Manual 34 About the X6 XMC Modules Chapters About the X6 XMC Modules In this chapter we will discuss the common features of the X6 module family Specifics on each module are covered in later chapters Chapter 6 X6 XMC Architecture The X6 XMC modul
117. evesseusvesdenssacssstsopecsunateactoateswaads 125 CDCDE72010 SPU POU p 126 NERO GP ORG oov sitesttoi o P E UR BUND SOR EQUI MM su QD ero UDIN MI IERI 126 VEXO DE Port 0X802 T W ass aseo pne bae Dn eio Nae anos iras 126 NYAS SOLU pec Ert 127 IPRIB BOT SOUECES PURUS 128 Front Panel External Trigger Input Requirements scssccsssssssscssscsssssccsssssessssssesessssseees 128 Framed Trigger Mod aa 129 DECIMAL mec E as 129 Trigger Controls in SNAP Example eee eeeticth acacia ipto dbi bae pape Se asses RI SUe pce eU RES 129 M ultE X D Synchr niZaH O oscar ire eR aree RR ae sped Fuded ocu ea gae erT ode De ea Ue epo dE Vp Ra ea E Oe eee 130 Frame Work Logic Functionality re ttreten tarea eere pr ee e pvb x obe Ue tan Pe orbus Reo ore HEC VR Peer ep pe Ee M EE pE eaa F e 131 Alert Bue A AA M M 132 MOV OTIC eT M MPnP 132 Types Of Alerts aoc do riada bus eub end ua ud dun Y Pelei ae Fdo Lund ks epa eA PN pP sasoe E nr SR sS 132 Alert Packet Format pP RR 133 Software Support for A erts uicieeessceaese senso eno se eth neue Urbe aaepe er pr e keen SE Ce DER ea nS IR ERES REA P ERR Ae ERE RM EUe aa Re 134 Tagine the Data inc M 134 AUNT AGNI iaa a sssi 135 Updating the Calibration Coefficients ooomommmmmmss 135 Using th CU LLL ULT Bm coc 135 Where A RAMS 1
118. g is used with a heat spreader Ruggedization levels for wide temperature operation and conformal coating are supported The FPGA logic can be fully customized using VHDL and MATLAB using the Frame Work Logic toolset The MATLAB BSP supports real time hardware in the loop development using the graphical block diagram Simulink environment with Xilinx System Generator IP cores for communications and signal processing functions are available Software tools for host development include C libraries and drivers for Windows and Linux Application examples demonstrating the module features and use are provided This extremely versatile module is easily adapted for use in virtually any type of system Our XMC carrier adapters offer conduction and convection cooling and are available for a range of interfaces including Desktop PCI Desktop PCI Express Cabled PCI Express CompactPCI and PXI PXI Express This module is also readily installed into Innovative Integration s eInstrument Embedded PC SBC ComEx Single Board Computer and Andale Data Loggers What is Malibu Malibu is the Innovative Integration authored component suite which combines with the Borland Microsoft or GNU C compilers and IDEs to support programming of Innovative hardware products under Windows and Linux Malibu supports both high speed data streaming plus asynchronous mailbox communications between the DSP and the Host PC plus a wealth of Host functions to visualize and p
119. h Connector Part Number Samtec ASP 105885 01 Figure 27 P16 XMC Connector Orientation X6 400M User s Manual 154 X6 400M XMC Module Table 34 X6 400M XMC Secondary Connector P16 Pinout Column Row A B C D E F 1 TXPO TXNO DIO PO TXPI TXNI DIO PI p DGND DGND DIO NO DGND DGND DIO NI 3 TXP2 TXN2 DIO P2 TXP3 TXN3 DIO P3 4 DGND DGND DIO N2 DGND DGND DIO N3 5 TXP4 TXN4 DIO P4 TXP5 TXNS DIO P5 6 DGND DGND DIO N4 DGND DGND DIO N5 Y TCP6 TXN6 DIO P6 TXP7 TXN7 DIO P7 8 DGND DGND DIO N6 DGND DGND DIO N7 9 FMC CLKP FMC_CLKN DIO P8 FMC REFCLKP FMC_REFCLKN DIO P9 10 DGND DGND DIO N8 DGND DGND DIO N9 11 RXPO RXNO DIO_P10 RXPI RXNI DIO Pll 12 DGND DGND DIO NIO DGND DGND DIO NII 13 RXP2 RXN2 DIO P12 RXP3 RXN3 DIO P13 14 DGND DGND DIO N12 DGND DGND DIO N13 15 RXP4 RXN4 DIO P14 RXP5 RXN5 DIO PI5 16 DGND DGND DIO _ N14 DGND DGND DIO_N15 17 RXP6 RXN6 DIO _ P16 RXP7 RXN7 DIO P17 18 DGND DGND DIO _ N16 DGND DGND DIO NI7 19 H TRIGO H TRIGI DIO P18 H PPS FMC VADJ DIO NI8 Note All unlabeled pins are not used by X6 modules but may defined in VITA42 and VITA42 3 specifications X6 400M User s Manual 155 X6 400M XMC Module Table 35 P16 Signal Descriptions Signal Description DIO_Px Nx Digital IO pairs
120. h DC coupled DAC output has a single ended output into a 50 ohm load impedance Other input ranges may be custom ordered Data codes to the DAC are 2 s complement The following table gives the transfer function DC Coupled Option Output voltage pk pk Conversion Code hex 0 5 Ox7FFF 0 25 Ox3FFF OV 0x0000 0 25 0xC000 0 5 0x8000 X6 400M User s Manual 114 X6 400M XMC Module Table 1 DC Coupled DAC Conversion Coding AC Coupled Outputs Each AC coupled DAC output has a single ended output into a 50 ohm load impedance This range is fixed Data codes to the DAC are 2 s complement The following table gives the transfer function AC Coupled Option Output voltage pk pk Conversion Code hex 450 mV Ox7FFF 225 mV Ox3FFF OV 0x0000 225 mV 0xC000 450mV 0x8000 Table 2 AC Coupled DAC Conversion Coding DAC Output Loads The X6 400M has single ended DC coupled outputs that are 50 ohm source impedance The 50 ohm source impedance matches the coax cable and output connectors characteristic impedance The load on each DAC must have a 50 ohm characteristic impedance to achieve the best signal quality and correct voltage range A typical cable arrangement to preserve the signal quality is to use coax cable with a 50 ohm impedance a 50 ohm connector and 50 ohm load Suitable coax cable types are RG 316 and RG 174 Part Number Description 67048 50
121. he FPGA device The logic loader reads data from the FLASH memory bank and writes it into the FPGA SelectMap interface To achieve the required configuration times for PCI Express systems the two FLASH memories are read together as a 32 bit word which is split into two 16 bit words and written into the FPGA at 80 MHz This architecture requires that the two FLASH devices are programmed as a 32 bit wide memory instead of two 16 bit devices Therefore both devices are used for configuration It is not recommended that the configuration FLASH be used for other purposes because of its unique purpose on the module The serial FLASH memory is available for other data and programs and should be used for those purposes JTAG Scan Path Order 1 FPGA Virtex6 2 CPLD XC2C384 Mode SelectMAP JP1 Logic Image Select None Image0 application logic Short Image1 backup image X6 400M User s Manual 64 About the X6 XMC Modules Figure 29 X6 Logic Configuration Subsystem Device Image Size bits Time to Program Time to Configure Notes per image XC6VLX240T 73 859 552 300 s 62 ms XC6VSX315T 104 465 888 430s 86 ms XC6VLX475T 156 689 504 640 s 126 ms Table 31 X6 FPGA Logic Image Sizes and Configuration Times Chapter 38 Logic Image Selection Two images are held in the FLASH memory at all times The first image is the application logic the second image is the backup image
122. he UI thread A call to Synchronize directs the event to call the event handler in the main UI thread context This results in a slight performance penalty but allows us to call UI methods in the event handler freely The Timer uses a similar synchronization method Thunk Here the event is called in the main thread context but the issuing thread does not wait for the event to be handled before proceeding This method is useful for notification events Creating a hardware object does not attach it to the hardware The object has to be explicitly opened The Open method of the baseboard activates the board for use It opens the device driver for the baseboard and allocates internal resources for use The next step is to call Reset method which performs a board reset to put the board into a known good state Note that reset will stop all data streaming through the busmaster interface and it should be called when data taking has been halted The size of the busmaster region is changeable by using the BusMasterSize property before opening the board Larger values provide more buffering during streaming at the cost of slower allocation at startup time Under Windows up to 32 MB can generally be allocated in each stream direction Under Linux only up to 4 MB can generally be allocated in each stream direction Insure BM size is a multiple of four MB const int Meg 1024 1024 const int BmSize std max Settings BusmasterSize 4 1 4 Mod
123. he power supply Allowance for decreased power supply efficiency due to heating can account for 10 derating Also dynamic loads should be considered so that peak power is adequate In many cases a factor of 2 for derating is recommended Environmental The X6 400M is available for environmental rating levels from LO office lab environment to L4 military and heavy industry Environment Rating LO L1 L2 L3 L4 ER Environment Office controlled Outdoor stationary Industrial Vehicles Military and heavy lab industry Applications Lab instruments Outdoor monitoring Industrial Manned vehicles Unmanned vehicles non condensing research and controls applications with missiles oil and gas moderate vibration exploration Cooling Forced Air Forced Air Conduction Conduction Conduction 5CFM 5 CFM Operating Temperature 0 to 50C 40 to 85C 20 to 65C 40 to 70C 40 to 85C Storage Temperature 20 to 90C 40 to 100C 40 to 100C 40 to 100C 50 to 100C Vibration Sine 2g 5g 10g 20 500 Hz 20 2000 Hz 20 2000 Hz Random 0 04 g Hz 0 1 g Hz 0 1 g Hz 20 2000 Hz 20 2000 Hz 20 2000 Hz Shock 20g 11 ms 30g 11 ms 40g 11 ms Humidity 0 to 95 0 to 100 0 to 100 0 to 100 0 to 100 X6 400M User s Manual 138 X6 400M XMC Module Conformal coating Conformal coating Conformal coating extended temperature range devices Conformal coating extended tem
124. he trigger is false One often misunderstood point about framed mode triggering is that it is best if the data packet size is set to the same or integer sub multiple packet size so that data will flow as expected If the packet size is equal to the frame size then the data packet will transfer to the system when the frame is complete When this is mismatched some or all of the data is stuck waiting for the packet to be completed If multiple triggers are expected then the next trigger may push the data out If you have only one trigger the data will not move to the host because the packet is not complete It is best in most cases to just make the data frame that same as packet size to avoid this confusion Multi A D Synchronization To synchronize multiple X6 400M cards there are several requirements e All cards must receive a synchronous clock or reference clock that is low jitter e All cards must receive a trigger signal that is a precisely time aligned to the input clock e All cards must be ready to take data when the trigger is fired This means that all A D have completed timing calibration and ready to take data X6 400M User s Manual 130 X6 400M XMC Module Provided that these requirements are met multiple cards can be synchronized for system expansion FrameWork Logic Functionality The FrameWork Logic implements a data flow for the X6 400M that supports standard data acquisition functionality This data flow when
125. host system to allow the host OS to recognize the X6 module on the PCIE bus Once this is accomplished a known good image may be reprogrammed into the EEPROM using the EEPROM exe tool X6 400M User s Manual 67 Writing Custom Applications Chapter 41 Writing Custom Applications Most scientific and engineering applications require the acquisition and storage of data for analysis after the fact Even in cases where most data analysis is done in place there is usually a requirement that some data be saved to monitor the system In many cases a pure data that does no immediate processing is the most common application The X6 XMC card family contains high bandwidth analog capture and playback modules with an advanced architecture that provides ultimate flexibility and speed for the most advanced hardware assisted signal processing and ultrasonic signal capture The maximum data rate from these module are often in the hundreds of MSPS This means that a simple logger that saves all of the data to the host disk is not feasible using standard operating system disk I O calls as the slower disk writes eventually cause overflow and data loss in the streaming system Some modules support decimation so that long duration samples can be taken without data Also quick snapshots of analog data can be taken without loss as long as the amount of data is less than the net capacity of system memory and what the baseboard holds The example program prov
126. ided for nearly all cards is this limited capacity data logger called the Snap example Chapter 42 The Snap Example The Snap example in each software distribution demonstrates this logging functionality It consists of a host program in Windows which works with the logic provided on the board s flash to stream data to the host It uses the Innovative Malibu software libraries to accomplish the tasks Chapter 43 Tools Required In general writing applications for the XMC requires the development of host program This requires a development environment a debugger and a set of support libraries from Innovative Table 33 Development Tools for the Windows Snap Example Processor Development Environment Innovative Project Directory Toolset Host PC Codegear Developers Studio C Malibu Examples Snap Bcb11 Microsoft Visual Studio Examples Snap VC9 QtCreator Examples Snap Qt Common Host Code Examples Snap Common On the host side the Malibu library is provided in source form plus pre compiled Microsoft Borland or GCC libraries The application code that implements the entirety of the board specific functionality of example is factored into the ApplicationIo cpp h unit All user interface aspects of the program are completely independent from the code in X6 400M User s Manual 68 Writing Custom Applications Applicationlo which contains code portable to any compilation environment 1 e it
127. iggering where a single trigger enables many data samples to be taken before rechecking the trigger This code enables framed mode or disables it depending on the settings X6 400M User s Manual 80 Writing Custom Applications The Stream Start command applies all of the above configuration settings to the module then enables PCI data flow The software timer is then started as well dads Start Streaming Stream Start UI gt Log Stream Mode started UI gt Status Stream Mode started FTicks 0 Timer Enabled true Handle Data Available Once streaming is enabled and the module is triggered data flow will commence Samples will be accumulated into the onboard FIFO then they are bus mastered to the Host PC into page locked driver allocated memory following a two word header data packets Upon receipt of a data packet Malibu signals the Stream OnDataAvailable event By hooking this event your application can perform processing on each acquired packet Note however that this event is signaled from within a background thread So you must not perform non reentrant OS system calls such as GUI updates from within your handler unless you marshal said processing into the foreground thread context This marshaling behavior can be automatically enabled by calling the event Thunked or Synchronized method as was done in the Open call earlier void ApplicationIo HandleDataAvailable VitaPacketStreamDataEvent Eve
128. ilable SetEvent this amp ApplicationIo HandleDataAvailable Stream DirectDataMode false The Stream object manages communication between the application and a piece of hardware Separating the I O into a separate class clarifies the distinction between an I O protocol and the implementing hardware In Malibu high rate data flow is controlled by one of a number of streaming classes In this example we use the events of the VitaPacketStream class to alert us when a packet arrives from the target When a data packet is delivered by the data streaming system OnDataAvailable event will be issued to process the incoming data This event is set to be handled by HandleDataAvailable After processing the data will be discarded unless saved in the handler Similarly OnDataRequired event is handled by HandleDataRequired In such a handler packets would be filled with data for output to the baseboard The Snap application does not generate output so the HandleDataRequired event is left unhandled Timer OnElapsed SetEvent this amp ApplicationIo HandleTimer Timer OnElapsed Thunk In this example a Malibu SoftwareTimer object has been added to the Applicationlo class to provide periodic status updates to the user interface The handler above serves this purpose An event is not necessarily called in the same thread as the UI If it is not and if you want to call a UI function in the handler you have to have the event synchronized with t
129. imes however the Applicationlo object needs to call back into the UI But since the code here is common it can t use a pointer to the main window or form as this would make ApplicationIo have to know details of Borland or the VC environment in use The standard solution to decouple the Applicationlo from the form is to use an Interface class to hide the implementation An interface class is an abstract class that defines a set of methods that can be called by a client class here ApplicationIo The other class produces an implementation of the Interface by either multiple inheriting from the interface or by creating a separate helper class object that derives from the interface In either case the implementing class forwards the call to the UI form class to perform the action ApplicationIo only has to know how to deal with a pointer to a class that implements the interface and all UI dependencies are hidden The predefined UserInterface interface class is defined in Applicationlo h The constructor of Applicationlo requires a pointer to the interface which is saved and used to perform the actual updates to the UI inside of ApplicationIo s methods Chapter 48 Applicationlo Initialization The main form creates an Applicationlo object in its constructor The object creates a number of Malibu objects at once as can be seen from this detail from the header Applicationlo h Modulelo Module IUserInterface UI Innovative VitaPacketStream
130. indicated channel of those active is filled with data and the remainder are zero filled Two tone mode fills the buffer with the sum of two waves of the indicated frequencies Stream Tab The Wave example supports the Preconfigure button This allows the DAC timebase and calibration to occur once before starting streaming leaving the clock undisturbed during the run If the Auto Preconfig checkbox is checked then it acts as if you pressed the Preconfigure button every run ig X6 400M PCIe Module Wave Example eas 38 ALC ale v Auto Preconfigure Blocks Rate MB s iream Eeprom Debug fid Version 3 03 Apr 52011 X6_400M specific wordset loaded gt No devices detected Open Failure Target board not found Open Failure Target board not found Open Failure m Target board not found E Chapter 51 Applicationlo Stream Preconfigure In order to support DAC systems that need calibration to tune the synchronization of their outputs the channel selection and timebase definition is moved out of the normal location to a special preconfiguration stage This stage must be manually triggered by the application by calling Stream Preconfigure The Wave example allows this by the additon of a preconfiguration button In addition the Auto Preconfigure mode will automatically call Stream Preconfigure whenever the stream is started All items that are initiali
131. ings ReferenceClockSource odule Clock ReferenceFrequency Settings ReferenceRate 1e6 Route clock odule Clock Source src Settings SampleClockSource odule Clock Frequency Settings SampleRate 1e6 Readback Frequency double freq actual Module Clock FrequencyActual std stringstream msg msg lt lt Actual PLL Frequency lt lt freq actual Log msg str Stream Preconfigure Start Streaming Setup of the stream is much like the Snap example We have similar error checking code and rate guarding X6 400M User s Manual IX6ClockIo IIReferenceSource ref IX6ClockIo rsExternal IX6ClockIo rsInternal IX6ClockIo IIClockSource src IX6ClockIo csExternal IX6ClockIlo csInternal 85 Writing Custom Applications Applicationlo StartStreaming void ApplicationIo StartStreaming Set up Parameters for Data Streaming First have UI get settings into our settings store UI GetSettings if auto preconfiging call preconfig here if Settings AutoPreconfig StreamPreconfigure if FStreamConnected Log Stream not connected Open the boards return false if Settings SampleRate 1 e6 Module Output Info MaxRate Log Sample rate too high return false The first difference is that we configure the Output sub object instead of Input The X6 Family divides the interface functio
132. l plane thereby reducing the heat concentration in the FPGA The heat spreader mounts to the card with four M2 screws A thermally conductive pad on the FPGA top surface provides a conduction path to the heat spreader X6 400M User s Manual 58 About the X6 XMC Modules Figure 27 X6 Heat Spreader for FPGA Caution If the heat spreader is removed for any reason extreme caution should be observed in its removal The thermal pad has adhesive to both the spreader and FPGA that makes it difficult to remove It is best to mildly heat 80C the entire assembly after the screws are removed then twist the heat spreader gently until it can be easily removed Chapter 31 X6 Power Saving Features The X6 modules have many controls for reducing the power consumption Many devices can be powered down if they are not used by the application or can be turned off for a sleep mode This can reduce average power consumption Feature Power Consumption Notes DRAM banks 4 total 750 mW per bank DRAM shutdown control turns off device All data is lost Power up time is approximately 1 ms P16 GTXs 8 lanes total 150 mW per lane P16 GTX s are off by default It is also possible to stop the GTX clock for reduced power Lane link is lost and must be re initialized on power up PCI interface 600 mW This interface is OFF unless enabled Analog I O Varies by module Most modules have analog power control Power up time should
133. m unburdened by the data flow The command channel provides the PCIe host direct access to the computing core logic for status control and initialization Since it is outside the packet system it is less complex to use and provides unimpeded access to the logic The application FPGA image is loaded at power up from onboard flash EEPROM storage Adding New Features to the FPGA The functionality of the computing core can be modified using the FrameWork Logic tools for the X6 module family The tools support development in either VHDL or MATLAB Signal processing data analysis and unique functions can be added to the X6 modules to suit application specific requirements See the X6 FrameWork Logic User Guide for each product for further information Chapter 8 X6 PCI PCI Express Interface The X6 module family has a PCI and PCI Express interface for host communications Only one interface either PCI or PCI Express is active at one time This allows the module to be used in both XMC IO sites and older PMC PCI bus sites PCI Express offers transfer rates up to 8 GB s while PCI transfers are 256MB s maximum X6 400M User s Manual 38 About the X6 XMC Modules The standard product ships with a x8 Genl PCIE Express interface IP cores for x1 x4 Genl and Gen2 are also avialble NOTE The higher speed x8 Gen PCIe core requires a 2 speed grade FPGA that must be specified at order Chapter 9 PCI Express Interface The PCI Express interfac
134. mmands The control register is a simple pair of registers to control each signal and read back the pin All device addressing commands and data are read using the LC software driver through the controls in this register VCXO DC Port 0x802 r w Bit Direction Definition 0 W SDA serial data bit 1 W SCK bit for serial clock 2 R Readback for I2C data pin 3 R Readback for I2C clock pin 6 4 Unused R W VCO output enable 0 disabled default X6 400M User s Manual 126 X6 400M XMC Module 31 8 Unused Table 18 VCXO control and I2C register 0x801 r w The I2C SDA data output 1s set using bit 0 and the pin is readback on bit 2 The I2C SCL clock is set using bit 1 and the pin readback is on bit 3 These signals must emulate the I2C pin functions for the protocol Triggering The X6 400M has a trigger control component in the FPGA that controls the data acquisition process The sample clock specifies the instant in time when data is sampled whereas triggering specifies when data is kept This allows the application to collect data at the desired rate and keep only the data that is required On the X6 400M module all A D channels operate synchronously using the same clock and trigger The trigger controls allow data to be acquired continuously or during a specified time as triggered by either a software or external trigger Data can also be decimated t
135. n logic can use the DRAM interface for any type of data for buffering or computation memory through the LPDDR2 interface The Framework Logic implements a data buffer with one or more queues for the A D and D A streams as appropriate for the particular X6 module The X6 TX has special support for pattern generation using the DRAM memory bank The pattern generation mode provides dynamic pattern generation using DRAM memory bank that is driven by control and data packets from the host This allows the DRAM to be used as an arbitrary waveform generator for applications such as communications testing RADAR stimulus generation and ultrasonic stimulus The buffer memory data transfer rates are limited by the maximum clock rate for the memory device and the speed of the logic device Each X6 module has a memory clock rate selected so that it supports the IO requirements of the card IN most X6 400M User s Manual 42 About the X6 XMC Modules cases this means that the clock rate 1s lower than the maximum clock rate that the DRAM can support simply because the power consumption is lowered and it is easier to meet timing during design X6 Module Maximum DRAM Maximum Memory FrameWork Memory FrameWork Logic Memory Clock Rate MHz Bandwidth MB s Clock MHz Bandwidth MB s X6 RX 533 4264 333 2664 X6 400M 533 4264 333 2664 Table 12 Buffer Memory Bandwidth Chapter 16 Serial FLASH Interface FLASH Memory D
136. nal Quality for Fout 160 1MHz Fs 1GSPS AC Coupled DAC Amplitude Variation vs Fout Normalized Power AC Coupled DAC Output Amplitude vs Fout 1 Fout MHz Power dBm dBm T 0 5 1 3 3 0 S 20 1 3 34 0 04 6 d bid d 8 i mmm Ch 0 normalized 100 1 2 49 0 81 Sa 150 1 1 5 1 8 D 200 1 0 4 2 9 250 1 1 3 4 6 E m 300 1 3 67 6 97 6 Fout MHz Figure 17 Frequency Response for 5 MHz to 500 MHz Figure 18 Frequency Response for 5 MHz to 500 MHz span AC Coupled Output Fs 500 MSPS NO span AC Coupled Output Fs 500 MSPS NO SINC CORRECTION SINC CORRECTION X6 400M User s Manual 147 X6 400M XMC Module AC Coupled Signal Quality vs Fout 70 60 50 SNR dB D 40 s SFDR dB THD dB 30 20 10 0 Le 0 20 40 60 80 100 120 140 160 180 MHz Stop 500 0 MHz VBW 1 0 kHz Sweep 60 3 s 1001 pts Res BW 1 0 kHz VBW 1 0 kHz Sweep 603 s 1001 pts Figure 20 AC Coupled Output Signal Quality for Fout Figure 21 AC Coupled Output Signal Quality for Fout 5 1MHz Fs 1GSPS 70 1MHz Fs 1GSPS X6 400M User s Manual 148 X6 400M XMC Module SENSE INT ALIGNAUTO D253 10AM A Avg Type Log Pwr R Cp Trig Free Run is Atten 30 dB Y Res BW 10 kHz Man Video BW 1 0 kHz Auto Man VBW 3dB RBW 10 Auto Man Span 3dB RBW 106 Auto Man RBW Control Gaussian 3 dB Stop 500 0
137. nalog Input Bandwidth 1 e S 0 2 c 64 2 c Ss c mum Dota dB 3 Qj o 3 a a amp 5 0 50 100 150 200 250 300 350 400 450 500 Fin MHz X6 400M AC Coupled Input Bandwidth 15 pF parallel cap at A D device input x BinView Vdmelane projects x6 x6 400m hardware reva test data plot8 bdd a Marh TBR co Q Time Frequoney Tex Summa Server Magnitude vs Frequency 20K 40K 60K 80K 100K KHz 120K 140K 160K 180K 200K Max S N dB S N d SINAD dB 860 698 634 ENOS bis SFDR dB THD 2 48 112 895 0 001575 96 198 Sample EE Leap 1024 Ande Ch0 v Samples 936716 AC Coupled A D wideband signal quality Fin 5 1 MHz Fs 400 MHz onboard PLL Channel 0 15pF parallel cap at A D device inputs x BinView dmelane projects x6 x6 400m hardware reva test data plot9 bdd amp Marh zp CO Y e Tine Fiequency Text Summar Seve 497 22 265 Magnitude vs Frequency 100K KHz 120K 140K 160K 180K 200K E BinView dmclane projects x6 x6 400m hardware reva test data plot9 bdd amp M4 Tee CO Y O Tine Frequency Tet Sunmay Seve 709 745 Magnitude vs Frequency 60K 62K 64K 66K 68K 70K 72K 74K 76K 78K 80K KHz SA GI SINAD E EROS is SFOR GB THD E 63 EN 1 T 00 2845 Leap 1024 Analyze ChO 7 Samples 929396 AC Coupled A D wideband signal quality Fin 70 1 MHz Fs 400 MHz onboard PLL Channel 0 15 pF parallel cap at A D device inputs
138. nd limit input signals if possible This avoids noise contributions and aliasing caused by out of band energy in the input signal e Scale your input signals to take advantage of the full scale input ad output ranges of the converters This will maximize signal to noise in most cases Custom input and output ranges can be ordered if necessary Use high coax cables at all times and terminate all signals to 50 ohms Cables should be RG 179 or better e Reference input signals to the module ground Be sure not to introduce ground loops Provide sufficient signal strength to drive the input The X6 400M terminates its inputs to 50 ohms so signals sources must be able to drive the DC termination effectively If you decide to test the X6 400M to verify its performance be aware that most signal sources are not good enough without additional filtering and careful use Most single ended lab instruments are limited by their distortion especially at higher frequencies to about 70 dB It is usually necessary to bandpass filter lab signal sources to improve the quality of the test signal before the X6 400M input The filter reduces out of band noise and harmonic distortion from the signal source Figure 10 Typical Performance Evaluation Setup Power Requirements Power Supplies The X6 400M requires the following voltages and power X6 400M User s Manual 136 X6 400M XMC Module Supply Voltage Nominal M
139. nerator that will fill a packet with an interleaved set of channels Sadly this packet is not in the proper format for sending to the X6 cards as it needs to be placed into the appropriate number of Vita packets with proper Stream Ids These packets then need to be inserted into a Velocia buffer to send Applicationlo FillWaveformBuffer Fill buffer with waveform data void ApplicationIo FillWaveformBuffer Builds a N channel buffer int channels Module Output ActiveChannels int bits Module Output Info Bits int samples static _cast lt int gt Settings PacketSize calculate scratch packet size in ints int scratch pkt size if bits 8 Scratch pkt size channels Holding lt char gt Settings PacketSize else if bits 16 Scratch pkt size channels Holding lt short gt Settings PacketSize else Scratch pkt size channels Settings PacketSize Innovative Buffer ScratchPacket ScratchPacket Resize scratch pkt size Builder SampleRate Settings SampleRate 1e6 Builder Format channels bits samples Builder BuildWave ScratchPacket The first step is to generate the actual wave data The approach taken is to have the original wave generator construct a standard wave file in a scratch buffer which we will then use to construct the correct Waveform packet So we need to calculate the size of the scratch buffer and load the generator parameters Then the Build Wave call c
140. nnovative Express Air or conduction cooled Air Cooled 80260 7 Conduction Cooled 80260 6RC Table 30 XMC Adapters and Hosts Chapter 36 Standalone Operation The X6 modules can be run standalone for embedded applications using a carrier card such as Innovative 90181 The host card provides power to the module and cooling Custom carrier cards have been created for specific applications that provide Ethernet ports Figure 28 eInstrument Node Enclosure P N 90181 Supports Standalone Operation The logic must be modified for standalone operation to remove the PCIe host interface and controls and substitute local controls and logic Other changes vital to system operation are detailed in the Framework Logic manuals X6 400M User s Manual 63 About the X6 XMC Modules Chapter 37 Logic Configuration FPGA logic can be loaded from either a non volatile FLASH EEPROM or through the FPGA JTAG port The logic image is loaded from the FLASH through the SelectMap interface to the FPGA at power up for normal operation The JTAG port is usually used during debugging and test Use of the JTAG port is described in the X6 FrameWork Logic User Guide Logic Configuration from FLASH EEPROM The FPGA loads its logic from a non volatile FLASH EEPROM on the X6 module The X6 module has a logic loader built on the module that loads the FPGA logic image from the FLASH memory after power on The image size is dependent on t
141. ns for Input and Output devices into separate configuration sub objects This allows Input and Output to be independently configured if Settings Framed Granularity is firmware limitation int framesize Module Output Info TriggerFrameGranularity if Settings FrameSize framesize std stringstream msg msg lt lt Error Frame count must be a multiple of lt lt framesize Log msg str UI gt AfterStreamStop return false This code checks that the frame size is valid for the particular board being used The granularity of the hardware frame size control could be different on different cards But as long as there is a standard means of getting the correct value the example can work for any card with the same code Configure Trigger Mananger Trig DelayedTriggerPeriod Settings TriggerDelayPeriod Trig ExternalTrigger Settings ExternalTrigger Trig AtConfigure FBlockCount 0 FBlockRate 0 Check Channel Enables int ActiveChannels Module Output ActiveChannels if ActiveChannels Log Error Must enable at least one channel UI gt AfterStreamStop X6 400M User s Manual 86 Writing Custom Applications return false The trigger manager is an object defined in the Application portion of Malibu to handle how and when the application manages the software trigger during a run Separating this kind of boilerplate code makes the Applicationlo object cleaner
142. nt if Stopped return VeloBuffer Packet Extract the packet from the Incoming Queue Event Sender gt Recv Packet FWordCount Packet SizeInInts if Settings IntermediateLogEnable if FWordCount lt WordsToLog IntermediateLogr LogWithHeader Packet IntegerDG Packet DG Packet TallyBlock Packet DG size sizeof int Per block triggering actions Trig AtBlockProcess Packet DG size sizeof int When the event is signaled the data buffer must be copied from the system bus master pool into an application buffer The preceding code copies the packet into the local Buffer called Packet Since data sent from the hardware can be of arbitrary X6 400M User s Manual 81 Writing Custom Applications type integers floats or even a mix depending on the board and the source Buffer objects have no assumed data type and have no functions to access the data in them In the case of X6 series XMC modules the data contained within the body of the buffer is a list of VITA49 subpackets These must be parsed and processed individually This is done as a post processing step since in normal cases the Binview application can display the contents of the data file without splitting it up As each Velocia packet is received and processed within the HandleDataAvailable method the TallyBlock method is called This routine calculates and reports the data flow rate through the user interface void A
143. nux hosts two XMC modules II P N 90199 A RR 33 Figure 15 X6 XMC Family Block Dia erdt atten i ede OR TEE e ont epe odas 37 Figure 16 PCI Express Interface Block DIAgtam o oce aepo e eda ues NB ORE 40 Figure 17 PCI Interface Block Diagram case taii ui Da hne Rc Pe d rien eo n rp e nares 4 Figure 18 Xo0 DRAM Interface steep uer eed yea dd il Raps vau cus 43 Figure 19 X6 Digital IO Block Dig grams ius EO V I NND REIS Maman DEEP RN EI NRI 46 Figure 20 Default Digital IO Contiguratlofi seco i reete ett t EO eer RII SR enc it cede pe e E TREE VES 48 Figure 21 X6 AuroracPOotts om PLO sucess A A A A ut RR E VES A 52 Figure 22 X6 Module Cluster Using Avrora sis sisassevecssncvaccvasasvessavacssantostveocevieseuvanssngunstenn reae eme o 53 Figure 23 X6 Temperature MOBITOBIBE diee etr ch onmi eder A qe ter Venda evt 55 Figure 24 Temperature Sensor Location uve tr rS pO REED rd np ce e eee 56 Figure 25 Example Fan Control Circuits e ooi i e eei E eR ERIS Yee rea RERO Ren 58 Figure 26 X6 Conduction Cooling Thermal Connection Areas eene 59 Figure 27 X6 Heat Spreader for EPQUA aon is la 60 Figure 28 eInstrument Node Enclosure P N 90181 Supports Standalone Operation 64 Figure 29 X6 Logic Configuration SUDSYSECID i o eres noe dps e ENERO 66 Figure 30 X6 Configuration FLASH Programmgetr eese eene nennen 67 Figure 31 X6 400M Module heatsink and analog shield removed
144. o 0S 45 Digital TO Connect e 46 Digital IO Electrical Character isticsivss sisiscdsscssencscedavscoressensastssencsvenasedausdabuuesteastsasedastonsagesvausssavaveosss 46 ENCMOS2 5 V PIDS us Eo ted eM dad A dade uS DA ME 46 EV DDS 2 5 PIs T tive 47 Software SUP POF qm M 47 Notes On Digital TO US c dai a dias 48 P16 Communication POLES a iaa Dana 48 GTX Comnections to uibs rm 49 GTX Electrical Characteristics UE REDE C SQUE 49 GTX Reference C locks ias edet iiit cna ie odd ita 50 PAUP OMA POE ES ias 51 Connecting Multiple X6 Modules Using Aurora Ports cccsccscsscssssscssssscssssscssssesscsssssseeseees 52 System Timing Features on Pio cis 53 Thermal Protection and Mornltorlig ise eeieseeise se etes eoo pie eee vade en b Peso Tee e PES epp S RR PeEo o EE RON e pR EE CHA Que eu E PNEEEN 54 Temperature Re300UL aio soie meret beternd aene eb ceedev in 56 Software Support for Temperature Monitoring eeeeee eese ee eese eerte tenent tn esten sees asset enun 56 System Thermal De t em 57 Pando ontFol A a E E 57 Conduction Cooling sses EN 58 X6 FPGA Heat DECO indie restet eoa i qoe sosestnotasseskcshasescesanesoueasncsietaeseaseactacdasausvaossbes 59 XO Power SAVING ucc ing Pr So 60 Power Supply COMUPONS eee lLGnid idas 61 Led Indicators iio feod
145. o eva Ee EZ Ue aea 62 LEDs NOT Lit with FrameWork Logic Installed uooomoooommmmmssssems bZ JTAG SCA i CM O02 Frame Work fcu dC rioja 0S Integrating with Host Cards and Systemis isssscccssscsssscvesssevssssvescconssssonsusvonsssessveseseessavavesercassonsasssvseeensees OO SEA O LET LoS COMER GALI ca da OS Logic Configuration from FLASH EEPROM seessessssesssesssocesoessocessoessoosssosesocsssesssosessosesossssssse 0D Losic Image SEO eem RE CU Updating the Logic Configuration FLASH EEPROM csssccsssscsssscsssscssssscssseessssscscseeeeees OO Rescuing the Card When the Logic Image is Bad sccssscccsssecscsscsscscscssscscsscscssccssssesscsseeeeeeO 7 Chapter 4 Writing Custom Applicati0Ns mooooommmmmsmmbY The Siap Exaile em E 00 Tools auo 0 Program D esioli 5n qo eiester erue ento cn dede Urea da soe The Host Application cria iii edi is PU User Interlacen aaa dd Conor Ta as 70 Setup E SS rd 71 SECA LAD EET E E 73 Host Side Program Organiza lO coincidan e oe erica cerca 4 O RR EIE E Horis ILIA ILIO RES END E DEP AT 75 Starine Data TION onse A a O GR 79 Handle Data Avarlables AS a DI e cena tuner eb lea pel ues DU sa D hana e REES 82 The Wave Example nani an User Interface naci nn eos TheSect p Tab A A A A e 83 BUR rM Pr PER 84 Stream Eae nec edo eode tec uio peeled SN t e ag 85 Alba TOTO sass reed sete etched A A OO Stream Precon ig ere
146. o reduce data rates Trigger Mode Data Collected Played Back Start Trigger Stop Trigger Continuous All enabled channel pairs Software or rising edge of Software or falling edge of external trigger external trigger Framed N sample points for each of Software or rising edge of Stops when N samples are the enabled channel pairs external trigger collected back Decimation M points are discarded for every point kept May be used with either trigger mode Table 19 Trigger Modes Fs Trigger Analog Input Samples are acquired when trigger is true on rising edges of Fs when trigger is true Figure 7 Analog Triggering Timing X6 400M User s Manual 127 X6 400M XMC Module As shown in the diagram samples are captured on the rising edges of the sample clock when the trigger is true The trigger is true in continuous mode after a rising edge on the trigger input software or external until a falling edge is found The trigger is timed against the sample clock and may have a 0 to 1 A D conversion clock uncertainty for an asynchronous trigger input To guarantee exact triggering no triggering uncertainty the input trigger MUST be synchronous to the sample clock Trigger Sources A software trigger or external trigger can be used by the trigger controls Software trigger can always be used but external triggering must be sele
147. ode for CMIXO and CMIXI If multiple registers are accessed on the same DAC device a wait statement should be inserted between each access to allow time for the SPI transaction 0x890 0x000020EA 1 ms 0x890 0x00003001 1 This script configures two registers in the DAC device with a 1 ms wait between the access In the Malibu software functions to execute scripts and direct access functions are provided The script mode allows pre written device configurations to be read in from script files a convenient method to have multiple setups ready for use The access functions in software perform the configurations directly while respecting the SPI port ready status so that no waits are required Sample Rate Generation and Clocking Controls Conversion clock sources on the X6 400M are on card PLL or an external clock reference input X6 400M User s Manual 118 X6 400M XMC Module J6 Ref Clk ADC Ref To FPGA Input DAC Ref To FPGA DAC CLK To FPGA To DAC To ADCO 1 To ADC2 3 12C Port 12C Port To MGT PLL Figure 3 Sample Clock Generation and Distribution Block Diagram Sample clocks are either generated by the PLL or are derived from an external input clock Specialized clock circuitry is used on the X6 400M for clock generation and distribution since these clocks must be extremely low noise to achieve the best digitizing accuracy This means that the clocks are NOT generated by the FPGA but rather the sp
148. ols in the Clock group offer configurations and routing of the clock The clock for the FPGA can come from an external clock EXT or from an onboard phase locked loop INT The selection can be made at upper right corner of this section The output sample rate of the selected clock source is specified in the Output field in MHz X6 400M User s Manual 70 Writing Custom Applications n n HJ X6 400M PCIe Module Snap Example E ica Configu i 1 Stream EEProm Debug Debug Logs Reference Clock Ext Clock Srey Communications Source Source Front Panel Alerts C Ext Int C Ext Int Velo Pkt Size Y Timestamp Input Overrange 51000 Y Software Frequency Frequency D 10000 Temperature Fifo Overflow 10 0 MHz 240 0 MHz Trigger Active Channels Trigger Cho Source Ext Trigger Srey Frame Mode Type v Ch1 Software Size Unframed Level External rie 4000 4 Framed C Edge Test Counter Decimation Sawtooth Enable v Enable 1 Event Log Be sure to read the help file for info on this program located in the root of the this example folder System wordset loaded ficl Version 3 03 Apr 5 2011 X6_400M specific wordset loaded ok No devices detected Module Device Open Failure Target board not found Module Device Open Failure Target board not found Module Device Open Failure Target board not found E SS SSO xd The controls in the Reference group specify the s
149. onstructs the wave in the scratch buffer X6 400M User s Manual 89 Writing Custom Applications The second step is to copy the data from the scratch buffer into an array of Vita buffers In this case we can do this as integers as the data format is the same for our one stream ID The maximum size of a Vita packet is relatively small so we have to support paging into a number of them We choose to make all the packets the same large size until the final one that holds the remainder We now have the data in a regular buffer We need to copy it into VITA buffers and then those VITAs into the Waveform packet std vector Innovative VitaBuffer VitaQ Innovative UIntegerDG ScratchDG ScratchPacket Bust up the scratch buffer into VITA packets unsigned int words remaining ScratchPacket SizeInInts unsigned int offset 0 while words remaining calculate size of VITA packet const unsigned int MaxVitaSize OxF000 Vita limited to 16 bit size unsigned int VP size std min MaxVitaSize words remaining Get a properly cleared inited Vita Header VitaBuffer VBuf Stream NativeVitaBuffer VP size Innovative UIntegerDG VitaDG VBuf The Native VitaBuffer function produces a buffer with a properly initialized header and trailer This is particularly important here since the trailer s padding field if not correct will not allow you to completely fill the packet using our Datagrams What
150. ontrols and utilities Link with the appropriate library for your platform Windows Unix Mac others coming shortly and compiler almost any popular C compiler and your application will adopt the look and feel appropriate to that platform On top of great GUI functionality wxWidgets gives you online help network programming streams clipboard and drag and drop multithreading image loading and saving in a variety of popular formats database support HTML viewing and printing and much more What is Qt Qt pronounced officially as cute KYOOT although commonly known also as Q T KYOO TEE is a cross platform application development framework widely used for the development of GUI programs in which case it 1s known as a widget toolkit and also used for developing non GUI programs such as console tools and servers Qt is most notably used in Google Earth KDE Opera before 10 60 version OPIE Skype VLC media player and VirtualBox It is produced by Nokia s Qt Development Frameworks division which came into being after Nokia s acquisition of the Norwegian company Trolltech the original producer of Qt on June 17 2008 Qt uses standard C but makes extensive use of a special pre processor called the Meta Object Compiler or moc to enrich the language Qt can also be used in several other programming languages via language bindings It runs on all major platforms and has extensive internationalization support Non GUI features incl
151. or LX240T core for signal processing and control Early release products are LX240T In addition to the features in the Virtex 6 logic such as embedded multipliers and memory blocks the FPGA computing core has four independent banks of LPDDR2 DRAM for data buffering and computing memory There are also a number of support peripherals for IO control and system integration Each XMC may have additional application specific support peripherals Peripheral Features XMC 3 PCI Express interface The X6 cards have an x8 lane PCI Express interface supporting Genl or Gen 2 operation Gen x8 requires speed upgrade to FPGA The XMC 3 host interface integrates with PCI Express systems using eight lanes operating at 5 Gbps Gen2 or 2 5 Gbps Gen1 each that provide up to 8 GBytes sec data rate on the bus full duplex This interface complies with VITA standard 42 3 which specifies PCI Express interface for the XMC module format The PCI Express interface is not available when PCI interface is being used Data transfers between the X6 and host use the Velocia packet system This protocol automates the DMA transfers using a credit based flow control for the packet transfers with the host The system is extensible through the use of virtual channels defined in the logic design A secondary command channel provides independent interface for control and status outside of the data channel that is extensible to custom applications PCIInterface
152. or and to prepare to shut down if necessary because thermal overload may be coming Better to shut down than crash in most cases The temperature failure alert tells the system that the module actually shut itself down This usually requires that the module be restarted when conditions permit X6 400M User s Manual 132 X6 400M XMC Module The data acquisition alerts including over ranges overflows and triggering tell the system that important events occurred in the data acquisition process Overflow is particularly bad data was lost and the system should try to alleviate the problem by unclogging the data pipe or just start over If you get an overrange alert then the data may just be bad for a while but acquisition can continue Modules with programmable input ranges can use this to trigger software range changes Software alerts are used to tag the data Any message can be made into an alert packet so that the data stream logged includes system information that is time correlated to the data Table 22 Alert Types Alert Purpose Timestamp rollover The 32 bit timestamp counter rolled over This can be used to extend the timestamp counter in software Software Alert The host software can create alerts to tag the data stream ADC Queue Overflow The ADC data queue overflowed indicating the the host did not consume the data quickly enough ADC Trigger The ADC trigger went active ADC Overrange An ADC channel was
153. ost process data received from or to be sent to the target DSP What is C Builder C Builder is a general purpose code authoring environment suitable for development of Windows applications of any type Armada extends the Builder IDE through the addition of functional blocks VCL components specifically tailored to perform real time data streaming functions X6 400M User s Manual 13 Introduction What is DialogBlocks DialogBlocks is an easy to use dialog editor for your wx Widgets applications generating C code and XRC resource files Using sizer based layout DialogBlocks helps you build dialogs and panels that look great on Windows Linux or any supported wxWidgets platform Add context sensitive help text tooltips images splitter windows and more What is wxWidgets wxWidgets was started in 1992 by Julian Smart at the University of Edinburgh Initially started as a project for creating applications portable across Unix and Windows it has grown to support the Mac platform WinCE and many other toolkits and platforms The number of developers contributing to the project is now in the dozens and the toolkit has a strong userbase that includes everyone from open source developers to corporations such as AOL So what is special about wx Widgets compared with other cross platform GUI toolkits wxWidgets gives you a single easy to use API for writing GUI applications on multiple platforms that still utilize the native platform s c
154. oth sustained high transfer rates driven by hardware and the ability to send multiple simultaneous data streams across the interface as virtual channels Velocia packets are bundles of VITA packets containing data for the IO and signal processing The packet stream to the PCIe host is enqueued in the VFIFO data buffer and subsequently packetized into Velocia packet for transfer Packets to output devices travel in the opposite direction from the link to the de framer and into the VFIFO data buffer The output IO such as a DAC then consumes the VITA data packets from the queue as required and dissembles them into a data stream for the output device The Alert Log monitors error conditions and important events for management of the data acquisition process Alerts are used to inform the system when an important event such as a trigger or error has occurred When a alert signaled a packet is created to the system that includes vital data messages or other status information The system receives an interrupt and can use the alert information to manage the card in its application The host interacts with the X6 computing core using the packet system for high speed data and over the command channel The packet system is the main data channel to the card and delivers the high performance real time data capability of moving data to and from the module Since it uses an efficient DMA system it is very efficient at moving data which leaves the host syste
155. ource and frequency of the reference clock The behavior of the reference clock and the meaning of these controls are a function specified Clock Source specified above If the clock source is internal the Reference controls specify the source and rate of the reference clock routed to the onboard PLL If the clock source is external the Reference controls specify the source and rate of the sample clock bypassing the PLL In this mode the ratio of the Reference Frequency Clock Frequency is used to control an onboard clock divider supporting sampling at integer submultiple rates of the reference clock The table below summarizes the behavior The physical line driving the external clock reference signal has a multiplexer on it that can select one of two sources for the signal One is the front panel input the second choice is to use the P16 connector clock as the source This signal is driven by Innovative s SBC Comex product line Reference Clock PLL Reference Sample Clock Sample Rate Source Source EXT EXT N A EXT CLK External rate REF_FREQ CLK_FREQ INT EXT N A Onboard Oscillator 100 MHz REF_FREQ CLK_FREQ EXT INT EXT CLK PLL CLK_FREQ INT INT Onboard Oscillator PLL CLK FREQ The Communications section controls the Alert features and the input data packets size Checking the box next to an alert will allow the logic to generate an alert if that condition occurs during data streaming This alert can then
156. overranged DAC Underflowed The DAC FIFO underflowed indicating that the host did not provide data fast enough Table 23 X6 Alerts Alert Packet Format Alert data packets have a fixed format in the system The Peripheral Device Number PDN is programmable in the software and is included in the packet header thus identifying the alert data packets in the data stream The packet shows the timestamp in system time what alerts were signaled and a status word for each alert Header 1 PDN amp Total N of Dwords in packet e g Headers data payload x 1303000 amp 000 amp timestamp_rollover DEDE GNNNNNEN X6 400M User s Manual 133 X6 400M XMC Module e Tempersturesensor ee i ibid i temp alert 29 Memory status x 1303 amp mem alert dout mem alert din lt vfifo3 afull amp vfifo3 aempty amp vfifo3 underflow amp vfifo3 overflow amp vfifo2 afull amp vfifo2_aempty vfifo2 underflow amp vfifo2 overflow amp vfifol afull amp vfifol aempty amp vfifol underflow amp vfifol overflow amp vfifoO afull amp vfifo0 aempty amp vfifoO underflow amp vfifoO overflow Table 24 Alert Packet Format Since alert packets contain status words such as temperature for each packet a software alert can essentially be used to read temperature of the module and so that it can be recorded Software Support for Alerts Applications have different needs for alert processing Aside from
157. ower speed channel is referred to as the command channel For the designer this structure allows the ports to be used primarily as a fast data channel to another card while the command channel provides a means for the control and status words used for flow control system coordination and initialization Customization for the Aurora ports and the data format is described in the X6 FrameWork Logic User Guide for each module X6 400M User s Manual 50 About the X6 XMC Modules Link O 4 lanes MGT RefCIkO 10MHz Ref 1ppm or 0 28ppm optional Figure 21 X6 Aurora Ports on P16 Chapter 25 Connecting Multiple X6 Modules Using Aurora Ports The Aurora ports are integrated into the data plane for the logic thereby allowing ports to communicate with system cards VITA data packets can flow to or from the Aurora cores to components in the FPGA Data is routed as VITA packets to system elements enabling larger channel count systems distributed processing and coordinated system functions Multiple cards can share data in a system over the Aurora ports using either Innovative adapter cards supporting Aurora cabling or in systems supporting an Aurora backplane The example cluster of three X6 modules shows a ring topology implemented using the Aurora ports The modules are mounted to x8 PCIe Adapter P N 80173 or P N 80259 and plugged into a rackmount or desktop PCIe system Each adapter card pins out the ports on SAT
158. p Tab This tab like that for the Snap application allows the user to set up the configuration of the board before starting streaming An additional option on this tab is the Trigger Delay setting This postpones the software start trigger for a given time to allow the application ample time to stream data into the card before starting output Ext Clock Src Communications Velo Packet J V Timestamp Software v Temperature Ox 10000 Configure Setup Waveform e aa Freq MHz Single Channel Two Tone Mode I Enable mande 10 Enabled T Enabled uen MHz Zero Square Amplitude FS active Channel Freq MHz ps0 Amedeo clon X6 400M specific wordset loaded gt No devices detected This tab collects the configuration of the output waveform into one area If the FPGA Waveform is enabled then it plays the time of waveform selected If a Sine wave is chosen then the frequency value is used as the rate of the sine wave In this mode no data is streamed by the software X6 400M User s Manual 83 Writing Custom Applications The software waveform generator uses the configuration selected to generate a single buffer s worth of data indicated by the size of the Velocia packet on the setup tab All active channels are filled with the same data unless single channel is enabled In that case the
159. perature range devices Thermal conduction assembly Conformal coating extended temperature range devices Thermal conduction assembly Wide temperature testing Wide temperature testing Vibration Shock Wide temperature testing Vibration Shock Epoxy bonding for devices Testing Functional Functional Functional Functional Functional Temperature cycling Temperature cycling Temperature cycling Temperature cycling Testing per MIL STD 810G for vibration shock temperature humidity Table 28 X6 400M Environmental Limits Testing for each unit is performed to verify compliance with the specified requirements For levels above L0 functional testing is performed over the specified temperature range and functional testing is verified during vibration tests Shock testing is non operation with post shock functional testing Humidity testing is performed on an engineering proof test basis only Individual units are not 100 tested for humidity Performance Data Analog Input Performance Summary All tests performed at room temperature with forced air cooling Operating temperature for the card 60C Test environment was PCIe adapter card P N 80259 in PC running testbed software using FrameWork Logic X6 400M User s Manual 139 X6 400M XMC Module DC Coupled Inputs Parameter Typ Units Notes Analog Input Bandwidth 250 MHz
160. pplication logic plus a module ready LED By default the Framework Logic image lights the blue LED when the FPGA finishes configuration The green LED indicates that the PCI Express interface link is active LED Ref Des Function Blue D1 ON Module power is ready for use power is good and the FPGA is configured Green LD2 ON PCI Express link is up Red LD1 No specific use Table 28 X6 LED Indicators Custom logic designs can use it for any purpose When using the stock firmware the state of user logic LEDs can be controlled using the Innovative X6 400M Led property LEDs NOT Lit with FrameWork Logic Installed If the two LEDs do not light up with the FrameWork Logic installed that means the PCI Express bus did not connect This is a bus error The card cannot communicate with the system Check installation and contact technical support Chapter 33 JTAG Scan Path X6 modules have a JTAG scan path for the Xilinx devices on the module This is used for logic development tools such as Xilinx ChipScope and System Generator and for initial programming of the PCI FPGA configuration FLASH ROM Nominally there are two devices in the scan chain the Virtex 6 device and the Coolrunner CPLD used to implement the configuration support Optionally the SRAM devices may be included in the scan chain 1f JTAG access is needed for debugging purposes JTAG Device Device Function Number 0 Virtex 6
161. pplicationIo TallyBlock size t bytes double Period Time Differential double AvgBytes BytesPerBlock Process static cast double bytes if Period FBlockRate AvgBytes Period 1 0e6 In this example each received packet is logged to a disk file The packet header and the body are written into the file which implies that a post analysis tool such as BinView must be used to parse packetized data from the file Alternately custom applications may use the Innovative VitaPacketFileDataSet object to conveniently extract channelized data from a Vita formatted packet data source Packets are processed until a specified amount of data is logged or the GUI Stop button is pressed Stop streaming when both Channels have passed their limit if Settings AutoStop amp amp IsDataLoggingCompleted amp amp Stopped Stop counter and display it double elapsed RunTimeSW Stop StopStreaming Log Stream Mode Stopped automatically Log std string Elasped S FloatToString elapsed Chapter 49 The Wave Example The Wave example in the software distribution demonstrates output streaming It will only be included if the board supports streaming out to a DAC or similar device or devices In many ways the Wave example is similar to the Snap example Differences are highlighted in this section X6 400M User s Manual 82 Writing Custom Applications Chapter 50 User Interface The Setu
162. r data buffering and computational memory All of the memory banks are LPDDR2 memory each with an independent connection to the FPGA Logic components in the Framework Logic implement memory controllers used for functions such as data queues pattern generators and computation buffers X6 400M User s Manual 41 About the X6 XMC Modules Chapter 15 DRAM Devices The DRAM devices are LPDDR2 memories These devices are similar to DDR2 with improvements resulting in lower power consumption and more flexibility for migration to larger memories The devices can operate at speeds up to 533 MHz Memory Size Device U23 U25 U26 U27 1GB 256M x 32bit x 4banks Micron MT42L256M32D4KP 25 IT Table 11 X6 DRAM Devices DRAM Connections to FPGA Each DRAM device has a Command Address bus and a data bus These buses connect directly to the FPGA where they are controlled by a memory interface component This logic component provides the interface protocol and timing required to communicate with the DRAM This includes initialization data transaction controls memory refresh and power controls Clock 200 to 533 MHz 10 Command Adare B Figure 18 X6 DRAM Interface Data Buffer DRAM Logic in the FPGA implements a data buffer or Virtual FIFO VFIFO for the system interface Data packets transacted with the host computer are en queued in the VFIFO using the DRAM as the memory for this queue Applicatio
163. re are additional classes to support these packets VeloBuffer to hold packet data and VeloHeaderDatagram to access the header The standard access datagrams will operate on VeloBuffers identically with the original buffers to access the data portion of the packet Chapter 57 Packet Data Format The contents of an X6 Velocia packet 1s not raw data as in earlier systems but a stream of VITA 49 formatted packets that are processed individually These packets can be split across Velo packets so the start of a Velo packet does not mean that a Vita packet header follows The initial data could be part of a previous Vita packet s data Chapter 58 X6 Vita Packets Like Velocia packets Vita packets require information included with them in addition to the data to indicate the data source and other useful information This header is seven words long There is an additional trailer word for each packet that increases the total to 8 words The total size of a Vita packet on the X6 must be a multiple of 4 words long The table below shows a minimal Vita packet it contains only 4 words of data with its 8 words of header information Table 36 Vita Packet Format 0 Header IF Word 1 Header SID Word 2 Header Class OUI Word 3 Header Class Info Word 4 Header Timestamp Integer Seconds Word 5 Header Timestamp Fractional Seconds High Word 6 Header Timestamp Fractional Seconds Low Word 7 Packet Data 0
164. rea Code Number Extension Fax poe Company Name Innovative Integration Address City State County Postal Code Product Board Mita Access Code 935846148 104 Applets Reserve Memory Applet ReserveMemDsp exe Each Innovative PCI based DSP baseboard requires 2 to 8 MB of memory to be reserved for its use depending on the rates of bus master transfer traffic which each baseboard will generate Applications operating at transfer rates in excess of 20 MB sec should reserve additional contiguous busmaster memory to ensure gap free data acquisition To reserve this memory the registry must be updated using the ReserveMemDsp applet If at any time you change the number of or rearrange the baseboards in your system then you must invoke this applet to reserve the proper space for the busmaster region See the Help file ReserveMemDsp hlp for operational details Data Analysis Applets Reserve Memory for Dsp Baseboards f si Number Installed Matador family al Type System 2048 y BM Region Size KB 2048 Rsv Region Size KB Configualim 1 Total physical memory MB 255 Non paged pool size MB 4 Status Ok Update Help Exit Ready Binary File Viewer Utility BinView exe BinView is a data display tool specifically designed to 3j BinView c vista vistat 1 dump bin allow simplified viewing of binary data stored in data Gc m
165. rget you can use the Finder program to blink the LED on each Target Once you have selected the BIT file press the load button to begin programming The progress bar shows that the programming is underway and when it is completed Programming a few minutes due to the size of the configuration bitstreams used by the Virtex 6 device DO NOT TURN OFF THE HOST COMPUTER OR RESTART IT UNTIL PROGRAMMING IS SUCCESSFULLY COMPLETED Once the EEPROM is reprogrammed the X6 module must be power cycled for reconfiguration to take place and the new bitstream loaded into the Virtex 6 device Chapter 40 Rescuing the Card When the Logic Image is Bad If an invalid image is programmed into the EEPROM or the process is interrupted before completion for any reason the Virtex 6 may no longer configure properly or may not communicate properly on the PCle bus If this occurs then the card can be booted from the backup image or can be programmed using a JTAG cable X6 400M User s Manual 66 About the X6 XMC Modules The backup image or golden image may be used to boot the X6 card by installing a jumper on JP1 This forces the logic loader to load the X6 logic with the backup image The card should boot with the backup image then allowing the primary image to be reprogrammed using the EEPROM applet If the backup image is bad or not available then the card can be programmed with a Xilinx JTAG using a known good image followed by a warm boot of the
166. riphLib ver rel 1586 rpm Board files and examples X3 Servo X3 Servo LinuxPeriphLib ver rel i586 rpm Board files and examples SBC ComEx Sbc ComEx LinuxPeriphLib ver rel i586 rpm Board files and examples Unpacking the Package As root type rpm i h X5 400 This extracts the X5 400 board files into the Innovative root directory Use the package for the particular board you are installing Creating Symbolic Links The example programs assume that the user has created symbolic links for the installed board packages A script file is provided to simplify this operation by the Malibu Red package In the MalibuRed KerPlug directory there is a script called quicklink quicklink X5 400 These commands will create a symbolic link x5 400 pointing to X5 400 1 1 LinuxPeriphLib 1 1 4 i1586 rpm 1 4 This script can be moved to the user s bin directory to allow it to be run from any directory X6 400M User s Manual Installation on Linux Completing the Board Install The normal board install is complete with the installation of the files The board driver install is already complete with the loading of the Malibu Red package If there are any board specific steps they will be listed at the end of this chapter Linux Directory Structure When a board package is installed its files are placed under the usr Innovative folder The base directory is named after the board with a version number attached for e
167. s Manual 165 X6 400M XMC Module X6 400M User s Manual 166
168. s sonet sta aiea Coin eau ree a inl o our coute tend snuedheaturiyhuna Doy EEr EEE veu t E 85 Start ROA EE A ad 86 Data Required Byent Erandler ohio reg feat eoe ee eu oa buta did 89 FillWaveformBuffer eoo a e a E RP OD Pho do AES 90 Developing Host ApplicatiGHS id VEU RON S Fe en VER YE Re FORO n ae x JJ Borland Turbo CHE LR Other CONSID EAL ONS nario taa no ala os ida Microsoft Visual Studio 200 0 dd DIALOG Blc sioi sE e aoas seps ei asar A A A E A Chapter 5 Vita Packet Format anni iO OVERVIEW NN X6 VelociaPacketS sisciscssescisscissesscvseseadecsassssevssveadecsesessecssbeedectascsscesstsovesbasesiecsesvestacessesssstesssseacessdecasseetses DO Packet Header FOrMat PR DO Packet Data Formada do UA A LP Packet Header QUSE EROR Rm 100 VITA Leader TE SvOordo eoo recen a ea 100 META Headet SID Word oiu vesucesees eee eee caa Oen Eh eoa ie eo e RO cir et ee taedas emia eive esa Po RE EE qued 101 VITA Header Class QUI Word senesni eed ibat eto teiweh eo eenaa aea shat Maa AEI SaS Nea qoin oda 102 Vita Header Class Info WOES ete cun strate A Eod 102 Vita Header Timestamp Integer Seconds Word sse 102 Vita Header Timestamp Fractional Seconds High and Low Words esses 102 Vita Packet Trailer Horii a met db 102 WT Ae PEAT A vette T eio as v etes ced e E ooo caus ch E NC 102 State and Event Bits and Enable Bliss arias rot E opa pce t A t e ete E EE 102 Bits 202 A ties
169. ser s Manual 32 Hardware Installation The PCI Express slot must be PCI Express 1 0a compatible and be able to map the following resources Table 2 Required PCIe Resource Allocations Required PCIe Resources BARO IMB Memory BARI 64K B Memory 1 Interrupt When you first plug in the module it will then be found and the driver should be installed for the module The standard driver resides in the Innovative drivers directory after software installation The XMC module may be used an any PCI Express slot supporting 1 or more lanes Innovative offers a line of adapters for use with the X6 series which allow the module to be used in PCI and cPCI environments These adapters may limit the number of lanes available to the X6 for host communication depending on their design Power Considerations Each XMC should be reviewed for its specific power cooling and any special mechanical considerations For each module the power consumption and required power supplies are shown in the specific discussion for that module For desktop applications you MUST provide forced air cooling with 5 10 CFM capability The air must blow directly on the Virtex 6 device The X6 XMCs are designed to operate over the typical commercial temperature range of 0 to 70 C but this relies on sufficient forced air cooling for most installations and modules At the lower temperatures it is also required that the environment be non cond
170. sing on card 10MHz reference 1ppm 0 28 ppm option is available Jitter 0 7 ps RMS Lock Time 25 ms Max Table 20 GTX PLL Reference Clock Characteristics The GTX can also receive a clock from P16 if the logic is recompiled to use the alternate GTX clock input This clock input directly connects to the GTXs The IO standard is LVDS For most applications this clock is in the range of 125 to 250 MHz X6 400M User s Manual 49 About the X6 XMC Modules 0 3V min 2 2V max Parameter Value Notes Frequency Range 62 5 to 650 MHz Rise Fall Time 200 ps Typical Duty Cycle 45 55 Lock Time 1 ms Max Input common mode voltage 1 2V typical For differential input voltage 350 mV Input Differential Voltage 1000mV max 100 ohm differential termiantion 100mV min Terminattion 100 ohms nominal Table 21 GTX Alternate Reference Clock Input Characteristics Chapter 24 Aurora Ports The Framework Logic implements dual Aurora communication cores for the secondary ports on P16 The two Aurora links are 4 lanes each providing up to 2GB s maximum transfer rates 5 Gbps operation full duplex The ports are independent in the FrameWork Logic but can be paired into a single 8 lane port in the logic design The Aurora ports support multiple virtual channels across the link enabling both high speed data transfer as well as low speed command control and status functions between cards The sl
171. some data and log it to disk This should let you verify that the module can acquire the data you want and give you a quick start on deciding what sample rates to use how to trigger the data acquisition best for your application and just get familiar with using the module The program also shows how to use BinView a data analysis and viewing program by Innovative that will let you see what you acquired in detail Both time domain and frequency domain data can be viewed and analyzed Data can also be exported to programs like Excel and MATLAB for further analysis Before you begin to write software taking a look at SNAP will allow you see everything working You can then look at the code for SNAP and modify it for your application or grab code from it that is useful For the outputs the WAVE program provides similar functionality WAVE generates output waveforms of various types including playback from files with controls for DAC clock rate and triggering A waveform generator in the FPGA can also be selected that can generate high frequency waveforms for test X6 400M User s Manual 135 X6 400M XMC Module Getting Good Analog Performance The X6 400M is capable of digitizing very high frequency signals To maximize signal to noise ratio and spur performance it is important to use do the following e Use only low jitter clock sources The higher the input output frequency the more sensitive the system will be to clock jitter e Ba
172. stomization Configure Alert Enables Module ConfigureAlerts Settings AlertEnable Alerts and starting the Stream are the same as in Input only mode We call a board specific function to handle the details Disable prefill if in test mode Stream PrefillPacketCount Settings TestGenEnable 0 PrefillPacketCount Fill Waveform Buffer if streaming if Settings TestGenEnable false FillWaveformBuffer Like all of our Wave examples streaming mode is handled by precalculating a wave pattern into a single buffer that is retransmitted each time data is required The calculation of the buffer itself is a little more involved but in the end there is a single Velo buffer that is repeatedly sent Trig AtStreamStart Start Streaming X6 400M User s Manual 87 Writing Custom Applications Stream Start Log Stream Mode started return true void Applicationlo StopStreaming if IsStreaming return if FStreamConnected Log Stream not connected Open the boards return Stop Streaming Stream Stop Timer Enabled false Disable test generator if Settings TestGenEnable Module SetTestConfiguration false Settings TestGenMode Trig AtStreamStop The stream stop process remains simple The trigger manager periodic timer and data stream objects are all stopped In addition the test generator is also turned off Data Required Event H
173. tachometer input to be active An example fan control circuit is shown in the following figure The fan connects to the circuit through the 3 pin header since it is usually mounted to the chassis A power MOSFET Fairchild Semi NDS355N is used for the fan motor control The FAN CTLZ signal is the PWM from the LM96193 and is OR d with the XMC_PRESENT signal When both are true the gate to the MOSFET is ON This particular MOSFET has an on threshold of 2V and a current capacity Id of 1 7A This allows the power MOSFET to turn on with a 3 3V logic signal and control a moderate size fan Check your fan specification for current requirement The fan tachometer feedback to the LM96193 is pulled up to 3 3V on the module using a 1K ohm resistor X6 400M User s Manual 56 About the X6 XMC Modules XMC0 FAN TACH XMCO_PRESENT Q5 4 XMCO_FAN A ne NDS355N zi FAN 1 4 H3 jpig DGND E HDR1X2V Figure 25 Example Fan Control Circuit Conduction Cooling If forced air cooling is not used conduction cooling is another method of dissipating the module heat A thermal plane in the card is attached to thermal conduction surfaces on each side of the module The thermal plane has NO electrical connection in the module and cannot be used as a ground The card can then be cooled by mounting the card on host card that supports conduction cooling per VITA specification 20 The conduction cooling features are a subset of the VITA 20 specifi
174. tem integration Timing and triggering Flexible clocking and synchronization features for I O including front panel clock or reference system reference and PPS inputs through J16 connector Data buffering and Computational Memory Four 1GB LPDDR2 DRAM devices are used provide data buffering processor memory and computation memory for the Application FPGA Alert Log Monitors system events and error conditions to help manage the data acquisition process Temperature and Power Monitoring Autonomous temperature and power monitoring over temperature protection for the module shuts down power temperature reporting and alerts for monitoring power supply health monitoring Table 6 X6 XMC Family Peripherals Chapter 7 X6 Computing Core The X6 XMC module family has an FPGA based computing core that controls the data acquisition process provides data buffing and host communications The computing core consists of a Xilinx Virtex 6FPGA one bank of DDR2 DRAM 4Gbits in a x64 configuration and two banks of QDR2 SRAM 32Mbits total in two x32 dual ported banks The FPGA uses the memories for data buffering and computational workspace Table 7 X6 Computing Core Devices Feature Device Part Number Application Logic FPGA Xilinx Virtex 6 SX315T XC6VSX315T 1FFG1156C some cards use 2 Xilinx Virtex 6 SX475T XC6VSX475T 1FFG1156C some cards use 2 Xilinx Virtex 6 LX240T XC6VLX240T 1FFG1156
175. ter A D performance X6 400M User s Manual 125 X6 400M XMC Module Input Frequency atts 500 MHz Input Amplitude 0 15 V ff BV Peak to peak Input Capacitance 15 pF Ps Excludes cabling Table 16 External Clock Input Requirements CDCDE72010 SPI Port The CDCDE72010 PLL Buffer device is configured through its SPI serial port This port is mapped to the PCI Express bus as a memory mapped register at address BAR1 0x801 Writes to this register transmit to the CDCDE72010 device reads from this address first transmit an address to the CDCDE72010 device then receive the current value Before any read write is performed the SPI READY bit should be read to and must be true 1 Bits Function 31 0 SPI write data Table 17 PLL SPI interface 0x801 r w The CDCDE72010 has an extensive set of registers in the device for configuration and status Consult the CDCDE72010 data sheet for details VCXO PC Port This register is an an I2C port that programs the VCXO for the PLL The VCXO is a Silicon Labs SI571 device offering a programmable center frequency controlled over its I2C port Software functions in Malibu tools provide support for programming this device including calculation of its register settings for use This I2C port is implemented using software controlled protocol This means that the I2C port SDA and SCL connections must be controlled with the software to implement the I2C interface timing and co
176. the Applicationlo object begins the process of opening the board driver and setting up the board for a run The first thing done is to link Malibu software events to callback functions in the applications by setting the handler functions Malibu uses events to allow functions to be plugged into the library to be called at certain times or in response to certain events detected Events allow a tight integration between an application and the library Configure Trigger Manager Event Handlers Trig OnDisableTrigger SetEvent this amp ApplicationIo HandleDisableTrigger Trig OnExternalTrigger SetEvent this amp ApplicationIlo HandleExternalTrigger Trig OnSoftwareTrigger SetEvent this amp ApplicationIo HandleSoftwareTrigger This code attaches event handlers associated with the various trigger conditions For example the OnDisableTrigger event fires when triggering is disabled When Malibu detects that condition it calls the Applicationlo HandleDisableTrigger method providing a means of user specific processing under that condition In a similar manner the events hooked below are called at strategic times during data streaming Configure Module Event Handlers Module OnBeforeStreamStart SetEvent this amp ApplicationIo HandleBeforeStreamStart Module OnBeforeStreamStart Synchronize Module OnAfterStreamStart SetEvent this Applicationlo HandleAfterStreamStart Module OnAfterStream
177. the bulk movement of data most applications require some means of handling special conditions such as post processing upon receipt of a stop trigger or closing a driver when an acquisition is completed When the alert system is enabled the module logic continuously monitors the status of the peripheral usually analog hardware present on the baseboard and generates an alert whenever an alert condition is detected It s also possible for application software to generate custom alert messages to tag the data stream with system information The Malibu software provides support for alert configuration and alert packet processing See the software manual for usage Tagging the Data Stream The Alert Log can be used to tag the data stream with system information by using software alerts This helps to provide system level correlation of events by creating alert packets in the data stream created by the host software Alert packets are then created by the X6 module and are in the stream of data packets from the module For example it is often interesting when something happens to the unit under test such as a change in engine speed or completion of test stimulus X6 400M User s Manual 134 X6 400M XMC Module Calibration Each X6 400M is calibrated as part of the production testing The calibration results are provided on the production test report with each module The results of the calibration are stored in the on board EEPROM memory These
178. the next trigger edge is detected This mode is well suited for applications such as spectral analysis using fixed input buffers submitted to FFTs The module supports one or more test modes for module debugging and system test The Test Counter Enable is used to turn on test mode and substitutes a ramp signal with channel number in the upper byte of the data The Decimation section sets up the decimation logic to discard data reducing the incoming data rate Stream Tab The two buttons in the button bar start and stop data streaming Press the running man button to start streaming data Press the stop button to stop streaming unless the stream has stopped itself When streaming the status bar data is collected and displayed This includes a count of the data samples received the data rate the measured temperature of the board logic and the PLL locked indicator bit value Data is logged to an intermediate file that holds the Velocia buffers with the Vita Buffer data This can be read by Binview in native mode for analysis The Post Processing button will extract the data from the Intermediate file and convert it into X5 compatible data files for use with older versions if desired The Auto Stop option determines if data streaming stops after collecting the given number of points a Snapshot of data or continues to stream forever until manually stopped X6 400M User s Manual 72 Writing Custom Applications fr v Hii X6
179. tive includes a variety of technical support facilities as part of the Malibu toolset Telephone hotline supported is available via Hotline 805 578 4260 8 00AM 5 00 PM PST Alternately you may e mail your technical questions at any time to techsprt innovative dsp com Also feel free to register and browse our product forums at http forum iidsp com which are an excellent source of FAQs and information submitted by Innovative employees and customers Innovative Integration Web Site Additional information on Innovative Integration hardware and the Malibu Toolset is available via the Innovative Integration website at www innovative dsp com Typographic Conventions This manual uses the typefaces described below to indicate special text Typeface Meaning Text in this style represents text as it appears onscreen or in code It Source Listing also represents anything you must type Boldface Text in this style is used to strongly emphasize certain words Text in this style is used to emphasize certain words such as new Emphasis terms Cpp Variable Text in this style represents C variables Text in this style represents C identifiers such as class function Cpp Symbol or type names KEYCAPS Text in this style indicates a key on your keyboard For example Press ESC to exit a menu Text in this style represents menu commands For example Click Menu Command View Tools Customize X6
180. to other system level events Alerts for critical system events such as triggering data overruns and underruns analog overrange and thermal warnings provide the host system with information to manage the module The Alert Log creates an alert packet whenever an enabled alert is active The packet includes information on the alert when it occurred in system time and other status information The system time is kept in the logic using a 32 bit counter running at the sample clock rate Each alert packet is transmitted in the packet stream to the host marked with a Peripheral Device Number corresponding to the Alert Log The Alter Log allows X6 modules to provide the host system with time critical information about the data acquisition to allow better system performance System events such as over ranges can be acted on in real time to improve the data acquisition quality Monitoring functions can be created in custom logic that triggers only when the digitized data shows that something interesting happened Alerts make this type of application easier for the host to implement since they don t require host activity until the event occurs Types of Alerts Alerts can be broadly categorized into system IO and software alerts System alerts include monitoring functions such as temperature time stamp rollover and PLL lost These alerts just monitor that the system is working properly The temperature warning should be used increase temperature monit
181. topped automatically Elasped 0 733 Starting Post Processing Ending Post Processing Figure 4 SNAP Example Sample Clock Controls Controlling the PLL How To Set the Sample Rate Generator to a Specific Frequency To generate the settings for a desired sample rate the PLL and VCXO are configured generate the closest possible frequency while meeting several restrictions PLL Parameter Constraint On card PLL reference 10MHz with 0 5 ppm stability External Reference Input Range 1 500 MHz VCXO Center Frequency Ranges Programmable 0 001 Hz resolution 10 to 945 970 to 1134 1213 to 1417 MHz X6 400M User s Manual 121 X6 400M XMC Module Table 11 Phase Comparator Set point 100 kHz Sample Rate Generation Parameters Step Calculation 1 Find an integer multiple even numbers only of the desired sample rate that is within the tuning range of the VCXO where D 1 2 4 6 8 10 12 14 16 18 20 24 28 32 64 80 Fvco D Fs Calculate the VCXO internal frequency to check operating mode Fpco Fvco HS DIV NI select HS DIV 4 5 6 7 9 or 11 N1 1 to 128 even only so that 4850 lt Fpco lt 5670 MHz HS DIV N1 gt 6 for 10 lt Fyco lt Fvco max MHz Set the VCXO center frequency RFREQ Fpco 114 285 MHz Use 38 bit math with 10 decimal places and 28 fractional bits Calculate PLL settings to generate the sample frequency
182. tor on the front panel The DC coupled output circuitry performs a current to voltage conversion filters the output and drives the output The DC coupled output path can provide gain adjustment by changing resistors on the output amplifier The output is 50 ohm terminated with an SMA output connector on the front panel The following figures show the schematics for the outputs X6 400M User s Manual 113 X6 400M XMC Module DAC_BIASO AGND R408 24 9 0 1 R500 L65 Les AA ned J9 UTA2 t INIT 1 Pa RRA SOR OCT J 1 49 9 12nH 12nH C639 C640 C641 i me 4 ort 90 1 22pF 6 8pF 22pF AGND AGND AGND Q AGND 5V_2 DAC BIASO AGND IOUTA2 R507 4 T 3 AGND AGND DNBAC_BIASO IOUTA1 R510 0 1 R511 DNP Jo OUT DAC BIAS1 R513 249 0 196 R514 374 ono R515 5v3 24 9 0 1 o jours Rate 100 0 1 m Pe R520 o I CNA 518 100 901 143 OUTBZ _ R519 100 0 196 1 J10 our 4 499 12nH 12nH moz AGND q R521 R523 C645 C648 C047 137 uss 24 90 1 249 0 19 22pF 6 8pF 22pF 8V_3 AGND AGND AGND 2 o ak GND 5V_3 DAC_BIAS1 AGND AGND IOUTB R525 DNP 4 T4 3 R526 DNP Ji0 OUT R52 DN AC BIAS IOUTB2 R530 DNP amp ano Figure 1 X6 400M DAC Output Circuitry Output bandwidth measurements are shown in the data section of this chapter Output Range and Conversion Codes DC Coupled Outputs Eac
183. tput DC 1 Vp p Standard on X6 400M calibration results may Range limit input range to 0 99 of full scale nominal Output AC 900 mVp p Standard on X6 400M calibration results may Range limit input range to 0 99 of full scale nominal Accuracy Offset AC or DC lt 10 mV Factory calibration average of 64K samples Gain AC or DC 0 02 Factory calibration average of 64K samples Analog Ground AC or DC 0 26 mVp p Playback wave of all 0 s Fs 999 994 MSPS Output Noise 256K samples 540 MHz low pass filter X6 400M User s Manual 144 X6 400M XMC Module Test Group Parameter Output Measured Units Test Conditions Coupling Ground AC or DC 100 dB Playback wave of all 0 s Fs 999 994 MSPS Noise Floor 256K samples 540 MHz low pass filter Analog Crosstalk AC or DC lt 90 dB Fs 1000 MHz Output Fout 0 95V p p output 5 1 MHz AC or DC lt 85 dB Fs 1000 MHz Fout 0 95V p p output 70 MHz Analog Bandwidth DC Coupled gt 220 MHz 3 dB NO SINC CORRECTION Response AC Coupled 450 MHz 3 dB NO SINC CORRECTION DC Coupled DAC Output Amplitude vs Fout Power dBm Normalized Pow er dBm Fout MHz 5 1 20 1 50 1 100 1 150 1 200 1 250 1 300 1 350 1 400 1 3 94 3 98 3 77 3 24 2 37 1 22 0 44 2 65 5 58 9 76 0 0 04 0 17 0 7 1 57 2 72 3 5 6 59 9 52 13 7 Figure 11 Frequency Response for 5 MHz to 500 MHz span DC Coupled Output Fs 500 M
184. u up pak pat jab po pes e ugs far dE p 1 0 9 8 7 16 5 4 3 2 gt ESA 578 fess 140 ES 129 TI CO Enables 1111 State and Event indicators Padding in E Context Packet count bytes State and Event Bits and Enable Bits Enable bit position State and event Indicator Indicator name bit position 31 19 Calibrated Time 30 18 Valid Data 29 17 Reference lock 28 16 AGC MGC Indicator 27 15 Detected Signal indicator 26 14 Spectral inversion 25 13 Over range indicator 24 12 Sample Loss over run Setting the appropriate bit in the Enable field will cause the State Event bit to follow the signals given in the table These will flag if the enabled conditions occur in the current Vita packet X6 400M User s Manual 101 Vita Packet Format Bits 20 23 These should always be set to 1 Context Packet Count This number tells which context packet is associated with this packet Context packets can give slowly changing information such as temperature readings into a data stream without burdening each data packet with data that is unlikely to be different from packet to packet Padding The Padding field indicate how many padding bytes were added to align the current packet to a 4 word boundary Padding values can be from 0 no padding to 15 1 data byte valid in the last 4 words Table 39 Padding Example Data n 3 Data n 4 Data n 5 Data n 6 Pa
185. ude SQL database access XML parsing thread management network support and a unified cross platform API for file handling Distributed under the terms of the GNU Lesser General Public License among others Qt is free and open source software All editions support a wide range of compilers including the GCC C compiler and the Visual Studio suite So what is special about wxWidgets compared with other cross platform GUI toolkits Qt gives you a single easy to use API for writing GUI applications on multiple platforms that still utilize the native platform s controls and utilities Link with the appropriate library for your platform Windows Unix Mac and compiler GNU C and your application will adopt the look and feel appropriate to that platform On top of great GUI functionality Qt gives you online help network programming streams clipboard and drag and drop multithreading image loading and saving in a variety of popular formats database support HTML viewing and printing and much more X6 400M User s Manual 14 Introduction What is Microsoft MSVC MSVC is a general purpose code authoring environment suitable for development of Windows applications of any type Armada extends the MSVC IDE through the addition of dynamically created MSVC compatible C classes specifically tailored to perform real time data streaming functions What kinds of applications are possible with Innovative Integration hardware Data acquisition
186. ule IncomingBusMasterSize BmSize Meg Module OutgoingBusMasterSize 1 Meg Module Target Settings Target Open Device try Module Open X6 400M User s Manual 76 Writing Custom Applications std stringstream msg msg lt lt Bus master size lt lt BmSize lt lt MB Log msg str catch Innovative MalibuException amp e UI gt Log Module Device Open Failure UI gt Log e what return cateh a UI gt Log Module Device Open Failure Unknown Exception Opened false return Module Reset Ul gt Log Module Device opened successfully Opened true This code shows how to open the device for streaming Each baseboard has a unique code given in a PC For instance if there are three boards in a system they will be targets 0 1 and 2 The order of the targets is determined by the location in the PCle bus so it will remain unchanged from run to run Moving the board to a different PCIe slot may change the target identification The Led property can be use to determine the association between a target number and the physical board in a configuration Connect Stream Stream ConnectTo amp Module Ref StreamConnected true UI gt Status Stream Connected Once the object is attached to actual physical device the streaming controller associates with a baseboard by the ConnectTo method The variable Module is a
187. ule LogicWarningTemperature 70 0 Read current failure temperature float t Module LogicFailureTemperature S if the module is in thermal shutdown bool state Module Failed System Thermal Design The X6 RX can dissipate upwards of 25 watts depending on the features in use and details of the logic design such as the rate of data processing Forced air cooling may be required depending on the power dissipation and the ambient operating temperatures This requirement is highly application dependent and must be evaluated for each application and installation Fan Control The X6 temperature monitor integrates a fan control circuit with the temperature sensor This fan control has a Pulse Width Modulated PWM output to control fan speed and tachometer input from the fan The fan control signals are on J15 connector see hardware chapter for pinout The LM96193 must be programmed to set the PWM resolution and tachometer scale factor which is unique for most fans This programming is done over the SMB bus connection to the Virtex 6 FPGA Consult the National Semiconductor LM96193 documentation for details The fan PWM output is NOT capable of driving most fans A separate power transistor must be used with the PWM signal as the control A 1K pullup on the PWM signal makes the fan ON by default if the LM96193 is not programmed The fan tachometer signal is a direct input to the LM96193 The LM96193 must be programmed for the
188. vO DIO N15 vO DIO_P17 vO DIO N17 vO DIO_P19 vO DIO N19 vO DIO_P21 vO DIO_N21 vO DIO_P23 vO DIO_N23 vO DIO_P25 vO DIO_N25 vO DIO_P27 vO DIO_N27 vO DIO_P29 vO DIO_N29 vO DIO_P31 vO 162 X6 400M XMC Module Signal Direction DIO_N30 TO Xilinx JTAG Connector Pin 63 Pin Signal Direction 64 DIO N31 vO JP3 is used for the Xilinx JTAG chain It connects directly with Xilinx JTAG cables such as Parallel Cable IV or Platform USB Connector Types Number of Connections Connector Part Number Mating Connector 14 pin dual row male header 2mm pin spacing right angle 14 arranged as 2 rows of 7 pins each Samtec TMM 107 01 L D RA or equivalent AMP 111623 3 or equivalent Board edge JP1 Figure 31 X6 400M JP3 Orientation board face view X6 400M User s Manual Board f Pin 13 Pin 14 W CU Pin2 Figure 32 X6 400M JP3 Orientation board top edge view 163 X6 400M XMC Module Pin Signal Direction 1 3 5 7 9 11 13 Digital Ground Power 2 1 8V Power 4 TMS I 6 TCK I 8 TDO O 10 TDI I 12 14 No Connect Table 39 X6 400M JP3 Xilinx JTAG Connector Pinout FLASH Boot Image Select JP1 is used to select the logic image used to boot the module JP3 Strapping Boot Image None Application Logic Image 1 2 Backup Image Golden Image Table 40 X6 400M JP
189. vent counting in samples 10 Real time timestamp counts in increments of 1 picosecond since last integer seconds event Not supported 11 Free running count timestamp No relation to the integer seconds field Counts in samples handled internally VITA Header SID word a 33 d a 2 2 px I gH pu pat fa a pp gp a PS PR ee LO ES 110 9 8 7 6 4 3 2 1 0 9 87 16 5 4 3 2 1 0 Destination Mask Stream ID The VITA 49 Stream Id field is split into two 16 bit fields Destination Mask and Stream ld The Destination Mask will help route packets to their destinations ie PCIE Aurora 0 or 1 etc The Stream ID will be used much like the peripheral ID is for Velocia packets to identify the source or meaning of the data in the packet X6 400M User s Manual Vita Packet Format VITA Header Class OUI Word This word is reserved Vita Header Class Info Word This word is reserved Vita Header Timestamp Integer Seconds Word This word contains the integer portion of the timestamp data Vita Header Timestamp Fractional Seconds High and Low Words These words contain the fractional portion of the timestamp data Chapter 60 Vita Packet Trailer Format VITA Trailer Word Sa 222 22 22 E220 E20 248 162 2 iil pb p
190. wering the machine back on to make certain everything is plugged in correctly Thank you from Innovative Integration 1 805 578 4260 www innovative dsp com Shutdown Now Shutdown Later Figure 6 Installation complete Click the Shutdown Now button to shut down your computer Once the shutdown process is complete unplug the system power cord from the power outlet and proceed to the next section Hardware Installation Hardware Installation Now that the software components of the Development Package have been installed the next step is to configure and install your hardware Detailed instructions on board installation are given in the Hardware Installation chapter following this chapter IMPORTANT Many of our high speed cards especially the PMC and XMC Families require forced air from a fan on the board for cooling Operating the board without proper airflow may lead to improper functioning poor results and even permanent physical damage to the board These boards also have temperature monitoring features to check the operating temperature The board may also be designed to intentionally fail on over temperature to avoid permanent damage See the specific hardware information for airflow requirements After Power up After completing the installation boot your system into Windows Innovative Integration boards are plug and play compliant allowing Windows to detect them and auto configure at start up
191. xample the version 2 0 X5 400 RPM extracts into usr Innovative X5 400 2 0 This allows multiple version of installs to coexist by using a symbolic link to point to a particular version Changing the symbolic link changes with version will be used Under the main directory there are a number of subdirectories Applets The applets subdirectory contains small application programs that aid in the use of the board For example there 1s a Finder program that allows the user to flash an LED on the board to determine which board is associated with a target number See the Applets chapter for a fuller description of the applets for a board Documentation This directory contains any documentation files for the project Open the index html file in the directory with a web browser to see the available files and a description of the contents Examples This directory and its subdirectories contain the projects source and example programs for the board Hardware This directory contains files associated with programming the board Logic and any logic images provided X6 400M User s Manual 28 Hardware Installation Chapter 4 Hardware Installation The X6 XMC cards may be used on a variety of host cards supporting an XMC 3 PCI Express VITA standard 42 3 compatible site XMC P16 is also used for system integration including use as a dedicated data channel Compatible Host Cards X6 XMC cards are compatible with the VITA 42 3 PCI Express
192. zed in the preconfiguration need to have their settings applied to the board object here In general the items that need to be set up are the clock timebase configuration and the DAC configuration particularly the enables X6 400M User s Manual Writing Custom Applications void ApplicationIlo StreamPreconfigure Log Preconfiguring Stream Make sure if Wave Generator is in single channel mode we have a valid active channel filled in if Builder Settings SingleChannelMode int active channels 0 for unsigned int i 0 i lt Settings ActiveChannels size i if Settings ActiveChannels i true false active channels if active channels 3 active channels 4 can t do a true 3 channel run promote to 4 if Builder Settings SingleChannelChannel active channels Log Error Invalid Active Channel selected in Single Channel Mode return Set Channel Enables Module Output ChannelDisableAl1 for unsigned int i 0 i lt Module Output Channels i bool active Settings ActiveChannels i true false if active true Module Output ChannelEnabled i true Clock Configuration Route ext clock source IX6ClockIo IIClockSelect cks IX6ClockIo cslFrontPanel IX6ClockIo cslP16 Jj odule Clock ExternalClkSelect cks Settings ExtClockSrcSelection Route reference odule Clock Reference ref Sett

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