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X3-2M User's Manual

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1. 30 Comp tationa SRAM EE 31 Data Buffer SRAM nepote tod RU RHENO app aii E E RO ED eH E EEE EEE ah 31 EEPROM m 3 Digital VO 5 1 o lives hee ST OD Re S IBRHHS DU nee er qae te are ado S AERA 32 Software Support nente arn RERO RETIRER IRE SN MEA IURI DEENEN 32 Hardware Implementar IO een dri p t RARI M GERTEGEU HERR 32 Front Panel DIO minena a eege A RHET ee E eee 33 Hardware Implementar epe ete eH erm er n tr e E RR A RO HIR 34 Digital UO TIME nri te aeri e ui A UO E ERE RAPERE HORRORE 35 Digital IO Electrical Charactertsttces ene enne nette eaaa tnnt eataa aans ipaa 36 Notes om Digital IO Use A E ee EIE NER 37 Serial EEPROM sinter face iade as ance te ee etre epp EE e EE mbt uc aL e dtes PUR ee ois 37 Thermal Protection and Monitoring sse enne nnne nennen enne nere nter tren nnne nnn ener enne nn 38 Thermal Failures eege lee Beete 40 LED Indicators a a ci t LU I e Ute emerunt i aes Mente n issue os 40 JTAG Scam Rath ye tein MI dette tester meteteste sities es ge 41 Frame Work DLogle 2n suene o edendi nmn EE 41 Integrating with Host Cards and Systems siae ied rte gereest 42 Writing Custom vli M H Snap Example e EEUU e RB EUIS RH RI E ge EAT 44 JS 44 Program Design P
2. 45 The Host Application eie dee Hee IRE GER n de ER e IRI ee dass EE ER C EL e deeds 45 User Interface itera uiu eoi eer eri ere to oie pata ique eee andi eun 45 Logic Io TE 45 A 46 Data Streaming icing nee t e UR EH EE Cuca UE TRAE IS ER Eee E REG RO e C RT RE RE URN 48 Ram E 49 EEPROM ACCESS n BEER a bc Eege ang er RES 49 ID PIGHIO o O E EE A A A 49 Host Side Program Organ zapen 49 ApplicationlQs EE 50 EIA EE 50 ENEE 53 Starting Data EE 55 Handle Data Requited ec xot en NEN ERR e tacet d dau ie ied 58 EP Erem Ee o eeu ennt e edid e e qe RR ee ut e EN eed 60 Developing Host DIUI O A OZ COMMON Ap re e eet ees e a ree eR EO PR EE EET 62 AMIANTO A 62 Reserve Memory Applet Beservchemlisp ege 63 Data Analysis Applets eerte ee E pte bee reete etude et epe tete b ed ERR 63 Binary File Viewer Utility BmNiew ee 63 X3 2M User s Manual PEPTOM i 64 Findet ernennen ni ene ERRES EOE E EEEE E EE SEET e 64 Logici Eoadet uie EN O CR ao EAE RO HR we eee ee 65 X3 2M OO TIntroductioBs e CR e etel e d es 66 Hardware Eeatutes z iie e e t EE 68 A D Convetters4 ga oet dace aeta teste eie Re estet e o ar hh e ete TA 68 Input Range and Conversion Code 70 Dr ving the A D Inputs ete m P PE ERR EE P PEE DG E VEG PIRE er RE ee
3. X3 2M Slave X3 2M ge A D 24 35 Slave X32M e A D 35 47 Slave Figure 3 Example 64 channel System Architecture To synchronize the system the following steps must be followed 1 Software configures the cards for sync master slave 2 Acommon clock is provided to the X3 2M cards If a common reference clock is used then the X3 2M cards must be configured to use an external reference then the PLL for each card must lock to this signal Do not proceed until all cards in the system have their PLL locked 3 Master releases the sync For best DC accuracy wait 5 minutes for thermal stabilization 4 The cards are now ready to collect data or playback At this point trigger can be fired at any time to control the data acquisition process FrameWork Logic Functionality The FrameWork Logic implements a data flow for the X3 2M that supports standard data acquisition functionality This data flow when used with the supporting software allows the X3 2M to act as a data acquisition card with 2MB of data buffering and high speed data streaming to the host PCI Express The example software for the X3 2M demonstrates data flow control logic loading and data logging X3 2M User s Manual Host Card 12 devices 12 channels Ni PCle Figure 4 X3 2M FrameWork Logic Data Flow The data flow is driven by the data acquisition process Data flows from the A D devices into the A D interface component in the F
4. List of Figures Figure I Vista Verification Dial g 1 Eege ig dal seed eee aes nee 14 Figure 2 Innovative Install Pr eR LR ese a Hie eld ei ee eee ber Pe T pte ta eadein 15 Figure 3 Progress is shown for each section 16 Figure4 Toolset registration fom te ea enhance todas aee dine p ai Eo cede qu teow Tas ut sped x pa Fe aie 17 Figure 5 BusMaster configuration oci Edessa e onse toto pr cette et da E Res ies e be EPA P e Hep pote gia 18 Figure 6 Installation complete iia 18 Figure 7 X3 XMC Family Block Diagr in ee dera cere ee IHRE GER GM ENEE 25 X3 Computing Core Block Di gram scisco ence idad ehe 28 Figure 8 DIO Control Register BAR TI0sl4n nnne nnne trennen enne nennen eerie 33 Figure 9 Digital IO Port Addresses nace ne erm A e RI 33 Figure 10 DIO Control Register BAR 1 0x14 eene nnne enne nenne nnne nente enne etnies 35 Figure 11 Digital IO Bert Addresses zi aene eru ii 35 Figure 12 Digital VO Port Ti uii tc er p HE OO E Rr p p TL DUNT operta 35 Figure 13 2X3 2M Module ueteres Ue oe E RU e E D oer E GERE e Pee e bod tele ang 67 Figure 14 X3 2M Block Diagram tet RN 68 Figure 15 X3 2M A D Channel Dageram essent nenhenne teint tette nnt net nn tnnt ret nntnettnnetnr nana 70 Figure 1 X3 2M Clock Generation and Controls Block Dageram eese 73 Figure 1 X3 2M External Clock Bart eet eere odd cites D LR e e a He eg t een Ruta qe bornes 74 Figure 2 Analog Triggering Tmmmg ecesesse
5. 0x8000 If the calculated coefficients are larger than this they are either wrong or the channel is damaged X3 2M User s Manual 90 Performance Data Power Consumption The X3 2M requires the following power for typical operation with when using the FrameWork Logic This typical number assumes a 67 MHz system clock rate and 10 MSPS A D data rates for the application logic Table 19 X3 2M Power Consumption Voltage Maximum Allowed Typical Current Typical Derived from Supplies these Devices Current A Required A Power W 3 3V 5A 1 98 6 5 Direct connect to the All devices on card power recommended PCIe host supplies use 3 3V as source 12V 0 0 Not required Total 6 5 Power Surge currents occur initially at power on and after application logic initialization The power on surge current lasts for about 10 ms 5A on the 3 3V supply This surge is due primarily to charging the on card capacitors and the startup current of the FPGAs After initial power up the logic configuration will also result in a step change to the current consumption because the logic will begin to operate In our testing and measurements this has not been a surge current as much as a just a step change in the power consumption Power consumption varies and is primarily as a function ofthe logic design Logic designs with high utilization and fast clock rates require higher power Since calculating power cons
6. 28 280 MHz This is the maximum frequency for the VCXO that is an even multiple of the desired clock rate The PLL will then run at 280 MHz and the dividers will be set to 28 X3 2M User s Manual 75 Programming the PLL to run at 280 MHz rate requires that the internal dividers be set so that the phase comparison is done at 100 kHz The remainder of this section discusses how to find these numbers for the PLL configuration For most applications the Malibu support software configures the PLL according to the desired sample rate The software configures the VCXO to the desired PLL frequency and then all PLL registers so that the output frequency is as close as possible to the required sample rate given the constraints of resolution as determined by the tuning parameters and the VCXO tuning range Note It is best to use the Malibu drivers for almost all applications and the following discussion is only for users who need to modify the PLL tuning for very unique applications The tuning equation for the AD9510 is Fvcxo Fret R x PB A where Fref 100 MHz or external reference frequency R to 16383 integers B 3 to 8191 integers 1 bypass A 0 to 63 integers used only in dual modulus mode P 1 2 3 4 8 16 or 32 and 10 MHz lt FVCXO lt 280 MHz All PLL tuning parameters R B A and P are software programmable through the PLL interface Step 1 Pick a phase detector frequency close t
7. Applicationlo HandleLoadComplete Module Logic OnFpgaLoadMessage SetEvent this Applicationlo HandleLoadError This code attaches script event handlers and X3 10M logic loader s informational event handlers to their corresponding events Malibu has a method where functions can be plugged into the library to be called at certain times or in response to certain events detected Events allow a tight integration between an application and the library These events are informational messages issued by the scripting and logic loader feature of the module They display feedback during the loading of the user logic and when script is used Alerts Module Alerts OnTimeStampRolloverAlert SetEvent this amp ApplicationIo HandleTimestampRolloverAlert Module Alerts OnSoftwareAlert SetEvent this amp ApplicationIo HandleSoftwareAlert Module Alerts OnWarningTemperature SetEvent this amp Applicationlo HandleWarningTempAlert Module Alerts OnPllLost SetEvent this amp ApplicationIlo HandlePllLostAlert Module Alerts OnInputFifoOverrun SetEvent this amp ApplicationIo HandleInputFifoOverrunAlert Module Alerts OnInputTrigger SetEvent this amp Applicationlo HandleInputTriggerAlert Module Alerts OnInputOverrange SetEvent this amp ApplicationIo HandleInputFifoOverrangeAlert This code attaches alert processing event handlers to their corresponding events Alerts are packets that the module generates and sen
8. FP DIO8 FP DIO6 FP DIO4 FP DIO2 FP DIOO AGND EXT CLK TRIGGER1 AGND AID11 IN AGND AID10 IN AGND AID9 IN AGND AID8 IN AGND AID7 IN AGND AID6 IN AGND AID5 IN AGND AIDA IN AGND AID3 IN AGND AID2 IN AGND AID1 IN AGND AIDO IN AGND FP DIO11 FP DIO9 FP DIO7 FP DIOS FP DIO3 FP DIO1 AGND EXT CLK TRIGGERO Note No Connect P Power I Input O Output relative to X3 module X3 2M User s Manual XMC P15 Connector P15 is the XMC PCI Express connector to the host Connector Types Number of Connections Connector Part Number Mating Connector XMC pin header 0 05 in pin spacing vertical mount 114 arranged as 6 rows of 19 pins each Samtec ASP 105885 01 Samtec ASP 105884 01 Figure 11 P15 XMC Connector Orientation X3 2M User s Manual 100 Column Row A B C D IS F 1 PETOpO PETOnO 3 3V VPWR 2 GND GND GND GND MRSTI 3 3 3V VPWR 4 GND GND GND GND MRSTO 5 3 3V VPWR 6 GND GND GND GND 12V 7 3 3V VPWR 8 GND GND GND GND 12V 9 VPWR 10 GND GND GND GND GAO 11 EROpO PEROnO MBIST VPWR 12 GND GND GA1 GND GND MPRESENT 13 3 3VAUX VPWR 14 GND GND GA2 GND GND MSDA 15 VPWR 16 GND G
9. Source Frame Mode Int M Auto Retrig Unframed 0x4000 Count The setup tab contains a large number of controls al ce a HE used to configure the on board timebase alert Digital 1 0 Data Loaging Test Counter Decimation Config Mask Samples Enable notifications analog channel selection range and TO E AutoStop Ense triggering etc Each of these controls is described below Clock Group The module features an on board AD9510 PLL which may be used as a sample clock during analog acquisition Alternately an external sample clock may be used The Clock Source radio control governs which timebase is used as the analog sample clock If the internal PLL is selected the sample rate entered in the Output Khz edit control is used to program the PLL to generate the specified sample rate during acquisition However if the clock source is external then the Output KHz control is used to inform the program of your intended external sample rate In that case you are expected to supply a clock running at the rate listed in the Clock Source MHz control to the external clock input connector on the module Communications Group All X3 modules support data transfer between Host memory and the on board FPGA via a dedicated PCI Express bus interface Data is transferred in packets which consist of a two word header followed by a fixed length data buffer Header word zero contains the buffer length in bits 0 23 and a perip
10. The AD7626 supports sample rates from 0 1 to 10 MSPS on the X3 2M module Either an external clock or on card PLL is used for sample rate generation as described in the sample clocking section Sample rates below 0 1 MHz result in poor results due to A D restrictions Data rates lower than 0 1 MSPS are supported using decimation in the logic Decimation gives better performance than running the A D at low rates because conversion circuitry internal to the A D cannot hold a signal long enough for a good conversion result The FrameWork Logic supports 1 N decimation resulting in lower data rates All channels must be decimated at the same rate Supporting software functions in the Malibu library automatically set the sample mode and clock rate required for the desired sample rate The single rate mode offers the best noise and dynamic range performance because more filtering is used The software always sets the converter to the lowest data rate mode possible to achieve the best performance X3 2M User s Manual 71 The module is designed to support 12 channels simultaneously acquiring data at 10 MSPS and flowing the data continuously to the host computer a data rate of 240 MB s To support this rate the host computer must be capable of storing data to memory or disk continuously at 240MB s For maximum rate on all channels the host PCIe slot must be x4 lanes to support the data rate Storage to disk requires either a high performance SSD or RAID
11. X9 Table 5 Temperature Data Format X3 2M User s Manual The logic component provides a programmable temperature warning BARO 0x4 and failure BARO 0x5 The warning and fail may create alert packets when enabled Both temperature warning and failure are latched when they occur and must be cleared by a read their respective registers Table 12 Temperature Alarms Alarm Setting Temperature Celsius Set Register to Warning 70 X 460 Fail 85 X 550 A temperature failure results in a power down signal to the analog electronics signaling to shut down The FPGA and host interface remain active and the module should continue to communicate unless a catastrophe has occurred The thermal shutdown behavior of each X3 module is detailed in the specific discussion of that t module The power down can be cleared by reading from the temperature fail register The temperature sensor must be present and responding for the module to operate If the temp sensor fails this is treated as a temperature failure The logic continues to attempt to communicate with the temperature sensor If multiple failure conditions are found the logic should be reloaded Note that the control logic for the temperature sensor is in the application logic so the logic must be configured to provide thermal protection It is unlikely except in cases of catastrophic failure that the module will overheat when the logic is not loaded sin
12. board temperature and current DIO pin state 1s shown in real time on the statistics status bar located at the bottom of the Streaming tab X3 2M User s Manual 48 Ram Test Select the ZotRam tab The control on this tab allows the onboard ZBT ram to be tested In practice the ZbtRam is directly addressed by custom FPGA firmware However the stock logic provides means of accessing this RAM using methods in the module control object to verify proper electrical operation EEPROM Access Select the EEPprom tab The controls on this tab allow the contents of the onboard EEPROM to be queried or changed The onboard EEPROM is used for non volatile storage of module identification strings digital calibration coefficients for each of the A D channels and for a calibration coefficient for the reference clock for the onboard PLL These values are determined during factory calibration and need not normally be changed by the user Debugging Select the Debug tab The controls on this tab support a few low level debug operations to be performed A debug script may be executed at any time to perform low level register fetches or stores to exercise custom FPGA firmware or determine the current hardware state Unlike the stream scripts described earlier this script executes manually via the button so you need not be streaming to put it to use A software alert may be generated by pressing the Software button The value in the edit cont
13. 0 to 100 0 to 100 0 to 100 0 to 100 non condensing Conformal coating Conformal coating Conformal coating extended temperature range devices Conformal coating extended temperature range devices Thermal conduction assembly Conformal coating extended temperature range devices Thermal conduction assembly Wide temperature testing Wide temperature testing Vibration Shock Wide temperature testing Vibration Shock Epoxy bonding for devices Testing Functional Functional Functional Functional Functional Temperature cycling Temperature Temperature Temperature Testing per MIL cycling cycling cycling STD 810G for vibration shock temperature humidity Table 20 X3 2M Environmental Limits X3 2M User s Manual 92 Testing for each unit is performed to verify compliance with the specified requirements For levels above LO functional testing is performed over the specified temperature range and functional testing is verified during vibration tests Shock testing is non operation with post shock functional testing Humidity testing is performed on an engineering proof test basis only Individual units are not 100 tested for humidity Analog Input A summary of the analog performance follows for the X3 2M module All tests performed at room temperature with no forced air cooling unless noted Test environment was PCle adapter card in PC runn
14. 07 PXI DSTARA conversion clocks 5 0 maximum 100 MHz or PXIE 100M PLL Reference clock 1 2 typical 0 05 1 5 maximum Table 12 X3 2M External Sample Clock Timing Triggering The X3 2M has a trigger control component in the FPGA that controls the data acquisition process The sample clock specifies the instant in time when data is sampled whereas triggering specifies when data 1s kept This allows the application to collect data at the desired rate and keep only the data that is required On the X3 2M module all A D channels operate synchronously using the same clock and trigger The trigger controls allows data to be acquired continuously or during a specified time as triggered by either a software or external trigger Data can also be decimated to reduce data rates X3 2M User s Manual 80 Trigger Mode Data Collected Played Back Start Trigger Stop Trigger Continuous All enabled channel pairs Software or rising edge of Software or falling edge of external trigger external trigger Framed N sample points for each of Software or rising edge of Stops when N samples are the enabled channel pairs external trigger collected back Decimation M points are discarded for every point kept May be used with either trigger mode Table 2 Trigger Modes On the X3 2M module the sample rate is equal to the clock rate The trigger component operates at the sample rate for its data c
15. 100 ZS 110 1 18 120 5 to 130 1 140 2 150 3 160 4 170 5 lo h b 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 0 0 04 02 03 04 05 06 07 0 8 0 9 10 KHz mS D A D E Max S N dB S N dB SINAD dB ENDB bits SFDR dB THD dB Min mV Max mV Delta mV Mean mV Std Dev mV Range dB 981 00 00 00 00 0 000000 0 0d8 1 2207e 00 3 3569e 00 4 5776e 00 485504e 01 462405601 na Sample Leap 40 Analyze M0 Y Sample H Leap 4096 Span 10000 Anayee h0 Y Ea Samples 102408 ences 102408 Figure 6 Noise Floor Spectrum Fs 10MSPS Figure 7 Noise Floor Fs 10MSPS X3 2M User s Manual 94 ax BinView c projects x3 2m hardware revb qual data requal 8 13 10 freq 10 1k_dec10 bdd a Marr CBR CO g 02 Time Frequency Test Summary Server 0 01 3 90 Magnitude vs Frequency K PSA Af l 10 F Fs Max S N dB S N dB SINAD dB ENOB bits SFDR dB THD dB 98 1 623 62 0 10 0 78 2 0 002586 91 7dB Sample Leap 40 Analyze D 7 Samples 102408 Figure 8 Signal Quality 101 kHz 1 9Vp p input 10 MSPS decimation 10 X3 2M User s Manual 95 ax BinView dmclane projectsbc x5 400m hardwarethsc test data plot23 bdd a Metro GEBE co Y 0 Time Frequency Text Summary Server 115 58 49 20 Magnitude vs Frequency 100K 120K 140K 160K KHz 180K 200K Max S N dB S N dB SINAD dB ENOB bits SFDR dB 86 0
16. 2 C3 DIO3 PXI TRIG3 Digital IO 3 PXIE trigger 3 C4 DIO4 PXI TRIG4 Digital IO 4 PXIE trigger 4 C5 DIO5 PXI TRIGS Digital IO 5 PXIE trigger 5 C6 DIO6 PXI TRIG6 Digital IO 6 PXIE trigger 6 C7 DIO7 PXI TRIG7 Digital IO 7 PXIE trigger 7 C8 DIOS PXI STAR Digital IO 8 PXIE star trigger C9 DIO9 PXIE_SYNC100 Digital IO 9 PXIE sync 100 C10 DIO10 PXIE_SYNC100 Digital IO 10 PXIE sync 100 Cll DIO11 Digital IO 11 C12 DIO12 Digital IO 12 C13 DIO13 Digital IO 13 C14 DIO14 Digital IO 14 C15 DIO15 Digital IO 15 C16 DIO16 Digital IO 16 C17 DIO17 Digital IO 17 C18 DIO18 Digital IO 18 C19 DIO19 Digital IO 19 Fl DIO20 Digital IO 20 F2 DIO21 Digital IO 21 F3 DIO22 Digital IO 22 F4 DIO23 Digital IO 23 F5 DIO24 Digital IO 24 F6 DIO25 Digital IO 25 F7 X3 2M User s Manual 105 Signal Description P16 Pin DIO26 Digital IO 26 F8 DIO27 Digital IO 27 F9 DIO28 Digital IO 28 F10 DIO29 Digital IO 29 F11 DIO30 Digital IO 30 F12 DIO31 Digital IO 31 F13 DIO32 Digital IO 32 F14 DIO33 Digital IO 33 F15 DIO34 Digital IO 34 F16 DIO35 PXI 10M Digital IO 35 PXI 10M Ref CIk F17 DIO36 PXI LBL6 Digital IO 36 PXI local bus left 6 F18 DIO37 PXI LBR_6 Digital IO 37 PXI local bus right 6 F19 DIO38 PXI DSTARA Digital IO 38 PXIE Differential STAR A A9 DIO39 PXI DSTARA Digital IO 39 PXIE Differential STAR A B9 DIO40 PXIE_100M Digital IO 40 PXIE 100M ref clk D9 DIO4 PXIE 100M Digital IO
17. 41 PXIE 100M ref clk E9 DIO42 PXIE_DSTARB Digital IO 42 PXIE Differential STAR B A19 DIO43 PXIE DSTARB Digital IO 43 PXIE Differential STAR B B19 DIO_CLK PXI_DSTARC Digital IO Clk PXIE Differential STAR C D19 DIO_CLK PXI_DSTARC Digital IO Clk PXIE Differential STAR C E19 Note PXI Express signals are only available when PXIE adapter card is used X3 2M User s Manual 106 Xilinx JTAG Connector JP3 is used for the Xilinx JTAG chain It connects directly with Xilinx JTAG cables such as Platform USB Note Some cables have a polarity bump on the connector This must be remove for use with X3 2M Connector Types 14 pin dual row male header 2mm pin spacing right angle Number of Connections 14 arranged as 2 rows of 7 pins each Connector Part Number Samtec TMM 107 01 L D RA or equivalent Mating Connector AMP 111623 3 or equivalent Top of PCB x Edge of PCB Pin AA Pini 13 Pin v Pin 2 14 JP3 Figure 13 X3 2M J3 Orientation Figure 14 X3 2M J3 Side View Table 26 X3 2M JP3 Xilinx JTAG Connector Pinout Pin Signal Direction 1 3 5 7 9 11 13 Digital Ground Power 2 3 3V Power 4 TMS I 6 TCK I 8 TDO O 10 TDI I 12 14 No Connect X3 2M User s Manual 107 Mechanicals The following diagram shows the X3 2M connectors and physical locations The bottom view of the XMC is shown which is the side against the host card when mounted The XMC conforms
18. 50 60 70 Offset Span 100 cho 80 90 100 Analyze ChO v Samples 4096 A 63 Applets for the X3 10M Baseboard EEProm X3 10M has two logic devices on it One controls the analog hardware and the interface to the peripherals This logic can be modified by the user and must be loaded by the user with an image on each session The second device performs the baseboard enumeration and PCI interface and has a ROM so that it can function at power up The EEProm exe applet is designed to allow field upgrades of this PCI logic firmware on the X3 10M The utility permits an embedded firmware logic update file to reprogrammed into the module Flash ROM which stores the personality of the board To use the applet select the target number of the baseboard whose logic is to be updated In systems containing only a single target The target combo box is disabled with the default selection of zero Use the Browse button to select the appropriate PCI firmware image to be reprogrammed into the on board flash Typically this image is located in the X3 10M Hardware Images folder with a xsvf extension Click the Load button to reprogram the onboard flash The operation typically takes under two minutes to complete Complete functionality is supplied in the application s help file TX Pmc Eeprom Programmer 1 z Target Xsvf File C Sinnovatives UWB Framework Logichpmc pci 2r v8B xs
19. Dialog gt InitialDir ExtractFilePath LogicFilenameEdit gt Text if Dialog gt Execute LogicFilenameEdit gt Text Dialog gt FileName The code above opens a dialog allowing the user to browse for logic file The filter property of this dialog masks out all the files in a folder other than exo file If the user cancels out no change will occur in the selection box If logic file is selected then we will move on to the loading it void _ fastcall TMainForm LogicLoadConfigBtnClick TObject Sender X3 2M User s Manual 53 Io LoadLogic In UL LogicLoadConfigBtnClick shown above is executed in response to the Configure button click It immediately checks whether the device is opened and stream is connected If the condition is true we exit the routine after logging the message in the message log We can also do some more UI tricks here such as setting up the progress bar limits and disabling the configure button etc We further extract the file name from the Textbox and pass it to the ApplicationIo method LoadLogic shown below Applicationlo LoadLogic Initiate Logic Load Process void ApplicationIlo LoadLogic if Opened UI gt Log No module on specified target return ULLOA dE UI gt Log Parsing Module logic file UlI gt GetSettings Module Logic ConfigureFpga Settings ExoFile In this method we make a call to the Malibu function ConfigureFpga wh
20. EXO or BIT file produced by popular logic design tools including Xilinx s It is essential that the Virtex be programmed before using related applications since some of the baseboard peripherals are dependent on the personality of the configured logic X3 Pmc Logic Loader DER Target Exo File C Innovative Uwb Hardware lmages pme_uwb exo En Event log No baseboards enumerated HW Variant HW Rev X3 2M User s Manual 65 X3 2M Hardware Introduction The X3 2M is a member of the X3 XMC family that has 12 channels of 16 bit 10 MSPS A D conversion The front end inputs are 50 ohm impedance low noise differential inputs The A D converter has exceptional signal quality with a usable dynamic range of over 90 dB A high performance computing core for signal processing data buffering and system IO is built around a Spartan3A DSP 1 4M gate FPGA optional 3 4M Supporting peripherals include 2MB of SRAM conversion timebase and triggering circuitry 44 bits digital IO and a PCI Express interface The module format is a single slot XMC conforming to IEEE 1384 CMC standard and is compatible with XMC 3 host sites X3 2M User s Manual 66 H n SS X 2m Figure 13 X3 2M Module Custom application logic development for the X3 2M is supported by the FrameWork Logic system from Innovative using VHDL and or MATLAB Simulink Signal processing data analysis and application specific alg
21. Express memory space This allows the host to access the PLL control ports for configuration and status Writes to the PLL interface ports generate a serial data stream to the PLL that is used to configure the PLL U36 PLL clock divider BARI 0xA Table 6 Clock Device Address This interface is only for configuration accesses should be spaced by the host computer to be at least 2 ms apart The Malibu library handles this restriction as part of the function The PLL interface uses a 24 bit word to communicate with the PLL that specifies a read or write access the PLL register address and the data byte to transfer For reads the data byte is a don t care The 24 bit word is as follows PLL register address Table 7 PLL Interface Word Format Writes Writes to the PLL are pokes to register OxA located in the system memory at BARI 0xA The data value is the 32 bit word as described above BARI 0xA X 00801C12 Write to PLL register 0x1C value 0x12 Table 8 PLL Read Sequence Reads Reads from the PLL require a two step process consisting of first a write to the PLL register specifying a read at an address followed by a read from the PLL register that returns the value of the PLL register specified by the address in the PLL word The PLL is read is a single byte For reads the PLL must be written to with a bit 23 as 1 and the address that is to be read then read from the PLL register For example a read to PLL r
22. The size of the data packets sent from the module to the Host during streaming is programmable This is helpful during framed acquisition since the packet size can be tailored to match a multiple of the frame size providing application notification on each acquired frame In other applications such as when an FFT is embedded within the FPGA the packet size can be programmed to match the processing block size from the algorithm within the FPGA Start Loggers on active channels if Settings PlotEnable Graph Quit if Settings LoggerEnable Settings PlotEnable Logger Start BlocksToLog Settings SamplesToLog Settings PacketSize Settings SamplesToLog Settings PacketSize 1 0 Stopped false The example illustrates logging data to a disk file with post viewing of the acquired data using BinView The code fragment above closes any pending instance of BinView and logger data files Module Dio DioPortConfig Settings DioConfig X3 2M User s Manual 56 The module supports programmable bit I O available on connector JP16 The code fragment above programs the direction of these DIO bits in accordance with the settings from the GUI Set test mode Module TestCounterEnable Settings TestCounterEnable For test purposes the FPGA firmware supports replacement of analog input samples with ascending ramp data If the test counter is enabled in the GUI it is applied to the hardware using the preceding code fr
23. These procedures need to be completed for every target machine Malibu To develop software for a baseboard the Malibu packages also must be installed Malibu LinuxPeriphLib ver rel 1586 rpm Installs Malibu Source Libraries and Examples Other Software Our examples use the DialogBlocks designer software and wxWidgets GUI library package for user interface code If you wish to rebuild the example programs you will have to install this software as well wxWidgets wxWidgets http www wxwidgets org DialogBlocks Anthemion http www anthemion co uk org dialogblocks Baseboard Package Installation Procedure Each baseboard installation for Linux consists of one or more package files containing self extracting packages of compressed files as listed in the table below Note that package version codes may vary from those listed in the table Each of these packages automatically extract files into the usr Innovative folder herein referred to as the Innovative root folder in the text that follows For example the X5 400 RPM extracts into usr Innovative X5 400 ver A symbolic link named x5 400 is then created pointing to the version directory to allow a single name to apply to any version that is in use X3 2M User s Manual 22 Board Packages X5 400M Malibu LinuxPeriphLib ver rel 1586 rpm Board files and examples X5 210M X5 210M LinuxPeriphLib ver rel 1586
24. a bridge device between the two buses PCI is not electrical Host Type Bus Mechanical Form factor Adapter Example card Required XMC 3 module PCI Express 1 0a XMC single width None Kontron CP6012 slot www kontron com Diversified Technology CPB4712 http www diversifiedtechnology com p roducts cpci cpb4712 html Desktop PC PCI Express 1 0a PCI Express Plug in card PCle XMC 3 Innovative 80172 adapter Desktop PC PCI 2 2 PCI Plug in card PCI XMC 3 Innovative 80167 adapter Compact PCI PCI Express 1 0a 3U or 6U CPCle XMC 3 TBD Express adapter Cabled PCI PCI Express 1 0a Cabled PCI Express to Cable PCIe Innovative 90181 0 Express remote IO Adapter and XMC 3 carrier PXI Express Compact PCI 3U 3U PXIe Innovative 80207 Express Adapter X3 2M User s Manual 42 Embedded PC Standalone PC Enclosure is Innovative 90201 90199 with dual XMC sites 195 x 252 x 75 mm OpenVPX PCI 3U 3U VPX XMC _ Innovative 80260 Air cooled or conduction cooled X3 2M User s Manual 43 Writing Custom Applications Most scientific and engineering applications require the acquisition and storage of data for analysis after the fact Even in cases where most data analysis is done in place there is usually a requirement that some data be saved to monitor the system In many cases a pure data that does no immediate processing is the most common application T
25. advantage of any power saving features on the module Many of the X3 modules have power saving features that allow you to turn off unused channels reduce clock rates or stop data when the module is not in use The chapter discussing module specifics has information on both the power consumption and the power saving features that can be used LED Indicators The X3 modules have two LEDs one that is used for PCI Express interface and one from the application logic Both LEDs are on the back side of the card These LEDs are not visible from the front panel in most installations They are used primarily for debug The LED from the PCI Express interface FPGA D4 is usually used to find the target number of the module The Finder applet blinks the LED when the target module is addressed This allows systems with multiple modules to find out the software target number for each module Another use for the PCI LED is to indicate that the PCI interface logic loaded This LED should ALWAYS be on after the host computer boots If it is not on that means the PCI control logic did not load The possible causes for this are bad power defective module or missing PCI logic image In any case if this LED is off the card will not communicate to the host system The second LED D5 is from the application logic The purpose of this LED is to indicate that the application logic has been configured and to blink when an over temperature condition occurs Custom lo
26. an acquisition is completed When the alert system is enabled the module logic continuously monitors the status of the peripheral usually analog hardware present on the baseboard and generates an alert whenever an alert condition is detected It s also possible for application software to generate custom alert messages to tag the data stream with system information The Malibu software provides support for alert configuration and alert packet processing See the software manual for usage Tagging the Data Stream The Alert Log can be used to tag the data stream with system information by using software alerts This helps to provide system level correlation of events by creating alert packets in the data stream created by the host software Alert packets are then created by the X3 module and are in the stream of data packets from the module For example it is often interesting when something happens to the unit under test such as a change in engine speed or completion of test stimulus Using the X3 2M Where to start The best place to start with the X3 2M module is to install the module and use the SNAP example to acquire some data This program lets you log data from the module and use all the features like triggering clocks alerts and calibration ROM You can use this program to acquire some data and log it to disk This should let you verify that the module can acquire the data you want and give you a quick start on deciding what samp
27. are also a number of support peripherals for IO control and system integration Each XMC may have additional application specific support peripherals X3 2M User s Manual Table 2 X3 XMC Family Peripherals Peripheral Features XMC 3 PCI Express interface The XMC 3 host interface Integrates with PCI Express systems using one lane operating at 2 5 Gbps that provides up to 180 MB s sustained data rates This interface complies with VITA standard 42 3 which specifies PCI Express interface for the XMC module format The Velocia packet system provides fast and flexible communications with the host using a credit based flow control supporting packet transfers with the host A secondary command channel provides independent interface for control and status outside of the data channel that is extensible to custom applications XMC P16 Provides digital IO or a private link to host cards capable of gt 200 MB s sustained operation Timing and triggering Flexible clocking and synchronization features for IO Data buffering and Computational Memory Two 2MB SRAM devices are used provide data buffering processor memory and computation memory for the Application FPGA Alert Log Monitors system events and error conditions to help manage the data acqusiton process Temperature Sensor Monitors the module temperature and provides thermal protection for the module X3 Computing Core The X3 XMC mo
28. bits X3 SD and X3 SDF or 512K by 32 bits all others This device is a synchronous ZBT SRAM and supports clock rates up to 100 MHz on X3 SD and X3 SDF 133 MHz on all other modules All SRAM control and data lines pins are directly connected to the FPGA allowing the SRAM memory control to be customized to the application The Framework Logic provides a simple SRAM interface that can be readily modified for many types of applications Detailed explanation of the interface control logic is described in the FrameWork Logic User Guide The Framework Logic provides a simple register interface to the SBSRAM control logic that is used for test and demonstration FPGA logic developers can easily replace the simple register interface logic to build on top of the high performance logic core when integrating the SRAM into their logic design MATLAB developers frequently use the SRAM as the real time data buffer during development Since the MATLAB Simulink tools operate over the FPGA JTAG during development at a low rate it is necessary to use the SRAM for real time high speed data buffering The MATLAB Simulink library for the X3 modules demonstrate the use of the SRAM as a data capture buffer The SRAM captures real time high speed data that can then be read out into MATLAB for analysis or display as a snapshot This allows high speed real time to be captured and brought into MATLAB Simulink over the slow 10Mb sec JTAG link See the X3 FrameWork Logic Us
29. conduction cooling method allows the module heat to be flowed out to the chassis The thermal plane has NO electrical connection in the module and cannot be used as a ground The front panel bracket is used for cooling and is attached to the thermal plane The front panel is not electrically connected to the module ground plane its is only connected to the thermal plane When the module is operating the front panel usually feels slightly warm this is normal Temperature Sensor and Over Temperature Protection The temperature sensor is described in detail in the Board Basics chapter of this manual The temperature sensor is used to monitor the module temperature and protect it from overheating Temperature readings from the module are provided for system monitoring and are also reported in each alert packet During system development it is a good idea to have a look at the temperature and verify that everything is OK inside the system during actual use When the module exceeds 85C LO rated modules the analog power supplies shut down reducing the power consumption to about 3W The module can continue to communicate but no valid data will be collected A temperature warning may be enabled via the Alert Log when the temperature is above 70C If a warning occurs it is best to do something either to reduce power consumption such as turning off the A D channels turning on a system fan or turning off other things in the system The application LED
30. failure The module could have failed the system power is bad or the environment is too harsh The first thing to do is inspect the module Is anything discolored or do any ICs show evidence of damage This may be due to device failure system power problems or from overheating If damage is noticed the module is suspect and should be sent for repair If not test the module outside the system in a benign environment such as on an adapter card in a desktop PC with a small fan It should not overheat If it does this module is now bad Now consider what may have caused the failure A bad module could be the cause but it could have went bad due to system failure or overheating The system power supply could cause a failure by not providing proper power to the module This could be too little power resulting in the module failing or power glitches causing the temp sensor to drop out Did other cards in the system fail If so this may indicate that a system problem must be solved If the module did overheat you should review the thermal design of the system What was the ambient temperature when failure occurred Is the air flow adequate Is air flow blocked to the card Did a fan fail If conduction cooling is being used what is the temperature of the surrounding components The heat must be dissipated either through conduction or convection for the module to keep from overheating You should also review application and be sure that you have taken
31. http www picmg com 2 5 Gbps data rate ANSI VITA 42 XMC module mechanicals and connectors VITA www vita org ANSI VITA 42 3 XMC module with PCI Express Interface VITA www vita org The X3 module family uses a Texas Instruments bridge chip to go from PCI Express to a local PCI bus on the module The PCI Express bridge works with the PCI FGPA to implement the Velocia packet system for data communications and also provides the module configuration and control features X3 2M User s Manual 29 a P Data link to App Logic 32 bit 66 MHz PCI Express rigg i Ec a ww Serial Link aid PCI Express Local PCI Bus Sue X1 or x4 lane 32 bit 66 MHz lt q M SelectMAP interface to Connector P15 app logic The major interfaces to the application logic are the data link command channel and SelectMAP interface The data link provides a high performance channel for the application logic to communicate with the host computer while the Command Channel is a command and control interface from the host computer to the application logic The SelectMAP interface is the application FPGA configuration port for loading the logic image The data link is the primary data path for the data communications between the application FPGA and host computer When data packets are created by the application logic such as A D samples or required by the application logic for output devices such as DAC channels the data
32. in this style represents text as it appears onscreen or in code It Source Listing I also represents anything you must type Boldface Text in this style is used to strongly emphasize certain words Text in this style is used to emphasize certain words such as new Emphasis terms Cpp Variable Text in this style represents C variables Text in this style represents C identifiers such as class function Cpp Symbol or type names KEYCAPS Text in this style indicates a key on your keyboard For example Press ESC to exit a menu Text in this style represents menu commands For example Click M mman i enu Co d View Tools Customize X3 2M User s Manual 12 Windows Installation This chapter describes the software and hardware installation procedure for the Windows platform WindowsXP Vista and Windows 7 Do NOT install the hardware card into your system at this time This will follow the software installation Host Hardware Requirements The software development tools require an IBM or 100 compatible Pentium IV class or higher machine for proper operation An Intel brand processor CPU is strongly recommended since AMD and other clone processors are not guaranteed to be compatible with the Intel MMX and SIMD instruction set extensions which the Armada and Malibu Host libraries utilize extensively to improve processing performance within a number of its components The host system must h
33. nicer dee ars 15 Tools Registration eet A i hath waa Ge A ew ete e e a eee P 17 Bus Master Memory Reservation Apple 17 Hardware InstallatiOh 2s A er e state eode agni ste tte deere ase cs 18 After Pow erat pies n Em 19 Installation on a Deployed System secco Selb ee han een ete e aee Dre I ARTE REL Dee ERR above ies 19 Running MalibuRed i13 eae evo t eye EES 19 Installation on Bin ccc Al Package File TEE 21 Prerequisites for Installation osse ete e HT ERE RO ERNEUT EC EO ede Me heels 21 The Redistribution Package Group Malbubed sessi 21 Mali bt EMI iaa 22 Other Software x x arg HR GUI E D Se ER E D ava REG EE HERE ati ue 22 Baseboard Package Installation Brocedure esses enne enne enne non rn ennt n nnne 22 Board Packages need t edi i ade e se qe MM I 23 Unpacking the Pack ge 4 ui esee et ale e eere ette esie aede ie e eei UR aS 23 Creating Symbolic En Cm 23 Completing the Board Install eese enne enne enne nennen nnne ne trennen non ran enne nne 24 Ein x Directory EE 24 EE 24 DOCUMENTATION EE 24 Exatiples eC tbe ee e b eee ee eee tee mde ae e is es t he 24 Hardwatezn3 t spe te Lt ave eeu Du eu te 24 About the X3 XMC Modulle scccccccccccsssssssscccccccccsssssscccccecccesesssccccceccesccsssssccscesescecsscccscessccsessces E X3 2M User s Manual EDIC 0 La 10s T NU ID T MI AE 25 X3 Computitig eenegen IBN NIIS 27 X3 PCLEXpress Interface RU OR BIER EUNT Ee 29 Data Buffering and MEMO ADEL
34. offset X3 2M User s Manual 89 Production Calibration Each X3 2M is calibrated as part of the production tests performed The calibration results are provided on the production test report with each module The results of the calibration are stored in the on board EEPROM memory These calibration values are used by the logic to correct the analog errors and are loaded into the A D as part of the initialization by the software The calibration technique used determines the A D errors by first measuring the output with ground connected then a known voltage A value close to full scale such as 9 8V and 9 8V are recommended The measurements are the average of 64K samples at each test voltage From these three points across the input range the gain and offset errors are calculated All test voltages are measured as part of the procedure with NIST traceable equipment Production calibration is performed at room temperature 24C with the module operating temperature at about 50C Under normal circumstances calibration is accurate for one year For recalibration the module can be sent to Innovative or re calibrated using a similar test procedure Updating the Calibration Coefficients A software applet for writing the calibration coefficients to the EEPROM is provided EEPROM exe New coefficients are simply typed into the offset and gain field for each channel Calibration coefficients for gain should not be greater than 1 1 and offset
35. rpm Board files and examples X3 10M X3 10M LinuxPeriphLib ver rel 1586 rpm Board files and examples X3 25M X3 25M LinuxPeriphLib ver rel i586 rpm Board files and examples X3 A4D4 X3 A4D4 LinuxPeriphLib ver rel 1586 rpm Board files and examples X3 SD X3 SD LinuxPeriphL ib ver rel 1586 rpm Board files and examples X3 SDF X3 SDF LinuxPeriphLib ver rel 1586 rpm Board files and examples X3 Servo X3 Servo LinuxPeriphLib ver rel i586 rpm Board files and examples SBC ComEx Sbc ComEx LinuxPeriphLib ver rel 1586 rpm Board files and examples Unpacking the Package As root type rpm i h X5 400 LinuxPeriphLib 1 1 4 i1586 rpm This extracts the X5 400 board files into the Innovative root directory Use the package for the particular board you are installing Creating Symbolic Links The example programs assume that the user has created symbolic links for the installed board packages A script file is provided to simplify this operation by the Malibu Red package In the MalibuRed KerPlug directory there is a script called quicklink quicklink X5 400 1 1 These commands will create a symbolic link x5 400 pointing to X5 400 1 1 This script can be moved to the user s bin directory to allow it to be run from any directory X3 2M User s Manual 23 Completing the Board Install The normal board install is complete with the installation of the files The board driver install is already complete with the loading of t
36. the A D The differential inputs reject common mode noise from the system and the card itself to improve the conversion results If you drive the inputs single ended the results will be worse by at least 6dB in most cases worse if the system noise is high For signal ended use the unused input must be grounded Unused input pairs may be left disconnected Overrange Detection Input voltage range is limited to 5V to 5V for single ended use for the standard configuration Overrange inputs saturate at full scale and do not exhibit polarity reversal The A D devices indicate when an overrange occurs on the input Overrange occurs when the input signal is above the 2V differential range is exceeded For small overrange conditions of less than 5 overrange the A D will recover in a few samples to proper readings For larger overrange conditions the A D may require longer to recover The overrange indicator bit from each A D can be used to trigger an alert in the logic to notify the application when this error condition has occurred The alert message shows when the overrange occurred in system time and which channels overranged Custom logic has access to the overrange bits in the A D interface component Each data sample indicates when an overrange occurs as part of its status byte appended to the data This allows implementation of automatic gain controls for auto ranging external front end signal conditioning A D Sampling Rates
37. to IEEE 1386 form factor 75mm x 150mm The spacing to the host card is 10 mm and consumes a single slot in desktop and Compact PCI PXI chassis The following views of the X3 2M show the connector placements The bottom view of the board is faces the carrier card when installed An EMI shield over the analog section is normally installed Detailed drawings for mechanical design work are available through technical support Note that the bottom of the card is the side with the XMC and front panel connectors P16 DIO Host DUE JP3 JTAG DS r3 b BENNETT g OP pH E d NHOVATIVE guint om o INTEGRATION 4 mace i MINUNI u eg 3003 Mes S Mew pill Seeeeeeeeeeeeeeege imime Bm Bie que HH deg hl EET Ze JPI IO JP2 Power Test P15 PCIe Figure 15 X3 2M Mechanicals Top View Rev B X3 2M User s Manual 108 iiid rs ep NN g mq G IFT Goss 7 mow Bo res RER 0 zi m ews at age wee poe mme ce E e een EDF ien GEE Md Te 3 SW ER SS W I E KT a E oh was E e ai 7 on n me EI e amb E E Gate 5 ege H Zeie me D Te E 2 oma En on Lon E AE ilm VIE zi Ti puc A kay z Seef a osos EI D Ha mu a Ars 3 H iot jo ge E eve ES A ws Wa A Hle ape nt ri ers quw ZP ocos et w l Vd HEH STANDARD XMC S m Eus EL PD ho Spe i nt sur L E are Um pre i dy 9 d i T ech LEES
38. using the FrontPanelPortConfig operator This sets the byte direction and the clock mode The port is then ready for read write operations via FrontPanelPortData Hardware Implementation Digital I O port activity is controlled by the digital I O configuration control and data register Port direction is controlled by the configuration control register Bit Function 0 DIO bits 7 0 direction control 0 input default 1 DIO bits 15 8 direction control 0 input default 2 DIO bits 23 16 direction control 0 input default 3 DIO bits 31 24 direction control 0 input default 4 DIO bits 39 32 output enable 0 input default 5 DIO bits 43 40 output enable 0 input default 30 6 31 Sample DIO inputs when DIO EXT CLK is true otherwise always sample 0 sample always default X3 2M User s Manual 34 Figure 10 DIO Control Register BAR1 0x14 Port Address DIO L BARI 0x13 DIO H BARI 0x16 Figure 11 Digital IO Port Addresses Data may be written to read from the digital I O port using the digital I O port data registers Data written to ports bits which are set for output mode will be latched and driven to the corresponding port pins while data written to input bits will be ignored The input DIO may be clocked externally by enabling the external digital clock bit in the appropriate configuration register If the internal clock is used the data is latched
39. 703 68 5 11 81 0 Sampie puces Se Samples 200000 Figure 9 Signal Quality 101 KHz 1 9Vp p input 10 MSPS decimation 10 THD dB 0 007111 83 008 X3 2M User s Manual 96 AS Otter 40 ual dare E CAII CEU o OTT ta COT gett ude a lt a b b Erxe CO d e Time Frequency Text Summary Server 143 47 89 85 Magnitude vs Frequency m me T ENOB bits H 10 5 Leap Analyze Ch0 7 IM z dB Samples 131076 0 000343 100 5dB Figure 10 Intermodulation Distortion 9 9 kHz and 11 kHz dual tone Fs 10 MSPS X3 2M User s Manual 97 Connectors Input Connector JP1 JP1connector is the front panel connector for the analog inputs external clock and external trigger inputs Connector Type MDR Number of Connections 68 Connector Part Number 3M part number 10268 55H3 VC Mating Connector 3M part number 10168 6000EC IDC Digikey www digikey com P N MPB68A ND Cable Innovative part number 65057 MDR 68 male to male 36 inches 0 91meters This is the MDR68 as viewed from the front panel Pin 35 Pin 68 de S Pin 1 Pin 34 X3 XMC Front Panel View X3 XMC X3 2M JP1 Front Panel Connector Pin Assignments X3 2M User s Manual 98 AGND A D11 IN AGND A D10 IN AGND AID9 IN AGND AID8 IN AGND A D7 IN AGND AID6 IN AGND AID5 IN AGND AIDA IN AGND AID3 IN AGND AID2 IN AGND AID1 IN AGND AIDO IN AGND FP DIO10
40. C Press F1 to see online help for this example Upon invocation the the device driver for the module number Novevices detected zero is opened This is crucial and must be performed prior to any subsequent communications with the board All X3 modules support a user configurable FPGA which is interfaced directly to all on board module peripherals Consequently the I O personality of the board can be changed X3 2M User s Manual 45 loading a firmware image into the FPGA in a process called configuration The controls located in the Exo Logic File group support dynamic configuration of the FPGA The Browse button with the caption allows selection of a firmware configuration file The Configure button parses the specified file and loads it into the on board FPGA Firmware image files in EXO or BIT file format may be loaded Note that the supplied LogicLoad exe applet may also be used to deliver firmware into the FPGA Setup Tab Configure Stream Zbt Ram EEProm Debug Clock Communications Source Output Alerts This tab has a set of controls that hold the Ca me ce Pkt Size Time Stamp Input venur parameters for data acquisition These settings 10005 0 010000 Software Input Trigger i n Temp Warning Input Overrange are delivered to the target and configure the Intemal PII Lost target when streaming is initiated via controls OD active Channels Hae Trigger the Stream tab described in the next section A
41. Innovative Integration X3 2M User s Manual X3 2M User s Manual The X3 2M User s Manual was prepared by the technical staff of Innovative Integration on August 30 2011 For further assistance contact Innovative Integration 2390 A Ward Ave Simi Valley California 93065 PH 805 578 4260 FAX 805 578 4225 email techsprt innovative dsp com Website www innovative dsp com This document is copyright 2011 by Innovative Integration All rights are reserved VSS Distributions 1 X3 2M Documentation 1 Manual X3 2MMaster odm FXXXXXX Rev 1 0 Table of Contents Xx3 2M User s Mana Es ue et Ur ET Real Time Solutions engen Sege Sege edet tete ec re ar ee iet A DR RE ERR Cat 9 bcne 9 What 1s GSP DET 10 WhatisMa hbu sinora E 10 Whatis C Bullder ii med Aa a o diel dete odo oe a E ei 10 What s Microsoft MSV A E Ee 10 What kinds of applications are possible with Innovative Integration hardware eee 11 Why do I need to use Malibu with my Baschoard 11 Finding detailed information on Mal 11 Online Help 5e dee et oe eee eoe Re Te eee 11 Innovative Integration Technical Support 11 Innovative Integration WebSite uis t eme b qute cash adsense etn eee 12 Typographic Conventions mers etie e e ER eee t eti e re Ro SEENEN 12 Windows Instalaci n LS Host Hardware US NISI RM 13 SEI EE EE e EE 13 Starting the Installation RR 14 The dnstaller Program en red
42. ND MVMRO GND GND MSCL 17 18 GND GND GND GND 19 PEX REFCLK PEX REFCLK WAKE ROOT Table 22 X3 2M XMC Connector P15 Pinout Note All unlabeled pins are not used by X3 modules but may defined in VITA42 and VITA42 3 specifications X3 2M User s Manual 101 Table 23 P15 Signal Descriptions Signal Description P15 Pin PETOpO PETOnO PCI Express Tx A1 B1 PEROp0 PEROn0 PCI Express Rx A11 B11 PEX REFCLK PCI Express reference clock 100 MHz A19 B19 MRSTI Master Reset Input active low F2 MRSTO Master Reset Output active low F4 GAO Geographic Address 0 F9 GA1 Geographic Address 1 C12 GA2 Geographic Address 2 C14 MBIST Built in Self Test active low Cll MPRESENT Present active low F11 MSDA PCI Express Serial ROM data F13 MSCL PCI Express Serial ROM clock F15 MVMRO PCI Express Serial ROM write enable C16 WAKE Wake indicator to upstream device active low D19 ROOT Root device active low E19 X3 2M User s Manual 102 XMC P16 Connector P16 is the XMC secondary connector to the host and is used for digital IO data link and triggering functions XMC pin header 0 05 in pin spacing vertical mount Number of Connections 114 arranged as 6 rows of 19 pins each Connector Part Number Samtec ASP 105885 01 ABCDEF Figure 12 P16 XMC Connector Orie
43. PA a a Las Lee ee E SCH zi S Zefe Sep ei ci Gee A Less AA AEN hg Zeie Pam 1 D maz eur nul nmn HH 2i E E s E e 5 nun e 3 p z SA EH me 2 oso la mid 5 Me E P of in ra z M X3 2M B BR H Jeff E y rix Zefe Sn EM mE Eb DC aed ne B Er a efe LA AA Js ES KS 1 i cp Hg o CR ub oe di LE Millor SS on E e m ETE e TE ue OE un E Safe Bam EE e EE SZ OB Te a9 E es i ocos Im oc kN gt Me ads Non E H FERRE Sg Safe zk W SSE Tle se uo GEES EO sl Nos HZ ts S sE e d EN tg E i ZU De EM E yia pe Lact e E e L Jm ge RHH EHH g ECH LER SC SS 13 i e 1 Be UR GE name Y D4 PCI LED D4 Application LED Figure 16 X3 2M Mechanicals Bottom View Rev B X3 2M User s Manual 109
44. PGA as they are acquired The data is then error corrected and the enabled channels are stored into the data buffer when trigger is true which is implemented a data queue in the SRAM When data is available in the buffer the packetizer pulls data from the queue creates data packets of the programmed size and sends those to the PCIe interface logic From here the Velocia packet system controls the flow of data to the host Data packets flow into host memory for consumption by the host program The Board Basics and Host Communications chapters of this manual discuss the use of the packet data system used on the X3 module family The X3 2M module FrameWork Logic connects the data from A D interface to the packet system by forming the 16 bit data into 32 bit words of consecutive enabled channel pairs channels 1 0 3 2 etc Status indicators for the A Ds are integrated with the alert log to provide host notifications of important events for monitoring the data acquisition process some of which are unique to the X3 2M The complete description of the FrameWork Logic is provided in the FrameWork Logic User Guide including the memory mapping register definitions and functional behavior This logic is about 2096 of the available logic in the application FPGA 1 4M gate device In many custom applications unused logic functions can be deleted to free up gates for the new application Power Controls and Thermal Design The X3 2M module has temperature
45. Registration Utility NewUser exe Some of the Host applets provided in the Developers Package are keyed to allow Innovative to obtain end user contact information These utilities allow unrestricted use during a 20 day trial period after which you are required to register your package with Innovative After the trial period operation will be disallowed until the unlock code provided as part of the registration is entered into the applet After using the NewUser exe applet to provide Innovative Integration with your registration information you will receive The unlock code necessary for unrestricted use of the Host applets A WSC tech support service code enabling free software maintenance downloads of development kit software and telephone technical hot line support for a one year period X3 2M User s Manual Registration Information User Name Fist IB Last Henderson Email Addres Telephone Country Code Area Code Number Extension Fax ES CodevNumber Company Sg Name Innovative Integration Address City Country Postal Code State p Product Board Vista Access Code 935846148 2 Help E Register Now Ok 62 Reserve Memory Applet ReserveMemDsp exe Each Innovative PCI based DSP baseboard requires 2 to 8 MB of memory to be reserved for its use depending on the rates of bus master transfer traf
46. Sectionl AsInt i Section2 LoadFromRom X3 2M User s Manual 37 for int i 50 i lt 100 i float x Section2 AsFloat i As delivered from the factory this EEPROM contains the calibration coefficients used for the A D error correction The serial EEPROM device is an Atmel AT24C16 or equivalent Caution the serial EEPROM contains the calibration coefficients for the analog and is preprogrammed at factory test Do not erase these coefficients or calibration will be lost Thermal Protection and Monitoring X3 modules have an on card temperature sensor that monitors the module and protects it from thermal damage The application software can monitor the module temperature and receive a warning if the temperature is above 70 C If the temperature exceeds 85C the module will shut down devices to prevent damage The temperature sensor is accurate to about 2 deg C with a resolution of 0 0625C Since it is mounted near the center of the card it indicates an average temperature not the maximum on the module Local hot spots may be 5 to 10 C hotter than the indicated reading The temperature sensor can be read by the host at address PCI BARO 0x3 The temperature is computed as Temperature C reading 0 0625 where the reading is a 12 bit signed number This table summarizes the relationship C BINARY wo ooo Er 8 mmm 59 25 9010109 19 os 0X03x0090 Q4 0 9000p00x0
47. Studio 2006 The example is coded to minimize the dependency on particulars of the graphic interface and to maximally illustrate high performance board control and data handling To that end the board specific control code has been factored into the ApplicationIo cpp h source files and this source is shared and used for the supplied example independent of the compiler used This code that performs the bult of the functionality of the example By contrast the User Interface portion of the program is de emphasized since it s implementation is not relevant to the control and operation of the module X3 2M User s Manual 44 Program Design The Snap example is designed to allow repeated data reception operations on command from the host As mentioned earlier received data can be saved as Host disk files When using modest samples rates less than 10 MB s data can be logged to standard disk files However full bandwidth storage of multiple A D channels can require up to 160 MB s capacity so a dedicated RAIDO drive array partitioned as NTFS for data storage will be required to provide storage at such rates The example application software is written to perform minimal processing of received data and is a suitable template for high bandwidth logging applications The example uses various configuration commands to prepare the module for data flow Parametric information is obtained from a Host GUI application but the code is written to be GUI agno
48. Table 6 Clock Device Add cum A Ue IR e Oe te edd s be a P tev dee 78 Table 7 PEL Interface Word Forimat z ue eter tette t tete eee eee P ORE det ehe Hr stb a a buie 78 Table 8 PLE E 78 Table 9 PDE Read Sequence ince e et RO RE eR RU D UH tr RET RENT leia 79 Table 10 PEL Read Word aene e een a HEU e et ERE NRI a Hebe teo peu vitae 79 Table 11 PLE Output Assiptiments u tee RR RR E OR ER NT AD ee 79 Table 12 X3 2M External Sample Clock Timing essere nnne nnne nnne nnne 80 Table 13 External Trigger Input ise eee t e Rt ee tet iban neis cda 82 Table 14 External Trigger Electrical Charactertstcs enne enne enne enne nnne nnns 82 Table 15 X3 Environmental Ratings for Temperature 85 Table 6 Reduced Power OA n etes n eu OR Ee DR dt 86 Table I7 Alert Types EE 87 Table 18 Alert Packet Formation ped e tede Eee rd ibn etr b Ra dee e adenine Mn aus 88 Table 19 X3 2M Power Consumption et e e cada 91 Table 20 X3 2M IN SAA 92 Table 21 X3 2M Analog Performance Summarg cnn r non ron nn rn RR RR RR Ran Ran Ran rn nn narrar narran rra rnnnnrrannnos 93 Table 22 X3 2M XMC Connector PIS Pinout scd ee RE e ERE HE PURSE ENEE 101 Table 23 P15 Signal Desctiptions i teet ee OY HER ERE ERE DHT DR Ee E Dg 102 Table 24 X3 2M XMC Secondary Connector P16 Pot 104 Table 25 P16 Signal Description aos 105 Table 26 X3 2M JP3 Xilinx JTAG Connector Pmout enne nennen nnne nnne nnne nnns 107 X3 2M User s Manual
49. V the application FPGA Output Voltage 3 0V For load lt 12mA 0 lt 0 8V Output Current 12mA FPGA can be reconfigured for custom designs for other drive currents Input Logic 1 gt 2VDC Thresholds 0 lt 0 8VDC Input Impedance gt 1M ohm 15 pF Excludes cabling Pulldown 8K ohms Pulldown is in the logic Table 10 Digital IO Bits Electrical Characteristics Parameter Value Notes Input Voltage Max 3 6V Exceeding these will damage Min 0 3V the application FPGA Signaling LVDS 2 5V EIA 644 Standard Input common Min 0 30V mode voltage Typ 1 25V Max 2 20V Input Logic Min 0 10V Differential voltage Vin Vin Thresholds Typ 0 30V Max 0 60V Termination 100 ohms X3 2M User s Manual 36 Table 11 Digital IO Clock Input Electrical Characteristics Notes on Digital IO Use The digital IO on X3 family as supported using the standard FrameWork Logic is intended for low speed bit IO controls and status The interface is capable of data rates exceeding 75MHz and custom logic developers can implement much higher speed and sophisticated interfaces by modifying the logic The digital IO clock input and LVDS signal pair is a capable of rates exceeding 200 MHz Since the bit IO is connected to the command channel interface in the standard logic this limits the effective update or read rate to about 200 kHz The limitation on this rate is the slow speed of the c
50. a Stream 88 UsmetheX3 32M s stetit oe Bde Eed 88 A A EIL 88 Getting Good Analog Bertomance sesten tests teS tsten estss esteses testes esteseesesesess et 89 ApplicatiOnXEOSIC EE 89 ere Te 89 Production Calibrations uerge gg e etta aa E re tree reuse eset hia E 90 Updating the Calibration Cocffcients ennemi EEE E nennen nnne 90 Nee ER ages eMe Rete quit tte e et delent RE HI Ure Ea 91 Power Consumpt omy 4 2 genii tem eset e e ERIE 91 Environmental Ratings 5 5 c ccc cust ele re Ne be e E e Eee reti Ue Ne eel bee o bent 91 Environmental Ratings ue ege io Gong Hr eee bt cr eed RAO RUE Ner EN 92 Analog tee Saal Seascale tens eee ied dee IVES etn Rib ee DR LSU tid 93 CONNEC CLOTS eee dates Cenc CIBC RU ge dee eei tear Glan de ue ep dee det EE oe et 98 Input Connector JP T iicet te reete e ileus ca toot e eed Var E ee eee n devel vais cette eel ee ye epe E eue Een eee Ege 98 X3 2M User s Manual AMES as 100 AMG P16 Connect m 103 Note PXI Express signals are only available when PXIE adapter card is use 106 Xilinx JLAG Codi E 107 Me ERI p 108 X3 2M User s Manual List of Tables Table 1 X3 X MG Family s fess hc Seow ey eh Ne es eee Ee 26 T ble 2 X3 XMC Famiuly Peripherals 5 ete e RT RE WWE Rs ER ee ees 27 T ble3 X3 Computing Core Devices A e a ree 27 Table 4 PCT Express Standards Conipliance o e a A E 29 Table 5 Interfaces f
51. ace to that region We further query if the ROM has been programmed using Is Empty method If revision system field is in alphanumeric form we display the relevant board information in the message log otherwise log a message that Module ID rom is uninitialized X3 2M User s Manual 60 Developing Host Applications Developing an application will more than likely involve using an integrated development environment IDE also known as an integrated design environment or an integrated debugging environment This is a type of computer software that assists computer programmers in developing software Refer to Chapter 3 Creating Applications using an IDE within the Malibu Library Users Manual for specific instructions for each of the supported compilers X3 2M User s Manual 61 Applets The software release for a baseboard contains programs in addition to the example projects These are collectively called applets They provide a variety of services ranging from post analysis of acquired data to loading programs and logic to a full replacement host user interface The applets provided with this release are described in this chapter Shortcuts to these utilities are installed in Windows by the installation To invoke any of these utilities go to the Start Menu Programs lt lt Baseboard Name gt gt and double click the shortcut for the program you are interested in running Common Applets
52. agment Set Decimation Factor if enabled if Settings DecimationEnable Module Input Decimation Settings DecimationFactor else Module Input Decimation 1 The module supports programmable decimation of acquired samples The preceding code fragment applies the user specified decimation factor to the hardware Route clock to active analog devices Set reference based on clock source to obtain correct FrequencyActual double reference if Settings SampleClockSource 0 reference SampleRate Module Input Info ClockFactor Module Clock OutputClock Ad9511 oExternal else reference Module Input Info ReferenceClock Module Clock OutputClock Ad9511 0Vco Apply timebase correction factor if available double correction Settings PllCorrection if correction correction correction 1 0 NaN so fix it Module Clock ReferenceCalibrationFactor correction Module Clock Reference reference Module Clock Frequency SampleRate The module may accept an external sample clock but also features a programmable PLL clock source which may be used as a sample clock for the A D input channels A11 channels trigger together Module Input ExternalTrigger Settings ExternalTrigger 1 Frame count in units of packet elements if Settings Framed Module Input Framed Settings FrameCount else Module Input Unframed Samples will not be acqui
53. ampleRate static cast float Module Clock FrequencyActual std stringstream msg msg precision 6 msg Actual sampling rate ActualSampleRate 1 e3 KHz UI gt Log msg str FTicks 0 Timer Enabled true Handle Data Required Once streaming is enabled and the module is triggered data flow will commence Samples will be accumulated into the on board FIFO then they are bus mastered to the Host PC into page locked driver allocated memory following a two word header data packets Upon receipt of a data packet Malibu signals the Stream OnDataAvailable even By hooking this event your application can perform processing on each acquired packet Note however that this event is signaled from within a background thread So you must not perform non reentrant OS system calls such as GUI updates from within your handler unless you marshal said processing into the foreground thread context void ApplicationIo HandleDataAvailable PacketStreamDataEvent amp Event if Stopped return static PmcBuffer Packet Extract the packet from the Incoming Queue Event Sender gt Recv Packet When the event is signaled the data buffer must be copied from the system bus master pool into an application buffer The preceding code copies the packet into the local PmcBuffer called Packet Process the data packet X3 2M User s Manual 58 int Channel Packet Header gt Peripheral
54. andard data acquisition function and is supported by software tools for data analysis and logging In this manual the FrameWork Logic features for each card are described in in general to explain the standard hardware functionality The X3 FrameWork Logic User Guide provides developers with the tools and know how for developing custom logic applications See this manual and the supporting source code for more information The X3 XMC modules are supported by the FrameWork Logic Development tools that allow designs to be developed in HDL or MATLAB Simulink Standard features are provided as components that may be included in custom applications or further modified to meet specific design requirements X3 2M User s Manual Integrating with Host Cards and Systems The X3 XMCs may be directly integrated PCI Express systems that support VITA 42 3 XMC modules The host card must be both mechanically and electrically compatible or an adapter card must be used The XMC modules conform to IEEE 1386 specification for single width mezzanine cards This specification is common to both PMC and XMC modules and specifies the size mounting mating card requirements for spacing and clearances There are several adapter cards that are used to integrate the XMC modules into other form factor PCI Express systems such as desktop systems There are also adapter cards to electrically adapter the PCI Express XMC modules in older PCI systems that use
55. array of HDD A single HDD will NOT meet the required continuous storage rates when the aggregate data rate is above 50 MB s A D Sample Destination Maximum Sample Rate FPGA logic or module data buffer 10 MSPS per channel Host system memory 10 MSPS per channel host system PCle must be x4 lane slot Host system HDD 10 MSPS per channel host system PCIe must be x4 lane slot AND either high performance SSD or a RAID array of HDD drives Table 1 X3 2M A D Sample Rates Sample Rate Generation and Clocking Controls The X3 2M can use a sample clock from the PLL the PLL locked to an external clock or an external clock This allows the module to synchronize to a system clock or use software programmable sample rates All clock selections are software programmable on the module Clock Mode Use for Restrictions Benefits PLL with internal Software programmable Clock rate has tuning resolution of about 10 Low jitter clock reference clock Hz PLL with external Software programmable External reference must be 1 to 100 MHz Lock to an external clock and reference clock referenced to 50 50 duty cycle see electrical requirements generate an sample clock external clock input below locked to it Clean up external clock jitter using the PLL External Clock Synchronize sampling to External clock must be 1 to 100MHz 50 50 Sample rate can be system devices duty cycle low jitter synchronized with other devices in the
56. at the beginning of any read from the port Data read from output bits is equal to the last latched bit values i e the last data written to the port by the host Digital I O port pins are pulled down to digital ground within the logic device Consequently the state of the DIO pins do not change as power is applied to the PC during system start up The pulldown resistor is about 8K ohms External signals connected to the digital I O port bits or timer input pins should be limited to a voltage range between 0 and 3 3V referenced to ground on the digital I O port connector Exceeding these limits will cause damage to the X3 module Digital UO Timing The following diagram gives timing information for the digital I O port when used in external readback clock mode see above for details This data is derived from device specifications and is not factory tested Extemal Readback Clock Input data V Data Valid V Figure 12 Digital I O Port Timing Table 9 Digital I O Port Timing Parameters Ho p X3 2M User s Manual 35 Digital IO Electrical Characteristics The digital IO pins are LVTTL compatible pins driven by 3 3V logic The DIO port connects directly to the application FPGA The DIO input clock is LVDS a differential input Warning the DIO pins are NOT 5V compatible Input voltage must not exceed 3 6V Parameter Value Notes Input Voltage Max 3 6V Exceeding these will damage Min 0 3
57. ative dsp com products malibu htm e On line Help nnovative Integration Technical Support nnovative Integration Web Site www innovative dsp com Online Help Help for Malibu is provided in a single file Malibu chm which is installed in the Innovative Documentation folder during the default installation It provides detailed information about the components contained in Malibu their Properties Methods Events and usage examples An equivalent version of this help file in HTML help format is also available online at http www innovative dsp com support onlinehelp Malibu Innovative Integration Technical Support Innovative includes a variety of technical support facilities as part of the Malibu toolset Telephone hotline supported is available via X3 2M User s Manual 11 Hotline 805 578 4260 8 00AM 5 00 PM PST Alternately you may e mail your technical questions at any time to techsprt innovative dsp com Also feel free to register and browse our product forums at http forum iidsp com which are an excellent source of FAQs and information submitted by Innovative employees and customers Innovative Integration Web Site Additional information on Innovative Integration hardware and the Malibu Toolset is available via the Innovative Integration website at www innovative dsp com Typographic Conventions This manual uses the typefaces described below to indicate special text Typeface Meaning Text
58. ave at least 1 GB of memory 2 GB recommended 1 GB available hard disk space and a DVD ROM drive Most versions of Windows released after Win2000 including XP Vista or Windows 7 referred to herein simply as Windows or later is required to run the developer s package software and are the target operating systems for which host software development is supported Software Installation The development package installation program will guide you through the installation process Note Before installing the host development libraries VCL components or MFC classes you must have Microsoft MSVC Studio version 9 or later CodeGear RAD Studio 2007 2009 Embarcadero Rad Studio 2010 or QtCreator installed on your system depending on which of these IDEs you plan to use for Host development If you are planning on using these environments it is imperative that they are tested and known operational before proceeding with the library installation If these items are not installed prior to running the Innovative Integration install the installation program will not permit installation of the associated development libraries However drivers and DLLs may be installed to facilitate field deployment You must have Administrator Privileges to install and run the software hardware onto your system refer to the Windows documentation for details on how to get these privileges X3 2M User s Manual 13 Starting the Installation To begin the insta
59. ce it is central to module operation Software support tools provide convenient access to the temperature and thermal controls These should be used in application programming configure and monitor the temperature as illustrated below Open the module Innovative X3 SD Module Module Target 0 Module Open Create reference to thermal management object on module const LogicTemperatureIntf amp Temp Module Thermal Read current temperature float t Module LogicTemperature Read write current warning temperature float t Module LogicWarningTemperature Module LogicWarningTemperature 70 0 Read current failure temperature float t Module LogicFailureTemperature See if the module is in thermal shutdown bool state Module Failed X3 2M User s Manual 39 Thermal Failures The X3 modules will shut down if the module temperature exceeds 85C This means that something is seriously wrong either with the module or with the system design Damage may occur if the module temperature exceeds this limit The Application LED will blink when the a temperature failure has occurred If your software was monitoring the alert packets you will also receive a temperature warning alert prior to failure The module temperature can always be read by the application software so this can also provide information pointing to overheating The most important thing to do is to determine the root cause of the
60. control 0 input default 2 DIO bits 23 16 direction control 0 input default 3 DIO bits 31 24 direction control 0 input default 4 DIO bits 39 32 output enable 0 input default 5 DIO bits 43 40 output enable 0 input default X3 2M User s Manual 32 Bit Function 30 6 31 Sample DIO inputs when DIO EXT CLK is true otherwise always sample 0 sample always default Figure 8 DIO Control Register BAR1 0x14 Port Address DIO L BAR1 0x13 DIO H BARI 0x16 Figure 9 Digital IO Port Addresses Data may be written to read from the digital I O port using the digital I O port data registers Data written to ports bits which are set for output mode will be latched and driven to the corresponding port pins while data written to input bits will be ignored The input DIO may be clocked externally by enabling the external digital clock bit in the appropriate configuration register If the internal clock is used the data is latched at the beginning of any read from the port Data read from output bits is equal to the last latched bit values i e the last data written to the port by the host Digital I O port pins are pulled down to digital ground within the logic device Consequently the state of the DIO pins do not change as power is applied to the PC during system start up The pulldown resistor is about 8K ohms External signals connected to the digital I O port bits o
61. cquisition applications Flexible trigger methods include counted frames software triggering and external triggering The sample rate clock is either an external clock or on board programmable PLL clock source Data acquisition control signal processing buffering and system interface functions are implemented in a Xilinx Spartan3A DSP FPGA 1 8M gate device Two 512Kx32 memory devices are used for data buffering and FPGA computing memory The logic can be fully customized using VHDL and MATLAB using the FrameWork Logic toolset The MATLAB BSP supports real time hardware in the loop development using the graphical block diagram Simulink environment with Xilinx System Generator The PCI Express interface supports continuous data rates up to 260 MB s between the module and the host A flexible data packet system implemented over the PCIe interface provides both high data rates to the host that 1s readily expandable for custom applications What is Malibu Malibu is the Innovative Integration authored component suite which combines with the Borland Microsoft or GNU C compilers and IDEs to support programming of Innovative hardware products under Windows and Linux Malibu supports both high speed data streaming plus asynchronous mailbox communications between the DSP and the Host PC plus a wealth of Host functions to visualize and post process data received from or to be sent to the target DSP What is C Builder C Builder is a genera
62. d For example the first sub install for Quadia Applets Examples Docs and Pismo libraries is shown below The installation will display a progress window similar to the one shown below for each item checked Quadia Documentation Thank you for choosing Quadia Installing Documentation Figure 3 Progress is shown for each section X3 2M User s Manual 16 Tools Registration Registration Information Name First Email Address Telephone Country Code Area Code Number Extension Fax Area Code Number Company Name Address City State Country Postal Code Product Board zi E Register Now Register Later Figure 4 ToolSet registration form Bus Master Memory Reservation Applet Reserve Memory for Dsp Combined DSP Board Usage Rsv Region Size MB Configuration Total physical memory MB 2047 Non paged pool size MB 255 Status Ok Update Help Exit Ready X3 2M User s Manual At the end of the installation process you will be prompted to register If you decide that you would like to register at a later time click Register Later When you are ready to register click Start All Programs Innovative Board Name Applets Open the New User folder and launch NewUser exe to start the registration application The registration form to the left will be displayed Before beginning DSP an
63. d Host software development you must register your installation with Innovative Integration Technical support will not be provided until registration is successfully completed Additionally some development applets will not operate until unlocked with a passcode provided during the registration process It is recommend that you completely fill out this form and return it to Innovative Integration via email or fax Upon receipt Innovative Integration will provide access codes to enable technical support and unrestricted access to applets At the conclusion of the installation process ReserveMem exe will run except for SBC products This will allow you to set the memory size needed for the busmastering to occur properly This applet may be run from the start menu later if you need to change the parameters For optimum performance reserve at least 64 MB of memory for each Innovative board to be used simultaneously within the PC plus 32 MB for other system use For example if using two X5 400M modules reserve 2 64 32 MB 160 MB To reserve this memory the registry must be updated using the ReserveMem applet Simply type the desired size into the Rsv Region Size MB field click Update and the applet will update the registry for you If at any time you change the number of boards in your system then you must invoke this applet found in Start All Programs Innovative target board Applets Reserve Memory After updating t
64. ds to the Host as packets containing out of band information concerning the state of the module For instance if the analog inputs were subjected to an input over range an alert packet would be sent to the Host interspersed into the data stream indicating the condition This information can be acted upon immediately or simply logged along with analog data for subsequent post analysis Module OnBeforeStreamStart SetEvent this Applicationlo HandleBeforeStreamStart Module OnBeforeStreamStart Synchronize Module OnAfterStreamStart SetEvent this amp ApplicationIlo HandleAfterStreamStart Module OnAfterStreamStart Synchronize Module OnAfterStreamStop SetEvent this amp ApplicationIo HandleAfterStreamStop Module OnAfterStreamStop Synchronize Similarly HandleBeforeStreamStart HandleAfterStreamStart and HandleAfterStreamStop handle events issued on before stream start after stream start and after stream stop respectively These handlers could be designed to perform multiple tasks as event occurs including displaying messages for user These events are tagged as synchronized so Malibu will marshall the execution of the handlers for these events into the main thread context allowing the handlers to perform user interface operations The Stream object manages communication between the application and a piece of hardware Separating the I O into a separate class clarifies the distinction between an I O protocol and the implementin
65. dule family has an FPGA based computing core that controls the data acquisition process providing data buffing and host communications The computing core consists of a Xilinx Spartan3 or 3A DSP FPGA and two banks of 2MB SRAM memory The FPGA uses the memories for data buffering and computational workspace Table 3 X3 Computing Core Devices Feature X3 Module Device Part Number Application Logic SD SDF Xilinx Spartan 3 1M XC351000 4FGG456C FPGA 10M Servo 25M DIO Xilinx Spartan 3A DSP 1 8M XC3SD1800 4FGG676C 2M SD16 A4D4 Buffer Memory SD SDF Synchronous Burst ZBT 1Mx16 100 MHz SRAM SRAM 10M Servo 25M DIO 512Kx32 133 MHz 2M SD16 A4D4 Computational SD SDF Synchronous Burst ZBT 1Mx16 100 MHz Memory SRAM SRAM 10M Servo 25M DIO 512Kx32 133 MHz 2M SD16 A4D4 The main focus of the module is the X3 s computing core which connects the IO peripherals host communications and support features Each IO device directly connects to the application FPGA on the X3 module providing tight coupling for high performance Real time IO The FPGA logic implements an interface to each device that connects them to the X3 2M User s Manual 27 controls and data communications features on the module Support features such as sample triggering and data analysis are implemented in the logic to provide precise real time control over the data acquisition process X3 Computing Core Bl
66. e object has to be explicitly opened The open method open hardware Open Devices Module Target Settings Target Module Open Module Reset UI gt Status Module Device Opened Opened true This code shows how to open the device for streaming Each baseboard has a unique code given in a PC For instance if there are three boards in a system they will be targets 0 1 and 2 The order of the targets is determined by the location in the PCI bus so it will remain unchanged from run to run Moving the board to a different PCI slot may change the target identification The Led property can be use to associate a target number with a physical board in a configuration The Malibu method Open is called to open the device driver for the baseboard and allocate internal resources for use The next step is to call Reset method which performs a board reset to put the board into a known good state Note that reset will stop all data streaming through the bus master interface and it should be called when data taking has been halted Le Connect Stream Stream ConnectTo amp Module StreamConnected true UI gt Status Stream Connected FHwPciClk Module Debug PciClockRate FHwBusWidth Module Debug PciBusWidth DisplayLogicVersion FChannels Module Input Info Channels Channels FDevices Module Input Info Channels Devices X3 2M User s Manual 52 Once the object i
67. e units The X3 10M object represent the board The Packet Stream object encapsulates supported board specific operations The Scripter object can be used to add a simple scripting language to the application for the purposes of performing hardware initialization during FPGA firmware development The PmcBuf fer class object can be used to access the contents of buffers received from the module during streaming When the device driver is opened using the call to ApplicationIo Open we hook up event handlers to various events call backs that the Malibu libraries generate when interacting with the X3 10M object X3 2M User s Manual Hook script event handlers Script OnCommand SetEvent this amp ApplicationIo HandleScriptCommand Script OnMessage SetEvent this amp ApplicationIo HandleScriptMessage Configure Module Event Handlers Module Logic OnFpgaFileReadProgress SetEvent this amp ApplicationIo HandleProgress Module Logic OnFpgaFileReadComplete SetEvent this amp ApplicationIo HandleParseComplete Module Logic OnFpgaParseProgress SetEvent this amp ApplicationIo HandleProgress Module Logic OnFpgaParseComplete SetEvent this amp ApplicationIo HandleParseComplete Module Logic OnFpgaParseMessage SetEvent this amp ApplicationIo HandleLoadError Module Logic OnFpgaLoadProgress SetEvent this amp Applicationlo HandleProgress Module Logic OnFpgaLoadComplete SetEvent this
68. ectMAP interface to the FPGA which is a byte wide configuration port on the FPGA from the host PCI Express X3 2M User s Manual 28 interface The configuration port for the FPGA is independent of the packet interface to the host and does not involve the use of the Velocia packet system The image can be loaded at any time over the SelectMAP interface allowing dynamic configuration of the FPGA for advanced applications Note There is no on card storage for this image and it must be loaded each time the host computer is powered down or reset Adding New Features to the FPGA The functionality of the computing core can be modified using the FrameWork Logic tools for the X3 module family The tools support development in either VHDL or MATLAB Signal processing data analysis and unique functions can be added to the X3 modules to suit application specific requirements See the X3 FrameWork Logic User Guide for further information X3 PCI Express Interface The X3 module family has a PCI Express interface that provides a lane 2 5 Gbps full duplex link to the host computer The interface is compatible with industry standard PCI Express systems and may be used in a variety of host computers The following standards govern the PCI Express interface on the X3 XMC modules Table 4 PCI Express Standards Compliance Standard Describes Standards Group PCI Express 1 0a PCI Express electrical and protocol standards PCI SIG
69. ed indicating the the host did not consume the data quickly enough ADC Trigger The ADC trigger went active ADC Overrange An ADC channel was overranged Alert Packet Format Alert data packets have a fixed format in the system The Peripheral Device Number PDN is programmable in the software and is included in the packet header thus identifying the alert data packets in the data stream The packet shows the timestamp in system time what alerts were signaled and a status word for each alert Dword Description 0 Header 1 PDN amp Total N of Dwords in packet e g Headers data payload 1 Header 2 0x00000000 2 Alerts Signaled 3 Timestamp 4 0 5 Software Word 6 temp_sensor_error amp temp_error amp 00 amp X 000 amp temp_data 7 temp_warning amp 000 amp X 000 amp temp_data 10 8 0 12 X 1303000 amp 000 amp mq_overflow 0 X3 2M User s Manual 87 35 13 unused Table 18 Alert Packet Format Since alert packets contain status words such as temperature for each packet a software alert can essentially be used to read temperature of the module and so that 1t can be recorded Software Support Applications have different needs for alert processing Aside from the bulk movement of data most applications require some means of handling special conditions such as post processing upon receipt of a stop trigger or closing a driver when
70. egister X 40 would be performed as X3 2M User s Manual 78 BARI 0xA X 00804000 Set up a read from PLL address X 40 BARI 0xA X x01303xx See format below Table 9 PLL Read Sequence The PLL readback word has the following format The PLL read must be performed before any additional writes are performed 0000000 X 1303 Table 10 PLL Read Word Notes About the PLL Configuration The PLL must be initialized through software before it will make a the correct sample clock rate This device has many configurations that require programming of a large number of registers prior to use The X3 support software provides PLL configurations that satisfy most applications and should be used if possible For custom configurations the AD9510 data sheet should be consulted The X3 2M requires the clock assignments as show in the following table The sample clock fs in the FPGA clock is connected to AD9510 output 0 The divider should be programmed to use LVPECL output to the FPGA while the other clocks are CMOS FPGA 0 LVPECL A D devices 0 1 2 44 CMOS A D devices 3 4 5 54 CMOS A D devices 6 7 8 CMOS A D devices 9 10 11 74 CMOS Table 11 PLL Output Assignments The VCXO is connected to the CLK2 input to the PLL The standard reference clock is 100 MHz to the PLL although an external reference may be used The output of the PLL section of the AD9510 can therefore be programmed to many numbers in
71. er Guide for more details and examples Data Buffer SRAM The second SRAM is provides a 2MB memory pool local to the FPGA The Framework Logic implements a data buffer with one or more queues for the A D and D A streams as appropriate for the particular X3 module In the Framework logic the SRAM use is demonstrated as a multiple queue FIFO memory that divides the 2 MB memory buffer into separate queues virtual FIFOs for input and output The logic component referred to as Multi Queue SRAM controls the SRAM to create the FIFO queue functionality Custom logic applications can use the Multi Queue SRAM buffer component to add additional queues for new devices EEPROM A serial EEPROM on the X3 modules is used to store configuration and calibration information The interface to the serial EEPROM is an I2C bus that is controlled by the PCI logic device The device is an Atmel AT24C16 10SI a 16K bit device The I2C bus is slow and the calibration is read out of the EEPROM at initialization time by the application software and written into registers in the application logic for real time error correction The EEPROM also has a write cycle limit of 100K cycles so it should only be written to when calibration is performed or configuration information changes Once the write cycle duration limit is exceeded the device will not reliably store data any more X3 2M User s Manual 31 Digital I O The X3 modules have a digital IO port and is acc
72. erformance begins to degrade below this output data rate The decimation simply discards N points for every point kept no averaging or filtering is used When decimation is true the number of points captured in the framed mode is the number of decimated points in other words the discarded points do not count Maximum decimation rate is 1 4095 When decimation is used in the framed trigger mode the number of points captured is after decimation The frame count is always the actual number of points inserted into the FIFO X3 2M User s Manual 82 48 channel System Example As an example a 48 channel system can be created using four X3 2M cards An Innovative X3 Timing card is used in this example to provide the synchronized triggers and clocks The X3 Timing card is configured to provide a 10 MHz reference clock to the system and triggers that are synchronized to this reference clock One of the X3 2M cards designated the sync master drives a sync to the other cards When the software releases the master sync all cards then start sampling in synchronization A trigger from either the system software or an external source begins the data acquisition playback process Clock Trigger Clock Clock Trigger A 64 channel simultaneously sampling system employing 4x X3 2M and X3 Timing X32M Master o Trigger o A Bel Glock E er Clock er 8 c Trigger A D 0 11 gt
73. ervo 12 channels 16 bit 250 ksps A D and 12 Xilinx Spartan3A DSP 1 8M Electromechanical controls channels 16 bit 250 ksps DAC low 3 4M option process instrumentation latency 16 bits front panel DIO X3 DIO 64 bits 32 pairs digital IO to FPGA Xilinx Spartan3A DSP 1 8M Test pattern generation LVCMOS or LVDS with streaming 3 4M option remote IO interfaces digital playback and capture features controls X3 10M 8 channels of 16 bit 25 MSPS A D with Xilinx Spartan3A DSP 1 8M Measurement for high speed programmable gain and instrumentation vibration ultrasound fault front end Xilinx Spartan3A DSP FPGA detection systems neurophysical applications X3 2M 12 channels of 16 bit 10 MSPS A D with Xilinx Spartan3A DSP 1 8M Multi channel applications in programmable gain and instrumentation ultrasound video sensors and front end Xilinx Spartan3A DSP FPGA optical sensors X3 SD16 16 channels of 24 bit 144 kHz A D and Xilinx Spartan3A DSP 1 8M Vibration monitoring 192 kHz D A with programmable gain and recording control Acoustic instrumentation front end Xilinx monitoring Geophysical Spartan3A DSP FPGA sensor interfaces Table 1 X3 XMC Family The X3 XMCs feature a Xilinx Spartan3 or Spartan3A DSP FPGA core for signal processing and control In addition to the features in the Spartan3 3A logic such as embedded multipliers and memory blocks the FPGA computing core has two local SRAMs for data buffering and computing memory There
74. essible over P16 that provides basic bit IO The port provides 44 bits of IO that may be used as inputs or outputs and a differential clock input The port is configured and accesses directly from the PCI Express host For more advance applications digital IO port may be reconfigured in custom logic applications for a variety purposes since it provides direct connections to the applicant FPGA The DIO port is presented on P16 See the connectors section of this chapter the connector pin out and information about the connector Software Support The digital I O hardware is controlled by the UsesExtendedDioPort class Its properties Table 6 IUsesExtendedDioPort Class Operations DioPortConfig Configures banks of bits for input or output DioPortData Broadside Read Write to low order 32 bits of DIO DioPortDataHigh Property Broadside Read Write to high order 12 bits of DIO Only Typical use of the digital IO port involves first configuring the port using the DioPortConfig operator This sets the byte direction and the clock mode The port is then ready for read write operations via DioPortData or DioPortDataHigh Hardware Implementation Digital I O port activity is controlled by the digital I O configuration control and data register Port direction is controlled by the configuration control register Bit Function 0 DIO bits 7 0 direction control 0 input default 1 DIO bits 15 8 direction
75. fic which each baseboard will generate Applications operating at transfer rates in excess of 20 MB sec should reserve Reserve Memory for Dsp Baseboards j 1 Numberinstaled Matador family Type additional contiguous busmaster memory to ensure gap free data acquisition To reserve this memory the registry must be updated using the ReserveMemDsp applet If at any time you change the number of or rearrange the baseboards in your system then you must invoke this applet to reserve the proper space for the busmaster region See the Help file ReserveMemDsp hlp for operational details Data Analysis Applets System 2048 y BM Region Size KB 2048 Rsv Region Size KB Status Configuration Total physical memory MB 255 Non paged pool size MB 4 Ok Update Ready Binary File Viewer Utility BinView exe BinView is a data display tool specifically designed to allow simplified viewing of binary data stored in data files or a resident in shared DSP memory Please see the on line BinView help file in your Binview installation directory X3 2M User s Manual s BinView c vista vistat 1 dump bin ac Time Frequency Text Summary Server I4 a b Pl ZBROG 92 la xl X lt Zoom Out Zoom In gt gt 48 34 1 64 Counts e9 AL Sample E Leap 10 Amplitude vs Offset 30 40
76. flows over the data link as packets The maximum transfer rate over the data link is 264 MB s with a 220 MB s sustained rate The data packets contain a Peripheral Device Number PDN that identifies the peripheral associated with the this data packet In this way the packet system is extensible to other devices that may be added to the logic For example an FFT analysis can be added to the logic and its result sent to the host as a new PDN for display and further analysis while maintaining other data streams from A D channels Table 5 Interfaces from PCI Express to Application Logic Application Logic Max Data Rate Typical Use Interface Data Link 264 MB s burst 240 MB s sustained Velocia packet system interface main path for data communications Command Channel 5 MB s sustained Command control and status SelectMAP 5 MB s Application logic configuration Data Buffering and Memory Use There are two 2MB SBSRAM devices attached to the application FPGA that provide data buffering and computational RAM for FPGA applications X3 2M User s Manual 30 Computational SRAM The SRAM on the X3 family is a2MB memory dedicated as FPGA local memory Applications in the FPGA may use the SRAM as a local buffer memory if the data buffer is too large to fit in FPGA block RAMs or as memory for an embedded processor in the FPGA The SRAM device connected to each Application FPGA is 2 MB total size organized as 1M by 16
77. g and analysis tool CodeHammer JTAG support for Code Composer Studio Innovative Components C Builder Support Product Registration ONE TENE Using this interface specify which product to install and where on your system to install it Figure 2 Innovative Install Program 1 Select the appropriate product from the Product Menu 2 Specify the path where the development package files are to be installed You may type a path or click Change to browse for or create a directory If left unchanged the install will use the default location of C Innovative 3 Typically most users will perform a Full Install by leaving all items in the Components to Install box checked If you do not wish to install a particular item simply uncheck it The Installer will alert you and automatically uncheck any item that requires a development environment that is not detected on your system 4 Click the Install button to begin the installation Note The default Product Filter setting for the installer interface is Current Only as indicated by the combo box located at the top right of the screen If the install that you require does not appear in the Product Selection Box 1 Change the Product Filter to Current plus Legacy X3 2M User s Manual 15 Each item of the checklist in the screen shown above has a sub install associated with it and will open a sub install screen if checke
78. g hardware In Malibu high rate data flow is controlled by one of a number of streaming classes In this example we use the events of the PacketStream Class to alert us when a packet arrives from the target When a data packet is delivered by the data streaming X3 2M User s Manual 51 system OnDataAvailable event will be issued to process the incoming data This event is set to be handled by HandleDataAvailable After processing the data will be discarded unless saved in the handler Similarly OnDataRequired event is handled by HandleDataRequired Configure Stream Event Handlers Stream OnDataAvailable SetEvent this Applicationlo HandleDataAvailable Stream OnDataAvailable Synchronize In this example a Malibu SoftwareTimer object has been added to the ApplicationIo class to provide periodic status updates to the user interface The handler below serves this purpose Timer OnElapsed SetEvent this Applicationlo HandleTimer Timer OnElapsed Thunk An event is not necessarily called in the same thread as the UI If it is not and if you want to call a UI function in the handler you have to have the event synchronized with the UI thread The call to Synchronize directs the event to call the event handler in the main UI thread context This results in a slight performance penalty but allows us to call UI methods in the event handler freely Creating a hardware object does not attach it to the hardware Th
79. gic designs can use it for any purpose When X3 2M User s Manual 40 using the stock firmware the state of user logic LED D5 can be controlled using the Innovative X3 SD Led property JTAG Scan Path The X3 modules have a JTAG scan path for the Xilinx devices on the module This is used for logic development tools such as Xilinx ChipScope and System Generator and for initial programming of the PCI FPGA configuration FLASH ROM There are three devices in the scan chain the Xilinx FLASH ROM Spartan 3E 250K used for PCI control and the Spartan 3 3A application logic When the devices are identified in the scan chain you will see these devices in this order Table 13 X3 Modules FPGA JTAG Scan Path JTAG Device Module Device Function Number 0 All X3 Xilinx XCF028 FLASH ROM PCI FPGA Spartan3E logic configuration ROM 1 All X3 Xilinx Spartan3E 250 FPGA Control FPGA for PCI XC3S250E 4FTG256C Interface 2 X3 SD X3 SDF Xilinx Spartan3 1000 FPGA Application Logic XC3S1000 4FGG456C optional 2M device could be installed here All others Xilinx Spartan3A DSP 1800 FPGA XC3SD1800 4FGG676C optional 3 4M device could be installed here FrameWork Logic Many of the standard X3 XMC features are implemented in the application logic This feature set includes a data flow triggering features and application specific features In many cases this logic provides the features needed for a st
80. hannels Group The X3 10M support simultaneous acquisition from up to eight analog input channels X3 2M User s Manual 46 simultaneously However to preserve bandwidth of the 32 bit data paths on board the module channels must always be enabled in pairs For instance in order to flow data from channel one channel zero must also be enabled The software enforces this restriction so that packets received from the module will always consist of integer multiples of 16 bit channel pairs Channel Range Group The X3 10M features individually programmable gain for each analog input channel controlled via the Range grid control Ranges are modal as listed in the table below Table 15 Analog Gain Ranges Trigger Group Acquisition may be triggered using an external signal or via software The Trigger Source radio control provides the means of selection Triggers act as a gate on data flow no data flows until a trigger has been received Triggers may be initiated via software or hardware depending on the Trigger Source control If software the application program must issue a command to initiate data flow If hardware a signal applied to the external trigger connector controls data flow Triggers are modal depending on the Trigger Mode control In Unframed mode triggers are level sensitive and data flow proceeds while the trigger is in the high active state and stops while the trigger is in the low inactive s
81. he Malibu Red package If there are any board specific steps they will be listed at the end of this chapter Linux Directory Structure When a board package is installed its files are placed under the usr Innovative folder The base directory is named after the board with a version number attached for example the version 2 0 X5 400 RPM extracts into usr Innovative X5 400 2 0 This allows multiple version of installs to coexist by using a symbolic link to point to a particular version Changing the symbolic link changes with version will be used Under the main directory there are a number of subdirectories Applets The applets subdirectory contains small application programs that aid in the use of the board For example there is a Finder program that allows the user to flash an LED on the board to determine which board is associated with a target number See the Applets chapter for a fuller description of the applets for a board Documentation This directory contains any documentation files for the project Open the index html file in the directory with a web browser to see the available files and a description of the contents Examples This directory and its subdirectories contain the projects source and example programs for the board Hardware This directory contains files associated with programming the board Logic and any logic images provided X3 2M User s Manual 24 About the X3 XMC Modules In this chapter
82. he X3 10M PMC card is a high bandwidth analog capture module with an advanced architecture that provides ultimate flexibility and speed for the most advanced hardware assisted signal processing and ultrasonic signal capture The X3 10M module streams in analog data and it is possible to log relevant data to host for post data analysis Because the maximum data rate from the X3 10M module is under 160 MB s a logger that saves all of the data to the host disk is feasible when used in conjunction with a suitable RAIDO disk array Snap Example The X3 10M Snap example in the software distribution demonstrates such functionality It consists of a host program which simultaneously works with user defined interface logic It uses the Innovative Malibu software libraries to accomplish the tasks Tools Required In general writing applications for the X3 10M requires the development of host program This requires a development environment a debugger and a set of support libraries from Innovative Table 14 Development Tools for the X3 10M Example Processor Development Environment Innovative Project Directory Toolset Host PC Borland Developers Studio C Malibu Examples Snap Bcb Examples Snap VC8 Microsoft Visual Studio 2005 CH Examples Snap Common Common Host Code The Malibu library is provided with full source code plus pre compiled libraries for MSVC 2003 2007 Borland BCB6 and Borland Developers
83. he system exit the applet by clicking the exit button to resume the installation process 17 Figure 5 BusMaster configuration At the end of the install process the following screen will appear Installation The installation is complete Shut down your computer and install your board s then reboot your computer The drivers should load automatically and your board will become available Please refer to your Hardware Software Manual for instructions on hardware installation priorto powering the machine back on to make certain everything is plugged in correctly Thank you from Innovative Integration 1 805 578 4250 www innovative dsp com Shutdown Now Shutdown Later Figure 6 Installation complete Click the Shutdown Now button to shut down your computer Once the shutdown process is complete unplug the system power cord from the power outlet and proceed to the next section Hardware Installation Hardware Installation Now that the software components of the Development Package have been installed the next step is to configure and install your hardware Detailed instructions on board installation are given in the Hardware Installation chapter following this chapter IMPORTANT Many of our high speed cards especially the PMC and XMC Families require forced air from a fan on the board for cooling Operating the board without proper airflow may lead to improper functioning poor results and even pe
84. heral ID in bits 24 31 The Communications Pkt Size edit control specifies the size of the packets transferred between the target and the Host Each packet transferred results in a Host interrupt handled by the Malibu libraries Consequently larger packets amortize the Host interrupt processing more efficiently However packets are transferred using a contiguous page locked memory region of Host memory known as bus master memory which is allocated during installation via the ReserveMemDsp exe applet Since bus master memory is Host memory it is limited in size by the amount of physical memory installed in the PC By default 32 MBytes are allocated as bus master memory which implies that the Pkt Size must be restricted to fit within this region Since packets main contain data from up to eight channels of sixteen bit data on an X3 10M packets should be sized less than 0x200000 In practice packets at least 0x40000 in size tend to provide good performance while fitting into available bus master memory All X3 modules support generation of data packets containing information signifying detection of exceptional conditions such as A D over range excessive temperature etc The Communications Alert checked list box controls whether the firmware generates notification data packets under such conditions If enabled and a exception is detected the module will transmit a special data packet to the Host containing details of the condition Active C
85. ich allows new logic image to be loaded This method takes name of the image file as an argument which will be read and loaded into the interface logic Logic loading triggers a series of events which are managed by the background thread void ApplicationIo HandleProgress ProcessProgressEvent amp event UI gt UpdateLogicLoadProgress event Percent Process progress events are issued to give a percentage progress of the entire operation These event are handled by HandleProgress This handler calls a UI method UpdateLogicLoadProgress where a Progress bar control is updated to give a visual effect of the loading progress void ApplicationIo HandleLoadComplete ProcessCompletionEvent amp event UI gt Log Load completed ok DisplayLogicVersion Finally the logic loader issues a process completion event when the load is complete This event is handled by HandleLoadComplete as shown above In this case all we do is update the UI so the user can see that the logic X3 2M User s Manual 54 configuration is complete and application status is idle In other cases this could trigger the application to automatically perform additional tasks Starting Data flow After downloading interface logic user can setup clocking and triggering options The stream button then can be used to start streaming and thus data flow void ApplicationlIo StartStreaming if StreamConnected UI gt Log S
86. ing testbed software using FrameWork Logic Table 21 X3 2M Analog Performance Summary Test Group Parameter Measured Units Test Conditions Analog Input Bandwidth 0 5 dB 0 to 5 MHz 3 dB 20 MHz Impedance 50 Ohms nominal Input Range Max 2 01 Vp p Standard on X3 2M calibration results may limit input Min differential range to 97 of full scale nominal 1 99V Accuracy Offset lt 100 uV Factory calibration average of 64K samples Gain lt 0 2 Factory calibration average of 64K samples Analog Input Ground Noise 0 63 mV 1std Input Grounded Fs 10MSPS dev Ground Noise 110 dB Input Grounded Fs 52 ksps 64K sample FFT non averaged Analog Input Crosstalk 85 dB 10 kHz input Fs 10MSPS 2Vp p input cable included all channels Common Mode 100 dB 100 kHz 2Vp p differential Rejection Intermodulation 97 dB 9 kHz and 11 kHz sine 1Vp p each differential Distortion X3 2M User s Manual 93 dB 1000 Figure 5 Frequency Response Analog Input Response Counts 10000 100000 1000000 10000000 Hz iisi ced Sprojas toto San doro anuo HS ett lt BAE APEA AO eege o Mero HEBE CO 07 Sa Me o uix co Q fede c Time Frequency Tet Sunma Seer 271050 11900 Magnitude wg Frequency X ZzomDu Zomin gt gt 70 Amplitude vs Time Sp A xil T ET 4 90 3
87. inimizes jitter on the clocks The clock circuitry allows for a variety of clock sources including two external sources to be used as conversion timebases See the clock discussion for more details The following block diagram shows the general arrangement of the A D The differential inputs from the front panel connector are adjusted for range through a differential amplifier and input to the A D X3 2M User s Manual 4 amp Ext Clk 4 Input _ 2V differential Ext Trigger Figure 15 X3 2M A D Channel Diagram Input Range and Conversion Codes The A D conversion codes for the analog ranges are shown in the following table All voltages are differential meaning that 2V requires two inputs 1 V and 1V to achieve full scale at a gain of 1 The output codes are 2 s complement 16 bit numbers Nominal Conversion Code hex 2V Ox7FFFFF 1V 0x400000 0v 0x000000 Differential Input d 0xA00000 Mc 2V 0x800000 Table 17 A D Conversion Coding X3 2M User s Manual Driving the A D Inputs The X3 2M has fully differential inputs with 50 Ohm input impedance The input range is specified as a differential voltage for the V and V input with a common mode voltage of OV for full range A full scale input is 1 Vp p on EACH of the inputs for a gain of 1 The input signals should be driven differentially to realize the full performance of
88. ively poor real time performance associated with the system Despite the high computational power of the PC it cannot reliably respond to real time events at rates much faster than a few hundred hertz The PC is really best at processing data not collecting it In fact most modern operating systems like Windows are simply not focused on real time performance but rather on ease of use and convenience Word processing and spreadsheets are simply not high performance real time tasks The solution to this problem is to provide specialized hardware assistance responsible solely for real time tasks Much the same as a dedicated video subsystem is required for adequate display performance dedicated hardware for real time data collection and signal processing is needed This is precisely the focus of our baseboards a high performance state of the art dedicated digital signal processor coupled with real time data I O capable of flowing data via a 64 bit PCI bus interface The hardware is really only half the story The other half is the Malibu software tool set which uses state of the art software techniques to bring our baseboards to life in the Windows environment These software tools allow you to create applications for your baseboard that encompass the whole job from high speed data acquisition to the user interface Finding detailed information on Malibu Information on Malibu is available in a variety of forms e Data Sheet http www innov
89. l purpose code authoring environment suitable for development of Windows applications of any type Armada extends the Builder IDE through the addition of functional blocks VCL components specifically tailored to perform real time data streaming functions What is Microsoft MSVC MSVC is a general purpose code authoring environment suitable for development of Windows applications of any type Armada extends the MSVC IDE through the addition of dynamically created MSVC compatible C classes specifically tailored to perform real time data streaming functions X3 2M User s Manual 10 What kinds of applications are possible with Innovative Integration hardware Data acquisition data logging stimulus response and signal processing jobs are easily solved with Innovative Integration baseboards using the Malibu software There are a wide selection of peripheral devices available in the Matador DSP product family for all types of signals from DC to RF frequency applications video or audio processing Additionally multiple Innovative Integration baseboards can be used for a large channel or mixed requirement systems and data acquisition cards from Innovative can be integrated with Innovative s other DSP or data acquisition baseboards for high performance signal processing Why do I need to use Malibu with my Baseboard One of the biggest issues in using the personal computer for data collection control and communications applications is the relat
90. l trigger is an LVTTL input and has the following electrical characteristics Typical Maximum Logic High gt 14V 3 6V Up to 5 5V if a 100 ohm series resistor is used Logic Low lt 0 7V 0 3V Input Impedance gt 1M ohm Table 14 External Trigger Electrical Characteristics Note Triggerl JP1 pin 34 is not used by the standard logic The signal does connect to the FPGA and is used for customer applications Framed Trigger Mode Framed trigger mode is useful for collecting data sets of a fixed size each time the input trigger is fired In framed mode the trigger goes false once the programmed number of points N have been collected Start triggers that occur during a frame trigger are ignored The maximum number of points per frame is 16 777 216 2 24 points while the minimum number of points is 2 Data flow to the host is independent of the framed triggering mode In most cases packet sizes to the host are selected to be integer sub multiples of the frame size to allow the entire data set to flow to the host That way the entire data frame can be moved immediately to the host without waiting for the next trigger frame Decimation The data may be decimated by a programmed ratio to reduce the data rate This mode is usually used when the data rate is less than the minimum sample rate of the A D We recommend using decimation if the data rate falls below 100 ksps that decimation be used because the A D p
91. ld Discard packets from sources other than analog devices if Channel gt Channels return Each PmcBuffer consists of a header and a body of data The header may be interrogated to determine the data source In the fragment above packets containing peripheral IDs greater than the number of enabled channels are discarded Consequently alert packets are not retained or processed Calculate transfer rate in KB s double KBytes Packet Size sizeof int 0x400 double Period Time Differential if Period FBlockRate KBytes Period The code fragment above calculates the nominal block processing rate The AveragedRate object Time maintains a moving averaged filtered rate This rate is stored in FBlockRate for use by display method of the GUI if Settings LoggerEnable amp amp Logger Logged Start counter Clock Start std stringstream msg msg lt lt Packet size lt lt Packet Size lt lt samples UI Log msg str Tf enabled log the data stream if Settings LoggerEnable Settings PlotEnable if FBlockCount BlocksToLog Logger LogWithHeader Packet Count the blocks gone by on each Channel FBlockCount In this example each received packet is logged to a disk file The packet header and the body are written into the file which implies that a post analysis tool such as BinView will be used to parse channelized data from the file Alternately cus
92. le rates to use how to trigger the data acquisition best for your application and just get familiar with using the module The program also shows how to use BinView a data analysis and viewing program by Innovative that will let you see what you acquired in detail Both time domain and frequency domain data can be viewed and analyzed Data can also be exported to programs like Excel and MATLAB for further analysis Before you begin to write software taking a look at SNAP will allow you see everything working You can then look at the code for SNAP and modify it for your application or grab code from it that is useful X3 2M User s Manual 88 Getting Good Analog Performance The X3 2M has a dynamic range exceeding 90 dB To take advantage of this it is important to do the following e Use differential signals to eliminate system noise Single ended signals give typically 10 to 20 dB worse results because of noise pickup e Band limit input signals Even though the A D has filtering and rejects most out of band noise it is a good idea to filter the incoming signal just to get rid of as much noise as possible e Scale your input signals to be 2V full scale Make the signal as big as possible so that the noise is a not as much a factor Custom ranges can be ordered if necessary e Usea high quality shielded cable The MDR68 cable was selected because it has a foil shield and delivers near coax performance e Reference input signals t
93. llation start Windows Shut down all running programs and disable anti virus software Insert the installation DVD If Autostart is enabled on your system the install program will launch If the DVD does not Autostart click on Start Run Enter the path to the Setup bat program located at the root of your DVD ROM drive 1 e E Setup bat and click OK to launch the setup program SETUP BAT detects if the OS is 64 bit or 32 bit and runs the appropriate installation for each environment It is important that this script be run to launch an install When installing on a Vista OS the dialog below may pop up In each case select Install this driver software anyway to continue Don t install this driver software You should check your manufacturer s website for updated driver software for your device Install this driver software anyway Only install driver software obtained from your manufacturer s website or disc Unsigned software from other sources may harm your computer or steal information v See details Figure 1 Vista Verification Dialog X3 2M User s Manual 14 The Installer Program After launching Setup you will be presented with the following screen Please select a product to install Installatton Path Je Innovative Change Components to Install for Quadia Quadia Applets examples Docs and Pismo libraries Malibu Host libraries utilites Docs drivers amp DLLs Bin View Data graphin
94. menting class forwards the call to the UI form class to perform the action ApplicationIo only has to know how to deal with a pointer to a class that implements the interface and all UI dependencies are hidden X3 2M User s Manual 49 The predefined IUserInterface interface class is defined in ApplicationIo h The constructor of ApplicationIo requires a pointer to the interface which is saved and used to perform the actual updates to the UI inside of Applicationlo s methods Applicationlo Initialization The main form creates an ApplicationIo object in its constructor The object creates a number of Malibu objects at once as can be seen from this detail from the header Applicationlo h Member Data Innovative X3 10M IUserInterface Innovative PacketStream IntArray unsigned int ii64 bool bool bool Innovative StopWatch Innovative DataLogger IntArray Innovative BinView Innovative Scripter float std string Innovative AveragedRat double std string Innovative SoftwareTimer int float int int int int int int Module UL Stream Rx Cursor BlocksToLog Opened Stopped StreamConnected Clock Logger DataRead Graph Script ActualSampleRate Root Time FBlockRate FVersion Timer FHwBusWidth FHwPciClk FBlockCount FDevices FChannels FTicks FTriggered FRanges In Malibu objects are defined to represent units of hardware as well as softwar
95. monitoring and power controls to aid in system integration Also the module has been designed to include conduction cooling to improve heat dissipation from the module These features can make the module more reliable in operation and also reduce power consumption X3 2M User s Manual 84 System Thermal Design The X3 2M dissipates about 6 5W Watts typically for all A D channels running at full rate In an office or lab environment the module can run without forced air cooling Operating temperature is about 48C for a typical 24C office environment Environmental Rating Cooling Method Temperature Range Typical Use LO Forced Air SCFM 0 to 70C Laboratory indoor installations Ll Forced Air SCFM 40 to 85C Outdoor installations L2 Conduction Cooled 20 to 65C Conduction cooled applications outdoor installations L3 Conduction Cooled 40 to 85C Conduction cooled applications outdoor installations L4 Conduction Cooled 40 to 85C Conduction cooled applications outdoor installations Table 15 X3 Environmental Ratings for Temperature Note Ratings L2 L4 are also rated for vibration shock and humidity Consult Innovative for details Conduction cooling is supported for the module and provides an effective method in many applications A thermal plane in the card is attached to the center stripe on the card The card can then be cooled by mounting the card on host card that supports conduction cooling The
96. n its depth and its range of performance and I O capabilities Whether you are seeking a simple DSP development platform or a complex multiprocessor multichannel data acquisition system Innovative Integration has the solution To enhance your productivity our hardware products are supported by comprehensive software libraries and device drivers providing optimal performance and maximum portability Innovative Integration s products employ the latest digital signal processor technology thereby providing you the competitive edge so critical in today s global markets Using our powerful data acquisition and DSP products allows you to incorporate leading edge technology into your system without the risk normally associated with advanced product development Your efforts are channeled into the area you know best your application Vocabulary X3 2M User s Manual What is X3 2M The X3 module family are XMC VITA 42 3 modules with a variety of IO capabilities and a PCI Express interface Each modules has a Spartan 3 3A DSP application FPGA buffer memory and clocking features to support the IO functions Two SRAMs are used one each for buffer memory and application memory Then XMC has a PCIe interface to the host computer The X3 2M is an XMC IO module featuring 12t simultaneously sampling 16 bit 10 MSPS A D channels designed for high speed instrumentation and analysis for neuro physical high speed motion analysis and high speed data a
97. nector JP1 or XMC secondary connector P16 To use the P16 connector inputs the carrier card must support the P16 pinout shown later in this chapter Here is where the external clock inputs are connected External Clock ext clk JP1 MDR6S front panel connector PXI DSTARA P16 a9 Pn XMC secondary connector PXIE 100M P16 D9 E9 XMC secondary connector Table 2 External Clock and Reference Signal Pinouts PLL Output Range and Resolution Limitations The sample rates that can be generated are limited by the VCXO tuning range the PLL reference frequency and the PLL tuning parameter limits For the standard VCXO and PLL circuitry the sample clocks tuning resolution is st to 100 kHz Considering the divider that follows the VCXO the output resolution is shown in this table for several dividers For VCXO tuning range of 10 to 280 MHz and integer output divisors D 1 to 32 the allowable output ranges are shown Output Divisor D Lower Limit MHz Upper Limit MHz Resolution MHz 10 0000 280 000 0 100000 5 0000 140 000 0 050000 1 2500 35 000 0 012500 16 0 6250 17 500 0 006250 32 0 3125 8 750 0 003125 Table 3 Sample Clock Output Ranges and Resolution Programming the PLL and VCXO The VCXO used on the X3 2M is programmable to set the center frequency The frequency is set so that PLL runs at the maximum rate possible an even multiple of the A D clock rate So if the A D needs a 10 MHz clock the VCXO will be set to 10 MHz
98. ngs The software tools provide hooks for direct programming of the PLL divisors to override the automatic functions in Malibu During experimentation the PLL registers can also be written using Peek Poke functions or scripts These functions are supported on the Debug tab in the example applications SNAP and WAVE Consult the AD9510 register map for details on register formats PLL Lock and Status The PLL has a status pin that can be programmed to show when the PLL is locked or other status information The software in the SNAP example configures this pin to be digital lock detect It indicates when the PLL is locked and ready for use If the PLL lock is false the PLL is not working properly and may give poor results or inaccurate frequencies Even when the PLL is unable to lock it will produce an output so the mere presence of data does not indicate that the PLL is operating at the correct frequency or is stable The PLL lock can also generate an alert to the system if an unlock condition occurs In this mode when the PLL falls out of lock as indicated by a falling edge on the PLL status pin an alert message is created showing the time of the unlock and other system information See the Alert Log section for further information on using Alerts PLL lock is only valid for phase comparisons 25 MHz It is unreliable above this frequency X3 2M User s Manual 77 PLL Control Interface There are two AD9510 devices is mapped into the PCI
99. not only the files that are to be installed but also installation scripts and dependency information to allow a smooth fit into the system This information allows the package to be removed or patched Innovative uses RPM packages in its installs Package File Names A package file name such as Malibu LinuxPeriphLib 1 1 3 1586 rpm encodes a lot of information Malibu Linux PeriphLib 1 1 3 1586 rpm Prerequisites for Installation In order to properly use the baseboard example programs and to develop software using the baseboard some packages need to be installed before the actual baseboard package The Redistribution Package Group MalibuRed This set of packages contain the libraries and drivers needed to run a program using Malibu This group is called MalibuRed because it contains the packages needed to allow running Malibu based programs on a target non development machine Red is short for redistributable WinDriver 9 2 1 1586 rpm Installs WinDriver 9 2 release MalibuLinux Red ver rel i586 rpm Installs Baseboard Driver Kernel Plugin intel ipp_rti 5 3p x32 rpm Installs Intel IPP library redistributable files X3 2M User s Manual 21 The installation CD or the web site contains a file called LinuxNotes pdf giving instructions on how to load these packages and how to install the drivers onto your Linux machine This file is also loaded onto the target machine by the the Malibu LinuxRed RPM
100. ntation X3 2M User s Manual 103 Table 24 X3 2M XMC Secondary Connector P16 Pinout Column Row A B C D E F 1 i DIOO0 PXI TRIGO E DIO19 2 DGND DGND DIO1 PXI TRIGI DGND DGND DIO20 3 z DIO2 PXI TRIG2 o DIO21 4 DGND DGND DIO3 PXI TRIG3 DGND DGND DIO22 5 DIO4 PXI_TRIG4 DIO23 6 DGND DGND DIOS PXI_TRIG5 DGND DGND DIO24 7 z DIO6 PXI TRIG6 f DIO25 8 DGND DGND DIO7 PXI TRIG7 DGND DGND DIO26 9 DIO38 DIO39 DIO8 PXI STAR DIO40 DIO41 DIO27 PXI DSTARA PXI DSTARA PXIE_100M PXIE_100M 10 DGND DGND DIO9 DGND DGND DIO28 PXIE_SYNC100 11 B DIO10 DIO29 PXIE_SYNC100 12 DGND DGND DIO11 DGND DGND DIO30 13 e DIO12 o DIO31 14 DGND DGND DIO13 DGND DGND DIO32 15 E 2 DIO14 DIO33 16 DGND DGND DIO15 DGND DGND DIO34 17 5 DIO16 DIO35 PXI 10M 18 DGND DGND DIO17 DGND DGND DIO36 PXI LBL6 19 DIO42 DIO43 DIO18 DIO_CLK DIO CLK PXI DIO37 PXIE DSTARB PXIE DSTARB PXI DSTARC DSTARC PXI LBR_6 Note all unused pins are not labeled X3 2M User s Manual 104 Table 25 P16 Signal Descriptions Signal Description P16 Pin DIO0 PXI TRIGO Digital IO 0 PXIE trigger 0 Cl DIO PXI TRIGI Digital IO 1 PXIE trigger 1 C2 DIO2 PXI TRIG2 Digital IO 2 PXIE trigger
101. o 100 kHz This Fphase_detector 100kHz matches the PLL configuration on the card 2 Calculate a reference divisor so that the phase detector Fphase detector Fref R 100kHz frequency is close to 100kHz R 1 to 16383 100 kHz lt Fref lt 250 MHz R 1000 for on board reference 3 For an output sample clock Fout find the output FVCXO Fout D divisor D that keeps the VCXO within its tuning range D 1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 or 32 100 MHz lt FVCXO lt 140 MHz 4 Find PLL feedback divisor M int FVCXO Fphase_detector 1 M 262144 5 Find operating mode fixed modulus or dual modulus A FVCXO mod Fphase detector and value of A If A 0 then mode should be fixed divide if A gt 0 then dual modulus mode is used X3 2M User s Manual 76 6 Select value of prescaler P based on operating mode Pick P and B such that M P B using smallest values and divisor ratio M possible For fixed divide P 1 2 or 3 For dual modulus P 2 4 8 16 or 32 B 3 to 8191 integers 1 bypass 7 Check calculations Fout FVCXO D FVCXO PB A Fref R 100 MHz lt FVCXO lt 140 MHz Table 4 Selecting values for PLL Divisors Fs MHz D FVCO Fref MHz R M A P B 31 100 4 124 4 100 1000 311 0 1 311 11 000 10 110 100 1000 110 0 1 110 5 100 20 102 100 1000 51 0 1 51 3 300 32 1056 100 1000 33 0 1 33 3 200 32 102 4 100 1000 32 0 1 32 Table 5 PLL Example Setti
102. o the module ground Be sure not to introduce ground loops If you decide to test the X3 2M to verify its performance be aware that most signal sources are not good enough without additional filtering and careful use Most single ended lab instruments are limited by their distortion to about 90 dB Post filter is necessary to clean them up if you want to test the X3 2M Application Logic The application logic must be loaded after every system boot up or reset There is no on card storage for the logic image The logic can be loaded using the LogicLoad software applet or 1s loaded as part of the application itself such as SNAP If you write your own application you will need to either use LogicLoad or incorporate a logic loader in the application The code in SNAP is a good example of how to do this Calibration Every A D sample is error corrected on the X3 2M module in real time by the application FPGA This error correction is done as the samples flow through the FPGA and is done digitally This results in improved performance and reliability for the module because the error correction does not change over time or temperature The basic error terms for offset and scale factor are corrected by the logic This is a first order error correction where y mx b wherein x the input sample m gain correction and b offset correction The resultant samples are the error corrected output samples Trim range is about 1 5 for gain and 10 for
103. ock Diagram The X3 module architecture is really defined by the features in the logic that connect the IO devices to the Velocia packet system For data from IO devices such as A Ds the data flows from the IO interface and is then enqueued in the multi queue buffer The packetizer then creates data packets from the data stream that are moved across the data link to the PCIe interface Packets to output devices travel in the opposite direction from the link to the deframer and into the multi queue data buffer The output IO such as a DAC then consumes the data from the queue as required The Alert Log monitors error conditions and important events for management of the data acquisition process The host interacts with the X3 computing core using the packet system for high speed data and over the command channel The packet system is the main data channel to the card and delivers the high performance real time data capability of moving data to and from the module Since it uses an efficient DMA system it is very efficient at moving data which leaves the host system unburdened by the data flow The command channel provides the PCIe host direct access to the computing core logic for status control and initialization Since it is outside the packet system it is less complex to use and provides unimpeded access to the logic The application FPGA image is loaded by the host computer as part of the module initialization The image is loaded over the Sel
104. ock factory supplied logic bit zero of the Test Register user logic offset 0x02 1s controlled by Test Counter Enable which forces an incremental ramp to replace A D data from each channel Decimation Group These controls govern the behavior enable the decimation logic When enabled only one of every Nth sample of acquired data is retained within the internal on board FIFOs and sent to the Host PC via bus mastering X3 2M User s Manual 47 Data Streaming Configure Setup Zbt Ram EEProm Debug Select the Stream tab The controls on this tab pil control data flow The meaning of each of the Start Scripts fields on this tab are explained below C innovative X3 10M E xamples Snap Bcb1 0 TestScript tt peines lr BEEN C Mnnovative X3 10M E xamples Snap Bcb10 T estScript txt Aft x Data collection is initiated when the VCR Start eme id hl Selfien d M button is pressed and terminates when the VCR Data Files Stop button is pressed or when the amount of data 19 M Pet Iv Overwnte Bdd specified in the Data Logging configuration controls is accumulated To accommodate custom logic development the application supports execution of simple user Soch Count Rate KB s Temp C Dig In authored scripts before and after the commencement of data flow The Start Scripts Before edit box specifies the full path spec to a text file containing valid script commands described below which will be executed prior to da
105. ollection process The trigger is synchronized to the sample clock rate Fs Trigger Analog Input Samples are acquired for each sample period when trigger is true Figure 2 Analog Triggering Timing As shown in the diagram samples are captured when the sample period and the trigger are true The trigger is true in continuous mode after a rising edge on the trigger input software or external until a falling edge is found The trigger is timed against the sample clock and may have a 0 to 1 A D sample uncertainty for an asynchronous trigger input The trigger control on the X3 2M module always ensures that a complete set of A D samples for the time period are acquired no matter when the trigger is deasserted This means that for an unsynchronized trigger input such as an external device you will always get samples for all enabled channels no matter when trigger is enabled or disabled Trigger Source A software trigger or external trigger can be used by the trigger controls Software trigger can always be used but external triggering must be selected This prevents spurious triggers from noise on external inputs The trigger source is level sensitive for the continuous mode or edge triggered for the framed mode triggering X3 2M User s Manual 81 External Trigger JP1 Pin Number TRIGGER 68 Table 13 External Trigger Input Externa
106. ommand channel itself Again custom logic implementations can achieve much higher data rates The X3 FrameWork Logic user Guide details logic supporting the digital IO port and gives the pin information for customization Serial EEPROM Interface X3 modules have a serial EEPROM for storing data such as board identification calibration coefficients and other data that needs to be stored permanently on the card This memory is 16K bits in size Functions for using the Serial EEPROM are included in the Malibu Toolset and example programs that allow the software application programmer to easily write and read from the memory without having to program the low level interface Use the baseboard IdRom method to obtain a reference to the internally managed IusesPmcEeprom object as shown below Open the module Innovative X3 SD Module Module Target 0 Module Open Create a 50 32 bit word section at offset zero in ROM user space PmcIdromSection Sectionl Module IdRom Rom PmcIdrom waUser 0 50 Create a 50 32 bit word section at offset 50 in ROM user space PmcIdromSection Section2 Module IdRom Rom PmcIdrom waUser 50 50 Write to ROM for int i 0 i lt 50 i Sectionl AsInt i i 2 Sectionl StoreToRom for int i 50 i lt 100 i Section2 AsFloat i static cast float i 2 Section2 StoreToRom Read from ROM Sectionl LoadFromRom for int i 0 i lt 50 i int x
107. on the X3 2M will flash when the module is too hot gt 85C The module must be completely powered down to restart once a failure occurs X3 2M User s Manual 85 Reducing Power Consumption The X3 2M has power controls that allow the application software to power down unused channels and run in reduced power mode for the A Ds If you incorporate these into your application you may be able to avoid problems later in hot installations Feature Power Saved Comments Analog Disabled 3 5W All A D powered down Allow warm up time of 1 minute for best performance PLL power down 0 3W PLL off must use external clock Application FPGA not configured 1 5W Must reload the FPGA to resume operation 33 MHz system clock 0 5 33 MHz FPGA system clock Data rate to host is limited to lt 100 MB s typically Requires FPGA modifications and installation of R428 Table 16 Reduced Power Options Alert Log Overview X3 modules have an Alert Log that can be used to monitor the data acquisition process and other significant events Using alerts the application can create a time history of the data acquisition process that shows when important events occurred and mark the data stream to correlate system events to the data This provides a precision timed log of all of the important events that occurred during the acquisition and playback for interpretation and correlation to other system level events Alerts for critical sy
108. orithms may be developed for use in the X3 2M logic and integrated with the hardware using the FrameWork Logic Software support for the module includes host integration support including device drivers XMC control and data flow and support applets X3 2M User s Manual 67 X3 2M Block Diagram OOOO Front Panel DIO 11 0 p Triggers 1 0 Figure 14 X3 2M Block Diagram Hardware Features A D Converters The X3 2M has 12 channels of 16 bit A D sampling at up to 10 MSPS using Analog Devices AD7626 A Ds The AD7626 is delivers a dynamic range in excess of 90 dB with excellent linearity and low power The AD7626 also has a low latency SAR conversion resulting in no pipeline delay X3 2M User s Manual 68 Feature Description Inputs 12 independent Input Range 1V to 1V differential Input Common Mode Range 2 to 2V DC Input Impedance 50 ohms A D Devices Analog Devices AD7626 Output Format 2 s complement 16 bit Number of A D Devices 12 simultaneously sampling Sample Rate 0 1 10 MSPS Lower rates use FPGA decimation See discussion Clock Rate 0 3125 to 10 MHz using on card PLL 0 1 to 10 MHz using external clock input Calibration Factory calibrated Gain and offset errors are digitally corrected in the A D Non volatile EEPROM coefficient memory Table 16 X3 2M A D Features Conversion clocking is provided through separate special circuitry that m
109. ply an external reference The PLL will generate an output synchronous to the external reference The sample clock for the front panel DIO is direct from the clock distribution circuitry and is NOT derived from the application logic clocks or PCI Express bus clock This is because these clocks have more jitter phase noise Note Conversion clocking is separate from triggering sample clock is the time when samples are digitized but trigger determines when those samples are kept External Clock and Reference Inputs The X3 2M has two external inputs that that may be used as sample clock plus two external inputs that may be used as the PLL reference clock The two external input clocks Ext Clk and PXI_DSTARA can be directly used as the sample clock The 100 MHz clock oscillator and PXI 100M clock can be used as references to the PLL The following table shows the clock multiplexer controls for the X3 modules Control Signal Device Function Result PLL REF SEL PLL Reference Mux Selects either PXI 100M or 100MHz fixed 0 100 MHz oscillator as the PLL reference 1 2 PXI 100M X3 2M User s Manual 73 Control Signal Device Function Result PLL CLKA SEL External Clock Mux Selects either Ext_Clk or PXI DSTARA as 0 Ext Clk input to the clock distribution 1 PXI DSTARA Table 1 X3 External and Reference Clock Selection To use an external clock the external clock multiplexer must be configured
110. r timer input pins should be limited to a voltage range between 0 and 3 3V referenced to ground on the digital I O port connector Exceeding these limits will cause damage to the X3 module Front Panel DIO Some modules in the X3 family notably the A4D4 25M Servo SD16 and 2M provide additional banks of digital I O accessible via the front panel MDR68 connector The number of available bits is shown in the table below These bits are direction programmable in banks of eight bits The FrontPanelPortConfig property is used to program the bank directions This low order two bits in the parameter sent to this method corresponds to up to two bytes of direction control where bit 0 corresponds to front panel DIO bits 0 7 bit 1 corresponds to front panel DIO bits 8 15 Subsequently use of the FrontPanelPortData property allows accessing the state of all bits Using the setter property updates all bits configured for output whereas using the getter property fetches the current state of all bits regardless of configuration X3 2M User s Manual 33 Table 7 Table 1 Front Panel DIO on X3 Modules This digital I O hardware is controlled by the UsesFrontPanelPort class Its properties Table 8 IUsesExtendedDioPort Class Operations FrontPanelPortConfig Configures banks of bits for input or output FrontPanelPortData Broadside Read Write to low order 32 bits of DIO Typical use of the digital IO port involves first configuring the port
111. red until the channels are triggered Triggering may be initiated by a software command or via an external input signal to the Trigger connector pin The code fragment above selects the trigger mode enum IUsesX3Alerts AlertType Alert IUsesX3Alerts alertTimeStampRollover IUsesX3Alerts alertSoftware IUsesX3Alerts alertWarningTemperature IUsesX3Alerts alertPllLost IUsesX3Alerts alertInputFifoOverrun X3 2M User s Manual 57 IUsesX3Alerts alertInputTrigger IUsesX3Alerts alertInputOverrange for unsigned int i 0 i lt Settings AlertEnable size i Module Alerts AlertEnable Alert i Settings AlertEnable i true false The fragment above enables alert generation by the module The GUI control includes check boxes for each of the types of alerts of which the module is capable The enabled state of the check boxes is copied into the Settings AlertEnable array This code fragment applies the state of each bit in that array to the Alerts sub object within the module During streaming an alert message will be sent to the Host tagged with a special alert packet ID PID to signify the alert condition Start Streaming Stream Start UI gt Log Stream Mode started UI gt Status Stream Mode started The Stream Start command applies all of the above configuration settings to the module then enables PCI data flow However samples will not be acquired until the module is triggered ActualS
112. rmanent physical damage to the board These boards also have temperature monitoring features to check the operating temperature The board may also be designed to intentionally fail on over temperature to avoid permanent damage See the specific hardware information for airflow requirements X3 2M User s Manual 18 After Power up After completing the installation boot your system into Windows Innovative Integration boards are plug and play compliant allowing Windows to detect them and auto configure at start up Under rare circumstances Windows will fail to auto install the device drivers for the JTAG and baseboards If this happens please refer to the TroubleShooting section Installation on a Deployed System The above instructions install the complete development platform onto a system for the development of application software Often however a developed application needs to be installed on a system that will only be used to run the program In this instance installing the complete library is overkill To support this situation Innovative has a minimal installation program called MalibuRED This is short for Malibu Redistributable This install will install the driver software and support DLLs required to run a Malibu application Note Specific applications may have their own additional requirements that are not covered by MalibuRED For example NET applications require the NET libraries to be installed a
113. rol to the right of this button is supplied as the code for the alert which is returned and displayed in the log if software alerts are enabled for display Host Side Program Organization The Malibu library is designed to be rebuilt using various compiler toolsets from Borland Microsoft and GCC Because the library has a common interface in all environments the code that interacts with Malibu is separated out into a class Applicationlo in the files ApplicationIo cpp h This class acts identically under each platform The Main form of the application creates an ApplicationIo to perform the work of the example The UI can call the methods of the Applicationlo to perform the work when for example a button is pressed or a control changed Sometimes however the ApplicationIo object needs to call back into the UI But since the code here is common it can t use a pointer to the main window or form as this would require that the class know details of particular compiler environment in use The standard solution to decouple the ApplicationIo from the form is to use an Interface class to hide the implementation An interface class is an abstract class that defines a set of methods that can be called by a client class here Applicationlo The other class produces an implementation of the Interface by either multiple inheriting from the interface or by creating a separate helper class object that derives from the interface In either case the imple
114. rom PCI Express to Application Logte eene nnne nnne 30 Table 6 IUsesExtendedDioPort Class Operations esses eene n nnn enne 32 Table 7 Table 1 Front Panel DIO on X3 Modules nennen nennen nnne nnne 34 Table 8 IUsesExtendedDioPort Class Operations sessi enint n nennen 34 Table 9 Digital VO Port Timing Parametros dais 35 Table 10 Digital IO Bits Electrical OCharactertsttcs ener nnne n nennen nennen 36 Table 11 Digital IO Clock Input Electrical Charactertsttcs nennen nnne nenne 37 Table 12 Temperature Alarmas ene EERSTEN EES eR 39 Table 13 X3 Modules FPGA JTAG Scan Path 41 Table 14 Development Tools for the X3 10M Example sss nne nnne 44 Table 15 Analog Gain Ranges eene nn nenne ntn nne nest NESES ESE ESen Eses Eesen nennen 47 ELO ER D EE 69 Table 17 A D Conversion Codmg tn testet Estes ESSES EASES NESES ESEESE Senses ESSES reestas stees teena ea 70 Table TX 32M A D Sample R ates 5 ege AR ERR E eel adie eigenen 72 Table 18 Sample Clock Modes nanninannan eaa a aaa EE a A E aen 72 Table 1 X3 External and Reference Clock Selection sse enne enne 74 Table 1 X3 External Clock and Reference Input Requirements esses enne nennen 75 Table 2 External Clock and Reference Signal Pnouts nennen nnne 75 Table 3 Sample Clock Output Ranges and Resolution seen enne 75 Table Selectng values for PEL DIVISOIS eet e Eege T Table PLL EE EE T
115. s AERE QU SAYS 71 Overrange Detectioti kesri acepte ettet cheese tat tert ettet br etse atte RE eret 71 AUD Sampling Rates oon ten qucd ate ee e in de ertet 71 Sample Rate Generation and Clocking Controls esses eene ener ennt enne nnne nnn 72 External Clock and Reference Inputs tret tet ERR UEENE IP GE B Pe SUPR OTT 73 PLL Output Range and Resolution Limitations esses enne nennen nennen nnne enne nnne nennen 75 Programming the PLL and V XQ esent iE RT SUN E ERE RR RUF EET EE di 75 PLE et BEE 77 PEL Control Intl a A 78 Notes About the PEL Conti guration and 79 Timing AO RR HE E DI e EU E REI AT ID and 80 a a M 80 TA A asi 81 Framed A Mode rtc o ita 82 pena 82 48 channiel System Ex mple eege ee 83 FrameWork Logic Functionality eie EG NUR ias 83 Power Controls and Thermal Desen get eser eee e ERR E ECHTE ER GERE EY eee EEN 84 System Thermal Deeg inier RH M aia 85 Temperature Sensor and Over Temperature Protection esses enne nnne nennen nnne 85 Reducing Power Consumption sis ariete Aisen 86 LAETI 86 ical D ENEE EERSTEN ed EE 86 Types Of EE 86 Alert Packet Eormat 0 2 cta dd a e Mee cere e opa e Ros 87 Software Supporters nescia e ei elato deii setae qi sadi iari oe RU Es 88 Tagging the Dat
116. s attached to actual physical device the streaming controller associates with a baseboard by the ConnectTo method Once connected the object is able to call into the baseboard for board specific operations during data streaming If an objects supports a stream type this call will be implemented Unsupported stream types will not compile Applicationlo Close Close Hardware amp set up callbacks void ApplicationIo Close Stream Disconnect StreamConnected false Opened false UI gt Status Stream Disconnected Similarly the Close method closes the hardware Inside this method first we logically detach the streaming subsystem from its associated baseboard using Disconnect method Malibu method C1ose is then used to detach the module from the hardware and release its resources Logic Loading The user interface logic for the module must be loaded at least once per session it remains valid until power is removed from the board In the following code we show how to browse and configure the desired logic In the UI when the logic browse button is pressed LogicLoadBrowseBtnClick method gets called as shown below void _ fastcall TMainForm LogicLoadBrowseBtnClick TObject Sender std auto_ptr lt TOpenDialog gt Dialog new TOpenDialog NULL Dialog gt Filter Logic File exo exo All Files Dialog gt Title Select FPGA Logic File if LogicFilenameEdit gt Text Length
117. s well Installation programs for NET can be obtained from Microsoft over the Internet Running MalibuRed MalibuRED can be found on the installation CD in the Windows 32 Malibu subdirectory The name of the installation file is MalibuRED exe Running the program displays the setup screen for the installer Select your baseboard i II NM Using the combo box select the appropriate baseboard to install support for In this case we are installing an X3 A4D4 board If support for multiple cards is needed the program must be run to completion once for each type of board This is required because parts of the installation such as baseboard device drivers may be different for different board types After selecting the board press Go to begin installation The window changes to display the progress of the install X3 2M User s Manual 19 rte Thank you for choosing X3 A4D4 Installing Malibu Redistributable Libraries After completing the installation reboot the system to allow Windows to recognize the new drivers Then proceed with the Hardware Installation as in the development system installation above X3 2M User s Manual 20 Installation on Linux This chapter contains instruction on the installation of the baseboard software for Linux operating systems Software installation on Linux is performed by loading a number of packages A Package is a special kind of archive file that contains
118. sseseeseeececesececsecsessecseesessessesseeaesesaesasecesecseesessesseesesseeaeeaeeaeesaeesaeesseeeseeed 81 Figure 3 Example 64 channel System Architecture eese enne nennen netten enne nnne 83 Figure 4 X3 2M FrameWork Logic Data How 84 Figure ANSIA 94 Figure 6 Noise Floor Spectrum Fs 10MSPS esses ne sienne nenne eren eterne reser enn 94 Figure 7 Noise Floor ES TOMSDS at eer RE e ERR e ONT CU A NR EE EC Eee es 94 Figure 8 Signal Quality 101 kHz 1 9Vp p input 10 MSPS decimation 10 eene 95 Figure 9 Signal Quality 101 kHz 1 9Vp p input 10 MSPS decimation 10 seen 96 Figure 10 Intermodulation Distortion 9 9 kHz and 11 kHz dual tone Fs 10 MS 97 Figure Ll P15 XMC Connectot Orientation ed eei EE pee te fe e Ree ERO Rotes EE 100 Figure 12 P16 XMC Connectot Orientation iet Eeer 103 Figure 13 X3 2M J3 Orientation ioa ete PD EO UD EUER e ride rd eo ee 107 Figure 14 X3 2M J3 Side DE 107 Figure 15 X3 2M Mechanicals Top View Rev B enne nnne nennen nnne neret enne enne 108 Figure 16 X3 2M Mechanicals Bottom View Rev Bi 109 X3 2M User s Manual Introduction Real Time Solutions Thank you for choosing Innovative Integration we appreciate your business Since 1988 Innovative Integration has grown to become one of the world s leading suppliers of DSP and data acquisition solutions Innovative offers a product portfolio unrivaled i
119. stem events such as triggering data overruns analog overranges and thermal warnings provide the host system with information to manage the module The Alert Log creates an alert packet whenever an enabled alert is active The packet includes information on the alert when it occurred in system time and other status information The system time is kept in the logic using a 32 bit counter running at the sample clock rate Each alert packet is transmitted in the packet stream to the host marked with a Peripheral Device Number corresponding to the Alert Log The Alter Log allows X3 modules to provide the host system with time critical information about the data acquisition to allow better system performance System events such as over ranges can be acted on in real time to improve the data acquisition quality Monitoring functions can be created in custom logic that triggers only when the digitized data shows that something interesting happened Alerts make this type of application easier for the host to implement since they don t require host activity until the event occurs Types of Alerts Alerts can be broadly categorized into system IO and software alerts System alerts include monitoring functions such as temperature time stamp rollover and PLL lost These alerts just help keep the system working properly The temperature warning should be used increase temperature monitor and to prepare to shut down if necessary because thermal overload ma
120. stic All board specific I O is performed within the ApplicationlIo cpp h unit Data is transferred from the module to the Host as packets of PmcBuffers The Host Application The image below shows the main window of X3 10M example This form is from the designer of the Borland C Builder version of the example but other implementations are similar User Interface This application has six tabs Each tab has its own significance and usage and several are inter related Below this tabbed control is a common area containing a memo control which is used to display messages and feedback throughout the operation of the program Logic Tab X3 Snap Example DER As soon as the application is launched the PCI bus is queried to Vos Setup Stream 20 Ram EEProm Debug determine the number of installed X3 modules This tally is Target used to populate the Target combo box in the Driver group 5 Malibu uses a common device driver for all X3 class modules Ero Logi Fie E NnnovativevX3 SDFNHardwareNmagesVX3 SDF routed v3 exo Multiple modules in a system are differentiated by an integer target number which uniquely corresponds to each particular board in a system The target number assigned to a module is dependent on the physical slot into which the module is installed so relocation of a module will change its target ID in a multi board system But target numbers are stable and reliable unless boards are relocated within a P
121. system Table 18 Sample Clock Modes The PLL can generate many sample rates that suit most applications The advantage of using the PLL is that the sample clock is very clean and low jitter The output frequency of the PLL is programmable and is determined by the reference clock rate and the VCXO tuning range Software functions for PLL configuration monitoring and clock distribution are provided in Innovative s Malibu software toolkit that configure the operating mode and sample rate required for the desired sample data rate The X3 2M uses one AD9510 devices for its PLL divider and clock distribution functions with a programmable VCXO This provides a clock generation range from 312 5 kHz to 280 MHz The useful range for the A Ds is limited to 0 1 to 10 MHz X3 2M User s Manual 72 PLL_REF_SEL 100MHz P16 RIO Ext Clock Input P1 PXI DSTARA P16 VCXO 12C Port FPGA vreco PLL_CLKA_SEL AD 0 LVCMOS AD 1 LVCMOS DAC 0 LVCMOS DAC 1 LVCMOS FPGA FPGA FPGA Figure 1 X3 2M Clock Generation and Controls Block Diagram The PLL reference is either a fixed 100 MHz reference clock or an external reference clock The output of the PLL is synchronous to the reference clock and the reference clock input or integer division of the reference determines the tuning resolution of the PLL To achieve an exact frequency that is not a division of the reference clock it is necessary to sup
122. ta flow Similarly the Start Scripts After edit box specifies the file containing commands to be executed after data flow is underway The following script commands are supported 1 na Store n to logic register address a la a n Fetch n from logic register address a p na Storen to port register address a pa a n Fetch n from oort register address a ms n Delay n milliseconds All commands use postfix notation so parameters preceed the command For instance 0x01 0x02 1 causes the value 0x01 to be stored to logic address 0x02 The Stream Data Files Log check box controls whether received packets are logged in real time If checked data will be accumulated until the limit specified in the Data Logging Samples edit box is reached The Stream Data Files Plot check box controls whether the BinView file viewer applet is invoked when streaming terminates to allow perusal of the acquired data stored in the disk file The Stream Data Files Overwrite BDD check box controls whether a new BinView binary data descriptor file should be created as streaming terminates Normally this should be enabled so that a valid BDD is available for use by BinView when it is opened to view acquired data But under some circumstances such as when comments are added to the BDD file it may be desirable to avoid re creating the file each run During data flow the number of received data packets data transfer rate
123. tate This mode is ideal for conventional data acquisition applications In Framed mode triggers are rising edge sensitive Upon detection of each edge Trigger Frame Count samples are acquired from all active channels then acquisition terminates until the next trigger edge is detected If Trigger Frame Auto Retrig is checked and the Trigger Source is software the application automatically re triggers upon completion of processing of the previous packet This mode is ideal for application such as spectral analysis using fixed input buffers submitted to FFTs Digital I O Group These controls govern the configuration of the DIO port on the module The DIO port can be configured for input or output on a byte wise basis as a function of the configuration code in Digital I O Config Mask See the DIO Control Register description user logic offset 0x14 for details Data Logging Group These controls govern the size of data files created by the application containing packet data received from the module during real time streaming The value of Data Logging Samples sets the upper bound on the number of stored events samples from each channel If the Data Logging Auto Stop checkbox is checked streaming will automatically terminate once the specified number of events has been collected and logged to disk Test Counter Group Use this control to enable a logic specific test mode if you are developing custom FPGA logic If you are using the st
124. the range of 10 to 280 MHz that may be subsequently divided in the outputs The dividers in the clock distribution section of the AD9510can be used to further divide the clock by 1 to 32 with the restriction only even numbers are used to make the clock a 5096 duty cycle X3 2M User s Manual 79 The external clock and optional fixed oscillator are connected to the CLK1 input The PLL must be programmed to use one of these two clock sources for the outputs The clock dividers on the outputs should be programmed to the same divisor to work with the standard logic The AD9510 is programmed during initialization of the card All configuration registers are written then an update command is sent to the PLL that makes the outputs update simultaneously After an update the clock is stable when the PLL status bit indicates a lock Timing Analysis There are several timing parameters associated with the clock control circuitry that affect the measurement process The following table summarizes two important effects Timing propagation delay through the logic for external clocks are shown for the maximum and typical timing The external clocks go through one or two multiplexers accounting for the differences in propagation delay to the various devices Jitter is summed as the root sum of squares for random jitter Clock Source Clock Destination Propagation Delay ns Additive Jitter ps RMS External clock or A D and DAC 3 6 typical 0
125. to select either the front panel external clock or the PXI DSTARA input on P16 The control signal PLL_CLKA_SEL is from the application logic FPGA and is set by the host software when the standard logic image is used The following diagram shows the clock path when an external clock is used Note that the PLL is bypassed when using an external clock PLL_REF_SEL t 100MHz P16 Cs Ext Clock Input P1 PXI VCXO 12C Port DSTARA P16 FPGA vrec PLL_CLKA_SEL A D D LVCMOS AD 1 LVCMOS DAC D LVCMOS DAC 1 LVCMOS FPGA lt FPGA FPGA Figure 1 X3 2M External Clock Path The selection of the PLL reference clock is also software programmable The reference clock multiplexer selects the PLL reference clock as either the 100 MHz oscillator or the PXI_100M input on P16 The control signal PLL_REF SEL is from the application logic FPGA and is set by the host software when the standard logic image is used All external clock and reference inputs are LVDS and must be driven as a differential pair Each differential pair is 100 ohm terminated The LVDS inputs cannot be driven single ended both inputs must be actively driven Electrical characteristics of the inputs are shown in the following table X3 2M User s Manual 74 Parameter Min Typical Max Table 1 X3 External Clock and Reference Input Requirements The external clock and reference inputs are from either the front panel con
126. tom applications may use the Innovative PacketDeviceMap object to conveniently extract channelized data from a packet data source Stop streaming when both Channels have passed their limit if Settings AutoStop amp amp IsDataLoggingCompleted amp amp Stopped Stop counter and display it double elapsed Clock Stop StopStreaming UI gt AfterStreamAutoStop UI gt Log Stream Mode Stopped automatically Ul gt Log std string Elasped S FloatToString elapsed Packets are processed until a specified amount of data is logged or the GUI Stop button is pressed Auto analyze and retrigger in framed mode if Settings Framed X3 2M User s Manual 59 return if Settings ExternalTrigger 0 int64 samples int triggers amp amp if triggers FTriggered SoftwareTrigger Settings AutoTrigger FBlockCount Settings PacketSize static_cast lt int gt samples Settings FrameCount In the event that were operating in framed trigger mode the example code re asserts a software trigger each time a frames worth of data packets have been received If we re in cont EEProm Access inuous mode no action need be performed to sustain data flow Each PMC module contains an IDROM region that can be used to write information associated with the module In the next line of code we make a call to Malibu method IdRom which returns an object that act as interf
127. tream not connected Open the boards return Set up Parameters for Data Streaming First have UI get settings into our settings store UI GetSettings Before we start streaming all necessary parameters must be checked and loaded into option object UI gt GetSettings loads the settings information from the UI controls into the Settings structure in the Applicationlo class if SampleRate Module Input Info MaxRate UI gt Log Sample rate too high StopStreaming UI AfterStreamAutoStop return We insure that the sample rate specified by the GUI is within the capabilities of the module if Settings Framed if Settings FrameCount lt Settings PacketSize UI gt Log Error Frame count must exceed packet size UI gt AfterStreamAutoStop return The module supports both framed and continuous triggering In framed mode each trigger event whether external or software initiated results in the acquisition of a fixed number of samples In continuous mode data flow continues whenever the trigger is active and pauses while the trigger is inactive The code above issues a warning if the trigger mode is framed and ill formed FBlockCount 0 FBlockRate 0 FTriggered 1 The class variables above are used to maintain counts of blocks received reception rate and whether the module is currently triggered These values are initialized prior to each s
128. treaming run X3 2M User s Manual 55 Channel Enables int RequestedChannels 0 for int i 0 i lt Channels i RequestedChannels Settings ActiveChannels i 1 0 Module Input Info Channels Enabled i Settings ActiveChannels i true false Module Input Range i static cast X3RangedIoDevice IIRange Settings Range i int ActiveChannels Module Input Info Channels ActiveChannels int ActiveDevices Module Input Info Channels ActiveDevices int GangSize Module Input Info GangSize if ActiveChannels UI gt Log Error Must enable at least one channel UI gt AfterStreamAutoStop return Warn of device enable granularity violations if ActiveChannels ActiveDevices GangSize std stringstream msg msg lt lt NOTE Streaming lt lt ActiveChannels lt lt instead of lt lt RequestedChannels lt lt channels UI gt Log msg str The module supports up to eight channels of simultaneous data flow The previous call to GetSettings populated the Settings object with the number of channels to be enabled on this run That information is used to enable the required channels via the Channels object within the Module Input Info object Packets scaled in units of events samples per each enabled channel int SamplesPerWord 1 Module ReturnPacketSize Settings PacketSize ActiveChannels SamplesPerWord 2
129. umption in the logic requires many details to be considered Xilinx tools such as XPower are used to get the best estimates It is important that any custom logic design have a substantial safety margin for the power consumption Allowance for decreased power supply efficiency due to heating can account for 10 derating Also dynamic loads should be considered so that peak power is adequate In many cases a factor of two for derating is recommended Environmental Ratings X3 2M User s Manual 91 Environmental Ratings The X3 2M is available for environmental rating levels from LO office lab environment to L4 military and heavy industry Environment Rating L0 LI L2 L3 L4 lt ER gt Environment Office controlled Outdoor stationary Industrial Vehicles Military and heavy lab industry Applications Lab instruments Outdoor monitoring Industrial Manned vehicles Unmanned vehicles research and controls applications with missiles oil and gas moderate vibration exploration Cooling Forced Air Forced Air Conduction Conduction Conduction 5 CFM 5 CFM Operating Temperature 0 to 50C 40 to 85C 20 to 65C 40 to 70C 40 to 85C Storage Temperature 20 to 90C 40 to 100C 40 to 100C 40 to 100C 50 to 100C Vibration Sine 2g 5g 10g 20 500 Hz 20 2000 Hz 20 2000 Hz Random 0 04 g Hz 0 1 g Hz 0 1 g Hz 20 2000 Hz 20 2000 Hz 20 2000 Hz Shock 20g 11 ms 30g 11 ms 40g 11 ms Humidity 0 to 95
130. vf Load Event dog No devices detected Elapsed Finder The Finder is designed to help correlate board target numbers against PCI slot numbers in systems employing multiple boards X3 2M User s Manual 64 Target Number Select the Target number of the board you wish to identify using the Target Number combo box 2 TX Pmc Finder Ob Target Number Set LED Blink Click the Blink button to blink the LED on the board for the specified target It will continue blinking until you click Stop On OFF Use the On and Off buttons to activate or deactivate respectively the LED on the baseboard for the specified target When you exit the application the board s LED will remain in the state programmed by this applet Logic Loader The logic loader applet is used to deliver known operational logic images to the user logic device installed on a X3 10M The user logic must be loaded once per session as the logic part is cleared on bus reset or power up The utility may be used to configure the firmware either through its command line interface or from its GUI Windows user interface The former is often convenient during PC boot up to install a standard logic file Place a short cut with the command line option set into the Windows Startup folder to execute the program when the system is started This application supports configuration of the onboard Virtex logic device from an
131. we will discuss the common features of the X3 module family Specifics on each module are covered in later chapters X3 XMC Architecture The X3 XMC modules share a common architecture as well as many features such as the PCI Express interface data buffering features the Application Logic and other system integration features This allows the X3 XMC modules to utilize common software and logic firmware while providing unique analog and digital features Figure 7 X3 XMC Family Block Diagram The X3 XMCs have a variety of analog and digital IO front ends suited to many applications X3 2M User s Manual 25 X3 XMC Features FPGA Applications X3 SD 16 channels of 24 bit 216 ksps A D 7100 Xilinx Spartan3 1M Vibration measurement dB 2M option acoustics wide dynamic range applications X3 SDF 4 channels of variable resolution speed Xilinx Spartan3 1M Vibration measurement A D up to 24 bit 5 MSPS or 16 bit 20 2M option acoustics wide dynamic MSPS gt 100 dB below 2 5 MSPS range applications X3 25M Two channels of 25 MSPS 16 bit A D and Xilinx Spartan3A DSP 1 8M Ultrasound pulse digitizing two channels of 16 bit 50 MSPS DAC 16 waveform generation and bits front panel DIO stimulus response X3 A4D4 4 channels of 16 bit 4 MSPS A D and 4 Xilinx Spartan3A DSP 1 8M Servo controls process channels 16 bit 2 MHz DAC with low instrumentation latency 8 bits front panel DIO X3 S
132. y be coming Better to shut down than crash in most cases The temperature X3 2M User s Manual 86 failure alert tells the system that the module actually shut itself down This usually requires that the module be restarted when conditions permit The data acquisition alerts including over ranges overflows and triggering tell the system that important events occurred in the data acquisition process Overflow is particularly bad data was lost and the system should try to alleviate the system by unclogging the data pipe or just start over If you get an overrange alert then the data may just be bad for a while but acquisition can continue Modules with programmable input ranges can use this to trigger software range changes Software alerts are used to tag the data Any message can be made into an alert packet so that the data stream logged includes system information that is time correlated to the data Table 17 Alert Types Alert Purpose Timestamp rollover The 32 bit timestamp counter rolled over This can be used to extend the timestamp counter in software Software Alert The host software can create alerts to tag the data stream Over Temperature Alarm Sensor Failure The module temperature exceeded 85C Temperature Warning The module temperature exceeded 70C PLL Lost The sample clock PLL lost lock The PLL must be reconfigured ADC Queue Overflow The ADC data queue overflow

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