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USER'S MANUAL - Oho

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2. could be soldered to the 5V supply voltage for generation of an 5V rail on tp6 Use 6800 to 10kQ for R44 22 FB4MC11 PLD22 pin14 Connection to the 24pin DIL plug to pin14 via serial resistor CON2 pin14 Not used for the 20pin DIL plug 23 FB4MC14 OSC osc Crystal oscillator input XOSC1 This signal should be routed internally to a global clock net 24 TDO TDO JTAG interface GOP_XC9572XL USER S MANUAL V0 9 Page 14 of 24 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de CON1 ping 25 GND Power GND Connection to the GND Layer of the PCB 26 VCCIO Power VCC Power supply 3 3V from regulator LP2992 3 3 27 FB4MC15 PLD27 pin15 Connection to the 24pin DIL plug to pin15 via serial resistor CON2 pin15 pin11 Connection to the 20pin DIL plug to pin11 via serial resistor 28 FB4MC17 PLD28 pin16 Connection to the 24pin DIL plug to pin16 via serial resistor CON2 pin16 pin12 Connection to the 20pin DIL plug to pin12 via serial resistor 29 FB2MC2 PLD29 pin17 Connection to the 24pin DIL plug to pin17 via serial resistor CON2 pin17 pin13 Connection to the 20pin DIL plug to pin13 via serial resistor 30 FB2MC5 PLD30 pin18 Connection to the 24pin DIL plug to pin18 via serial resistor CON2 pin18 pin14 Connection to the 20pin DIL plug to pin14 via serial resistor 31 FB2MC6 PLD31 pin19 Connectio
3. devices gt Rapid Prototyping gt Fast evaluation of Xilinx CPLD s gt Hardware platform for VHDL VERILOG digital design introductory courses GOP_XC9572XL USER S MANUAL V0 9 Page 5 of 24 OHO Elektronik Rudolf Diesel Str 8 gt D 85221 Dachau Germany www oho elektronik de 2 3 Xilinx XC9572XL CPLD Features Document 1 and 2 lists lots of goodies here are the best facts gt Highest density and lowest cost non volatile CPLD device in the 64 macrocell device class but with 72 macrocells gt 4 logic arrays 18V54 each offers 54 array inputs with 18 macrocells and 90 product terms wired together by a FASTCONNECT II SWITCHMATRIX Inputs are 5V tolerant gt Macrocells offer D and T type flipflops with dedicated CE input gt 3 global clocks 2 global tristate nets and a global set reset net Programmable ground I O pins decreases ground bounce problems gt Free powerful VHDL VERILOG schematics simulation design software availlable Webpack gt 10000 reprogramming cycles 20 years data retention Widely used CPLD lots of information availlable by XILINX Inc and on the web 2 4 Xilinx XC9572XL CPLD Disadvantages The following items are not relevant in most cases However they should be used as a checklist wheather an application is affected gt Relative high power consumption gt Output current driving capability is asymmetrical VOH 4 mA VOL 8 mA in a 3 3V VCCIO con
4. logical 0 must be 0 8V The minimum high input voltage VIH where the CPLD sees a logical M must be 2 0V and must not exceed 5 5V Voltage levels in between VIL and VIH should change very fast transition times should be lower than 100ns although Xilinx makes no recommendations about them in this CPLD family As stated in the datasheet after configuration of the device there are buskeepers on the I O s which only allows digital levels However the ISE software also knows of a floating pin option but the CPLD always has buskeepers on it s inputs and unused pins after configuration It is remarkable that because of the 5V tolerant inputs there is no diode between the inputs and VCC So the devices can be used in hot plugging applications 6 The XC9500 series outputs delivers different voltage levels dependent on the supplied VCCIO voltage In the GOP_XC9572XL module this voltage is 3 3V In this case the CPLD drives a low output O with a maximum of 0 4V at 8mA sink current If the CPLD sources current on a logical 1 output the voltage is guaranteed to be 2 4V minimum at 4mA So sourcing and sinking current is not symmetrical If more output current is desired 3 shows appropriate I V curves Another important fact is that a bidirectional I O with a pullup to 5V can not drive to 5V on the output but 3 3V only The output driver stage clamps the voltage to VCCIO in that case As an example driving bright leds wit
5. pin 32 pin16 21 FB2MC15 PLD37 pin21 Connection to CPLD pin 37 via serial resistor CPLD pin 37 pin17 22 FB2MC17 PLD38 pin22 Connection to CPLD pin 38 via serial resistor CPLD pin 38 pin18 23 FB1IMC2 PLD39 pin23 Connection to CPLD pin 39 via serial resistor CPLD pin 39 pin19 GOP_XC9572XL USER S MANUAL V0 9 Page 17 of 24 OHO Elektronik Rudolf Diesel Str 8 gt D 85221 Dachau Germany www oho elektronik de 24 PIN 24 5V input voltage to the module 10 DIL Connector Layout GOP_XC9572XL module top view for 24 pin and 20 pin emulation mode lt 20mm PAKA AGE d 4 oo0000000 oN 28mn 6 40 5mm _ gt 49 5mm GOP_XC9572XL USER S MANUAL V0 9 Page 18 of 24 st oO N To BG O 5 T L 3994S HCH GOOCAT OZ og utd uwy G z AOYETTIDSQ eTqeUuy lt p Utd oO oe 10199UUO ertaag UTdgz lt Z T Utd D D ZCGVEbX 1XZ2969X d09 sel See re dadung uondo utd wwz S A aGgwNnN 1UswunDog iS O 20p xzz96x dob JILIL ENDI 84DOS sDInag urdpz NYHOLG TzzG8 oyzjepue hg ubisag ZW OWS TG 8 41S TSSstq sTOPNa MINOYLAA1T4 OHO SE ET ci is CU FT TT CH E cc Zey Ze SEO E wa BE Ed az cea 9 ZZ eu C 5
6. 0kQ could be soldered on position R44 Please note that 5V rails can be produced only by tristating outputs A logical 1 output on an XC9572XL is clamped to VCCIO which is 3 3V on this module A crystal oscillator with an output frequency of 49 152MHz is connected to another I O of the CPLD This oscillator can be disabled completely by removing its power supply at jumper block CONS position 3 4 Please note that this clock must be routed inside the CPLD to a global clock net to insure proper synchronous circuit operation Furthermore 2 I O s are connected to a dual led having a red and a green chip in it s case These leds can be lighted by driving a logical 1 to these I O s Finally 2 I O s are connected to an RC network for demontration purpose A simple RC oscillator can be evaluated However it can be observed that an XC95xxx RC oscillator does t produce a stable clock The same PCB is used for the CoolRunner I module where the RC oscillator works fine due to selectable Schmitt Trigger inputs For the same reason CPLD pin 7 is fixed to GND this is a compatibility issue to the CoolRunner ll module 3 2 JTAG Port The CPLD JTAG signals are routed directly to the Xilinx standard 2mm 14pin JTAG port connector CON1 supported from the Parallel cable IV and Platform USB cable see 7 8 Pin 1 of the port is connected to GND which allows high speed programming with the above cables Pins 12 13 and 14 of the JTAG port ar
7. GOP XC9572XL USER S MANUAL V 0 9 OHO Elektronik www oho elektronik de Author M Randelzhofer OHO Elektronik Rudolf Diesel Str 8 gt D 85221 Dachau Germany www oho elektronik de OHO Elektronik Michael Randelzhofer Rudolf Diesel Str 8 85221 Dachau Germany WEB www oho elektronik de EMAIL info oho elektronik de Phone 49 8131 339230 FAX 49 8131 339294 2005 OHO Elektronik Michael Randelzhofer All rights reserved Disclaimer Under no circumstances OHO Elektronik Michael Randelzhofer is liable for conseguential costs losses damages lost profits Any schematics pcb or program parts are under the copyright of OHO Elektronik Michael Randelzhofer and can only be reproduced by permission of this company The contents of this USER S MANUAL are subject to change without notice However the main changes are listed in the revision table at the end of this document Products of OHO Elektronik Michael Randelzhofer are not designed for use in life support systems where malfunction of these products could result in personal injury The products of OHO Elektronik Michael Randelzhofer are intended for use in a laboratory test environment only They can generate radio freguency energy depending on the downloaded design and application which can disturb local radio or TV eguipment and so they have not been tested to be CE compliant If you encounter any technical problems or mistakes in this docu
8. LD pin 2 via serial resistor CPLD pin 2 pin6 7 FB1IMC17 PLD3 pin7 Connection to CPLD pin 3 via serial resistor CPLD pin 3 pin7 8 FB3MC5 PLD6 ping Connection to CPLD pin 6 via serial resistor CPLD pin 6 pin8 9 FB3MC2 PLD5 pin9 Connection to CPLD pin 5 via serial resistor CPLD pin 5 pin9 10 FB3MC11 PLD12 pin10 Connection to CPLD pin 12 via serial resistor CPLD pin 12 Short to GND by CONS for 20pin DIL plug 11 FB3MC14 PLD13 pin11 Connection to CPLD pin 13 via serial resistor CPLD pin 13 Not used for the 20pin DIL plug 12 GND GND Power ground plane connection 13 FB2MC14 PLD36 pin13 Connection to CPLD pin 36 via serial resistor O GTS1 CPLD pin 36 Not used for the 20pin DIL plug This is also an input to the global tri state net GTS1 14 FB4MC11 PLD22 pin14 Connection to CPLD pin 22 via serial resistor CPLD pin 22 Not used for the 20pin DIL plug 15 FB4MC15 PLD27 pin15 Connection to CPLD pin 27 via serial resistor CPLD pin 27 pin11 16 FB4MC17 PLD28 pin16 Connection to CPLD pin 28 via serial resistor CPLD pin 28 pin12 17 FB2MC2 PLD29 pin17 Connection to CPLD pin 29 via serial resistor CPLD pin 29 pin13 18 FB2MC5 PLD30 pin18 Connection to CPLD pin 30 via serial resistor CPLD pin 30 pin14 19 FB2MC6 PLD31 pin19 Connection to CPLD pin 31 via serial resistor CPLD pin 31 pin15 20 FB2MC8 PLD32 pin20 Connection to CPLD pin 32 via serial resistor CPLD
9. OP_XC9572XL USER S MANUAL V0 9 Page 23 of 24 OHO Elektronik Rudolf Diesel Str 8 gt D 85221 Dachau Germany www oho elektronik de 16 USER S MANUAL Revisions Version Date Comments V0 9 23 10 2005 Prerelease GOP_XC9572XL USER S MANUAL V0 9 Page 24 of 24
10. acenewsae eacesicntaxeestatancanicaieensaspaivaceveateecesaatee rncurxeunanuonse 22 15 IEN EEN 23 16 USER S MANUAL Kena inna aU 24 GOP_XC9572XL USER S MANUAL V0 9 Page 3 of 24 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de GOP_XC9572XL USER S MANUAL V0 9 Page 4 of 24 OHO Elektronik Rudolf Diesel Str 8 gt D 85221 Dachau Germany www oho elektronik de 2 Introduction The GOP XC9572XL is a mini module composed of a CPLD device with a PAL GAL compatible 24 pin DIL footprint Many additional features make it useful and flexible 2 1 GOP XC9572XL Features gt XC9572XL 10VQ44C CPLD a member of the XILINX XC9500XL family with a 24 or 20 pin PAL GAL compatible DIL footprint gt Xilinx Parallel Cable IV or Platform USB compatible download connector 14pin 2mm an OHO Elektronik low cost programmer is also availlable gt Operating voltage from 3 5V to 5 5V Serial resistors in the I O and test connector pins helps to decrease ringing gt Onboard Clock oscillator with 49 152 MHz for audio or RS232 applications gt Reverse plug in protection gt Ared green dual led gt A 7 pin test connector for probing internal signals or interconnecting several GOP s Solder jumpers for additional ground connections gt Easy to reuse Professional design manufactured on a 4 layer PCB Made in Germany 2 2 GOP XC9572XL Applications gt Replacement of PAL GAL
11. ard Overview 2mm 14pin JTAG PORT CON1 TELLERI 10000600 Te Gin e 2 54mm 24 Pin nd DIL k socket PLUG CH JP1 JP2 JP3 CON2 E E E E E E Access e Solder Jumper e To 22 e For Additional Ground 2 4 CPLD Connections e Pins 1 3 2mm 4pin 0 3 GAP Jumper Block CON3 1 2 20 Pin Ground 3 4 XOSC Supply 2 54mm 7pin Test Connector CON4 3 1 I O Distribution 22 Xilinx XC9572XL 10VQ44C CPLD I O s are wired to a 24 pin DIL socket plug CON2 on the bottom of the module through 220 serial resistors These resistors primarily reduces ringing Pin 1 and 2 of the DIL plug accesses global clock nets GCK1 and GCK2 inside the CPLD Pin 13 accesses the global tristate net GTS1 5 remaining I O s are availlable to the front side test connector CON4 also through 220 series resistors Pin 2 of the connector accesses the global tristate net GTS2 GOP_XC9572XL USER S MANUAL V0 9 Page 9 of 24 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de This pin also has a pullup resistor to VCC R39 A 2 54mm jumper can be used to short pin 2 to GND at pin 1 of the testconnector as a simple status input Pin 7 of the testconnector has an unmounted pullup resistor to the 5V supply voltage If a 5V rails is needed on this pin a resistor between 6800 and 1
12. e not used on this module Please notice the pin orientation of JTAG port CON1 GOP_XC9572XL USER S MANUAL V0 9 Page 10 of 24 OHO Elektronik Rudolf Diesel Str 8 gt D 85221 Dachau Germany www oho elektronik de 3 3 Power Suppy The module can be powered at DIL pin 24 from 3 5 to 5 5 Volts Module GND pin is pin 12 in 24 pin mode and pin 10 in 20 pin mode An onboard voltage regulator produces the CPLD core and I O voltage of 3 3V The regulator 5 can source up to 250mA While it s specification allows input voltages up to 16V power dissipation can reach it s maximum on lower input voltages depending on the CPLD design However if R44 is left unmounted the module can absorb transients up to 16V The module has a protection against reverse insertion or reverse power connection In that case the protection shorts the power supply by a polyfuse device The polyfuse recovers after deactivation of the power supply Burn through cycles of the polyfuse are limited For more information please consult the data sheet Even so care should be taken when plugging the module Consider that a short pulse of several amps can damage the environment in which the module is inserted 3 4 PAL GAL Emulation Of 24 Pin And 20 Pin Devices As a general hint the DIL plug should be protected mechanically with the supplied DIL sockets as an adaptor In 24 pin mode of the module a 24 pin socket should be used In 20 pin mod
13. e of the module a 20 pin socket should be used Please insure that pin 1 of the module is always pin 1 of a socket In the 20 pin mode an additional GND connection must be done via a 2mm jumper on jumper block CONS at position 1 2 see Layout Top View This adds GND to pin 10 In rare cases additional GND connections are desired Pins 3 14 and 23 can be shorted to GND with solder jumpers JP1 JP3 JP2 respectively on the bottom side of the module These shorts should be soldered via a stereo microscope to insure that there are no other invalid connections GOP_XC9572XL USER S MANUAL V0 9 Page 11 of 24 OHO Elektronik Rudolf Diesel Str 8 gt D 85221 Dachau Germany www oho elektronik de 4 CPLD Design Support As for CPLD design 4 and 9 are very recommended readings VHDL and UCF design templates for 20 and 24 pin configurations are availlable GOP_XC9572XL USER S MANUAL V0 9 Page 12 of 24 OHO Elektronik Rudolf Diesel Str 8 gt D 85221 Dachau Germany www oho elektronik de 5 GOP XC9572XL I O Voltage Levels Since CPLD 1 O s can be inputs or outputs or bidirectional we have to distinguish between voltage levels driven from the outputs of the CPLD and voltage levels that are applied to their inputs The XC9500 series inputs can accept input voltage levels from 0 to 5V so they are 5V tolerant However they can not deal with analog input voltages The maximum low input voltage VIL where the CPLD sees a
14. erial resistor 40 FB1MC5 PLD40 pin3 Connection to the 20 24pin DIL plug to pin3 via serial CON2 pin3 pin3 resistor 41 FB1MC6 PLD41 pin4 Connection to the 20 24pin DIL plug to pin4 via serial CON2 pin4 pin4 resistor 42 FB1MC8 amp PLD42 pind Connection to the 20 24pin DIL plug to pin5 via serial CON2 pind pin5 resistor 43 FB1MC9 PLD43 pint Connection to the 20 24pin DIL plug to pin1 via serial O GCK1 CON2 pin10 pint resistor This is also an input to the global clock net 1 GCK1 44 FB1MC11 PLD44 pin2 Connection to the 20 24pin DIL plug to pin2 via serial O GCK2 CON2 pin10 pin2 resistor This is also an input to the global clock net 2 GCK2 FB1MC11 denotes function block1 macrocell 11 There is an UCF file definition for 24pin and another one for 20pin device usage GOP_XC9572XL USER S MANUAL V0 9 Page 15 of 24 OHO Elektronik Rudolf Diesel Str 8 gt D 85221 Dachau Germany www oho elektronik de 7 CON4 Test Connector Pinout Table Pin CPLD pin Schema UCF function net name port Comment 8 routed to name 1 GND GND Power ground plane connection 2 FB2MC11 PLD34 tp2 Test connector pin2 R38 is soldered to the 3 3V supply O GTS2 CON4 pin2 voltage as a pullup on tp2 Tp2 can be used as a simple input by shorting to tp1 This is also an input to the global tri state net GTS2 3 FB3MC15 PLD14 tp3 Test connector pin3 CON4 p
15. figuration gt Inputs do not have sufficient hysteresis for Schmitt Trigger functionality simple rc oscillators won t work gt Relatively unflexible product term distribution no PLA structure gt Output voltages drives only up to VCCIO a pullup can not reach 5V except in tristate gt No input registers I O setup time is 6 5ns for XC9572XL 10 parts gt In rare cases reprogramming is only possible if no running clocks are applied to any CPLD pin GOP_XC9572XL USER S MANUAL V0 9 Page 6 of 24 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de Flipflops can trigger on positive or negative edges only not on both This is a feature found on CoolRunner Il devices only gt No pullup option on the I O s after configuration but buskeepers gt Only 2 I O standards 3 3V and 2 5V low 2 5V output drive capability 2 5 GOP XC9572XL Board Picures Top And Bottom View Ls fs are BS ge amn gt e wes e iii Sekt eh ar KE Se VE TA TIR j LI e Ko M0 eege i 3 L VER GOP_XC9572XL USER S MANUAL V0 9 Page 7 of 24 OHO Elektronik Rudolf Diesel Str 8 gt D 85221 Dachau Germany www oho elektronik de 2 6 GOP XC9572XL Board In A Lab Environment GOP_XC9572XL USER S MANUAL V0 9 Page 8 of 24 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 3 GOP XC9572XL Bo
16. gt D 85221 Dachau Germany www oho elektronik de 14 Technical Specifications CPLD Xilinx XC9572XL 10VQ44C Supply Voltage on PIN24 3 5 5 5V Size 40 5 x 20mm 1 594 x 0 787 Height PCB to Top max 8mm 0 315 Height PCB to Bottom max 12mm 0 472 Weight 7g GOP_XC9572XL USER S MANUAL V0 9 Page 22 of 24 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 15 Literature 1 DS054 XC9500XL High Performance CPLD Family Data Sheet http direct xilinx com bvdocs publications DS054 pdf 2 DS057 XC9572XL High Performance CPLD http direct xilinx com bvdocs publications ds057 pdf 3 XAPP150 I V Curves for Xilinx FPGA and CPLD Families http direct xilinx com bvdocs appnotes xapp150 pdf 4 XAPP444 CPLD Fitting Tips and Tricks http direct xilinx com bvdocs appnotes xapp444 pdf 5 LP2992 Micropower 250 mA Low Noise Ultra Low Dropout Regulator http cache national com ds LP LP2992 pdf 6 XAPP140 XC9500XL CPLD Power Sequencing and Hot Plugging http direct xilinx com bvdocs appnotes xapp140 pdf 7 DS097 Xilinx Parallel Cable IV http direct xilinx com bvdocs publications ds097 pdf 8 DS300 Platform Cable USB http direct xilinx com bvdocs publications ds300 pdf 9 XAPP784 Bulletproof CPLD Design Practices http direct xilinx com bvdocs appnotes xapp784 pdf 10 XAPP805 Driving Leds with Xilinx CPLD s http direct xilinx com bvdocs appnotes xapp805 pdf G
17. h relatively high current consumption is best done by sinking current or in other words the cathode of the led should be connected to a CPLD I O the anode to the led s supply voltage If the leds have forward voltages beyond 3 3V e g blue leds the 5V tolerance can be used to completely turn off the led by tristating the output For driving leds with CPLD s see also 10 Please consider that there are 220 series resistors between GOP XC9572XL pin connections and the CPLD GOP_XC9572XL USER S MANUAL V0 9 Page 13 of 24 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 6 Detailed XC9572XL VQ44 CPLD Pinout Table CPLD pin Schema UCF port Pin function net name 24pin 1 Comment 2 routed to 20 pin 1 FB1MC14 gck3 Useas an internal clock node to the global clock net GCK3 O GCK3 If XOSC1 is used but not routed to GCK1 or GCK2 use this global net instead 2 FB1MC15 PLD2 pin6 Connection to the 20 24pin DIL plug to pin6 via serial CON2 pin6 pin6 resistor 3 FB1MC17 PLD3 pin7 Connection to the 20 24pin DIL plug to pin7 via serial CON2 pin7 pin7 resistor 4 GND Power GND Connection to the GND Layer of the PCB 5 FB3MC2 PLD5 pind Connection to the 20 24pin DIL plug to pin9 via serial CON2 pind pin9 resistor 6 FB3MC5 PLD6 ping Connection to the 20 24pin DIL plug to pin8 via
18. in3 4 FB4MC2 PLD19 tp4 Test connector pin4 CON4 pin4 5 FB4MC5 PLD20 tp5 Test connector pin5 CON4 pind 6 FB4MC8 PLD21 tp6 Test connector pin6 CON4 pin6 R44 could be soldered to the 5V supply voltage for generation of an 5V rail on tp6 Use 6800 to 10kQ for R44 R ode 5V input voltage protected by a polyfuse 8 CON3 Configuration Jumper options Enable 20pin PAL GAL Emulation put GND to pin 10 of CON2 Enable XOSC1 crystal oscillator 49 152 MHz GOP_XC9572XL USER S MANUAL V0 9 Page 16 of 24 OHO Elektronik Rudolf Diesel Str 8 gt D 85221 Dachau Germany www oho elektronik de 9 CON2 DIL Connector Pinout Table Pin CPLD pin Schema UCF function net name port Comment routed to name 1 FB1MC9 PLD43 pint Connection to CPLD pin 43 via serial resistor O GCK1 CPLD pin 43 pin1 This is also an input to the global clock net 1 GCK1 2 FB1MC11 PLD44 pin2 Connection to CPLD pin 44 via serial resistor O GCK2 CPLD pin 44 pin2 This is also an input to the global clock net 2 GCK2 3 FB1MC5 PLD40 pin3 Connection to CPLD pin 40 via serial resistor CPLD pin 40 pin3 4 FB1MC6 PLD41 pin4 Connection to CPLD pin 41 via serial resistor CPLD pin 41 pin4 5 FB1MC8 PLD42 pin5 Connection to CPLD pin 42 via serial resistor CPLD pin 42 pind 6 FB1MC15 PLD2 pin6 Connection to CP
19. ment please contact mrandelzhofer oho elektronik de serious hints are very appreciated Trademarks All brand names or product names mentioned are trademarks or registered trademarks of their respective holders PAL and GAL are registered trademarks of Lattice Semiconductor Corp GOP_XC9572XL USER S MANUAL V0 9 Page 2 of 24 OHO Elektronik Rudolf Diesel Str 8 gt D 85221 Dachau Germany www oho elektronik de 1 Table of contents Uert TS 3 SE ue e EE 5 21 SOP XC9S E EE 5 2 2 GOP XC9572 XL App aa en anna 5 232 Xilinx EE TEE 6 TA Xilinx XC9572XL CPLD A 6 2 3 GOP XC9572XL Board Picures Top And Bottom VIEW Mo oo o ooommomoomsmbntk 7 2 6 GOP XC9572XL Board In A Lab Environment o ooooo iemneaanank nina 8 Be GOP XC9572 E E ET 9 SS MO KE elt han ina AN ARE NN EE E ER RER 9 EE e E EEN 10 3s en Se aan BB 11 3 4 PAL GAL Emulation Of 24 Pin And 20 Pin Devices cccceccsecssecesecseeeeesceceecesaeceseceeneeeaees 11 Ae CPLD D si n SOP OTL ieira saen esere ainn EEE EEE EREE OE EE E UNTAN TN SAS NASA 12 ae GOP XC9572XL VO Volt ge Levels EEN 13 6 Detailed XC9572XL VQ44 CPLD Pinout Table 14 Ts CON4 Test Connector Pinout EE 16 8 CONS Configuration Jumper options rian kekanan Basa 16 9 CON2 DIL Connector Pinout Table E 17 10 DIL Connector Lay E 18 11 KEE 19 12 gt Mod le Layout Top E 20 13 Module L yout Bottom Eeer nan annA R N a 21 14 Technical Specifications lt c gpeicescocencasansuacescnraevac
20. n to the 24pin DIL plug to pin19 via serial resistor CON2 pin19 pin15 Connection to the 20pin DIL plug to pin15 via serial resistor 32 FB2MC8 PLD32 pin20 Connection to the 24pin DIL plug to pin20 via serial resistor CON2 pin20 pin16 Connection to the 20pin DIL plug to pin16 via serial resistor 33 FB2MC9 LED R ledrd Red led of the duo led O GSR LED1 0 gt led off 1 gt led on This is also an input to the global set reset net GSR 34 FB2MC11 PLD34 tp2 Test connector pin2 R38 is soldered to the 3 3V supply O GTS2 CON4 pin2 voltage as a pullup on tp2 Tp2 can be used as a simple input by shorting to tp1 This is also an input to the global tri state net GTS2 35 VCCINT PowerVCC Power supply 3 3V from regulator LP2992 3 3 36 FB2MC14 PLD36 pin13 Connection to the 24pin DIL plug to pin13 via serial resistor O GTS1 CON2 pin13 Not used for the 20pin DIL plug This is also an input to the global tri state net GTS1 37 FB2MC15 PLD37 pin21 Connection to the 24pin DIL plug to pin21 via serial resistor CON2 pin21 pin17 Connection to the 20pin DIL plug to pin17 via serial resistor 38 FB2MC17 PLD38 pin22 Connection to the 24pin DIL plug to pin22 via serial resistor CON2 pin22 pin18 Connection to the 20pin DIL plug to pin18 via serial resistor 39 FBIMC2 PLD39 pin23 Connection to the 24pin DIL plug to pin23 via serial resistor CON2 pin23 pin19 Connection to the 20pin DIL plug to pin19 via s
21. serial CON2 ping pin8 resistor 7 FB3MC8 PRG GND Additional GND connection as a programmable ground pin Power GND 8 FB3MC9 LED_G ledgn Green led of the duo led LED1 0 gt led off 1 gt led on 9 TDI TDI JTAG interface additional 47k pullup to VCC CON 1 pin10 10 TMS TMS JTAG interface additional 47k pullup to VCC CON1 pin4 11 TCK TCK JTAG interface additional 47k pullup to VCC CON1 pin6 12 FB3MC11 PLD12 pin10 Connection to the 24pin DIL plug to pin10 via serial resistor CON2 pin10 Short to GND by CON3 for 20pin DIL plug 13 FB3MC14 PLD13 pin11 Connection to the 24pin DIL plug to pin11 via serial resistor CON2 pin11 Not used for the 20pin DIL plug 14 FB3MC15 PLD14 tp3 Test connector pin3 CON4 pin3 15 VCCINT Power VCC Power supply 3 3V from regulator LP2992 3 3 16 FB3MC17 RC IN rcin Input to an RC network this is for demonstration that rc RC network oscillators do not work reliably with XC9500 but on CoolRunner ll devices with Schmitt Trigger inputs 17 GND Power GND Connection to the GND Layer of the PCB 18 FB3MC16 RC OUT rcout Output from an RC network this is for demonstration that RC network rc oscillators do not work reliably with XC9500 but on CoolRunner ll devices with Schmitt Trigger inputs 19 FB4MC2 PLD19 tp4 Test connector pin4 CON4 pin4 20 FB4MC5 PLD20 tp5 Test connector pin5 CON4 pin5 21 FB4MC8 PLD21 tp6 Test connector pin6 CON4 pin6 R44

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