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PCl-20091W-1 HIGH SPEED ANALOG INPUT BOARD USER

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1. 2 10 HS RUN 6 20 Functions arae 73 74 DMA operation eren 74 73 VO type codes tate 7 3 mnemonic definitions 3 5 I O types DMA channel list 5 6 H READ iei 6 22 table 6 7 Hard disk WTEC 6 24 subdirectory for Software Drivers 3 4 ID code Hardware Board 7 6 block 12 configuring eese reete tenete 2 9 configuration and installation 2 1 ID codes initialization examples 63 discussion eene eerte 74 installation s 2 11 Illegal channels 6 10 programming procedures 7 13 INCLUDE QuickBASIC command 61 specifications ess 7 20 INIT instruction 3 5 6 3 6 21 technical 7 1 Input channel testing and calibration 71 7 13 Hardware configuration Installation for high speed data acquisition Al hardware nr 2 1 3 1 INDEX 4 PCI 20091W 1 INDEX Installation
2. 26 3 6 IN wo IN W12 IN W14 IN amp HCDCO 27 W27 IN W28 ING 28 1 ADDRESS 29 a en M 31 32 33 we aah ee 2 ALL OTHER JUMPERS OUT DMA diocl E e eed acie unde 242200 Be ce ars 37 l 39 ANALOG INPUT SIGNALS MUST BE CONNECTED TO THE TERMINALS LABELED 40 4 5 6 AND 7 ON THE PCI 20010T 1 AND THE PCI 20010T 1 MUST BE 41 CONNECTED TO THE PCI 20091W 1 42 9 deese dede dede de Je dee ee de dede ee de dee de de dede de de dede de dede dee dee de de dede ede de dede Je dco dede de de de de dee dede de jede fede de 43 18 INCLUDE THE DRIVER INTERFACE HEADER FILE n SINCLUDE 5 48 INITIALIZE THE PCI 20092S 1 SYSTEM THIS CALL MUST BE MADE PRIOR a CALLING ANY OTHER 1 200925 1 INSTRUCTION 51 PRINT 55 PRINT Begin PCI 20092S 1 Sample Program 4 24 CALLS ABSOLUTE SYSINIT 56 SEGMT DEFINED BELOW IS THE BASE ADDRESS OF THE 20091 1 57 USE amp HCDCO BUT YOU CAN SET IT ANYWHERE REFER TO THE 1 20091 1 58 MANUAL FOR MORE INFORMATION INIT MUST BE CALLED ONCE FOR EACH 20 CARD IN THE SYSTEM EACH WITH ITS OWN ADDRESS 61 amp HCDCO CALLS ABSOLUTE SEGMT INIT 64 CHECK FOR A SYSTEM ERROR DURING DEBUG CALL ERR SYS OFTEN 65 POSSIBLY AFTER EVERY CALL TO THE PCI 20092S 1
3. 3 8 3 7 1 ERRORS WHILE LOADING THE SOFTWARE DRIVERS 3 9 3 7 2 MEMORY RESIDENT PROGRAMS 3 10 5722 OWL GHB SEEN AR Soke 3 11 SWITCH V INTERRUPT VECTOR 3 11 SWITCH G BYPASSING CONFIRMATION 3 11 SWITCH ALLOCATE DMA BUFFER 3 11 SWITCH X EXECUTE COMMAND LINE 3 12 3 7 4 EXAMPLES OF LOADING THE SOFTWARE DRIVERS 3 12 iii PCI 20091W 1 High Speed Analog Input Board CHAPTER 4 HIGH SPEED ANALOG DATA ACQUISITION 4 1 4 2 4 3 4 4 Introduction and Chapter Overview 4 1 Hardware Configuration 4 1 Programming Guidelines 4 2 431 TIMING oh pect RC 4 2 4 3 2 TESTING HIGH SPEED SAMPLING RATES 4 3 High Speed Mode 4 Hardware Controlled High Speed Analog Acquisition 4 3 4 4 1 DESCRIPTION 4 3 4 4 2 PROGRAMMING 4 4 CHAPTER 5 DMA DATA ACQUISITION AND CONTROL 5 1 Introduction and Chapter Overview 5 1 5 1 1 DMA INTRODUCTION 5 1 5 1 2 SEQUENCE OF OPERATION 5 1 5 1 3 INFORMATION REQUIRED FOR RUN
4. 5 5 DMA Rates The maximum rate speed at which a DMA process will run without overrun errors is dependent on several factors The rate is defined as the average number of bytes per second at which data is transferred by the DMA process For example if you have set up a DMA rate of 20 000 samples per second then the average byte per second rate is 40 000 The absolute maximum DMA rate with this system is 89 000 samples per second The factors affecting maximum DMA speed include 1 The amount of data being acquired The smaller the burst of data the faster it can be sampled 2 The host computer being used Variations in maximum DMA rates occur for different PC compatibles IBM ATs and compatibles are actually slower than PCs because of the way DMA is implemented internally 3 The nature of the foreground program If the processor is executing instructions which use many bus cycles and will not relinquish the bus then the maximum DMA rate will be much lower If your program outputs to the screen and causes it to scroll or clears the screen then you may get an overrun error ifa DMA process is running at the same time If your program sets up a DMA process which is too fast for your system the DMA controller will do its best to execute it However if a pacing signal occurs before the previous data word is completely transferred that pacing signal is ignored and the corresponding data is lost and the overrun error
5. 2 7 2 6 Interrupt Levels and Sources 2 7 2 7 DMA e EPI 2 9 2 7 1 DMA CAPABILITY AND INTERRUPT 2 9 272 DMA MODES pego st 2 9 273 PACING SOURCE 2 10 27 4 DELAY COUNTER E SON Foe es 2 10 2 7 5 CHANNEL SELECTION 2 10 2 8 Rate Generator ee ae a e 2 10 2 9 Installing the Board Into Your 2 11 2 10 Pins and Ports Connecting to the Outside World 2 12 2 10 1 ANALOG CONNECTOR 2 2 12 2 10 2 DIGITAL CONNECTOR 2 12 CHAPTER 3 SOFTWARE INSTALLATION 3 4 Chapter Overview 3 1 3 2 Software Drivers Included With Your System 3 1 3 3 System Configuration Requirements 3 2 3 4 The PCI 20092S Software Drivers License Agreement 3 2 3 5 Creating a Working Copy of Your Software 3 2 3 5 1 PROCEDURE FOR ONE OR TWO FLOPPY DISK DRIVES 3 3 3 5 2 PROCEDURE FOR ONE FLOPPY DISK DRIVE AND A FIXED DISK DRIVE 3 4 3 6 Software Drivers Description 3 5 3 7 Loading the Software Drivers Routines
6. 7 8 DMA terminal count Interruption 2 8 DMA RUN 6 15 DMA STAT instruction 6 6 6 16 DMA STOP instruction 6 6 6 18 DOS batch file processing 3 13 COMMAND COM 3 8 COMP 3 4 INDEX DISKCOMP command 3 3 DISKCOPY command 3 3 EXIT comnmaftd ue eod ens 3 8 MODE 3 10 MORE 3 3 PATH command 3 10 PRINT command 3 10 PROMPT command 3 10 SET 4 5 4 4 3 10 user defined interrupts 3 11 version required ess 3 2 E Emulation of PCI 20041C Carrier 1 3 Enable procedure delay Counter uiii porre 7 15 rate generator 7 16 Entry point offsets Mnemonic definitions 3 5 Environment error 2 4 40 4 7 3 10 ERR SYS instruction 3 5 6 6 6 19 6 25 Error codes aio horae eet arae n eina 3 5 6 25 PUR PONE TRENT 6 25 Errors command line 3 9 during application program 6 2 6 19 6 25
7. 6 9 SOUTCE 5 2 SPCC d 5 3 starting acquisition 6 15 SCOPING esa edi bud 6 18 System resource requirements 5 1 5 2 triggered lt lt 4 5 2 DMA channel list 6 9 6 10 DMA channel selection factory configuration 2 10 DMA control hardware function s 7 4 DMA data reading qu 6 8 DMA enable 2 9 DMA mode dieti tc 7 7 DMA mode 20 5 2 checking termination 6 16 7 16 stopping before terminal count 6 18 DMA mode 5 2 5 6 checking for trigger 6 16 7 17 stopping before trigger condition 6 18 mode 4 esci iri ost osi HEN 5 3 7 18 6 18 DMA mode sio 5 6 DMA modes buffers 5 5 200475 Software Drivers 2 9 DMA programming procedure external start convert pacing 7 16 rate generator pacing 7 16 DMA start etis 7 7 DMA stop
8. od epit 6 2 DEFIN 6 7 DIM 6 7 gir que 6 2 POKE se edle qd 6 2 QuickBASIC variables 6 7 R Ranges 2 6 Rate generator uenire rient tdeo 6 13 DMA programming 7 16 enable or disable 7 16 frequency determination 6 13 frequency reference 2 10 hardware function 7 3 initialization erac etrazrende ines 7 16 2 7 6 13 output signal 1 2 programming 7 16 programming procedures 7 16 cuc MM 7 8 7 9 start conversion source 1 2 start of conversion source 2 6 Status register 7 11 time base for high speed data acquisition4 1 eia tuse 6 13 Read back command delay counter 7 11 rate generator eseessensseesesroreesevrorre se 7 11 INDEX Read MSB ac ooa 2 7 start conversion 5 1 2 start of conversion source 2 7 Read procedure delay counter 7 15 READ CH instruction 3 5 6 6 6 22 Reading chann
9. M 3 12 Software command allocate DMA buffer 3 11 start conversion source 1 2 bypassing confirmation 3 11 Software drivers 73 execute command line 3 12 channel numbers assigned 6 3 D 3 11 compatibility 7 12 interrupt vector eere 3 11 DMA channel support 2 10 eene ene eene nennen 3 12 DOS commands 3 10 SYSINIT instruction 3 5 6 23 errors while loading 3 9 SYSINIT instruction 6 19 general theory of operation 3 5 System resources hardware initialization 6 3 used by DMA eene 5 1 instruction specifications 6 6 System status 3 1 444442000 4 1 1 7 7 hist of calls 6 4 list of files eee rettet 3 loading soe M 3 8 T loading from batch file 3 11 3 12 3 5 Terminal count technical 6 1 0 44 4 0 2 8 unloading 3 8 3 13 Testing using in application pro
10. 2 8 TABLE 2 6 DMAControlJumper Settings 2 9 TABLE 2 7 Mode Descriptions 2 10 TABLE 2 8 DMA Control Jumper Settings 2 10 TABLE 2 9 Digital Connector pinouts and signal descriptions 2 12 TABLE 3 1 Summary of PCI_92S EXE switches 3 12 TABLE 4 1 High Speed Programming Instructions 4 2 TABLE 5 1 Effect of the DMA Process on Foreground Programs 5 4 TABLE 6 1 TYPOS oe Su E p auk E RR 6 7 TABLE 6 2 DMA Status Return Values 6 16 TABLE 7 1 PCI 20019M 1A Calibration Set Points 7 2 TABLE 7 2 PCI 20019M 1A Calibration Set 7 2 TABLE 7 3 Register Offsets 7 5 TABLE 7 4 DMA Control Jumper Settings 7 6 TABLE 7 5 Offset 043 Control Words 7 10 TABLE 7 6 Offset 043 Rate Generator RG Programming Codes 7 10 TABLE 7 7 Offset 043 Counter Data and Status Read Command Format 7 11 TABLE 7 8 Offset 040 or 041 Returned Status Format 7 11 TABLE 7 9 Jumper Definitions Summary 7 19 TABLE 7 10 A D Conversion Formaulas 7 22 TABLE 7 11 A D Codes vi PCI 20091W High Speed Analog Input Board 20000 Pers
11. eren 7 7 Requirements for PCI 20091W 1 een 1 2 for 200925 3 2 software language nne 3 2 Return value 0 8 2 6 6 RG T 6 24 S Sampling rate e 5 3 PCI 20091W 1 INDEX 7 PCI 20091W 1 High Speed Analog Input Board formula 6 14 DE 2 10 Sampling rates factory 2 6 DMA 4 5 4 jumpers 27 high speed data acquisition 4 3 hari 7 12 55 4 4 4 4 3 SOftware 4 0 2 7 Scanner start channel sources 1164 0 2 4 440 1 2 agitis 7 13 Subdirectory for Software Drivers 3 4 Segment Switches memory address 7 4 base address eee 7 4 Sequence of operation CICK BASIC 6 1 DMA 5 1 setting addresses 2 1 high speed data acquisition 44 Switches software Settling delay 7 14 JD e anteire 3 11 Shell progr ms 3 10 CM P 3 11 Software AN 3 11 installation 3 1 7
12. 4 1 PCI 20041C Carrier emulation 1 3 M PCI 20046S Software Drivers compatibility with PCI 20091W 1 1 3 M 200475 Software Drivers anual channel advance DMA mod 29 DA eer DM 6 9 Hich dd aum 20091 1 igh speed data acquisition 6 11 sunimum reduirements 12 Manual overview 1 1 Memory addresses 74 summary 4 1 1 Memory map system compatibility 1 3 IBM PC 2 1 Memory resident programs 3 10 Gcr peel de Dri quaa M M Mnemonic definitions esses 3 5 en es MODE DOS command 3 10 brief description 1 2 MORE DOS command 33 description 3 1 2 9 925 described mana 3 5 N PCIHEADQ BAS application programs and 6 1 Naming conventions 2 2 3 5 6 1 3 2 PEEK QuickBASIC command 6 2 POKE QuickBASIC command 6 2 Polarity 2 6 Offset Posttrigger 5 3 memory address 7 4 Pretrigger data e 5 3 Offsets PRINT DO
13. LX3 NI NI NI NI T3NNYHO T3NNVH9 IBNNVHO TANNVHO TANNVHO 1 2 TANNVHO TANNVHO NI Q Nr s aun OR LY3ANO9 Luvis 1X3 LIBIHNI LYSANOO _ 31907 LYaANOO 4841 401983439 ALVY 39019 TOULNOS v MOMN3 L SOLA NOLLONN 53119975 M340d 019373 ssayaay 5 x 30193134 04 S Lr n d NOILVS3N39 Qi WALSAS HE vivd VLVO SSHOLIMS 553 00 193135 W3LSAS Fig 1 1 Hardware Block Diagram PCI 20091W 1 1 4 Chapter 2 Hardware Configuration 2 1 Configuration and Installation An Overview This chapter covers physically configuring and installing your hardware For more in depth information on the hardware see chapter 7 You must set switches and jumpers to configure your Board The following list gives the configuration options for your board and the sections in which these topics are covered e You must set the base address of your Board section 2 2 You must choose an analog signal range section 2 3 e You must select a method of starting a conversion section 2 4 You can enable an automatic channel scanning sequence s
14. WRITE NOT USED Offset 102 MSB Analog Data READ MSB Analog Input Data bits 0 3 Reading this offset returns data that is right justified in the following format Reading this offset also clears the AI EOC bit in the Interrupt Status register If the Board is configured for start of conversion on read of MSB reading this register will start a new analog to digital A D conversion See section 2 4 for information on configuring this mode WRITE NOT USED Offset 103 Start Conversion Reading from or writing to this register initiates a software analog input start convert READ Start Conversion data undefined Reading this offset starts a conversion The data read has no meaning WRITE Start Conversion data ignored Writing to this offset starts a conversion The data written has no meaning 7 12 PCI 20091W 1 Chapter 7 Hardware Technical Reference Offset 104 Input Channel READ NOT USED WRITE Input Channel bits 0 3 Writing to this offset sets the analog input channel to be converted on the next hardware or software start convert command If automatic channel sequencing is enabled the first channel in the sequence input channel must be set by writing to this register as well as by programming Offset 105 bit 3 0 disable MUX 1 enable MUX bits 0 2 channel number of analog input channel Offset 105 Scanner Start Channel READ NOT USED WRITE Scanner Start Channel bits 0 2
15. 5 5 5 7 5 REGISTER USE bed Rd ed RC Bee 7 6 Offset 000 Board ID Interrupt Status Mode 7 6 Offset 001 System Status Interrupt Status 7 7 Offset 002 DMA Start Mode 7 7 Offset 003 DMA Stop 7 8 Offset 004 ID Code 2 7 8 Offsets 005 Reserved 7 8 Offset 040 Low Order Rate Generator Counter 7 8 Offset 041 High Order Rate Generator Counter 7 8 Offset 042 Delay Counter 7 9 Offset 043 Rate Generator and Delay Counter Control 7 9 Offsets 044 OFF Reserved 7 11 Offset 100 ID Code 3 ur e eo 7 11 Offset 103 Stat Conversion 7 12 Offset 104 Input 7 13 Offset 105 Scanner Start Channel 7 13 75 Hardware Programming Procedures 7 13 7 5 1 MEMORY ADDRESSES 7 13 7 5 2 ANALOG INPUT PROCEDURE 7 13 PCI 20091W 1 High Speed Analog Input Board 7 5 8 DATA ACQUISITION WITH HARDWARE TIMING 7 14 7 5 4 DELAY COUNTER INITIALIZATION PROCEDURE 7 14 7 5
16. Instructions used CNERG Configure Rate Generator WRITE CH Write Channel A 3 3 SAMPLE PROGRAM 3 DESCRIPTION HIGH SPEED DATA ACQUISITION This program sets up and performs a data acquisition using High Speed Mode 4 It samples channels 4 5 6 and 7 The complete channel list is scanned 20 times You should provide known signals on at least some of these channels to compare with the measured values Instructions used HS RUN Run High Speed CNEHS Configure High Speed CNERG Configure Rate Generator A 3 4 SAMPLE PROGRAM 4 DESCRIPTION DMA DATA ACQUISITION This program demonstrates DMA input running in DMA Mode 3 You must con figure your Board to enable DMA on DMA channel 1 When you load 925 Q EXE you must specify the switch B1 This DMA mode requires a trigger signal which you should supply on the External Interrupt input The program samples channels 4 5 6 and 7 The complete channel list is scanned up to 64 times You should provide known signals on at least some of these channels to compare with the measured values Instructions used CNEDMA Configure DMA CNERG Configure Rate Generator WRITE CH Write Channel DMA RUN Run DMA DMA STAT DMA Status BUEDEC Decode Buffer DMA STOP Stop DMA A 3 5 SAMPLE PROGRAM 5 DESCRIPTION DMA DATA ACQUISITION This program demonstrates DMA input running in DMA Mode 2 You must con figure your Board to enable DMA on DMA channel 1 When you load 1925 Q E
17. jumper selectable An interrupt is used to signal the computer that an event has happened and that the Board requires action from the computer There is an PCI 20091W 1 2 7 20091 1 High Speed Analog Input Board excellent discussion of interrupts and their applications to data acquisition with the PCI 20000 System in The Handbook of Personal Computer Instrumentation which is provided with your system In order to use interrupts from your Board a signal from the Board must be connected to the Board s IRQO line and the Board s IRQO line must be connected to an interrupt level input on the computer Please refer to tables 2 4 and 2 5 for the jumper settings needed to select interrupt level and source The interrupt source is selected by jumpers W4 and W5 W4 IN selects the DMA Terminal Count signal as interrupt source This signalis generated when the Board receives a terminal count from the PC s DMA controller W5 IN selects the External Interrupt source Factory configuration for W4 W5 is OUT An interrupt on the selected level will occur when any selected source goes low TABLE 2 4 Interrupt Source Jumper Settings Interrupt Source Jumpers IN Jumpers OUT None WA W5 DMA Terminal Count WA W5 External Interrupt W5 4 Factory configuration The hardware interrupt level on the PCI 20091W 1 is controlled by jumpers W22 through W26 and jumper W32 using the settings given in table 2 5 No
18. 3 2 6 7 Voltage calibration 7 1 Voltage range 2 6 Voltage ranges analog 11 Select p 2 6 Voltages 2 11 7 2 Windowing programs 3 10 Working copy on two floppy 3 3 Software Drivers esse 3 3 with one floppy and one fixed drive 3 4 Write instructions eese 6 5 WRITE CH instruction 3 5 6 24 Writing hardware registers 7 4 Writing QuickBASIC application prografns PCI 20091W 1 INDEX 9 Appendix 1 200925 Sample Programs A 1 Appendix Overview Sections A 1 through A 4 introduce the sample programs we have included with your Software Drivers in order to help you optimize your usage of your hardware and software Section A 2 summarizes the sample programs and their associated instructions Section A 3 describes use of these programs with Microsoft QuickBASIC Section A 4 describes the graphics demonstration program A 2 SAMPLE PROGRAMS INTRODUCTION The Sample Programs on your Software Drivers diskette are described briefly below After you have set up your PCI 20000 system and have loaded the 200925 software you might want to try out those programs that illustrate the hardware features you will u
19. 6 20 INIT Initialize Utility Instruction 6 21 READ CH Read Channel Read Instruction 6 22 SYSINIT System Initialize 2 Utility Instruction 6 23 WRITE CH Write Channel Write Instruction 6 24 66 6 25 6 6 1 0 99 System Error Codes 6 25 6 6 2 100 199 Analog Input Error Codes 6 26 6 6 3 800 899 Rate Generator Error Codes 6 26 6 6 4 15 000 15 799 High Speed Acquisition Error Codes 6 26 6 6 5 15 800 16 499 Error Codes 6 28 6 6 6 20 100 20 199 BufferErrorCodes 6 29 CHAPTER 7 HARDWARE TECHNICAL REFERENCE 71 Introduction and Chapter Overview 7 1 72 Testing and Calibration 7 1 7 3 Doing It Yourself Hardware Programming 7 3 7 31 ANALOG TO DIGITAL A D CONVERTER 7 3 73 2 RATE GENERATOR 7 3 73 3 DMA OPERATION 25 555 ee 7 4 7 3 8 BOARD IDENTIFICATION 7 4 7A Register OUNSEIS RA Oe Re o 7 4 TAA WO REGISTERS ee de RAS D 7 4 7 4 2 MEMORY ADDRESSES 7 4 743
20. CALLS ABSOLUTE ERROR CODE ERR SYS IF ERROR CODE lt gt O THEN PRINT Error ERROR CODE Note that the variable ERROR CODE is set to zero before the first call to ERR SYS A general purpose error checking subroutine is incorporated into the Sample Programs Now you are ready to add calls to read and write your system s input and output channels and perform various control functions Until you are familiar with the 200925 1 instructions you should add call statements a few at a time with frequent calls to ERR SYS For example to read analog input channel number and place the returned value in VALUE you could add CALLS ABSOLUTE AI T CHN VALUE READ CH CALLS ABSOLUTE ERROR CODE ERR SYS IF ERROR CODE lt gt O THEN PRINT Error ERROR CODE You might also include program lines to display the data value returned in VALUE Save your program and then run it and check for errors after each change QuickBASIC provides no protection against the possibility of an instruction being called with the wrong number of arguments or non integer arguments There is also nothing built into QuickBASIC to prevent you from attempting to call functions when PCI 92S EXE has not been loaded although the header contains routines to 6 2 PCI 20091W 1 Chapter 6 Software Technical Reference check for a valid 925 To avoid losing your work if you inadvertently call an instruction incorrectly you sho
21. Factory configuration 2 4 Start of Conversion The PCI 20091W 2 provides four means of starting an A D conversion an external signal the onboard Rate Generator start conversionwhen the previous data is read and software command Conversions can always be started by software command The jumper settings to select the other three sources are shown in table 2 2 The hardware start of conversion sources are External Start Convert and the onboard Rate Generator An external start convert signal can be generated by a TTL low to high transition at pin 2 of connector P3 The Rate Generator is an counter driven by an on board 8MHz frequency reference If the onboard Rate Generator is selected it must be properly programmed See section 7 4 for information on how to do this or use the included 200925 Software Drivers A hardware start of conversion source must be used for high speed or DMA data acquisition In either hardware mode analog conversions may be inhibited by taking the Conversion Inhibit signal connector P3 pin 3 low The Board is factory configured for start of conversion from the Rate Generator 2 6 PCI 20091W 1 Chapter 2 Hardware Configuration Conversion can also be started when the previous data is read or by software command These are software sources A software start convert command is generated by a read or write to a command register or by a read of the most sig nificant data byte MSB Refer to se
22. PCI 20091W 1 High Speed Analog Input Board A D CONVERTER Input Range Unipolar 0to5V 0to10V Bipolar 2 5V 5V 10V Resolution 12 bits Output Code Unipolar Complementary Binary Bipolar Complementary Offset Binary Linearity Error 1 2 LSB Drift 3 ppm C Accuracy Trimmable to 0 1 2 LSB Drift 30 A D CODES To calculate the value for the voltage being measured substitute the A D output code INDATA from table 12 into the appropriate formula listed in table 7 10 TABLE 7 10 A D Conversion Formulas Voltage Range Conversion Formula 2 5V Range VOLTS 4095 INDATA 5 4096 2 5 5V Range VOLTS 4095 INDATA 10 4096 5 10V Range VOLTS 4095 INDATA 20 4096 10 5V Range VOLTS 4095 INDATA 5 4096 0 TO 10V Range VOLTS 4095 INDATA 10 4096 For example if the conversion code is 2047 and the PCI 20019M 1A is jumpered for a bipolar range of 10 volts then VOLTS 4095 2047 20 4096 10 0 7 22 PCI 20091W 1 TABLE 7 11 A D Codes Chapter 7 Hardware Technical Reference VOLTS Unipolar A D Output Code INDATA Full Scale Minus One LSB 0 1 2 Full Scale 2047 7FF Hex 0 4095 FFF Hex VOLTS Bipolar INDATA Full Scale Minus One LSB 0 0 egative Full Scale RATE GENERATOR Frequency Range Frequency Accuracy Output Signal POWER REQUIREMENTS T5V PHYSICAL L x H OPERATING TEMPERATURE 2047 7FF Hex 4095 Hex 2
23. 15500 15601 15701 Chapter 6 Software Technical Reference Illegal trigger address The trigger channel must be on the same Board or one at a higher segment address as the analog input chan nels in the channel list This can occur in a multi Board system Illegal trigger The specified trigger type is not legal in High Speed Mode 4 Invalid time base High speed acquisition timing operation is not supported for the specified channel Illegal time base address The pacer channel must be on the same PCI 20091W 1 or oneata higher segment address as the analog input channels in the channel list Illegal time base The specified time base typ is not legal in this High Speed mode llegal rate generator mode The rate generator is configured in a mode which is illegal for a pacer No High Speed Mode 1 function Data acquisition in High Speed Mode 1 is not supported by this software List empty The first element of the analog channel list was 1 the list terminator Invalid high speed mode The only high speed mode supported is Mode 4 Analog configuration error All analog input channels in the channel list must be reside on the same Board High speed configuration error A successful high speed configura tion was not performed prior to attempting a high speed acquisition Invalid pass count A pass count of 0 was specified or a pass count high enough to produce more than 64K of data was specified for a buffer not
24. INSTRUCTION TO 152 ACCESS THE DATA IN THE BUFFER 166 DIM CLUST 4 167 168 PRINT 169 PRINT Channel 170 PRINT Cluster 172 FOR 1 2 173 PRINT USING CHNS J 174 XT J 175 176 PRINT 177 176 FOR I 1 NUMCLSTS 180 DEC CLUSTS 1 153 NUM DECODED 0 183 CALLS ABSOLUTE DEC CLUSTS CLUST 1 NUM DECODED BUF DEC 184 ErrorCheck Error found while decoding buffer data 186 IF NUM DECODED lt gt DEC CLUSTS THEN 151 PRINT Internal Error Did not decode fuil cluster 157 END IF 125 PRINT THE DATA IN ALL FOUR FRAMES OF THE CLUSTER FIELD BY FIELD io PRINT USING s 1 195 FOR J 1 70 4 196 FDATA 20 4096 4095 CLUST J 10 197 PRINT USING 198 XT J 199 200 DO 201 K INKEYS 202 LOOP WHILE 203 204 PRINT 205 IF K 0 OR THEN END 207 NEXT I 208 209 PRINT Done 210 211 END 212 213 DEFSNG A E G Z 21 SUB ErrorCheck ErrorString AS STRING 215 DEFINE A GENERAL PURPOSE ERROR PROCESSING ROUTINE 218 ERROR CODEZ 0 219 CALLS ABSOLUTE ERROR CODE ERR SYS 221 IF ERROR CODE lt gt 0 THEN 223 STOP ANY DMA ACQUISITION THAT MIGHT HAVE BEEN RUNNING WHEN THE 224 ERROR OCCURRED 226 CLUSTSZ 0 244 CALLS ABSOLUTE CLUSTS Z DMA STOP 229 PRINT THE ERROR MESSAGE PASSED IN AS A PARAMETER AND THEN PRINT THE 251 ERROR CODE NUMBER 3 232 PRINT ErrorString ERROR CODEZ 233 END 234 235 END IF 236 237 END SUB 238 Sample Program
25. Invalid input channel Input functions for this channel are not sup ported Invalid output channel Output functions for this channel are not supported Invalid configuration A configure function is not supported for this channel type Re entry error An illegal re entry to the Software Driver routines has been attempted This can be caused by calling the Software Drivers routines from interrupt routines Test failure A Board initialization test failed 100 199 Analog Input Error Codes Analog to digital A D converter time out No end of conversion signal was received from an A D converter 6 6 3 800 899 Rate Generator Error Codes 6 6 4 15100 Invalid rate generator mode The rate generator mode specified is not supported for the specified channel Rate generator not configured A rate generator must be configured prior to a write operation Illegal count value The specified count value is not legal for the rate generator mode being configured Eight bit rate generator modes modes 6 through 11 must be configured with count values less than 256 In modes 2 3 8 and 9 a count value of 1 is illegal 15 000 15 799 High Speed Acquisition Error Codes Invalid trigger High speed acquisition trigger operation is not sup ported for the specified channel 6 26 PCI 20091W 1 15101 15102 15200 15201 15203 15204 15300 15301 15302 15303 15304 15305 15307 15309 15400
26. If you change this setting you must alter the Sample Programs Change the line SEGMT amp HCDCO to the segment part of the base address you have configured For example if you have set the base address to C8000 this line should read SEGMT amp HC800 To run the Sample Programs follow these steps 1 Configure your PCI 20091W 1 Board and install it in your computer as described in Chapter 2 Note that some of the sample programs expect specific jumper configurations 2 Make a work disk or set up a hard disk subdirectory as explained in Chapter 3 and put your original Software Drivers diskette away in a safe place 3 Load the Software Drivers by running PCI92S_Q EXE Specify the 1 switch if you will be running Sample Progams 4 or 5 Then load QuickBASIC with the User Library PCI 20091W Appendix 200925 Sample Programs If the User Library is not provided with your version of QuickBASIC refer to your QuickBASIC manual for instructions on how to create it 4 Determine which Sample Program you would like to try and load it into the QuickBASIC programming environment If necessary change the value of SEGMT as described above 5 Run the Sample Program providing inputs and monitoring outputs as appropriate Feel free to modify the Sample Programs to experi ment with your system A 5 Graphics Demonstration Program The file GRAPH BAS is a demonstration program that shows how
27. bits 0 02 DMA mode number DMA Mode 2 010 DMA Mode 3 011 DMA Mode 4 100 The Rate Generator and the Delay counter should be enabled only after the counters have been properly configured as described under Offset 43 PCI 20091W 1 7 7 PCI 20091W 1 High Speed Analog Input Board 7 8 Following complete DMA cata acquisition the Board s DMA circuitry must be reset before starting another acquisition Write a 0 and then a 1 to bit 5 to initialize and re enable DMA operation Offset 003 DMA Stop READ DMA Stop data undefined Reading this register will stop a DMA process in case of an overrun error This is the normal termination of a Mode 4 process only The data read has no meaning WRITE NOT USED Offset 004 ID Code 2 READ ID Code 2 bits 0 7 Reading this register returns 87 Hex This code can be used to uniquely identify this Board as being a PCI 20091W 1 rather than a PCI 20041C 3A Carrier PCI 20019M 1A Module combination See section 1 4 for an explanation of how the Board emulates this Carrier Module combination WRITE NOT USED Offsets 005 O3F Reserved Offset 040 Low Order Rate Generator Counter Before any reads or writes are performed from this register the Rate Generator control register must be configured see Offset 043 READ Reading this offset returns the current value of the low order 16 bits of the Rate Generator counter The data must be read as two consecutive bytes f
28. during channel reads 6 22 environment size 3 10 file not found eese 3 9 in arguments to CALLS 6 2 6 25 Subroutine to check 6 2 while loading command processor 3 9 while loading the Software Drivers 3 9 Examples channel list 6 10 hardware initialization 6 3 loading the software 3 12 EXIT DOS command 3 8 Expanded memory interrupt vector esee 3 11 Extended ID 7 6 Extended mode 2 9 External start convert 1 2 programming procedure 7 16 2 7 start of conversion source 2 6 PCI 20091W 1 INDEX 3 PCI 20091W 1 High Speed Analog Input Board F Hardware initialization software eene tenentes 6 3 Factory configuration examples 6 3 address switch 21 Hardware 12 channel scanning sequence 27 Hardware start convert channel selection 2 10 configuring eere teens 2 6 interrupt 28 High speed channel amp 6 11 interrupt 420 2 214
29. ported for the specified channel 16201 Invalid time base code No time base was specified or an invalid code was used 6 6 6 20 100 20 199 Buffer Error Codes 20100 Internal Error 20105 Data acquisition process running An attempt was made to modify or read buffer parameters for a buffer actively in use for data acquisition Halt all data acquisition processes before modifying buffers 20107 Internal error 20108 Internal error 20109 Invalid cluster size An attempt was made to initialize a buffer with a cluster size greater than the buffer size 20110 Internal error 20115 No memory has been allocated for buffers Reload the Software Drivers specifying B on the command line to allocate the desired amount of buffer memory PCI 20091W 1 6 29 Chapter 7 Hardware Technical Reference 7 1 Introduction and Chapter Overview This chapter contains technical details of your hardware including register infor mation that you may need for creating application programs if you choose not to use the included software or the PCI 20026S and PCI 20027S Software Drivers Section 7 2 tells how to test and calibrate your Board Sections 7 3 and 7 4 cover the details of addresses segments and registers offsets Section 7 5 gives the specific details on how to program your hardware using the registers Section 7 6 gives a summary table of the jumper assignments Be sure to read the descriptions in chapter 2 before using this t
30. 28 High speed data acquisition start conversion source 26 capabilities rere 4 1 voltage 42 2 6 channel selection 42 Features computer lock up 4 2 analog 1 1 configuring in software 6 11 automatic channel selection 12 hardware configuration 4 1 Convert Inhibit es 12 InsStrBctions 4 2 DMA trigger 12 Mode 4 4 3 12 4 1 rate 12 sampling rate formula 6 14 SDIBW 1 2 sequence 4 4 1 1 testing sampling 4 3 Files time 4 1 3 2 43 Foreground programs timing signal nere 6 11 and DM ran e 5 4 trigger signal 6 11 Forground programs trigger source ete 4 2 and 5 4 High Speed Mode 4 5 6 nennen 4 1 BRAIN c desi T an 5 5 High Speed Modes 1 43 41 Frequency reference High level language support 7 3 rate
31. 36 4 5 6 AND 7 ON THE PCI 20010T 1 AND THE PCI 20010T 1 MUST BE 37 CONNECTED TO THE PCI 20091W 1 38 9 dee de de dede de dee dede de dede dede dee de de deve dete de dede fe dee e dede deed eee dede eee de dee ede ede dee 39 My INCLUDE THE DRIVER INTERFACE HEADER FILE 22 INCLUDE PCIHEADQ BAS 44 INITIALIZE THE 200925 1 SYSTEM THIS CALL MUST BE MADE PRIOR n TO CALLING ANY OTHER 200925 1 47 PRINT 48 PRINT Begin PCI 20092S 1 Sample Program 3 zh CALLS ABSOLUTE SYSINIT 52 SEGMT DEFINED BELOW IS THE BASE ADDRESS OF THE PCI 20091 1 53 USE amp HCDCO BUT YOU CAN SET IT ANYWHERE REFER TO THE PCI 20091 1 54 MANUAL FOR MORE INFORMATION INIT MUST BE CALLED ONCE FOR EACH 22 CARD IN THE SYSTEM EACH WITH ITS OWN ADDRESS 57 amp HCDCO 55 CALLS ABSOLUTE SEGMT INIT 60 CHECK FOR A SYSTEM ERROR DURING DEBUG CALL ERR SYS OFTEN 61 POSSIBLY AFTER EVERY CALL TO THE PCI 20092S 1 IS GOOD IDEA 62 TO LEAVE A FEW ERR SYS CALLS IN A FINISHED PROGRAM TO MONITOR THE 95 STATUS OF THE SYSTEM 42 ErrorRoutine Error found during INIT 67 CONFIGURE THE SYSTEM FOR HIGH SPEED RUN USE RATE GENERATOR 68 CHANNEL O AS THE PACER IN MODE 4 69 READ ANALOG INPUT CHANNELS 4 5 6 AND 7 PCI 20091W Sample Program 3 71 PRINT Configuring High Speed Run 72 DIM HSCHNS 5 73 RG T 74 PAC CHN 0 75 4 76 TR TYPE 0 77 TR
32. 5 DELAY COUNTER ENABLE OR DISABLE PROCEDURE 7 15 7 5 6 DELAY COUNTER READPROCEDURE 7 15 7 5 7 RATE GENERATOR INITIALIZATION PROCEDURE 7 16 7 5 8 RATE GENERATOR ENABLE OR DISABLE PROCEDURE 7 16 7 5 9 DMA PROCEDURES 7 16 7 5 10 DMA MODE 2 PROCEDURE 7 16 7 5 11 MODE 3 PROCEDURE 7 17 7 5 12 DMA MODE 4 PROCEDURE 7 18 7 6 Jumper Definitions Summary 7 19 7 7 Hardware Specifications 7 20 Figure Listing Fig 1 1 Hardware Block Diagram 1 4 Fig 2 1 IBM Personal Computer Memory Map 2 3 Fig 2 2 Examples of setting addresses 2 4 Fig 2 3 Jumper Locations 2 5 Fig 2 4 Connector pin assignments 2 13 Fig 3 1 BASIC Language Software Drivers System 3 6 Fig 3 2 PCIHEADQBAS listing e 3 7 Table Listing TABLE 2 1Analog Input Voltage Range Settings 2 6 TABLE 2 2 Start of Conversion Jumper Settings 2 7 TABLE 2 3 Channel Scanning Sequence Jumper Settings 2 7 TABLE 2 4 Interrupt Source Jumper Settings 2 8 TABLE 2 5 Interrupt Level Jumper Settings
33. 6 3 2 EXAMPLES OF HARDWARE INITIALIZATION 6 3 Example 1 One 20091 6 3 Example 2 Two PCI 20091W 1 Boards 6 4 Example 3 PCI 20091W 1 with a PCI 20041C 3A Carrier 6 4 6 4 641 UTILITY INSTRUCTIONS 6 4 64 2 CONFIGURATION INSTRUCTIONS 6 5 6 4 3 READ INSTRUCTIONS 6 5 64 4 WRITE INSTRUCTIONS 6 5 6 4 5 BUFFER UIILITIES 6 5 646 HIGH SPEED ANALOG ACQUISITION INSTRUCTIONS 6 5 6 4 7 DMA DATA ACQUISITION AND CONTROL INSTRUCTIONS 6 6 Instruction Specifications 6 6 PCI 20091W High Speed Analog Input Board BUF DEC Decode Buffer Buffer Instruction 6 8 CNF DMA Configure DMA Configuration Instruction 6 9 CNF HS Configure High Speed Configuration Instruction 6 11 CNF RG Configure Rate Generator Configuration Instruction 6 13 DMA RUN Run DMA DMA Control Instruction 6 15 DMA STAT DMA Status DMA Control Instruction 6 16 DMA STOP Stop DMA DMA Control Instruction 6 18 ERR SYS System Error Utility Instruction 6 19 HS RUN RunHighSpeed Data Acquisition Instruction
34. 8 polarity eere 2 6 Rate Generator 2 7 read MSB data 2 7 Start of conversion eene 2 7 SUMMAFY 7 19 terminal count interrupt 2 9 voltage range 26 W11 through W13 4 4 27 W14 and 15 0 2 7 W16 through 18 4 444 2 2 9 2 7 2 7 2 10 W22 through 26 4 4 44 4 4 2 8 2 8 W4 and 5 2 8 W6 through 2 6 Jumpers W27 through W31 2 10 PCI 20091W 1 INDEX 5 PCI 20091W 1 High Speed Analog Input Board L Pacing sources 1 2 Page boundary 5 5 Language requirements 3 2 PATH DOS 3 10 Lethal voltages reist 7 2 20000 System License 3 2 compatibility 1 3 Linear buffers 5 5 200265 Software Drivers 3 1 Loading the software 7 7 4 3 8 compatibility with PCI 20091W 1 1 3 3 12 200265 Software Drives Lock up of computer description aciei re RARE RISE 1 2 high speed data acquisition 4 2 200275 high speed modes
35. CHN 0 78 HSCHNS 1 4 HSCHNS 2 79 HSCHNS 4 7 HSCHNS 5 80 CALLS ABSOLUTE PAC TYPE PAC CHN MODE TR TYPE TR CHN HSCHNS 1 CNF HS 81 ErrorRoutine Error found during CNF HS 5 HSCHNS 3 6 82 PRINT Done 82 CONFIGURE THE RATE GENERATOR PACER FREQUENCY 87 PRINT Configuring Rate Generator 3 88 RGCHN 0 89 1 1000 90 COUNT2 2 91 M 2 92 CALLS ABSOLUTE RGCHN COUNT1 COUNT2 MODE CNF RG 93 ErrorRoutine Error found during CNF RG 94 55 PRINT Done 21 START THE HIGH SPEED ACQUISITION 99 PRINT 100 PRINT Ready to perform High Speed Acquisition Press to start 3 102 DO 103 K INKEYS 104 LOOP WHILE K 1 106 PRINT 107 108 IF lt gt AND K lt gt THEN High Speed Acquisition cancelled ID END IF 113 PRINT Start High Speed Acquisition 114 PASS 20 115 DIM DARRAY 80 116 SEGMNT 0 117 5 ABSOLUTE PASS DARRAY 1 SEGMNT HS RUN 118 ErrorRoutine Error found during HS RUN 119 121 PRINT Done 101 DISPLAY THE COLLECTED DATA 124 PRINT Channel 125 PRINT Pass 126 127 FOR J 1 TO 4 128 PRINT HSCHNS J 129 NEXT J 130 131 PRINT 132 PRINT 133 134 FOR I 1 TO PASS n PRINT USING Me T3 137 FOR J 1 TO 4 138 FDATA 4095 DARRAY 4 I 1 J 4096 20 10 139 PRINT USING FDATA 140 NEXT J 141 PRINT 142 NEXT I 143
36. CONFIGURATION INSTRUCTIONS CNF RG Configure Rate Generator Configures the rate generator SYNTAX CALLS ABSOLUTE CHN COUNT1 COUNT2 MODE CNERG 6 4 3 READ INSTRUCTIONS READ CH Read Channel Reads a value from a channel of any appropriate type SYNTAX CALLS ABSOLUTE IO TYPE CHN STOR READ CH 6 4 4 WRITE INSTRUCTIONS WRITE CH Write Channel Writes a value to a channel of any appropriate type SYNTAX CALLS ABSOLUTE IO TYPE VALU WRITE CH 6 4 5 BUFFER UTILITIES BUF DEC Decode Buffer Decodes and returns the specified number of data units to the user s array SYNTAX CALLS ABSOLUTE COUNT DARRAY 1 XCOUNT BUEDEC 6 4 6 HIGH SPEED ANALOG ACQUISITION INSTRUCTIONS CNF HS Configure High Speed Configures system for high speed analog acquisition SYNTAX CALLS ABSOLUTE PAC TYPE PAC CHN MODE TR TYPE TR CHN AI CHNS 1 CNEHS PCT 20091W 1 6 5 PCI 20091W 1 High Speed Analog Input Board HS RUN Run High Speed Executes a high speed analog acquisition operation SYNTAX CALLS ABSOLUTE PASS DARRAY 1 SEGMNT HS RUN 6 4 7 DMA DATA ACQUISITION AND CONTROL INSTRUCTIONS CNF DMA Configure DMA Sets up a general DMA channel list SYNTAX CALLS ABSOLUTE PAC TYPE PAC CHN MODE TR TYPE TR CHN TYPES 1 CHNS 1 CNT CNEDMA DMA RUN Run DMA Executes a DMA controlled data acquisition or output process SYNTAX CALLS ABSOLUTE CLUSTERS DELAY DMA RUN DMA STAT DMA Status Returns the
37. DMA Mode 3 the DMA process starts transferring data to the host computer on a software command and continues to do so until a specified trigger event is received Then the DMA process continues for a specified number of data acquisi 5 2 PCI 20091W 1 Chapter 5 DMA eee LM tions and stops Only the latest data are stored in the buffer earlier data is overwritten after the data buffer has been filled once This DMA Mode can leave both pretrigger and posttrigger data in the buffer The location of the trigger point in the buffer may be calculated by counting back from the end of the buffer by the length of the programmed delay All data before the trigger point is pretrigger and all data after this point is posttrigger The PCI 200925 1 Software Drivers always put the oldest data in the beginning of the buffer Pr OCDE ae eee ee ee 5 4 DMA Mode 4 Start on Command Stop on Command DMA mode 4 is a continuous DMA process The DMA process is started on com puter command and Analog Input data from the PCI 20091W begins filling the buffer When the end of the buffer is reached the computer s DMA controller resets to the beginning of the buffer and begins overwriting old data with new The process stops on computer command leaving only the most recent samples in memory The number of samples collected depends on the size of the buffer used LL ee _
38. Drivers operate to ac complish this type of data acquisition Section 4 3 gives high speed data acquisition programming guidelines section 4 4 describes the High Speed data acquisition mode Many applications require the acquisition of a high speed snapshot of analog data The snapshot may be initiated by some sort of trigger after which the analog signals are sampled at accurately timed intervals The PCI 20091W 1 is very well suited to applications of this kind You may select one of two time base signals and which channels to read Acquisition rates of up to 89 000 samples per second may be achieved using high speed acquisition with the PCI 20091W 1 The 200275 Software Drivers support three different high speed analog data acquisition modes with the PCI 20091W 1 Board As a subset of the 200275 Software Drivers the 200925 Software Drivers support High Speed Mode 4 This mode provides the highest speed acquisition with hardware controlled channel selection and conversion timing High speed modes supported by PCI 20027S are Mode 1 with software controlled timing and more flexible timing options and Mode 3 with software controlled channel selection High Speed analog data acquisition can be performed with a single PCI 20091W 1 Board and the PCI 20092S 1 Software Drivers PCI 20091W 1 must be con figured to provide a source of clock signals to pace the acquisition and may be configured to provide a gate
39. FRAMES PER CLUSTER 2 BOARD SEG amp HCDCO BOARD SEGMENT ADDRESS 52 AI T PACER TYPE AND CHANNEL e PAC CHN 0 55 0 TRIGGER AND CHANNEL NO TRIGGER 35 TRIG CHN 0 58 DMA MODE 2 DMA MODE FOR THE ACQUISITION 22 TERMINAL COUNT 20 DESIRED NUMBER OF CLUSTERS 61 DEFINE THE DMA CHANNEL AND LISTS THESE LISTS SPECIFY THE 62 CHANNELS WHICH WILL BE READ BY DMA IN EACH CLUSTER THE 1 ELEMENT 63 IN THE CHANNELS LIST IS A MARKER OF THE END OF THE LIST 65 DIM TYPES 4 66 DIM CHNS 5 68 5 1 AI T CHNS 1 4 69 TYPES 2 AIX T CHNS 2 5 70 TYPES 3 AIX T CHNS 3 6 71 TYPES 4 1 CHNS 4 7 14 CHNS 5 1 DEFINE RATE GENERATOR PARAMETERS 76 COUNTI 2400 RATE GENERATOR COUNTS 77 COUNT2 2 78 RG CHN 0 RATE GENERATOR CHANNEL 79 RG MODE 2 RATE GENERATOR MODE 80 RG ENABLE 1 RATE GENERATOR ENABLE VALUE 81 e dede de dee dee 83 INITIALIZE THE PCI 20092S 1 SYSTEM THIS CALL MUST BE MADE PRIOR 84 CALLING ANY OTHER PCI 20092S 1 INSTRUCTION 85 86 PRINT 51 PRINT Begin PCI 20092S 1 Sample Program 5 dd CALLS ABSOLUTE SYSINIT PCI 20091W A 13 Appendix PCI 20092S Sample Programs SEGMT DEFINED BELOW IS THE BASE ADDRESS OF THE PCI 20091 1 WE USE amp H
40. IT IS A GOOD IDEA 66 TO LEAVE A FEW ERR SYS CALLS IN A FINISHED PROGRAM TO MONITOR THE STATUS OF THE SYSTEM a ErrorCheck Error found during INIT 71 CONFIGURE THE SYSTEM FOR DMA INPUT USE THE END OF CONVERT SIGNAL 72 FROM THE ANALOG INPUT SECTION AS THE PACER TRIGGER OFF OF THE 73 XSYNC INPUT TO THE BOARD CONNECTOR P3 PIN 5 RUN IN DMA MODE 3 AND ACQUIRE ANALOG CHANNELS 4 5 6 AND 7 A 10 PCI 20091W Sample Program 4 76 PRINT Configuring DMA 77 DIM CHNS 5 DIM TYPES 4 78 PAC TYPE AI T 79 PAC CHN 0 80 DMODE 3 81 XSYNC T 52 TR CHN 0 8 84 TYPES 1 CHNS 1 4 85 TYPES 2 AIX T CHNS 2 5 86 TYPES 3 AIX T CHNS 3 6 87 TYPES 4 AIX T CHNS 4 7 88 CHNS 5 1 END OF LIST 89 90 LENGTH 0 tipa Es ABSOLUTE PAC TYPE PAC CHN DMODE TR TYPE TR CHN TYPES 1 CHNS 1 LENGTH 32 ErrorCheck Error found during CNF DMA 24 PRINT Done 96 CONFIGURE THE RATE GENERATOR FREQUENCY THE RATE GENERATOR OUTPUT 97 SIGNAL WILL START ANALOG TO DIGITAL CONVERSIONS WHEN EACH 98 CONVERSION IS COMPLETE THE PCI 20091W 1 WILL GENERATE THE DMA 125 PACER SIGNAL END OF CONVERT 101 COUNT1 100 102 COUNT2 2 104 RG CHN 0 105 PRINT Configuring Rate Generator 106 CALLS ABSOLUTE RG CHN COUNT1 COUNT2 RMODE CNF RG 107 ErrorCheck Error found during CNF RG 109 PRINT Done 110 at UP THE DMA ACQU
41. OFTEN 61 POSSIBLY AFTER EVERY CALL TO THE PCI 20092S 1 IS GOOD IDEA 62 LEAVE A FEW ERR SYS CALLS IN A FINISHED PROGRAM TO MONITOR THE 22 STATUS OF THE SYSTEM 6 65 ErrorRoutine Error found during INIT 67 CONFIGURE RATE GENERATOR CHANNEL O WITH COUNTER ONE SET TO 4 68 COUNTER TWO SET TO 2 AND MODE 2 69 70 CHN 0 71 4 72 CNT2 2 73 MODE 2 74 CALLS ABSOLUTE CHN CNT1 CNT2 MODE CNF RG 75 ErrorRoutine Error found during CNF RG 77 ALTERNATELY ENABLE AND DISABLE THE RATE GENERATOR 79 PRINT The Rate Generator has been configured to generate a square wave 80 PRINT The program will now enable or disable the Rate Generator whenever 51 RINT a key is pressed Press Q to quit 84 ENABLE 1 85 DISABLE O 86 ENABLE 87 88 DO 20 CALLS ABSOLUTE RG T CHN RGDATA WRITE CH 91 IF RGDATA ENABLE THEN 92 ErrorRoutine Error found during WRITE CH enable 93 PRINT ON 94 RGDATA DISABLE 95 ELSE 96 ErrorRoutine Error found during WRITE CH disable 97 PRINT off 98 RGDATA ENABLE 100 END IF 102 WAIT FOR A KEY THEN CHANGE THE RATE GENERATOR STATE 103 DO 104 INKEYS 702 LOOP WHILE 5 108 LOOP WHILE K lt gt 0 AND K lt gt q 109 PRINT 110 PRINT Done 111 112 END 113 114 DEFSNG A E G Z 115 SUB ErrorRoutine ErrorString AS STRING 116 i DEFINE A GENERAL PURPOSE ERROR PROCESSING ROUTINE 119 ER
42. Speed Analog Input Board 7 4 4 REGISTER USE A detailed description of the use of each register follows offsets given in hex Offset 000 Board ID Interrupt Status Mode READ Board ID bits 0 7 Reading this register returns one of the following ID codes which can be inter preted as follows ID code DMA Terminal Count Extended enabled interrupt D7 YES NO NO D3 NO NO NO D1 YES YES NO C4 YES NO YES C5 YES YES YES The first three ID codes are equivalent to a PCI 20041C 3A Carrier with a Module in slot 1 The extended IDs C4 Hex and C5 Hex are incompatible with older versions of our software drivers the PCI 20046S PCI 20047S and older versions of the 200925 Software Drivers The different IDs are selected by jumpers as shown in table 7 4 TABLE 7 4 Control Jumper Settings 7 6 ID Code Jumper IN Jumpers OUT DMA without terminal count W16 W17 W18 Non DMA mode W16 W17 W18 DMA with terminal count W17 W16 W18 Extended without terminal count W16 W17 W18 Extended with terminal count W18 W16 W17 Factory configuration WRITE Interrupt Status Mode bit 7 Writing an appropriate value to bit 7 of this register sets the interrupt mode A value of 80 Hex bit 7 set sets latched interrupt mode A value of 0 Hex bit 7 clear sets pass through interrupt mode Bits 0 through 6 are not used bit 7 0 pass through 1 latched When the Interrupt Mode is set for latched operation t
43. TABLE 5V DGND 15 15 AGND SHT 1L u gt us u z vo ERSTES E us se 5 a s LECT Em v jw us zo 2 DELAY vf a fa lt MSB_EN cs Je uzo TITLE PLOT DATE SCH HIGH SPEED ANALOG INPUT BOARD 17 JUN 91 PRODUCT NO VOL LABEL 9235008 1 1 DOCUMENT REV SHEET 91W 1 FILE 92350080 5 92 35008 SCH D 14 4
44. THEN PRINT Aborted CALLS ABSOLUTE CLUSTERS DMA STOP 14 PCI 20091W Sample Program 5 177 ERR CODE 0 178 CALLS ABSOLUTE ERR CODE ERR SYS 179 IF ERR CODE lt gt 0 THEN 180 PRINT Error found during DMA STOP ERR CODE continuing 181 END IF 182 ELSE 183 PRINT Done 184 END IF 185 157 THE ACQUISITION IS NOW COMPLETE 188 PRINT 189 PRINT CLUSTERS clusters of data are available 190 PRINT Press any character to display next cluster Q to quit 191 122 PRINT THE DATA THE BUFFER 194 DIM CLUST 4 195 196 PRINT 197 PRINT Channel 196 PRINT Cluster 200 FOR J 1 TO 4 201 PRINT USING 1 CHNS J 202 NEXT J 203 204 PRINT 205 DEC CLUSTS 1 206 207 FOR I 1 TO CLUSTERS 0 209 USE BUF DEC TO READ AND PRINT EACH CLUSTER ELEMENT 210 gt PRE DEFINE THE RETURNED VALUE NUM DECODED 211 212 NUM DECODED 0 213 CALLS ABSOLUTE DEC CLUSTS CLUST 1 NUM DECODED BUF DEC AT ErrorCheck Error found while decoding buffer data 216 IF NUM DECODED DEC CLUSTS THEN 217 PRINT Internal Error Did not decode full cluster 218 END 212 END IF 221 PRINT THE DATA IN ALL FOUR FRAMES OF THE CLUSTER FIELD BY FIELD 225 PRINT USING 224 FOR J 1 TO 4 225 FDATA 20 4096 4095 CLUST J 10 226 PRINT USING FDATA 227 NEXT J 228 229 PRINT 230 231 DO 232 K INKEYS 224 LOOP WHILE 332 IF K Q
45. TYPE TR CHN ALCHNS 1 CNEHS 1 PAC TYPE The V O type of the pacing signal used as the time base for high speed acquisition This may be the standard I O type of RG T or the external start convert signal may be used by specifying PAC TYPE of 0 The pacer must be independently configured it will be armed or enabled as necessary by HS RUN Run High Speed 2 PAC CHN Channel number of the pacing signal 3 MODE High speed acquisition mode must be 4 4 TR TYPE Must be 0 5 TR CHN Must be 0 6 ALCHNS List of analog input channel numbers contained array with the final array value being 1 to indicate the end of the list This instruction only supports analog channels on a single PCI 20091W 1 Board See the discussion below for legal channel list for mat High Speed Mode 4 uses hardware controlled timing to maximize data throughput to the user s array The A D converter on the PCI 20091W 1 gets its start conversion signal from the onboard rate gener ator or the External Start Convert During data acquisition the software polls the End Of Convert signal When this signal is detected the current channel is read and the data is stored The software then resumes polling for the end of convert signal The Software Drivers use the information in the array AI CHNS to set up the frame map and determine the number of frames per cluster The channel list passed to CNEHS must follow certain conventions because of
46. WILL STOP WHEN THE TERMINAL COUNT IS REACHED PRINT Configuring DMA PRE DEFINE RETURNED VALUE BYTES PER CLUSTER BYTES PER CLUSTER 0 CALLS ABSOLUTE PAC CHN DMA MODE TRIG TYPE TRIG CHN TYPES 1 CHNS 1 9 v e v CNF DMA ErrorCheck Error found during call to CNF DMA PRINT Done ACQUIRE DATA CALL DMA RUN TO ENABLE THE DMA CONTROLLER AND START THE MODE 2 ACQUISITION AND CALL WRITE CH TO ENABLE THE RATE GENERATOR EN THE DMA RUN CALL RETURNS CALL THE DMA STAT STATUS ROUTINE TO DETERMINE WHEN THE ACQUISITION IS COMPLETE RUN DMA ACQUISITION IN MODE 2 THE SECOND PARAMETER DELAY IS IGNORED MODE 2 DELAY oe acquisition CALLS ABSOLUTE TERMINAL COUNT DELAY DMA RUN ErrorCheck Error found on call to DMA RUN ENABLE RATE GENERATOR TO SEND START CONVERT SIGNALS PRINT Starting rate generator siatt Convert Signa sees ms CALLS ABSOLUTE RG T G CHN RG ENABLE WRITE CH ErrorCheck Error encountered during WRITE CH to start RG PRINT Done WAIT FOR THE DMA PROCESS TO COMPLETE PRE DEFINE THE RETURNED VALUES STAT AND CLUSTERS STAT 0 CLUSTERS 0 PRINT PRINT DMA running Press key to abort PRINT Waiting for DMA process to complete DO CALLS ABSOLUTE CLUSTERS STAT DMA STAT ErrorCheck Error in call to DMA STAT K INKEYS LOOP WHILE STAT 2 AND K IF STAT 2
47. a 0 if the section is to be disabled Step 2 Write the enable byte to the DMA mode register BYTE 002 This register cannot be read so you must store the enable byte in program memory 7 5 6 DELAY COUNTER READ PROCEDURE This procedure latches and reads the current counter status and count Other read back options are available and the counter can also be read without latching the count Step 1 Set up the read back control byte To read the counter status and count this byte should be C8H The count and status can optionally be read separately Step 2 Write the control byte to the appropriate control register BYTE BA 043H This latches the status and the count which will be the next three bytes read from the count register Step 3 Read the status byte from the count register BYTE 042 Step 4 Read the count bytes from the count register Read first the low byte and then the high byte of the count Both bytes are read from the same register this is nota WORD operation If no pulses have been received at the counter clock input since the initial count was programmed bit 6 of the status byte will be 1 and the count read will be indeterminate After one pulse is received the count read will be the initial count that was programmed Thereafter the initial count will be decremented for each pulse received The count is decremented by one or two depending on the operating mode PCI 20091W 1
48. any command line you would type at the DOS prompt It may invoke any batch file or any executable EXE or COM file Command line arguments may be included Note You must type the double quotes or an acceptable substitute around the text string Acceptable substitutes are single quotes X text or square brackets X text The characters that you choose should be ones that do not appear within the text string If the command line contains DOS pipe or redirection characters lt or gt you must use double quotes The X switch is useful for applications that are designed to run automatically If PCI_92S EXE is invoked from a batch file it should appear on the last line of that batch file You can then continue batch processing by specifying a second batch file with the X switch TABLE 31 Summary of PCI 925 Switches Switch Description Na Allows the user to specify an interrupt vector other than the default value of Hex 60 IG Bypasses user confirmation Useful for batch file operations Bb Allocates a DMA buffer b Kbytes in length Allowable values for b are 1 to 64 Kbytes X text Specifies a command line to be executed by 925 3 7 4 EXAMPLES OF LOADING THE SOFTWARE DRIVERS If you are loading PCI 92S EXE from a batch file you must put the command PCI 928 switches as the last line of the batch file Lines after the 200925 1 command will not be processed until PCI 925 exits
49. automatic 1 2 DEFINT QuickBASIC command 67 high speed data acquisition 4 2 Delay counter Channel sequencing configuring 2 10 and clusters 5 6 enable or 7 15 Chapter overview initialization 7 14 chapter 11 programming procedure 7 14 7 15 chapter 2 1 read 2 4 7 15 3 1 3 1 7 9 4 1 status 711 5 1 Device drivers 6 1 software performance 3 10 ur PRO EP RUNE 7 1 Digital connector 2 12 Circular 5 5 DIM QuickBASIC command 6 7 data frames and clusters 5 6 Disable procedure Clock delay 7 15 rate 4 44 4 2 10 rate 2 7 16 Clusters 5 5 DISKCOMP DOS 3 3 circular 5 6 DISKCOPY 3 3 CNEDMA instruction 6 6 6 9 DMA CNEHS instruction 6 11 6 20 5 4 CN
50. event has been recorded This deter mines the DMA mode to be used A signal used to stop the DMA process is called the DMA Trigger Event 4 What signal is to be used to pace the transfer of data The PCI 20091W 1 Board uses the A D converter s End of Conversion signal to control the DMA process This signal is the DMA Source Event The A D conversion rate is in turn determined by the signal connected to the Start Convert input when you configure your hardware system 5 What signals must be connected in order to ensure that all components of the system function automatically during the data acquisition Since DMA is a hardware technique certain jumpers must be installed on the PCI 20091W 1 in order to make the proper signals appear in the right places Refer to chapter 2 for jumper configuration details The answers to these questions provide the PCI 20091W 1 hardware with the parameters it requires for a successful DMA operation Y 4 4 AA A 5 2 DMA Mode 2 Start on Command Stop on Terminal Count DMA Mode 2 is a fixed period data acquisition mode The DMA process starts with a software command and terminates after a specified amount of data has been transferred to the host computer Use this mode to sample continuous input signals for a definite length of time EE ee a s 5 3 DMA Mode 3 Start on Command Stop on Trigger after Delay In
51. high speed data acquisition are listed and commented in table 4 1 in the order you would call each instruction Section 4 4 describes High Speed Mode 4 chapter 6 describes each individual instruction in greater detail Not all the instructions given in table 4 1 will be used for every data acquisition con figuration Be sure to refer to the entry for each instruction in chapter 6 for full details on the instruction arguments TABLE 4 1 High Speed Programming Instructions CNERG If the PCI 20091W 1 rate generator is used as a time base use this instruction to set up the rate generator channel CNERG if used must be called once before the first call to HS RUN This instruction is not required if you are using the external start convert input as the acquisition pacer CNF HS Use this instruction to specify the time base of the acquisition High Speed Mode 4 and the list of analog channels that will be read during the acquisition CNEHS must be called once before the first call to HS RUN HS RUN Use this instruction to perform the high speed data acquisition Specify the number of passes through the channel list and the address of the array where the data will be stored ERR SYS If an error occurs this instruction will provide information as to exactly where in the program the error occurred and the nature of the error We recommend that you call this instruction after every call 4 3 1 TIMING If the onboard rate generator is used for t
52. list always has I O type ALT analog input If the list contains more than one channel subsequent channels have type AIX T This is a special I O type not used by the READ CH Read Channel instruction One pass through the complete list of AI T and AIX T channels results in a cluster of data frames each data frame containing a different analog channel Thatis the first data frame in a cluster contains data from the AI T channel each successive data frame in the cluster contains data from the next associated AIX T channel in the 5 6 PC1 20091W 1 Chapter 5 DMA frame map The software ensures that the DMA buffer contains only complete clusters of data frames and the BUEDEC Decode Buffer instruction returns data in complete clusters clei 5 10 DMA INSTRUCTIONS The following sections briefly describe the instructions required for DMA Al though all these instructions are not required for all applications the instructions required for a particular application should be executed in the order indicated 5 10 1 DMA INITIALIZATION INSTRUCTIONS CNEDMA Configure DMA Call this instruction to initialize pacer source DMA mode trigger source and frame map 5 10 2 CONTROL INITIALIZATION INSTRUCTIONS CNERG Configure Rate Generator Configure rate generator if used to start conversion prior to running DMA 5 10 3 DMA EXECUTION INSTRUCTIONS DMA RUN Run DMA Start the DMA p
53. more than one of these jumpers should be installed Factory configuration for these jumpers is OUT TABLE 2 5 Interrupt Level Jumper Settings Interrupt Jumpers IN Jumpers OTU Level None1 W22 W23 W24 W25 W26 W32 2 W32 W22 W23 W24 W25 W26 3 W22 W23 W24 W25 W26 W32 4 W23 W22 W24 W25 W26 W32 5 W24 W22 W23 W25 W26 W32 6 W25 W22 W23 W24 W26 W32 7 W26 W22 W23 W24 W25 W32 1 Factory configuration 2 8 PCI 20091W 1 Chapter 2 Hardware Configuration ir SON S 2 7 DMA Contro The PCI 20091W 1 incorporates a DMA controller similar to the one used on the PCI 20041C 3A All DMA transfers are made to the PC computer s memory and are paced by the A D converter s end of conversion EOC signal The maximum DMA rate is determined by the PCI 20091W 1 Board s hardware capability as 89 000 samples sec Programming the Board for DMA data acquisition can be ac complished through use of the included PCI 20092S Software Drivers Information on programming the Board directly is contained in section 7 4 2 7 1 CAPABILITY AND INTERRUPT STATUS The DMA control and DMA terminal count interrupt capability of the PCI 20091W 1 Board are enabled by setting jumpers appropriately These jumpers also deter mine the ID code that will be read from the Board ID register Offset 000 Register offsets are described in chapter 7 Two jumper settings correspond to extended mode configuration
54. n Retry failed In any of these conditions the following will appear Errors detected code not installed If non fatal command line errors are detected the following messages may appear Extra characters on input line Input line errors ignored If the error is detected as the Software Drivers attempt to load the command processor COMMAND COM the following message will be displayed PCI 200928 Execute failed followed by one of these informative messages Invalid function File not found Memory allocation error or memory control blocks damaged Insufficient memory Incorrect segment Bad environment Bad format Undefined error In the case the error File not found a message similar to the following will appear PCI 20091W 1 3 9 PCI 20091W 1 High Speed Analog Input Board a ER Can t find C COMMAND COM Insert boot disk and press lt ENTER gt to retry Place your DOS diskette containing COMMAND COM in the drive you use to boot your system and press the lt ENTER gt key When the ENTER key is pressed the Software Drivers will try again to load the command processor If any other key is pressed the Software Drivers will exit 3 7 2 MEMORY RESIDENT PROGRAMS If you use memory resident programs also known as TSRs such as Borland s Sidekick or SuperKey or DOS external commands PRINT or MODE you should load these programs before you load the PCI 20092S 1 software If
55. per sonal computer interface between you and the PCI 20091W 1 High Speed Analog Input Board The 200925 1 Software Drivers are prebuilt subset of the PCI 200265 200275 Software Drivers As such they support the Microsoft QuickBASIC Language and most of the functions of your Board including a high speed data acquisition mode and DMA data acquisition modes The calls used in the PCI 200925 Software Drivers are identical to calls used in the PCI 20026S and 200275 Software Drivers The 200265 and 200275 Software Drivers offer greater capabilities in several areas They support other languages IBM Interpreted BASIC C and Turbo Pascal other hardware in the PCI 20000 System and a greater diver sity of the high speed and DMA data acquisition methods As an illustration of the simplicity of the 200925 1 Software Drivers consider the following example PCI 20091W 1 31 20091 1 High Speed Analog Input Board CALLS ABSOLUTE GAIN Z CHN RANGE CALLS ABSOLUTE AI T CHN STOR READ CH The above two program lines show calls which first configure prepare an analog input channel to read data and then read the analog input data from the specified channel These calls supported by the PCI 20092S 1 Software Drivers allow you to interface with the hardware in a straightforward and painless way The variable names we use in our program listings are arbi
56. rupts from an auxiliary device or intercept one or more system interrupts which may reduce the system performance For this reason you may wish to avoid using any unnecessary memory resident programs or device drivers when you are acquir ing data with PCI 20092S 1 3 10 PCI 20091W 1 Chapter 3 Software Installation 3 7 3 SWITCHES SWITCH V INTERRUPT VECTOR Interrupt vector 60 Hex is used to store the beginning address of the resident routines The switch V which is used when invoking PCI 925 determines the interrupt vector to be used in calling the Software Drivers This switch in the form Va where a is a variable may be used to specify an interrupt vector other than the default interrupt vector of 60 Hex PC DOS has reserved vectors 60 through 67 Hex for definition by the user If you specify any vector other than the default value of 60 Hex you must make sure that the vector will be recognized by your applications programs The method of accomplishing this is given in the section on creating application programs Note that in the PC interrupts are allocated four bytes so each interrupt vector is calculated to be at an address four times the interrupt number However if a is greater than FF Hex it is interpreted as an offset in Segment 0000 rather than as an interrupt vector and the automatic multiplication by 4 will not be performed For example V180 is equivalent to V60 You will only need t
57. sequencing capability of the Board If your application involves sampling more than one channel you must connect your input signals to channels N through 7 where N depends on the number of input signals You must enable automatic channel sequencing Refer to section 2 5 4 3 Programming Guidelines The instructions used for high speed data acquisition are listed and commented in table 4 1 in the order you would call each instruction Section 4 4 describes High Speed Mode 4 chapter 6 describes each individual instruction in greater detail Not all the instructions given in table 4 1 will be used for every data acquisition con figuration Be sure to refer to the entry for each instruction in chapter 6 for full details on the instruction arguments TABLE 4 1 High Speed Programming Instructions CNF RG If the PCI 20091W 1 rate generator is used as a time base use this instruction to set up the rate generator channel CNERG if used must be called once before the first call to HS RUN This instruction is not required if you are using the external start convert input as the acquisition pacer CNF HS Use this instruction to specify the time base of the acquisition High Speed Mode 4 and the list of analog channels that will be read during the acquisition CNEHS must be called once before the first call to HS RUN HS RUN Use this instruction to perform the high speed data acquisition Specify the number of passes through the channel list and
58. the address of the array where the data will be stored ERR SYS If an error occurs this instruction will provide information as to exactly where in the program the error occurred and the nature of the error We recommend that you call this instruction after every call 4 3 1 TIMING If the onboard rate generator is used for timing the data acquisition sampling rate is determined by the rate generator counts n1 and n2 in the CNERG instruction 42 PCI 20091W 1 PCI 20091W 1 High Speed Analog Input Board You may provide a signal to the Conversion Inhibit input in order to trigger data acquisition to begin following a desired event When the the Conversion Inhibit input goes high data acquisition will commence If analog conversions fail to take place either because Conversion Inhibit remains low because pacing signals are absent or because the pacing signals are not reaching the A D converter the computer will effectively be locked up necessitating a system reset If your application involves sampling a single channel you can either use channel 7 for your input signal or disable the automatic channel sequencing capability of the Board If your application involves sampling more than one channel you must connect your input signals to channels N through 7 where N depends on the number of input signals You must enable automatic channel sequencing Refer to section 2 5 4 3 Programming Guidelines The instructions used for
59. the way the PCI 20091W 1 hardware operates If the PCI 20091W 1 is configured with automatic channel advance disabled the channel list may consist of any single analog channel If the PCI 20091W 1 is configured with automatic channel advance enabled the channel list may consist of a channel sequence in numerical order beginning with where lt 7 and ending with 7 PCI 20091W 1 6 11 PCI 20091W 1 High Speed Analog Input Board Refer to the examples of acceptable and unacceptable channel lists given under the CNEDMA Configure DMA instruction 6 12 20091 1 Chapter 6 Software Technical Reference CNF RG Configure Rate Generator Configuration Instruction PURPOSE Configure a Rate Generator channel with two 16 bit initial counts and an Intel 8254 Mode code SYNTAX CALLS ABSOLUTE 1 COUNT2 MODE ARGUMENTS 1 Rate Generator channel to configure 2 COUNT1 Count data word LSW for low order section of Rate Generator A count of 1 is illegal in Modes 2 3 8 and 9 3 COUNT2 Count data word MSW for high order section of Rate Generator A count of 1 is illegal in Modes 2 3 8 and 9 4 MODE Intel 8254 Mode code 0 through 5 to select 16 bit Modes 6 through 11 to select corresponding 8 bit Modes Only Modes 2 3 8 and 9 are true rate generator Modes REMARKS This instruction configures a specified rate generator channel writ ing the control wo
60. to use three subroutines to build display windows and graph data in them The subroutine InitWindow sets up the coordinates of nine windows four quarter screen windows four half screen windows and a full screen window These win dows allow you to display up to four data sets simultaneously or to use larger windows for one or two data sets The subroutine PlotWindow draws a graph box with tic marks for the specified window The subroutine PlotData scales a data set calls PlotWindow to draw a box labels the axes and plots the data You can generate simple graphical displays of your data by incorporating these subroutines or modified versions of them into your application programs The comments in GRAPH BAS will show you how to use the subroutines 4 4 PCI 20091W Sample Program 1 Sample Program 1 1 3 ve dede se de de ve ve ve ee ve ve dese de de ve e de vede de dede de de vede dede dede dr ede dede de de dede ede dee de de ede dedo dee dede 2 4 PROGRAM SAMPLE PROGRAM 1 3 VERSION 1 1 409 5 re LANGUAGE BASIC 6 9 TRANSLATOR MICROSOFT QUICK BASIC VERSION 4 0 7 3 ede de vede de se dede defe de de de de de de de de de dede de de de de de de de e de de de Je dede de de de dede de dede de dede dede de dede dede de de deve dede dede de fee dee 8 9 DECLARE SUB ErrorRoutine ErrorString AS STRING 10 11 gt 5 PROGRA
61. you load memory resident programs after loading 200925 1 be sure to unload them in the order they were loaded before unloading PCI 20092S 1 Some memory resident programs including PRINT and MODE cannot be unloaded If you use DOS environment commands such as PATH PROMPT and SET you should give these commands before loading any memory resident programs other wise you may get the DOS error message out of environment space The environ ment size can be increased for DOS versions 3 2 and later consult your DOS manuals if you need to do this The precautions noted above for memory resident programs also apply if you use a windowing program such as TopView In addition you should never have two applications both of which access the same copy of PCI 20092S 1 routines running simultaneously Running 200925 1 in conjunction with a windowing program is not recommended and is not guaranteed to work If you use a shell program to replace or supplement the DOS command interpreter you may wish to load the Software Drivers before you enter the shell program If you load the Software Drivers from the shell program you will not return to the shell until you exit the Software Drivers Device Drivers are a special type of memory resident program which are loaded automatically during your computer startup sequence These files usually have the extension SYS Some device drivers and memory resident programs enable inter
62. 0000 0000 Binary A19 AO EXAMPLE 4 Memory Address 0000 LCS Address CDCOO Hex 1100 1101 1100 0000 0000 Binary A19 PCI 20091W 855M180E UM Fig 2 2 Examples of setting addresses 24 PCI 20091W 1 Chapter 2 Hardware Configuration EO 1 bese LU MED lm 18 me J R Fig 2 3 Jumper Locations PCI 20091W 1 PCI 20091W 1 High Speed Analog Input Board 2 3 Analog Input Voltage Ranges An Analog to Digital A D converter on your Board converts the analog signal on the selected channel into digital data to be transferred to the computer There are five jumper selectable A D range polarity settings Your Board has been set at the factory for the analog input voltage range of 10 volts However you can easily change this setting by changing the jumpers as shown in table 2 1 We recommend that you use the smallest range that you think will fit your signal The digital code for the output data is complementary binary for the unipolar ranges 0 to 5 volt and 0 to 10 volt and complementary offset binary for the bipolar ranges 2 5 5 and 10 volts TABLE 2 1 Analog Input Voltage Range Jumper Settings Jumper Settings Voltage Jumpers IN Jumpers OUT 2 5 W7 W9 W10 W6 W8 5V W7 W9 W6 W8 W10 10v W6 W9 W7 W8 W10 0 to 5V W7 W8 W10 W6 W9 0 to 10V W7 W8 W6 W9 W10
63. 091W 1 High Speed Analog Input Board BUF DEC Decode Buffer Buffer Instruction PURPOSE SYNTAX ARGUMENTS REMARKS Decodes and returns the specified number of clusters from the buffer to the user s array starting at the current location pointer The loca tion pointer is updated to the end of the data decoded CALLS ABSOLUTE COUNT DARRAY 1 XCOUNT BUEDEC 1 COUNT Number of clusters to return 2 DARRAY 1 Array for returned data 3 XCOUNT Number of data units actually transferred Be sure to predefine this argument by setting it equal to 0 prior to this call This instruction decodes COUNT clusters into the user s array DARRAY starting at the current location in the buffer 12 bit analog data is returned as an integer between 0 and 4095 in complementary binary or complementary offset binary format right justified and zero filled If DMA is in progress and at least one cluster has been acquired the most recent cluster will be returned If no complete clusters have been read XCOUNT returns 0 and no data is returned 6 8 PCI 20091W 1 Chapter 6 Software Technical Reference CNF DMA Configure DMA Configuration Instruction PURPOSE SYNTAX ARGUMENTS REMARKS PCI 20091W 1 Prepare for DMA data acquisition Set up general DMA channel list Supports DMA Modes 2 and 3 CALLS ABSOLUTE PAC TYPE PAC CHN MODE TR TYPE TR CHN TYPES 1 CHNS 1 CNT CNEDMA 1 PAC TYP
64. 144 END 145 146 DEFSNG A E G Z 147 SUB ErrorRoutine ErrorString AS STRING 149 DEFINE GENERAL PURPOSE ERROR PROCESSING ROUTINE 132 CALLS ABSOLUTE ERROR CODEZ ERR SYS 134 IF ERROR CODEZ lt gt 0 THEN 122 PRINT ErrorString ERROR CODEZ PCI 20091W Ag Appendix 200925 Sample Programs 157 END 158 159 END IF 160 161 END SUB Sample Program 4 1 9 dee e ede de ede dede de dece dede de dede de de de dee 2 PROGRAM NAME SAMPLE PROGRAM 4 30 VERSION 1 1 4 9 50 LANGUAGE BASIC 6 TRANSLATOR MICROSOFT QUICK BASIC VERSION 4 0 7 9 dedededese dese de ee EEK de de de de de de de dece je dee de de de de fede dede Ve de de de dede dye de dede de de ye de dee dede he 8 4 DECLARE SUB ErrorCheck ErrorString AS STRING 1 11 THIS PROGRAM DEMONSTRATES THE DMA INPUT FEATURE OF THE PCI 20091W 1 12 RUNNING IN DMA MODE 3 WITH PCI 20010T 1 WHEN 200925 1 IS 13 LOADED USE 1 TO LIMIT THE DMA BUFFER 1024 BYTES OTHERWISE THE 14 AMOUNT DATA TAKEN MAY BE UNWIELDY THE PROGRAM USES THE FOLLOWING 15 PCI 200928 1 INSTRUCTIONS 17 SYSINIT INIT ERR SYS 18 CNF DMA CNF RG WRITE CH DMA RUN 19 DMA STAT BUF DEC DMA STOP 2 FOLLOWING HARDWARE CONFIGURATION IS REQUIRED 23 2 24 5 PCI 20091W 1 25
65. 2 0 Rate Generator PCI 20091W 1 1 1 Rate Generator PCI 20091W 1 2 Example 3 PCI 20091W 1 with a PCI 20041C 3A Carrier If you have a PCI 20091W 1 Board in the same system as you have a PCI 20041C 3A Carrier the channels might be assigned as follows assuming that you INIT the Carrier first then the Board Example 3 Channel Configuration Channel Numbers Channel Types Description 0 Rate Generator 20041 0 31 Digital 1 20041 0 7 Analog Inputs 20091 1 1 Rate Generator 20091 1 6 4 Software Calls This section provides a complete reference for the use of the 200925 1 Software Drivers system The instruction summary below contains a quick reference listing of the entire set of instructions available accompanied by a brief explanatory description Note that each instruction is listed by its actual call name then by a more explanatory name and definition Section 6 5 the Instruction Specifications provides a detailed description of each instruction 6 4 1 UTILITY INSTRUCTIONS ERR SYS System Error Returns the latest error code and clears the error register SYNTAX CALLS ABSOLUTE ERROR CODE ERR SYS 6 4 20091 1 Chapter 6 Software Technical Reference INIT Initialize Initializes the system hardware SYNTAX CALLS ABSOLUTE SEGMT INIT SYSINIT System Initialize Initializes the system software SYNTAX CALLS ABSOLUTE SYSINIT 6 4 2
66. 3 6 4 WEE 6 5 write CANNEL 5 7 write channel caccia 6 24 WRITE CH 3 5 5 7 6 24 Interrupt terminal count enable 2 9 Interrupt level factory configuration 2 8 2 8 SelecHng 2 8 Interrupt Request GeBnitlon a dif Interrupt source factory configuration 2 8 2 8 selecting 2 8 Interrupt vector setting in PCIHEADQ BAS 3 11 6 1 setting with 3 11 used by expanded memory 3 11 Interrupt Status clear register T 7 7 Interrupt Status mode M 7 6 Interrupt Status mode register 7 6 Interrupt Status register 7 12 Interrupts capability eere 1 2 IRQO definition PD 2 7 J Jumpers Board 7 6 CAUTION 2 1 DMA channel eee 2 9 DMA channel selection 2 10 DMA configuration 5 2 DMA control 2 9 DMA 2 9 terminal count interrupt 2 8 extended mode 2 9 external start convert 2 7 IDET E 2 9 interrupt level 2 8 interrupt source 2
67. 3 C22 1213 oND sv 53 T 6 8 25V D R B R 1 18 AO jaz 155 16 BAI T DMA IN 1 gt rS 1 27 NT MODE lt YA pa eas ANOO Fi ee ee 1 lt du 9 yA SR lt 1 26 lt 1 2 2 212 5 em 258 1 811 o 9 2 3 2Y3 BAZ 19 d 26 U19 9 745244 BRD BWR R BIZAS DO 8 BDO Bb Al_ DECODER 1 n O1 7 h 5 pi A EX ng RE HA 55 EY Pig 0 5 4 04 IS 05 p ICHN SEL S EIAS 1 6 F4 19 IR BDEN 1 TW 111 BWR 12 900 049 3H DR z SHI 2 lt BDEN SYS ML IL Pi A25 AS 12 do 11 2 BD do 2 AS 2 10 Lo 1XBA2 230 4 014 BAG 14 6 470 2 ae Dig BA8 es 8 9 1 0 AMICUS 216 BAS BD5 16 4 179 4 s gt RESET DRV 7 D 18 BRST BD7 18 d 170 6 C36 9 7 bem d 1 50 1 021 8 NU IO 900X021 900X022 1 gt 5 5 AAA gu 4 4 7K SIP 10 WANA 51 S aN 50 1 1 4 0 1 7 5 0 1 16 5 1 15 ZL 1 12 1 13 5 C 1 12 9 022 74ALS520 TITLE m PLOT DATE SCH HIGH SPEED ANALOG INPUT BOARD 17 JUN 91 PRODUCT NO
68. 41 hardware function eren 74 Analog input jumpers 7 6 channel 1 1 PCI 20019M 1A 7 11 convert inhibit 12 registers M M 7 6 7 8 pacing GSOUYLCES cccccccccossccccoseccsoccocseccceeee 1 2 UNIQUE eere eene 7 6 procedure with hardware timing 7 14 Bracket slot 2 12 programming 713 BUEDEC instruction 5 6 6 6 6 8 read channel sess 6 22 Buffers selecting voltage ranges 2 6 and page boundary 5 5 voltage 1 1 5 5 Analog input channel iiie dpi rt ap riae i Re bw ee 51 Sac MN 7 13 data organization eene 5 5 Analog to digital converter DMA modes 4 5 6 hardware function 73 DMA modes and 5 5 Application programs eee 6 1 for DIMA CURE PD 54 bie Eo 6 2 Deal ase acepta 5 5 header files and 6 1 maximum 5 2 55 sequence of 6 2 reading eere 4 444 24 47 4 6 8 Autom
69. 5 1 SLEEK e o E EE CERE E FREE E ER ERE 2 PROGRAM NAME SAMPLE PROGRAM 5 3 VERSION 1 1 A 12 PCI 20091W Sample Program 5 LANGUAGE BASIC TRANSLATOR MICROSOFT QUICK BASIC VERSION 4 0 4 5 6 7 3 eve dee de dede de dede ede dee de de dee ede de dede de dete ve de de de de de de de deve dede e dee ye TEI dee eee dede dede dede tede eee te 8 9 DECLARE SUB ErrorCheck ErrorString AS STRING g 11 THIS PROGRAM DEMONSTRATES THE DMA INPUT FEATURE OF THE PCI 20091W 1 12 RUNNING IN DMA MODE 2 WITH A PCI 20010T 1 WHEN PCI 20092S 1 15 13 LOADED USE B TO GET A 64K DMA BUFFER THE PROGRAM USES THE 14 FOLLOWING 200265 1 INSTRUCTIONS 16 SYSINIT INIT ERR SYS 17 BUF DEC CNF DMA CNF RG DMA RUN 18 DMA STAT DMA STOP WRITE CH 20 THE FOLLOWING HARDWARE CONFIGURATION IS REQUIRED 6 IN wo IN W12 IN W14 IN W27 IN W28 IN ALL OTHER JUMPERS OUT DMA H W 9 9 9 9 THE ANALOG INPUT SIGNALS MUST BE CONNECTED TO THE TERMINALS LABELED 39 74 5 6 AND 7 ON THE PCI 20010T 1 AND THE PCI 20010T 1 MUST BE 40 CONNECTED TO THE PCI 20091W 1 4 RRR AA AAA RARE ALAR RARE ER AERA RARE fede dede dede dete de dede REECE 43 INCLUDE THE DRIVER INTERFACE HEADER FILE 44 SINCLUDE PCIHEADQ BAS n DEFINE DMA DATA ACQUISITION PARAMETERS 49 FRAMES PER CLUSTER 4 NUMBER OF
70. 6 96 PRINT Channel Analog Input voltage is 5 PRINT USING 444 404 FDATA 100 WAIT FOR A KEY THEN TAKE ANOTHER READING PRESS Q TO STOP 101 DO 102 K INKEYS 193 LOOP WHILE 195 5 0 KS q THEN END 107 NEXT CHN 108 109 PRINT Done 110 111 END 112 113 DEFSNG A E G Z 115 SUB ErrorRoutine ErrorString AS STRING Hs DEFINE A GENERAL PURPOSE ERROR PROCESSING ROUTINE 118 ERROR CODEZ 0 119 CALLS ABSOLUTE ERROR CODEZ ERR SYS 121 IF ERROR CODEZ lt gt THEN 123 PRINT ErrorString ERROR CODE 124 END 125 126 END IF 127 128 END SUB 129 Sample Program 2 1 9 de dee e ve e ve e de de de e de e ede de ede de dede de de de dete de ede de dede dee de dede dede dede dede dede eee ee de ede de dede dede ee dee 2 PROGRAM NAME SAMPLE PROGRAM 2 2 VERSION 1 1 5 LANGUAGE BASIC 6 TRANSLATOR MICROSOFT QUICK BASIC VERSION 4 0 7 8 jo DECLARE SUB ErrorRoutine ErrorString AS STRING 11 THIS PROGRAM OUTPUTS A PULSE TRAIN FROM THE RATE GENERATOR ON THE PCI 20091W 1 USING THE FOLLOWING PCI 20092S 1 INSTRUCTIONS 3 14 SYSINIT INIT ERR SYS 12 CNF RG WRITE CH FOLLOWING HARDWARE CONFIGURATION IS REQUIRED 19 9 lt 2 lt 4 lt 20 PCI 20091W 1 21 4 lt 2 lt 2 lt fone access 22 amp HCDCO 23 JUMPE
71. 7 15 20091 1 High Speed Analog Input Board 7 16 7 5 7 GENERATOR INITIALIZATION PROCEDURE This procedure initializes the Rate Generator Step 1 Write the first control byte 36H for mode 3 34H for mode 2 to the control register BYTE BA 043H This resets the count register of the Rate Generator section and disables counting The output signal is set high Step 2 Write the second control byte 76H for mode 3 74H for mode 2 to the control register BYTE BA 043H Step 3 Write the first count to the first count register BYTE BA 040H Write first the low byte and then the high byte of the count Both bytes are written to the same register this is nota WORD operation Step 4 Write the second count to the second count register BYTE BA 041H Write first the low byte and then the high byte of the count Both bytes are written to the same register this is not a WORD operation 7 5 8 GENERATOR ENABLE OR DISABLE PROCEDURE This procedure enables or disables the Rate Generator Step 1 Set up the enable byte Since this register controls the Delay counter the Rate Generator and DMA operation you must be sure to set all bits correctly The enable byte should have each bit that corresponds to the Delay counter or Rate Generator section set to a 1 if the section is to be enabled and to a 0 if the section is to be disabled Step 2 Write the enable byte to the enable register BYTE BA 002
72. CDCO BUT YOU CAN SET IT ANYWHERE REFER TO THE PCI 20091 1 MANUAL FOR MORE INFORMATION INIT MUST BE CALLED ONCE FOR EACH CARD IN THE SYSTEM EACH WITH ITS OWN ADDRESS CALLS ABSOLUTE BOARD SEG INIT CHECK FOR A SYSTEM ERROR DURING DEBUG CALL ERR SYS OFTEN POSSIBLY AFTER EVERY CALL TO THE 200925 1 IS A GOOD IDEA TO LEAVE A FEW ERR SYS CALLS IN A FINISHED PROGRAM TO MONITOR THE STATUS OF THE SYSTEM ErrorCheck Error found during INIT CONFIGURE THE RATE GENERATOR CHANNEL THE CHANNEL NUMBER TO CONFIGURE AND THE COUNT AND MODE CONFIGURATION PARAMETERS MAY BE FOUND IN RG CHN COUNT1 COUNT2 AND RG MODE PRINT Configuring rate generator channel CALLS ABSOLUTE RG CHN COUNT1 COUNT2 RG MODE CNF RG ErrorCheck Error found in call to CnfRg PRINT Done CONFIGURE THE DMA PROCESS WHICH WILL BE RUN LATER THE PACER AND TRIGGER TYPES AND CHANNELS ARE DEFINED IN PAC TYPE PAC CHN TRIG TYPE AND TRIG CHN THE DMA CHANNEL AND TYPE LISTS MAY BE FOUND IN CHNS AND TYPES RESPECTIVELY THE NUMBER OF BYTES IN EACH CLUSTER IS RETURNED TO THE CALLER 1 THE DMA PROCESS WILL BE PACED BY THE END OF CONVERSION SIGNAL FROM THE PCI 20091W 1 THIS SIGNAL BECOMES ACTIVE WHEN AN ANALOG CHANNEL VALUE HAS BEEN CONVERTED TO A DIGITAL VALUE AND IS READY TO BE READ 2 THE START CONVERT SIGNAL TO THE PCI 20091W 1 IS SUPPLIED FROM THE ON BOARD RATE GENERATOR 3 THE DMA PROCESS WILL BEGIN ON COMMAND AND
73. E The I O type of the pacing signal for the DMA process The pacer type must always be 2 PAC CHN The channel number of the first channel on the PCI 20091W 1 Board This will be 0 unless your system contains more than one PCI 20091W 1 3 MODE DMA Mode desired Valid modes are 2 3 or 4 4 TR TYPE The type ofthe trigger source The user may specify XSYNC to use the external interrupt line on the PCI 20091W 1 or 0 for no trigger Note only DMA Mode 3 requires a trigger A trigger event occurs when the External Interrupt is taken low 5 TR CHN Trigger source channel number Must be 0 6 TYPES type list corresponding to the channel list of Argu ment 7 See the discussion below for legal type list format 7 CHNS List of channel numbers with the final balue being 1 to indicate the end of the list See the discussion below for legal channel list format 8 CNT Number of bytes per cluster or 0 if errors were encountered Be sure to predefine this argument by setting it equal to 0 prior to this call The Software Drivers use the information in the arrays TYPES and CHNS to set up the frame map and determine the number of frames per cluster The number of bytes per cluster is returned as the final instruction argument The channel and type lists passed to CNEDMA must follow certain conventions because of the way the PCI 20091W 1 hardware operates If the PCI 20091W 1 is configured with autom
74. ERG 6 13 channel channel configuration 2 9 Command line 3 9 channel 5 6 COMMAND COM DOS 3 8 checking status ee 6 16 COMP DOS 1 3 4 continuous mode 53 Compatibility with PCI 20000 system 1 3 control configuration 2 9 Compatibility with Software Drivers 7 12 delay 2 10 Computer memory 2 1 effect on foreground programs 54 Configuration fixed period mode 52 automatic channel sequencing 27 instructions 5 7 control 29 5 2 hardware o 2 1 maximum sampling rates 54 high speed acquisition 41 OvVerrun 4 44 5 3 5 4 2 7 pacing signal eset 2 10 start of conversion source 2 6 programming 5 7 Configuring DMA sampling rate 5 3 ro qui EET 6 9 sampling rate formula 6 14 Connector sequence 5 1 INDEX 2 PC1 20091W 1 setting delay counter 6 15 setting terminal count 6 15 software configuration
75. ERVED EXTERNAL INTERRUPT DIGITAL GROUND 5V PCI 20091W 855M1BOC UMI Chapter 3 Software Installation re EE EEE EE E EEEE EE E EEEE EEEE Ed 3 1 Chapter Overview This chapter covers installation of the PCI 20092S Software Drivers Chapters 4 and 5 cover the topics of high speed analog data acquisition Direct Memory Access DMA and buffer management in detail The software technical reference chapter chapter 6 gives information on creating application programs lists and describes the calls used by the Software Drivers and lists the error codes you may encounter Sections 3 2 through 3 4 introduce the Software Drivers and list the hardware and software needed to run them Section 3 5 gives instructions on how to make a working copy of your Software Drivers Section 3 6 describes how the Software Drivers work Section 3 7 tells you how to install your software into your computer and how to get your software up and running 3 2 Software Drivers Included With Your System The 200925 1 Software Drivers included with your PCI 20091W 1 Board pro vide an uncomplicated consistent and useful interface between the Microsoft QuickBASIC language programmer and the PCI 20091W 1 They provide QuickBASIC support of the most useful hardware level functions while buffering the programmer from the details of running the hardware We believe you will find the PCI 20092S 1 Software Drivers to be a very flexible powerful and useful
76. FF 80000 7FFFF 00500 004 00400 00000 USER AREA AT XT PC USER AREA USER AREA RECOMMENDED RECOMMENDED LOCATION FOR LOCATION FOR LIM EXPANDED EXPANDED LIM EXPANDED MEMORY 64K MEMORY 64K MEMORY 64K 1 1 1 USER AREA USER AREA USER AREA RECOMMENDED LOCATION FOR PRIMARY PCI 20000 SYSTEM ADDRESS LOCATIONS PRIMARY PCi 20000 SYSTEM ADDRESS LOCATIONS PRIMARY PCI 20000 SYSTEM ADDRESS LOCATIONS USER AREA ROM EXPANSION MEMORY AREA ROM EXPANSION MEMORY AREA 2 2 2 EGA BIOS EGA BIOS EGA BIOS 3 3 3 ROM EXPANSION MEMORY AREA EGA SCREEN BUFFERS EGA SCREEN BUFFERS EGA SCREEN BUFFERS 3 3 3 128K RAM EXPANSION AREA 4 ALTERNATIVE PCI 20000 SYSTEM ADDRESS LOCATIONS 1 Without LIM boord 3 Without EGA adapter 2 Sometimes available 4 only without 128K expansion board PCI 20091W 855M180D UMI Fig 2 1 IBM Personal Computer Memory Map PCI 20091W 1 2 3 PCI 20091W 1 High Speed Analog Input Board EXAMPLE 1 Memory Address CD00 0000 fT eel Cn ir Address 0000 1100 1101 0000 0000 0000 Binary A19 EXAMPLE 2 Memory Address CD40 0000 ie Address CD400 Hex 1100 1101 0100 0000 0000 Binary 19 EXAMPLE 3 Memory Address CD80 0000 ire Address CD800 Hex 1100 1101 1000
77. H This register cannot be read so you must store the enable byte in program memory 7 5 9 DMA PROCEDURES In the DMA procedures below it is assumed that the DMA pacing source is the on board rate generator If the External Start Convert input is used as the pacing source omit the rate generator programming In this case to keep the input channels from becoming rotated the start convert signal should only be applied after DMA programming is complete and the DMA circuitry is enabled This can be accomplished by using the Convert Inhibit input to gate the start convert signal 7 5 10 DMA MODE 2 PROCEDURE This procedure describes programming the Board for DMA Mode 2 operation If the External Start Convert input is used as the pacing source omit the rate generator programming PC1 20091W 1 Step 1 Step 2 Step 3 Step 4 Step 5 Step 6 Step 7 Step 8 Step 9 Step 10 Chapter 7 Hardware Technical Reference First make sure that the source of A D start convert signals is disabled The on board rate generator can be disabled by clearing bit 3 of 002 Set the on board rate generator frequency as described in section 7 5 6 RATE GENERATOR INITIALIZATION PROCEDURE Reset the PCI 20091W s DMA controller by writing 00H to BYTE BA 002 Configure the PC s DMA controller for no auto initialize operation and set the base address byte count registers and terminal count Program DMA Mode 2and ena
78. ISITION 113 SFRAMES 0 114 DELAY 20 115 PRINT Setting Up DMA Acquisition 116 CALLS ABSOLUTE SFRAMES DELAY DMA RUN i ErrorCheck Error found during DMA RUN 115 PRINT Done 12 START THE ACQUISITION 123 ENABLE 1 124 PRINT Starting DMA Acquisition 125 CALLS ABSOLUTE RG T RG CHN ENABLE WRITE CH 126 ErrorCheck Error found during WRITE CH 128 PRINT Done 129 130 WAIT FOR TRIGGER AND DELAY TO COMPLETE 131 PRE DEFINE NUMCLSTS NUMBER OF CLUSTERS READ AND STATUS 133 PRINT 134 PRINT DMA running Press any to abort 135 PRINT Waiting for Trigger and Delay to Complete 136 NUMCLSTS 0 137 STATUS 0 138 139 DO 140 CALLS ABSOLUTE NUMCLSTS STATUS DMA STAT 115 a a ferre rror found during DMA STAT trigger and delay wait INKEY s LOOP WHILE STATUS 3 AND KS 145 IF STATUS 3 THEN 146 PRINT Aborted 147 CALLS ABSOLUTE NUMCLSTS DMA STOP 148 ERR CODE 0 149 CALLS ABSOLUTE ERR CODE ERR SYS 150 IF ERR CODE lt gt 0 THEN 151 PRINT Error found during DMA STOP ERR CODE continuing 152 END IF 153 ELSE 154 PRINT Done 122 END IF 137 THE ACQUISITION IS NOW COMPLETE 159 PRINT 160 PRINT NUMCLSTS clusters of data are available 161 PRINT Press any character to display next cluster Q to quit PCI 20091W A 11 Appendix 200925 Sample Programs 162 163 PRINTS THE DATA IN THE BUFFER USE THE BUF DEC
79. If the PCI 20091W 1 Board is configured for Hardware Scan mode see section 2 5 the starting channel must be written to this register In addition Offset 104 must be programmed with the first channel to be read bits 0 through 2 channel number of analog input channel pV VO V M 7 5 Hardware Programming Procedures 7 5 1 MEMORY ADDRESSES The following procedures are given as representative examples for programming this Board These procedures are not intended to be an exhaustive list of program ming possibilities In the programming procedures that follow the address of each register is expressed as BA n where n is the register offset and is the Board s block address Single byte references are identified as BYTE address and two byte references are identified as WORD address For example a word at local register offset 102 Hex on a Board would be identified as WORD BA 102H A byte local register offset 040 Hex a Board would be identified as BYTE BA 040H 7 5 2 ANALOG INPUT PROCEDURE The following procedure performs a conversion on an analog input channel and reads the converted data PCI 20091W 1 7 13 20091 1 High Speed Analog Input Board Step 1 Make sure the Interrupt Status register is reset by reading BYTE BA 102H Ignore the data read Step 2 Set
80. M READS ANALOG INPUT WITH PCI 20091W 1 AND A 12 PCI 20010T 1 USING THE FOLLOWING PCI 20092S 1 INSTRUCTIONS 14 SYSINIT INIT ERR SYS 12 gt READ CH 6 i THE FOLLOWING HARDWARE CONFIGURATION IS REQUIRED 19 2 20 PCI 20091W 1 21 Ed andate Bs unice 25 6 IN wo IN Wi5 IN W19 IN amp HCDCO 24 ADDRESS 25 26 27 J TIMEBASE 28 x 29 ae ee een 30 ALL OTHER JUMPERS OUT DMA 31 9 LEES 5 35 gt THE ANALOG SIGNAL BE MEASURED MUST BE CONNECTED TO THE TERMINAL 36 LABELED 0 ON THE PCI 20010T 1 AND THE PCI 20091W 1 MUST BE CONNECTED 37 TO THE PCI 20010T 1 38 PARRA Aa Aw AAA AK vete dede e dese de de dede dede fe deve de de dee RE e ede ede dee e dede dede dede e dede k kk dede 40 INCLUDE THE DRIVER INTERFACE HEADER FILE 42 INCLUDE 44 INITIALIZE THE 1 200925 1 SYSTEM THIS CALL MUST BE MADE PRIOR 45 TO CALLING ANY OTHER PCI 20092S 1 INSTRUCTION 46 47 PRINT 19 PRINT Begin PCI 20092S 1 Sample Program 1 Be CALLS ABSOLUTE 545111 52 SEGMT DEFINED BELOW IS THE BASE ADDRESS OF THE PCI 20091 1 WE 53 USE amp HCDCO BUT YOU CAN SET IT ANYWHERE REFER THE PCI 20091 1 54
81. MA 24 25 CONST CNF HS 30 26 CONST CNF RG 36 27 CONST DMA RUN 42 28 CONST DMA STAT 48 29 CONST DMA STOP 54 30 CONST ERR SYS 60 31 CONST HS RUN 66 32 CONST INIT 72 33 CONST READ CH 78 34 CONST SYSINIT 84 35 CONST WRITE CH 90 36 Define the PCI 20092S 1 I O types 37 CONST 1 38 CONST RG T 8 39 CONST EXINT T 100 40 CONST XSYNC T 104 41 5 105 42 Buffer functions present 43 CONST BUF 0 44 DMA functions present 45 CONST DMA 0 46 High speed acquisition functions present 47 CONST HSA 0 48 49 DEF SEG 0 INTVEC amp H180 50 SEGMT PEEK INTVEC 2 amp H100 PEEK INTVEC 3 51 DEF SEG SEGMT 52 Check for installed software 53 IF SEGMT lt gt 0 AND PEEK 11 33 AND PEEK 12 amp H9A THEN 2 54 1 PRINT PCI 20092S 1 not installed or invalid CHRS 7 END 55 2 CALLS ABSOLUTE VERS L VCHK 1 VCHK L AUTOGRPH 56 IF VCHK L lt gt VERS L THEN 1 57 FOR I 1 TO VCHK L IF VERS I lt gt VCHK THEN 1 58 NEXT I Fig 3 2 PCIHEADQ BAS listing PC1 20091W 1 3 7 PCI 20091W 1 High Speed Analog Input Board The instructions in lines 49 through 58 verify the presence of the resident software and set the segment used by call statements to reference the PCI_92S EXE jump table The PCIHEADQ BAS header file is stored in ASCII format It may be incorporated into an application program with the INCLUDE metacommand as descr
82. MANUAL FOR MORE INFORMATION INIT MUST BE CALLED ONCE FOR EACH 55 CARD IN THE SYSTEM EACH WITH ITS OWN ADDRESS 57 SEGMT amp HCDCO 58 CALLS ABSOLUTE SEGMT INIT 59 60 CHECK FOR A SYSTEM ERROR DURING DEBUG CALL ERR SYS OFTEN 61 POSSIBLY AFTER EVERY CALL TO THE PCI 20092S 1 15 A GOOD IDEA 62 LEAVE ERR SYS CALLS IN A FINISHED PROGRAM TO MONITOR THE 2 STATUS THE SYSTEM 65 ErrorRoutine Error found during INIT 67 READ THE ANALOG INPUT CHANNEL 68 gt PRE DEFINE THE RETURNED VALUE 70 ADATA 0 72 PRINT Reading data 8 channels 73 PRINT This program assumes the board is configured for 10 V 74 PRINT Press any key to continue Q to stop 22 FOR 0 TO 7 79 CALLS ABSOLUTE AI T ADATA READ CH 2 ErrorRoutine Error found during READ CH PCI 20091W A 5 Appendix 1 200925 Sample Programs 8 CONVERT THI ADC READING INTO VOLTS AND DISPLAY E THE ASSUMPTION IS THAT THE PCI 20091W 1 IS SET UP FOR 10 VOLTS es FDATA 4095 ADATA 20 4096 10 88 THE FOLLOWING TABLE GIVES THE EQUATIONS TO BE USED IN PLACE OF THE 8 ABOVE LINE FOR OTHER THAN 10 VOLTS 91 4 2 5 FDATA 4095 5 4096 2 5 92 5 FDATA 4095 ADATA 10 4096 5 93 0105 4095 5 4096 d 23 0 1010 FDATA 4095 ADATA 10 409
83. MHz 0 002 Hz 0 01 25 C TTL compatible 1 7 A typ 2 5 A max 7 5 x 4 2 0 70 C PCI 20091W 1 7 23 INDEX Index m Dd A Backup Software Drivers ess 3 3 ABSOLUTE QuickBASIC utility 6 1 Base 4 4 02 0 2 2 7 04 12 0 44 4 4 2 1 ABSOLUTE utility eee 3 5 and register 75 Batch file calibration sssini 7 1 loading Software Drivers fronB 11 3 12 Address Batch file 3 13 LII 2 1 Bit assignments Address switches eene 2 1 analog input channel register 7 13 2 2 delay counter control register 7 10 factory configuration 2 1 DMA mode register eene 7 7 recommended settings 22 Interrupt Status mode register 7 6 Addresses rate generator control register 7 10 MEMOLY PN NEN 7 4 scanner start channel registet 7 13 6 22 system status 7 7 Analog 1 2 12 Block diagram Analog data hardware 1 2 PI Hu 7 12 Board ID Analog data acquisition extended 7 6 high speed
84. NINGDMA 5 2 DMA Mode 2 Start on Command Stop on Terminal Count 5 2 Mode Start on Command Stop on Trigger after Delay 5 2 Mode 4 Start on Command Stop Command 5 3 DMA Rates 5255 5 3 DMA and Foreground Programs 5 4 DMA BUR OES ae tae SR 5 4 Sill BUFFER SIZE 6 2 wg EC wm x 3 se a 5 5 5 7 2 BUFFER DATA ORGANIZATION 5 5 Data Frames and Clusters 5 5 5 8 1 AUTO SEQUENCED CHANNELS 5 6 5 8 2 DATA FRAMES AND DMA MODES 3 and4 5 6 HO TYPOS oe eue hoe a a a ebd Cathie 5 6 DMA INSTRUCTIONS 5 7 5 10 1 DMA INITIALIZATION INSTRUCTIONS 5 7 5 10 2 CONTROL INITIALIZATION INSTRUCTIONS 5 7 5 10 3 DMA EXECUTION INSTRUCTIONS 5 7 5 10 4 BUFFER CONTROL INSTRUCTIONS 5 7 CHAPTER 6 SOFTWARE TECHNICAL REFERENCE 6 1 6 2 6 3 6 5 Chapter Overview 6 1 Creating Application Programs 6 1 Hardware Initialization 6 3 63 1 INITIALIZATION SEQUENCE 6 3
85. O 1 78 NEXT WINDNO 79 aitKey En NEXT SETNO 82 FOR WINDNO 8 TO 9 83 PlotData FRAME Y PLOTNO WINDNO 84 PLOTNO PLOTNO 1 52 NEXT WINDNO 87 WaitKey 55 END 20 SUB InitWindow FRAME 9s Define windows to plot in 9 94 Windovs 1 2 3 and 4 are one quarter screen windows 96 FRAME TOPX 1 296 FRAME TOPY 1 4 97 FRAME BOTX 56 FRAME BOTY 1 84 1 1 99 FRAME TOPX 2 600 FRAME TOPY 2 4 100 FRAME BOTX 2 360 FRAME BOTY 2 84 3 3 4 102 FRAME 296 FRAME TOPY 3 108 103 FRAME 56 FRAME BOTY 3 188 105 FRAME TOPX 600 FRAME TOPY 4 108 106 FRAME BOTX 4 360 FRAME BOTY 4 188 108 Window 5 is a full screen window 110 FRAME TOPX 5 616 FRAME TOPY 5 4 FRAME BOTX 5 56 FRAME BOTY 5 188 Windows 6 and 7 are half screen horizontal windows Wu me den e et 6 600 FRAME TOPY 6 4 6 56 6 84 FRAME TOPX 7 600 FRAME TOPY 7 108 FRAME BOTX 7 56 FRAME BOTY 7 188 121 Windows 8 and 9 are half screen vertical windows 123 FRAME TOPX 8 296 FRAME TOPY 8 4 124 FRAME BOTX 8 56 FRAME BOTY 8 188 126 FRAME TOPX 9 600 FRAME TOPY 9 4 155 FRAME BOTX 9 360 FRAME BOTY 9 188 150 END SUB 131 SUB PlotData FRAME Y PLOTNO WINDNO 133 Subroutine t
86. OR K THEN END 237 NEXT I 238 239 PRINT Done 240 24 END 242 243 DEFSNG A E G Z 244 SUB ErrorCheck ErrorString AS STRING 245 217 DEFINE GENERAL PURPOSE ERROR PROCESSING ROUTINE 248 ERROR CODEZ 0 CALLS ABSOLUTE ERROR CODEZ ERR SYS 325 IF ERROR CODEZ lt gt 0 THEN 253 STOP ANY DMA ACQUISITION THAT MIGHT HAVE BEEN RUNNING WHEN THE 254 ERROR OCCURRED 255 256 CLUSTS 0 200 CALLS ABSOLUTE CLUSTSZ DMA STOP 259 PRINT THE ERROR MESSAGE PASSED IN 5 A PARAMETER AND THEN PRINT THE 260 ERROR CODE NUMBER 262 PET ErrorString ERROR CODEZ PCI 20091W 4 15 Appendix PCI 20092S Sample Programs 264 265 END IF 266 267 END SUB 268 1 DECLARE SUB WaitKey 2 DECLARE SUB InitWindow FRAME 3 DECLARE SUB PlotWindow FRAME WINDNO 2 DECLARE SUB PlotData FRAME PLOTNO WINDNO CLS SCREEN 2 KEY OFF 8 FRAME 1 w is a two dimensional array containing the coordinates of the 9 corners of each window defined Mnemonic indices are defined for the 10 four corners of each window 11 gt and define the upper left hand corner 12 and BOTY the lower right hand corner of the plot windows WINDS sets the number of windows defined to 9 1 15 Y m n is a two dimensional array containing the data sets for each plot 16 where m is the plot number and is the data point index 1 PASSES sets the number of datapoints p
87. R SETTINGS DO AFFECT THE RATE 24 GENERATOR THE FACTORY CONFIGURATION IS ADDRESS 25 FINE 26 27 TIMEBASE 28 eem 29 30 DMA H W 3 fl eee ctu oe ee 32 ki 20091 Sample Program 2 35 THE TTL DIGITAL PULSE TRAIN GENERATED BY THIS PROGRAM IS AVAILABLE 36 CONNECTOR PIN 1 OF THE PCI 20091W 1 AND DIGITAL GROUND IS 37 AVAILABLE ON CONNECTOR P3 PIN 6 OF THE PCI 20091W 1 38 dede ede dede vede dee dede dede de ede deve dede de de dede dede dete de eee det tee dee dee eee dete ee 39 A INCLUDE THE DRIVER INTERFACE HEADER FILE 1 42 SINCLUDE gt BAS 4 44 INITIALIZE THE PCI 20092S 1 SYSTEM THIS CALL MUST BE MADE PRIOR 45 TO CALLING ANY OTHER PCI 20092S 1 INSTRUCTION 46 47 PRINT 20 PRINT Begin 1 200925 1 Sample Program 2 22 CALLS ABSOLUTE SYSINIT 52 SEGMT DEFINED BELOW IS THE BASE ADDRESS OF THE PCI 20091 1 53 gt USE amp HCDCO BUT YOU CAN SET IT ANYWHERE REFER TO THE 1 20091 1 54 MANUAL FOR MORE INFORMATION INIT MUST BE CALLED ONCE FOR EACH 55 CARD IN THE SYSTEM EACH WITH ITS OWN ADDRESS 57 SEGMT amp HCDCO 58 CALLS ABSOLUTE SEGMT INIT 59 60 CHECK FOR A SYSTEM ERROR DURING DEBUG CALL ERR SYS
88. RCE The PCI 20091W 1 s DMA controller is paced by the A D converter s End Of Con vert signal The data acquisition pacing is controlled by the source of the A D converter s start convert signal This signal can be configured to come from either the Rate Generator or the External Start Convert see section 2 4 2 7 4 DELAY COUNTER DMA Mode 3 permits sampling of pre and post trigger data The delay counter which can be programmed for a count of up to 65 000 samples controls the amount of data taken after the trigger event The Delay Counter must be initialized before DMA Mode 3 is started see chapter 6 or section 7 4 2 7 5 CHANNEL SELECTION The DMA channel is jumper selectable among channels 1 2 and 3 by jumper W21 and jumpers W27 through W31 as shown in table 2 8 TABLE 2 8 DMA Control Jumper Settings DMA Channel Jumpers IN Jumpers OUT 1 W21 W27 W28 W29 W30 W31 1 W27 W28 W21 W29 W30 W31 2 W21 W31 W27 W28 W29 W30 3 W29 W30 W21 W27 W28 W31 Factory configuration Note DMA channel 1 is recommended since IBM PCs use DMA channel 2 for floppy disk drives and channel 3 for hard disk drives The included PCI 20092S Software Drivers support only DMA channel 1 2 8 Rate Generator The Rate Generator can be used for pacing A D conversions and DMA transfers Its output is also available on pin 1 of connector P3 The Rate Generator is actually two concatenated 16 bit cou
89. RGANIZATION The logical structure of a buffer may be either linear or circular depending on which DMA Mode you specify in the CNEDMA Configure DMA instruction DMA Mode 2 uses a simple linear buffer This means that the DMA process starts loading data into the buffer at the buffer s lowest address and continues to load data into the buffer until the buffer is full or the DMA process reaches the programmed number of bytes terminal count whichever comes first At that point the DMA process stops Data is stored sequentially in the buffer and is always left justified in the buffer That is the oldest data is at the beginning of the buffer and the newest data is at the end DMA Modes 3 and 4 use what is called a circular buffer Data is stored sequentially in the buffer as above but if the DMA process reaches the end of the buffer it starts over again at wraps around to the beginning until the stopping criterion is met Newly acquired data will thus overwrite the old data and when data acquisition stops the oldest data may lie somewhere in the middle of the buffer The PCI 200925 1 software postprocesses the buffer unwrapping it if required so that the oldest data is put at the beginning of the buffer and the newest data is put at the end Thus the buffer wrap around is invisible to the application a OMM MN RN 5 8 Data Frames and Clusters The PCI 20092S 1 Software Drivers handle the tra
90. ROR CODEZ s 0 PCI 20091W 7 Appendix PCI 20092S Sample Programs 120 CALLS ABSOLUTE ERROR CODE ERR SYS 122 IF ERROR CODEZ lt gt THEN 12 124 PRINT ErrorString ERROR CODEZ 125 END 126 127 END IF 128 129 END SUB 130 Sample Program 3 1 9 deese de dede dede de de dede de dede dede de de dede dede de dede dede dee dede BE de dede de dede II deve de eode dede dede deese dee dede edt 2 SAMPLE PROGRAM 3 3 VERSION 1 1 4 5 LANGUAGE BASIC 6 TRANSLATOR MICROSOFT QUICK BASIC VERSION 4 0 7 8 12 DECLARE SUB ErrorRoutine ErrorString AS STRING 11 THIS PROGRAM DEMONSTRATES THE HIGH SPEED FEATURE OF THE PCI 20091W 1 15 WITH PCI 20010T 1 USING THE FOLLOWING PCI 20092S 1 INSTRUCTIONS 14 2 SYSINIT INIT ERR SYS HS RUN CNF HS CNF RG i THE FOLLOWING HARDWARE CONFIGURATION IS REQUIRED 19 34 2 222 2 22 2 2 2 22 2 2 22 2 22222 22 222222 222 22 2 2 2 2 222222 22 2 2 2 2 20 PCI 20091W 1 21 3 E 25 6 IN 9 IN W12 IN W14 IN amp HCDCO 24 ADDRESS 25 26 AG MEM LZZLLLZBOQNlll LL OUNHU UP PPS 27 TIMEBASE 28 si 5555 29 ee ee 31 ALL OTHER JUMPERS OUT DMA H W 1 ga Willi s dee 35 gt liil 35 THE ANALOG INPUT SIGNALS MUST BE CONNECTED TO THE TERMINALS LABELED
91. RST START 3 STOR 581 1 TITLE SCH HIGH SPEED ANALOG INPUT BOARD PLOT DATE 17 JUN 91 PRODUCT NO VOL LABEL 9235008 1 1 DOCUMENT NO REV SHEET 91W 1 FILE 923s0088 scH 92 35008 SCH D 2 4 REVISIONS APRV D SPAN OFFSET UN RS R4 50K MSB_LATCH 15V 4 gt 15 15V lt gt 15V R5 177 270K 180K 8 6 BK OUT 11 CH58 se a INS stas 52 19 2 INS 270 lt 01 50V AD E Oe GAIN ADu 22 lt gt MuUX508 coMP 22 L S 2 3 I S 2 10v 24 Wifo o P2 6 zov fas gt 5 24 REF out 18 lt gt 25 SHC5320 Bur our 28 Bur IN 20 ANA COM 28 V gt 5V 4 7K 5 SIP 5V A P3 CONV INHIB gt P3 3 EXT STRT CONV P3 2 5V E 5 A m sv P3 7 w12 gt i RN1 M780 DGND P3 6 VOUT VIN 5V REG fa 6 8 25V 12 is Mr 0 _ lt 5 8 CDMALON RO TBIOR 5 PLOT DATE 17 JUN 91 REV SHEET 3 4 TITLE SCH HIGH SPEED ANALOG INPUT BOARD PRODUCT NO VOL LABEL 9235008 1 1 DOCUMENT NO 91W 1 FILE 9235008 5 9255008 SCH POWER AND GROUND
92. S 3 10 entry ioo 3 5 Program license 3 2 hardware registers 7 4 Programming 7 3 Operation of Software Drivers 3 5 5 7 Overrun Programming codes high speed data acquisition 6 20 delay counter control register 7 10 Overrun error rate generator control register 7 10 DM A 5 3 Programming procedure delay counter initialization 7 14 Programming procedures 7 13 P analog input serene 7 13 analog input settling delay 7 14 Pacing signal delay counter enable or disable 7 15 DMA 210 delay counter read 7 15 6400029000005000900900000002006050 205900040009000900059 DMA Mode 2 7 16 INDEX 6 PCI 20091W 1 DMA MOdt3 7 17 DMA Mode frion 7 18 rate generator enable or disable 7 16 rate generator initialization 7 16 PROMPT DOS command 3 10 Q QuickBASIC ABSOLUTE utility 3 5 6 1 INCLUDE command 6 1 user uode detis mede 6 1 6 1 QuickBASIC application 5 6 1 QuickBASIC commands CALS cci sinas adu dud amis 6 7 CALLS and 6 1 DEF SEG
93. Ss hs Ss ses PCI 20091W 1 6 17 PCI 20091W 1 High Speed Analog Input Board DMA STOP Stop DMA DMA Control Instruction PURPOSE SYNTAX ARGUMENTS REMARKS Stop the DMA operation This instruction is required in DMA Mode 4 in other DMA modes this instruction will also stop the DMA process but an error code will be set if acquisition was in progress If an overrun condition exists the error code for the overrun will super sede errors due to an acquisition in progress CALLS ABSOLUTE COUNT DMA STOP 1 COUNT Number of clusters available to be read If errors other than an overrun were encountered a count of 0 will be returned Be sure to predefine this argument by setting it equal to 0 prior to this call If DMA STOP is called in DMA Mode 2 an error code will be set if the DMA process has not been terminated by terminal count In DMA Mode 3 an error code will be set if the DMA process has not been terminated by the trigger condition Calling DMA STOP in DMA Mode 4 will not set a system error code this is the normal method of terminating a DMA process in DMA Mode 4 This instruction should be called prior to exiting your application program to ensure that all DMA activity is terminated 6 18 PC1 20091W 1 Chapter 6 Software Technical Reference IE ES E ES TE SRE SEE E D ERR SYS System Error Utility Instruction PURPOSE Return the latest error code and clear the error register S
94. THE BURR BROWN 20000 PERSONAL COMPUTER INTELLIGENT INSTRUMENTATION SYSTEM PCI 20091W 1 HIGH SPEED ANALOG INPUT BOARD USER MANUAL 855 180 1 3 Copyright 1989 Burr Brown Corporation Tucson Arizona USA Copyright 1989 by Intelligent Instrumentation Inc Tucson Arizona USA All rights reserved Warranty and Repair Policy Summary All Burr Brown products are backed by a warranty policy which is fully described on the back of the packing list enclosed with product shipments The factory must be contacted prior to the return of any product If a product is suspected of being inoperative please contact your local Burr Brown representative If the returned unit is under warranty and requires repair it will be repaired or replaced at the discretion of Burr Brown and returned to you If the unit is out of warranty and requires repair a repair or replacement price will be quoted Your purchase order for these repair charges will authorize repair replacement action If a unit is returned that is found not to be defective you may be charged a nominal fee for the evaluation service and for the return shipment Version Date 1 0 1 1 1 2 1 3 880614 880909 880930 891020 PCI 20091W High Speed Analog Input Board 20091 1 USER S MANUAL REVISION HISTORY Revision Original Added measurement of Fi on pacer clock Added DMA Mode 4 and frequency reference information Added DMA procedures and
95. Table 7 9 summarizes the jumper functions discussed in chapter 2 Once you have grown familiar with the PCI 20091W 1 you may wish to refer to this table for changing your Board s configuration Factory settings are indicated in boldface type TABLE 7 9 Jumper Definitions Summary Jumper Function W4 IN Enables DMA Terminal Count interrupt OUT Disables DMA Terminal Count interrupt W5 IN Enables External Interrupt OUT Disables External Interrupt W6 IN W7 OUT These jumpers select the A D W8 OUT Range and Polarity see W9 IN section 2 3 W10 OUT Wi2 IN Enables rate generator start convert OUT Disables rate generator start convert W13 IN Enables start convert on read of MSB OUT Disables start convert on read of MSB W14 IN Enables channel scanner OUT Disables channel scanner W15 IN Disables channel scanner OUT Enables channel scanner W16 OUT These jumpers select capabilities W17 OUT and Board ID codes see section W18 OUT see section 2 7 W19 IN Disables channel scanner OUT Enables channel scanner W20 IN Enables external start convert OUT Disables external start convert PCI 20091W 1 7 19 PCI 20091W 1 High Speed Analog Input Board DEFINITION Table 7 9 cont d JUMPER W21 OUT W22 IN OUT W23 OUT W24 IN OUT W25 IN OUT W26 IN OUT W27 IN OUT W28 IN OUT W29 OUT W30 IN OUT W31 IN OUT W32 IN OUT Enables DMA channel 2 Disables DMA channel 2 Enables PC interrupt level 3 Disable
96. VOL LABEL 923S008 1 1 DOCUMENT NO REV SHEET 91W 1 FILE 9235008 5 9255008 SCH D 11 4 RATE GENERATOR BUFFER 011 011 LEGG gt 5 3 bui 15917 RG OUT P3 1 s 74LS04 p 741504 1575 SHT 1 EXT INT P3 5 STATU D BUS gt SHT 1 RES U11 N BBS EM 2 8 foo 4 22 ___ 1 266 gt 804 9 222 NOS ums W23 IRQ4 J N BB2 12 1Y4 o m PI 24B gt 801 16 lo o 1 23 gt BDO 1Y1 O IRQ7 gt TINT MODE SHIT SHT CES pMA_ON N 74LS04 74LS04 PALCLK 422 13 10 11 LIK lt 1 20 2 1711 U11 741574 1 map SHT 3 gt PACER gt SHT 3 U3 BDO 8 MHz gt 5V BO D2 CLKO 4 SHT 5 0 Se a ee 857 156 oi 4 D7 G1 BRD 22 OUTI RD DAC uu jas Bn oj 4B BASEL CEI TUR AO G 2511 gus ee o 21 DACK2 51 555 TONTRSEL gt SHT1 21 foo WSO DACKS 51 158 8254 C31 ULPBACER 22PF ONFIC lo 27 2891 bi isB 2 DELAY TRES Q2 PACER D 2 38 w29 DRG 9 P1 16B 18 EN EN 8 715 __ MODE VER DMA MODE IC Pi 27B Q 12 C34 BRST 470PF gt SHT_1 Ut LSB_EN 7415574 IOR MSB_EN B
97. W 1 6 19 20091 1 High Speed Analog Input Board HS RUN Run High Speed Data Acquisition Instruction PURPOSE Execute a high speed analog acquisition operation SYNTAX CALLS ABSOLUTE PASS DARRAY 1 SEGMNT HS RUN ARGUMENTS 1 PASS Indicates how many times the high speed acquisition routine is to go through the list of channels set up by the CNEHS Configure High Speed instruction The pass count parameter of this instruction may not exceed amp HFFFF 65535 decimal or 32767 if decimal integers are used 2 DARRAY Array in which the acquired data is stored Must be dimensioned to a size that will hold at least the number of channels in the list multiplied by the number of passes specified 3 SEGMNT Must be 0 REMARKS Overrun conditions are not detected in High Speed Mode 4 Note HS RUN disables all interrupts including the computer timer If you call HS RUN your computer s timer will not be correct 6 20 PCI 20091W 1 Chapter 6 Software Technical Reference INIT Initialize Utility Instruction PURPOSE SYNTAX ARGUMENTS REMARKS Initialize the PCI 20091W 1 setting up channel assignments for all I O channels contained on the PCI 20091W 1 and performing hardware initialization where appropriate CALLS ABSOLUTE SEGMT INIT 1 SEGMT Segment address high order 16 bits in memory at which the PCI 20091W 1 Board is located as determined by the Board s switch settings See s
98. X FXINC Next draw a line from the previous point to the new point IF J 1 THEN to FOLDX OLDY FXNEW NEWY Finally the new XY point becomes the old XY point FOLDX FXNEW OLDY NEWY NEXT J END SUB SUB PlotWindow FRAME WINDNO Subroutine to draw the plotting window and add tic marks to the axes Xl FRAME BOTX WINDNO Yl FRAME BOTY WINDNO X2 FRAME TOPX WINDNO Y2 FRAME TOPY WINDNO Set size of tic marks and clear border plot window 5 XTIC 10 BORD 2 Draw the window LINE X1 Yl BORD X1 Y2 BORD LINE Xl Yl BORD X2 Y1 BORD LINE X2 Y2 BORD X2 1 BORD LINE X2 Y2 1 Y2 BORD Add tic marks to the Y axis FYINT Y2 Y1 10 FOR I O TO 10 xs X1 Yl I FYINT X1 1 I FYINT E Add tic marks to the X axis FXINT X2 X1 10 FOR I O TO 10 ime dB X1 I FXINT Yl I FXINT Yl YTIC BORD END SUB SUB WaitKey DO K INKEYS LOOP WHILE K CLS END SUB PCI 20091W 89091902 RE RELEASED UNDER NEW P N OLD P N WAS 9235002 6 8 25V 5 EA 1 25V 91010903 012 WAS 900X030 SHEET 3 a 5V SOURCE 20 00 E cal 90010805 CORRECTED JUMPER AND OSCILLATOR ERRORS 33 o3s css D 90031201 114 IS 900x081 WAS 900x026 5 3 10 15 22 22 7457 a C1
99. XE you must specify the switch B1 The program samples channels 4 5 6 and 7 The complete channel list is scanned 20 times You should provide 4 2 PCI 20091W Appendix 200925 Sample Programs known signals on at least some of these channels to compare with the measured values Instructions used CNEDMA Configure DMA CNERG Configure Rate Generator WRITE CH Write Channel DMA RUN Run DMA DMA STAT DMA Status BUEDEC Decode Buffer DMA STOP Stop DMA A 4 Running the Sample Programs All of the Sample Programs are written for Microsoft QuickBASIC and have file names with the extension BAS and all of them are ASCII files This means that you can list them to the screen using the DOS TYPE command or list them to the printer using the DOS PRINT command You may also edit these files using a general pur pose editor The header file PCIHEADQ BAS contains definitions and program statements which must be executed at the beginning of any program which accesses the Software Drivers The Sample Programs incorporate the header file with the SIN CLUDE metacommand We recommend that you do this in your application programs as well The Sample Programs also include an error testing subroutine ErrorRoutine which you may wish to copy into your application programs The Sample Programs are written for a PCI 20091W 1 Board with the address switches configured for a base address of CDC00 Hex the factory default setting
100. YNTAX CALLS ABSOLUTE ERROR CODE ERR SYS ARGUMENTS 1 ERROR CODE Error code value Be sure to predefine this argu ment by setting it equal to 0 prior to this call See sections 6 7 through 6 13 for an explanation of the error codes There is no indication provided if previous error conditions have gone unchecked The value 0 indicates no error REMARKS This instruction returns the contents of the error register as the return value The contents of the error register reflect the last error that occurred Note that this does not imply that the error is necessarily associated with the last instruction called because the contents of the error register are changed only under three conditions calling the SYSINIT System Initialize instruction which sets the error register to 0 calling an instruction that causes an error code to be put in the error register or calling ERR SYS which returns the error and then sets the error register to 0 If you wish to ensure that the error code returned is associated with a particular instruction call ERR SYS before calling that instruction to set the error register to 0 and then again after calling that instruction to return the error code if any It is good practice when debugging your program to call ERR SYS after each 200925 1 call In this way your program will immedi ately be informed of any instruction errors and the codes in the error register will always be up to date PCI 20091
101. able Section 7 7 gives the hardware specifications 7 2 Testing and Calibration Your Board comes from the factory configured and calibrated for a range of 10 volts If you change this configuration or if you suspect inaccuracies check the calibration on your Board If the results of this test are out of specification and unacceptable for your application use the following procedure to recalibrate EQUIPMENT NEEDED 1 Voltage calibrator accurate to 0 5 mV over a range of 10 V 2 41 2 digit digital multimeter 3 Small insulated screwdriver for adjusting potentiometers Warning If you use an uninsulated screwdriver and accidentally touch other components you may damage your Board 4 A test program to sample the input continuously and display the results 5 IBM PC IBM XT IBM AT or equivalent 6 The PCI 20091W 1 High Speed Analog Input Board 7 PCI 20012A Analog Cable or equivalent 8 The PCI 20010T Analog Termination Panel or equivalent PROCEDURE 1 Turn off the power to the computer PCI 20091W 1 7 1 PCI 20091W 1 High Speed Analog Input Board WARNING Lethal voltages exist inside computers Always ensure that power is removed before opening the case CAUTION Failing to turn off the power when inserting or removing boards will damage the boards and possibly the computer as well Reading errors of more than 5 to 10 counts suggest a test procedure dif ficulty Check your setup carefully be
102. ad as two consecutive bytes to the register reading the least significant byte LSB first The programmed mode and status of the counter can be read from this register using the read back command described under Offset 43 WRITE Writing to this register sets the Delay counter The data must be written as two consecutive bytes to the register writing the least significant byte LSB first Offset 043 Rate Generator and Delay Counter Control READ Cannot be read The programmed counter mode can be read from the count registers using a read back command described below WRITE Rate Generator and Delay Counter Modes Writing to this offset defines the mode of both the Rate Generator and Delay counters The Rate Generator clock counters Offsets 040 and 041 should be programmed in Intel Modes 2 or 3 See the discussion of the CNERG Configure Rate Generator instruction in chapter 6 for details The Delay counter used for DMA must be configured in Intel Mode 0 The values for the control word to perform these operations are given in table 7 5 PCI 20091W 1 7 9 PCI 20091W 1 High Speed Analog Input Board TABLE 7 5 Offset 043 Control Words Bit Name Function 7 SC1 00 Rate generator LSB 6 SCO 01 Rate generator MSB 10 Delay 11 read back command 5 00 counter latch command 4 RWO 01 LSB only 10 MSB only 11 LSB then MSB 3 M2 000 Intel Mode 0 2 M1 001 Intel Mode 1 1 MO 010 Intel Mode 2 011 Intel Mo
103. addressing scheme in their provisions for absolute memory reference Consult your programming manual to find out how to read and write absolute memory locations It does not matter how you divide the address specification between SEGMENT and OFFSET but for simplicity we will assume that the SEGMENT is chosen so that the base address of the Carrier is at OFFSET 0 When OFFSET is 0 the 20 bit ADDRESS will correspond exactly to the setting of the base address switches on the Board Information on how to set the address switches can be found in chapter 2 7 4 3 REGISTER OFFSETS The register offsets from the Board s base address are given in table 7 3 All register addresses are expressed in hexadecimal This table also tells whether the registers are read write or read write and summarizes each register s functions The remainder of the section describes each of registers individually TABLE 7 3 Register Offsets Read Write Offset hex Function 000 R ID Code 1 W Interrupt Status Mode 001 R System Status W Interrupt Status Clear 002 R DMA Start W DMA Mode 003 R DMA Stop 004 R ID Code 2 005 Reserved 040 R W Low Order Pacer Counter 041 R W High Order Pacer Counter 042 R W Delay Counter 043 W Pacer Delay Control Register 044 OFF Reserved 100 R ID Code 3 101 R LSB analog data 102 R MSB analog data 103 R W Start Conversion 104 W Input Channel 105 W Scanner Start Channel PCI 20091W 1 7 5 PCI 20091W 1 High
104. aligned on an even 16 byte paragraph Internal error Pass count too large The pass count specified would cause the data acquisition buffer size to be exceeded No High Speed Mode 2 function Data acquisition in High Speed Mode 216 not supported by this software No High Speed Mode 3 function Data acquisition in High Speed Mode 3 is not supported by this software Illegal channel sequence Illegal I O type The specified pacer or trigger type is not sup ported by the PCI 20091W 1 Board PC1 20091W 1 6 27 PCI 20091W 1 High Speed Analog Input Board 6 6 5 15800 15801 15804 15805 15806 15807 15809 15810 15811 15814 15817 15818 15823 16000 16001 16002 16005 16100 15 800 16 499 DMA Error Codes No DMA function The PCI 20091W 1 Board has not been jumper configured for DMA operation No DMA buffer 200925 1 software was loaded without DMA buffer The software package should be removed and reloaded specifying a buffer of the desired size Configuration error All specified channels are not on the same Board Invalid mode An incorrect DMA acquisition mode was specified DMA configuration error A successful DMA configuration was not performed prior to attempting a DMA acquisition read status check or stop Invalid pass count A pass count of 0 was specified or the pass count specified would exceed the size of the data acquisition buffer DMA ove
105. alog Input Module installed in Module Position 1 It does not support all hardware interrupt sources Using the 200925 Software Drivers the Board can be combined with one or more other PCI 20091W 1 Boards or with one or more PCI 20041C Carriers with or without PCI 20019M 1A Modules The PCI 20092S Software Drivers will not sup port digital I O functions of the PCI 20041C Carriers The included 200925 1 Software Drivers support Microsoft QuickBASIC and the high speed and DMA functions of your Board see chapters 4 and 5 They also support all functions of the PCI 20091W 1 Board as performed by the PCI 20041C Carrier without digital in combination with the PCI 20019M 1A High Speed Analog Input Module Please note that the PCI 20041C 3A is more complex than the PCI 20091W 1 it therefore has greater flexibility and more capabilities The PCI 20091W 1 Board is compatible with the PCI 20026S Software Drivers the 200465 Software Drivers version 3 0 and later and with all members of the PCI family of hardware products If you choose to combine the PCI 20091W 1 Board with any PCI hardware products except the PCI 20041C Carrier or the PCI 20019M Module you must have the PCI 20026S Software Drivers in order to support the functions of each component in the system PCI 20091W 1 1 3 PCI 20091W 1 High Speed Analog Input Board INN VOBINSSE 16002 avoas 100 54 1 3 gt
106. am the automatic channel scanner by writing the same channel number you used in Step 2 to BYTE 105 Step 4 Wait for a hardware initiated conversion to complete To test whether the conversion is complete read the conversion status in the ap propriate bit of BYTE 001 Step 5 Read the converted data from WORD BA 101H Repeat Steps 4 and 5 until data acquisition is complete 7 5 4 DELAY COUNTER INITIALIZATION PROCEDURE This procedure initializes the Delay counter 7 14 PCI 20091W 1 Chapter 7 Hardware Technical Reference Step 1 Write the control byte to the control register BYTE BA 043H This programs the delay counter for Intel Mode 0 binary code and 16 bit read write format The count register is reset counting is dis abled and the output signal is set low Step 2 Write the initial count to the count register BYTE BA 042H Write first the low byte and then the high byte of the count Both bytes are written to the same register this is not a WORD operation 7 5 5 DELAY COUNTER ENABLE OR DISABLE PROCEDURE This procedure enables or disables the Delay counter Step 1 Set up the enable byte Since this register controls the Delay counter the Rate Generator clock and the DMA operation you must be sure to set all bits correctly The enable byte should have each bit that corresponds to the Delay counter or rate generator clock section set to a 1 if the section is to be enabled and to
107. and returns control to the original copy of COM MAND COM If you want to continue batch processing you can have PCI 925 run a second batch file or any executable file To do this you must specify the file to be loaded using the X load option switch Example 1 The following batch file calls PCI 92S EXE allocates a 32K DMA buffer starts QuickBASIC PCI 92S G B32 X QB L 3 12 PCI 20091W 1 Chapter 3 Software Installation Example 2 The following batch file which might be an AUTOEXEC BAT file sets up some operating system parameters calls 925 and invokes a second batch file It also invokes internal DOS commands CLS PATH and PROMPT CLS PATH C 3C WORK PROMPT p g 925 2 DATAL The second batch file AUTO2 BAT runs two programs and saves a data file PROGl 71 COPY 21 C PROG2 The 761 symbol passes the parameter to the batch file Batch file process ing is discussed in detail in your DOS manual Note that when the batch files or programs specified by the X switch have finished running and the computer returns to DOS the 200925 1 routines will automat ically unload PCI 20091W 1 3 13 Chapter 4 High Speed Acquisition A 4 1 Introduction and Chapter Overview This chapter contains an in depth discussion of the concepts related to High Speed analog acquisition and how the PCI 20092S 1 Software
108. anded memory conforming to the Lotus Intel Microsoft PCI 20091W 1 2 1 PCI 20091W 1 High Speed Analog Input Board LIM specification we recommend that you configure this memory to start at address 00000 Hex in order to ensure the availability of addresses between CD000 and CFC00 for your Board Refer to figure 2 1 for an illustration of the IBM PC AT memory map and the recommended locations for addressing your Board Factory configuration of the Board s address 15 segment hex The base address of the 1 Kbyte block to be used is selected by switches 1 through 10 on the Board with switch 1 corresponding to address bit 10 and switch 10 corresponding to address bit 19 A switch setting of OFF determines a bit value of 1 and a setting of ON determines a bit value of 0 Figure 2 2 illustrates several Board addressing examples showing how to set the switches for addresses CDC00 CD000 CD400 and CD800 Hex Please note that the Board s base address as set by the switches is expressed as a five digit Hex number 20 bit binary number in which bits 10 through 19 may be switched The Segment Offset address that results from the physical switch setting is also shown for each example 2 2 PCI 20091W 1 Chapter 2 Hardware Configuration FFFFFF 100000 FFFFF 20000 EFFFF E0000 DFFFF 00000 CFFFF CCFFF C8000 C7FFF C4000 C3FFF C0000 BFFFF B0000 AFFFF A0000 OFF
109. annel To disable a channel write a zero to it 6 24 PCI 20091W 1 Chapter 6 Software Technical Reference 6 6 Software Error Codes 200925 1 Software Drivers quite failure resistant When a failure does occur either because of internal error or because of inappropriate user requests the system does not lock up Instead the system simply returns to the user s QuickBASIC program and leaves the error code register of the Software Drivers set with a number corresponding to the error that occurred This error code can be read using the ERR SYS System Error instruction The only exception is the case in which a Software Drivers instruction is called using an incorrect number of arguments In this case the return to QuickBASIC will be incorrect and there is a possibility that the computer will lock up requiring a system reset The error codes represent three types of errors Internal errors are caused only by software inconsistencies Any such errors should be reported to the factory imme diately Hardware incompatibility errors are primarily due to unrecognized PCI 20091W 1 IDs and could result from using hardware which postdates the version of the Software Drivers that is being used User errors result from improper calls by the user Sections 6 7 1 through 6 7 6 give the error code values returned by the ERR SYS instruction and a brief description of each 6 6 1 0 99 System Error Codes Error C
110. ardware level functions of the individual Modules and Carriers are supported as well as various system configurations such as multiple channel high speed analog acquisition Each of the components of the PCI 20000 System is fully described in its own User s Manual In addition a PCI 20000 System User s Manualis provided to explain how to put a system together and install it in a computer The System Manual also contains useful tutorial information on computer and data acquisition concepts We recommend that you become familiar with the 20000 System by reading the System Manual first and then the User s Manual for each of the components you have chosen for your application Utt Chapter 1 Introduction 1 4 Manual and Chapter Overview Congratulations on purchasing another quality member of the PCI family of products You will find that this product provides you with an easy to use high speed analog input system capable of supporting high speed and direct memory access DMA data acquisition techniques This manual is organized into seven chapters The first chapter is an introduction to the manual an introduction to the PCI family of products and an introduction to the product you have just purchased Chapter 2 tells you how to install your hardware and chapter 3 tells you how to install your software Chapters 4 and 5 cover the details of high speed data acquisition and Direct Memory Access DMA data acquisition Chap
111. at of the returned status is given in table 7 8 TABLE 7 8 Offset 040 or 041 Returned Status Format Bit Name Function 7 OUTPUT OUT low 1 OUT pin high 6 NULL COUNT 1 null count 5 programmed 4 RWO Read Write mode 3 M2 programmed 2 M1 1 MO Intel Mode 0 BCD programmed BCD Bits 0 5 are equal to the previously programmed mode of the counter Note The term Intel Mode refers to the Intel 8254 counter timer modes This mode is distinct from DMA Mode Offsets 044 OFF Reserved Offset 100 ID Code 3 READ ID Code 3 bits 0 7 Reading this register returns an ID code This code indicates whether or not the Board is configured for automatic channel scanning See section 2 5 for a discussion of configuring automatic channel scanning PCT 20091 W 1 7 11 PCI 20091W 1 High Speed Analog Input Board C4 Automatic channel scanning enabled C5 Automatic channel scanning disabled These are the same ID codes that are returned from a PCI 20019M 1A High Speed Analog Input Module They must be used in order to maintain compatibility with older versions of the software drivers 200465 and 200475 and older ver sions of PCI 20092S Software Drivers WRITE NOT USED Offset 101 LSB Analog Data READ LSB Analog Input Data bits 0 7 Reading this register returns analog conversion data that is right justified in the following format 07 ps pi po
112. ata Isb where Isb range top range bottom 4096 ERRORS Any error encountered during a read of an analog input will cause the returned data to be set to 1 6 22 PCI 20091W 1 Chapter 6 Software Technical Reference X H Se TS SYSINIT System Initialize Utility Instruction PURPOSE Initialize the Software Drivers system memory area This instruction must be called prior to any other call SYNTAX CALLS ABSOLUTE SYSINIT ARGUMENTS None REMARKS This instruction completely initializes the Software Drivers system including setting up all of the internal variables and initializing the system data area SYSINIT is normally called only once during ex ecution of a program 20091 1 6 23 PCI 20091W 1 High Speed Analog Input Board WRITE CH Write Channel Write Instruction PURPOSE Enable or disable a PCI 20091W 1 rate generator channel SYNTAX CALLS ABSOLUTE VALU WRITE CH ARGUMENTS 1 IO TYPE Integer specifying the I O type of the channel to be written Must be 2 CHN Integer specifying the channel number to be written to 3 VALU Data value to be written REMARKS This instruction writes to the output device specified by arguments 1 and 2 The third argument is written to the output To enable a rate generator channel write any non zero value to that ch
113. atic channel advance disabled the channel list may consist of any single channel of type ALT If the PCI 20091W 1 is configured with automatic channel advance enabled the channel list may consist of a channel sequence in numerical order beginning with where lt 7 and ending with 6 9 PCI 20091W 1 High Speed Analog Input Board 7 The first channel N has type ALT and subsequent channels have type AIX T The following examples illustrate each case SINGLE ANALOG INPUT CHANNEL Channel 3 on the 20091 1 is read PCI 20091W 1 must configured with automatic channel advance disabled Type Channel Number ALT 3 SEVERAL ANALOG INPUT CHANNELS Channels 4 5 6 and 7 are read PCI 20091W 1 must be con figured with automatic channel advance enabled Type Channel Number 4 AIX T 5 AIX T 6 AIX T 7 The channels on the following list are NOT LEGAL because the channels are not consecutive If CNEDMA encounters a channel list like this it will return an error ILLEGAL CHANNELS Type Channel Number ALT 2 AIX T 5 AIX T 6 AIX T 7 PCI 20091W 1 Chapter 6 Software Technical Reference meee Abeer 6 Lechnical Reference CNF HS Configure High Speed Configuration Instruction Oe PURPOSE SYNTAX ARGUMENTS REMARKS Configures the system for high speed analog acquisition CALLS ABSOLUTE PAC TYPE PAC CHN MODE TR
114. atic channel advance wrap around 5 5 DMA 6 9 High speed data acquisition 6 11 Automatic channel sequencing 5 A 7 13 Calibration 7 1 CALLS QuickBASIC command 6 1 6 7 B Channel advance automatic and manual 6 9 6 11 Background operation Channel list tren 54 69 PCI 20091W 1 INDEX 1 PCI 20091W 1 High Speed Analog Input Board high speed data acquisition 6 11 analog 2 12 illegal for 6 10 digital F3 2 12 Channel numbers Constants analog 2 12 defined in PCIHEADQ BAS 6 1 assigned by software 6 3 ly pes coquit 6 7 numbering sequence 6 3 Channel programming FE BIS CED sos a tie geh qut 7 13 D Channel scanner start register 7 13 Data acquisition Channel scanning sequence procedure with hardware timing 7 14 configuration 1 4 4 2 7 Data frames iias 5 5 factory configuration 2 7 5 6 2 7 5 6 7 11 frame map 5 6 Channel selection DEF SEG QuickBASIC command 6 2
115. ble DMA operation on the PCI 20091W by writing 22H to BYTE BA 002 Set up the analog input channel sequence as described in section 7 5 2 DATA ACQUISITION WITH HARDWARE TIMING Enable the IBM PC s DMA Start the DMA process by reading BYTE BA 002 Enable the rate generator as described in section 7 5 7 RATE GENER ATOR ENABLE OR DISABLE PROCEDURE The Board s DMA operation must be started Step 8 before starting the rate generator or the analog input channels may be rotated The DMA process will stop after the specified number of bytes have been transferred You can determine when the process reaches ter minal count by monitoring bit 2 of BYTE BA 001 7 5 11 DMA MODE 3 PROCEDURE This procedure describes DMA Mode 3 operation If the External Start Convert input is used as the pacing source omit the rate generator programming Step 1 Step 2 Step 3 Step 4 Step 5 First make sure that the source of A D start convert signals is disabled The on board rate generator can be disabled by clearing bit 3 of BYTE BA 002 Setthe on board rate generator frequency as described in section 7 5 6 RATE GENERATOR INITIALIZATION PROCEDURE Reset the PCI 20091W s DMA controller by writing 00H to BYTE 002 Set up the delay counter as described in section 7 5 3 DELAY COUNTER INITIALIZATION PROCEDURE and section 7 5 4 DELAY COUNTER ENABLE OR DISABLE PROCEDURE Configure the PC s DMA controller for auto
116. ction 7 4 for a complete discussion of I O registers Software start convert is appropriate for acquiring randomly timed chan nel samples Start convert on read of MSB data is included for backward com patibility with other PCI products and is not a recommended method TABLE 2 2 Start of Conversion Jumper Settings Jumper Settings Source Jumper IN Jumpers OUT External Start Convert W20 W12 W13 Rate Generator W12 W13 W20 Read of MSB data W13 W12 W20 Factory configuration 2 5 Channel Scanning Sequence The input channel may be selected by a hardware channel scanner or under software control The hardware scan selects channels N through 7 in sequence where N is an integer from 0 to 7 The scanner must be enabled by setting jumpers as shown in table 2 3 The channel is advanced by a signal derived from the analog to digital A D converter s end of convert EOC line The input channel may be selected in software by writing the desired channel to a channel selection register Programming the channel scanner and channel selection are discussed in section 7 4 TABLE 2 3 Channel Scanning Sequence Jumper Settings Jumper Settings Channel Sequence Mode Jumpers IN Jumpers OUT Software Selection W15 W19 W14 Hardware Scan W14 W15 W19 Factory configuration lao RE 2 6 Interrupt Levels and Sources The PCI 20091W 1 provides a PC interrupt IRQO the level and source of which
117. de 3 100 Intel Mode 4 101 Intel Mode 5 BCD 0 Binary 1 BCD To program the Rate Generator in Intel Mode 2 2 byte LSB then MSB data transfer write the codes given in table 7 6 to Offset 043 TABLE 7 6 Offset 043 Rate Generator RG Programming Codes If you wish to program Program Offset these registers to the 043 to this Intel Mode at right Hex code Register Offset Intel Mode Control Code RG LSW 040 2 34 Hex RG LSW 040 3 36 Hex RG MSW 041 2 74 Hex RG MSW 041 3 76 Hex After the counters have been configured the count registers may be initialized or read To read the counter s data or status the read back command should be issued to the control register The format of the read back command is shown in table 77 7 10 PCI 20091W 1 Chapter 7 Hardware Technical Reference TABLE 7 7 Offset 043 Counter Data and Status Read Command Format Bit Name Function 7 SC1 1 read back command 6 SCO 1 read back command 5 COUNT 0 latch count 4 STATUS latch status 3 Delay 1 select Delay counter 2 RG MSB 1 select MSB of RG 1 RG LSB 1 select LSB of RG 0 0 To set the Delay counter for read back the command word to be written to Offset 043 is 11001000 C4 Hex This latches both the count and the status of the Delay counter The status is returned in the first read of the Delay counter Offset 042 The next two reads from the Delay counter give the two count bytes The form
118. de Buffer DMA STAT DMA Status or DMA STOP Stop DMA instructions are called Use the ERR SYS System Error instruction to check for the overrun error code TABLE 5 1 Effect of the DMA Process on Foreground Programs Percent Degradation of DMA Transfer Rate Foreground Program in Ksamples per Second Execution Speed 10 4 50 15 70 23 89 30 Because of the effect of the DMA process on foreground program execution you must use caution if your foreground program is performing time critical tasks such as high speed data acquisition 5 7 DMA Buffers A data buffer is a block of program memory used for temporary storage of input data during data acquisition The PCI 20092S 1 Software Drivers store data in an input buffer during a DMA data acquisition process When the process is complete the 4 PCI 20091W 1 Chapter 5 DMA Senna application program can read the data from the buffer and process display or store it Details on loading buffers are in given in section 2 6 5 7 1 BUFFER SIZE Because of the internal design of IBM PCs and compatibles a DMA process cannot automatically transfer data into or out of a buffer which crosses a 64 Kbyte page boundary A 64 Kbyte page boundary is a memory address evenly divisible by 65536 10000 Hex The 640 Kbyte DOS memory space comprises ten pages For this reason the DMA Modes on this Board are limited to a maximum of 64 Kbytes of data 5 7 2 BUFFER DATA O
119. e Software Drivers will display a sign on message After the drivers have been successfully loaded you will see a DOS sign on message and a DOS prompt If the file COMMAND COM cannot be found or if other errors are encountered you will see an error message after the 200925 1 sign on messages For more information on this and other error messages see the discussion below The Software Drivers routines are automatically unloaded along with the second of COMMAND COM when the DOS command EXIT is typed You will see the message PCI 200928 End of execution PCI 20091 W 1 Chapter 3 Software Installation when 925 terminates Note that if you run batch files which contain the EXIT command for the purposes of nesting batch files you may inadvertently remove the resident Software Drivers routines 3 7 1 ERRORS WHILE LOADING THE SOFTWARE DRIVERS If an error usually command line error is detected during preliminary processing the software may display one or more of the following messages Invalid dispatch vector COMSPEC not set in environment Invalid execute specification Memory allocation error Se ale ate Unrecognized switches The software drivers perform a timing calibration test on your computer during the load process If this test fails you may see one of the following messages System clock driver not running R Interrupts detected level s
120. ection 2 2 This instruction initializes the system to support an installed PCI 20091W 1 All rate generator channels are disabled by the INIT call PCI 20091W 1 must have previously been set up with its address switches to have its segment address specified by the argument When multiple PCI 20091W 1 Boards are installed in your computer INIT each of them in decreasing order of segment addresses Refer to section 6 3for a detailed discussion of the initialization procedures for the PCT 20091W 1 PCI 20091W 1 6 21 20091 1 High Speed Analog Input Board READ CH Read Channel Read Instruction PURPOSE SYNTAX ARGUMENTS REMARKS Read the specified analog channel and return the value read CALLS ABSOLUTE IO TYPE CHN STOR READ CH 1 type of the desired channel Must be ALT 2 CHN Analog input channel number to read 3 STOR Data read Be sure to predefine this argument by setting it equal to 0 prior to this call A return value of 1 may indicate an error condition This instruction reads the analog input channel specified by the CHN argument An analog conversion is performed by software command On completion the data from the conversion is read and the input value is transferred to the return value variable STOR The data returned by READ CH may be converted to volts by means of the appropriate formula for PCI 20091W 1 analog inputs Volts range bottom 4095 d
121. ection 2 5 e You can configure your Board to generate interrupts specifying the interrupt level and sources section 2 6 You configure your Board for DMA control capability section 2 7 e You may make use of the Rate Generator output signal section 2 8 For installation you will need to know how to physically place the Board into your computer and how to connect your Board to the outside world These topics are covered in sections 2 9 and 2 10 respectively The locations of the jumpers are shown in figure 2 3 Table xx chapter 8 sum marizes the jumper functions Only plug in jumpers are intended to be removed 2 2 Setting the Board Addresses In order to use your Board you must set its base address If this address is not set properly the Board will not work at all and it may prevent other components of your computer system from operating This section describes how to select an address The PCI 20091W 1 system occupies 1 Kbyte of memory space The base address is selected by a 10 position dual in line package DIP switch on the board The range of addresses is from 400 hex segment 40 hex to FFC00 hex segment FFCO hex in hex 400 increments When you choose the base address for your Board be sure to select a location in memory that is not used by any other hardware in your system The particular address you use is determined by the hardware configuration of your system If your computer includes exp
122. els analog input esee 6 22 6 22 Reading hardware registers 74 Register Offsets aeree 74 7 5 Registers analog input channel 7 13 automatic channel sequencing 7 13 Board ID sconto eiut ident 7 6 channel scanning sequence 7 11 delay counter eret 7 9 delay counter control 7 9 delay counter status 7 11 description 7 6 DMA mode 0 7 7 DMA St aft ccssssssonssosecssenscessencesenesssacees 7 7 stop 78 ID code 2 eee rere 7 8 ID code 3 eee rene 7 11 Interrupt Status clear 7 7 Interrupt status mode 7 6 LSB analog data 7 12 MSB analog data 7 12 offset list erre eere ee teens 7 5 rate generator control 7 9 Rate generator LSW 7 8 Rate generator 7 8 rate generator 5 7 11 reading and writing 7 4 scanner start channel 7 13 start of conversion 7 12 system status
123. er plot to 100 1 19 CONST MAXPLOTS 16 CONST PASSES 100 CONST MAXWINDS 9 27 CONST 1 CONST TOPX 2 CONST BOTY 3 CONST TOPY 4 22 The arrays are dimensioned This is done once at the beginning of the 24 program 25 DIM FRAME 4 MAXWINDS 20 DIM Y MAXPLOTS PASSES 28 The following program sets up 8 data sets to demonstrate the plotting 56 routines 51 First define the windows to plot data in InitWindow FRAME 22 Set up test data Define 8 data sets to plot 37 FOR I 1 TO 100 38 1 I INT 50 SIN I 3 14 50 39 2 I INT 1 I I 40 Y 3 I Y 1 I 1 Y 2 41 4 I 1 Y 1 I Y 2 I 42 Y 5 I 20000 RND I 10000 43 Y 6 I 10 LOG I 5 44 Y 7 I 25 COS I 3 14 25 I 25 45 Y 8 I INT I 20 47 NEXT I 15 Finally plot the data sets 50 CLS 51 LOCATE 10 32 52 PRINT Ready to plot 53 LOCATE 12 14 24 PRINT Press any key when you are ready for the next screen 55 WaitKey 56 PLOTNO 1 8 59 FOR SETNO 1 TO 2 60 FOR WINDNO 1 TO 4 61 PlotData FRAME Y PLOTNO WINDNO 62 PLOTNO PLOTNO 1 63 NEXT WINDNO 64 WaitKey 52 NEXT SETNO 67 WINDNO 5 68 FOR PLOTNO 1 TO 2 69 PlotData FRAME Y PLOTNO WINDNO 70 WaitKey 5 NEXT PLOTNO 73 PLOTNO 3 74 FOR SETNO 1 TO 2 75 FOR WINDNO 6 TO 7 A 16 PCI 20091W GRAPH BAS eee GRA BAS 76 PlotData FRAME PLOTNO WINDNO 77 PLOTNO PLOTN
124. ers hardware initialization Sections 6 4 and 6 5 pro vide a reference guide to the individual calls you will need to use Section 6 6 lists and describes the error codes you may get 6 2 Creating Application Programs This section should get you started writing QuickBASIC application programs for your PCI 20091W 1 hardware Before you begin to work on your own programs you may wish to try out some of the Sample Programs on the PCI 20092S 1 diskette to familiarize yourself with the system When you start QuickBASIC you must load the default User Library OB OLB This library contains the ABSOLUTE utility which calls 200925 1 instructions To load the user library type QB L zatthe DOS prompt Some versions of QuickBASIC require that you first create the User Library Refer to your QuickBASIC documentation for details on Quick Libraries You must use the header provided as PCIHEADQ BAS at the beginning of your program The easiest way to incorporate this file into your QuickBASIC program is to use the INCLUDE metacommand SINCLUDE PCIHEADQ BAS in your program as we have done in the Sample Programs listed in appendix A PCIHEADQ BAS sets up constants including the instruction names that you may need in your program and verifies that the correct version of PCI 925 was previously loaded in memory This file also defines the interrupt vector that was used to load PCI 92S EXE 1f you specified an interrupt
125. file SAMPLE PROGRAMS SAMPLE01 BAS GRAPHICS DEMONSTRATION GRAPH BAS OPTIONAL TEXT FILE README Use of the Software Drivers is discussed in the remaining sections of this chapter The Sample Programs are listed in appendix A The optional text file if present contains information that is too recent to appear in this manual and should be read It may be read by typing MORE lt README at the DOS prompt MORE is a DOS external command meaning that it is a file on the DOS diskettes Before you begin to experiment with your Software Drivers you should make a working copy of your master diskette containing a copy of all of the files on your original diskette You should never use the original diskette for everyday opera tions Once you have made this working copy use it for your everyday operations and store your master diskette in a safe place 3 5 1 PROCEDURE FOR ONE OR TWO FLOPPY DISK DRIVES Place your DOS operating system diskette in drive A and type DISKCOPY A B and follow the instructions that appear on the screen to make your working copy This command tells DOS to copy all the files from the diskette in your drive to the diskette in your B drive If you wish to check the integrity of your backup when the process completes place your DOS diskette in drive A again and type DISKCOMP A B to verify that there are no comparison errors Note that DISKCOPY and DIS KCOMP are both DOS external commands meani
126. fines mnemonics for the various I O Type codes which are required by the READ CH Read Channel and WRITE CH Write Channel in structions Note that the entry point offsets and I O type constants must be QuickBASIC integers This is ensured in line 2 which defines all variables except those begin ning with F to be integers we have reserved F for floating point data conversions Therefore be sure to avoid variable names that start with F unless they relate to floating point data conversions 20091 W 1 3 5 PCI 20091W 1 High Speed Analog Input Board 20091 1 MEMORY MAPPED TOP OF SYSTEM RAM BOTTOM OF USER S BASIC PROGRAM USER RAM PCI 192S EXE RESIDENT PROGRAM 200925 1 SOFTWARE SUPPORT ROUTINES HARDWARE DRIVERS SYSTEM CONFIGURATION DATA AREA 3 6 PCI 20091W 1 Chapter 3 Software Installation 1 gt Header File for 200925 1 Microsoft QuickBASIC Applications 2 DEFINT A E G Z 3 Define the internal signature 4 CONST VCHK L 15 VERS L 15 5 DIM VCHK VCHK L VERS VERS L 6 7 8 VERS 1 257 VERS 2 17 VERS 3 17 9 VERS 4 0 10 VERS 5 0 11 VERS 6 17 12 VERS 7 4352 13 VERS 8 0 14 VERS 9 4096 15 VERS 10 4369 16 VERS 11 0 17 VERS 12 0 18 VERS 13 0 19 VERS 14 4352 20 VERS 15 17 21 Define the 200925 1 instruction offsets 22 CONST AUTOGRPH 12 23 CONST BUF DEC 18 24 CONST CNF D
127. flag is set on the PCI 20091W 1 This does not stop the DMA process the next pacing signal will be honored if possible The data however will have gaps PCI 20091W 1 5 3 PCI 20091W 1 High Speed Analog Input Board 5 6 DMA and Foreground Programs The DMA process operates by stealing bus cycles from the processor The programmer needs to be aware that even though a DMA process is running in the background while it is running it will affect the execution speed of any foreground program The faster DMA process is running the slower the foreground program will run DMA Mode 2 will typically not affect foreground program execution since processes in this mode normally don t last long enough DMA Modes 3 and 4 however can have a dramatic but predictable effect on foreground program execution The execution speed of the foreground program is affected by the DMA rate the average number of bytes per second being transferred Table 5 1 shows foreground program speed degradation versus byte per second DMA transfer rate for an IBM XT This table may be used as a guide We recommend that you test for a maximum DMA transfer rate using the conditions under which you intend to run your application This may be accomplished by setting up a DMA run and then monitoring the overrun flag in the host computer Increase the rate of DMA transfers until the flag becomes true The overrun condition will set an error code when the BUEDEC Deco
128. fore making large adjustments 2 Remove the cover from the computer following the manufacturer s instructions 3 If you haven t already done so install your Board see chapter 2 4 Connect any additional cables into the Termination Panel s 5 Turn on the power to the computer Allow at least 10 minutes warm up time before continuing 6 Connect the calibrator to Channel 0 and set its output following the guidelines given in table 7 1 TABLE 7 1 PCI 20019M 1A Calibration Set Points Module Input Range Calibrator Output 5 V 4 9988 V 0to 10V 1 22 mV 10 V 9 9976 V Oto 5V 0 610 2 5 V 2 4994 V 7 Start the sampling program Adjust Pot R4 until the reading displayed on the computer is alternating between 4094 and 4095 8 Set the output of the calibrator using the data in table 7 2 TABLE 7 2 1 20019 1 Calibration Set Points Module Input Range Calibrator Output 5 V 4 9963 V Oto 10V 9 9963 V 10 V 3 9 9927 V Oto 5 14 9982 V 2 5 V 2 4982 V 7 2 PCI 20091W 1 Chapter 7 Hardware Technical Reference 9 Adjust Pot R3 until the reading alternates between 0 and 1 10 Replace the cover on your computer 11 End of test and calibration procedure 7 3 Doing It Yourself Hardware Programming We highly recommend our 200265 200275 200925 Software Drivers These Software Drivers are efficient and provide most functions that you might w
129. grams 6 1 DMA sampling 5 4 3 3 hardware 4 7 1 x Testing sampling rates high speed data acquisition 4 3 device drivers and 3 10 Time base Software requirements sss 3 2 high speed data acquisition 41 Software start 2 2 2 6 Timing CODD gurges cespite 2 7 data acquisition 1 10 0 6 14 read MSB 2 7 high speed data acquisition saute 4 3 6 11 eb TR 7 12 Trigger Source event high speed data acquisition 6 11 DMA 5 2 Trigger event Specifications D M RT 5 2 Trigger functions ette 12 Speed Trigger source data acquisition 41 4 1 1 high speed data 42 Start of conversion TSR programs 4 4 44700 4 0 0 4 7 3 10 choosing SOURCE v cccsssscascsessoastsvontancniasses 2 6 INDEX 8 PCI 20091W 1 INDEX U Unique Board ID oi iinis 7 8 Dass 7 6 Unloading Software Drivers 3 8 3 13 Variables declaring in QuickBASIC 6 1 6 7 naming
130. he Pacer External Interrupt and Terminal Count status bits read from Offset 001 below are latched The PCI 20091W 1 Chapter 7 Hardware Technical Reference External Interrupt hardware interrupt signal is also latched The A D converter End Of Convert status bit is always latched Offset 001 System Status Interrupt Status Clear READ System Status bits 0 5 Reading this register returns system status information which can be interpreted using the information below The DMA terminal count signal must be latched to be used properly during DMA input bit5 AIEOC A D converter End of Conversion bit4 Rate generator output status bit3 EXTINT interrupt status External Interrupt bit2 DMA terminal count interrupt status bit1 1 DMA overrun bit0 1 DMA in progress WRITE Interrupt Status Clear data ignored Writing any data to this register clears an interrupt generated from the External Interrupt input and also clears the System Status Register Offset 002 DMA Start DMA Mode READ Start data undefined Reading this register initiates anew DMA transfer sequence The data read has no meaning WRITE DMA Mode bits 0 5 Writing to this offset sets the DMA Mode and enables or disables the DMA Trigger Delay the Rate Generator and DMA operations as shown below bit5 0 init DMA 1 enable DMA bit4 0 disable Delay 1 enable Delay bit 3 0 disable Rate Generator 1 enable Rate Generator
131. ibed in Chapter 5 3 7 Loading the Software Drivers Routines 3 8 The 925 Software Driver routines must be loaded before running any application program which calls them The Software Drivers routines must be loaded from DOS before starting QuickBASIC They cannot be loaded from QuickBASIC s DOS command utility If you create an application program you will not be able to run it unless the Software Drivers routines were loaded before you began your session If this was not done you will have to save your work and exit to DOS load PCI_92S EXE and then resume your work If you compile your QuickBASIC application to an EXE file to be run after you exit QuickBASIC you do not have to load the Software Drivers until you are ready to run the application To load the PCI 20092S Software Drivers place your work disk in the computer or select the directory on your fixed disk containing the Software Drivers files At the DOS prompt type PCI 925 1 61 X text then press the RETURN key Actual examples are given in section 3 7 4 EXAMPLES OF LOADING THE SOFTWARE DRIVERS below The switches are described below and are summarized in table 3 1 You must have a copy of the DOS file COMMAND COM in the drive you use to boot your system normally A or PCI 92S EXE loads a second copy of MAND COM which requires about 3 5 KBytes in addition to the memory allocation of the Software Drivers routines themselves Th
132. iming the data acquisition sampling rate is determined by the rate generator counts n1 and n2 in the CNERG instruction 4 2 20091 1 Chapter 4 High Speed Acquisition SE Refer to the discussion of the CNERG instruction in chapter 6 for details on setting this frequency Tests performed using an IBM PC with an 8088 microprocessor and an internal clock speed of 4 77 MHz and an IBM AT with an 80286 microprocessor and an internal clock speed of 6 MHz resulted in sampling rates of 62 500 samples second and 89 000 samples per second respectively Faster times are possible if you use a computer with a faster internal clock a faster microprocessor or both 4 3 2 TESTING HIGH SPEED SAMPLING RATES These paragraphs provide a suggested test procedure for determining the maximum high speed data acquisition rate possible for your configuration More information on calculating the sampling rate can be found in chapter 6 under the description of the CNERG instruction Connect input channels 0 through 7 of the PCI 20091W 1 to a known static input pattern For example Channel 0 0 volts Channel 1 1 volt Channel 7 7 volts Jumper the PCI 20091W 1 for automatic channel advance see section 2 5 for infor mation on setting jumpers for channel advance Perform a high speed acquisition with the channel list consisting of the above channels Examine the data for several runs of several passes each to ve
133. initialize operation and set the base address byte count registers and terminal count When the DMA controller reaches the programmed terminal count it will reset its address to the base address and continue 20091 1 7 17 PCI 20091W 1 High Speed Analog Input Board Step 6 Step 7 Step 8 Step 9 Step 10 Step 10 Step 11 Program DMA Mode 3 and enable DMA operation and the Delay Counter on the PCI 20091W by writing 33H to BYTE BA 002 Set up the analog input channel sequence as described in section 7 5 2 DATA ACQUISITION WITH HARDWARE TIMING Enable the IBM PC s DMA Enable the DMA process by reading BYTE BA 002 Enable the rate generator as described in section 7 5 7 RATE GENER ATOR ENABLE OR DISABLE PROCEDURE The Board s DMA operation must be started Step 9 before starting the rate generator or the analog input channels may be rotated The DMA process will stop after the specified number of bytes have been transferred You can determine when the process reaches ter minal count by monitoring bit 2 of BYTE BA 001 The DMA process will stop after the specified delay from the DMA Trigger event You can determine when the process reaches terminal count by monitoring bit 7 of the Delay Count Status register which can be read as described in section 7 55 DELAY COUNTER READ PROCEDURE 7 5 12 DMA MODE 4 PROCEDURE This procedure describes DMA Mode 4 operation If the External Start Co
134. instruction P3 2 External Start Convert This TTL level input initiates an A D conversion cycle on a low to high edge The Analog Input section must be properly jumpered for this option see section 2 4 P3 3 Convert Inhibit Taking this pin to a TTL low level will inhibit any further A D conversions from occurring This signal does not affect software start convert commands P3 5 External Interrupt This signal can be connected to generate a PC interrupt when taken to a TTL low level see section 2 6 In DMA Mode 3 it can generate the DMA Trigger on a high to low transition This signal is also available as a bit in the PCI 20091W 1 Status Register which may be polled by a software P3 6 Digital Ground Used for digital return on P3 P3 7 5 Volt Source This source is current limited at 250 mA in addition to the limitation on Connector P2 PCI 20091W 1 Chapter 2 Hardware Configuration P2 CHANNEL PILA RESERVED ANALOG COMMON X X RESERVED CHANNEL 1 IN ANALOG COMMON CHANNEL 2 IN 04 RESERVED ANALOG COMMON RESERVED CHANNEL 3 IN ANALOG COMMON CHANNEL 4 IN x RESERVED RESERVED RESERVED CHANNEL 5 IN ANALOG COMMON CHANNEL 6 IN RESERVED RESERVED RESERVED CHANNEL 7 IN ANALOG COMMON RESERVED 5 PS FUNCTION Fig 2 4 Connector pin assignments PCI 20091W 1 a Analog and b Digital RATE GENERATOR OUT EXTERNAL START CONVERT CONVERSION INHIBIT RES
135. ish to implement with your board and they can save you a great deal of time However if you wish to write your own software the following sections provide important information The PCI 20091W 1 Board has certain functions that are programmed by reads and writes to various registers offsets While a discussion of the individual offsets is given in section 7 4 this section gives an overview of the operation of these func tions and of the offsets needed to properly program these functions 7 3 1 ANALOG TO DIGITAL A D CONVERTER The A D converter provides an A D Status signal which goes low whena conversion is completed It is set high when the most significant byte MSB of data is read The A D status can be read in Offset 01 When the conversion is completed the data must be read before another conversion is started or the data will be lost A read of Offset 101 Hex returns the least significant 8 bits of data A read of Offset 102 Hex returns the most significant 4 bits of the 12 bit conversion in a right justified format 7 3 2 GENERATOR The PCI 20091W 1 provides a rate generator that outputs a variable duty cycle mode 2 or square wave mode 3 TTL levelsignal The output period is set by the following formula Period 1 2 8 10 where 1 is the rate generator low order 16 bits and 2 is the rate generator high order 16 bits N1 and N2 can be programmed with values from 2 to 65536 to produce a
136. king place You can allocate memory for a data buffer when the PCI 20092S 1 drivers are loaded by setting a switch on the command line See section 3 7 for details on switches 5 1 2 SEQUENCE OF OPERATION The PCI 20092S 1 Software Drivers sets up the PCI 20091W 1 and the host PC to _ perform a DMA process The hardware then performs the data acquisition process While the DMA process is running in the background control returns to the user s application program and other processing may occur in the foreground The application program can query the Software Drivers for the status of the DMA process and monitor the data being acquired When the process terminates the application program can process the acquired data PCI 20091W 1 5 1 PCI 20091W 1 High Speed Analog Input Board 5 1 3 INFORMATION REQUIRED FOR RUNNING DMA Once the decision has been made to use a DMA process for data acquisition the following questions should be considered 1 What data is to be transferred by DMA The PCI 20091W 1 can transfer data from one to seven analog input channels The desired inputs must be connected to appropriate channels and automatic channel sequencing must be enabled if ap propriate 2 How much data is to be transferred An adequate data buffer must be available and the software must be programmed accordingly 3 How is the DMA process to stop The DMA process can acquire a specific amount of data or it can terminate when a specific
137. made minor corrections ECO 89091902 Major modifications to software section 521 PCI 20091W 1 High Speed Analog Input Board USE OF EQUIPMENT Burr Brown Corp assumes no responsibility for any direct indirect or consequen tial loss or damages resulting from misuse of the equipment or for improper or inadequate maintenance of the equipment or for any such damage or loss resulting from the use of other equipment attachments accessories and repairs at any time made to or placed upon the equipment or any replacement thereof Furthermore Burr Brown Corp makes no representations or warranties either expressed or implied in connection with the use of the equipment in the event it is improperly used repaired or maintained WARNING Lethal voltages exist inside computers Always ensure that power is removed before opening the case Only qualified technicians should in stall modify or adjust equipment inside any computer unit CAUTION Failing to turn off the power when inserting or removing boards will damage the boards and possibly the computer as well FCC Radio Frequency Interference Statement This equipment generates and uses radio frequency energy and may cause inter ference to radio or television reception Per FCC rules Part 15 Subpart J operation of this equipment is subject to the conditions that no harmful interference is caused and that interference must be accepted that may be caused by other i
138. ncidental or restricted radiation devices industrial scientific or medical equipment or from any authorized radio user The operator of a computing device may be required to stop operating his device upon a finding that the device is causing harmful interference and it is in the public interest to stop operation until the interference problem has been corrected The user of this equipment is responsible for any interference to radio or television reception caused by the equipment It is the responsibility of the user to correct such interference PCI 20091W High Speed Analog Input Board Table of Contents Preface CHAPTER 1 INTRODUCTION 11 Manual Chapter Overview 1 1 1 2 20091 1 High Speed Analog Input Board Description 1 1 SUMMA oe ak eee tnd QU a 1 1 1 22 DEFINITIONS AND CAPABILITIES 1 2 1 2 3 MINIMUM REQUIREMENTS FOR USING THIS PRODUCT 1 2 1 3 PCI System Compatibility and Emulation 1 3 CHAPTER 2 HARDWARE CONFIGURATION AND INSTALLATION 2 4 Configuration and Installation An Overview 2 1 22 Setting the Board Addresses 2 1 2 3 Analog Input Voltage Ranges 2 6 24 Start of Conversion 2 6 25 Channel Scanning Sequence
139. ng they are files on the PC DOS PCI 20091W 1 3 w 20091 1 High Speed Analog Input Board cr MS DOS system diskettes If you have only one floppy disk drive the same commands will work just follow the instructions on the screen After you have copied your software drivers diskette store your original diskette in a safe place and use the working copy for all subsequent operations 3 5 2 PROCEDURE FOR ONE FLOPPY DISK DRIVE AND A FIXED DISK DRIVE If you have a fixed hard disk drive and only one floppy disk drive you can create a backup while installing the software on your hard disk First create a subdirectory by typing the DOS command MD subdirectory This tells DOS to Make a Directory with the name you type in after MD Note that the restrictions on file names also apply to directory names they can only be eight characters long with an optional three character extension See your DOS manual for further details After you have created a subdirectory place your master diskette in your floppy disk drive the A drive and type at the DOS prompt COPY A C subdirectory V This tells DOS to copy all the files from your A drive to your subdirectory verifying that each file is copied correctly To double check the integrity of your files you might wish to type COMP A C subdirectory This command will cause DOS to compare the files on your master diskette with the files in your subdirectory Note
140. nsfer of data by means of struc tures called data frames Each data frame consists of two bytes which contain the reading from one channel one sample One frame one sample is transferred at each tick of the Start Convert signal for example the PCI 20091W 1 s onboard rate generator Data from the various input channels in the data frames are grouped into clusters Each cluster is associated with one pass through the channel list that you specified in the CNEDMA Configure DMA instruction The number of frames per cluster varies from one to eight depending on how many channels you choose to read PCI 20091W 1 5 5 PCI 20091W 1 High Speed Analog Input Board 200925 1 Software takes care of organizing the frame map in accordance with the information you provide The frame map is used to program the PCI 20091W 1 and to decode data frames It is a list of the I O channels which to involved in the DMA input of data Data frames reside in the buffer in the host computer and contain the actual data that is transferred to or from the I O channels The DMA process transfers data into memory buffers allocated and controlled by the PCI 20092S 1 Software Drivers The DMA process does not directly access your application program memory The Software Drivers provide an instruction BUEDEC Decode Buffer that you may use to retrieve data from the buffer to your program memory This instruction automatically formats the da
141. ntains an introduction to the PCI 20092S 1 Software Drivers DMA processes including a discussion which should help you determine at a high level whether DMA is appropriate to your needs 200275 Software Drivers support nine different DMA modes PCI 200925 Software Drivers as a subset of the PCI 20027S Software Drivers support three of those modes DMA Mode 2 DMA Mode 3 and DMA Mode 4 These modes are described in sections 5 2 5 3 and 5 4 data acquisition rates are discussed in section 5 5 Operating other programs while DMA is in progress is described in section 5 6 Storage of DMA data is discussed in sections 5 7 and 5 8 Programming DMA data acquisitions using the included Software Drivers is described in sections 5 9 and 5 10 5 1 1 DMA INTRODUCTION The 200925 1 Software Drivers DMA makes the full power and flexibility of the PCI 20091W 1 available DMA is a hardware technique that allows you to take data without software intervention This gives you high speed data transfer and true background operation While DMA is running the only computer resources it uses are the memory it is filling up one channel of your computer s DMA controller and the bus cycles necessary to complete the transfers Data transfer speeds up to 89 000 samples per second can be achieved on an IBM XT The 1 200925 1 DMA process uses data buffers locations in memory used to store input data while the DMA process is ta
142. nters driven by an 8 MHz frequency reference These 2 10 PCI 20091W 1 Chapter 2 Hardware Configuration counters are referred to as the Rate Generator s Least Significant Word LSW and Most Significant Word MSW counters 2 9 Installing the Board Into Your Computer The procedure for installing your Board in an IBM PC is described below The procedure for installing the Board in other machines may differ somewhat but will be similar in nature 1 Turn off the power to your computer and unplug it Lethal voltages exist inside computers Always ensure that power is removed before opening the case Only qualified technicians should in stall modify or adjust equipment inside any computer unit CAUTION Failing to turn off the power when inserting or removing boards will damage the boards and possibly the computer as well 2 Remove the five screws on the rear panel of the computer s chassis that hold the cover to the chassis 3 Carefully slide the cover toward the front of the chassis lift it up slightly and remove it 4 Select an empty expansion slot for your Board You will be plugging the Board into this slot 5 Remove the slot cover from the expansion slot 6 Align the Board above its expansion slot connector with the front left edge of the Board pushed against the card guide and the card edge fingers on the Board aligned with the connector in the expansion slot 7 Gentl
143. nvert input is used as the pacing source omit the rate generator programming Step 1 Step 2 Step 3 Step 4 Step 5 Step 6 Step 7 Step 8 First make sure that the source of A D start convert signals is disabled The on board rate generator can be disabled by clearing bit 3 of BYTE BA 002 Set the on board rate generator frequency as described in section 7 5 6 RATE GENERATOR INITIALIZATION PROCEDURE Reset the PCI 20091W s DMA controller by writing to BYTE BA 002 Configure the PC s DMA controller for auto initialize operation and set the base address byte count registers and terminal count When the DMA controller reaches the programmed terminal count it will reset its address to the base address and continue Program DMA Mode 4and enable DMA operation on the PCI 20091W by writing 24H to BYTE BA 002 Set up the analog input channel sequence as described in section 7 5 2 DATA ACQUISITION WITH HARDWARE TIMING Enable the IBM PC s DMA Start the DMA process by reading BYTE BA 002 7 18 PC1 20091W 1 Step 9 Step 10 Chapter 7 Hardware Technical Reference Enable the rate generator as described in section 7 5 7 RATE GENER ATOR ENABLE OR DISABLE PROCEDURE The Board s DMA operation must be started Step 8 before starting the rate generator or the analog input channels may be rotated Stop the DMA process by reading BYTE BA 003 7 6 Jumper Definitions Summary
144. o scale and plot the data in the previously defined 134 window 136 gt First find minimum and maximum data values and calculate scaling 137 constants to plot the data in a window 139 YMIN Y PLOTNO 1 YMAX Y PLOTNO 1 140 POINTS UBOUND Y 2 14 142 FOR I 2 TO POINTS 143 IF Y PLOTNO I gt YMAX THEN 144 Y PLOTNO I 145 END IF 146 IF Y PLOTNO I lt YMIN THEN 147 Y PLOTNO I 148 END IF 150 151 Xl FRAME BOTX WINDNO FRAME BOTY WINDNO 125 2 FRAME TOPX WINDNO Y2 FRAME WINDNO 154 The following line computes the factors to autoscale the data 122 in the axis 157 YSPAN YMAX YMIN FYFACT 2 1 YSPAN 158 FXINC X2 X1 POINTS 160 Plot the window label x and y axes 162 PlotWindow FRAME WINDNO PCI 20091W 4 17 Appendix 200925 Sample Programs 163 164 165 166 167 168 169 170 A 18 LOCATE INT Y2 INT X1 LOCATE INT Y1 8 1 8 1 INT X1 8 2 INT X2 8 2 INT X1 PRINT USING YMAX 3 PRINT USING YMIN 3 PRINT USING POINTS 3 PRINT 0 LOCATE INT Y1 LOCATE INT Y1 FOLDX X1 Scale and plot the data FOR J 1 TO POINTS First autoscale a new Y point to the plot window Y PLOTNO J YMIN FYFACT Y1 Then autoscale a new X point to the plot window FXNEW FOLD
145. o use switch V when loading 925 if you have another application that uses interrupt 60 Note If you use any vector other than the default of 60 Hex you must change the reference to this vector in the header to your program In the header file PCIHEADQ BAS which you copied to your work disk this vector is specified in the line defining INTVEC in the typical PCIHEADQ BAS figure 3 2 Note on Expanded Memory Expanded memory drivers use interrupt 67 Hex SWITCH G BYPASSING CONFIRMATION Normally 200925 1 stops after displaying the sign on message to request user confirmation The switch G causes the Software Drivers to Go bypassing user confirmation as it is loaded If you run PCI 92S EXE from a batch file you will probably use this switch SWITCH B ALLOCATE DMA BUFFER When the 200925 Software Drivers are loaded into memory a buffer may be allocated by specifying the Bb load option switch where b is an integer variable This switch allocates a buffer at the top of memory If the b parameter is not present a default buffer 64 Kbytes in length will be allocated If b is present b Kbytes will be allocated Any size buffer from 1 to 64 Kbytes may be allocated PCT 20091W 1 3 11 PCI 20091W 1 High Speed Analog Input Board SWITCH X EXECUTE COMMAND LINE The switch X text allows the user to specify a command line to be executed by 925 The command line text be
146. ode Description 0 No error condition since the last call to the system error code routine 1 Internal error 2 Bad function call A call has been made to offset 0 in the Software Drivers segment This usually occurs if a function name is incorrectly typed in a QuickBASIC program 3 Invalid VO type The I O type specified in a read channel or write channel call is not supported by this software The only types sup ported by this software are ALT and 4 Invalid input type Input from the specified type is not supported by this software 5 Invalid output type Output to the specified I O type is not supported by this software 6 Invalid channel number The specified channel number does not exist for the I O type specified PCI 20091W 1 6 25 20091 1 High Speed Analog Input Board 7 16 6 6 2 101 Duplicate 20091 1 initialization Two calls to initialize the same Board INIT have been made Call the system initialization function SYSINIT at the beginning of the program to clear the system memory Invalid PCI 20091W 1 ID An invalid PCI 20091W 1 ID has been found at the segment address specified by the INIT call Check your address swithc for proper settings Invalid minor PCI 20091W 1 ID The minor PCI 20091W 1 ID code is not supported by this software This error code may appear if a 20041 Carrier is used with an unsupported Module Internal error
147. onal Computer Instrumentation System The PCI 20000 System is a modular instrumentation system for use with IBM PC tm and compatible personal computers The System consists of Instrument Modules for data acquisition and control Carriers to provide an interface between the Modules and the PC bus Termination Panels and accessories to facilitate bringing real world signals to and from the Modules and Software Support packages to enable the user to operate his system easily and effectively The Instrument Modules are small 4 X 4 cards each one having a specific set of capabilities Modules may be chosen to provide such functions as digital inputs out puts analog inputs analog outputs triggering and frequency measurements Up to three Modules may be plugged into a Carrier which is a 13 X 4 card designed to interface with the IBM PC tm bus All Carriers provide inter Module com munications and power for the Instrument Modules and some Carriers also provide on board digital and rate generator functions Various rack mountable Analog and Digital Termination Panels provide con venient screw terminal connections for field wiring including thermocouples and RTDs Some Panels have board space for user installed signal conditioning com ponents other Panels provide signal conditioning or isolation features Software Support packages provide high level and assembly language support for the PCI 20000 System The most useful h
148. outines and are completely transparent to the user The computer jumps to the appropriate routines in PCI 92S EXE to execute the desired function These routines maintain local data area the System Configuration Data Area which is contained within the resident program area and which keeps track of the current state of the hardware The data area is initialized by the SYSINIT System Initialize function and local data structures are built by the INIT Initialize function These structures are modified by Configuration functions I O functions such as READ CH Read Channel and WRITE CH Write Channel make use of the stored data and access the Hardware Drivers to perform the desired function In the event that an error results from an instruction call the Software Drivers will return to the user s Microsoft QuickBASIC program with an error code set in the system error code register The contents of the system error code register can be read by executing the ERR SYS System Error instruction To interpret the mean ing of the error code returned refer to sections 6 7 through 6 13 When a PCI 200925 1 instruction is called the call is actually handled by the QuickBASIC ABSOLUTE utility which uses its final argument to locate the offset of the instruction s entry point in the PCI_92S EXE jump table These entry point offsets are defined in the header file PCIHEADQ BAS Figure 3 2 shows a typical header file PCIHEADQ BAS also de
149. procedure 2 1 Instruction offsets mnemonic definitions 3 5 Instructions iode tote 6 1 BUEDEC 5 7 6 6 6 8 buffer Utility 6 5 5 7 6 6 6 9 4 2 6 11 CNERG 4 2 5 7 6 13 configuration essen 6 5 configure 5 7 6 9 configure high speed 4 2 6 11 configure rate generator 4 2 5 7 6 13 decode 5 7 6 8 DMA SE 57 22 02 7 5 7 6 16 225646 5 7 6 15 DMA STAT 5 7 6 6 6 16 5 7 6 6 6 18 ERR 3 5 4 2 6 6 6 19 high speed 6 5 high speed 4 2 4 2 6 20 3 5 6 3 6 21 6 21 jc 6 4 Pea 6 5 6 22 READ ICs 3 5 6 6 6 22 return Value 0 5 6 6 run 5 7 6 15 run high 4 2 6 20 6 6 stop 5 7 6 18 6 4 3 5 6 23 SyStem 4 2 6 19 system 6 2
150. rds and initial counts to the hardware Two inter nally connected counters are set by the two count arguments LSW and MSW The rate generator waveform produced by these two counters operating in Intel mode 2 or 8 is shown in figure 8 Modes 3 and 9 produces a square wave output A rate generator channel must be configured using this instruction before it is enabled with the WRITE CH Write Channel instruction Tlow Thigh 5V OV _____ _ ate Generator Waveform modes 2 Intel Mode 2 Tlow LSW counts 1 8 10 Thigh LSW counts MSW counts 1 8 10 Intel Mode 3 Thigh LSW counts MSW counts 1 8 10 If a rate generator channel is used for high speed data acquisition or DMA data acquisition the data acquisition sampling rate in cycles per PCI 20091W 1 6 13 PCI 20091W 1 High Speed Analog Input Board second F is determined by the rate generator counts LSW arid MSW The sampling period in seconds T is given by T 1 F LSW MSW 8 106 The minimum values for LSW and MSW corresponding to the maxi mum sampling rate are determined by the hardware configuration and the data acquisition mode used 6 14 PCI 20091W 1 Chapter 6 Software Technical Reference DMA RUN Run DMA DMA Control Instruction PURPOSE SYNTAX ARGUMENTS REMARKS Execute a DMA process set up by the CNEDMA Configu
151. re DMA instruction CALLS ABSOLUTE CLUSTERS DELAY DMA RUN 1 CLUSTERS This argument is used in DMA Mode 2 to specify the number of clusters of data to acquire In DMA Modes 3 and 4 the number of clusters acquired is the maximum that will fit into the DMA buffer CLUSTERS must be set to 0 Note that in Modes 3 and 4 much more data may be read as new data overwrites old data 2 DELAY Specifies the number of clusters for the DMA process to transfer after the trigger event DMA mode 3 Since the delay counter counts frames pacer clock ticks the count with which the delay counter is programmed will be determined by multiplying DELAY by the number of samples per cluster DELAY should be set to 0in DMA Modes 2 and 4 None 20091 1 6 15 PCI 20091W 1 High Speed Analog Input Board honc o I EP A DMA STAT DMA Status DMA Control Instruction PURPOSE Return the status of a DMA run SYNTAX CALLS ABSOLUTE COUNT STATUS DMA STAT ARGUMENTS 1 COUNT Number of clusters available for reading Zero will be returned if the status return value below is non zero Be sure to predefine this argument by setting it equal to 0 prior to this call 2 STATUS A zero will be returned if there is no DMA process running 1 will be returned if there was an error other than overrun associated with a DMA process The system error register will indicate an overrun condition if one exists Other status code
152. re Start Convert command and Read MSB Data You can select the channel sampling sequence through hardware or software When you choose hardware controlled channel scanning the channel is automat ically advanced by the hardware following each conversion The PCI 20091W 1 provides a rate generator function The rate generator signal is buffered and brought out to a rate generator output in addition to being available on the Board as a data acquisition pacing signal The rate generator output provides a variable duty cycle with a minimum duty cycle of 50 The Board accepts external TTL control signals in addition to the External Start Convert signal mentioned above A Convert Inhibit input can be used to gate enable High Speed or DMA analog data acquisitions An External Interrupt input can provide interrupts to the PC from an external source or act as a DMA Trigger event signal A PC interrupt can be also generated to signal termination of a DMA data acquisition See figure 1 1 for a hardware block diagram of the PCI 20091W 1 1 2 2 DEFINITIONS AND CAPABILITIES Programming analog channels reading analog data programming the Rate Gener ator and setting up the DMA ciruitry can be accomplished through the use of the included PCI 20092S Software Drivers or the 200265 PCI 20027S Software Drivers or by the use of your own custom software Programming guidelines are provided later in this manual to assist users who wish to write
153. rify that correct data is being read O rOEHPeoBg e 4 4 High Speed Mode 4 Hardware Controlled High Speed Analog Acquisition 4 4 1 DESCRIPTION High Speed Mode4is a data acquisition mode with completely hardware controlled timing and channel selection This mode is fast and accurately timed timing signal is supplied to the start convert input of the A D converter and the same signal controls automatic channel selection A trigger event may be used to gate the timing signal input to the start convert input or a gate applied to the Convert Inhibit input Once the acquisition is under way the software will read data from the proper analog input channel s each time the end of conversion signal from the PCI 20091W 1 is detected PC1 20091W 1 4 3 PCI 20091W 1 High Speed Analog Input Board When data acquisition takes place with hardware controlled timing and channel selection the Software Drivers perform the following steps 1 When conversion is complete read and store the data 2 Check the number of samples taken and go to step 1 if sampling is not complete 4 4 2 PROGRAMMING See the discussion in section 4 3 for information on high speed data acquisition programming 4 4 PCI 20091W 1 Chapter 5 DMA 5 1 Introduction and Chapter Overview This chapter describes how the PCI 20092S 1 Software Drivers operate direct memory access DMA This section co
154. rocess with this instruction In Mode 3 specify the trigger delay in clusters that you want between the trigger event and the end of the DMA process WRITE CH Write Channel If you are using the onboard rate generator channel to start analog conversions call this instruction to enable the rate generator after the call to DMA RUN DMA STAT DMA Status Use this instruction to check whether or not the DMA process has completed DMA STOP Stop DMA This instruction may be used to stop the DMA process prior to its automatic termination 5 10 4 BUFFER CONTROL INSTRUCTIONS BUEDEC Decode Buffer Call this instruction one or more times to read input data from the buffer Specify the number of clusters to input in each call You can call this instruction during DMA operation to return the most recently read cluster This instruction returns data clusters from an input buffer The buffer must contain data acquired by a DMA mode process For example first acquire data with a DMA Mode 3 process When the process is complete read back the data using BUEDEC To monitor data as it is taken call BUEDEC to return the single most recent cluster in the buffer PC1 20091W 1 5 7 Chapter 6 Software Technical Reference 6 1 Chapter Overview This chapter covers in depth technical information for your software drivers Sec tion 6 2 gives a high level discussion of creating application programs in Microsoft QuickBASIC Section 6 3 cov
155. rom the register reading the least significant byte LSB first The programmed mode and status of the counter can be read from this register using the read back command described under Offset 43 WRITE Writing to this offset sets the initial value of the low order 16 bits of the Rate Generator counter The data must be written as two consecutive bytes to the register writing the least significant byte LSB first Offset 041 High Order Rate Generator Counter Before any reads or writes are performed from this Offset the Rate Generator control register must be configured see Offset 043 PCI 20091W 1 Chapter 7 Hardware Technical Reference READ Reading this offset returns the high order 16 bits of the Rate Generator counter The data must be read as two consecutive bytes to this offset reading the least significant byte LSB first The programmed mode and status of the counter can be read from this register using the read back command described under Offset 43 WRITE Writing to this offset sets the high order 16 bits of the Rate Generator counter The data must be written as two consecutive bytes to this offset writing the least significant byte LSB first Offset 042 Delay Counter Before any reads or writes are performed from this register the Delay counter control register must be configured see Offset 043 READ Reading this register returns the current value of the Delay counter The data must be re
156. rrun The DMA timing signal is too fast Slow down the acquisition Trigger active The DMA Trigger delay was still active when DMA acquisition was stopped In Mode 3 the trigger location in the buffer will not be correct DMA active DMA acquisition was active when DMA acquisition was stopped in modes other than stop on command In Mode 2 fewer data were transferred than requested Alternatively DMA acquisition was active when an attempt was made to start acquisition No DMA data The BUEDEC was called prior to calling the DMA run function Delay count too large The delay count converted from cluster count to frame count exceeded 65536 Internal error Internal error No DMA list function DMA acquisition is not supported for a specified channel list empty The first entry in the DMA channel array was 1 Illegal list configuration The I O type sequence in the DMA list is incorrect Cluster size error Two analog input channel sequences were specified Invalid trigger DMA acquisition trigger operation is not supported for the specified channel 6 28 PC1 20091W 1 Chapter 6 Software Technical Reference 16101 No trigger Mode 3 requires that a trigger be specified 16102 Invalid trigger code An invalid code was used to specify the DMA trigger The only I O codes supported for the PCI 20091W 1 is XSYNC 16200 Invalid time base DMA acquisition timing operation is not sup
157. s described below indicate that a DMA process is running Be sure to predefine this argument by setting it equal to 0 prior to this call Table 6 2 summarizes the status codes returned when this instruction is called during various phases of a DMA process TABLE 6 2 DMA Status Return Values DMA Run DMA Trigger Delay Terminal Stop DMA Mode Command Event Count Count Command 2 0 kk 2 kk D kk D kk 0 0 3 0 kk 3 kk 3 0 0 0 4 0 2 kk kk 2 kk kk kk kk 2 0 Notes The vertical bars indicate the time at which the indicated function or event occurred The asterisks indicate phases during which data is being trans ferred via DMA process REMARKS This instruction is useful for monitoring the status of a DMA opera tion It DMA Modes 2 and 2 it may be used to determine whether the DMA process has completed In all DMA modes it checks for DMA overruns and sets the error code if an overrun has occurred The COUNT value is set only after DMA process is complete While the DMA process is active COUNT is returned as 0 In DMA Modes 2 and 3 in which the DMA process is stopped auto matically you must call an instruction that will cause the Software 6 16 PCI 20091W 1 Chapter 6 Software Technical Reference Drivers to check the status of the DMA process after it halts Such instructions include DMA STAT DMA STOP and BUEDEC ra
158. s These ID codes are not supported by earlier versions of the software drivers PCI 20046S PCI 20047S and early versions of the PCI 20092S Software Drivers Terminal count interrupt modes are not supported by the in cluded PCI 200925 Software Drivers The DMA control and ID code jumper settings are shown in table 2 6 below TABLE 2 6 DMA Control Jumper Settings ID Code Jumper IN Jumpers OUT DMA without terminal count W16 W17 W18 Non DMA mode W16 W17 W18 DMA with terminal count W17 W16 W18 Extended without terminal count W16 W17 W18 Extended with terminal count W18 W16 W17 Factory configuration 2 7 2 DMA MODES er E E Direct memory access DMA is a method of loading output data from the PCI 20091W 1 to the host computer s memory under automatic hardware control The 200275 Software Drivers support nine different DMA modes The PCI 20092S Software Drivers as a subset of the PCI 20047S Software Drivers support three of those modes DMA Mode 2 DMA Mode 3 and DMA Mode 4 The different DMA modes are characterized by different start and stop conditions for data acquisition shown in table 2 7 There is a detailed discussion of DMA and of these DMA modes in chapter 5 PCT 20091W 1 2 9 PCI 20091W 1 High Speed Analog Input Board TABLE 2 7 DMA Mode Description DMA Mode Start Condition Stop Condition 2 Command Terminal Count 3 Command Trigger with Delay 4 Command Command 2 7 3 PACING SOU
159. s PC interrupt level 3 Enables PC interrupt level 4 Disables PC interrupt level 4 Enables PC interrupt level 5 Disables PC interrupt level 5 Enables PC interrupt level 6 Disables PC interrupt level 6 Enables PC interrupt level 7 Disables PC interrupt level 7 Enables DMA channel 1 Disables DMA channel 1 Enables DMA channel 1 Disables DMA channel 1 Enables DMA channel 3 Disables DMA channel 3 Enables DMA channel 3 Disables DMA channel 3 Enables DMA channel 2 Disables DMA channel 2 Enables PC interrupt level 2 Disables PC interrupt level 2 7 20 PCI 20091W 1 Chapter 7 Hardware Technical Reference 7 7 Hardware Specifications ANALOG INPUTS Offset Voltage Offset Drift Unipolar Bipolar Impedance Voltage Range Linear Without Damage Bias Current Noise EXTERNAL CONTROL SIGNALS External Start Convert Active Edge Conversion Inhibit Active Level External Interrupt Active Level DYNAMIC RESPONSE Mux Settling Time to 0 01 A D Conversion Time Acquisition Time to 0 01 Aperture Jitter Total Conversion Time Crosstalk Trimmable to 0 1 2 LSB 3 ppm C 15 1 Mohm single ended 10V 20 V above supplies 100 nA 1 LSB on the 2 5 volt range shorted inputs TTL compatible High to Low to start conversion TTL compatible Low to inhibit TTL compatible Low to interrupt 3 5 Max 10 sec max 1 5 usec max 0 3 nsec max 11 25 usec typ 1 2 LSB PCT 20091W 1 7 21
160. scussion under each of these offsets for more information fh si 7 4 Register Offsets The computer controls the functions of the PCI 20091W 1 by accessing registers at memory mapped offsets within the Board s 1 Kbyte block of memory The program ming language you use must have the capability of absolute memory reference 7 4 1 1 0 REGISTERS registers may be read only write only or read and write registers In addition the same register may be used for two different functions depending on whether it is read or written If the register is read only you will not be able to change its contents directly If the register is write only or if its read function is unrelated to its write function you will not be able to read back data that was previously written to the register you must save the data in program memory in order to reference it later In some cases just reading or writing a register may trigger an event such as an analog conversion regardless of the data involved Be careful not to inadvertently read or write such registers particularly if you use a debugger during program development 7 4 2 MEMORY ADDRESSES The 8086 microprocessor family addresses memory using a 16 bit SEGMENT register in conjunction with a 16 bit OFFSET to specify a 20 bit ADDRESS as follows 7 4 PCI 20091W 1 Chapter 7 Hardware Technical Reference ADDRESS SEGMENT 16 OFFSET Most programming languages reflect this
161. se for your application The Sample Programs are extensively commented and contain many PRINT statements You may find it instructive to study the Sample Programs before you begin to write your own application programs As you run the Sample Programs you should supply signals to hardware inputs and monitor the outputs as required by the programs A 3 Sample Programs Instructions The Sample Programs are intended to help you understand how to use the software in combination with your hardware Each sample program illustrates the use of certain hardware features in combination with certain Software Drivers instruc tions This section contains a list of the sample programs by number with the software calls used by each program All sample programs use the following instructions ERR SYS System Error INIT Initialize SYSINIT System Initialize A 3 1 SAMPLE PROGRAM 1 DESCRIPTION ANALOG INPUT This program reads all eight analog input channels on the Board The Board should be configured for 10 volts You should provide known voltages on at least some of the channels which you can verify against the values reported by the program PCI 20091W Appendix 200925 Sample Programs Instructions used READ CH Read Channel A 3 2 SAMPLE PROGRAM 2 DESCRIPTION PULSE TRAIN This program outputs a pulse train from the rate generator You should monitor the rate generator output with a scope or frequency counter
162. status of a run SYNTAX CALLS ABSOLUTE COUNT STATUS DMA STAT DMA STOP Stop DMA Stops the DMA operation SYNTAX CALLS ABSOLUTE COUNT DMA STOP v em TER GNE A 6 5 Instruction Specifications This section contains a detailed listing of the instructions available in the PCI 200925 1 Software Driver system The listing is presented in alphabetical order by actual call for ease of reference The specific syntax of each instruction is given The semantic description of the arguments is included The arguments are numbered in the order in which they appear in the given format Some instructions notably the READ CH ERR SYS BUEDEC CNEDMA DMA STAT and DMA STOP instructions pass a return value to the calling program This value appears as the final argument in the argument list Table 6 1 lists the I O types and what their names are 6 6 PCI 20091W 1 Chapter 6 Software Technical Reference TABLE 6 1 1 0 Types Definition Name Analog Input ALT Analog input auto sequencing AIX T Rate Generator Pacer Channel RG T The call to each instruction appears as it would be used in your program Constants and variables used 200925 1 CALLS statements must be integers That means they either must be of the form variable or a DEFINT command must exist in the program or they must be declared as integers in a DIM statement PCI 20091W 1 6 7 PCI 20
163. ta and returns circular buffer data in chronological order 5 8 1 AUTO SEQUENCED CHANNELS A cluster consists of one to eight data frames each successive data frame in a cluster will contain data from the next analog channel in the frame map One complete pass through the list of analog channels constitutes a cluster For example if you have configured the PCI 20091W 1 for auto sequencing and you wish to sample channels 5 6 and 7 each cluster will contain three data frames In this case the first data frame would contain the first analog channel channel 5 the second would contain the second analog channel 6 and the third would contain the third analog channel 7 5 8 2 FRAMES AND DMA MODES 3 and 4 When a buffer is used for DMA Mode 3 or 4 the PCI 20092S 1 Software Drivers adjust the length of the circular buffer so that it contains an exact integral number of clusters This ensures that when the buffer is overwritten or wraps the first data frame in the buffer always contains the first analog channel the second data frame contains the second analog channel and so forth This ensures that the data can be unambiguously associated with the correct channel sequence In DMA Mode 3 stop on trigger with delay the delay is specified in clusters This ensures that an integral number of clusters is always transferred ee 5 9 1 0 Types Two types are used to specify the DMA channel list The first channel in the
164. ter 6 is an in depth technical discussion of the software that came with your system along with some programming guidelines for writing your own software for this system Chapter 7 is an in depth technical discussion of your hardware including a specifications list Appendix A contains the sample program listings The last part of this manual is that indispensable tool the index 1 2 PCI 20091W 1 High Speed Analog Input Board Description 1 2 4 Summary The PCI 20091W 1 High Speed Analog Input Board is a single Board system that provides high speed and DMA analog acquisition functions with up to 8 eight single ended analog input channels a 12 bit resolution analog to digital A D converter a general purpose rate generator that can be used as a data acquisition pacer and PC interrupt capability Analog acquisition speeds of up to 89 000 samples per second can be obtained with this Board The Board s analog input section provides eight single ended input channels By proper placement of jumpers see chapter 2 channel ranges may be selected for 2 5 volts 5 volts 10 volts 0 to 5 volts and 0 to 10 volts 20091 1 1 1 PCI 20091W 1 High Speed Analog Input Board The analog input system can provide high speed data acquisition using a variety of conversion pacing sources These sources include two hardware sources an Exter nal Start Convert and the onboard Rate Generator and two software sources a Softwa
165. that COMP is a DOS external commands mean ing it is a file on the PC DOS or MS DOS system diskettes your working diskette or you copy those files onto second floppy diskette and use that second floppy as your working backup If you wish to use the subdirectory stop here and skip to section 3 6 If you wish to make a separate floppy 7 gt ct S lt to 45 w m h fo rt A ct et 2 4 e lt D fb COPY C subdirectory A V To verify the integrity of your files type COMP C subdirectory 3 4 PC1 20091W 1 Chapter 3 Software Installation Once you are sure you have a complete copy of your master diskette put your master diskette away and use the diskette you have just created as your working copy 3 6 Software Drivers Description The structure of the 200925 1 Software Drivers system is shown schematically in figure 3 1 The PCI 92S EXE program is the controlling center of the system The user loads it into memory where it remains resident for use by QuickBASIC programs When 200925 1 Software Drivers instruction is called program control is passed from QuickBASIC to the PCI 925 routines as shown in figure 3 1 of the following steps are then taken care of by the Software Drivers r
166. the multiplexers by writing the appropriate byte to BYTE BA 104H Step 3 Wait for the input amplifier and multiplexer to settle You will probab ly not need to do this unless you are programming in assembly language on a high performance computer You can ensure an ade quate settling delay by entering a count down loop with the number of loop cycles adjusted suitably Step 4 Initiate a conversion by writing any data to BYTE BA 103H Step 5 Wait for the conversion to complete To test whether the conversion is complete read the conversion status in the appropriate bit of BYTE BA 001H Depending on the speed of your CPU this step may not be necessary Step 6 Read the converted data from WORD 101 Repeated measurements of the same channel can be performed by repeating Steps 4 through 6 7 5 3 DATA ACQUISITION WITH HARDWARE TIMING This procedure uses a hardware pacing source rate generator or external start convert for pacing the acquisition It is assumed that the board is jumpered for automatic channel scanning The Conversion Inhibit input may be used to gate the acquisitions This procedure may be used to sample a single channel 7 from one to eight channels N 7 or all eight channels 0 7 Step 1 Make sure the Interrupt Status register is reset by reading BYTE 102 Ignore the data read Step 2 Set the initial channel by writing the appropriate byte to BYTE BA 104H Step 3 Progr
167. their own software The PCI 20092S Software Drivers described in detail in chapters 3 through 6 are a subset of the 200265 and PCI 20027S Software Drivers This subset supports the specific functions of the PCI 20091W 1 Board The PCI 20026S Software Drivers support the functions of other PCI products They also support the programming languages IBM Interpreted BASIC C and Turbo Pascal 1 2 3 MINIMUM REQUIREMENTS FOR USING THIS PRODUCT In order to use this product successfully you need to have at a minimum the following available 1 The PCI 20091W 1 High Speed Analog Input Board and accessories We recom mend the 20012 1 or the PCI 20012A 2 Analog Signal Cables and the PCI 20010 1 Analog Termination Panel 2 The accompanying 200925 Software Drivers packaged with this product 3 Microsoft QuickBASIC programming language 12 PCI 20091W 1 Chapter 1 Introduction 4 An IBM PC XT AT or compatible This list gives a minimum configuration This product is flexible and expandable other products you can use with this system are described in the next section i n 1 3 PCI System Compatibility and Emulation This section describes the PCI 20091W 1 s compatibility with the PCI system The PCI 20091W 1 Board emulates most functions of a PCI 20041C 3A Carrier without digital with a PCI 20019M 1A High Speed An
168. trary for the purpose of clarity You may use any variable names which do not conflict with names defined by the PCI 20092S 1 software or with the requirements of your programming language See figure 3 2 PCIHEADQ BAS 3 3 System Configuration Requirements Your personal computer system must use PC DOS or MS DOS version 2 0 or higher and have approximately 33 Kbytes of memory for the PCI 20092S 1 Software Drivers in addition to the memory required for the computer s operating system and QuickBASIC One user defined interrupt in the range 60 Hex through 67 Hex must be available default value is 60 Hex You can find more information on interrupt vectors and how to change them elsewhere in this manual In order to use the PCI 20092S 1 Software Drivers Microsoft QuickBASIC must be available on the computer 3 4 The PCI 20092S Software Drivers License Agreement Read the PROGRAM LICENSE AGREEMENT printed on the envelope containing the PCI 20092S 1 Software Drivers diskette and make sure you fully understand it If you have any questions contact your sales representative before continuing 3 5 Creating a Working Copy of Your Software The 200925 1 Software Drivers system diskette which is for Microsoft QuickBASIC language programmers contains the following files 3 2 PC1 20091W 1 Chapter 3 Software Installation SOFTWARE DRIVERS GROUP 925 Software Drivers program PCIHEADO BAS Header
169. uld save your program after every change involv ing calls 6 3 Hardware Initialization This section describes the system s hardware initialization sequence This is impor tant because the initialization sequence determines which channel number is used to reference each of the hardware channels 6 3 1 INITIALIZATION SEQUENCE The initialization is simple and straightforward Each time your program executes the INIT Initialize instruction the system first checks that a PCI 20091W 1 exists at the segment address given and that an PCI 20091W 1 at that address has not previously been initialized Then the system initializes the following channels 8 Analog Channels 1 Rate Generator Channel All channel number sequences begin with 0 as the first channel 1 as the second channel and so forth 6 3 2 EXAMPLES OF HARDWARE INITIALIZATION Example 1 One PCI 20091W 1 Consider a system with one PCI 20091W 1 installed The following channels will be configured Example 1 Channel Configuration Channel Numbers Channel Types 0 7 Analog Inputs Rate Generator e Ww PCI 20091W 1 6 PCI 20091W 1 High Speed Analog Input Board E Example 2 Two PCI 20091W 1 Boards Consider a system with two PCI 20091W 1 Boards installed The following channels will be configured Example 2 Channel Configuration Channel Numbers Channel Types Description 0 7 Analog Inputs PCI 20091W 1 1 8 15 Analog Inputs PCI 20091W 1
170. vector other than the default 60 Hex when you loaded PCI 92S EXE you must edit PCIHEADQ BAS to specify that same vector Your program will control the PCI 20091W 1 hardware and read input data through QuickBASIC CALLS statement You must be sure that all variables used in CALLS PCI 20091W 1 6 PCI 20091W 1 High Speed Analog Input Board statements are integers The file PCIHEADQ BAS declares all variables starting with letters other than F to be integers F is reserved for floating point variables Note that the header statement DEF SEG SEGMT defines the segment used by the CALLS statements DEF SEG is also used conjunction with PEEK and POKE statements If your application program uses PEEKs and POKEs to access QuickBASIC s data space or if you have CALLS or CALL statements to subroutines from some other software package you must use the appropriate DEF SEG statements throughout your program to ensure that the correct segment is set for each CALLS CALL PEEK and POKE statement The first calls you make in your program should ordinarily be CALLS ABSOLUTE SYSINIT CALLS ABSOLUTE SEGMT INIT You should call INIT for every PCI 20091W 1 you have installed in your system setting the variable SEGMT to each segment address in turn that you have estab lished with the address switches on each PCI 20091W 1 You can check for hardware configuration errors and other problems with the following ERROR CODE 0
171. which will determine when the acquisition will begin I _______ SUS SEO A a aE 4 2 Hardware Configuration This section describes the hardware configuration for a high speed data acquisition You will need to select a time base and you may optionally use a trigger source and automatic channel selection The time base for the high speed acquisition may be provided by the PCI 20091W 1 s onboard rate generator or by an external start convert signal In either case you must configure the Board with appropriate jumpers To use the external Hardware Start Convert you must provide an external signal TTL compatible at the ap propriate pin of the PCI 20091W 1 digital connector Refer to section 2 4 for the appropriate jumper configuration in either case PC1 20091W 1 41 PCI 20091W 1 High Speed Analog Input Board You may provide a signal to the Conversion Inhibit input in order to trigger data acquisition to begin following a desired event When the the Conversion Inhibit input goes high data acquisition will commence If analog conversions fail to take place either because Conversion Inhibit remains low because pacing signals are absent or because the pacing signals are not reaching the A D converter the computer will effectively be locked up necessitating a system reset If your application involves sampling a single channel you can either use channel 7 for your input signal or disable the automatic channel
172. wide range of output frequencies In the variable duty cycle mode mode 2 thelow time of theoutput T1 and the high time of the output T2 are determined by T1 N1 8 10 T2 N1 N2 1 8 109 N1 is set by writing to Offset 40 Hex and N2 is set by writing to Offset 41 Hex The operating modes and functions of the rate generator are set by writing the PCI 20091W 1 7 3 PCI 20091W 1 High Speed Analog Input Board proper control word to Offset 43 Hex The status of the Rate Generator output signal can be monitored by reading Offset 01 7 3 3 OPERATION The Board contains DMA control circuitry allowing it to communicate with the PC s DMA controller to sample analog input data under complete hardware control The Board s DMA mode is programmed to one of three modes by writing to Offset 02 DMA data transfers are started and stopped by reads to Offset 02 and Offset 03 respectively Status of a DMA operation including the occurance of DMA overruns can be monitored by reading Offset 01 7 3 4 BOARD IDENTIFICATION Several offsets and jumpers are concerned with different identification codes Of fset 000 holds a value for an ID code which identifies the Board as either a PCI 20041C Carrier with one Module installed or as a PCI 20091W 1 Offset 004 Hex uniquely identifies the Board as a PCI 20091W 1 Offset 100 Hex provides an ID code that identifies a PCI 20019M Module as being present See the di
173. y push the Board down toward the connector keeping the front left edge of the Board seated in the card guide Press on the top of the Board at each end and with a gentle rocking motion insert the Board into the connector Do not force the Board as this could break the connector 8 Attach the Board firmly to the computer using the mounting screw on the bracket 9 Connect the input output cables to the Board 10 Replace the computer s cover using the five screws previously removed PCI 20091W 1 2 11 PCI 20091W 1 High Speed Analog Input Board 2 10 Pins and Ports Connecting to the Outside World 2 10 1 ANALOG CONNECTOR P2 All analog signal connections are made through a 26 pin right angle shrouded header protruding through the bracket This connector figure 5a is compatible with our cables and Termination Panels The connector is keyed to prevent reverse orientation 2 10 2 DIGITAL CONNECTOR P3 A seven pin digital I O connector figure 5b transfers control signals between the PCI 20091W 1 and the outside world This connector is accessible through the bracketslot The connector is keyed to prevent reverse orientation The pin out and signal description are given in table 2 9 TABLE 2 9 Digital Connector P3 Pinouts and Signal Description Pin Number Signal Description 1 Rate Generator Output This signal is the TTL buffered onboard pacer clock For a timing description see section 6 6 CNF RG

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