STD 7000 7605 Programmable TTL 1/0 Card USER'S MANUAL
Contents
1. SSSEE ASSEMBLY 1605 gt GENERAL PURPOSE 2uwTATTL I O CARD 105779 eorom NA C PI PRO LOG 2411 Garden Road Monterey California 93940 Telephone 408 372 4593 TWX 910 360 7082 106666A 200 9 812. Care must be taken to avoid ground loops lo al TONS dd a 8 7605 OPERATING SUBROUTINE MODULES This section provides flow diagrams and subroutines to operate your 7605 card These may be used intact or used as models to construct subroutines for a specific application The subroutines are written in 8080 family assembly code and will execute on 8080 8085 and Z80 processors The memory addresses selected are compatible with Pro Log s 7801 8085A and 7803 Z80 processor cards The 7605 port addresses used are the address jumper selections made when the 7605 is shipped To use these subroutines in systems other than those described above the memory and or 1 0 port addresses may require change for compatibility The flow diagrams presented can be easily translated into the assembly code used by any microprocessor since they show the steps required to achieve 7605 operation without reference to a particular microprocessor The following subroutines are written to act only on a single bit on the output or input ports For routines which act on all 8 bits of a port at the same time see the 7604 User s Manual Initialize 7605 This subroutine sets all outputs to a predefined state It also initializes all viariables used by the other subroutines PAGE Set bit This routine accepts a hex value in the accumulator which corre sponds to the 1 0 module to be turned on If the 1 0 module number
3. INTERFACE CONNECTOR PIN LIST CONNECTOR J1 CONNECTOR J2 PIN NUMBER PIN NUMBER SIGNAL SIGNAL uuo fos I pre 8 uou EEC 6 602 2220 Por Pie TEGE 1 P3 0 1 0 Low Level Active All odd numbered pins go to ground Interface Connector Pin List STD 7605 EDGE CONNECTOR PIN LIST PIN NUMBER PIN NUMBER OUTPUT LSTTL DRIVE OUTPUT LSTTL DRIVE INPUT LSTTL LOADS XX MNEMONIC MNEMONIC ysvoiTs jucc 21 5 ROUND 3 enol GROUND narco 5 D 155 1 EN 1 ACI C Erle OC 155 elles A 1 0 1 EEN ge 1 A As do far TTET 28 feof fa ZZZ E E EAA Ai TELE asp AAA 1 j 2 AAA ro TRR memo Jaja 1 IC E oer KAA KANA pas RRS saroso Teo ke T _ 52051 russa TRG T 1 Ra L warmer Paassen je IL sv9REsET CT E LC E ee Feci A 5 iere moxa IIS EC Low Level Active Designates LSTTL Loads Edge Connector Pin List FIGURE 6 NOTE Vee is provided on the user interface pins JI and J2 These should be used only after the system designer has thoroughly studied the system implication
4. Readback User selectable Port Address 256 Port Field Socketed ICs Single 5V Operation Uses Two Latching 40 pin Headers Input Port Loading 14 LSTTL Loads Output can Drive 50 LSTTL Loads C BLOCK DIAGRAM SYSAESET Q INOICATES ACTIVE LOW LOGIC FIGURE 1 FUNCTIONAL DESCRIPTION The 7605 provides 32 alternating bidirectional data and ground lines These signal lines can be up to 10 feet 3 05M long with proper electrical con siderations Each bidirectional line characteristic whether input or output is determined by the circuit shown in the Bidirectional 1 0 Circuit diagram The output circuit capability is supplied through an open collector inverting driver and a pullup resistor There are no programming constraints in the output mode active high data is written to the output port causing the user interface pin to operate fn the active low state Input circuit capability is provided through an inverting input port buffer The Schmitt trigger characteristic of the input port buffer remoyes noise induced voltage spikes from the input signal There is one programming con straint in the input mode active high data cannot be written to the output port bit that is to be used on an input port bit This constraint is required to disable the open collector output drive for that bit NOTE On system power up the SYSRESET signal clears the output port and places the output drivers in the disabled state
5. Thus programming overhead is not required to select the input mode of operation GENERAL PURPOSE INTERFACE The 7605 is useful as a general purpose TTL interface card Tf ftat cable or twisted pair discrete wire cable assemblies are used the ground signal ground of the 1 0 connectors minimizes crosstalk between inter system signal lines in electrically noisy environments The bidirectional signal lines at the card edge connector are active low on both input and output The signals are terminated with a IK pullup resistor TO STD DATA BUS BUFFER OUTPUT STROBE FROM PORT SELECT DECODERS FROM OTHER CIRCUTS Typical Bidirectional 1 O Circuit FIGURE 2 O 3 CARD ADDRESS MAPPING The 7605 is selected by a decoded combination of address lines A2 A7 The user chooses the card address combination by connecting one jumper wire from SX and SY to pad matrices adjacent to U2 and U3 see the 7605 Assembly diagram The 7605 is shipped mapped at hex port address 00 To map the 7605 anywhere in the hexadecimal address range of 00 to FF change the decoder outputs connected to SX and SY 4 ADDRESS DECODER OPERATION Refer to the schematic Document 105778 The 7605 uses four cascaded 74LS42 decoders U2 U3 U5 and U6 to decode address lines 0 7 These decoders are enabled only when and are active The WR signal is used to gate the select strobes from U6 that control the output ports The R
6. is out of range the carry flag will be set PAGE Clear bit This routine accepts a hex value in the accumulator which corre sponds to the 1 0 module to be turned off If the 1 0 module number is out of range the carry flag will be set PAGE PAGE PAGE PAGE REGISTERS FLOW START NAME AND DESCRIPTION CHANGED DIAGRAM PROGRAM ADDRESS 1300 1395 13A0 continued NAME AND DESCRIPTION Test hit This routine accepts a hex value in the accumulator which corre sponds to the 1 0 module to be tested If the 1 0 module num ber is out of range the carry flag will be set The subroutine returns with P 0 if there was no change and P if the addressed module did change since the last test The Z flag 0 if the bit is set and Z l if the input port is clear Complement a bit This routine accepts a hex value in the accumulator which corre sponds to the 1 0 module to be complemented If the 1 0 module is out of range the carry flag will be set START ADDRESS INITIALIZE 7605 gt INITIALIZE OUTPUT PORTS INITIALIZE VARIABLES SET A BIT TEST INPUT BIT nee HAT CLEAR A BIT TEST INPUT BIT COMPLEMENT BIT TEST INPUT BIT WHICH PORT AND BIT CHECK y PORT 00 CHECK PORT 02 CHECK PORT 03 N SET ERROR EXIT MASK OFF BIT ON PORT 00 MASK OFF BIT ON PORT Ol MASK OFF BIT O
7. CORPORATION 7605 Programmable TTL I O Car DI PRO LOG STD 7000 USER S MANUAL 7605 Programmable TTL I O Card USER S MANUAL CORPORATION 9 81 7605 TTL PROGRAMMABLE TTL 1 0 CARD TABLE OF CONTENTS SECTION 1 SECTION 2 SECTION 3 SECTION 4 SECTION 5 SECTION 6 SECTION 7 SECTION 8 SECTION 9 Product Overview Block Diagram Pune oni Description General Purpose Interface Mapping Address Decoder Operation Changing the 7605 s Port Address 7605 Card Environmental Specifications Electrical Specifications Mechanical 7605 Operating S broutins Modules Maintenance C PRODUCT DATA SHEET 7605 PROGRAMMABLE TTL 1 0 CARD A PRODUCT OVERVIEW The 7605 supplies four 8 bit 1 0 ports that can be programmed as input output or output with readback total of 32 programmable 1 0 lines Port access is via two 40 pin latched connectors with 025 inch square post headers The output lines are TTL compatible open collector drivers with IK pullups These lines are tied to input ports After power on reset all ports are in input mode To use an output port the user simply writes to the port lines desired The 7605 decodes 8 address lines with provision for expansion An on card jumper system allows the user to map the four consecutive port addresses occupied by the 7605 anywhere in the 256 port address field B PRODUCT FEATURES 32 1 0 Lines Each Programmable as Input Output or Output with
8. D signal is used to gate the select strobes from U5 that control the input ports CHANGING THE 7605 s PORT ADDRESS Refer to the Assembly diagram Document 105779 Locate decoders U2 and U3 74LS42 adjacent to the STD BUS edge connector Each decoder device has a dual row of pads which form decoder output select matrices Make one and only one connection to each of the matrices adjacent to U2 and U3 The decoder jumper pads numbered as shown in Figure 3 are adjacent to the decoder chips on the 7605 Also shown are the jumpers at XO and YO which produce hexadecimal port addresses 00 01 02 and 03 the selections made when the card is shipped 00 00 oo woo 00 00 x amp i FIGURE 3 DECODER JUMPER PAD NUMBERING poo w oo 00 00 400 The 1 0 address mapping and jumper selection table for four addresses per card shows where to place jumper straps to obtain any four sequential port addresses in the hexadecimal range 00 FF Using the lower of the 2 digit hexadecimal addresses desired find the most significant hexadecimal address digit along the vertical axis and the least significant hex digit on the horizontal axis For example port addresses 50 51 52 and 53 are obtained by connecting jumpers at X2 and Yb The only restriction that applies in address selection for the 7605 is that the lower of the four port addresses 00 as shipped must oc
9. HARACTERISTICS Must meet all requirements for TTL 1 0 cards timing as specified in the Series 7000 General Test Specification C 7 MECHANICAL The 7605 is shipped fully populated Power dissipation can be reduced by removing unused input or output ports by removing the ICs INPUT OUTPUT PORT SELECTION PORT NO FOR ONLY AN INPUT FOR ONLY AN OUTPUT PORT REMOVE ICs PORT REMOVE IC U7 015 019 09 016 U20 911 017 021 013 018 U22 Leaving the input buffers place allows the processor to read back the output port data to check for noise alteration or to use the output port as a data register tos ASSY 105779 q YA d _ RP s R7 o 0 o 0 0 oo o o m O O OO 2 2 2 00000000 ME p PORT gt PORTS 2 3 Q R4 R 9 0 o o o ef oo o o e BER f PI J2 PORTS 0 1 JI 500000000000000000000 7605 Assembly FIGURE 5 Refer to the Component Placement diagram for component placement information The 7505 meets all STD BUS general mechanical specifications The 7605 requires one card slot in a standard STD BUS card rack The 1 0 connectors use low profile mass termination 0 25 inch square post latching connectors Recommended flat cable card edge connectors include 3 M part number 3417 6040 1 or equivalent 7605 USER
10. N PORT 02 MASK OFF BIT ON PORT 03 COMPARE MEMORY AND INPUT PORT UPDATE MEMORY SET FLAG O e G COMPLEMENT A BIT WHICH PORT AND BIT PORT 00D COMPLEMENT OUTPUT 00 COMPLEMENT OUTPUT 01 COMPLEMENT OUTPUT 02 COMPLEMENT OUTPUT 03 PORT 03 N SET ERROR UPDATE MEMORY PRO LOG CORPORATION PROGRAM ASSEMBLY FORM A AE Au 001 zi 1608 Lbei NL CIN ITIALIZE PROGRAM o o O AA CDA ERA ANAIS 31235 L _ DR ESE ell RE E REG nl an TW EYE Gu ELT IIA ET EENES ESTA w ES A s O PRO LOG CORPORATION PROGRAM ASSEMBLY FORM PRO LOG CORPORATION PROGRAM ASSEMBLY FORM MNEMONIG TITLE DATE ANA MASK ANG IX lENE OERS ALONE PRO LOG CORPORATION PROGRAM ASSEMBLY FORM Eramiha 1 6 4 3 2 1 o Tore M e USER A RELEASE rex Pen Loy USER INTERFACE 1 PORTS INTERFACE J Y 17622 33 2 s v IL GD raD CD Fey 5 TD r 12 5 J1 5 8 1 32 5 no 34 D pera ren EN ihr EDA GD rose P2 5 c omm A nr Dtm CARD SELECT DECODER
11. S R S 2 b Ge who Op XP 35 rot lot a A NOTES UNLESS OTHERWISE SPECIFIED I ALL RESISTORS IK a ED L TUMPER MOVES 1 0 PORTS IN 8 CONSECUTIVE BLOCKS pe OF 32 PORTS PER BLOCK LM er TUMPER MOVES 1 0 POPTS mE IN B CONSECUTIVE BLOCKS AALE SPARE CIRCUT INPUTS gcc cet LL SPARE Ci as ARE TIED TO A RESISTOR MER See Aloe SEE TABLE FOR SPECIFIC GON UPS ALL OUT 33 HAVE 110 CONNECTION 14 ea E 74 244 or Bd p Gre DERN 8 P3 2n UZDABTORTE I 9 TO K8 en 112141 10682 SYSKESE N ME RST E a REFERENCE ONLY 15V 2 2 ne M 2 HOME Fy FT gt 2sv I Sov _PRO LOG CORPORATION 2c Ol 550155 SE SCHEMATIC 7605 20 1 EEE GENERAL PUPDSE C A CLARK 10 074 TTL 1 0 CARO o 0 05778 ques 4 1 5 4 3 2 1 en Y INITIAL RELEASE PER PEN 0713 Ot Tai 2 BALS Aes 9 SEE DETAIL A ASSY 105770 NOTES UNLESS OTHERWISE SPECIFIED DENOTES PIN I END OF SOCKETS BOARD TO CONFORM WITH ASSEMBLY PROCEDURES AS1004 Qs IDENTIFY WIN ASSEMBLY KEY LETTER USING RUBBER STAMP FOKT 00 REFERENCE ONLY a jaa SCHEMATIC NO 404718 FARIS LIST NO 105780
12. cur only at every fourth possible address for example the sequence Ol 02 03 and 04 is not allowed by the decoder The pad matrices adjacent to U2 and U3 are on 0 10 inch 0 25cm centers The jumper wires may be conveniently replaced by wirewrap post if frequent address selection changes are anticipated LEAST SIGNIFICANT HEX ADDRESS JUMPER SELECTION ST SIGNIFICANT 212 4151 YO Y ESKE Address Mapping And Jumper Selection Table For 4 Addresses Per Card FIGURE 4 5 7605 CARD ENVIRONMENTAL SPECIFICATIONS A SEBA 1 FUN LIMITS ABSOLUTE NON OPERATING RECOMMENDED OPERATING LIMITS PARAMETER Free Air Temperature Humidity O Non condensing 6 ELECTRICAL SPECIFICATIONS 7605 GENERAL PURPOSE TTL 1 0 CARD ELECTRICAL TEST SPECIFICATION RECOMMENDED OPERATING LIMITS ABSOLUTE NON OPERATING LIMITS PARAMETER ww me MIX w ow _ mem o fa lt MNEM USER WORST CASE ELECTRICAL CHARACTERISTICS OVER RECOMMENDED TEST LIMITS PARAMETER TYP MAX UNIT LOW LEVEL INTERFACE VOLTAGE LoL LOW LEVEL INTERFACE CURRENT STD BUS ELECTRICAL CHARACTERISTICS OVER RECOMMENDED TEST LIMITS PARAMETER i MIN sto BUS INPUT LOAD See Figure STD BUS OUTPUT DRIVE See Figure amp ME IN At 2 volt A At 30mA current level A At 0 70 Volt level AC ELECTRICAL C
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