User Manual TPMC600
Contents
1. Expansion ROM used e Or PCI I O Space mapping starting at bit location 2 the first bit set determines the size of the required PCI I O Space size For PCI Memory Space mapping starting at bit location 4 the first bit set to 1 determines the size of the required PCI Memory Space size For PCI Expansion ROM mapping starting at bit location 11 the first bit set to 1 determines the required PCI Expansion ROM size For example if bit 5 of a PCI Base Address Register is detected as the first bit set to 1 the PCI 9050 is requesting a 32 byte space address bits 4 0 are not part of base address decoding e Determine the base address and write the base address to the PCI9050 PCI Base Address Register For PCI Memory Space mapping the mapped address region must comply with the definition of bits 3 1 of the PCI9050 PCI Base Address Register After programming the PCI9050 PCI Base Address Registers the software must enable the PCI9050 for PCI I O and or PCI Memory Space access in the PCI9050 PCI Command Register Offset 0x04 To enable PCI I O Space access to the PCI9050 set bit 0 to 1 To enable PCI Memory Space access to the PCI9050 set bit 1 to 1 For further information please refer to the PCI9050 manual which is part of the TPMC600 ED Engineering Documentation TPMC600 User Manual Issue 1 3 Page 14 of 25 TEWS lt TECHNOLOGIES 4 2 Local Configuration Register LCR After reset the PCI9050 Local Configurati2. FIGURE 3 5 RISING EDGE INTERRUPT ENABLE REGISTER a 8 FIGURE 3 6 FALLING EDGE INTERRUPT ENABLE REGISTER a 9 FIGURE 3 7 RISING EDGE INTERRUPT STATUS REOGIGTER 9 FIGURE 3 8 FALLING EDGE INTERRUPT STATUS REGISTER a 9 FIGURE 3 9 DEBOUNCE TIME REGISTER AAA 10 FIGURE 3 10 FORMULA TO DETERMINE DREI OADVALUE rna n ran nn ran 10 FIGURE 3 11 DEBOUNCE TIME EXAMPLES L L KEEA n n u 12 FIGURE 4 1 PCI9050 HEADER TPMC600 10 eee L ran EEA S S ua 13 FIGURE 4 2 LOCAL CONFIGURATION REGISTER L n S 15 FIGURE 4 3 CONFIGURATION EEPROM TPMC600 XX nanna nnn nn tran rna 16 FIGURE 5 1 LOCAL BUS LITTLE BIG ENDIAN AAA 17 FIGURE 5 2 INTERRUPT CONTROL STATUS REGISTER INTCSR 0X4C 18 FIGURE 6 1 ISOLATED DIGITAL INPBUTE L U a 20 FIGURE SA INPUT WIRING Gusta allea ala 23 FIGURE 9 1 HD50 SCSl 2 TYPE CONNECTOR L rr 24 FIGURE 9 2 MEZZANINE CARD CONNECTOR D A 25 TPMC600 User Manual Issue 1 3 Page 4 of 25 TEWS TECHNOLOGIES 1 Product Description The TPMC600 is a PMC compatible module and has 32 digital inputs galvanicallv isolated by optocoupler The individual inputs are potential free in relation to each other A high performance input circuit ensures a defined switching point and polarization protection against confusing the pole All inputs have an electronic debounce circuit with a freelv programmable deboun
3. Only RW Read Write R C Read Clear R S Read Set 1999 2003 by TEWS TECHNOLOGIES GmbH Issue Description Date 1 0 First Issue June 1999 1 1 General Revision February 2003 1 2 Addition Technical Specification April 2003 1 3 Correction Debounce Time Register September 2003 TPMC600 User Manual Issue 1 3 Page 2 of 25 TEWS lt TECHNOLOGIES Table of Contents 1 PRODUCT DESCRIPTION 5 2 TECHNICAL SPECIFICATION T J 6 3 LOCAL SPACE ADDRESSING ici 7 3 1 PCI9050 Local Space Configuration U a uuu u u u 7 3 2 Local Register Space 1 iii 7 3 2 1 Data Input Register nanna anna nanna 8 3 2 2 Control e E EEN 8 3 2 3 Rising Edge Interrupt Enable Register nn 8 3 2 4 Falling Edge Interrupt Enable Register nn 9 3 2 5 Rising Edge Interrupt Status Register 9 3 2 6 Falling Edge Interrupt Status Register nn 9 3 2 7 Debounce Time Register nanna nanna nanna 10 4 PENOSO TARGET CHIP a nnmnnn nnna 13 4 1 PCI Configuration Registers PCR ran 13 AAA A e iii 13 4 1 2 PCI Base Address Initialization narran cnn 14 4 2 Local Config
4. 0 20 208020 h TPMC600 1 1 21 313610 h Humidity 5 95 non condensing Weight 74g TPMC600 User Manual Issue 1 3 Figure 2 1 Technical Specification Page 6 of 25 TEWS TECHNOLOGIES 3 Local Space Addressing 3 1 PCI9050 Local Space Configuration The local on board addressable regions are accessed from the PCI side bv using the PCI9050 local spaces PCI9050 PCI9050 PCI Space Size Port Endian Description Local PCI Base Address Mapping Byte Width Mode Space Offset in PCI Bit Configuration Space 0 0 0x10 MEM 128 32 LITTLE Local Configuration Registers 1 1 0x14 1 0 128 32 LITTLE Local Configuration Registers 2 2 0x18 MEM 32 32 BIG Local Address Space 0 3 3 0x1C Local Address Space 1 4 4 0x20 Local Address Space 2 5 5 0x24 Local Address Space 3 6 6 0x30 Local Expansion ROM Space Figure 3 1 PCI9050 Local Space Configuration 3 2 Local Register Space 1 PCI Base Address PCI9050 PCI Base Address 2 Offset 0x18 in PCI Configuration Space Offset to PCI Register Name Access Size Base Address 2 Bit 0x0000 Data Input R 32 0x0004 Control RAW 32 0x0008 Rising Edge Interrupt Enable R W 32 0x000C Falling Edge Interrupt Enable R W 32 0x0010 Rising Edge Interrupt Status R W 32 0x0014 Falling Edge Interrupt Status R W 32 0x0018 Debounce Time R W 32 Figure 3 2 Local Register Space 1 After po
5. 00 11 21 digital inputs The standard signal level for these inputs is 24V DC The switching level of the inputs is between 7 5V and 14V All inputs are isolated bv optocoupler from the computer svstem and are also isolated against each other in groups of four inputs Group Ground Input 11 GND 11 IN 1 IN 2 IN 3 IN 4 GND 12 IN 5 IN 6 IN 7 IN 8 GND 13 IN 9 IN 10 IN 11 IN 12 GND 14 IN 13 IN 14 IN 15 IN 16 GND 15 IN 17 IN 18 IN 19 IN 20 GND 16 IN21 IN 22 IN 23 IN 24 GND 17 IN 25 IN 26 IN 27 IN 28 GND 18 IN 29 IN 30 IN 31 IN 32 Figure 6 1 Isolated Digital Inputs TPMC600 User Manual Issue 1 3 Page 20 of 25 TEWS TECHNOLOGIES 6 1 2 Debounce Function A programmable debounce function common for all inputs is implemented on the TPMC600 There is only one debounce time adjustable for all 32 TPMC600 10 20 or 16 TPMC600 11 21 digital inputs If the debounce function is enabled the input pin must be static for the programmed debounce time before the rising or falling edge is recognized as valid So only after a correct identification the Data Input Register is updated and an interrupt is generated The debounce function is disabled after power on and reset The debounce time is set to value 0 6 1 3 Interrupt Logic Interrupt generation can be individually programmed for each channel and input transition
6. 041 0x50 Miscellaneous Control Register 0x00780000 Figure 4 2 Local Configuration Register TPMC600 User Manual Issue 1 3 Page 15 of 25 TEWS TECHNOLOGIES 4 3 Configuration EEPROM After power on or PCI reset the PCI9050 loads initial configuration register data from the on board configuration EEPROM The configuration EEPROM contains the following configuration data e Address 0x00 to 0x0F PCI9050 PCI Configuration Register Values e Address 0x10 to 0x64 PCI9050 Local Configuration Register Values e Address 0x65 to 0x7C Not used e Address 0x7E to 0x7F TPMC variant See the PCI9050 Manual for more information Address Offset 0x00 0x02 0x04 0x06 0x08 Ox0A 0x0C Ox0E 0x00 0x0258 0x1498 0x1180 0x0000 s b 0x1498 0x0000 0x0100 0x10 OxOFFF OxFFEO 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x20 0x0000 0x0000 0x0000 0x0001 0x0000 0x0000 0x0000 0x0000 0x30 0x0000 0x0000 0x0000 0x0000 0x01B1 0x7880 0x0000 0x0000 0x40 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x001 1 0x50 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0041 0x60 0x0078 0x0000 OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF 0x70 OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF Figure 4 3 Configuration EEPROM TPMC600 xx Subsystem ID Value Offset 0x08 TPMC600 10 Ox000A TPMC600 11 0x000B TPMC600 20 0x0014 TPMC600 21 0x0015 TPMC600 User Manual Issue 1 3 Page 16 of 25 5 Configuration Hints 5 1 Big Little Endian PCI
7. Bus Little Endian Byte O AD 7 0 Byte 1 AD 15 8 Byte 2 AD 23 16 Byte 3 AD 31 24 Big Endian Little Endian 32 Bit 32 Bit Byte 0 Ca Byte 1 SE Byte 2 0123 16 Byte 3 SE 16 Bit upper lane 16 Bit Byte 0 Ca TA SE 16 Bit lower lane PA 8 Bit upper lane 8 Bit Byte 0 Ca 8 Bit lower lane PA Byte 0 D 7 0 Figure 5 1 Local Bus Little Big Endian TPMC600 User Manual Issue 1 3 TEWS TECHNOLOGIES Everv Local Address Space 0 3 and the Expansion ROM Space can be programmed to operate in Big or Little Endian Mode Page 17 of 25 Standard use of the TPMC600 Local Address Space 0 Local Address Space 1 Local Address Space 2 Local Address Space 3 Expansion ROM Space TEWS lt TECHNOLOGIES 32 bit bus in Big Endian Mode not used not used not used not used To change the Endian Mode use the Local Configuration Registers for the corresponding Space Bit 24 of the according register sets the mode A value of 1 indicates Big Endian and a value of 0 indicates Little Endian For further information please refer to the PCI9050 manual which is also part of the TPMC600 ED Engineering Documentation Use the PCI Base Address 0 Offset or PCI Base Address 1 Offset Short cut Offset Name LASOBRD 0x28 LAS1BRD 0x2C LAS2BRD 0x30 LAS3BRD 0x34 EROMBRD 0x38 Local Address Space O Bus Region Description Register Local Address Space O Bus Region Description Register Local Address S
8. Class Code Revision ID N 11800000 0x0C BIST Header Type PCI Latency Cache Line Y 7 0 00 00 00 00 Timer Size 0x10 PCI Base Address 0 for MEM Mapped Config Registers Y FFFFFF80 0x14 PCI Base Address 1 for I O Mapped Config Registers Y FFFFFF81 0x18 PCI Base Address 2 for Local Address Space 0 Y FFFFFFEO 0x1C PCI Base Address 3 for Local Address Space 1 Y 00000000 0x20 PCI Base Address 4 for Local Address Space 2 Y 00000000 0x24 PCI Base Address 5 for Local Address Space 3 Y 00000000 0x28 PCI Cardbus Information Structure Pointer N 00000000 0x2C Subsystem ID Subsystem Vendor ID N 000A 1498 0x30 PCI Base Address for Local Expansion ROM Y 00000000 0x34 Reserved N 00000000 0x38 Reserved N 00000000 0x3C Max_Lat Min_Gnt Interrupt Pin Interrupt Line Y 7 0 00 00 01 00 Figure 4 1 PCI9050 Header TPMC600 10 TPMC600 User Manual Issue 1 3 Page 13 of 25 TEWS lt TECHNOLOGIES 4 1 2 PCI Base Address Initialization PCI Base Address Initialization is scope of the PCI host software PCI9050 PCI Base Address Initialization e Write OxFFFF_FFFF to the PCI9050 PCI Base Address Register e Read back the PCI9050 PCI Base Address Register e For PCI Base Address Registers 0 5 check bit O for PCI Address Space Bit 0 O requires PCI Memory Space mapping Bit 0 1 requires PCI I O Space mapping For the PCI Expansion ROM Base Address Register check bit 0 for usage Bit 0 0 Expansion ROM not used Bit 0 1
9. TEWS S The Embedded I O Company TECHNOLOGIES TPMC600 32 16 Digital Inputs 24V Version 1 0 User Manual Issue 1 3 September 2003 D76600800 TEWS TECHNOLOGIES GmbH TEWS TECHNOLOGIES LLC Am Bahnhof 7 25469 Halstenbek Germany 1 E Liberty Street Sixth Floor Reno Nevada 89504 USA Phone 49 0 4101 4058 0 Fax 49 0 4101 4058 19 Phone 1 775 686 6077 Fax 1 775 686 6024 e mail info tews com www tews com e mail usasales tews com www tews com TPMC600 10 32 digital inputs front panel I O TPMC600 11 16 digital inputs front panel I O TPMC600 20 32 digital inputs P14 I O TPMC600 21 16 digital inputs P14 I O TEWS amp TECHNOLOGIES This document contains information which is proprietary to TEWS TECHNOLOGIES GmbH Any reproduction without written permission is forbidden TEWS TECHNOLOGIES GmbH has made any effort to ensure that this manual is accurate and complete However TEWS TECHNOLOGIES GmbH reserves the right to change the product described in this document at any time without notice TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein Style Conventions Hexadecimal characters are specified with prefix Ox i e 0x029E that means hexadecimal value 029E For signals on hardware products an Active Low is represented by the signal name with following i e IP_RESET Access terms are described as W Write Onlv R Read
10. To enable the interrupt after a reset the Global Interrupt Enable bit in the Control Register must be set to the value 1 Also the respective bit for rising or falling edge in the Rising Edge Falling Edge Interrupt Enable Register must be set The Global Interrupt Enable bit and also all individually interrupt enable bits are disabled after power on and reset TPMC600 User Manual Issue 1 3 Page 21 of 25 TEWS lt TECHNOLOGIES 7 Programming Hints 7 1 Local Read Write The local register design is developed for a long word 32 bit read write access A byte or word access could be fail Use also long word read write accesses at TPMC600 11 21 TPMC600 User Manual Issue 1 3 Page 22 of 25 TEWIS O 8 Installation 8 1 Input Wiring 24V L GND IN Figure 8 1 Input Wiring TPMC600 User Manual Issue 1 3 Page 23 of 25 TEWS TECHNOLOGIES 9 Pin Assignment I O Connector 9 1 Front panel UO IN 26 IN 27 IN 28 IN 29 IN 30 IN 31 IN 32 GND 11 GND 12 GND 13 GND 14 GND 15 GND 16 GND 17 GND 18 NC NC NC NC NC NC NC NC NC 25 IN 25 NC Figure 9 1 HD50 SCSI 2 type Connector TPMC600 User Manual Issue 1 3 Page 24 of 25 9 2 Mezzanine Card Connector P14 TEWS TECHNOLOGIES Pin Signal IN 22 IN 23 IN 24 IN 25 IN 26 IN 27 IN 28 IN 29 IN 30 IN 31 IN 32 GND 11 GND 12 GND 13 GND 14 GND 15 GND 16 GND 17 GND 18 NG NC Figur
11. ce time A version with 16 inputs is available as TPMC600 11 All inputs can generate an interrupt The signal edge handling is programmable Local Control Logic Figure 1 1 Block Diagram TPMC600 User Manual Issue 1 3 Page 5 of 25 TEWS lt TECHNOLOGIES 2 Technical Specification PMC Interface Mechanical Interface PCI Mezzanine Card PMC Interface Single Size Electrical Interface PCI Rev 2 1 compliant 33MHz 32 bit PCI 5V PCI Signaling Voltage On Board Devices PCI Target Chip PCI9050 PLX Technology Number of Channels TPMC600 10 20 32 digital inputs TPMC600 11 21 16 digital inputs Input Isolation Optocoupler for galvanic isolation also isolated to each other in groups of four inputs Input Voltage 24V DC typical Input Current 4 2mA typical 24V input voltage Input Switching Level 2V typical 7 5V minimum 14V maximum Input Signal Debouncing Electronic debouncing Zus to 440ms in steps of Zus common for all input channels can be disabled Input Interrupts 32 16 input interrupts trigger on rising falling or both edges I O Interface UO Connector TPMC600 10 11 HD50 connector TPMC600 20 21 PMC P14 I O 64 pin Mezzanine Connector Physical Data Power Requirements 250mA typical 5V DC Temperature Range Operating l 40 C to 85 C Storage 55 C to 125 G MTBF TPMC600 1
12. cess Reset Value 31 0 Bit O reflects the interrupt request status of input 1 for the falling R W edge bit 31 reflects the interrupt request status of input 31 All other bits are equivalent 1 Interrupt request pending 0 No interrupt request pending Writing 1 to clear an interrupt request of a specific input Figure 3 8 Falling Edge Interrupt Status Register TPMC600 User Manual Issue 1 3 Page 9 of 25 TEWS lt TECHNOLOGIES 3 2 7 Debounce Time Register TPMC600 User Manual Issue 1 3 Page 10 of 25 TEWS lt TECHNOLOGIES OO sos omo 004 sco oo oa sos ov 007 sco 3 oo aer 00 00 00 sos 5 006 0060 em 6 006 om wow s ov TPMC600 User Manual Issue 1 3 Page 11 of 25 TEWS TECHNOLOGIES Tvp Debounce Time ms Inaccuracy ms 350 000 50 000 52082 CB72 400 000 57 142 59522 E882 440 402 62 915 65535 FFFF Figure 3 11 Debounce Time Examples TPMC600 User Manual Issue 1 3 Page 12 of 25 TEWS TECHNOLOGIES 4 PCI9050 Target Chip 4 1 PCI Configuration Registers PCR 4 1 1 PCI9050 Header PCI CFG Write 0 to all unused Reserved bits PCI Initial Values Register writeable Hex Values AQ 24 23 16 15 8 7 0 0x00 Device ID Vendor ID N 0258 1498 0x04 Status Command Y 0280 0000 0x08
13. e 9 2 Mezzanine Card Connector P14 TPMC600 User Manual Issue 1 3 Page 25 of 25
14. nput channel 32 All other bits are equivalent 1 Interrupt Rising Edge enabled 0 Interrupt Rising Edge disabled Figure 3 5 Rising Edge Interrupt Enable Register TPMC600 User Manual Issue 1 3 Page 8 of 25 TEWS TECHNOLOGIES 3 2 4 Falling Edge Interrupt Enable Register The Falling Edge Interrupt Enable Register is a 32 bit wide read write register Bit Symbol Description Access Reset Value 31 0 Bit O enables the interrupt of input channel 1 for the falling edge bit R W 31 enables interrupt of input channel 32 All other bits are equivalent 1 Interrupt Falling Edge enabled 0 Interrupt Falling Edge disabled Figure 3 6 Falling Edge Interrupt Enable Register 3 2 5 Rising Edge Interrupt Status Register The Rising Edge Status Enable Register is a 32 bit wide read write register Bit Symbol Description Access Reset Value 31 0 Bit 0 reflects the interrupt request status of input 1 for the rising R W edge bit 31 reflects the interrupt request status of input 31 All other bits are equivalent 1 Interrupt request pending 0 No interrupt request pending Writing 1 to clear an interrupt request of a specific input Figure 3 7 Rising Edge Interrupt Status Register 3 2 6 Falling Edge Interrupt Status Register The Falling Edge Status Enable Register is a 32 bit wide read write register Bit Symbol Description Ac
15. on Registers are loaded from the on board serial configuration EEPROM The PCI base address for the PCI9050 Local Configuration Registers is PCI9050 PCI Base Address 0 PCI Memory Space Offset 0x10 in the PCI9050 PCI Configuration Register Space or PCI9050 PCI Base Address 1 PCI I O Space Offset 0x14 in the PCI9050 PCI Configuration Register Space Do not change hardware dependent bit settings in the PCI9050 Local Configuration Registers PCI Offset Register Value from Local Base Address 0x00 Local Address Space 0 Range OxOFFFFFEO 0x04 Local Address Space 1 Range 0x00000000 0x08 Local Address Space 2 Range 0x00000000 0x0C Local Address Space 3 Range 0x00000000 0x10 Local Exp ROM Range 0x00000000 0x14 Local Re map Register Space 0 0x00000001 0x18 Local Re map Register Space 1 0x00000000 0x1C Local Re map Register Space 2 0x00000000 0x20 Local Re map Register Space 3 0x00000000 0x24 Local Re map Register ROM 0x00000000 0x28 Local Address Space 0 Descriptor 0x01B17880 0x2C Local Address Space 1 Descriptor Ox00000000 0x30 Local Address Space 2 Descriptor Ox00000000 0x34 Local Address Space 3 Descriptor Ox00000000 0x38 Local Exp ROM Descriptor 0x00000000 0x3C Chip Select 0 Base Address 0x00000011 0x40 Chip Select 1 Base Address 0x00000000 0x44 Chip Select 2 Base Address 0x00000000 0x48 Chip Select 3 Base Address 0x00000000 0x4C Interrupt Control Status 0x00000
16. pace O Bus Region Description Register Local Address Space O Bus Region Description Register Expansion ROM Bus Region Description Register You could also use the PCI Base Address 1 I O Mapped Configuration Registers 5 1 1 PCI Interrupt Control Status Register All 32 input channels generate interrupts at pin INTA of the PCI bus The interrupt status can be read at the Interrupt Status Register INTCSR of the PCI Controller PCI9050 1 Bit Description Access Reset Value 31 8 unused R 0 7 Software Interrupt R W 0 6 PCI Interrupt Enable R W 1 5 Local Interrupt 2 Status R 0 4 Local Interrupt 2 Polarity R W 0 3 Local Interrupt 2 Enable R W 0 2 Local Interrupt 1Status R 0 1 Local Interrupt 1 Polarity R W 0 0 Local Interrupt 1 Enable R W 1 Figure 5 2 Interrupt Control Status Register INTCSR 0x4C TPMC600 User Manual Issue 1 3 Page 18 of 25 TEWS TECHNOLOGIES 5 2 Software Reset Controller and LRESET A host on the PCI bus can set the software reset bit in the Miscellaneous Control Register CNTRL 0x50 of the PCI Controller PCI9050 to reset the Controller and assert LRESET output The PCI9050 remains in this reset condition until the PCI host clears the software reset bit TPMC600 User Manual Issue 1 3 Page 19 of 25 6 Functional Description 6 1 Digital Inputs 6 1 1 Optical Isolation TEWS TECHNOLOGIES The TPMC600 has 32 TPMC600 10 20 or 16 TPMC6
17. uration Register LCR u rn 15 4 3 Configuration EEPROM iii ai 16 5 CONFIGURATION HINTS La 17 5 1 Big Little Endiam is 38 ie i a u S au iaia lait 17 5 1 1 PCI Interrupt Control Status Register 18 5 2 Software Reset Controller and LRESET 8 nenne nunne nunne nnan nnmnnn nnna 19 6 FUNCTIONAL DESCRIPTION 20 6 1 Digital Ip 20 61 1 Optical Solan EE 20 6 1 2 Deboun e Function rali rea 21 GC Ware UE 21 7 PROGRAMMING HINTS 22 TA Local Read Write conoci it iii 22 B INSTALLATION siria 23 8 1 Input WiN eieiaeo aaaea aeaa a a es da 23 9 PIN ASSIGNMENT O CONNECTOR 24 9 1 Front panel O ii i i idea 24 9 2 Mezzanine Card Connector P14 l J Emman nanna nn J T 25 TPMC600 User Manual Issue 1 3 Page 3 of 25 TEWS lt TECHNOLOGIES Table of Figures FIGURE 1 1 BLOCK DIAGRANM i 5 FIGURE 2 1 TECHNICAL SPECIFICATION L n L nn SSS 6 FIGURE 3 1 PCI9050 LOCAL SPACE CONFIGURATION e 7 FIGURE 3 2 LOCAL REGISTER SPAGET escusa ka bdieha ee 7 FIGURE 3 3 DATA INPUT REGISTER iii ia 8 FIGURE 3 4 CONTROL REGISTER iii arcas lia 8
18. wer on or reset all read write registers are cleared to 0 TPMC600 User Manual Issue 1 3 Page 7 of 25 TEWS TECHNOLOGIES 3 2 1 Data Input Register The Data Input Register is a 32 bit wide read oniv register that reflects the actual status of the inputs Bit Symbol Description Access Reset Value 31 0 32 bit Input Data R Bit O represents INPUT 1 and bit 31 represents INPUT32 Figure 3 3 Data Input Register 3 2 2 Control Register The Control Register is a read write register Bit Symbol Description Access Reset Value 31 3 Not used and undefined during reads 2 Debounce Enable bit R W 1 enables the debounce function for all 32 inputs 0 disable 1 Not used 0 Global Interrupt Enable bit R W 1 enables interrupt for all 32 inputs 0 disable The input channels generate interrupts at pin INTA of the PCI bus Figure 3 4 Control Register Additional to this Global Interrupt Enable the Interrupt INTA must be enabled in the Interrupt Control Status Register INTCSR 0x4C of the PCI Controller PCI9050 1 Default after power on or reset INTA is enabled 3 2 3 Rising Edge Interrupt Enable Register The Rising Edge Interrupt Enable Register is a 32 bit wide read write register Bit Symbol Description Access Reset Value 31 0 Bit O enables the interrupt of input channel 1 for the rising edge bit R W 31 enables interrupt of i
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