STD 7000 7801 808SA Processor Card USER'S MANUAL
Contents
1. 3 2 1 REVISIONS foo m G REVISED PCN 9385 of fo oe A 1 CA 19 0 741524 vie 2 9 0 0 O 6 o gt 55559 REGD v3 7415244 602 5 575 9 4 Ite 4 p T4 S42 3 3 022 yj L K JN 424 14514581 ESS Aw st ES US 51 Ne TWERK Ne TWERK A 3 REQ D 31 2eOnVew Rie R Our SIM pP pU XUL ITEM DESCRIPTION DESIGNATION IDENTIFY WITH ASSEN BLY AND REV LE T TER USING RUBSER STAMP TUMPIRS AS SAS AN OIN COMP SIDE BOARS NO 102745 INDICATE 5 PIN NO TOF SOCKETS TYP PART LIST NO 102747 1 FCR ASSY FRCCZOURES SEE AS 1904 NOTES UNLESS OTHERWISE SPECIFIED 382 FROCESSOR CARO 2 ths tes ao NE uec mage 6 MEZ EE 5 4 3 mue TEST EQUIPMENT M825 8085 A SYSTEM ANALYZER The M825 System Analyzer is a portable cost effective instrument which supports the design development production and field service of 8085 and 8085A Microprocessor based systems The unit functions as a program monitor program2. vezO SYN X4 Wi svon armoe NI i s Ast age 1 Qom 4 8 wou O 39 G L 49 v lt tv 5 6 P 68 ov 021 21 ES BL vam a 6 a v 1 i 3 2223 our x i AN OE 3 oft 122 85 fu O 3 88 in 9 mU T a vw tot 83002939 133739 8 Age t 0 8 9 l 0443 20 NOILVIN3W31dW AYOWSW 1 214 1 MEME M me zE 341913 AD 09 Rov Input Output 1 0 Port Addressing The 7801 can address up to 256 each input ports and output ports The port address appears on the low order half of the Address Bus A0 A7 and is repeated on the high order half of the Address Bus 8 15 specific 1 0 port is addressed when the following conditions are met a The Address Bus A0 A7 contains the specific address of the 1 0 port 00 through FF hexadecimal b 10805 1 0 Request is active c IOEXP 1 0 Expansion is active d RD read is active to select an input port or WR write is active to select an output port The 8 bit input ports provide
3. 1 1 AL se TEE CYCLE OPCODE FETCH MEMORY REAO THE AODRESS PC 1 POINTS TO THE SECONO BYTE OF THE INSTRUCTION Low ORDER BYTE OF THE OIRECT AOORESS THE ADORESS CONTENTS OF THE PROGRAM COUNTER POINTS TO THE FIRST BYTE OPCOOE OF THE INSTRUCTION ADORESS BUS OATA BUS INSTRUCTION OPCODE M M RR I CT FIGURE 25 TIMING FOR STAD INSTR STOR FORM NO 101905 INSTRUCTION CYCLE PRO LOG CORPORATION dh THE 55 POINTS TO THE THIRD BYTE OF THE INSTRUCTION HIGH ORDER BYTE OF THE DIRECT AODRESS MEMORY REAO MEMORY WRITE THE 55 15 THE OIRECT ADORESS ACCESSED IN M2 ANO M3 CONTENTS OF THE ACCUMULATOR TEAS Sy rat SAS CUMULATOR DIRECT 106903 42 P AP The first machine cycle in the instruction 1 in Figure 25 is always used to read the instruction s operation code opcode from the program area of memory 15 called the opcode fetch cycle and is used by the 8085A to decode the instruction and prepare itself for the operation specified The opcode fetch cycle always requires a minimum of four time states 1 2 T4 although some instructions stretch by adding T5 and T6 to gain additional time Certain instructions execute fully during the opcode fetch cycle Other instructions require additional machine cycl
4. Specific abbreviations are given in the Legend on each page of the specification Denotes low level active signal PRO LOG CORPORATION 224 FORM NO 101905 CYCLE CLICRX fo NL SYMBOL PARAMETER TAVDV D Any Data i line 00 07 R RD line L Low state H Highstate V Valid be valid Data setu Address valid before bus data must be valid i 525 AS TRLDV RD active before bus data must RD pulse width Data hold time 20 T IRL cr ee 7 u 23 4 1 t tame Bs i TRUDE f e _ _ 5 2 4 7 cra PE EE 250 i ns 2 High Data bus drivers OFF high impedance impedance read mode after 0 ns RD active Address hold time after RD 5 135 ns inactive FIGURE 10 READ TIMING MEMORY FETCH INPUT PORT INTERRUPT INSTRUCTION NOTE onboard memory read operations Section 6 the Data Bus does not enter the high impedence read mode instead the 7801 drives data fetched from the onboard memory sockets onto the Data Bus to facilitate logic state analysis The access time for onboard memory devices may not exceed the values shown for TAVDV and TRLDV shown above T IN 3 rt MIN FORM
5. SE SET 1 STATE OF INDICATED FLAG COMPLEMENT AJ ADJUST DECIMAL ACCUMULATOR FLAGS PAIRED AR ROTATE RIGHT 8 GENERAL REGISTER PAIRS AL ROTATE LEFT 16 BIT DATA POINTERS 5 PUSH VIA STACK HL PL PULL VIA STACK ANY REGISTER PAIR R ANY SINGLE REGISTER INPUT FROM PORT M MEMORY ADDRESSED INDIRECTLY OUTPUT PORT i INTERRUPTS MISCELLANEOUS EN ENABLE 0 DISABLE PC PROGRAM COUNTER UN UNCONDITIONAL JP JUMP 5 STACK POINTER NONMASKABLE INTERRUPT E ME TO IN x REGISTER IMMEDIATE DATA MODIFIER MSB MOST SIGNIFICANT BIT xx REGISTER PAIR MODIFIER RTS RETURN FROM SUBROUTINE c Ue CONDITION HLT HALT Px PORT ADDRESS 1 byte LABEL MEMORY ADORESS 2 bytes Figure 17 STD MNEMONICS PRO LOG CORPORATION FORM NO 101905 REV 1512 106903 A FORM NO 101905 INSTRUCTION STANDARD INTEL CATEGORY MNEMONIC MNEMONIC LDA x LDB x LOC x LDO x LDE x LDH x LDL x MOMENT LDA x LDB x LDC x 100 LDOE x LDH x LDL x LDAD STAD LDAO STA LDA LMR LDAN STAX D LDA m LDB m LOC m LOD m MOV r M LDAX B LDE m LDH m LDL m STAN LDAX D ADD r AOC r SUB r SBB r CMP r ADA x ACA x SCA x SUB M SBB M XRA x CPA x XRA M ORA M ADI SUI 58 ANI ORI RLA RRA RLAC RRAC
6. 22 22 M 7 ALM CARRY 1 i i OPA ADORESS 1 oe ee eee CUT i INSTRUCTION 1 REGISTER INTERRUPT t J x y t 4 ee ae eg 71 t ROM h JP i STACK MEMORY ra ADDRESS INPUT PORT 1 1 DIRECT A H T INDIRECT 1 8 1 ADORESS RT ADORESS XM PROGRAM 2 4 i i ADDRESS 1 m COUNTER i t ti t 2 2 m lt gt e mo om oo lt gt 48 rf FIGURE 15 8085A PROGRAMMING MODEL Data flow Memory Port Address PRO LOG CORPORATION FORM NO 101905 8085A Architecture 8085A processor figure 15 consists of 8 bit instruction register 16 bit Program Address Counter a 16 bit Stack Pointer six 8 bit General Purpose Registers that can be paired to form three l6 bit Register Pairs and 8 bit Arithmetic Logical Unit ALU containing an 8 bit Accumulator Register and 5 bit Flag Register 8 bit interrupt register provides serial 1 0 capability and additional interrupt control Instruction Register The 8 bit Instruction Register provides storage and decoding for instruction operation codes opcodes as they are re
7. Bank Selection Jumpers G and H hold MEMEX and IOEXP respectively active by connecting the traces to ground on the 7801 card At least one additional 64K memory bank and 256 1 0 port bank could be enabled on the same motherboard by employing memory 1 0 cards which regard MEMEX and IOEXP as high level active signals Thus a high level on these traces would select the alternate memory or 1 0 bank while a low level selects the primary banks the user wishes to implement alternate memory 1 0 banks open jumper trace MEMEX or H IOEXP the 7801 This allows peripheral card to drive the bank expansion traces as required Note that the 7801 s onboard memory sockets are not qualified by MEMEX a thus remain available regardless of the state of MEMEX providing a convenient location for the instructions which control the memory bank selection FORM NO 101905 DOCUMENTATION PRO LOG CORPORATION s 51 44 7 Uo R133 7445240 8 2 g3 3 7 39 el 21 8452 F7 n 2 3 4 INTR 2 53 LPS E INTR 6 5 2 2 5 ES INTRS SA 3 d 4 TRUE CU Sv ix 1 1 65 35 ror Rit 1941484 22 55 3446 4 Re LOUJF 2208 ees e5v Qe 15V gt 5278 0 1 4 Sov 50 a 74 26 WALLS c
8. OUT OF RANGE Jo CYCLE COUNT mmn STATUS m 5 5 MEMORY MEMORY WRITE READ MS 4 MS MG M7 MB VO WRITE lt 10 READ CLOCK HALT REGPRUPT BUSACK ENABLED MAE FADE pose NOT FOUND AUTOMATIC Mes REFRESH INSTRUCTION 02 INSTRUCTIONS ADDRESS ADORESS COUNT 1 EXTERNAL INPUT E LINE ADDRESS CLEAR INSTRUCTION CYCLE gt DISPLAY ADORESS ADDRESS LATCH OFF ENABLE TRIGGER TRIGGER OUT M825 Front Panel ADDRESS CONTROLS ADORESS Switches Sixteen address bit select toggle switches broken into two groups Page Address high order address thru 415 and Line Address low order address or AO thru A7 used to establish the trigger reference address RUN STOP Switch Selects dynamic mode microprocessor continues to run or static mode microprocessor is stopped at Data Latch time and may be stepped through the program COMPARE STEP Switch Is only functional in stop mode and selects Stop on Address Compare and single Step on cycle or instruction MEMORY Switch Selects examination of data flow to from memory location defined by Page and Line Address switches or I O device defined by the low order Line address switches HOLD REFRESH Switch Controis latching of the data display In HOLD the display is frozen the first time the selecte
9. TH time states are clock periods during which the 7801 has relinquished the STD BUS allowing DMA operations to proceed with an alternate controller card Equivalent to 8085A Hold mode 2 The following Control Bus lines are floated when BUSAK is active RD IORQ MEMRQ MCSYNC STATUS 1 STATUS 0 INTAK SYSRESET DATA BUS 00 07 ADDRESS BUS 0 15 o FIGURE 7801 STD BUS TIMING FOR DIRECT MEMORY ACCESS DMA OPERATIONS FORM NO 101905 Mechanical The 7801 meets all STD BUS mechanical specifications Refer to the Series 7000 Technical Manual for outline dimensions If the Interrupt and Serial 1 0 access socket JI is used one additional open card slot on the component side of the 7801 may be needed for ribbon cable access depending on the connector and cable type used Environmental PARAMETER MIN UNITS Free Air Ambient o Operating Temperature Absolute Free Air Ambient 75 Temperature Relative Humidity Noncondensing Absolute Nonoperating Relative Humidity Noncondensing FIGURE 14 ENVIRONMENTAL SPECIFICATIONS PRO LOG CORPORATION cas FORM NO 101905 SECTION 4 8085A ARCHITECTURE AND INSTRUCTION SET 226 STAN LDR _____ __ 2 a OUTPUT PORT LDAN 1 t Sae rrr ee EXE MEMORY EI 129 ATA
10. PRO LOG STD 7000 CORPORATION 7801 8085A Processor Card USER S MANUAL 7801 8085A Processor USER S MANUAL DIL PRO LOG CORPORATION 9 81 7801 USER S MANUAL TABLE OF CONTENTS SECTION TITLE PAGE 1 INTRODUCTION 2 THE STD BUS STD BUS Summary 7801 Pin Utilization Control Bus Signal Table Processor Status Codes 3 7801 SPECIFICATIONS Power Requirements Drive Capability and Loading Clock Generator Timing and Waveforms Mechanical Environmental 4 8085 ARCHITECTURE AND INSTRUCTION SET 8085A Programming Model 8080 8085A Z80 Compatibility 8085A vs 8085 Characteristics STD Instruction Mnemonics Instruction Cross Reference Table 8085A Instruction Set Interrupts 5 PROGRAM INSTRUCTION TIMING Introduction WAIT States DMA Mode Instruction Timing Table Programmed Timing Example 6 MEMORY AND 1 0 MAPPING AND CONTROL Memory Addressing 12K Byte Onboard Memory Input Output Port Addressing Onboard Serial 1 0 Lines 7 PROGRAM AND HARDWARE DEBUGGING Microprocessor Logic State Analysis Instruction Diagnostic Tables M825 System Analyzer APPENDIX A 7801 STRAPPING OPTIONS 2 SCHEMATIC ASSEMBLY DIAGRAMS M825 SYSTEM ANALYZER DATA SHEET PRO LOG CORPORATION ec gt FORM NO 101905 SECTION ONE PRODUCT OVERVIEW 8085A PROCESSOR CARD This card combines a buffered and fully expandable 8085A microprocessor with onboard RAM and PROM sockets
11. Load interrupt Mask Write Serial Output from Accumulator INPUT OUTPUT INSTRUCTIONS Input from Px to ACC The Second Byte Px is a 2 digit hex port address Output from ACC to Px No operation Figure 198 8085 INSTRUCTIONS PRO LOG CORPORATION gt 45 FORM NO 101905 5 SIGN 4 ZERO D GECIMAL half carry CARRY Carry borrow from sin NOU TOUR ar sets Undefined 1 for even parity carry trom bit 3 OF 2 1 if zero same as bit 7 of resuit FIGURE 20 FLAG BIT ALLOCATION IN REGISTER F AUTOMATIC MEMORY OPERATIONS PSP JS JI Page at 5 1 Line at SP 2 PLP RTS Line from SP Page from SP 1 HL L gt SP gt SP 1 LDPO HL L gt ADR STPO HL lt gt ADR 1 FIGURE 21 AUTOMATIC MEMORY ALLOCATION BY INSTRUCTION NOTE This table shows how memory is allocated automatically by the processor when certain instructions are executed For example the PLP instruction pulls a line address or low order register C E F or L increments the SP then pulls a page address or high order register y A B D or H and increments the SP again leaving the SP two counts higher than its initial value PRO LOG CORPORATION A FORM NO 101905 REGISTER AFTER LOA
12. The 7801 includes 1K byte of RAM with sockets for up to 4K and sockets for up to 8K bytes of ROM or EPROM An STD BUS system using the 7801 card be expanded to full 8085A memory and I O capability The 7801 STD BUS interface may be disabled for OMA FEATURES 8085A Processor 4096 bytes RAM capacity onboard 1024 bytes RAM included 21141 type 8192 bytes ROM capacity onboard 2716 type 3 State Address Data Control Buses Power on reset pushbutton reset input Five interrupts Serial 1 lines socketed Single 5V operation 7801 6 25 MHz crystal 320ns time states 7801 1 6 144MHz crystal 325 5ns time states External clock input option J1 INTERRUPT 805 SERIAL 09 07 ACCESS AODRESS BUS A0 A15 MEMRQ au em eee INTRQ wr MCSYNC WAITRQ INTAK susar TATUS 0 ext CUR MEMEX 3 5 PORESET 4 sus surten IOEXP SHAO NG 1 SOCKETS ONLY INOICATES ACTIVE LOW LOGIC FIGURE ONE 7801 BLOCK DIAGRAM P FORM NO 101905 SECTION TWO THE STD BUS The STD BUS standardizes the physical and electrical aspects of modular 8 bit microprocessor card systems providing a dedicated orderly interconnect scheme The STD BUS is dedicated to internal communication and power distribution between cards with all external communication made via 1
13. 0 connectors which are suitable to the application The standardized pinout and 56 connector lends itself to a bussed motherboard that allows any card to work in any slot As the system processor and primary system control card the 7801 is responsible for maintaining the signal functionality defined by the STD BUS standard A complete copy of the STD BUS standard is contained in the SERIES 7000 STD BUS TECHNICAL MANUAL available from Pro Log Corporation 2411 Garden Road Monterey California 93940 STD BUS Summary The 56 pin STD BUS is organized into five functional groups of backplane signals 1 Logic Power Bus pins 1 6 2 Data Bus pins 7 14 3 Address Bus pins 15 30 4 Control Bus pins 31 52 5 Auxilary Power pins 53 56 Figure 2 shows the organization and pinout of the STD BUS with mnemonic function and signal flow relative to the 7801 Processor card COMPONENT SIDE CIRCUIT SIDE SIGNAL SIGNAL 1 5 Voits OC Bussed 5 Sussed 7 03 DATA 9 02 BUS 11 01 13 DO Digital Ground Bussed Digital Grou c ADDRESS BUS 5 Voits OC 5 Voits OC in Out Low Order Data In Out High Order Data Bus In Out Low Order Data Bus In Out High Order Bus In Out Low Order Oata Bus In Out High Order Cata Bus In Out Low Order Data In Out High Order Caza Bus Low Order Address B
14. 0 port addresses over the eight low order address lines AO through A7 on pins 15 17 19 21 23 25 27 and 29 The 7801 releases the Address Bus when BUSAK is active in response to BUSRQ as in DMA operations 4 Control Bus Pins 31 through 52 provide control signals for memory 1 0 interrupt and fundamental system operations Figure 3 summarizes these signals and shows how they are derived from 8085A signals The 7801 releases the Control Bus during BUSAK in response to BUSRQ except for the following output signals MEMEX IOEXP BUSAK CLOCK PCO 5 Auxilary Power Bus Pins 53 through 56 are not used by the 7801 and are electrically open The 7801 meets all of the signal requirements of the STD BUS standard Detailed timing information and specifications are in Section 3 o PRO LOG CORPORATION FORM NO 101905 MNEMONIC in out FUNCTION HOW DERIVED 8085A NAME ae Write to memory 1 0 Read from memory or 1 0 MEMRQ to read interrupt vector 110805 33 A0 A7 hold valid 1 0 address 10 M jMEMRQ 34 OUT 15 hold valid memory 10 M address OEXP 35 OUT 1 0 expansion control User removable ground iMEMEX 36 OUT Memory expansion control 61 ground iREFRESH 37 Not used Electrically open IMCSYNC 38 OUT One transition per machine ALE cycle undecoded status
15. 3m 3 25 Par au 3 9 0 m 3m 3 26 emescabensa 0 e oz 1 30 amp eweeTeorsmewmrat Te 5 5 2 em increment Decrement Pur Cound e 2 1 1 98 7 Grp eee pe prec pee HE Ci 55 1 Aor 3 26 QJ CooDpo ADDRESS foo to ON REGISTER PAIR ele CT p 527 73 S fe oen eai Me Ces fret 0 IN Read interrupt Masks and Serial In 4 195 128 1 30 interrupt Masks and Serai Out Fus 11 30 s 18 130 INSTRUCTION TIMING CALCULATIONS T 2 Nt Where T Execution Time Number of time states t Time State Time FIGURE 27 7801 8085A INSTRUCTION TIMING TABLE PRO LOG CORPORATION A I INSTRUCTION PRO LOG CATEGORY MNEMONIC LOA x LOB x LDC x LOD x LOB x LOC x LOO x _ ug c STAD STAD LDAO STA LDA LMA LDAN MOV M r STAX B 5 LDA m LDB m LDC m LOO m MOV r M LDAX B LDE m LDH m LDL m STAN LDAX D 0 1 1 SUB r SBB r ORA r ADA x ADO M ADC M SUB M SBB M XRA x ORA
16. Address Compare latch wiil be set and the next Address Compare occurring will stop the system via the WAIT line whether or not the Analyzer is in the Run mode Depressing CLEAR will release the system and reset the latch GROUND Pin Ground provided for all outputs and triggers USER SYSTEM REQUIREMENTS The READY RESET IN and TRAP lines must be capable of being wire ORed All interrupt lines must be strapped inactive if not used A minimum gate isolation resistance of 2202 is recommendec 3 M825 8085 SYSTEM ANALYZER MAXIMUM uP CLOCK FREQUENCY 3 2 MHz LOADING SPECIFICATIONS Inputs Address Data Clock and System Control Lines INTR RST 7 5 RST 6 5 and RST 5 5 READY RESET IN TRAP Display Latch and Address Enable Trigger Outputs READY RESET IN TRAP Address and Data Sync Out POWER REQUIREMENTS 50 60Hz 115 0 75 50 60 Hz 230 0 300 amp PHYSICAL CHARACTERISTICS Analyzer Control Unit Buffer Module and Cables Height 4 5 Height 1 125 Width 21 Width 2 5 Length 12 Length 4 5 Total product weight is less than 15 pounds OPERATING TEMPERATURE 0 C to 45 M825 INCLUDES Analyzer Control Unit 40 Pin Low Profile Connector Assembly Attache Case Two Copies of Operating Manual HIRES SPECIFICATIONS 0 125 TTL Loads 0 50 pf 0 25 TTL Loads 50pf gt 16 TTL Loads 100 pf 0 125 TTL Loads 100 pf 16 TTL Loads 50 pf 8 TTL
17. C d z s p Sub from A 4 2 5 Sub from W C 0 01 2 5 And with 0 00 2 5 Exctusive with 0 00 2 5 Or with A 3 2 0 00 21 50 1 Clear and carry 0 00 2 5 Clear carry Complement carry Compiement A Set carry 2 0 4 2 5 Adjust A0 C A0 A7 Rotate A right 7 7 AQ Rotate A left 0 Rotate right W C 7 0 Rotate A left W C Store A direct Load A direct 3 Byte Instructions Byte 2 Lower Order Address Line data bits 0 7 Byte 3 Higher Order Address Page data bits 38 15 Figure 19A 8085A INSTRUCTIONS FORM NO 101905 REGISTER PAIR OPERATIONS Increment Pair Decrement Pair Store A Indirect Load A Indirect Add to Pair HL Push SP AF c d z s p Pull SP Store HL Direct Load HL Direct Load Pair immediate Exchange Top amp HL Exchange Pair DE4 gt HL Load SP with HL PROGRAM ADORESS CONTROL INSTRUCTIONS DESCRIPTION OF INSTRUCTION Jump Condition Jump to Subroutine Return trom Subroutine Jump Indirect ur RESTART SPECIFIED ADDRESS IN PAGE 00 VA NL 0 3 bite instructidn JPN JUMP TO INTERRUPT INTERRUPT AND SERIAL 1 0 INSTRUCTIONS EE ee 2 00000000
18. Loads ON Source 40 mA min to 5V OFF Open Circuit 1 TTL Load Attache Case Height 6 5 Width 12 5 Length 23 Plug in Buffer Module and Cable LI MM 40 Pin DIP Clip Connector Assembly pot ren Of DIT PRO LOG TWX 910 360 7082 CORPORATION 2411 Garden Road Monterey California 93940 Telephone 408 372 4593 O USER S MANUAL DI PRO LOG CORPORATION 2411 Garden Road Monterey California 93940 Telephone 408 372 4593 TWX 910 360 7082 106903A 2K 9 81
19. STATUS 1 39 OUT Undecoded status Note 1 1 O 50 OUT Undecoded status Note i 1501 BUSAK OUT Acknowledges BUSRQ HLDA 805805 42 IN request DMA synchronous HOLD processor halt and 3 state driver disable I NTAK 43 Acknowledges INTRQ and replaces INTA i I NTRQ MA TRQ 5 IN NMIRQ h6 j IN SYSRESET 47 PBRESET 48 IN OUT CLOCK CNTRL PCO i 52 51 FIGURE 3 FARM NO 101905 IN OUT Priority chain INTR Nonmaskable interrupt request TRAP Maskable interrupt request Synchronous processor halt System power on and pushbutton RST reset one shot output Re CLOCK user optional jumper connection External clock input 2 times 01 user optional jumper Time State Clock frequency connection Note 2 Pushbutton reset input Time State Clock 1 2 crystal frequency RARE a Low level active Output buffer disabled when BUSAK active Denotes equivalent 8085A signal name information 1 See Figure 4 for status to PCO to 2 Trace on 780 connects maintain chain continuity 7801 CONTROL BUS SIGNALS MCSYNC STATUS STATUS 1 Signals 7801 Processor Status MCSYNC STATUS and STATUS 1 signals provide encoded status information which is peculiar to the 8085A microproces
20. Upper address lines 8 15 memory address stable shortly after the start of Tl b MEMRQ or 10805 and STATUS 0 STATUS 1 stable shortly after the start of S TUNA 45 AG AIS Lower address lines 7 memory line or 1 0 port address stable prior to the end of Tl d MCSYNC ALE issued during the first half of TI T2 RD WR signal active shortly after the start of T2 b memory or output port write operations output data i is stable on the Data Bus shortly after the start of 2 WAITRQ line is sampled at the midpoint of 2 BUSRQ line is sampled at the end of 2 TW If the WAITRQ line was active when sampled T2 processor enters the WAIT state instead of T3 If WAITRQ was inactive TW does not exist and the processor goes directly to T3 memory or input port read operations the processor reads the Data Bus at the lagging rising edge of the RD line during the second half of T3 memory or output port write operations the memory Or port device latches the data on the Data Bus at the lagging rising edge of WR in the second half of T3 c If BUSRQ was active when sampled during T2 the processor issues BUSAK and adlows DMA operations at the end of T3 T5 T6 These time states only occur in the opcode fetch cycle The processor uses them for internal operations and f new data or control state
21. a means for reading data or status lines into the processor to take part in programmed operations The 8 bit output ports provide a means for outputting program generated data or control states Typical input and output port circuits are shown in Figure 33 Onboard Serial 1 0 Lines The 7801 provides serial output line 500 and serial input line 510 which are accessed at pins 4 and 5 respectively of the User Interface Connector Jl The serial 1 0 lines are TTL compatible and suitable for serial communications between 7801 Processor cards in a local distributed processing system or as general purpose programmable TTL 1 0 control lines These lines allow direct serial communication over short runs of dual twisted pair signal ground lines up to 3 feet 1 meter or less unterminated For longer distances or for communication with UART isolation or signal conditioning may be necessary 500 and 510 are programmed by the LDA and LDI A RIM and SIM instructions as shown in Figure 22 PRO LOG CORPORATION A _ FORM NO 101905 an RST 205 BUFFERS 8 OUTPUT PORT pcd U2 1415244 74 527 oso 10ExPx 35 INPUT PORT A7 5 Ae 17 as 9 10503 33 0 0 21 13 744532 wre 3 Z ra D Por PORT SELECT DECODERS 2 0573 7 050 Em 6 FIGURE TYPICAL INPUT amp OUTPUT PORT IMPLEMENTATION and de
22. by the second byte of the IPA or OPA instruction allowing up to 256 each input and output ports In the 7801 all ports are provided on external cards One serial input line and one serial output line are provided at the 7801 JI interface connector These lines are operated by the LDA and LDI A instructions as shown in Figure 22 8080 8085 280 Compatibility Both the 8085 and the Z80 instruction sets include the 8080 s instructions as a subset Programs writtenexclusively in 8080 assembly codes will execute normally in the 8085 and the Z80 Note however that all three processors require a dif ferent number of time states in some instances to execute otherwise identical instructions and in most systems the processors use different time state clock frequencies Accordingly programmed timing such as count and test time delays will require modification when running 8080 or 280 program on 8085 and vice versa Note that only the 8085 instructions which are not part of the 8080 set are the LDA LDI A RIM and SIM serial 1 0 and interrupt mask instructions 3085 vs 8085 Characteristics The 8085A differs from the 8085 in the following characteristics a ALE Address Latch Enable ALE MCSYNC on the 7801 In the 8085A ALE is not generated during machine cycles 2 and 3 for the ADP Add Pair instruction only equivalent to Intel mnemonic DAD This applies only to the ADP instruction In addition ALE does
23. is active only in response to INTRQ as noted above However the coincidence of status signals shown in Figure 4 can be detected outside the 7801 when needed to note the processor s response to any of the other interrupts This function is seldom necessary since NMIRQ and the INTR 7 5 6 5 and 5 5 are all implied vector interrupts while INTRQ is a supplied vector interrupt requirin INTAK to control the information exchange between the 7801 and the interrupting device J Pro Log s 7320 Priority Interrupt Controller may be used to expand any of the 7801 s five interrupt inputs regardless of edge or level sensitivity Each 7320 card expands the interrupt line by a factor of eight and provides additional program control over the interrupt system while handling expansion signal protocol T INTR5 5 INPUTS 22 INTRQ INPUTS Ne i 22 Ae 866 c9o FOF 9 22517 INTR 5 54 7320 7801 CPU TR i 5 3 B 2 H n M E STD Ege 224 rae eee FIGURE 24 EXAMPLE 7801 INTERRUPT INPUTS EXPANDED WIT 320 CARDS Note Address and data busses omitted open collector low level active PRO LOG CORPORATION w TI FORM NO 101905 SECTION 5 PROGRAM INSTRUCTION TIMING Introduction The execution of a program instruction is a sequential process clock Section 3 is used to step the 8085A through a specifi
24. its task effect of holding WAITRQ active indefinitely is to halt the processor when WAITRQ is released the processor resumes operation with no change in its internal data or control states DMA Mode 8085A HOLD Mode Direct Memory Access DMA operations are controlled by driving the 7801 s BUSRQ line active when sampled at the end of the T2 time state This causes the 7801 to relinquish the STD Data and Address Busses and many of the Control Bus lines see Section 2 for signal functionality and Section 3 for precise BUSRQ BUSAK signal timing The BUSAK signal is used to signify that the 7801 s 3 state bus drivers are in the OFF condition allowing an alternate system controller to operate the memory 1 0 and other peripheral cards external to the 7801 on the same mother board Once in DMA mode the 8085A itself halts in a manner similar to the WAIT state with its internal data and control states protected for restoration when c BUSRQ is removed Like WAITRQ BUSRQ can be held active indefinitely PRO LOG CORPORATION 515 FORM 101905 Sequential Time State Operations The table in Figure 26 shows function of the time state within a machine cycle This table is a summary only with the precise timing needed to interface memory device ports WAIT state circuitry and DMA circuitry given in Section 3 5
25. not float during reset DMA operations and in WAIT states Note however that MCSYNC is floated on the STD BUS during DMA operations b INTERRUPTS The 8085A asserts ORQ during any interrupt acknowledge machine cycle while the 8085 asserts MEMRQ In the 8085A NMIRQ nonmaskable interrupt or Trap does not destroy the previous interrupt enable status The LDA instruction load accumulator with interrupt mask register or RIM must be executed after response to NMIRQ in order to restore the previous interrupt status ORM NO 101905 STD INSTRUCTION MNEMONICS The STD Instruction Mnemonics are a standard set of processor instruction abbreviations suitable for use as an assembly language for writing programs These mnemonics are standard in that they do not change but keep the same meaning regardiess of the processor they are applied to They are also standard that they are derived from a set of easily understood rules 1 The operator is a unique two letter abbreviation that suggests the action 2 The locator follows the operator and designates the operand or data to be operated on Instruc tions without operands ignore the locator 3 The qualifier states the addressing mode or provides further qualifying information for compound instructions 4 The modifier carries detailed support informa tion labels conditions addressing and data The operator locator and qualifier letters are
26. to 8K of EPROM or masked 10M devices and expand the to 4K The onboard memory sockets have addressing restrictions Figure 31 and are not accessatle in operations The onboard memory is organized as follows EPROM ROM sockets provide capacity for four 2716 or equivalent single 5V supply EPROM devices which can be mixed in any combination with 2316 or equivalent masked ROMs Each device is a 2048 byte 2K read only memory for a total capacity of 8192 8K bytes All of these devices are supplied by the user b RAM and RAM Sockets provides two 2114 or equivalent RAM devices organized as 1024 byte memory and sockets for six additional user supplied 2114 RAMs The 2114 is 1024x4 device and two chips are required for each IK of RAM added to the card The total RAM capacity of the 7801 with all sockets loaded is 4096 bytes PRO LOG CORPORATION FORM NO 101905 506101 ON WHOS pg 15 MEMORY DEVICE FULL HEXADECIMAL ADDRESS FIELD AN DESIGNATION AS SHIPPED OPTION A OPTION B OPTION C ROM 2K 0000 O7FF 0000 07FF C000 C7FF 000 C7FF ROM 1 2k 0800 OFFF 0800 OFFF C800 CFFF C800 CFFF ROM 2 2K 1000 17 1000 17FF 0000 D7FF 0000 D7FF ROM 3 2K 1800 IFFF 1800 IFFF 0800 DFFF D800 DFFF Z RAM 015 019 1K 016 020 1K 017 021 RAM 018 022 1K A N UNUSA
27. 0 4 10 OPA 3 20 PORT 00 Test for Five DCB CTR 1 28 ps End Times JP 20 JP 3 20 ys LOOP 4 times 2 24 ps once Output Line Low FIGURE 30 SAMPLE TIMING CALCULATION The total execution time for the functions performed once outside the loop 1 2 24 1 28 3 20 6 72 us One pass through the loop requires 1 28 3 20 2 24 3 20 1 28 3 20 14 40 us Five loop iterations requires 5 14 40 72 00 us however the JP ZO instruction requires only 2 24 us the fifth time instead of 3 20 us so the total time is corrected to 72 00 0 96 71 04 ps 71 05 6 72 77 76 ys The period of the pulses is found by adding the time the pulse is low to the time the pulse is high The pulse is low from the end of the first OPA instruction to the end of the second 2 24 3 20 5 44 ps The pulse is high from the end of the second OPA instruction to the end of the first or third OPA instruction as the program flows around or exits the loop 1 28 3 20 1 28 3 20 8 96 ys The period of the pulses is therefore 5 44 8 96 14 40 ys except the last pulse which is The total time for the program segment instructions inside and outside the loop is 13 55 44 us due to the action of the JP ZO instruction PRO LOG CORPORATION FORM 101905 SECTION 6 MEMORY AND 1 0 MAPPING AND CONTROL Memory A
28. 0 port addressing is always direct unless 1 0 is memory mapped Figure 21 shows automatic memory allocation for certain instructions Interrupt The 8085A has a single maskable vectorable interrupt STD BUS line INTRQ and a single nonmaskable implied vector interrupt NMIRQ Three additional maskable implied vector interrupts are provided at the 7801 5 Jl socket Figure 23 shows the addresses implied by these interrupts and figure 22 shows how the interrupt mask is programmed for these inputs The vectorable INTRQ input when acknowledged causes INTAK to be asserted INTAK is used to read an instruction supplied by the interrupting device into the processor via the Data Bus This may be any 2 or 3 byte instruction if a multibyte instruction INTAK will be asserted one or two more times after the opcode to read in the entire instruction The instruction s execution time is unchanged when supplied during interrupt The JI jump to interrupt o or RESTART instructions are an efficient means of handling up to eight interrupts without polling see Figure 198 PRO LOG CORPORATION A scs 27 FORM NO 101905 Inputs and Outputs 1 0 Separate 1 0 instructions and control signals allow 1 0 to be mapped separately from memory The OPA instruction writes data from the Accumulator to the specified output port and the IPA instruction reads data from the specified input port to the Accumulator Ports are specified
29. BLE 3000 3FFF 2000 2FFF 000 FFFF EO00 EFFF INTENDED APPLICATION ROM memory at 0000 allows onboard ROM mapped into upper quadrant of memory memory to take control immediately allows user supplied RAM memory with after system reset recommended for post reset bootstrap at address 0000 most control applications required in many data processing and development system applications M M RAM addressing options allow for compatibility with various existing firmware packages and 8085A based systems from other manufacturers NOTES implement wire jumper options and refer to Appendix A A RAM devices 015 and 019 are supplied with the 7801 All other memory devices are supplied by the user Maximum 2201 system addressing range is 60K 12K onboard plus 48K on external cards when using the 7801 s onboard memory If the onboard memory is disabled Appendix maximum system memory size is 64K and no mapping restrictions are imposed by the 7801 FIGURE 31 7801 ONBOARD MEMORY SOCKETS ADDRESS MAPPING m 4914201 q3vo AIMM WOII AN 722 ec 04 zT 4 5 501 084 18 54 10904 29 34 OISU 39 at wai wd a 900 24084 20 t de 29 d Ut Hide d 94 st Mt 725016 CET LLL Sm 514200 1517 S13Vd 29
30. EMONIC vous 2101 71141557028 eroon alfe __ fes Of puce pg 2202 12 22 0 0 4 s La Eoo EX 5 26 5 5 32 335 5 Memex ROUT se ss wr 57 REFRESH STATUS 517 SUSRG 5 2 BUSAK 125 INTRQ INTR 5 INTAK INTA TRAP PBRESET R CNTRL EXT CLK IN PCI AUX GND AUX V Designates Active Low Level Logic Designates equivalent 8085A pin names 106903 Jl SERIAL 1 0 AND INTERRUPT PIN OUT AND LOADING PIN NUMBER PIN NUMBER OUTPUT LSTTL INPUT LSTTL INTERRUPT 7 5 5 1 16 cw s a 5 ___ or owmwess 5 or SPARE 3 SPARE Ww Low Level Active FIGURE 7 SERIAL 1 0 amp INTERRUPT CONNECTOR PINOUT AND LOADING NOTE Pads are provided at spare pins for user connected signals PRO LOG CORPORATION AT TRE FORM 101905 Clock Generator The 7801 s 8085A microprocessor has an internal clock oscillator that serves as the primary timing element 7801 system The oscillator s output is divided by two to produce the time state clock T
31. L T 5 i 3 8825 gt 1 3 811313 1 413111 23155 1 12 15 ui E E 1 3111 13 813 i HE 2 1 3 1 3 31 12 3 13 8 3 ijs 31314111 31211111 31131111 1311 2148 2 lt 3 giv 1213 2 3 3 2 1 1 1 5 2 aH HET aa a iisbirii viriiiidii 32 23 8 Ela n HHE NUMBER 0 FIGURE 34 GURE 3 7801 DATA BUS CONTENT BY INSTRUCTION AND TIME STATE PRO LOG CORPORATION A was FORM NO 101905 B NENNEN NEN GCE CE E DECRE GE Pro Log M825 System Analyzer o Figure 35 below summarizes the ability of the M825 to capture format and display the information available from all the time states in any user specified machine cycle at any instruction in the operating program The M825 can debug the program System in dynamic single step and breakpoint modes track interrupts and DMA operations pick instructions out of nested loops and trigger other test equipment The M825 is portable and clips onto the 8085A device on the 7801 eliminating the need for test probes and a lengthy test setup procedure INGTRUCTIOQN CYCLE M825 SYSTEM ANALYZER 8085 MICROPROCESSOR 55 CYCLE e 5 Oma aus aca 7 PAGE UNE 0 AUN
32. M SUI 58 ANI ORI RLA RLAC RRAC RLC RRC RAL RAR CLAC CLC CMC CMA SEC AJA JMP JC JNC JZ JNZ CALL CNC CZ CNZ RET RC RNC RC RNZ ats RTS CX RP RM RPE RPO xm UXI B LXI H LXI SP JMP PUSH B PUSH D POP H PUSH PSW POP H lt POP PSW xer oem a INCP xx ICP INX D INX H INX SP 9 DECP xx DCP DEX B DEX D DEX H DEX SP c SHLO LHLD STPO HL LDPD HL SHLD LHLD SPHL ADP ADP HE 0408 DAD D DAD H DAO SP ira iea 22222 d O wma PRO LOG CORPORATION A gt 101905 El 28 TION CATEGORY AND MNEMONIC CROSS REFERENCE po UOI Eu REL CENE S NR DUE OPEM Instruction Timing Example The execution time for any routine program segment is found by totalling all of the time states in all of the instructions executed The factors affecting the execution time of a program segment are a The clock frequency which determines the time state period Section 3 b The specific instructions used which determines the number of time states in the segment Figure 27 The instantaneous Flag Register F bit states which summarize processor conditions when the conditional instructions jump jump to subroutine return from subroutine are executed F
33. MACHINE CYCLE STATUS SIGNALS active Active 0 Inactive 1 NOTES 1 The states shown for MEMRQ and 10805 during interrupt acknowledge cycles are those produced by the 8085A device For the earlier 8085 the MEMRQ and ORQ States are reversed 2 The Data is idle during the second and third machine cycles machine cycles for the ADP instruction Intel mnemonic is DAD No MCSYNC ALE signal is generated during these cycles 8085A only 3 Processor pins 10 M RD WR are in the high impedance state 4 Timing for STATUS 0 and STATUS l is similar to Address Bus timing Section 3 Q For additional information refer to the 8085A manufacturer s literature FORM NO 101905 SECTION 3 7801 SPECIFICATIONS Power Requirements RECOMMENDED EN LIMITS ABSOLUTE NONOPERATING LIMITS PARAMETER MIN MIN UNITS Vcc Note 1 4 75 5 00 5 25 0 5 50 Volts tee Note 2 1 00 1 40 Ampere FIGURE 5 801 POWER SUPPLY SPECIFICATION NOTES 1 In order to guarantee correct operation the following power supply considerations apply Vcc rise must be monotonic rising from 0 50 Volt to 4 75 Volts in 10 ms or less b If Vee drops below 4 75 Volts at any time it must be returned to less than 0 50 Volt before restoration to the specified operating range 2 specification assumes that all EPROM and RAM sockets on the 7801 are loaded Su
34. NO 101905 address Line 0 15 MEMRQ 1080 line line 00 07 W VI Valid fi X Don t 1 SYMBOL TAVWH FIGURE 11 PRO LOG CORPORATION TTE FORM NO 101905 PARAMETER Address valid before write e strobe WR rising ed MIN 625 Data setup time and WR pulse widthi 400 Data and address hold time WRITE TIMING MEMORY AND OUTPUT PORT MAX UNITS ns a n A MEARS gt 29 2 M as 4 TR TAVQL 7 CL H lt lt 4 es o see oe LEGEND i SYMBOL PARAMETER MIN MAX UNITS A Any address line 0 15 10805 CLOCK Low state High state TAVQL Aadress valid before WAITRQ jg must be active to insert 5 WAIT state in this cycle TQLCL WAITRQ setup time prior to clock transition 2 110 ns first WAIT state or in TW TCLQH WAITRQ hold time after clock transition in T2 for first WAIT statelor in eos D o o aea NOTE MEMRQ and IORQ timing is identical to Address Bus timing WAITRQ TIMING One WAIT st
35. OCK Indicates the processor clock is operational INTERRUPT REQ Indicates a System Interrupt has occurred HALT Indicates the processor is in the HALT state BUS ACK Indicates the processor has acknowledged and responded to a Bus Request RUN STOP Indicates status of the Machine READY line RUN for program execution STOP for processor idle WAIT state CYCLE COUNT Machine cycle indicator showing the cycle of the instruction with which the displayed data is associated NOT FOUND Indicates that the selected machine cycie was not found ENABLED Indicates the Address Interrupt feature is enabled OUT OF RANGE Indicates a Machine Cycle greater than 8 is being displayed SYNC POINTS ADORESS SYNC OUT Provides a negative pulse out for oscilloscope triggering each time the selected address compares with the system address lines DATA SYNC OUT Provides a delayed negative pulse out for oscilloscope triggering each time the Analyzer data display is latched The delay is a function of the setting of Address Instruction Machine Cycle Count selectors DISPLAY LATCH TRIGGER IN Each negative input edge causes the Analyzer to latch data at the next T2 time If the display selector is in the Hold mode Address and Data are latched for each negative edge and ail Address Compare Data is locked out If the Analyzer is in the Stop mode the system can thus be haited by the external event ADORESS ENABLE TRIGGER IN For each negative input edge an
36. RLC RRC RAL RAR CLAC CLC CMC Acc CMA SEC AJA CMC CMA STC DAA JMP JC JNC JZ JNZ CALL CC CNC CZ CNZ 1958 RNC RNZ ws A LXI B LXI O LXI H 54515 PUSH B PUSH D PUSH PSW XCP DE HL XCPT HL INCP xx ICP INXE INX D INXH INX SP DECP xx DCP DEX B DEX D DEX H DEX SP SHLD LHLD STPD LDPD HL SHLD LHLD LDP SPIHL SPHL JPN PCHL ADP ADPHL DAD B DAD D DAD H DAD SP ADDRESS REGISTER PAIR HLT HLT HLT iai 17 Luna ta sw 8085A INSTRUCTION SET Figures 19 and 198 present the 8085 8085A instruction set with STD mnemonics and functionally grouped by Register Memory Program Address Control Machine Register Pair Input Output and Restart instructions The flag status nomenclature is as follows Lower case letters are variable upper case followed by 0 or 1 indicate absolute condition Only the affected flags are tabulated The information presented in figures 19 22 is available from Pro Log as a shirt pocket programming aid card document 102967 REGISTER AND MEMORY INSTRUCTIONS INSTRUCTION IMMEDIATE 2 5 MEMORY DESCRIPTION OF REGISTER OPERATION INSTR M Load with register x increment register x 2 Decrement register x c dizsp Add to A C d z s p Add to A W C
37. SERIAL di INPUT DATA 5 5 ENABLED 7 5 LATCHED 6 5 1 6 5 ACTIVE 75 5 5 REGISTER BEFORE LDI A SERIAL OUTPUT 5 5 idus f DATA 6 5 SERIAL OISABLE WRITE 7 5 1 ENABLE 1 MASK WRITE RESET 2 3 ENABLE FIGURE 22 BIT FUNCTIONS OF THE LDA AND LDI A INSTRUCTIONS i PRO LOG CORPORATION TE FORM NO 101905 Interrupts 7801 has five interrupt request inputs with two NMIRQ INTRQ available at the STD BUS backplane and three INTR 5 5 INTR 6 5 and INTR 7 5 at Serial 1 0 and Interrupt Connector JI located near the card ejector The various interrupt inputs have different characteristics as summarized in Figure 23 INTERRUPT INPUT PROCESSOR ACTION GENERATES 8080 280 NAME sensitivity jPREORITY UPON RESPONSE INTAK COMPATIBLE MASKABLE NMIRQ iFalling edge Restart at hex land low level ANSE address 0028 no no INTR 7 5 edge Second Restart at hex yes address 003C INTR 6 54 Low level Third Restart at hex ne dis address 0034 INTR 5 5 Low level Fourth Restart at hex yes _ address 002 INTRQ Low level Lowest Read 1 3 byte yes yes yes instruction from to 3 pulses Figure 23 Interrupt Summary NMIRQ STD BUS pin 46 is nonmaskable and cannot be disabled by the progr
38. ad from program memory The second and third words of multiple word instructions bypass the Instruction Register These provide either data or addressing information and are routed directly to the General Purpose Registers the Accumulator or the Program Address Counter as required Program Address Counter The l6 bit Program Address Counter PC keeps track of the location of the next instruction to be executed from the program memory The PC increments automatically for each instruction word the JUMP and RETURN instructions modify the PC s address content by loading a new address 3tack Pointer l6 bit auto counting Stack Pointer SP provides the address of the subroutine return address stack location in RAM memorv The SP is used for controlling subroutines and interrupts and can also be used to push and pull data in memory at high speed Subroutine return addresses are automatically stored on the stack when a jump to subroutine JS instruction is executed and are retrieved when return RT instruction is executed Interrupts in 8085A systems are generally treated as subroutine jumps All of the General Purpose Register Pairs and the Accumulator Flag Register pair can be stored and fetched from memory using the SP as an indirect address register 16 bit data movement and address autocounting in the SP result in fast data manipulation The address stored in the SP be brought into the HL Register Pair for arith
39. am Its input characteristics require that it fall low then remain low to be recognized It cannot be recognized a second time until after the first response and then being returned high and then again dropped and held low NMIRQ is often used for catastrophic system events such as impending power failure but may be used for any interrupt function INTR 7 55 Jl pin 1 drives an edge sensitive latch in the 8085A Register bit 4 resets this latch with the LDI A instruction Figure 22 INTR 7 55 INTR 6 5 pin 2 and INTR 5 5 pin 3 are monitored and maske by the Register Bits 4 5 6 allow the program to monitor activity at the request pins regardless of whether the interrupts are enabled Figure 22 and bits bits 0 1 2 allow the program to read the mask using LDA to see which interrupts are enabled Bits 0 1 2 are also used to set or clear the three mask bits using the LDI A instruction to disable enable these three interrupts Note that bit 3 must be high in order to write into the interrupt mask INTRQ STD BUS pin 44 is identical to the 8080 s interrupt system INTRQ is a maskable interrupt and is enabled disabled with the and 051 instructions Register bit 3 when read with the LDA instruction shows whether the interrupt system is currently enabled or disabled Figure 22 When the 7801 responds to INTRQ it asserts INTAK interrupt acknowledge This signal is used by the interrupting devi
40. ate shown FIGURE 12 WAIT REQUEST The WAITRQ input allows the 7801 to enter the WAIT state in any memory 1 0 or interrupt acknowledge cycle while a slow memory device responds or until a control function such as an analog to digital converter finishes WAITRQ can also be used to single step the 7801 PRO LOG CORPORATION 77 FORM 101905 1 2746 mm pes TS Th 4 832 bg TOLCH i lt a CHGH EROR V ae Sule LS 5 gt 5 m d TKLBZ lt 42 notre 20 918 T Seam ere ARS DAVEN OS am s Mice EE ns oa BUSAK BUSRQ setup time C CLOCK TCHQH BUSRQ active after start of T3 BUSRQ hold time Address Bus LEGEND SYMBOL PARAMETER MIN UNTTS BUSRO TOLCH BUSRQ active prior to T3 200 TKLCH i BUSAK asserted prior to 1 Data Bus 25 Control Bus TH Note 1 TKLBZ Address Bus Data Bus and L L i most Control Bus Note 2 50 ns 2 High imp 7801 resumes drive the V Valid Address Data and Control outputs float after BUSAK is asserted allowing DMA operations 50 ns Busses after BUSAK goes inactive o an mer se NOTES
41. btract 75 mA 2716 EPROM and 50mA 211484 RAM for each device not used typical values Both the 8085A and 2114L devices require 10 milliseconds minimum after initial power on for stabilization of internal bias oscillators The 7801 5 power on reset one shot provides adequate stabilization delay only if Vcc risetime is less than 10 milliseconds Drive Capability and Loading The 7801 s STD BUS Edge Connector Pin List Figure 6 and Serial 1 0 and Interrupt Socket Jl Figure 7 give input loading and output drive LSTTL loads as defined the SERIES 7000 TECHNICAL MANUAL In general input lines and disabled 3 state outputs present 5 LSTTL loads maximum one LSTTL or MOS input plus 4 7K pullup resistor Output lines can drive a minimum of 50 LSTTL loads Pins which are unspecified in Figures 6 and 7 are electrically open Exceptions to the general loading rules a WAITRQ input which is 15 LSTTL loads PBRESET input which is 1 uF typical in parallel with 2 LSTTL loads CLOCK output which can drive 10 LSTTL loads PC and PCO which are connected to each other but to nothing else on the 7801 PRO LOG CORPORATION acs FORM 101905 FIGURE 6 7801 STD BUS EDGE CONNECTOR PINOUT AND LOADING STD 7801 EDGE CONNECTOR PIN LIST PIN NUMBER PIN NUMBER OUTPUT LSTTL DRIVE _ OUTPUT LSTTL DRIVE INPUT LSTTL LOADS INPUT LSTTL LOADS MN
42. c sequence for each instruction type The execution time for each instruction the time states needed by the instruction with the time state period set by the processor s clock oscillator The time state is the tatal of An understanding of the 8085A s instruction execution timing is important in real time programming where the program s execution rate is precisely matched When using a signal or logic to the speed requirements of the application state analyzer a knowledge of the time state sequence makes it possible to predict the data and control states present on the STD BUS backplane and at the 8085A chip pins at any given instant the execution of a program Figure 34 Machine Cycles Each transaction between the 8085A and its memory and 0 ports requires a distinct time period called a machine cycle In the 8085A machine cycles are composed of 3 to 6 time states with specific activity occurring in each time state Al though the number of time states and machine cycles vary among different types of instructionS they are precisely predictable for any given inscruction Figure 25 is a timing diagram for the STAD STore Accumulator Direct instruction This instruction requires four machine cycles MI through M4 with a total of 13 Figure 27 time states Four machine cycles are necessary because the instruction accesses memory four times ott TIME STATE 2 T4 1 2 T3
43. ce a read memory strobe the interrupting device responds by placing an instruction opcode onto the STD Data Bus during INTAK level active RE PRO LOG CORPORATION a FORM NO 101905 i If it is desired to vector the program to an interrupt service routine as is usually the case the instruction inserted during INTAK is generally either one of the JI Jump to Interrupt or RESTART instructions or one of the JS Jump to Subroutine instructions shown in Figure 19B These instructions store the return from interrupt address on the Stack via the Stack Pointer and allow the interrupt routine to exit back to the interrupted program using the RTS instructions Alternately any instruction in the instruction set can be executed out of sequence in the interrupt ackowledge cycle identified by INTAK Note that any l 2 or 3 byte instruction can be executed at interrupt The 8085A determines after decoding the opcode read in by the first INTAK whether a multibyte instruction requiring one two more INTAK cucles 15 being executed The 8085A automatically disables the interrupt system when acknowledging INTRQ thereby eliminating any critical timing for the INTRQ signal Simply wait until INTRQ is inactive before executing the ENI instruction and multiple responses to the same INTRQ signal cannot occur an input port bit or the Serial Input Jl pin 5 can be used to monitor INTRQ INTAK 570 BUS pin 43
44. characteristics of the microprocessor type used The characteristics of the 7801 are dictated by its 8085A microprocessor with LSTTL buffering added to enhance the card s drive capability The buffers decrease memory and 1 0 access time slightly The allocation of STD BUS lines for the 7801 is given below 1 Logic Power Bus 5V pins 1 2 and Logic Ground Pins 3 4 supply operating power to the 7801 Pins 5 and 6 are open 2 Data Bus Pins 7 through 14 form 8 bit bidirectional 3 state data bus as shown in Figure 2 High level active data flows between the 7801 and its peripheral cards over this bus When the 7801 fetches data from its onboard memory sockets this data also appears on the STD Data Bus With the exception of Direct Memory Access DMA operations the 7801 controls the direction of data flow with its MEMRQ 10805 RD and INTAK control signal outputs Peripheral cards are required to release the data bus to the high impedance state except when addressed and directed to drive the data bus by the 7801 Note that the low order address bits A0 A7 are multiplexed on the Data Bus A0 A7 appear on 00 07 while MCSYNC is active The 7801 releases tke Data Bus when BUSAK is active in response to BUSRQ as in DMA operations 3 Address Bus Pins 15 through 30 form a l6 bit 3 state address bus as shown in Figure 2 7801 drives high level active 16 bit memory addresses over these lines and 8 bit 1
45. d compare condition is met n REFRESH the display is refreshed each time the selected compare condition is met 2 M825 8085 SYSTEM ANALYZER DELAYED DATA CAPTURE CONTROLS ADDRESS INSTRUCTION PASS Toggle Switch Address Instruction mode allows data selection and display at an address up to 99 instructions beyond Compare Address Pass mode allows up to 99 passes through a selected address before data is displayed ADDRESS COUNT INSTRUCTION COUNT Rotary Switch Controls the number of address passes in Pass mode the number of additional instruction in Address Instruction mode CYCLE COUNT Rotary Switch Selects machine cycle of interest ADORESS INTERRUPT PUSH BUTTON ADORESS INTERRUPT Activation of this push button will set an Address Compare latch and the next occurrence of Address Compare will generate a Interrupt Appropriate interrupt service routines must be supplied by the user and located at the required memory location If the Analyzer is stopped by Address Compare the interrupt will be generated immediately DISPLAYS ADDRESS Displays 16 bit address as 4 Hex digits within a range of 0000 DATA a 2 digit Hex display and two groups of 8 bit indicators providing binary and hex data representa tion STATUS Eight individual indicators showing Data and Machine Status MEMORY READ WRITE AND 1 READ WRITE Indicate the function associated with the data being displayed CL
46. ddressing The 7801 s 16 bit Address Bus can directly address a 65 536 byte 64K memory A specific memory location is addressed when these conditions are met a The Address Bus contains the specific address of the memory location 0000 through FFFF hexadecimal b MEMRQ memory request and RD read WR write control signals are active MEMEX memory expansion is active Other factors affecting the 7801 s control of its memory are a In the Interrupt Acknowledge Cycle the 7801 issues INTAK in place of thememory enable signals when responding to INTRQ This causes the interrupting device to provide an instruction to the 7801 over the STD Data Bus b The 7801 can pause to wait for a slow memory mapped device or be single stepped by inserting WAIT states in memory access machine cycles c The 7801 can disconnect from the STD BUS and enter the WAIT state while Direct Memory Access DMA operations are conducted by an alternate system controller card DMA is controlled the BUSRQ BUSAK Bus Request Bus Acknowledge signals A typical memory implementation 15 shown Figure 32 12K Byte Onboard Memory The 7001 card as a combined and RAM memory the card which is large enough to store program and variable data required in many applications without the neeu for additional external memory cards The card is shipped with IK of RAM and sockets which allow the user to add up
47. ee 15 2 Hi DA 6 gt 2 7 SPARES HLOA 0 9 i 8 9 26 532 mtm 6 5 DECODER 10 SD R 5 ALL ME MORY g Tey 7 m gt as 15 022 NI 7 5 E Ace N 3 MEN _ 35 23 Hee _ 4 pa 9 gt Ioma 19744800 ROMS ADDRESS LATCHES n AM 10 RES 3 dus Ala 10 14 532 inta 5 1 59 2 27 7 7484 52 ROK 4 A3 dn uit y Ll A z WE FOR ASSY 102746 7231 JSE CENTER ROE ASSY Seen FAUNE bat MABRY STL PAL ALE SO OTHERWISE SETI ES 7 6 5 55 INTA we 47 BAAK X tu 7415144 MCEYN DA 5 9 i 4 Ge NE X e 2 P 3 lt 02105 5 HLDA 1 02745 _ EA REF DESIGNATION 7501 6 BUS BUFFERS 5 6 8 14 15 20 e STATUS 33 2 RD x 30 WR 9 3 gt 7 9 lt 5 aie 2 2 a e BEER RIN 14152448 ve 8 e i 1 B 29 AO 10 78 Lind 106575 RPORATION CARD PRESEI CLOCK ID 1102745
48. es up to M5 to execute the 8085 decodes the opcode during it will add additional machine cycles if it finds that a The instruction is composed of more than one byte with or 2 bytes of data memory address or 1 0 port address appended to the opcode b The instruction requires the processor to access memory 1 0 port as part of the function performed by the instruction Either condition results in additional machine cycles with each subsequent machine cycle following MI composed of only three time states For example the STAD instruction in Figure 25 is a 3 byte instruction opcode plus 16 bit address contained in the next two bytes following the opcode and the instruction is one which Stores one byte in memory Therefore STAD requires 4 machine cycles with M2 M3 used to read the 3 byte instruction and M4 used to perform the operation WAIT States Although the number of time states in any given machine cycle is fixed the user can insert one or more WAIT states in the cycle WAIT states are added by driving the 7801 s WAITRQ line active during the T2 time state in the machine cycle see Section 3 for precise timing requirements for WAITRQ The WAIT state is a do nothing time period that can be used to interface slow memories to the 7801 to cause the processor to pause while slow system function such as analog to digital converter or arithmetic processor completes
49. ger channels and operating modes needed to interface with a processor system such as the 7801 Data Bus Voltage Levels and Timing The 7801 and all of its peripheral cards in a given system will drive the Data Bus at different times and will do so with a variety of logic high and logic low levels all of which are different but within specification This presents two problems the operator will find it difficult to identify the source of any given waveform on the scope display and in order to see a specific data segment on the Data Bus the operator will find it necessary to synchronize the display with the processor s software program rather than with the voltage output of any one element of system hardware The logic state analyzer solves these problems by displaying formatted high low logic states rather than analog wave forms and by offering enough trigger channels and coincidence logic to allow literal program display synchronization A logic state analyzer is considered an essential troubleshooting aid for both program development and system maintenance 7801 based system where the needs of the Manufacturing Test and Field Service organizations are important considerations The logic state analyzer performs these basic functions a Tracks the actual instruction sequence as the program executes facilitating program debugging b Monitors control states and data passing between the processor and the system it con
50. he time state clock s period is the shortest program related period of interest in the system Instruction execution times are computed as whole multiples of the time state clock period see Section 5 The 7801 is shipped with a crystal installed which sets the system s time state period The only difference between the 7801 and 7801 1 is the resonant frequency of this crystal If desired the user can substitute a different crystal or replace the crystal with a TTL compatible clock signal generated externally Details of this option are given in Appendix A The frequency period characteristics of the crystal or external clock signal are shown in Figure 8 i CRYSTAL OR RESULTING EXTERNAL CLOCK TIME STATE FREQUENCY PERIOD COMMENT 320 00 ns 7801 operating rate fastest allowable rate for 8085 with onboard crystal 6 250 MHz 6 144 MHz 325 52 5 7801 1 operating rate compatible with SBC type systems and divisible to standard Baud rates 6 000 MHz 333 33 ns Fastest recommended external user provided clock signal with crystal removed 2000 00 5 Slowest allowable crystal external clock signal for 1 80854 1 000 MHz FIGURE 8 7801 Clock Oscillator Frequency Summary PRO LOG CORPORATION A ss JAM NO 101905 Timing Specifications Based 320ns 0 05 time states An understanding of the 7801 s sig
51. igure 20 d The number of instruction loops within the instruction sequence and the number of times each loop is executed loop iterations e f the program segment has more than one entrance or exit every combination of routes through the segment that are used by the program should be considered The following example shows how to compute execution times in a program segment The 8085 is programmed to generate a series of five short pulses at output port bit line Determine the overall execution time of the program segment and the period of the pulses generated FIGURE 29 INSTRUCTION SEGMENT TIMING EXAMPLE CORPORATION Alu PRO LOG FORM NO 101905 In the example in Figure 30 6 of the program segment s 9 instructions are within the loop and are executed 5 times each The last instruction in the loop JP 20 executes in one of two numbers of time states 7 or 10 Figure 27 according to whether or not the condition is met that the Z Zero flag is not set Z 0 Fewer time states are needed if the jump does not occur which 1 the case on the fifth iteration of the loop wore Sa EXECUTION TI FLOW DIAGRAM TIMES TIME EXECUTION TIME IN FUNCTION PERFORMED INSTRUCTIONS 320 NS 7801 SYSTEM Set Loop LRI 2 2 24 ys 15 Count 5 2 Pulse output Five ACC 1 28 us line once Times OPA 10 OPA 3 20 ps PORT 00 LDAI 7 LRI 2 2b ps 8
52. lay modes are dynamic mode in which the processor continues to run without analyzer interference and static mode in which the analyzer controls the processor WAIT line Delayed Data Capture affords the capability of observing a particular machine cycle up to 99 instructions past a chosen reference address The feature also allows observing the reference address after a user defined number of passes over that address A two decade address counter coupled with a single machine cycle counter provides the operator with the capability of simply dialing his way through the program under investigation This delay capability may be extended to any number by utilizing Stop Compare mode The M825 provides Memory or I O Address selection and Interrupt Trap and or Stop on Interrupt along with Hex address Hex and Binary Data and Status Displays The analyzer also features an synchronization output pulse during Address Compare and Data Display Latch time DATA SYNC OUT can be utilized to trigger an oscilloscope at any selectable instruction cycle Operator initiated functions include microprocessor push button Reset Latch Display or Latch Display and Stop at the next T2 state after trigger Stop on Next Address Compare after trigger and generation of non maskable interrupt at Address Compare time M825 8085 SYSTEM ANALYZER PRO LOG M825 SYSTEM ANALYZER 8085 A MICROPROCESSOR
53. metic manipulation with the ADP HL SP instruction and restored with the LDP HL SP instruction General Purpose Registers Consists of six 8 bit registers B C D E H L which can be treated as three 16 bit Register Pairs DE HL Specific instructions regard them as individual registers while other instructions treat them as pairs These registers are useful for the temporary storage of 8 bit or 16 bit data and as pairs can be used as indirect address registers Data can be transferred from register to register register to memory memory to register or from the second word of the instruction 8 bit or second and third words of the instruction 16 bit pair Individual registers and register pairs can be incremented decremented and added In 16 bit arithmetic carry propagates automatically from the lower register to the higher _PRO LOG CORPORATION ees 5 7 FORM NO 101905 The HL register pair forms the indirect memory address for register arithmetic and logical operations with any memory location HL can also be exchanged with pair DE or the top of the stack and loaded to the Stack Pointer and Program Counter indirect jump The BC and DE pairs can also be used for indirect addressing with the Accumulator A register only Arithmetic Logical Unit ALU The Accumulator Register A and five status flags Register F with associated control logic form the ALU The ALU provides add and subtract With
54. nal timing characteristics is necessary for the selection of speed compatible memory devices 1 0 functions and other peripheral STD BUS cards and for real time logic analysis of 7801 based STD BUS card systems The 7801 s timing characteristics are established by its 8085A microprocessor with additional delays added by LSTTL buffers The basic operations performed by the 7801 and the signals controlling these operations are shown in Figure SIGNALS OPERATION WAVEFORM EN Read from memory Figure 0 15 MEMRQ RS AN 0 15 10805 AN Read from an input port Figure A0 A7 IORQ A0 A7 Read interrupt instruction Figure 10 in response to INTRQ only FIGURE 9 BASIC 7801 OPERATIONS ZN Note that the following signals all have identical timing characteristics ADDRESS BUS 8 15 MEMRQ 10805 STATUS 0 STATUS 1 The waveforms on the following pages show timing measurements as a 5 letter code as follows First letter is lways T for Timing measurement Second letter is the abbreviation of the signal which starts the measurement D Data Bus Third letter is the condition of the start signal V Valid et letter is the abbreviation of the signal which ends the measurement R RD TDVRH fifth letter is the condition of the end signal H High For example TDVRH stands for Time from Data Valid until RD READ High inactive
55. or without carry borrow and the logical operations AND OR Exclusive OR complement and shift Arithmetic logical operations are performed on the A register using data from the other registers or from memory or from the second byte of the instruction immediate data The A register can be decimally adjusted and rotated right or left with or without the carry bit All 1 0 operations involve the data contained in Register A unless the system uses memory mapped 1 0 The Flag Register contains five status flags see figure 20 1 Carry Borrow 2 Zero Result 2 3 Sign 4 Parity P 5 Decimal half carry 0 The C Z S P flags can all be tested by the conditional jump and return instructions for decision making The D flag affects the decimal adjust Operation The C flag is affected by arithmetic logical and rotate instructions and has its own set clear and complement instructions Memory The 16 bit register pairs the Stack Pointer and the Program Counter allow addressing of 64K bytes of memory which can be any combination of ROM and RAM See Section 6 is required for stack operations to allow the use of subroutines and interrupt The instruction set allows long direct addressing 16 bit memory address is part of the instruction immediate 8 bit l6 bit data is part of the instruction and indirect 16 bit memory address is contained in one of the register pairs the Stack Pointer 1
56. po PR REFRESH stoe ie e wee TROC TIONS PAGE ADORESS ees 3 Er aor ne E Too 35 L T oes 5 FORM 101905 APPENDIX 7801 USER STRAPPING OPTIONS In new 7801 applications system characteristics such as memory mapping and clock frequency are generally arbitrary as shipped configuration of the 7801 is recommended to minimize system assembly costs and field service and repair documentation efforts Jumper wire strapping options are provided on the 7801 to allow processor upgrading in existing applications compatibility with similar cards from other manufacturers and compatibility with existing program firmware The strapping options for the 780 are identified by the letters A through M on the Schematic Pro Log document 102745 Assembly Diagram 102756 and by silkscreened letters on the 7801 circuit card The options include a Clock jumpers 0 output clock to STD 85 or input external clock in place of crystal b Mapping and Bank Control jumpers E M remap disable the onboard RAM and EPROM memory sockets and allow external control of bank selection MEMEX and IOEXP lines Clock Output Certain 8085A peripheral devices 1 0 functions and BUS or logic signal analyzers require access to the system clock Connecting jumper A places the 3 125 MHz clock 7801 on STD BUS t
57. race pin 49 CLOCK Note that the output driver for this signal is not floated during DMA operations Input an external clock be used to drive the 8085A s 01 input This should be a TTL compatible signal in the range of to 6 MHz with 50 duty cycle The 8085A will divide the external clock by 2 producing time states in the range 2000 ns to 333 ns Figure 8 The external clock is assigned STD BUS pin 50 CNTRL Remove the 7801 s crystal Yl and connect jumper B connect CNTRL to 8085A pin 1 8085A pin 2 should remain open MOTE the driver supplying the clock to the 9095 should have VOH 4hV 470 56 tolKpullup to 5 is recommended for standard TTL and LSTTL drivers Mapping The 7801 s onboard memory can occupy the lower quadrant of memory 0000 3FFF as shipped or the upper quadrant 000 or be disabled Within the enabled selections RAM can be contiguous with EPROM or separated for program compatibility with SBC type cards Figure 36 summarizes these selections and shows the jumpers required to obtain them PRO LOG CORPORATION FORM NO 101905 MEMORY ADDRES ADDRESS ASSIGNMENT JUMPER WIRES PRAMS E F LEM Lemno wrrr sooo erre wunpens opens ooo orrr rooo Frer open opens DISABLED DISABLED DON T CARE FIGURE 36 ONBOARD MEMORY MAPPING JUMPERS
58. s appear externally to the 8085A for logic analysis i Not all MI cycles use time states T5 and T6 Note that if present T4 T5 and T6 continue to execute internally in the 8085A even when the processor issues BUSAK and enters DMA mode at the end of T3 FIGURE 26 SUMMARY OF 8085A TIME STATE OPERATIONS PRO LOG CORPORATION mu OF FORM NO 101905 Instruction Timing Table The table in Figure 27 shows the actual number of memory bytes machine cycles and time states required for all of the 8085A instruction set Three time state periods are included for convenience with the full execution time of the instructions shown for the three different time state periods The time state periods shown are a 320 ns 7801 state time the fastest allowed for the 8085A b 325 5 ns 7801 1 and SBC type state time 488 ns Included for comparison with Pro Log s older 8080 based systems note some 8085A instructions execute with fewer time states others with more time states than 8080 identical instruction functions Figure 27 uses the concept of Instruction Categories where similar instruction types are grouped without regard to specific instruction mnemonics For example the 49 load register with register instructions LDA A LDA B all have identical timing and are grouped together as the LRR group Figure 28 is included to support Figure 27 It shows how the Instruction Categories are formed
59. sor These signals are useful for displaying processor status in logic signal analyzers and can be used to drive certain peripheral chips and systems designed to work with the 8085A specifically The use of these signals is not recommended in systems where microprocessor device type independence is a design goal MCSYNC serves a dual function Its leading edge denotes the approximate start of a machine cycle Section 3 Counting the MCSYNC transitions allows a logic signal analyzer to select a specific machine cycle within a multi cycle instruction for analysis The lagging edge of MCSYNC occurs when a stable memory line address or 1 0 port address is present on the STD Data Bus The 8085A device multiplexes its low order address lines A0 A7 during time state Tl the address information is followed by data in subsequent time states within the machine cycle The lagging rising edge of MCSYNC is used on the 7801 to latch the low order address MCSYNC is equivalent to the 8085A s ALE Address Latch Enable output signal STATUS 0 and STATUS 1 can be decoded externally to identify the type of machine cycle in progress as shown in Figure 4 SEE NOTE MACHINE CYCLE TYPE STATUS Ce NONE OO pe __ ___ Aeinowtedge ime or vro e Acknowledge NMIRQ and interrupts 5 5 6 5 7 5 Bus idle during ADP Add to H L pair instruction E 2 HALT instruction HH FIGURE 4
60. strung together to form the instruction mnemonic The modifier when needed stands alone either in its own separate column or separated by spaces or additional lines in written text The instruction mnemonic is an abbreviated action statement containing an operator a locator and a qualifier plus a supplemental and separate modifier OPERATOR LOCATOR INSTRUCTION DESCRIPTION fare Return rom Subroutine _____ ta a B 77 7 ue A umswB Load A indirect using ac Jump to Subroutine Figure iw Examples of Instruction Mnemonic Structure PRO FORM NO 101905 LOG CORPORATION wee The following table defines all STD mnemonics and contains specific 8085 notation used in the instruction tables figures 19 198 4 STANDARD MNEMONICS DEFINITIONS LOCATORS MODIFIERS QUALIFIERS OPERATIONS LD ACCUMULATOR REGISTER WITH CARRY ST STORE 8 0 GENERAL 8 BIT REGISTER ic INCREMENT H L 8 BIT REGISTERS D DIRECT ADORESSING DEC IMAL OECREMENT IMMEDIATE ADDRESSING AD AC ADO WITH CARRY FLAG REGISTER INDIRECT ADDRESSING i SU SC SUBTRACT WITH CARRY i T OF STACK i AN AND c CARRY FLAG OR INCLUSIVE OR 4 DECIMAL FLAG EXCLUSIVE OR z ZERO FLAG 5 SIGN FLAG MSB CLEAR PARITY FLAG
61. to hardware integrator and provides many of the display functions of acomputer control panel FEATURES Tests Systems using the 8085 or 8085A Microprocessor Dispiays Address Data Machine Cycle and Status e Static and Dynamic Display Modes System Run Step Control System Reset Push Button Connects to Processor Chip Via Clip On or Low Profile Connector Oscilloscope Trigger at Address Compare or Data Display Time Delayed Data Capture Memory or I O Address Select Non Maskable Interrupt Capability at Address Compare e External Controi of Data Display e Address Stop Interrupt Trap and Display Interface Buffer to Minimize Microprocessor Loading High Impact Attache Case M825 System Analyzer in Case The M825 is self contained and easily connected to your system microprocessor by means of asingle DIP clip or low profile connector It is useful as an alternative or complement to software techniques for program development or debugging of 8085 based microprocessor systems Since it is easily attached the M825 System Analyzer together with adequate program documentation is an ideal tool for field service or production The Analyzer allows examination of the system address data and status during a user specified machine cycle at the desired Compare Address Observation ofthe system is possible at full system speed or by single step by instruction or machine cycle The possible disp
62. tols allowing the system external to the processor card to be observed at the same time as the program flow using the same display c Provides a multi qualified trigger to a conventional oscilloscope when analog measurements are unavoidable e g propagation delay through a suspected memory device PRG LOG CORPORATIONA TE FORM NO 101905 Figure 38 below shows the Data Bus content during the various time states for all of the 8085A s instructions listed by Instruction Category see also Figure 28 This is the information the user would expect to see presented on a logic state 8 analyzer with the 7801 s Data Bus displayed a He HERE 85 11 3 LIB ee ies EN e WRITE STACK W MEM R MEM WRITE STACK MACHINE CYCLE THREE our 25 3253 33 i lt lt lt zizz n e e e CAC 2 2200 el WRITE MACHINE CYCLE TWO ADA STATUS MACHINE CYCLE ONE HI SALVLE v1vQ M vLYO 2 18 3 4454 133 AQv3u OL 563 9 um 314 E 513 01111111 DL
63. us Low Order Address Bus Low Order Address Bus Low Order Address Bus Low Order Address Bus Low Order Address Bus Low Order Address 8us Low Order Address High Order Acdress Bus High Order Accress Bus High Order Address Bus High Order Agaress Bus High Order Adaress Bus High Order Adcress Bus High Order Aadress Bus High Order Address Bus Write to Memory or 1 Read to Memory or LO Address Select Memory Select IOEXP Expansion MEMEX Memory Expansion REFRESH Refresh Timing CPU Machine Cycie Sync CONTROL STATUS 1 CPU Status STATUS 0 CPU Status BUS BUSAK Bus Acknowiedge BUSRO Bus Request INTAK Interrupt Acknowledge INTRQ Interrupt Request WAITRQ Wait Request NMIRQ Non Maskabie Interrupt 47 SYSRESET System Reset 48 Push Button Aeset o 49 CLOCK Clock from Processor 50 CNTRL AUX Timing PCO Priority Chain Out PCI Priority Char tn AUXGNO AUX Ground AUX V AUX Negative 12 Voits 51 52 54 805 56 Low Level Active Indicator F amp 2 STD Bus FORM NO 101905 _ 3 STD BUS Pin Utilization by 7801 Since the STD BUS standard does not specify timing or require that all available pins used the timing signal allocation assumes many of the
64. using both Pro Log s STD instruction mnemonics and the equivalent Intel mnemonics for the 80854 PRO LOG CORPORATION A FORM NO 101905 101905 INSTRUCTION TIMING TsEXECUTION TIMES NUMBER OF INSTRUCTION WOROS INSTRUCTION CATEGORY 1 1 LAR Load Register with Register 41 195 128 Pa ew Used Register immecat pe pen 22 1 1 CTR Count Register increment or Decrement 4 1 95 1 28 4 3 2548 Register A Accumuiator Store Load Direct 13 834 416 4 23 Toad Memory wit Register en 2 28 Fx LE Regem Memory pen 228 7 ue rises meno maan 1 28 Papa Leta coun temo EXECHECHNEPE 1 ft Arithmetic or Logical trom Register 4 195 122 30 or tom Menon 11 364 28 few 272 EME E Unconditional Jump 10 488 320 7 342 224 on rsg sumoa Unconditional Subrautine Jump 18 878 5 76 B Js Jump to Subroutine 9 439 288 E fie 570 Unconditional Subroutine Return 10 as 320 Suorouuna oum e 35 E On Fiag Condom meme s au 1 9 3291 Papa Jose
65. vice types typically used to implement 1 0 ports 7900 Series 1 0 modules are similar to this example 16 90 This figure illustrates the Bus interface and 0 port address decoding cireui 0 Pro Log s 7500 7600 an i LATCHED GLITCH FREE USER OUTPUTS GATED USER INPUTS O SECTION 7 PROGRAM AND HARDWARE DEBUGGING Cw EDAD ECKE CLE C ECC LC c Ca Microprocessor Logic State Analysis An attempt at monitoring the execution of a microprocessor program in real time using a conventional multitrace oscilloscope will be found to be impossible for practical purposes The capacity of the scope and the operator will be quickly exhausted by the magnitude of the problem because of the following characteristics a P d d addr Data is transferred as byte parallel information the address bus is 2 bytes wide Individual bits on these busses have little meaning in program debugging It is neces sary to see the full content of both busses at once and a hexadecimal display of numeric values is much more meaningful than binary waveforms b Display Trigger Qualification As many as 20 signals combined address and control signals may be used simultaneously to qualify the enabling of a peripheral memory card for example n order to capture this event the test instrumentation must also be trigger qualified by the same group of signals Conventional oscilloscopes lack the number of trig
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