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SIS3301 65/100 MHz VME FADCs User Manual

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1. SIS Documentation SIS3300 3301 SIS GmbH 65 100 MHz FADCs VME 0x0020002C 4 R W Max No of Events register ADC1 ADC2 0x00201000 0x1000 BLT32 R Event directory bank 1 ADC1 ADC2 0x00202000 0x1000 BLT32 R Event directory bank 2 ADC1 ADC2 Event information ADC group 2 0x00280000 4 R W Event configuration register ADC3 ADC4 0x00280004 4 R W Trigger Threshold register ADC3 ADC4 0x00280008 4 R Bank address counter ADC3 ADC4 0x0028000C 4 2 R Bank address counter ADC3 ADC4 0x00280010 4 R Bank1 Event counter ADC3 ADC4 0x00280014 4 R Bank Event counter ADC3 ADC4 0x00280018 4 R Actual Sample Value ADC3 ADC3 0x0028001C 4 R W Trigger Flag Clear Counter register ADC3 ADC4 0x00280020 4 R W Compress Event Readout configuration ADC3 ADC4 0x00280028 4 R W Trigger setup register ADC3 ADC4 0x0028002C 4 R W Max No of Events register ADC3 ADC4 0x00281000 0x1000 BLT32 R Event directory bank ADC3 ADC4 0x00282000 0x1000 BLT32 R Event directory bank 2 ADC3 ADC4 Event information ADC group 3 0x00300000 4 R W Event configuration register ADC5 ADC6 0x00300004 4 R W Trigger Threshold register ADCS ADC6 0x00300008 4 R Bank1 address counter ADC5 ADC6 0x0030000C 4 2 R Bank address counter ADC5 ADC6 0x00300010 4 R Bank Event counter ADC5 ADC6 0x00300014 4 R Bank Ev
2. a Jumper Function Factory default 1 5 1 unused open AS 2 enable watchdog closed 2 3 unused open 00 4 unused open ago 5 unused open DD 6 Connect module reset to VME_Sysreset closed DD 7 unused open H E 8 unused open The enable watchdog jumper has to be removed during the initial JTAG firmware load Page 64 of 73 SIS Documentation SIS3300 3301 SIS GmbH 65 100 MHz FADCs VME 10 3 Offset adjustment The pedestal or offset of the ADC channels can be adjusted with the potentiometers RP10A through RP80A see table below The sensitivity for the positive or negative offset can be reduced by two limit jumpers 2 mm the full range is available with both jumpers open Do not install both jumpers for a channel in parallel channel limit pos offset limit neg offset Offset Potentiometer 1 JP78 JP79 RP80A 2 JP76 JP77 RP70A 3 JP58 JP59 RP60A 4 JP56 JP57 RP50A 5 JP38 JP39 RP40A 6 JP36 JP37 RP30A 7 JP18 JP19 RP20A 8 JP16 JP17 RP1OA The position of the two jumpers JP78 and JP79 close to potentiometer RP80A for ADC channel 1 is illustrated in the portion of the board shown below The displayed area is the vicinity of the channel 1 LEMO input connector CON80 Page 65 of 73 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME 10 4 JTAG The SIS3300 on board logic can l
3. define SIS3301_EVENT_READOUT_CONFIG_ALL_ ADC 0x100020 write only D32 define SIS3301_EVENT_READOUT_CONFIG_ADC12 0x200020 read write D32 define SIS3301_EVENT_READOUT_CONFIG_ADC34 0x280020 read write D32 define SIS3301_EVENT_READOUT_CONFIG_ADC56 0x300020 read write D32 define SIS3301_EVENT_READOUT_CONFIG_ADC78 0x380020 read write D32 This register is implemented for each channel group Bit Function Default 31 Unused read 0 0 20 Unused read 0 0 19 Reserved 18 Event Readout compress factor bit 2 17 Event Readout compress factor bit 1 16 Event Readout compress factor bit O 0 15 Event Readout length bit 15 MSB 0 0 Event Readout length bit 0 LSB 0 The power up default value reads Ox 00000000 Event Readout compress factor compress compress compress factor Sum over samples Shift right factor factor bit 2 factor bit 1 bit 0 0 0 0 1 no sum 0 no shift 14 bit result 0 0 1 2 0 no shift 15 bit result 0 1 0 4 0 no shift 16 bit result 0 1 1 8 1 16 bit result 1 0 0 16 2 16 bit result 1 0 1 32 3 16 bit result 1 1 0 64 4 16 bit result 1 1 1 64 4 16 bit result Overflow Underflow If one sample of the samples of the sum has an overflow or an underflow condition the sum will be set to Oxffff or 0x0
4. Dual Channel Group 3 Channels 5 and 6 Dual Channel Group 2 Channels 3 and 4 Dual Channel Group 1 Channels 1 and 2 Page 8 of 73 SIS Documentation SIS3300 3301 SIS GmbH i 65 100 MHz FADCs VME 2 2 1 Dual channel group Two ADC channels form a group which memory is handled by one Field Programmable Gate Array FPGA 12 14 E Input Data Memory ADC 2 Stage 2 S E Aaress Bank 2 FPGA 17 12 14 32 Input ADC 1 Event Data Memory Stage 1 Directory age Bank 1 17 2 3 Modes of Operation The SIS3300 was developed with maximum flexibility in mind The FPGA based design of the card allows to meet the requirements of many readout applications with dedicated firmware designs in the future The initial firmware is supposed to furnish you with an easy to use yet powerful high speed high resolution Flash Analog to Digital Converter FADC implementation that covers many everyday analog to digital applications 2 4 Memory management The individual memory bank s can be used either as one contiguous memory or as a subdivided multi event memory In addition memory depth can be limited in single event operation to match the requirements of the given application The memory configuration is defined through the memory configuration register
5. define SIS3300_BANK1_EVENT_CNT_ADC12 0x200010 read only D32 define SIS3300_BANK1_EVENT_CNT_ADC34 0x280010 read only D32 define SIS3300_BANK1_EVENT_CNT_ADC56 0x300010 read only D32 define SIS3300_BANK1_EVENT_CNT_ADC78 0x380010 read only D32 This read only registers hold the current bank 1 event counter for ADC groups 1 2 3 4 The counter is 12 bit wide The counter will change while the ADC is sampling as events are coming in The returned value is the current event number The register is implemented on the channel group base but the information is redundant and in the standard readout case you will want to retrieve the information from one channel group only Bit 31 16 15 0 Function unused read back as O event counter The event counter is not in a defined state after power up or Key Reset 4 31 Bank 2 event counter 0x200014 0x280014 0x300014 0x380014 define SIS3300_BANK2_EVENT_CNT_ADC12 0x200014 read only D32 define SIS3300_BANK2_EVENT_CNT_ADC34 0x280014 read only D32 define SIS3300_BANK2_EVENT_CNT_ADC56 0x300014 read only D32 define SIS3300_BANK2_EVENT_CNT_ADC78 0x380014 read only D32 Same as bank 1 event counter but for bank 2 of ADC groups 1 4 Page 45 of 73 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME 4 32 Actual Sample registers 0
6. 15 unused read 0 14 Event_CONF Bit 14 reserved function 13 Event_CONF Bit 13 reserved function 12 1 former enable trigger event directory 11 EXTERNAL CLOCK RANDOM MODE 10 Event_CONF Bit 10 reserved function 9 Channel Group ID Bit 1 Channel Group ID Bit 0 Event_CONF Bit 7 reserved function Event_CONF Bit 6 reserved function Event_CONF Bit 5 reserved function ENABLE_GATE_CHAINING_MODE wl amp Nn a oo Enable Wrap around mode no address auto stop 0 Autostop at end of page 1 Wrap around page until STOP External or KEY Page size Bit 2 Page size Bit 1 O w Page size Bit 0 Page 30 of 73 SIS Documentation SIS3300 3301 SIS GmbH 65 100 MHz FADCs VME The power up default values of the registers are SIS3300_EVENT_CONFIG_ADC12 0x00001000 SIS3300_EVENT_CONFIG_ADC34 0x00001100 SIS3300_EVENT_CONFIG_ADC56 0x00001200 SIS3300_EVENT_CONFIG_ADC78 0x00001300 i e the two channel group ID bits identify the four channel groups 4 18 1 Gate chaining mode Gate chaining mode was implemented to allow for effective acquisition of small events of arbitrary length Sampling in gate chaining mode will stop when e Maximum number of events see 4 22 1 is reached e End of bank is reached the last event gate may be incomplete in this case The first data
7. c eeeseeeeeeeeee 7 A Eegen SE 11 33 UMS cui ica 66 TAS BETS annn aani 33 41 42 43 O E 39 A devious ies socks ei EEEO 38 POS biie deer Zu 11 Picnic as idad 11 frisser controladas sins 11 Page 72 of 73 SIS Documentation SIS3300 3301 trigger event directory ooooococnnooccccnnoncnonnnnncnnnnnnos 41 trig Ser FR 37 trigger generaton 11 MUNG AS soo e eege ted Ba eaten od ee 20 Universiada 20 user siaN BAS A 18 62 LR A D GE 18 GUDDE Ae EET T 18 62 O 47 E e Dub catre darian atrae acidos 62 enablers irana geet dE gees 18 user output Clan lalc e dial siai s 17 SIS GmbH 65 100 MHz FADCs VME VCC oo ces ooh eect ANE ha ae et E cue OR AR ceca ook de 66 VM P cta ala cas 12 68 COMME ivan rolas 69 IU ia 11 readout speed A era 12 KK EE 64 VME addressing cooocccooncconccconcninncnononccnonacionacnnne 13 VME TE 7 13 68 70 Ka 70 MS Barcia tetitas 7 69 width external start stop oooooccnnnoocccononancnonananinnnananos 62 WIAD EE 34 AA REO 41 42 Page 73 of 73
8. Note The user can generate a gate of defined length in clock ticks by fanning a short pulse to the start and stop input with start stop mode active stop delay enabled and the stop delay register programmed to the desired gate width Pipelining will have to be taken into account Le the digitised signal is about 40 ns with the module sampling at 100 MHz ahead of the respective control signal a fact that can be used in external trigger decisions For longer external trigger decisions one can consider to pipeline the ADC data in the FPGA in future firmware revisions before storing them to memory 4 8 Time stamp predivider register 0x1C define SIS3300_TIMESTAMP_PREDIVIDER 0x1C read write D32 The read write time stamp predivider register is used to define a prescale factor for the frequency of the time stamp counter The time stamp counter counts at the clock rate with the time stamp predivider value of O and 1 a prescale factor of 2 65535 is selected by writing the corresponding value to the register Bit 31 unused read as O 16 unused read as 0 15 Time stamp predivider BIT15 0 Time stamp predivider BITO The power up default value is 0 Note A predivider value of 0 can not be used with firmware V201 Page 26 of 73 SIS Documentation SIS3300 3301 SIS GmbH 65 100 MHz FADCs VME 4 9 Key address general reset 0x20 write define SIS3300_KEY
9. Event Readout length Event Readout Number of 32 bit words Number of compressed 16 bit Length words 0 1 2 1 2 4 2 3 6 65535 65536 2x65536 128k samples Page 55 of 73 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME 6 2 Compress Event Readout Fifo 0x180000 0x18fffc define SIS3301_EVENT_READOUT_FIFO 0x180000 read D32 BLT32 MBL64 2eVME size 0x10000 Data format D31 16 D15 0 second sum first sum 6 3 Example set compress factor and auto readout length data i_compress_factor lt lt 16 readout_length_lwords 1 addr base_addr S1IS3301_EVENT_READOUT_CONFIG_ALL_ADC vme_A32D32_ write amp sisl100_devicel addr data Start FSM Readout data 0x80000000 reset input Fifo 0x0 lt lt 20 bank 0x0 lt lt 17 ADC select memory_start_index Oxlffff memory address addr base_addr SIS3301_EVENT_READOUT_START_CMD vme_A32D32_write sis1100_device addr data special readout addr base_addr SIS3301_EVENT_READOUT_FIFO return_code vme_A32MBLT64_read sis1100_device addr rblt_data readout_length_lwords amp get_lwords Data in ADC Memory with normal readout address 0x0 0x4 0x8 0xC 33400000 1000200 1010201 1020202 1030203 33400010 1040204 1050205 1060206 1070207 33400020 1080208 1090209 10a020a
10. 11 3 2 Hot swap live insertion Please note that the VME standard does not support hot swap by default The SIS3300 is configured for hot swap in conjunction with a VME64x backplane In non VME64x backplane environments the crate has to be powered down for module insertion and removal Page 68 of 73 SIS Documentation SIS3300 3301 SIS GmbH i 65 100 MHz FADCs VME 11 4 Connector types The VME connectors and the two different types of front panel connectors used on the SIS3300 are Connector Purpose Part Number 160 pin zabcd VME P1 P2 Harting 02 01 160 2101 LEMO PCB Coax control connector LEMO EPB 00 250 NTN 90 PCB LEMO Analog input connector LEMO EPL 00 250 NTN 90 PCB LEMO Analog input connector LEMO EPG 00 302 NLN 3301 differential input version 11 5 P2 row A C pin assignments The P2 connector of the SIS3300 has several connections on rows A and C for the F1002 compatible use at the DESY H1 FNC subdetector This implies that the module can not be operated in a VME slot with a special A C backplane like VSB e g The pin assignments of P2 rows A C of the SIS3300 is shown below P2A Function P2C Function 1 5 2 V 1 5 2 V 2 5 2 V 2 5 2 V 3 5 2 V 3 5 2 V 4 not connected 4 not connected 5 not connected 5 not connected 6 DGND 6 DGND 7 P2 CLOCK_H 7 P2_CLOCK_L 8 DGND 8 DGND 9 P2 START H 9 Pi
11. 7 2 Arm for sampling e define in Acquistion register Enable Sample Clock for Memory Bank or Bank 7 3 Start Sampling e in Single Event mode Issue key Start or External Start e in Multi Event mode with Autostart disabled Issue key Start or External Start for each Event e in Multi Event mode with Autostart enabled Issue key Start or External Start for the first Event only Note activation of auto bank switch mode with multi event mode enabled will start sampling automatically Page 58 of 73 SIS Documentation SIS3300 3301 SIS GmbH 65 100 MHz FADCs VME 7 4 Stop Sampling Event e in Single Event mode with Autostop enabled sampling stops automatically at the end address of the page e in Single Event mode with Autostop is disabled Wrap around mode Issue key Stop or External Stop e in Multi Event mode with Autostop is enabled sampling stops automatically at the end address of each page e in Multi Event mode with Autostop is disabled Wrap around mode Issue key Stop or External Stop for each Event 7 5 End of Sampling clear arm disable Sample Clock e in single event mode the Sample Clock Enable bit of the sampling bank is cleared by the logic at the end of sampling one event e in multi event mode the Sample Clock Enable bit of the sampling bank is cleared by the logic at the end of sampling last event The user software can poll on the status of the sample
12. 3 VME Addressing As the SIS3300 VME FADC features memory options with up to 2 banks of 4 times 128 K samples each A32 addressing was implemented as the only option Hence the module occupies an address space of OXFFFFFF Bytes i e 16 MBytes are used by the module The SIS3300 1 firmware addressing concept is a pragmatic approach to combine standard rotary switch style settings with the use of VME64x backplane geographical addressing functionality The base address is defined by the selected addressing mode which is defined by jumper array J1 and possibly SW1 and SW2 in non geographical mode Function EN_A32 EN_GEO EN_VIPA reserved Ir The table below summarises the possible base address settings J1 Setting Bits A32 GEO VIPA 31 30 29 28 27 26 25 24 x SWl SW2 tloa lalalo x D ojoj oli lt lt lt lt O O V O O x Not implemented in this design Shorthand Explanation Sw1 Sw2 Setting of rotary switch SW1 or SW2 respective GAO GA4 Geographical address bit as defined by the VME64x P backplane Notes e This concept allows the use of the SIS3300 1 in standard VME as well as in VME64x environments i e the user does not need to use a VME64x backplane e The factory default setting is EN_A32 closed SW1 3 SW2 0 i e the module will react to
13. 4 Clock In RN140A 3 Start RN140B 2 Stop RN140C 1 User in RN140D 9 2 Analog inputs 9 2 1 Single ended LEMO version The analog inputs of the single ended version are terminated with 50 Q The input range of the initial series is 5V it is shifted with the offset adjustment potentiometer to match the required user input voltage range of 0 5V or 2 5 V 2 5V 9 2 2 Differential version The differential input version will be based on another printed circuit design input termination and availbale input ranges are yet to be defined Page 62 of 73 SIS Documentation SIS3300 3301 SIS GmbH I 65 100 MHz FADCs VME 9 3 LED s The SIS3300 has 8 front panel LEDs to visualise part of the modules status The user and access LED are a good way to check first time communication addressing with the module Color Designator Function Red A Access to SIS3300 VME slave port Yellow P Power Green R Ready on board logic configured Green U User to be set cleared under program control Red SAM Sampling Yellow SRT Start lit with start input or leading edge in gate mode Green STP Stop lit with stop input or trailing edge in gate mode Green TRG Trigger lit if one or more channels are above threshold The on duration of the access sampling start stop and trigger LEDs is stretched to guarantee visibility even under low rate conditions 9 4 PCB LEDs The 8 surfac
14. At this point the flag BI FULL will be set and acquisition changes over to bank 2 if the flag B2_FULL is not set The user can read out data from bank 1 in parallel to ongoing acquisition into bank 2 and clear the B1_FULL flag after the readout was completed As soon as memory bank 2 is filled acquisition will be handed over to bank 1 again if B1_FULL has been cleared already The active memory bank will acquire data until the bank is filled if a KEY SIOP AUTO BANK SWITCH is issued Page 67 of 73 SIS Documentation SIS3300 5153301 SIS GmbH 65 100 MHz FADC VME 11 2 consumption The SIS3300 1 is a single supply design to facilitate operation in any VME environment Le the module does not require special backplanes or non standard VME voltages The power consumption of a two memory bank module digitizing at 100 MHz was measured to be Voltage Current 5V lt 6A 12 V lt 40 mA 12V lt 60 mA P lt 32W 11 3 Operating conditions 11 3 1 Cooling Although the SIS3300 1 is mainly a 2 5 and 3 3 V low power design substantial power is consumed by the Analog to Digital converter chips and linear regulators Hence forced air flow is required for the operation of the board The board may be operated in a non condensing environment at an ambient temperature between 10 and 40 Celsius A power up warm up time of some 10 minutes is recommended to ensure equilibrium on board temperature conditions
15. D31 D30 D29 D28 D27 D26 D25 D24 o D18 D17 o D23 20 19 End Address 1 of Event 0 vd vd N LA a a vd nn bel nN vd bel 00 0x0 End Address 1 of Event 1023 ee vd S vd UI gt ON vd vd 00 o Oxffc T1 T2 W wrap around bit T1 T8 trigger information ADC 1 ADC 8 1 ADC channel has met trigger criterion for this event 0 ADC channel has not triggered for this event 4 25 Trigger event directory bank 2 0x102000 0x102ffc define SIS3300_EVENT_DIRECTORY_BANK2_ ALL ADC 0x102000 read only D32 BLT32 size 0x1000 Same as above but for bank 2 Page 41 of 73 SIS Documentation SIS3300 5153301 SIS GmbH 65 100 MHz FADC VME 4 26 Event directories bank 1 0x201000 0x201ffc 0x281000 0x281ffc 0x301000 0x301ffc 0x381000 0x381ffc define SIS3300_EVENT_DIRECTORY_BANK1_ADC12 0x201000 define SIS3300_EVENT_DIRECTORY_BANK1_ADC34 0x281000 define SIS3300_EVENT_DIRECTORY_BANK1_ADC56 0x301000 define SIS3300_EVENT_DIRECTORY_BANK1_ADC78 0x381000 read only D32 BLT32 size 0x1000 These arrays are redundant and not used in standard operation use the trigger event directory instead The event directories hold the stop pointer s 1 e end address 1 of each channel group of memory ba
16. FIR filter output data can be stored to memory with FIR test mode enabled The output data of one ADC of the dual channel group are stored to the memory of the other ADC while the ADC raw data are stored to the channels own memory portion FIR test mode is enabled by setting bit 21 of the trigger setup register for the corresponding dual channel group With bit 20 set also test even ADC FIR data of ADC2 are stored to ADC1 memory with bit 20 cleared ADC1 FIR data are stored to ADC2 memory Page 37 of 73 SIS Documentation SIS3300 5153301 SIS GmbH 65 100 MHz FADC VME 4 22 1 3 Trigger generation Trigger generation is implemented in the dual channel group FPGAs The number of required bits for the sum depends on the peaking time The running sum is build with the full accuracy before the result is stored to a 16 bit wide ring buffer P Peaking time number of values to sum G Gap time distance in clock ticks of the two running sums A setting for P 0 and 1 is not valid and will be superseded with 2 automatically 12 bit units SIS3300 if P 2to7 16 bit signless add sub 16 bit to ring buffer 15 0 ifP 8to 15 17 bit signless add sub 16 bit to ring buffer 16 1 shift right by 1 if P 16to 31 18 bit signless add sub 16 bit to ring buffer 17 2 shift right by 2 if P 32 to 63 19 bit signless add sub 16 bit to ring buffer 18 3 shift right by 3 if P 64 to 127 20 bit signless add sub 16 bit to ri
17. KA Page 71 of 73 SIS Documentation SIS3300 5153301 clear bank full flag oonnoonnccnnnnccnonccionncnnnns 28 clear bank full flag oeer 28 general reset iii Eat start auto bank switch mode 28 stop auto bank switch mode 28 VME start sampling ooooooocnnoocccnononccnnnonncncnnnnns 27 VME stop sampling ooooooccnoocccnnnoncnnnonancnononnns 21 Key address cccooveriociononanionasicconia ica a a 14 LED A 63 ACCESS tds 63 P 63 R 63 SAM aida ss 63 SRT cas ias 63 S EE Eege EE ee 63 TRG aaa 63 U 63 E E E E ES 17 18 63 LEDs front panel 63 E A CO OO sde E dee ee et 48 65 LTIN AD A E E inpetethoees 20 live Inserti oi ee epena iar eea n 68 70 M36 MBU TOA ereere TN 7 12 16 A O 7 9 EIER dE 9 mulp event 9 Memory divisions sprs peisir nikin eirp hees 30 mode auto bank switch oooooooccnnonccnnoconcncnonnncnnnannnoss 67 EE 31 dual bale dorados ira t 9 external random clock 32 FIR testis Ek sde OREA 37 OT 48 E E 31 47 multi event 9 59 eet d e 24 35 A eege deed e deeg 36 random external clock 24 62 67 GER E 59 Statt StOP EE 11 48 WIP SS 34 module dest en 8 multi event MEAN ii ini 9 N 36 AS 65 Operating Copndhttons eee eeeeeeseeceereeeereeeeneees 68 Operation siini ieser steiere 48 51 58 operation mode 9 output bank UE 62 liar isis 62 NS 11 17 62 US in diciones hd 62 P 36 DEE 70 SIS GmbH y 65 100 MHz FADC VME Pr lol is 7 70 PIN ASSIgOIMENtS cccooccconncconnnonnnncnoncc
18. SIS3301 65 SIS3301 105 100 MHz X X 50 MHz X X X 25 MHz X X X 12 5 MHz X 6 25 MHz X 3 125 MHz X 2 5 2 External clock A symmetric external clock NIM level ratio between 45 55 and 55 45 can be fed to the module through a LEMOOO connector For optimum performance the clock frequency should be within the specified range for the given ADC chip Module Min sym clock Max sym clock SIS3300 1 MHz 105 MHz SIS3301 65 15 MHz 65 MHz SIS3301 105 15 MHz 105 MHz 2 5 3 Random External Clock Random external clock mode allows to operate the SIS3300 1 with basically arbitrary external clock pulse trains or slow external clocks The module is clocked with the internal clock typically at 100 MHz and a data word will be stored to memory upon the next leading edge of the internal clock after a leading edge on the external clock input is detected Internal pipelining has to be taken into account the datum will precede the clock by 10 clock ticks 1 e about 100 ns on a SIS3300 clocking at 100 MHz Page 10 of 73 SIS Documentation SIS3300 3301 SIS GmbH 65 100 MHz FADCs VME 2 6 Trigger control pre post start stop and gate mode The SIS3300 1 features pre post trigger capability as well as start stop mode acquisition and a gate mode in which start and stop are derived from the leading and trailing edge of a single control input signal The trigger behaviour is defined
19. while bank handling on dual memory bank modules is under control of the acquisition control register 2 4 1 Single Event Mode The full memory of 128 K Samples of the SIS3300 1 is used as one big circular buffer or as single shot memory in single event mode unless memory size is limited by the event configuration register 2 4 2 Multi Event Mode The memory can be divided in up to 1024 pages or events to make the acquisition of shorter signals more efficient The stop pointers for the individual page can be retrieved from the event directory In auto start mode the ADC advances to the next page and starts sampling automatically 2 4 3 Dual Bank Mode Dual bank mode Bank Switch mode is available on cards except SIS3300 V1 PCBs The single multi event selection will influence both memory banks in the same fashion Data from the inactive bank can be readout while the other bank is acquiring new data Page 9 of 73 SIS3300 5153301 SIS Documentation SIS GmbH 65 100 MHz FADC VME 2 5 Clock sources The SIS3300 3301 features 3 basic clock modes e Internal clock e External symmetric clock e External random clock 2 5 1 Internal clock The internal clock is generated from an on board 50 MHz quartz It is either doubled by a delay locked loop to 100 MHz or divided down to lower clock frequencies The table below lists the valid clock settings for the different SIS3300 3301 boards Clock SIS3300
20. 11 Status Control 11 10 set bank full pulse to output 3 Status Bank full pulse on LEMO output 3 9 set bank full pulse to output 2 Status Bank full pulse on LEMO output 2 8 set bank full pulse to output 1 Status Bank full pulse on LEMO output 1 highest priority 7 Set reserved 7 Status Control 7 6 Enable internal trigger routing Status trigger routing 1 to input 0 don t route 5 Activate trigger upon armed and started Status trigger generation 1 armed and started O armed 4 Invert trigger output Status trigger output inversion 1 inverted O straight Page 17 of 73 SIS Documentation SIS3300 5153301 SIS GmbH 65 100 MHz FADC VME 3 Set Reset Delay Locked Loop DLL for Status Reset delay locked loop for external external clock clock SIS3301 11 16 only 2 Enable trigger output disable user output Status of user trigger output 1 trigger output O user output 1 Set user output if bit 2 is not set Status User Output 1 output on O output off 0 Switch on user LED Status User LED 1 LED on 0 LED off denotes power up default setting 4 1 1 Trigger activation Trigger generation can be activated for two states of the SIS3300 1 By default trigger generation is active as soon as the module is armed i e a sample clock is active In this mode the trigger can be used to start the digitizer with stop condition end of event e g Trigger generation upon armed and started 1 e b
21. 2 memory 0x600000 ONT 47 5 Description of Start Stop and Gate operation mod 48 5 1 Start st p Modernitas naaa 48 5 1 1 Front panel statt StOPre ias 48 9 2 Gate rr EE 48 5 3 Start logic SUMMALY E 49 54 Stop logic summary ciencia cities 50 6 Special Compress Event Readout Leet eaten dE ee teg 5I 6 1 Compress Event Readout register dscrption 53 6 1 1 Start Compress Event Readout register 0x50 read write oooooooonnnncccnnnooccocooonccononnncos 53 6 1 2 Stop Abort Compress Event Readout register 0x54 write 53 6 1 3 Compress Event Readout Status register 0x54 read 54 6 1 4 Compress Event Readout configuration register 0x100020 0x200020 0x280020 0x300020 le LEE 55 6 2 Compress Event Readout Fifo 0x180000 Ox 18 fC oooooconooccnnnoocccccnonccccononcnnnnonnnnononnnnnconannnnnono 56 E SN EE 56 T Operation TEE 58 7 1 CONSUL oa to Sah tie 58 KS Ne Ee Or 58 7 3 Start Sample A O N a 58 TA stop Sampling Event ii A 59 7 5 End of Sampling clear arm disable Sample Clock eee eeseeesecsseeceseeeeseeeeeaeecsaeessaeesseeesseeeesaes 59 Bo Board BET E EE 60 tegt Deele EE EE Ee 61 9 1 Control M OUtpUtS ue EEGENEN NEESS 62 9 1 1 User e 62 9 1 2 Control input termination sisisi ao oa AEAEE EENE EE E 62 925 Analog puts A ana 62 9 2 1 Single ended LEMO version 1 cc ccesccsessoeesonesecseossceveseesnnetonosescnpesenevobsensnsenesonessbscenssensers 62 9 2 2 Differential version EE 62 D
22. EEN 10 23 CONTO Stat nian iia 66 configurations talados 64 connector iia aia it 7 connector DES 2 eeeekegdeete conociendo 69 control Puta nina tias 11 GUU iii aii slecis ies 62 Orange load 62 MIO 40 seid ee el ah eee 62 CO SE 68 Crosstalle ee ee ie E E H RSR H data ee EE 47 delay locked Loop 18 DES e e ade edad 69 differential riore RN 62 DOB aeret Set a a Seef 20 edge ledidi Sis a il edi 11 AMIS aiii its io eaa Eat 11 A GE 9 Ae A e EEN 45 event directory A 30 42 43 44 Event SIZE elei E T E EREA 30 external clock n ira da 18 PADECE Sd ha a ee Ca acne Rocks 9 BIB OS nee ce ik See heh eh een 38 FIR cage tas 37 FTN E 6 66 FING ee och task ins eB pte cee E 69 FOTIA GS iis ses He at tha dees ae dee UR a Bee 47 Ee dd io 9 COMO is 63 front panel sia oat EE 7 61 GA A T a R 13 Be 37 38 gate chaining ironin n aie conos 31 Pate Uleies ee ee 11 geographical addressing oooocccnocccnocccnonccnonncnnne 70 GIN EE 66 A Bee eee eee 19 TA Dee tates e ee ebe 69 hot SWAP ET 68 70 input ANALOG s isssedsisssstessasousgsiascetaslascwadsids E TEGS 62 CONEON O a A R E E 62 Ue 62 A tee disse ge DEELEN Rue 20 interrupt bank ll 59 end of event cate 59 interrupter mode 20 interrupter De 20 use Te 6 IRQ A A 21 d of eyen a EE 21 E EE 21 TRO 0d iia aaa 20 ROAK cua acacia 20 RORAS cuca aaa das 20 d a ae eee 23 J113 64 REN 64 LA a e ae e a 6 64 66 JUMPED nea ea cds 64 A ene Re ER RAS 65 TESOL Soi Be ee ce 64
23. START L 10 P2_STOP_H 10 P2_STOP_L 11 P2_TEST_H 11 P2_TEST_L 12 DGND 12 DGND 13 DGND 13 DGND 14 DGND 14 DGND 15 DGND 15 DGND 16 not connected 16 not connected E Ke 17 Es 31 not connected 18 not connected Page 69 of 73 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME 11 6 Row d and z Pin Assignments The SIS3300 is prepared for the use with VME64x and VME64xP backplanes Foreseen features include geographical addressing PCB revisions V2 and higher and live insertion hot swap The prepared pins on the d and z rows of the P1 and P2 connectors are listed below Position P1 J1 P2 J2 Row z Row d Row z Row d 1 VPC 1 2 GND GND 1 GND 3 4 GND GND 5 6 GND GND 7 8 GND GND 9 GAP 10 GND GAO GND 11 RESP GAI1 12 GND GND 13 GA2 14 GND GND 15 GA3 16 GND GND 17 GA4 18 GND GND 19 20 GND GND 21 22 GND GND 23 24 GND GND 25 26 GND GND 27 28 GND GND 29 30 GND GND 31 GND 1 GND 1 32 GND VPC 1 GND VPC 1 Note Pins designated with 1 are so called MFBL mate first break last pins on the installed 160 pin connectors VPC 1 pins are
24. by the acquisition control register 2 7 Internal Trigger generation The trigger output of the SIS3300 1 can be either used to interact with external trigger logic or to base start stop on a threshold i e one individual threshold per ADC channel of the digitized data Trigger generation can be activated with two conditions e module armed i e sample clock active trigger can be used to start acquisition e module armed and started trigger can be used to stop acquisition The user can select between triggering on the conditions above and below threshold 2 8 Time Stamp Memory A 1024 x 24 bit Time Stamp Memory is implemented for each memory bank An internal counter starts with the first Stop trigger condition in multievent mode and it will be incremented with the sample clock or with the predivided sample clock factor 1 to 256 Each stop trigger condition end of event writes the counter value into Time Stamp Memory 2 9 VME Interrupts Two registers the Interrupt configuration and the Interrupt control register are implemented for interrupt setup and control Four Interrupt sources are implemented External User Input LEMO input 1 End of event End of last event in multievent mode Memory bank full in bank switch mode Dual bank Page 11 of 73 SIS Documentation SIS3300 5153301 SIS GmbH 65 100 MHz FADC VME 2 10 VME Readout Speed The VME interface is optimized for readout speed An internal FIFO
25. 0x300004 read write D32 define SIS3300_TRIGGER_THRESHOLD_ADC78 0x380004 read write D32 These read write registers hold the threshold values for the ADC channels 1 3 5 7 and 2 4 6 8 Bit 31 16 15 0 Function threshold value threshold value ADC 1 3 5 7 ADC 2 4 6 7 default after Reset OxOfffOfff disable Trigger Page 33 of 73 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME 4 20 Trigger Flag Clear Counter register 0x10001C 0x20001C 0x28001C 0x3001C 0x38001C define SIS3300_TRIGGER_FLAG_CLR_CNT_ALL_ADC 0x10001C write only D32 define SIS3300_TRIGGER_FLAG_CLR_CNT_ADC12 0x20001C read write D32 define SIS3300_TRIGGER_FLAG_CLR_CNT_ADC34 0x28001C read write D32 define SIS3300_TRIGGER_FLAG_CLR_CNT_ADC56 0x30001C read write D32 define SIS3300_TRIGGER_FLAG_CLR_CNT_ADC78 0x38001C read write D32 This register is implemented on the base of the channel group Use the address 5153300_TRIGGER_FLAG_CLR_CNT_ALL_ADC to write to the registers of all channel groups simultaneously The Trigger Flag bit is set as soon as an ADC channel meets the trigger criterion This flag remains latched until the next event start i e it will not be cleared as new ADC data which do not meet the trigger criterion come in with Wrap mode active The Trigger Flag Clear Counter register allows you to define a nu
26. 10b020b 33400030 10c020c 10d020d 10e020e 10f020 33400040 1100210 1110211 1120212 1130213 33400050 1140214 1150215 1160216 1170217 33400060 1180218 1190219 11a02la 11b021b 33400070 11c021c 11d021d 11e021le 11 021f 33400080 1200220 1210221 1220222 1230223 33400090 1240224 1250225 1260226 1270227 334000a0 1280228 1290229 12a022a 12b022b 334000b0 12c022c 12d022d 12e022e 12 022 334000c0 1300230 1310231 1320232 1330233 334000d0 1340234 1350235 1360236 1370237 334000e0 1380238 1390239 13a023a 13b023b 334000f0 13c023c 13d023d 13e023e 13 023f Page 56 of 73 SIS Documentation SIS3300 3301 65 100 MHz FADCs SIS GmbH VME Data with Compress Event readout Start Address 0x0 Compress Factor 0x0 Event Readout Length Oxff address 0x0 0x4 0x8 33180000 1010100 1030102 1050104 33180010 1090108 10b010a 10d010c 33180020 1110110 1130112 1150114 33180030 1190118 11b0lla 11d011c 33180040 1210120 1230122 1250124 33180050 1290128 12b012a 1240120 33180060 1310130 1330132 1350134 33180070 1390138 13b013a 13d013c 33180080 1410140 1430142 1450144 33180090 1490148 14b014a 14d014c 331800a0 1510150 1530152 1550154 331800b0 1590158 15b015a 15d015c 331800c0 1610160 1630162 1650164 331800d0 1690168 16b016a 1640160 331800e0 1710170 1730172 1750174 331800f0 1790178 17b017a 1740170 Data with Compress Event readout Start Address 0x0 Compress Factor 0x1 Event Readout Length 0x0f
27. 29 of 73 SIS Documentation SIS3300 5153301 SIS GmbH 65 100 MHz FADC VME 4 18 Event configuration registers 0x100000 0x200000 0x280000 0x300000 0x380000 define SIS3300_EVENT_CONFIG_ALL_ADC 0x100000 write only D32 define SIS3300_EVENT_CONFIG_ADC12 0x200000 read write D32 define SIS3300_EVENT_CONFIG_ADC34 0x280000 read write D32 define SIS3300_EVENT_CONFIG_ADC56 0x300000 read write D32 define SIS3300_EVENT_CONFIG_ADC78 0x380000 read write D32 This register is implemented for each channel group and it has to be written with the same value the best way is to make use of the address S1S3300_EVENT_CONFIG_ALL_ADC to write to the registers of all channel groups simultaneously The number of memory divisions events is defined by this register in multi event mode The lowest three bits define the number of memory divisions as listed in the table below On dual bank units both memory banks will be affected by the configuration of the event configuration register The maximum number of events is defined by the size of the event directory which has 256 entries The maximum number of events is limited to 65535 in gate chaining mode to allow for shorter gates also Bit function 31 unused read 0 20 unused read 0 19 Event_CONF Bit 19 reserved function 18 Average Bit 2 17 Average Bit 1 16 Average Bit 0
28. 80000 BLT32 MBLT64 2eVME R W Bank memory ADC3 ADC4 0x00500000 0x80000 BLT32 MBLT64 2eVME R W Bank 1 memory ADC5 ADC6 0x00580000 0x80000 BLT32 MBLT64 2eVME R W Bank memory ADC7 ADC8 Bank 2 memory 0x00600000 0x80000 BLT32 MBLT64 2eVME R W Bank 2 memory ADCI ADC2 0x00680000 0x80000 BLT32 MBLT64 2eVME R W Bank 2 memory ADC3 ADC4 0x00700000 0x80000 BLT32 MBLT64 2eVME R W Bank 2 memory ADC5 ADC6 0x00780000 0x80000 BLT32 MBLT64 2eVME R W Bank 2 memory ADC7 ADC8 W in D32 only for memory test e g Note 1 The event information is identical for the four ADC groups unless the module has a hardware problem hence it will be sufficient for normal operation to retrieve the needed information from one group only Note 2 MBLT64 and 2eVME read access is supported from the memory banks only Page 16 of 73 SIS Documentation SIS3300 3301 SIS GmbH 65 100 MHz FADCs VME 4 Register Description The function of the individual registers is described in detail in this section The first line after the subsection header in Courier font like define SIS3300_CONTROL_STATUS 0x0 read write D32 refers to the sis3300 h header file 4 1 Control Status Register 0x write read define SIS3300_CONTROL_STATUS 0x0 read write D32 The control register is in charge of the control of basic properties o
29. A32 addressing under address 0x30000000 e Early SIS3300 boards PCB SIS3300_V1 have a different base address scheme Page 13 of 73 SIS Documentation SIS3300 5153301 SIS GmbH 65 100 MHz FADC VME 3 1 Address Map The SIS3300 resources and their locations are listed in the table below Note Write access to a key address KA with arbitrary data invokes the respective action Offset Size in BLT Access Function Bytes 0x00000000 4 W R Control Status Register J K register 0x00000004 4 R Module Id and Firmware Revision register 0x00000008 4 R W Interrupt configuration register 0x0000000C 4 R W Interrupt control register 0x00000010 4 R W Acquisition control status register J K register 0x00000014 4 R W Extern Start Delay register 0x00000018 4 R W Extern Stop Delay register 0x0000001C 4 R W Time stamp predivider register 0x00000020 4 KAW General Reset 0x00000030 4 KAW VME Start sampling 0x00000034 4 KAW VME Stop sampling 0x00000040 4 KAW Start auto bank switch 0x00000044 4 KAW Stop auto bank switch 0x00000048 4 KAW Clear bank 1 memory full 0x0000004C 4 KAW Clear bank 2 memory full 0x00000050 4 R W Start Compress Event Readout 0x00000054 4 R W Stop Abort Compress Event Read
30. IS3300 1 5 LEMO Start In trailing edge A MUX Internal Trigger LEMO Stop In STOP P2 Reset In a Pee VME Key Stop STOP Autostop Note Condition Register Comment I Bit 8 1 Acquisition Control Enable front panel start stop logic Z Bit 9 1 Acquisition Control Enable P2 start stop logic 3 Bit 7 1 Acquisition Control Stop delay enable 4 Bit 7 0 Acquisition Control No stop delay 5 Bit 10 0 Acquisition Control use start stop mode Bit 10 1 use gate mode 6 Bit 6 1 Control Route trigger Page 50 of 73 SIS Documentation SIS3300 3301 65 100 MHz FADCs SIS GmbH VME 6 Special Compress Event Readout Logic The Compress Event Readout logic enables a vme compressed readout of one ADC Event inside a programmed wrap page ADC7 8 FPGA Compress Logic VME FPGA Data Address Page Logic O 0 ADC Memory Input FIFO 1K x 32 Almost Full 960 Address H Memo Memory anc 8 ADC8 Bank Bank2 Memory Memory ADC7 ADC 7 Bank Bank Memo Memory ADC E ADC2 Bank1 Bank2 Memory Memory ADC 1 ADC 1 Banki Bank2 ADC 1 2 FPGA Compress Logic Address Page Logic Compress Event Readout Statemachine The following regi
31. RESET 0x20 write only D32 A write with arbitrary data to this register key address resets the SIS3300 to it s power up state 4 10 Key address VME start sampling 0x30 write define SIS3300_KEY_START 0x30 write only D32 A write with arbitrary data to this register key address will initiate sampling on the active memory bank if a bank is armed for sampling 4 11 Key address VME stop sampling 0x34 write define SIS3300_KEY_STOP 0x34 write only D32 A write with arbitrary data to this register key address will halt sampling on the active page In Single Event Mode or during the last page the sampling this command will halt the the sampling To Abort a sampling in Multi Event Multibank mode the following cycles have to be executed issue disable autostart issue KEY_STOP_AUTO_BANK_SWITCH issue SIS3300_KEY_STOP issue clear BX ENABLE Page 27 of 73 SIS Documentation SIS3300 5153301 SIS GmbH 65 100 MHz FADC VME 4 12 Key address start Auto Bank Switch mode 0x40 write define SIS3300_KEY_START_AUTO_BANK_SWITCH 0x40 write only D32 A write with arbitrary data to this register key address will start the auto bank switch mode 4 13 Key address stop Auto Bank Switch mode 0x44 write define SIS3300_KEY_STOP_AUTO_BANK_SWITCH 0x44 write only D32 A write with arbitrary data to this register key address will stop th
32. SIS Documentation SIS3300 3301 SIS GmbH t 65 100 MHz FADCs VME SIS3301 65 100 MHz VME FADCs User Manual SIS GmbH Harksheider Str 102A 22399 Hamburg Germany Phone 49 0 40 60 87 305 0 Fax 49 0 40 60 87 305 20 email info struck de http www struck de Version Greta 1 30 as of 02 10 09 Page 1 of 73 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME Revision Table Revision Date Modification 1 00 20 06 02 Generation from V3 00 SIS3300 3301 manual 1 10 17 11 04 Delay locked loop for clock on SIS3301 and 14 bit design firmware version 1 20 20 07 09 Add Compress Event Readout Version 0x33011115 1 21 03 08 09 Compress Event Readout documentation modified 1 22 28 09 09 Trigger Setup registers documentation modified 1 30 02 10 09 ADC clock source add External Clock LEMO In direct mode Control register add Reset External Clock DLL feature Acquisition Control register Page 2 of 73 SIS Documentation SIS3300 3301 SIS GmbH 65 100 MHz FADCs VME Table of contents e KEE 3 TOO CON ei ri A paid 6 1 1 Related sdoCu ments teta clip de de Oe eera a Eege 6 2 Technical Properties EE 7 2 1 Key functionality EE 7 2 2 Module desig eeigeiderebter capta 8 2 2 1 Dual channel groupiero tee eer Eed 9 2 3 Modes ot Operation a inal a EES 9 2 4 Memory management cnini scien EES ENEE a a E A 9 2 4 1 S
33. SIS GmbH 65 100 MHz FADC VME 4 23 MAX No of Events registers Ox 10002C 0x20002C 0x28002C 0x30002C 0x38002C 00 40 4 24 Trigger event directory bank 1 Ox101000 Ox101ffc oooooonocccnonccnonccononccnonccnonccnonacconanonanccnanccnanccinne 41 4 25 Trigger event directory bank 2 0x102000 Ox lU 41 4 26 Event directories bank 1 0x201000 0Ox201ffc 0x281000 0Ox281ffc 0x301000 0x301ffc 0x381000 0X38 ITTE nos A 42 4 26 1 Bankl_ADC12 0x2001000 enneren a a a a T a E T 42 4 26 2 Bank1_ADC12 OOx2g0 000 42 4 26 3 Bankl_ADC56 0x3001000 essssssesssesesssessressressressrrssrrsrissessessressressressreseresereseeestesseessresete 43 4 26 4 Bankl_ADC78 OOx2R0 000 43 4 27 Event directories bank 2 0x202000 0x202ffc 0x282000 0x282ffc 0x302000 0x302ffc 0x382000 0X3 8246 EE 43 4 28 Bank 1 address counter 0x200008 0x280008 0x300008 02000 44 4 29 Bank 2 address counter 0x20000C 0x28000C 0x30000C 02800 44 4 30 Bank 1 event counter 0x200010 0x280010 0x300010 0x380010 0ooocconcncnononoononoonononononnnononnnonnnnos 45 4 31 Bank 2 event counter 0x200014 0x280014 0x300014 0x380014 000oooocccccooooooonooooooononnonononnnnnnnnnnnos 45 4 32 Actual Sample registers 0x200018 0x280018 0x300018 Ox 28001 46 4 33 Bank 1 memory 0x400000 OXST EC oooooconoocccnnnoccccnooocnncnnoncnonnononononnnonononnnnnn nono ono rnnnn cnn rnnnnnnnnannns 47 4 34 Bank
34. VB NN 63 94 EE ei CR ER E 63 DEL o oia AA A eeE EEE 64 RE 64 O AS A NN 64 10 1 2 5183300 2 and ME EE 64 10 2 TORES tido 64 10 3 Offsettadjustmentis EE 65 104 LAGO io sico 66 A A iden dveaesil beads e E a iae peabenesvadbuidd ent Enn SEs 67 TLI Data acquisition TTT 67 Page 4 of 73 SIS Documentation SIS3300 3301 SIS GmbH 65 100 MHz FADCs VME PET Random xternal clock mod ees eege ege eg AE deed EEN in SEN ENEE 67 LTD Atto bank Switch Moderaci n rl a aiii 67 TP 122 COR dee 68 TES Operatin s CONTAINS 68 L Colinin ne A A eae eka des ie hie Be ehh eas 68 11 3 2 Hotswap live eerste ege EE EES 68 TL4 Connector types ENNER ENEE ENEE ENEE ENER ENEE SEENEN EE EEEE 69 RE P2 rows A G pin assignments EE 69 HG Rood ands Pin Assignments ies eseu lealtad 70 A ut TEEN 71 Page 5 of 73 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME 1 Introduction The SIS3300 3301 are eight channel ADC digitizer boards with a sampling rate of up to 105 MHz for the individual channel and a resolution of 12 14 bit The boards are single width 6U VME card which has no special i e non standard VME voltage requirements Dual memory bank functionality in conjunction with multi event memory structure and a range of trigger options give the unit the flexibility to cover a variety of applications Applications comprise but are not limited to e digitization of slow detectors like calorimet
35. _ADC12 0x600000 define SIS3300_MEMBASE_BANK2_ADC34 0x680000 define SIS3300_MEMBASE_BANK2_ADC56 0x700000 define SIS3300_MEMBASE_ BANK2_ADC78 0x780000 Bank 2 memory is installed to allow for parallel readout from one memory bank while the other memory bank is acquiring data The second memory bank has the same structure as bank 1 Page 47 of 73 SIS Documentation SIS3300 5153301 SIS GmbH 65 100 MHz FADC VME 5 Description of Start Stop and Gate operation modi 5 1 Start stop mode Different start and stop conditions can be used in combination with start stop mode as illustrated in the start and stop logic summaries Note LEMO output 2 ready for stop reflects the phase in which the digitizer is sampling unless the signal was assigned to reflect the bank full pulse by setting bit 9 of the control register Start Stop OV Sampling OFN LEMO Output 2 5 1 1 Front panel start stop One option to use start stop mode is with NIM front panel start and stop signals The width of the start and stop pulse has to exceed 2 sampling clocks Following steps are part of the setup in this case e enable front panel start stop logic by setting bit 8 of acquisition control register e connect start to LEMO input 3 e connect stop to LEMO input 2 5 2 Gate mode A single external signal is used to define sampling start and stop The start signal i e LEMO input 3 is
36. address 0x0 0x4 0x8 33180000 2050201 20d0209 SEET 33180010 2250221 2240229 2350231 33180020 2450241 24d0249 2550251 33180030 2650261 26d0269 2150271 Data with Compress Event readout Start Address 0x4 Compress Factor 0x1 Event Readout Length 0x0f address 0x0 0x4 0x8 33180000 20d0209 21 50 2 151 21d0219 33180010 22d0229 2350231 23d0239 33180020 24d0249 2550251 25d0259 33180030 26d0269 2750271 2740279 0xC 106 10e 116 lle 126 12e 136 13e 146 14e 156 15e 166 16e 176 17e J o h J o h Y JO On 01 O ds ds GA 0YNNRRPOO Hb JF JF JF J D O EE OO E O EE E 0xC 21d0219 23d0239 25d0259 27d0279 0xC 2250221 2450241 2650261 2850281 Page 57 of 73 SIS Documentation SIS3300 SIS3301 65 100 MHz FADC SIS GmbH VME 7 Operation 7 1 Configuration e Issue key reset e define in Interrupt configuration register VME IRQ Level and Vector type of IRQ requester e define in Interrupt control register enable IRQ source e define in Acquistion register Set Clock source Set Start Stop or Gate mode Enable Disable P2 External Start Stop Enable Disable LEMO External Start Stop Enable Disable External Stop Delay Enable Disable External Start Delay Set Single or Multi Event Mode if Multi Event then enable disable Autostart e define in Event configuration register Enable Disable Autostop at end address of Page Set Page size
37. cle 0 2 IRQ Vector Bit 2 placed on D2 during VME IRQ ACK cycle 0 1 IRQ Vector Bit 1 placed on D1 during VME IRQ ACK cycle 0 0 IRQ Vector Bit 0 placed on DO during VME IRQ ACK cycle 0 The power up default value reads Ox 00000000 Page 20 of 73 SIS Documentation SIS3300 3301 65 100 MHz FADCs SIS GmbH VME 4 4 Interrupt control register 0xC define SIS3300_IRQ CONTROL OxC read write D32 This register controls the VME interrupt behaviour of the SIS3300 ADC Four interrupt sources are foreseen for the time being three of them are associated with an interrupt condition the fourth condition is reserved for future use Bit Function w r Default 31 unused Status IRQ source 3 user input 0 30 unused Status IRQ source 2 reserved 0 29 unused Status IRQ source 1 end of last event bank full 0 28 unused Status IRQ source 0 end of event 0 27 unused Status VME IRQ 0 26 unused Status internal IRQ 0 25 unused 0 0 24 unused 0 0 23 Clear IRQ source 3 Status flag source 3 0 22 Clear IRQ source 2 Status flag source 2 0 21 Clear IRQ source 1 Status flag source 1 0 20 Clear IRQ source O Status flag source 0 0 19 Disable IRQ source 3 0 0 18 Disable IRQ source 2 0 0 17 Disable IRQ source 1 0 0 16 Disable IRQ source 0 0 0 15 unused 0 0 14 unused 0 0 13 unused 0 0 12 unuse
38. clock enable bit in the acquisition control register or use the end of event or bank full interrupt conditions Page 59 of 73 SIS Documentation SIS3300 5153301 SIS a 65 100 MHz FADC VME 8 Board layout A printout of the silk screen of the component side of the PCB is shown below 3 DR mM AE y LED94LEDES LEDS2LEDB1 A Cat al Co cin Ok yg s 5 8 j pH a CH Bi ES Sen gn uaaa J want 7 uze cr24 7 ACLL op Ca ca Ll IA LL JE Lis LJ LIC 4 HE LA lo lo la mnn LC CH SL Z C1706 cazon I Beer Page 60 of 73 SIS Documentation SIS3300 3301 SIS GmbH t 65 100 MHz FADCs VME 9 Front panel The SIS3300 is a single width 4TE 6U VME module A sketch of the front panel without handles is show below D a a un O O O Ri o 3 Lo q SR gt S N OO 00O Page 61 of 73 SIS3300 5153301 SIS Documentation SIS GmbH 65 100 MHz FADC VME 9 1 Control In Outputs The control I O se
39. connected via inductors Page 70 of 73 SIS Documentation SIS3300 3301 SIS GmbH 65 100 MHz FADCs VME 12 Index 2eVME tee ere ast Pvt 7 12 16 AT EE 61 isis di 61 Eege eer ie bedreet cas EE staves H Anere ege eelerer las bs do 7 13 64 address EN 64 Address Mapicciciotins iii 14 SS i niesna TO 13 addressing geographical inicia H AMMAN dais int ege de EE ee edu ege teens 19 Analog putita 62 AMA 17 AUTOSTART ix ados 67 AVETASING a cs 31 RE RO eege eege GE ae es 67 B2 RUDD ile 67 back pl Meninas 7 13 68 bank 1 address counter ceeeeeseeeeesseeeeeetneeeeeeteees 44 disable sample clock ooooooonoccnnonccnonccnonnccnnoss 23 enable sample clock 23 event COUNTED isigi Tei resi Teri TS 45 EVENt directory O Ataa 42 43 event time stamp directory cooooonocccnonccnonnncnnns 29 MEMO EE 47 trigger event directory ooooooooccccononcncnnonncnnnnnnos 41 bank 2 address counter eceeeeseeeeesseeeeeeeneeeeeeeees 44 disable sample clock oooooconccnnonccnonccionncinnns 23 enable sample clock 23 Event COUNT ER 45 event time stamp directory oooooccocccnonccnonnncnnnss 29 MEMO aiii 47 trigger event directory ooooocoooccccononcccnononcnonnnnns 41 block RAM ii sesveiassiveteriaeeierctieestaccstecateceeecdaceesens 9 BEE geed 7 12 board layout eeeeeeseceeseeceseeesneecsneeseneeeesaes 60 Bora 20 ON H external nina 10 18 internal ceci iii recta nei 10 LO iii die 10 Clock SOUICE iii
40. ction features 8 LEMOOO connectors with NIM levels Designation Inputs Outputs Designation 4 Clock In Clock Out 4 3 Start Ready for Start bank full output 3 2 Stop Ready for Stop bank full output 2 1 User in User out trigger Multiplexer Strobe bank full output 1 The ready for start and ready for stop outputs can be used to interfere with external deadtime logic Ready for start will become active as soon as the sample clock for one of the banks is active Ready for stop will go active as soon as the start signal was seen by the module The external clock must be a symmetric signal unless the module is operated in external random clock mode The width of an external start stop pulse must be greater or equal two sampling clock periods 9 1 1 User input User input functionality was implemented to allow for synchronous recording of one external status bit like chopper on off e g with the ADC data stream The user bin information is recorded with the ADC data see section 4 33 The current status of the logic level is represented by Bit 16 of the status register 9 1 2 Control input termination The control inputs are configured for 50 2 termination i e with 47 Q by default Each input is terminated with a resistor network 5 pins 4 resistors common pin to socket pin 6 to ground the names of the input sockets are listed in the table below Designation Inputs Resistor Network
41. d 0 0 11 unused 0 0 4 unused 0 0 3 Enable IRQ source 3 Status enable source 3 read as 1 if enabled 0 if disabled 0 2 Enable IRQ source 2 Status enable source 2 read as 1 if enabled 0 if disabled 0 1 Enable IRQ source 1 Status enable source 1 read as 1 if enabled 0 if disabled 0 0 Enable IRQ source 0 Status enable source 0 read as 1 if enabled 0 if disabled 0 The power up default value reads Ox 00000000 Page 21 of 73 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME The generation of the status flags the IRQ flags and the actual IRQ is illustrated with the schematic below Es Status FLAG Source O Source 0 SC es ource Clear Enable 0 x Status FLAG SE internal VME_IRQ Status IRQ o SEET Sie 1 OR VME_IRQ m ear Enable 1 SN ae Clear Source 2 1 pi ource Cleat Enable 2 Y Status FLAG Se LU Source 3 AN D Source 3 Source 3 clear Enable 3 VME_IRQ_ENABLE gt o ROAK AN D RD_IRQ_ACK Page 22 of 73 SIS Documentation SIS3300 3301 SIS GmbH 65 100 MHz FADCs VME 4 5 Acquisition control register 0x10 read write define SIS3300_ACQUISTION_CONTROL 0x10 read write D32 The acquisition control register is in charge of most of the settings related to the actual configuration of the digitization process Like the control re
42. e auto bank switch mode 4 14 Key address clear BANK1 FULL Flag 0x48 write define SIS3300_KEY_BANK1_FULL_FLAG 0x48 write only D32 A write with arbitrary data to this register key address will clear the BANK1 FULL Flag 4 15 Key address clear BANK2 FULL Flag 0x4C write define SIS3300_KEY_BANK2_FULL_ FLAG 0x4C write only D32 A write with arbitrary data to this register key address will clear the BANK2 FULL Flag Page 28 of 73 SIS Documentation SIS3300 3301 SIS GmbH 65 100 MHz FADCs VME 4 16 Event Time Stamp directory bank 1 0x1000 0x13fc read only define SIS3300_EVENT_TIMESTAMP_DIR_BANK1 0x1000 read only D32 BLT32 size 0x400 The event time stamp directory can be used to measure time between triggers stops in multi event mode A scaler counting the ADC clock is enabled with the first stop hence the time stamp for the first event will read 0 always The counter value of the 24 bit wide scaler is written to the corresponding location for subsequent events offset address Time Stamp D23 D0 0x0 Time Stamp 0 Ox3fc Time Stamp 255 4 17 Event Time Stamp directory bank 2 0x2000 0x2ffc read only define SIS3300_EVENT_TIMESTAMP_DIR_BANK2 0x2000 read only D32 BLT32 size 0x400 As for bank 1 offset address Time Stamp D23 D0 0x0 Time Stamp 0 Oxffc Time Stamp 255 Page
43. e mounted red LEDs D200A to D200H on the top left corner of the component side of the SIS3300 are routed to the control FPGA their use may depend on the firmware design Page 63 of 73 SIS3300 5153301 65 100 MHz FADC SIS Documentation SIS GmbH VME 10 Jumpers Configuration 10 1 J1 The function of J1 depends on the PCB printed circuit board revision level The board revision level is printed in white on the lower edge of the card on the component side as a text of the form SIS3300_V1 e g 10 1 1 SIS3300_V1 Selection of bits 31 28 of the 32 bit A32 address see base address section 10 1 2 SIS3300_V2 and higher The SIS3300 supports several addressing modes the actual mode is selected by jumper array J1 The given mode is selected if its corresponding jumper is in place The four jumper positions are described in the table below The A32 jumper is closest to the modules front panel Jumper Function Factory default EEE A32 enable A32 addressing closed E GEO enable geographical addressing open VIPA not implemented yet open a reserved reserved open 10 2 J190 Reset Jumper 5 of jumper array J190 defines the reset behaviour of the SIS3300 upon VME Sysreset If the jumper is closed the module will be reset with VME Sysreset The other fields of the array are unused in the current firmware design
44. ed for better resolution with symmetric input range Common properties of all boards are 8 channels special clock modes clock prescaling external arbitrary clock channel to channel crosstalk below noise i e invisible in Fourier spectrum external internal clock multi event mode Read on the fly actual sample value pre post trigger option Two independent memory banks trigger generation 4 NIM control inputs 4 NIM control outputs A32 D32 BLT32 MBLT64 2eVME Geographical addressing mode in conjunction with VME64x backplane Hot swap in conjunction with VME64x backplane VME64x Connectors VME64x Front panel EMC shielding on request VME64x extractor handles on request F1002 compatible P2 row A C assignment 5 V 12V and 12 V VME standard voltages Note The SIS3300 1 shall not be operated on P2 row A C extensions like VSB e g due to the compatibility to the F1001 FADC modules clock and start stop distribution scheme Page 7 of 73 SIS Documentation SIS3300 5153301 65 100 MHz FADC SIS GmbH VME 2 2 Module design The SIS3300 consists of four identical groups of 2 ADC channels and a control section as shown in the simplified block diagram below System Clock Fr Control UO VME Interface and ont Panel A Control FPGA A Distribution Clock ae VMEBus Dual Channel Group 4 Channels 7 and 8
45. emo Start Stop logic Status front panel start stop logic 7 Enable stop delay value defined by stop delay register Status stop delay 6 Enable start delay value defined by start delay register Status start delay 5 Enable multi event mode Status multi event mode 0 Enable Sample Clock will be cleared with end of event 1 Enable Sample Clock will be cleared at end of bank only i e with last page of memory 4 Enable Autostart in multi event mode only Status Autostart 3 Enable reserved Status reserved 2 Enable auto bank switch mode Status auto bank switch mode 1 Enable Sample Clock for Memory Bank 2 arm for sampling Status sample clock bank 2 0 Enable Sample Clock for Memory Bank arm for sampling Status sample clock bank 1 The power up default value reads Ox Page 23 of 73 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME Clock source bit setting table Clock Source Clock Source Clock Source Clock Source Bit2 Bitl BitO 0 0 0 internal 100 MHz 0 0 1 internal 50 MHz 0 1 0 internal 25 MHz 0 1 1 internal 12 5 MHz 1 0 0 internal 6 25 MHz 1 0 1 internal 3 125 MHz 1 1 0 external clock front panel LEMO IN 4 via DLL 1 1 1 external clock front panel LEMO IN 4 direct Refer to the table in section 2 5 2for allowed clock speeds Lower sampling rates into memory can be accomplished with a sampling clock within the specified range i
46. en for the time being three of them are associated with an interrupt condition the fourth condition is reserved for future use The interrupter type is DO8 4 3 1 IRQ mode In RORA release on register access mode the interrupt will be pending until the IRQ source is cleared by specific access to the corresponding disable VME IRQ source bit After the interrupt is serviced the source has to be activated with the enable VME IRQ source bit again In ROAK release on acknowledge mode the interrupt condition will be cleared and the IRQ source disabled as soon as the interrupt is acknowledged by the CPU After the interrupt is serviced the source has to be activated with the enable VME IRQ source bit again ROAK IRQ mode can be used in conjunction with the University of Bonn LINUX Tundra Universe II driver by Dr J rgen Hannappel on Intel based VME SBCs Bit Function Default 31 0 BS 0 16 0 15 0 14 0 13 0 12 RORA ROAK Mode 0 RORA 1 ROAK 0 11 VME IRQ Enable 0 IRQ disabled 1 IRQ enabled 0 10 VME IRQ Level Bit 2 0 9 VME IRQ Level Bit 1 0 8 VME IRQ Level Bit 0 0 7 IRQ Vector Bit 7 placed on D7 during VME IRQ ACK cycle 0 6 IRQ Vector Bit 6 placed on D6 during VME IRQ ACK cycle 0 5 IRQ Vector Bit 5 placed on D5 during VME IRQ ACK cycle 0 4 IRQ Vector Bit 4 placed on D4 during VME IRQ ACK cycle 0 3 IRQ Vector Bit 3 placed on D3 during VME IRQ ACK cy
47. ent counter ADC5 ADC6 0x00300018 4 R Actual Sample Value ADC5 ADC6 0x0030001C 4 R W Trigger Flag Clear Counter register ADCS ADC6 0x00300020 4 R W Compress Event Readout configuration ADCS ADC6 0x00300028 4 R W Trigger setup register ADC5 ADC6 0x0030002C 4 R W Max No of Events register ADCS ADC6 0x00301000 0x1000 BLT32 R Event directory bank 1 ADCS ADC6 0x00302000 0x1000 BLT32 R Event directory bank 2 ADCS ADC6 Event information ADC group 4 0x00380000 4 R W Event configuration Register ADC7 ADC8 0x00380004 4 R W Trigger Threshold register ADC7 ADC8 0x00380008 4 R Bank address counter ADC7 ADC8 0x0038000C 4 E R Bank address counter ADC7 ADC8 0x00380010 4 R Bank1 Event counter ADC7 ADC8 0x00380014 4 R Bank Event counter ADC7 ADC8 0x00380018 4 R Actual Sample Value ADC7 ADC8 0x0038001C 4 R W Trigger Flag Clear Counter register ADC7 ADC8 0x00380020 4 R W Compress Event Readout configuration ADC7 ADC8 0x00380028 4 R W Trigger setup register ADC7 ADC8 0x0038002C 4 R W Max No of Events register ADC7 ADC8 0x00381000 0x1000 BLT32 R Event directory bank 1 ADC7 ADC8 0x00382000 0x1000 BLT32 R Event directory bank 2 ADC7 ADC8 Bank 1 memory Page 15 of 73 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME 0x00400000 0x80000 BLT32 MBLT64 2eVME R W Bank memory ADCI ADC2 0x00480000 0x
48. ers e spectroscopy with Ge detecors e beam profile monitor readout e serialized readout of u Strip detector data This manual describes the filtering trigger firmware version of the SIS3300 At present this design is not implemented for the SIS3301 yet this can be done on request on short notice however As we are aware that no manual is perfect we appreciate your feedback and will try to incorporate proposed changes and corrections as quickly as possible The most recent version of this manual can be obtained by email from info struck de the revision dates are online under http www struck de manuals htm 1 1 Related documents A list of available firmware designs can be retrieved from http www struck de sis3300firm htm The JTAG firmware installation procedure is described in http www struck de sis3300_jtagprog pdf Page 6 of 73 SIS Documentation SIS3300 3301 SIS GmbH 65 100 MHz FADCs VME 2 Technical Properties Features 2 1 Key functionality Find below a list of key features of the SIS3300 and SIS3301 digitizers SIS3300 SIS3301 65 SIS3301 105 Sampling rate per channel 105 MHz 65 MHz 105 MHz Minimum symmetric clock 1 MHz 15 MHz 15 MHz Resolution 12 bit 14 bit 14 bit Analog bandwidth gt 80 MHz 35 MHz Typical pedestal variance 0 7 bit 1 1 bit Y Differential input version A A 2 x 128 KSample default A A A 2 x 512 KSample option A A limit
49. f the SIS3300 1 board like output signal assignment in write access It is implemented via a selective J K register a specific function is enabled by writing a 1 into the set enable bit the function is disabled by writing a 1 into the clear disable bit which location is 16 bit higher in the register An undefined toggle status will result from setting both the enable and disable bits for a specific function at the same time On read access the same register represents the status register Bit write Function read Function 31 Clear reserved 15 30 Clear reserved 14 29 Clear reserved 13 28 Clear reserved 12 27 Clear reserved 11 26 clear bank full pulse to output 3 25 clear bank full pulse to output 2 24 clear bank full pulse to output 1 23 Clear reserved 7 22 Disable internal trigger routing 21 Activate trigger upon armed 20 Non inverted trigger output 19 Clear Reset Delay Locked Loop DLL for Status P2_SAMPLE_IN external clock 18 Enable user output disable trigger output Status P2_RESET_IN 17 Clear user output Status P2_TEST_IN 16 Switch off user LED Status User Input 15 Set reserved 15 Status Control 15 14 Set reserved 14 Status Control 14 13 Set reserved 13 Status Control 13 12 Set reserved 12 Status Control 12 11 Set reserved
50. gister it is implemented in a J K fashion Bit Write Function Read 31 Clear reserved 0 30 Clear Clock Source Bit2 0 29 Clear Clock Source Bitl 0 28 Clear Clock Source BitO 0 27 Disable external clock random mode 0 26 Disable front panel gate mode not start stop 0 25 Disable P2 Start Stop logic 0 24 Disable front panel LEMO start stop logic 0 23 Disable external stop delay Bank 2 full 22 Disable external start delay Bank 2 busy 21 Disable multi event mode Bank 1 full 0 Enable sample clock will be cleared with end of event 1 Enable sample clock will be cleared at end of bank only i e with last page of memory 20 Disable Autostart in multi event mode only Bank 1 busy 19 Disable reserved 0 18 Disable auto bank switch mode Bank switch busy 17 Disable sample clock for memory bank 2 disarm sampling 0 16 Disable sample clock for memory bank disarm sampling ADC_BUSY 15 Set reserved 0 14 Set clock source Bit 2 Status clock source Bit 2 13 Set clock source Bit 1 Status clock source Bit 1 12 Set clock source Bit 0 Status clock source Bit 0 11 __ Enable external clock random mode Status external clock random mode 10 Enable front panel gate mode not Start Stop Status front panel gate mode 9 Enable P2 Start Stop logic Status P2 start stop logic 8 Enable front panel L
51. he peaking time P 10 again This mechanism is implemented in the example software also 153301_Slave Test menue Values after Init SIS3300_ACQUISTION_CONTROL 80 64 800 100a SIS3300_CONTROL_STATUS SIS3300_STOP_DELAY SIS3300_EVENT_CONFIG_ADC1z2 IS3300_TRIGGER_THRESHOLD_ADC1Z 72008000 SIS3300_TRICGER_THRESHOLD_ADC12 80008000 SIS3300_TRIGGER_THRESHOLD_ADC12 80008000 IS3300_TRIGGER_THRESHOLD_ADC1Z 70008000 Page Size F 4K Sample Wrap around Stop Delay dec Peaking Time dec 2048 4 10 Ch Flag reg dec Gap Time dec 2300 Fl 30 FIR Test Mode Trig Puls Length 0 3 FIR Test ADC 1 3 5 7 Threshold hex FIR Counts dec ADC Counts dec E 1750 Y Min Scale ADCS disable Fel 8000 ADCS disable 8000 ADCS disable o ADC4 disable 8000 ADC3 disable 8000 ADC2 disable 8000 app Sut em EE ER 22 DDD D 2 D 1750 i i 1990 2000 2010 2030 2040 2050 2060 2070 2080 2080 show only ADC1 2090 xMarScale he QUIT Page 39 of 73 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME 4 23 MAX No of Events registers 0x10002C 0x20002C 0x28002C 0x30002C 0x38002C tdefine SIS3300_MAX_NO_OF_EVENTS_ALL_ADC 0x10002C write only D32 define SIS3300_ MAX_NO_OF_EVENTS_ADC12 0x20002C read wr
52. ingle Event Mode cinta ii EES 9 2 4 2 Multi Event Modest il ee anida 9 2 4 3 Dual Bank Moderna a Sieh ae Bi ass ataca ose 9 Zid ee Oe re 10 2 5 1 Internal Clock cita iia iaa oa a A ah isis 10 2 5 2 External clock iii ica aia daa a 10 2 5 3 Random External Clock ceci siii aaa oa nani ici 10 2 6 Trigger control pre post start stop and gate mode 11 21 Internal RS A NN 11 2 87 Tite Stamp Memory 015 0 su da id a as 11 29 MME A NS 11 210 MME Readout Speed ef A sde edereg t kee deteget bd stee n kd Eet ege kd Eet ege deefe eege ea 12 S EE 13 3 1 Address Mapa a sd ds me eS 14 do Register DEIER 17 4 1 Control Status Register 0x writeiread nro nonnn cnn cnn nnnnnnnnnnnnnnnnnnnns 17 4 1 1 Re A T teases ten sler ges AE AT ti 18 4 1 2 Ree 18 4 1 3 Reset locked loop for external clock SIS3301 IIIe 18 4 2 Module Id and Firmware Revision Register 0x4 read 19 4 2 1 Major revision DEE eege O teasiss 19 4 3 Interrupt configuration register Us 20 4 3 1 ROM eege ata Ee er aman east imal 20 4 46 Interrupt control register LTE besen geesde deeg eege eet eege EE 21 4 5 Acquisition control register 0x10 readiwrte 23 4 6 Start Delay register 0x14 readiwrte non nncnnnnconnnonnn nc nnncnnnccinns 25 4 7 Stop Delay register 0x18 readiwrte nono nncnonnncon ccoo nncnnnncnanacinne 25 4 8 Time stamp predivider register sl 26 4 9 Key address general reset 0x20 write non nncnnnnnan arca ano nnnncnanacinne 27 4 10 Key add
53. it 6 of the control register set the trigger 1s used to stop the module what is a efficient mode of operation in conjunction with autostart e g 4 1 2 Trigger routing The trigger status is present on LEMO output 1 with user output and multiplexer mode disabled It can be used to form a general trigger decision with external trigger electronics which is fed back to the corresponding input start stop on the digitizer s The trigger is routed on board to the stop input with the internal trigger routing bit set 4 1 3 Reset locked loop for external clock SIS3301 11 16 If this bit is set then the DLL for the external Clock LEMO In is in Reset state After clearing this bit the DLL needs 1000 clocks to work correctly The external clock for DLL has to be running continuously The external clock signal in the range 60 105 MHz from a SIS3820 clock distributor e g is used to drive a delay locked loop The delay locked loop output is used as ADC clock Page 18 of 73 SIS Documentation SIS3300 3301 SIS GmbH 65 100 MHz FADCs VME 4 2 Module ld and Firmware Revision Register 0x4 read define SIS3300_MODID 0x4 read only D32 This register reflects the module identification of the SIS3300 1 and its minor and major firmware revision levels The major revision level will be used to distinguish between substantial design differences and experiment specific designs while the minor revision level will be used to mark
54. ite D32 define SIS3300_ MAX_NO_OF_EVENTS_ADC34 0x28002C read write D32 define SIS3300_ MAX_NO_OF_EVENTS_ADC56 0x30002C read write D32 define SIS3300_ MAX_NO_OF_EVENTS_ADC78 0x38002C read write D32 This register is implemented for each channel group and it has to be configured to the same value in all groups what is done most straightforward by writing to the address STS3300_MAX_NO_OF_EVENTS_ALL_ADC This register is used in GATE Chaining Multi Event Mode only It limits the number of Events in the GATE Chaining Multi Event Mode ate chaining mode sampling will stop when a the maximum number of events is reached or b the end of bank is reached In this case the last event gate may be incomplete Bit 31 16 15 0 Function unused read back as O Max No Of Events The power up default value is 0 Page 40 of 73 SIS Documentation SIS3300 3301 SIS GmbH I 65 100 MHz FADCs VME 4 24 Trigger event directory bank 1 0x101000 0x101ffc define SIS3300_EVENT_DIRECTORY_BANK1_ ALL ADC 0x101000 read only D32 BLT32 size 0x1000 This Trigger event directory holds the stop pointer s i e end address 1 of memory bank 1 The directory is 32 bits wide a wrap around bit i e bit 19 will be set if the page was filled at least once i e if the memory pointer has reached the end offset address Event Data End Address D16 D0
55. mber of samples after which the Trigger Flag bit will be cleared unless a new trigger occurred A counter for the given ADC channel is preloaded with the value of the Trigger Flag Clear counter register when the trigger criterion for this channel is met Consecutive sampling clocks will decrement the counter and the Trigger Flag bit will be cleared as soon as the counter reaches 0 If a new trigger occurs before the counter has reached O it will be reloaded with the value from the register retrigger Note typically the user may want to set the value of the Trigger Flag Clear counter register to the memory page size but this is not mandatory The Trigger Flag Clear Logic is disabled if the counter is loaded with 0 power up default Bit 31 16 15 0 Function unused read back as 0 __ Trigger Flag Clear counter register The power up default value is 0 Page 34 of 73 SIS Documentation SIS3300 3301 SIS GmbH 65 100 MHz FADCs VME 4 21 No_Of_Sample register 0x100024 0x200024 0x280024 0x300024 0x380024 define SIS3300_NO_OF_SAMPLE_ALL ADC 0x100024 write only D32 define SIS3300_NO_OF_SAMPLE_ADC12 0x200024 read write D32 define SIS3300_NO_OF_SAMPLE_ADC34 0x280024 read write D32 define SIS3300_NO_OF_SAMPLE_ADC56 0x300024 read write D32 define SIS3300_NO_OF_SAMPLE_ADC78 0x380024 read write D32 This register is implemented for each channel group and it has to be
56. n combination with the clock predivider register in multiplexer mode or random external clock mode Page 24 of 73 SIS Documentation SIS3300 3301 SIS GmbH i 65 100 MHz FADCs VME 4 6 Start Delay register 0x14 read write define SIS3300_START_DELAY 0x14 read write D32 Pretrigger operation can be implemented via the start delay register in conjunction with front panel start stop or gate mode operation The external and autostart start signal or leading edge of the gate will be delayed by the value of the register 2 clocks if the external start delay is enabled in the acquisition control register Bit 31 unused read as O 16 unused read as O 15 START_DELAY_BITI5 0 START_DELAY_BITO The power up default value is O 4 7 Stop Delay register 0x18 read write define SIS3300_STOP_DELAY 0x18 read write D32 Posttrigger operation can be implemented via the stop delay register in conjunction with front panel start stop or gate mode operation The external stop signal or trailing edge of the gate will be delayed by the value of the register 2 clocks if the stop delay is enabled in the acquisition control register Bit 31 unused read as O 16 unused read as O 15 STOP_DELAY_BITI5 0 STOP _DELAY_BITO The power up default value is 0 Page 25 of 73 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME
57. ng buffer 19 4 shift right by 4 if P 128 to 255 21 bit signless add sub 16 bit to ring buffer 20 5 shift right by 5 14 bit units SIS3301 ifP 2to7 16 bit signless add sub 16 bit to ring buffer 17 2 shift right by 2 ifP 8to 15 17 bit signless add sub 16 bit to ring buffer 18 3 shift right by 3 if P 16to 31 18 bit signless add sub 16 bit to ring buffer 19 4 shift right by 4 if P 32 to 63 19 bit signless add sub 16 bit to ring buffer 20 5 shift right by 5 if P 64 to 127 20 bit signless add sub 16 bit to ring buffer 21 6 shift right by 6 if P 128 to 255 21 bit signless add sub 16 bit to ring buffer 22 7 shift right by 7 SUMI 0 for G i lt G P i SUM1 SUM1 adc_value i SUM2 0 for G 0 i lt P i SUM2 SUM2 adc_value i Trigger sum SUM1 SUM2 gt gt x_ 0x8000 x see above Oxffff if SUM1 gt SUM2 0x8000 if SUMI SUM2 if SUMI lt SUM2 0x0 Page 38 of 73 SIS Documentation SIS3300 3301 SIS GmbH 65 100 MHz FADCs VME 4 22 1 4 Trigger example The screenshot below shows a signal on ADC channel 1 and the resulting FIR value with test mode enabled The trigger condition is set to LT the hexadecimal threshold ist at 0x7E00 what results in a decimal threshold of 102 counts 0x7E00 0x8000 0x200 this has to be shifted to the left by 1 bit as the peaking time p is in between of 8 and 15 the resulting 1024 has to be divided by t
58. nk 1 The directories are 32 bits wide a wrap around bit i e bit 19 will be set if the page was filled at least once i e if the memory pointer has reached the end 4 26 1 Bank1_ADC12 0x2001000 offset address _ Event Data End Address D16 D0 O Al o uI O ol DI Gi O el A AL al al A QA ll a a ae aaaa ae ealya 0x0 T T O W O End Address 1 of Event 0 1 2 Oxffc TT O W O End Address 1 of Event 1023 1 2 W wrap around bit T1 T2 trigger information ADC 1 and ADC 2 4 26 2 Bank1_ADC12 0x2801000 offset address Event Data End Address D16 D0 D23 20 D19 D18 D17 D31 D30 D29 D28 D27 D26 D25 D24 0x0 End Address 1 of Event 0 L rd AH Oxffc End Address 1 of Event 1023 mge gt W wrap around bit T3 T4 trigger information ADC 3 and ADC 4 Page 42 of 73 SIS Documentation SIS3300 3301 SIS GmbH i 65 100 MHz FADCs VME 4 26 3 Bank1_ADC56 0x3001000 offset address _ Event Data End Address D16 D0 S O Al CO R O M DY O el A AL Al Al A QA ll el a aaaaaaaeeaaya 0x0 T T O W 0 End Address 1 of Event 0 5 6 Oxffc TIT O IW O End Address 1 of Event 1023 5 6 W wrap around bit T5 T6 t
59. nnnccnananinnnos 69 PAra ios 9 Pares cima 32 PB a 64 70 Peaking tim n rengar ara a 37 38 pipelines niie n e Reali inka 26 Pipetite e R Sa 10 26 el d IERE E E Bee ES 59 potentiometer OMS dat 65 power CONSUMPTION ooconocccnocccoonncnonccionaconnnccnnncono 68 PROM eiia n nico o fa de 66 pulse lesions naa dise 37 LM IT co eat 47 register acquisition control 9 11 23 25 48 49 59 67 actual sample 46 clock Predivide ici 40 compress event readout configuration 55 compress event readout status 54 ee te 19 48 49 descrpton c occcccooocccnnonccccononcnonnnnncnnonancnoninnnnno 17 event Copftguraton 9 30 firmware revision ocooooooonnonnccnnnonnncnnnancnoninnnnnos 19 interrupt configuration ooooonocccnocncnonncnnnnos 20 21 memory configuration ooooconccnonccconancnonccnonccnnne 9 module Idi 19 No OC Sample cooococccooccnccnoncccnnonncnnonananoninnncnos 35 start compressed event readout 53 A Ledunetet eege Ne e 23 25 E E 62 stop delo indio 23 25 stop abort compress event readout 53 Ubresbhold 33 34 time stamp Dredtvider ee eeeeeeeeesneeeeneees 26 tigger SCP en dieses oe EEN 36 37 Eben Geess deeg e eens 64 ROAR vii seis atin EES 20 RORA cuca dlls 20 Tot ryiS A OT 13 e EE 20 A cupidse des teas a Ea anei aut 62 KI LEE 38 SIS33 Leica aiii 38 MO dd a ado 38 SM Lita a ai 13 AE 13 TCK EE 66 NEIE 66 TDO iia andes 66 Technical Properties Features
60. oad its firmware either from two serial PROMs or via the JTAG port on connector CON100 A list of firmware designs can be found under http www struck de sis3300firm htm Hardware like the XILINX HW JTAG PC in connection with the appropriate software will be required for in field JTAG firmware upgrades The JTAG connector is a 9 pin single row 1 10 inch header the pin assignment on the connector can be found in the table below Pin Short hand Description 1 VCC Supply voltage 2 GND Ground 3 nc not connected cut to avoid polarity mismatch 4 TCK test clock 5 nc not connected 6 TDO test data out 7 TDI test data in 8 nc not connected 9 TMS test modus Page 66 of 73 SIS Documentation SIS3300 3301 SIS GmbH 65 100 MHz FADCs VME 11 Appendix 11 1 Data acquisition modes 11 1 1 Random external clock mode Random external clock mode is activated by writing 0x800 to the acquisition control register 11 1 2 Auto bank switch mode Auto bank switch mode was introduced for efficient use of the two memory banks on acquisition The mode is activated by issuing a KEY_START_AUTO_BANK_ SWITCH after the feature was activated by setting bit 2 in the acquisition control register The bank full flags B1_FULL and B2_FULL are cleared with the KEY at the same time a first start is generated if AUTOSTART is enabled also Data will be acquired into memory bank 1 until the bank is full
61. out 0x00001000 0x1000 BLT32 R Event Time Stamp directory bank 1 0x00002000 0x1000 BLT32 R Event Time Stamp directory bank 2 Event information all ADC groups 0x00100000 4 W only Event configuration register all ADCs 0x00100004 4 W only Trigger Threshold register all ADCs 0x0010001C 4 W only Trigger Flag Clear Counter register all ADCs 0x00100020 4 W only Compress Event Readout configuration all ADCs 0x00100028 4 W only _ Trigger setup register all ADCs 0x0010002C 4 W only Max No of Events register all ADCs 0x00101000 0x1000 BLT32 R Event directory bank 1 all ADCs 0x00102000 0x1000 BLT32 R Eevent directory bank 2 all ADCs 0x00180000 0x 10000 Ronly Compress Event Readout Fifo Event information ADC group 1 0x00200000 4 R W Event configuration register ADC1 ADC2 0x00200004 4 R W Trigger Threshold register ADC1 ADC2 0x00200008 4 R Bank address counter ADC1 ADC2 0x0020000C 4 R Bank2 address counter ADC1 ADC2 0x00200010 4 R Bank Event counter ADC1 ADC2 0x00200014 4 R Bank2 Event counter ADC1 ADC2 0x00200018 4 R Actual Sample Value ADC1 ADC2 0x0020001C 4 R W Trigger Flag Clear Counter register ADC1 ADC2 0x00200020 4 R W Compress Event Readout configuration ADC1 ADC2 0x00200028 4 R W Trigger setup register ADC1 ADC2 Page 14 of 73
62. pipeline structure allows for high speed readout in block transfer mode BLT32 MBLT64 2eVME The timings below were measured with the SIS3100 VME master and the SIS3300 SIS3301 VME Slave The upper scope trace shows the VME signal DS1 Data strobe low active The VME Master asserts the DS1 to request read data The lower signal shows the VME signal DTACK Data Acknowledge low active The VME Slave asserts the DTACK to acknowledge that the data is valid on VME Tek Run LOOMs s gut Res Trig 118ns i 11815 Edge Slope l SIS330x DS to DTACK 30 40ns FARN US 32bit every 120ns gt 33 MByte sec e DIS Um 2 00 V w CH 2 00 M Toons Chia i s4 v l Source Coupling Level lode TYPE amp lt Edge gt cht ER X 1 84 V Holdoff Tek Run 100MS 5 il Res DE j i SIS330x DS to DTACK 30 40ns a o ANS YE 64bit every 125ns gt 64 MByte sec z i ES 2 00V NM Ch2 2 00 v 100ns Chi A 1 84 V Source coupling slope Level Mode lt Edge gt chi DC 1 34 V Hokioff MBLT64 Tek Run 100MS s Hi Res iT rig LF i Ha 2285 edge stope SIS330x DS to DTACK 50 60ns epee ae Pa 128bit every 200ns gt 80 MByte sec LL Zi pl H Mode Holdoff L Source Coupling Level chi DC 189 V 2eVME Page 12 of 73 SIS Documentation SIS3300 3301 SIS GmbH I 65 100 MHz FADCs VME
63. r SIS3300_TRIGGER_SETUP_ALL_ADC is used to write to the registers of all channel groups simultaneously Bit 31 reserved 30 reserved read 0 29 reserved read 0 28 enable pulse mode 27 Trigger mode ADC2 of group GT 26 Trigger mode ADC2 of group LT 25 Trigger mode ADC1 of group GT 24 Trigger mode ADC1 of group LT 23 reserved read 0 22 reserved read 0 21 Enable FIR test mode 20 Test even ADC 0 ADC1 FIR data stored to ADC2 memory 19 P bit 3 18 P bit 2 17 Phil Puls length P 16 P bit 0 15 G bit 7 14 G bit 6 13 G bit 5 12 G bit 4 Il G bit 3 SSES 10 G bit 2 9 G bit 1 8 G bit 0 7 P bit 7 6 P bit 6 5 P bit 5 4 P bit 4 3 TE Peaking time P 2 P bit 2 1 P bit 1 0 P bit 0 The power up default value reads 0x 00000000 Page 36 of 73 SIS Documentation SIS3300 3301 SIS GmbH 65 100 MHz FADCs VME 4 22 1 FIR Trigger A trapezoidal FIR filter was implemented in major firmware revision 0x11 according to the document description of a FIR filter to be implemented in the SIS3300 board by Kai Vetter of LLNL 4 22 1 1 Activation setup FIR triggering has to be disabled before setting the peaking time gap time and pulse length parameters The proper procedure is disable FIR trigger clear bit31 of trigger setup register set peaking time set gap time set pulse length enable FIR trigger Note parameter changes with FIR triggering being active 4 22 1 2 Test mode
64. ress VME start sampling 0x30 wrte 27 4 11 Key address VME stop sampling 0x34 wte conan ncnanccinne 27 4 12 Key address start Auto Bank Switch mode 0x40 Write oooooonnnocccnnnoocccnoooncncnoonnnononnncnnnnnnnnnnnnannnonns 28 4 13 Key address stop Auto Bank Switch mode 0x44 wrtel 28 4 14 Key address clear BANK1 FULL Flag 0x48 write oooooocconccnonccconccononccnnnnonanccnonacconnnonnnnonnnccnanacinne 28 4 15 Key address clear BANK2 FULL Flag Ox4C wrtei eee eeeseecsseeceseeeeseeeesneecsseecseesesaeeesaeeesaeees 28 4 16 Event Time Stamp directory bank 1 0x 1000 Ox1 3fc read oli 29 4 17 Event Time Stamp directory bank 2 0x2000 0x2ffc read ONLY coooccnnocccnonccnonncnonccconanonanccnnnconanacinne 29 4 18 Event configuration registers 0x100000 0x200000 0x280000 0x300000 0x380000 30 4 18 Gate chaining ee read hk GT See a is 31 4 18 2 Averaging mode ci 31 4 183 EXTERNAL RANDOM CLOCK MODE A 32 418 4 Pasesiz a edi it 32 4 19 Threshold registers Ox 100004 0x200004 0x280004 0x300004 0x380004 ooooococcccocccconcccocnccnoncon 33 4 20 Trigger Flag Clear Counter register 0x10001C 0x20001C 0x28001C 0x3001C 0x38001C 34 4 21 No_Of_ Sample register 0x100024 0x200024 0x280024 0x300024 Os 28004 35 4 22 Trigger setup registers 0x100028 0x200028 0x280028 0x300028 0x380028 00oooocoooocococococococnnos 36 4 22 i PERO a a IO 37 Page 3 of 73 SIS Documentation SIS3300 SIS3301
65. rigger information ADC 5 and ADC 6 4 26 4 Bank1_ADC78 0x3801000 offset address _ Event Data End Address D16 D0 S O Cl CO EH O ol DY CO O el A AL Al al al QA QA el a 2188 ere rere ee 0x0 T T 0O WO End Address 1 of Event 0 7 8 Oxffc T T 10 W O End Address 1 of Event 1023 7 8 W wrap around bit T7 T8 trigger information ADC 7 and ADC 8 4 27 Event directories bank 2 0x202000 0x202ffc 0x282000 0x282ffc 0x302000 0x302ffc 0x382000 0x382ffc define SIS3300_EVENT_DIRECTORY_BANK2_ADC12 0x202000 define SIS3300_EVENT_DIRECTORY_BANK2_ADC34 0x282000 define SIS3300_EVENT_DIRECTORY_BANK2_ADC56 0x302000 define SIS3300_EVENT_DIRECTORY_BANK2_ADC78 0x382000 read only D32 BLT32 size 0x1000 Same as above but for bank 2 Page 43 of 73 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME 4 28 Bank 1 address counter 0x200008 0x280008 0x300008 0x380008 define SIS3300_BANK1_ADDR_CNT_ADC12 0x200008 read only D32 define SIS3300_BANK1_ADDR_CNT_ADC34 0x280008 read only D32 define SIS3300_BANK1_ADDR_CNT_ADC56 0x300008 read only D32 define SIS3300_BANK1_ADDR_CNT_ADC78 0x380008 read only D32 These read only registers hold the current bank 1 address counter for ADC group 1 2 3 4 and bank The counter is 17 bit wide The counter will change
66. rite D32 read D32 BLT32 MBL64 2eVME size 0x80000 Bank memory is divided into 4 channel groups of 128 KSamples each i e 512 KByte deep for every channel group 2MByte in total The 32 bit wide memory locations hold the data of 2 ADCs each Readout can be done with D32 BLT32 MBLT64 or 2eVME for memory tests D32 write cycles only are supported Notes e FIFO block transfer cycles i e readout from a constant VME address in block transfer are supported from every channel group internal 17 bit address counter A18 to A2 e 2eVME cycles have to start on a 0x100 boundary 0x0 0x100 0x200 Data format for SIS3300 offset address ADC 1 3 5 7 ADC 2 4 6 8 D31 D30 29 D28 D27 16 D15 D14 13 D12 D11 0 0x0 U 00 OR bit 12 bit data G 00 OR bit 12 bit data Ox7fffc U 00 OR bit 12 bit data G 00 OR bit 12 bit data Data format for SIS3301 offset address ADC 1 3 5 7 ADC 2 4 6 8 D31 D30 D29 16 D15 D14 D13 0 0x0 U OR bit 14 bit data G OR bit 14 bit data Ox7fffc U OR bit 14 bit data G OR bit 14 bit data Shorthand Explanation U status of user bit if enabled 0 otherwise OR out of range set with over or underflow 0 otherwise G set on the first sample in Gate Chaining Mode 0 otherwise 4 34 Bank 2 memory 0x600000 Ox7ffffc define SIS3300_MEMBASE_BANK2
67. se as illustrated below Pipelining between the actual analog input signal and the value stored to memory has to be taken into account Both bit 11 of the acquisition control register and bit 11 of the event configuration register have to be set to acquire data in external random clock mode External Clock TLO AAA E AA eeng Clock to Memory AAA i Ho 4 18 4 Page size The page event size is defined by the 3 page size bits as follows Page size Page size Page size Page size Number of divisions Bit 2 Bit 1 Bit 0 Events Bank 0 0 0 128 K Samples 1 0 0 1 16K Samples 8 0 1 0 4 K Samples 32 0 1 1 2 K Samples 64 1 0 0 1 K Samples 128 1 0 1 512 Samples 256 1 1 0 512 Samples 256 1 1 1 512 Samples 256 Page 32 of 73 SIS Documentation SIS3300 3301 SIS GmbH 65 100 MHz FADCs VME 4 19 Threshold registers 0x100004 0x200004 0x280004 0x300004 0x380004 define SIS3300_TRIGGER_THRESHOLD_ALL_ADC 0x100004 write only D32 This register is implemented on the base of the individual channel group The address 5153300_TRIGGER_THRESHOLD_ALL_ADC can be used to write the same value simultaneously to the registers of all channel groups define SIS3300_TRIGGER_THRESHOLD_ADC12 0x200004 read write D32 define SIS3300_TRIGGER_THRESHOLD_ADC34 0x280004 read write D32 define SIS3300_TRIGGER_THRESHOLD_ADC56
68. ster and fifo addresses are implemented to control the logic and readout the data via VME Start Compress Event Readout register R W Abort Stop Compress Event Readout register W Compress Event Readout Status register R Compress Event Readout Configuration register R W ADC Memory Input Fifo R Page 51 of 73 VME SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME Write to Start Compress Event Readout Selected ADC FPGA writes compressed data to ADC Memory Input Fifo if the Input Fifo is NOT Almost Full BUSY Flag 1 Requested number of data are written or Write to Abort Compress Event Readout If the Compress Event Readout statemachine is busy then it is not possible allowed to access read or write the ADC FPGAs Page 52 of 73 SIS Documentation SIS3300 3301 SIS GmbH i 65 100 MHz FADCs VME 6 1 Compress Event Readout register discription 6 1 1 Start Compress Event Readout register 0x50 read write define SIS3301_EVENT_READOUT_START_CMD 0x50 rd wr D32 A write to this register will start the Compress Event Readout statemachine If bit 32 is set then the Input Fifo is cleared at the beginning The Compress Event Readout statemachine reads the ADC Memory from the written start address and pushes the requested number of data to the ADC Memory Input Fifo The ADC Memory address will be increment inside
69. the programmed wrap page If the Input Fifo is almost full then logic waits until the fifo is read Bit 31 1 Reset ADC Memory Input FIFO at the beginning 30 20 Start Address Bank Select 19 Start Address ADC Select bit 2 18 Start Address ADC Select bit 1 17 Start Address ADC Select bit 0 16 Start Address ADC Memory address bit 16 15 Start Address ADC Memory address bit 15 0 Start Address ADC Memory address bit 0 The power up default value is 0 6 1 2 Stop Abort Compress Event Readout register 0x54 write define SIS3301_EVENT_READOUT_ABORT_CMD 0x54 write D32 A write to this register stops aborts the Compress Event Readout Statemachine Page 53 of 73 SIS Documentation SIS3300 SIS3301 SIS GmbH i 65 100 MHz FADC VME 6 1 3 Compress Event Readout Status register 0x54 read define SIS3301_EVENT_READOUT_STATUS 0x54 vead D32 Bit 31 Compress Event Readout Statemachine Busy Flag 30 0 26 0 25 Input fifo write pointer bit 9 16 Input fifo write pointer bit O 15 0 10 0 9 Input fifo read pointer bit 9 0 Input fifo read pointer bit 0 Page 54 of 73 SIS Documentation SIS3300 3301 SIS GmbH i 65 100 MHz FADCs VME 6 1 4 Compress Event Readout configuration register 0x100020 0x200020 0x280020 0x300020 0x380020
70. used as gate input in this mode The leading edge of the signal defines the start the stop condition is given by the trailing edge as illustrated below The width of the gate has to exceed 2 sample clocks Following steps are required to activate gate mode e enable front panel start stop logic set bit 8 of acquisition control register e enable front panel gate mode set bit 10 of acquisition control register ov Start LEMO Input 3 0 7 V ov Sampling LEMO Output 2 0 7 V Page 48 of 73 SIS Documentation SIS3300 3301 SIS GmbH i 65 100 MHz FADCs VME Note LEMO output 2 ready for stop reflects the phase in which the digitizer is sampling unless the signal was assigned to reflect the bank full pulse by setting bit 9 of the control register 5 3 Start logic summary The diagram below illustrates the implemented start conditions of the SIS3300 1 Autostart LEMO Start In P2 Sample In 2 VME Key Start Note Condition Register Comment I Bit 8 1 Acquisition Control Enable front panel start stop logic 2 Bit 9 1 Acquisition Control Enable P2 start stop logic 2 Bit 6 1 Acquisition Control Start delay enable 4 Bit 6 0 Acquisition Control No start delay Page 49 of 73 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME 5 4 Stop logic summary The diagram below illustrates the implemented stop conditions of the S
71. user specific adaptations Bit Function Reading 31 Module Id Bit 15 30 Module Id Bit 14 3 29 Module Id Bit 13 28 Module Id Bit 12 27 Module Id Bit 11 26 Module Id Bit 10 3 25 Module Id Bit 9 24 Module Id Bit 8 23 Module Id Bit 7 22 Module Id Bit 6 O 21 Module Id Bit 5 20 Module Id Bit 4 19 Module Id Bit 3 18 Module Id Bit 2 0 1 17 Module Id Bit 1 16 Module Id Bit 0 15 Major Revision Bit 7 14 Major Revision Bit 6 1 13 Major Revision Bit 5 12 Major Revision Bit 4 11 Major Revision Bit 3 10 Major Revision Bit 2 1 9 Major Revision Bit 1 8 Major Revision Bit 0 7 Minor Revision Bit 7 6 Minor Revision Bit 6 5 Minor Revision Bit 5 4 Minor Revision Bit 4 3 Minor Revision Bit 3 2 Minor Revision Bit 2 1 Minor Revision Bit 1 0 Minor Revision Bit 0 4 2 1 Major revision numbers Find below a table with major revision numbers used to date Major revision number Application user 0x01 to OxOF Generic designs 0x10 Amanda 0x11 Greta Page 19 of 73 SIS Documentation SIS3300 5153301 SIS GmbH 65 100 MHz FADC VME 4 3 Interrupt configuration register 0x8 define SIS3300_IRQ CONFIG 0x8 read write D32 This read write register controls the VME interrupt behaviour of the SIS3300 ADC Four interrupt sources are forese
72. while the ADC is sampling after the ADC was stopped the stop position can be retrieved in multi event mode it will have to be read from the event directory The address counter points to the next memory location that will be written to see Trigger event directory also The register is implemented on the channel group base but the information is redundant and in the standard readout case you will want to retrieve the information from one channel group only Bit 31 17 16 00 Function unused read back as O address counter The address counter is not in a defined state after power up or Key Reset Unused bits are not updated and may contain arbitrary data i e only the number of bits that corresponds to the selected page size will hold significant data example the lowest 7 bits are valid for a page size of 128 4 29 Bank 2 address counter 0x20000C 0x28000C 0x30000C 0x38000C define SIS3300_BANK2_ADDR_CNT_ADC12 0x20000C read only D32 define SIS3300_BANK2_ADDR_CNT_ADC34 0x28000C read only D32 define SIS3300_BANK2_ADDR_CNT_ADC56 0x30000C read only D32 define SIS3300_BANK2_ADDR_CNT_ADC78 0x38000C read only D32 Same as bank 1 address counters but for bank 2 of ADC groups 1 2 3 4 Page 44 of 73 SIS Documentation SIS3300 3301 SIS GmbH 65 100 MHz FADCs VME 4 30 Bank 1 event counter 0x200010 0x280010 0x300010 0x380010
73. word of a gate is marked with a 1 in the G ate bit in memory refer to the data format table in section 4 33 For up to 1024 events the information in the event directory is valid also For gate chaining mode you have to a enable multi event mode b enable gate chaining mode The deadtime between two gates is 8 clock ticks Note the page size bits 2 0 of the event configuration are ignored in gate chaining mode as the event size is defined by the gate length of the individual gate pulses which does not have to be constant 4 18 2 Averaging mode Averaging mode is implemented to improve the signal to noise ratio in lower speed digitization applications N consecutive samples are summed up in the FPGAs of the dual channel groups Averaging mode is activated by specifying a non zero value for bits 18 16 of the event configuration register s Average Bit 2 Average Bit 1 Average Bu OU averaged samples 0 0 0 1 no average 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 Page 31 of 73 SIS Documentation SIS3300 SIS3301 SIS GmbH 65 100 MHz FADC VME 4 18 3 EXTERNAL RANDOM CLOCK MODE This mode allows for sampling at arbitrary low and non symmetric external clock The digitizer is set up for internal clock and will strobe one datum to memory with the leading edge of the internal clock cycle that follows the leading edge of an external clock pul
74. written with the same value Use the address 5153300_NO_OF_SAMPLE_ALL_ADC to write to the registers of all channel groups simultaneously The No_of_Sample factor max 255 Oxff is defined by this register It is used in MULTIPEXER mode only Bit Function Default 31 Unused read 0 0 8 Unused read 0 0 7 No_Of_Sample bit 7 MSB 0 0 No_Of_Sample bit 0 LSB 0 The power up default value reads Ox 00000000 Note The value of these registers Clock Predivider No_of_Sample is copied autonomously to the 4 ADC groups As the register is write only the user will have to read back the value from one of the ADC groups in case read back functionality is desired Page 35 of 73 SIS Documentation SIS3300 SIS3301 SIS GmbH l 65 100 MHz FADC VME 4 22 Trigger setup registers 0x100028 0x200028 0x280028 0x300028 0x380028 define SIS3300_TRIGGER_SETUP_ALL_ADC 0x100028 write only D32 define SIS3300_TRIGGER_SETUP_ADC12 0x200028 read write D32 define SIS3300_TRIGGER_SETUP_ADC34 0x280028 read write D32 define SIS3300_TRIGGER_SETUP_ADC56 0x300028 read write D32 define SIS3300_TRIGGER_SETUP_ADC78 0x380028 read write D32 This bit register is implemented on the channel group the registe
75. x200018 0x280018 0x300018 0x380018 define SIS3300_ACTUAL_SAMPLE_VALUE_ADC12 0x200018 read only D32 define SIS3300_ACTUAL_SAMPLE_VALUE_ADC34 0x200018 read only D32 define SIS3300_ACTUAL_SAMPLE_VALUE_ADC56 0x200018 read only D32 define SIS3300_ACTUAL_SAMPLE_VALUE_ADC78 0x200018 read only D32 Read on the fly of the actual converted ADC values The registers are updated with every ADC clock unless a concurrent VME read access is pending The register contents is refreshed and can be read any time i e they are updated independent of the unarmed armed sampling state as long as a sampling clock is distributed on the ADC board internal clock or active clocking external clock For SIS3300 ADC1 3 5 7 ADC2 4 6 8 D31 29 D28 D27 16 D15 13 D12 D11 0 000 OR bit 12 bit data 000 OR bit 12 bit data For SIS3301 ADC1 3 5 7 ADC2 4 6 8 D31 D30 D29 16 D15 D14 D13 0 0 OR bit 14 bit data 0 OR bit 14 bit data OR Out of range set with over or underflow Page 46 of 73 SIS Documentation SIS3300 3301 SIS GmbH V 65 100 MHz FADCs VME 4 33 Bank 1 memory 0x400000 Ox5ffffc define SIS3300_MEMBASE_BANK1_ADC12 0x400000 define SIS3300_MEMBASE_BANK1_ADC34 0x480000 define SIS3300_MEMBASE_BANK1_ADC56 0x500000 define SIS3300_MEMBASE_BANK1_ADC78 0x580000 w

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