TB-6S-LX150T-IMG2 Hardware User Manual
Contents
1. Bpi OGF baumnicadipg 1 a Gable Figure 8 19 Write into the Device 7 Rev 1 02 TOKYO ELECTRON DEVICE LIMITED inreviunW 8 If the write operation into the Flash memory is successfully completed a message Program Succeeded will appear Est San Ehe Ba Operations dev x FER 1 Ella ns BOR deve Soon Bir SFE pu ACE File FADH Forman iMPACT ane ame eril oy Eran ak Hasipi e Deere PRR Formalar FPGA 1 s successfully PROGRESS END End Operar iti Elapsed time 662 E Consoles ILE Figure 8 20 Write into the Device 8 Rev 1 02 TOKYO ELECTRON DEVICE LIMITED inreviunW 9 The data written in the Flash memory device is used for FPGA configuration using Master SPI The FPGA configuration can be initiated either by turning on the power switch of the board2. 3 MEN ob ____ 17 ___ 3 _ 3 18 ___ 3 _ 3 GND aere 3 v 3 2 3 8 gt 23 1823 3 12 ob a 3 12 7 3 _taayp 26 _ LA27 N LA26 N A 32 esPVAUX 12 X 33 12 a ____ __ 35 _ 12 12 5 _ 2 9 1 02 TOKYO ELECTRON DEVICE LIMITED 35 Table 7 18 LPC2 CN4 Column amp Pin to FPGA Pin Assignment Pinno G H Pinno Bank No svREAMC 3 2 4PRSNT CL 3 3 D ob 4 3 5 3 _ 3 6 ian w 3 3 j awp 9 A6 1 03 40 aap 3 tt 3 3 ace __ __ 12 3 a LAON 13 ayp a2 3 _ 1 3 3 aH 1 2 45 3
3. T Z T USB uart PINHEADER FMC LPC2 Figure 7 4 FPGA Banks and Peripheral Devices Table 7 2 FPGA Banks and Corresponding Devices Bank Funcii Volt Selection an unction Selectable BankO FMC HPC CN5 3 3V 2 5V DDR3 DSW LEDjPSWUSB 15V Selectable Bank3 FMC LPC1 CN3 FMC_LPC2 CN4 3 3V 2 5V DDR3 Selectable voltage is initially 2 5V settings __ _ Selectable Bank2 FMC HPC CN5 BankO Bank2 3 at 1 JP3 2 12 Figure 7 5 Location of FPGA Bank Voltage Selection Rev 1 02 TOKYO ELECTRON DEVICE LIMITED 7 2 Oscillator The board provides following clock sources cx1048c CL20V8C 74 250M 200 000M 6701008 X emn R578 2 er xa MMCX Single Input M la 5 MMCX_P Input gt c gt lt C2 6 7 T TETEE al suem CE 1 Mum m zm 4 n HMCX Single Output CNS _ 569 CI Figure 7 6 Clock Sources CX_N Input E Imm EJ PLL Control FPGA DIPSW DIPSW AH27 Y22 Y23 AE25 AE26 Y24 BANK1 n LVDS 27 gt SEL SEL LVDS LVDS MGT101 CDCM61001 gt p B13 MGTREFCLKOP_101 IC35 i 13
4. a La2N 3 ev 39 b Ld 140 ___ 1202 GND Rev 1 02 TOKYO ELECTRON DEVICE LIMITED 32 inreviunW 1SCL SDA The board provides test points TP27 and TP28 with pullup resistors pad to enable communications with the LPC1 CN3 FPGA mezzanine TC LPCi SCL Lco TDO EB LL LPC1 SDA 3P3VAUX 22 SS TMs OPHAV TREE eu 4 1 D ATuF 1608 _ LPC1 Address 01 1 R451 10kohm 452 0 R453 N M R454 10kohm Figure 7 17 SDA SCL GA1 0 TDI TDO 2 GA 1 0 The board has the above circuit design for notification of an ID to the FRGA mezzanine card By default the value is set to 01 3 TDI TDO The board provides a loopback structure for communication from the FPGA mezzanine card By default this loopback function is not provided because the R448 resistor is not installed 4 2 PRSNT_M2C The board provides structure to output to the FPGA mezzanine card By default it is to open i VREF M2C GBTCLKO_M2c_P E Muir GBTCiKD M2C M How T GHD Figure 7 18 PG_C2M PRSNT_M2C_L Table 7 16 PG_C2M PRSNT_M2C L settings Level settings Signal E O PG 2 442 R443 PRSNT_M2C_L R440 R441 5 VREF_A_M2C The board provides a test pad TP26 t
5. 40 Table 7 21 UART 41 Table 7 22 Serial EEPROM 0 41 Table 7 23 42 Table 7 24 DIP Switch PIziASSIODEDIBEL _ _ ____ 43 Table 7 25 Push Button Switch Pin 44 Table 7 26 Pin Header 45 Table 6 1 iial a R 59 Rev 1 02 TOKYO ELECTRON DEVICE LIMITED inreviunW Introduction Thank you for purchasing TB 6S LX150T IMG2 board Before using the product be sure to carefully read this user manual and fully understand how to correctly use the product First read through this manual and then always keep it handy Observe the precautions listed below to prevent injuries to you or other personnel or damage to property e Before using the product read these safety precautions carefully to assure correct use e These precautions contain serious safety instructions that must be observed e After reading through this manual be sure to always keep it handy The following conventions are used to indicate the possibility of injury damage and classify precautions if the product is handled incorrectly Indicates the high possibility of serious injury or death if the product is handled Danger incorrectl
6. Figure 8 23 Changing Configuration Time Target for Configuration Time Configuration Rate 2MHz Configuration Time approx 17 seconds Configuration Rate 10MHz Configuration Time approx 6 seconds Rev 1 02 TOKYO ELECTRON DEVICE LIMITED 58 TB 6S LX150T IMG2 Hardware User Manual ag 8 4 Factory Switch and Jumpper Settings er T E TOKYO LIMI 2 E ARTN 19939795 5 im ms t 5 1 6 Y Og m quiH t 35883 m i tH Figure 8 24 positions Table 8 1 Initial settings 14 JA 12 __ FMC_LPC1 VADJ Power seting 25V 3 3V None re 467 12 1 2 Power seting 2 5V 3 3V None 69 12 FFMC HPC VADJ Power setting 2 5V 3 3V None _ Bold character is factory setting Setting of the two jumpers must the same position Rev 1 02 TOKYO ELECTRON DEVICE LIMITED inreviunW m TOKYO ELECTRON DEVICE PLD Solution Division URL http www inrevium jp eng x fpga board E mail psd support teldevice co jp HEAD Quarter Yokohama East Square 1 4 Kinko cho Kanagawa ku Yokohama City Kanagawa Japan 221 0056 TEL 81 45 443 4016 FAX 81 45 443 4058 Rev 1 02 TOKYO ELECTRON DEVICE LIMITED
7. 101 LVDS MMCX_P CN10 MMCX_N CN11 gt PS LDIBMGTREEQUKDP 123 C36 18 123 LVDS FMC LVDS gt LVDS MGT245 CLK Cleaner AJ13 MGTREFCLKOP 245 ICS810001 21 1C33 AKT3 MGTREFCLKON 245 MMCX IN CN9 e ICS8545 02 1C32 7 DIPSW LVCMOS33 LVDS d Ctrl MGT267 SS 18 267 267 E 12 amp N6SLVDS250 _ cM REM 24 2 MMCX_OUT CN8 CO X2 200MHz LVDS 17 2 AK17 BANK2 MMCX_P CN6 LVDS P AH16 BANK2 MMCXCNCNS AK16 BANK2 x1 CDCLVD2102 74 25 2 Lvcmos33 25V M LVDS N p WA BANK3 X P OSC LVCMOS33 25V C16 BANKO LVDS N gt 16 CDCLVD2102 B15 BANKO 15 E16 BANKO D16 BANKO AC16 BANK2 i N AEG BANK H15 BANKO G15 BANKO 4 V3 BANK3 AA1 BANK3 2 AB1 BANK3 Figure 7 7 Clock Distribution Diagram Rev 1 02 TOKYO ELECTRON DEVICE LIMITED inreviunW Table 7 3 Details of On board Oscillator CLK74 25M P N LVDS W5 W4 Single ended to differential signal buffer x1 CLK200M P N LVDS AJ17 AK17 DDR3 IDelay clock X3 CLK_OPTION_P N LVDS C16 A16 Single ended to differential signal buffer CN6 7 _ LVDS AH16 AK16
8. 27 MGTRXPO 245 10 i4 MGTRXNO 245 DP4M2CN 15 GND 1 16 XDP6 MC P AG20 MGTRXPO 267 1 t7 DP6 MAC N MGTRXNO 267 MGTRXP 245 12 05 i8 J MGTRXN1 245 AH12 DP5 M2CN 19 ______ __ __ rl Low p 101 DP1 came 22 101 DP1C2MN 23 02 12 2 25 123 B21 DP2C2MP __ MGTTXNO 123 A21 2 277 12 28 22 123 B23 30 MGTTXN1 123 23 31 1 DP7C2MP 267 1 33 PT MGTTXN1 267 camp 34 MGTTXNO 245 0 4 5 36 DP6 CAMP 21 267 931 06 267 245 DP5C2MP 38 cow ewoo to RESON 1 GBTCLK1 M2C P n can be assigned to reference clock of 4 MGT tiles by IC37 For more details please refer to 7 3 3 reference clock selector Rev 1 02 TOKYO ELECTRON DEVICE LIMITED
9. BH g a a om a sqm 1 aT ii E a Figure 6 2 Hole positions Rev 1 02 TOKYO ELECTRON DEVICE LIMITED inreviunW 7 Description of Components 7 1 Power Supply Structure Option Option Option FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA Board Board Board AUX IO GTP1 GTP2 amp 0083 1 amp DDR3 2 amp DDR3 3 DDR3 Core Power Monitor LED 12 2 5 14 0 3 3V 4 0A 3 3V 3 5A 2 5 2 1 2V 1 5A 1 2 0 75 0 75VA 0A 0 75V 1 0A 1 5V 3 5A 1 2V 1 26V 8 0A AVAGO 4 5A HSMH C191 x13 Power Monitor LED 1874201 TPS74201 TPS51200 QSMR C13F x1 bias E bias Vref Vref Vref TI TI TPS54425 TPS54425 TPS54425 315 315 315 pm BAO Power Switch DC JACK nikkai CUI Inc MS 12AAB1 12V PJ 002AH 11 13V Voltage USB Supervisors FPGA FPGA FPGA FPGA Power AUX 10 DDR3 Core 3 USB Mini B Connector TUSB3410 vios HIROSE 32V 25V 15 12V 126V IE UX60 MB 5ST VCC 85232 5 RX TXIRTSICTS TPS386000 Y RESET Figure 7 1 Power Supply Structure Power Input Power is supplied through the AC adaptor AC Adapter Input m a DC 12V IN TE Y T 24265 Figure 7 2 Structure of the AC adapter input power connection Rev 1 02 TOKYO ELECTRON DEVICE LIMITED
10. Formi Faght check ko Add Devica IT AG cham Proceipes esie ni PROM File Formater Single FPGA Writing file mca Writing file Writing file ci mmmpie Urtitied czi lt Wenn 2 the Douncdisryo ran chan Cable Me Figure 8 13 Writing into the Device 1 Rev 1 02 TOKYO ELECTRON DEVICE LIMITED inreviunW 2 Abit jed file configuration window will appear Cancel it Select an FPGA and right click to select Add SPI BPI Flash Honandary dp E Gperstionn Lig E ARE X 9 ROT m 9 A Caer ia 42 1 Accent c Cen Deos k Cet Searhces Sete ACE Creme File Fie Forma Cond pue ard enin Fas Sel Programming Prosperi Sar rage Launch File Wird Sat MPACT bad m oF USE Agere Set cP USE ab Resje LGE Doni
11. Figure 7 15 2 2 5 2 Table 7 13 2 PRSNT_M2C settings Level settings Rev 1 02 TOKYO ELECTRON DEVICE LIMITED 29 inreviunW 6 Power Supply The board provides a 12V output to the 12POV pin and a 3 3V output to the 3P3V and 3P3VAUX pins 3 3V and 2 5V output are also selectable for VADJ pins as shown in the following circuit diagram The target FPGA pins are E39 F40 G39 and H40 The VADJ voltage supply is set by jumping across the identical pins on jumpers and JP9 The power status can be monitored by the adjacent LED Caution Do not jumper more than two portions of JP8 and Always jumper the same pins of both JP8 and 9 LED23 8529 104 Yellow OP425V DP 43 3V JPA JPI 100 iin gl 1 a 4 3 Figure 7 16 VADJ 7 VREF A M2C VREF M2C The VREF A M2C terminal of the H1 pin can be monitored by TP36 and the VREF B M2C terminal of the K1 pin by TP34 8 VIO B M2C The VIO B M2C terminal of each J39 and K40 pin can be monitored by TP35 Rev 1 02 TOKYO ELECTRON DEVICE LIMITED 30 7 4 2 LPC Low Pin Count LPC1 The FMC low pin count connector connects the following number of signals Low Speed LA 34 pair 68 single end and 2 clocks FPGA IO Bank3 cannot output LVDS signals It is a limitation of the FPGA Table 7 14 CN3 Column 8 D
12. LATOP 15 NC TT ef c3 ES p 558 55 I e gt fal m iii o T LAA 1 GND Connector LPO Connector Figure 7 13 VITA 57 Standard Low Pin Count Connector LPO Connector 1 02 TOKYO ELECTRON DEVICE LIMITED 2 7 4 1 HPC High Pin Count The FMC high pin count connector connects the following number of signals to the FPGA High Speed 8 ch TX 8 ch RX and 2 clocks Low Speed LA 34 pair 68 single end and 2 clocks 24 pair 48 single end and 2 clocks common of HA HB HB 22 pair 44 single end Table 7 8 HPC Column A amp B Pin to FPGA Pin Assignment BakNo PnN a 8B Pino Banno 12 13 MGTRXP 101 012 2 MGTRXN1 101 ON 3 12 4 J y 12 5 Domen 123 020 DP2 CP 6 MGTRXNO 123 20 DP2M2CN 7 12 12 2 123 022 __ MGTRXN1 123 cz2 DP3 11 _ 1 12 DP7M2CP AG22 267 _ wen
13. external clock IC32 FB CLEANUP CLKP N Or HPC CLK M101 P N B13 A13 CN5 HPC GBTCLKO M2C P N HPC CLK M245 P N AJ13 AK13 Or HPC CLK M123 P N LVDS D18 C18 MGT reference clock CN5 HPC_GBTCLK1_M2C_P N HPC_CLK_M267_P N AG18 AH18 or IC36 PLL MMCX CLKP N FMC HPC CN5 HPC CLKO M2C P N LVDS B15 A15 HPC LA interface clock FMC HPC CN5 HPC CLK1 M2C P N LVDS E16 D16 HPC LA interface clock FMC HPC CN5 HPC CLK2 M2C P N LVDS AC16 AD16 HPC HA HB interface clock FMC HPC CN5 HPC CLK3 M2C P N LVDS AF16 AG16 HPC HA HB interface clock Supplementary explanation CLK M2C P N LPC M2C P N be used for single end signal Rev 1 02 TOKYO ELECTRON DEVICE LIMITED 7 3 reference clock DIPSW DIPSW SW6 SW7 X5 LVDS 27MHz SEL SEL CDCM61001 EXPE me wee 101 IC35 gt 101 BIDS MMCX_N CN11 1 CDCLVD1204 LVDS MGT123 D18 MGTREFCLKOP 123 PLUMMCX CLK C36 C18 MGTREFCLKON_123 LVDS FB_CLEANUP_CLKPIN FMC ps gt HPC CLK Cleaner LVDS MGT245 AJI3 MGTREFCLKOP 245 ICS810001 21 133 AKT3 MGTREFCLKON 245 MMCX_IN CN9 cuo DIPSW LVCMOS33 LVDS mis NL BEEN Mcr ICS8545 02 1C32 AH18 267 CDCLVC1102 SN6SLVDS250
14. 1 2 16 tAMP 6 3 GND AF6 3 men wi _ 20 3 w 1 0 won 2 ime 12 123 mony 3 3 AD azp 3 am LAZN _ 25 3 _ _____ __ GND 26 3 3 7 3 acs 1 5 _ 28 3 oD 29 3 3 2 iP 30 3 ak LAN 31 L28P 3 E 32 ___3 1 31 3 ACA 34 LA30P a5 3 35 3 3 ve asp 6 3 LA3N _ 37 La2P 3 12 ta2N 3 9 1 02 TOKYO ELECTRON DEVICE LIMITED 36 inreviunW 1SCL SDA The board provides test points TP30 and TP31 with pullup resistors pad to enable communications with the mezzanine card man q x SCL 9 LPC2 spa 77 OP43 3V 333 D ATuF 1608 LECZ Address 10 T 0 R475 N M R476 10kohm 1 R477 10kohm R478 N M Figure 7 20 SDA SCL GA1 0 TDI TDO 2 GA 1 0 The board has the above circuit design for notification of an ID to the FPGA
15. 24 7 4 2 LPC Low Pirn Count LPG sues 31 7 4 3 LPC Low Pin Count EPA used 35 7 9 DOR 39 7 6 E 41 7 7 I 42 7 8 DIR 43 7 9 OO 44 7 10 PIN amp 45 TW Wg 46 t t 47 8 1 Creating a Configuration 47 8 2 Writing a Configuration File into the Flash 52 8 3 GT hE TNR 58 8 4 Factory Switch and Jumpper Settings 59 Rev 1 02 TOKYO ELECTRON DEVICE LIMITED inreviunW List of Figures FIGURE 4 1 Block EDT m 10 Figure 5 1 component 11 Figure 5 2 S0Ider SIGG TITRE 11 Figure 6 1 TB 6S LX150T IMG2 board 5 nnn 12 Fig re 6 2 13 Figure 7 1 Power Supply 14 Figure 7 2 Structure of the AC adapter input power connection 14 Figure 7 4 FPGA Banks and Peripheral Devices 16 meique de 0 8 16 EN T m MEN 17 Figure 7 7 Clock Dist
16. OUTPUT CHANNEL 1 OUTPUT CHANNEL 2 OUTPUT CHANNEL 3 OUTPUT CHANNEL 4 510 511 12 520 521 27122 530 531 3Y 3Z 540 540 4 42 OFF OFF 1A 1B OFF OFF 1A 1B OFF OFF OFF OFF 1A 1B For example Selecting CLEANUP CLKP N to M123 245 P N GBTCLKO M2C P N to M101 267 P N Rev 1 02 TOKYO ELECTRON DEVICE LIMITED inreviunW 7 4 Connector Interface The board provides 3 Samtec FMC connectors High Pin Count 1 CN5 Low Pin Count 2 Figure 7 12 and Figure 7 13 show the VITA 57 High Pin Count and Low Pin Count pinouts respectively Notice Not all pins of the HPC and LPC connectors are connected to the FPGA uM J H G F E D Fr GND MCN Sa Le LPG Connector LPG Connactar LPC Connector LPG Connector Figure 7 12 VITA 57 Standard High Pin Count Connector H D 1 A NC MG pe i6 T NC 565 one o 1 6 1 19 NF GE gt NG NC GND Lesr eH 12 NC So __
17. PROM File Formatter WebTalk Data iMPACT Processes O Fx No automatically saved previous project to load Console Errors Figure 8 2 iMPACT Window 1 TOKYO ELECTRON DEVICE LIMITED Rev 1 02 inreviunW 3 Choose SPI Flash Configure Single FPGA and then click the right pointing arrow PROM File Formatter Step Select Storage Target otep 2 Add Storage Device s Step d Enter Data pu i 1 jeneral File Value Storage Device Type Target FPGA Spartan3E 1 al Flash PROM LM Checksum Fill 27 Storage Device thitst 5126 value Sparban3AM ru File Name E SPI Flash Add Storage De vice Remove Storage Device ESSE ame Untitled Configure Single FPGA 2 Output n zm Configure MultiBaat FPGA rLA1S0T IMGiverzitara config Flash is Configure Single FPGA Configure Multibook FPGA Flash PROM File Property Value Configure From Paralleled PROMs T Eis Format Generic Parallel PROM Use Power of 2 For Start Addr Number of Bitstream 2 Bitstream D Start Address Bitstream 1 Start Address 675840 add Non Configuration Data Files es Number of Data File Auto Select PROM Description Ifyou are targeting any 3rd party supplied SPI PROM select this storage dewice type Figure
18. Table 7 4 PLL MMCX_CLK_P N 20 Table 7 5 Clock Generator CDCM61001RHBT IC settings 20 Table 7 6 Clock Generator ICS810001DK 21LF IC settings 21 Table 7 7 MGT reference clock settings 22 Table 7 8 HPC Column A amp B Pin to FPGA Pin 24 Table 7 9 HPC Column C amp D Pin to FPGA Pin 25 Table 7 10 HPC Column E 8 F Pin to FPGA Pin 26 Table 7 11 HPC Column G amp Pin to FPGA Pin 27 Table 7 12 Column J amp Pin to FPGA Pin 28 Table 7 13 2 2 5 29 Table 7 14 LPC1 CN3 Column amp D Pin to FPGA Pin 31 Table 7 15 LPC1 CN3 Column amp pin Pin to FPGA Pin assignment 32 Table 7 16 C2M PRSNT 2 33 Table 7 17 2 4 Column amp D to FPGA Pin 35 Table 7 18 LPC2 4 Column G 4 H Pin to FPGA Pin 36 Table 7 19 C2M PRSNT 2 37 Table 7 20 DDR3 SDRAM
19. 8 3 IMPACT Window 2 4 On Storage Device bits select 64M and then click Add Storage Device PROM File Formatter step f Select Storage Target Siep 27 Add Storage Device s Step 9 Enter Data i Heneral File Value Storage Device Type Beane 55 2 value Wilinx Flash PROM Checksum Fill E E Non Volatile FPGA Add Storage Device 256K gum De vice Value Spartan 3AM 157 2K EEUU SPI Flash Output File Mame Untitled Configure Single FPGA 2 Output File mul Configure MultiBoot FPGA bee El BPI Flash Configure Single FPGA Fake PUEDE EOE Flash PROM File Property Value Configure From Paralleled PROMs 128 Se BIN Generic Parallel PROM Power of 2 for Stark Addr Number of Bitstream 2 Bitstream Start Address 0 Bitstream 1 Start Address 675840 Ladd Non Configuration Data Files Nes Humber of Data File Auto Select PROM ee Description In this step you will select the appropriate target device Storage De wice This selection allows you to choose the specific device memory density you are targeting Add Storage Dewice After selecting the memory target use this button to add the to the target Storage Device list below Remove Storage Device Use this button to delete the targe
20. inreviunW Power Status LED The board provides 13 LEDs to signal the correct operational status of each voltage rail Table 7 1 Power status LEDs Voltage Description Power for 2 1 62 5V Red ___ Power forFPGAVCCINT Red LED4 Power for FPGAVREF DDR3 Red LEDS PowerforFPGAVCCIO Red LED6 PowerfeFPGAVCCIO Red LED Power for FPGAVREF ODR3 Red OP 25v _ PowerforFMC _________ Red 09 ___ Power for MGTAVCCTIAVIT Red MG075 LED10 PowerferFPGAVREFDDRG Red Leon PowerferMGTAVCCHAVTI2 Red LEDiS PowerfeFPGAVCCIO Red 1 AM i ASL 061 CT dO 5 f prer a oer ae i h Lo 02 Figure 7 3 Power status LED Rev 1 02 TOKYO ELECTRON DEVICE LIMITED TB 6S LX150T IMG2 Hardware User Manual inrevium a FPGA Bank Voltage Selection Various peripheral devices are connected to FPGA as shown in following figure The FMC connectors allow the developers to select an appropriate FPGA Bank voltage VCCIO by setting the onboard jumpers JP1 2 and 3 to meet the voltage requirements 3 3V or 2 5V for the connected interfaces FMC LPC1 CN3 DDR3 DDR3 LO 2 LED O
21. product may be damaged B Disclaimer This product 15 an evaluation board for Xilinx FPGA Tokyo Electron Device Limited assumes no responsibility for any damages resulting from the use of this product for purposes other than those stated Even if the product is used properly Tokyo Electron Device Limited assumes no responsibility for any damages caused by 1 Earthquake thunder natural disaster or fire resulting from the use beyond our responsibility acts by a third party or other accidents the customer s willful or accidental misuse or use under other abnormal conditions 2 Secondary impact arising from use of this product or its unusable state business interruption or others 3 Use of this product against the instructions given in this manual 4 Malfunctions due to connection to other devices Tokyo Electron Device Limited assumes no responsibility or liability for 1 Erasure or corruption of data arising from use of this product 2 Any consequences or other abnormalities arising from use of this product or 3 Damage of this product not due to our responsibility or failure due to modification This product has been developed by assuming its use for research testing or evaluation is not authorized for use in any system or application that requires high reliability Repair of this product is carried out by replacing it on a chargeable basis not repairing the faulty devices However non chargeabl
22. to specify the base ofthe file to which your PROM data will be written Output File Location This slows you to specify the directory in which the file named sbowe will be created s File Format PROM can be generated in any number of industry standard formats Depending on the PROM format your PROM programmer uses you output MCS SC or BIN file MGS is the most popular IS is used when targeting programming flows that utilize IEEE Std 1522 Third Party socket based programmers usually accept any ofthe listed Figure 8 5 iMPACT Window 4 6 Click OK Add Device Start adding device file to 1 Revision 0 Figure 8 6 IMPACT Window 5 Rev 1 02 TOKYO ELECTRON DEVICE LIMITED 7 Select a bit file to create a configuration file Add Device Loki Gp eamle e sample mcs Recent Documents Documents Computer My Network Fie sample mes Files of type Figure 8 7 iMPACT Window 6 8 Click No Add Device Would vou like to add another device file to Revision 0 7 9 Click OK You have completed the device file entry 1 7 Glick Ok to continue Figure 8 9 iMPACT Window 8 Rev 1 02 TOKYO ELECTRON DEVICE LIMITED TB 6S LX150T IMG2 Hardware User Manual inrevium a 10 Double click Generate File P ISE iMPACT M 63c PROM File Formatter SPI Flash Single FPGA E
23. 50 Figure 51 Figure 8 11 IMPACT Window 10 51 Figure 8 12 Onboard JTAG 52 Figure 8 13 Writing into the Device 1 52 Figure 6 14 Writing into the Device 2 erret bes osea eoe o3 Figure 8 15 Writing into the Device 3 o3 Figure 8 16 Writing into the 4 54 Figure 8 17 Writing into the DEVICE D 54 Figure 8 18 Writing into the Device 6 55 Figure 8 19 Write into the Device 7 55 Figure 8 20 Write into the Device 8 56 Figur 9 21 SWIEDQTI usos caus sacs 57 Figure 6 22 Contguratlob Status sss a a Ea 57 Figure 8 23 Changing Configuration Time nennen nennen 58 59 Rev 1 02 TOKYO ELECTRON DEVICE LIMITED inreviunW List of Tables Table 7 1 Power status LEDS em 15 Table 7 2 FPGA Banks and Corresponding 16 Table 7 3 Details of On board 18
24. AH24 BANK2 OUT CN8 Figure 7 8 MGT reference clock structure 7 3 1 PLL MMCX CLK P N PLL MMCX P N is input clock for SN65LVDS250DBT This is selected MMCX P N CN10 11 or a clock generator IC35 CDCM61001RHBT by clock selector IC36 CDCLVD1204RGT and SW 6 DIP SW The clock generator IC35 uses 27MHz OSC X5 for its master clock X5 235 IC36 PLL MMCX_CLK_P gt p t SN65LVDS250DBT XIN OUTP OUTN MMCX_P CN10 PR 1 0 MMCX en OD 2 0 IRSTN XC6SLX150T F GG900 3 3 CDCLVD1204RGT GND CDCM61001RHBT Figure 7 9 PLL MMCX P N structure Rev 1 02 TOKYO ELECTRON DEVICE LIMITED Table 7 4 P N setting Selected clock OFF MMCX ON PLL Clock ON PLL Clock 7 3 1 1 Clock Generator CDCM61001RHBT This board uses a low jitter clock generator TI CDCM61001RHBT For more detail settings please refer to the data sheet of CDCM61001RHBT The output frequency and reset of clock generator is controlled by FPGA It has 27MHz OSC for XIN Table 7 5 Clock Generator CDCM61001RHBT IC settings PR 1 AE26 oetting for pre scaler divider and feedback divider AE25 PRO _ vw RSTN Reset from FPGA 0811 0 01 fixed Y23 OD 1 Setting for output divider 24 Calculation for frequency of clock output Fout Prescaler Divider Output Divider
25. C 181 910 1 4 l 7 i 2 GNG pis LEDT V TRH xr DTOIAZK LEDJA Reea 12V 0 T p 4 ME GND 7 ELIE TR32 Mur DTO 137K CHD E e e uz Figure 7 25 LED Table 7 23 LED pin assignment Device FPGA LED1 LED2 LED3 LED4 LEDS LED6 LED7 LED8 Name LED26 LED27 LED28 LED29 LED30 LED31 LED32 LED33 Rev 1 02 TOKYO ELECTRON DEVICE LIMITED inreviunW 7 8 DIP Switch The board provides a 10 pole DIP switch When a DIP switch is set to the ON side it generates a high input to the associated FPGA pin Figure 7 26 DIP Switch Diagram and Location Table 7 24 DIP Switch Pin Assignment Signal Name Pin no __ Pa oswa Pa Rev 1 02 TOKYO ELECTRON DEVICE LIMITED inreviunW 7 9 Push Button Switches The board provides 4 push button switches When a switch is depressed it generates a high input to the associated FPGA pin Pania WS 835 3012 2 510 E k Pea 286 TWIT B33N 3012 8354 3012 ___ EE 2012 2 ND PLP ORO 0 14 Figure 7 27 Push Button Switch Table 7 25 Push Button Switch Pin Assignment SW10 PSW2 AK28 SW11 PSW3 U24 12 4 1 02 TOKYO ELECTR
26. File Edit View Operations Output Debug Window Help 2 2 7 2 iMPACT Flows 22 Boundary Scan SystemACE Create PROM File PROM File Formatter WebTalk Data 0 0000 0000 nac xcBslx150t sample bit iMPACT Processes Available Operations are mb Generate File HS 14 7 0x007F FFFF PROM File Formatter SPI Flash Single FPGA 9 File Location C sample Auto Select false Number of Revisions 1 Number of PROMs 1 PROM Name PROM Size 8388608 hits END of Report 1 Loading file C sample sample bit j INFO iMPACT Elapsed time 2 sec done 3 INFO iMPACT 501 1 Added Device xc6slxi50t successfully one device 406881 lt Console Errors Warnings PROM File Generation Tareet SPI Flash 33 761 696 Bits used File sample in Location CXsample Figure 8 10 iMPACT Window 9 11 If the configuration file has been successfully created a message PROM File Generation Succeeded will appear ISE iMPACT M 63c PROM File Formatter SPI Flash Single FPGA ue File Edit View Operations Output Debug Window Help IMPACT Flows 28 Boundary Scan 0 0000 0000 SystemACE Create PROM File PROM File Formatter WebTalk Data F4 16 22 sample bit xcBslx150t sample bit iMPACT Processes Available Operations are Gene
27. For example Generate 135MHz clock output Conditions Input clock is 27 2 2025 PR 1 0 OFF ON Prescaler Divider 5 Feedback Divider 15 OD 2 0 OFF ON OFF Output Divider 3 Rev 1 02 TOKYO ELECTRON DEVICE LIMITED 7 3 2 CLKP N FB CLEANUP CLKP N is differential input clock signal the SN65LVDS250DBT This differential signal is converted from single ended to differential by IC32 The single ended clock is generated by the IDT video clock generator ICS810001DK 21LF IC16 C31 MMCX CN8 32 to SN65LVDS250DBT FPGA Buffer IC33 FB CLEANUP CLKP FB CLEANUP CLKN Buffer XC6SLX150T FGG900 CDCLVC1102PW MMCX CN9 ICS8545AG 02LF V 3 0 SEL MF N 1 0 1 0 IN DONE OUT ICS810001DK 21LF GND Figure 7 10 FB CLEANUP CLKP N structure 7 3 2 1 Clock Generator ICS810001DK 21LF The board provides an onboard video clock generation circuit using the IDT ICS810001DK 21LF For details about setting clock frequencies refer to the corresponding IDT data sheet This device accepts a clock sourced from the FPGA AH24 pin or from an external MMCX connector CN9 The clock source selection is made via DIP switch SW5 The user selects the output clock frequency generated by this IDT video clock generator PLL DIP switch SW5 The XTAL IN is connected a 27MHz oscillator A reset to this device occurs du
28. HC 49U S SMD 241 256 XR2A 0811 N PinHeader 14 pin Samtec TSM 114 01 L DV Push Switch x4 omron B3SN 3012 Dip Switch 10 poles omron A6S 0104 H LED x8 AVAGO HSMD C191 Figure 4 1 Block Diagram Rev 1 02 TOKYO ELECTRON DEVICE LIMITED 5 External view of board Clock Clock Cleanup MMCX Single FMC_LPC1 Connector Generator Selector Clock In Out Low Pin Option OSC 2 ______ HABE JAPAN 7 Texas Instruments MMOX Differential Input Flash Memory Differential Power Input LVDS 4x4 DDR3 SDRAM CROSSPOINT SWITCH T FPGA E En SW 4 El 4 DDR3 SDRAM onnector ME vl X S Pin XILIN ce i 2 1 200 SPARTANY JM adii 74 25 Power LED USB USB RESET SW FMC_LPC2 Connector Dip SW LED JTAG Push SW Pin Header CLK RESET SW Low Pin Figure 5 1 component side 1012015 417 2P2002 01 Figure 5 2 Solder side Rev 1 02 TOKYO ELECTRON DEVICE LIMITED inreviunW 6 Board Specifications External Dimensions W 240 00mm x H 175 00mm Number of Layers 12 layers Board Thickness 1 6mm Material FR 4 FPGA Xilinx XC6SLX150T 3F GG900 PROM ST Micro M25P64 VMF6P FMC Connector High Pin oamtec ASP 134486 01 FMC Connector Low Pin Samtec ASP 134603 01 DDR2 SDRAM Micron M
29. N 25 17000 _ 0 ap 0 o J LA24 N 2 _ 0 121 0 LN _ 31 __ ob 32 0 32 9 GND 0 LAMN 1406 ob 35 ___ _ 0 F4 asp 36 __ 0 224 La3N 3 X ta2P Ese 38 D5 9 GND Lew 40 O Rev 1 02 TOKYO ELECTRON DEVICE LIMITED Table 7 12 HPC Column J amp K Pin to FPGA Pin Assignment Bank No _ en 1 vvREBMC 002 2 ame mcp 2 2 2 men 3 GND 4 acie 2 5 2 cn 1 w2 2 8 vo 2 9 AMB 2 ABIB 2 _ 2 2 2 E 20 4 23 _____ 25 27 44 AF9 28 oya 2 __ 29 AMA 2 30 31 BEBE _ p AF11 ob 55 2 ADM 36 ___ _____ 2 37 __ 14 pd 39 J 1 to 1 02 TOKYO ELECTRON DEVICE LIMITED 28 inreviunW 1GBTCLKO M2C Thi
30. ON DEVICE LIMITED 44 inreviunW 7 10 Pin Header The board provides a 14 header connector CN12 8 pins are connected to the FPGA Interface level is 1 5V Figure 7 28 PinHeader Table 7 26 Pin Header pin assignment MH NENNEN 1 02 TOKYO ELECTRON DEVICE LIMITED inreviunW 7 11 Battery A Battery socket is not mounted on the solder side of the board at location CN2 Battery power is connected to VBATT AB26 of FPGA Please use CR1220 size battery GND GND Coin Battery CR1220 Figure 7 29 Battery Rev 1 02 TOKYO ELECTRON DEVICE LIMITED 8 8 1 Creating Configuration File This section describes how to create a configuration file using Xilinx ISE software version 12 2 Create a configuration file to write into the Flash memory 1 Double click Generate Target PROM ACE File Processes Hw Design Summary Reports Desien Utilities User Constraints Hi EIE Ee MQ Place amp Route Generate Programming File d Configure Target Device A Manage Configuration Project iMPACT Design Using Chipscope Figure 8 1 Creating a Configuration File with ISE 12 2 2 Double click Create PROM File ISE iMPACT M 63c File Edit View Operations Output Debug Window Help Gal Boundary Scan SystemACE I3 Create PROM File
31. Pin to FPGA Pin assignment Pinno c Dp Pin No Bank No _ b 1 recm ppocame 2 3 4 D 5 ppomece 6 mac NN 7 GND D 8 twePCC D 9 ance _ asp to enD 14 aop b a d s oD FM 14 1 co _0 em taon 15 Laon D GND NENNEN _ ob tz w 0 LAMP 1 181 LAN A7 LAN 719 GND D 20 b 21 cn _ Hr 22 n cz 23 tase F8 o NEM GND GND 1 _ 2 tee ev o azn 27 D7 J J 9 _ sc 9 sa a 32 eseVAX NEN GND TMS 4 sev 35 b 36 2 sov 7 2 8 o 9 NEN 40 63P3V Rev 1 02 TOKYO ELECTRON DEVICE LIMITED Table 7 15 LPC1 CN3 Column amp pin Pin t
32. T reference clock structure Rev 1 02 TOKYO ELECTRON DEVICE LIMITED 25 Table 7 10 HPC Column 4 Pin to FPGA Pin Assignment BankNo F Bank No _ 1 A ___2 A 3 EE 7141 wre o 5 02202 1 02 TOKYO ELECTRON DEVICE LIMITED 26 inreviunW Table 7 11 HPC Column G amp H Pin to FPGA Pin Assignment BakNo G H Bank _ 12 en 1 vvRFAMC 0o __ 2 0 3 J _________ oD 4 B5 5 0 6 0 221 taooNcc 7 ob ian Fo 0o asp 9 0 aon __ to tw4P 62 0 11 22 0 aop 12 b J y 0 LA8N 13 tayP F3 o 12 14 223 _ __ 1 2 s 0 16 _ 0 mep 8 0 aen 19 ob __ 0o 0 113 aon 22 1496 B5 23 a5 0 azp 2 b J 0 LA
33. T41J64M16LA 15E MMOCXConnector oamtec MMCX J P H ST TH1 i o pes 77 T animas 1 i a 4 E a 1 ih 4 T m m 8 of IM ua ar H g TELLE T 4 m ouo a 4 E F E EU ee TESS V T ub Ours Wm 2 a eee BEN TE 097 g i M TITITIMI u 87 IN um Ed o L DS dris Loma o ri 4 P T E F F Figure 6 1 TB 6S LX150T IMG2 board dimensions Rev 1 02 TOKYO ELECTRON DEVICE LIMITED inreviunW 5 m m m m A B T a i EE in a 8 LU EVE a i m m p t poo tt mU S spe gt J Hi wm in F i F is z 4 g m ai sE S i wr d Ms 1 1 11 do
34. and ZIO is N C Rev 1 02 TOKYO ELECTRON DEVICE LIMITED 7 6 USB UART The board provides a MiniUSB B Type interface connector CN13 as a means to communicate between a computer terminal emulator using the USB RS232C conversion device IC40 for bidirectional UART based communication and the FPGA JP10 enables the SCL pin of the USB RS232C conversion device s associated EEPROM 5 13 is the reset push button 1 40 IC16 40 7 72 SHIFTER ICTS SN74AVC2T45DCUR IC38 12 00 147 SHIFTER IRTS USB_DM USB SN74AVC2T45DCUR CONNECTOR USB RS232C USB_DP XC6SLX150T FGG900 OO Q 213 UX60 MB 5ST EEPROM SW13 _ tT TUSB3410RHB GND Figure 7 24 USB UART Table 7 21 UART pin assignment Table 7 22 Serial EEPROM SCL Rev 1 02 TOKYO ELECTRON DEVICE LIMITED 7 7 LED The board provides 8 onboard LEDs These LEDs will light when the corresponding FPGA output pin is driven high LED25 Rea 12 toys HSMD C 181 910 1 1 xm 2 LEDI TRIS WE DTDiiizK LEDZT U101MW 2 t a TR26 DTO 1327K LEDs RB7D 12 LED3 R573 12 HSMO CTSF 910 14 TE 4 ED TRI DTD1i3zK LEDs Rava HW 91D 1MW IU 1 BEN GND gt TR 132K LED32 Reve 12 HSMD
35. ce Tl CX104BC CDCM61001RHBT Burer CDCLVD1204RGT Connector Samtec MMCX J P H ST TH1 Dip Switch poles omron Connector 2101 Samtec MMCX J P H ST TH1 Dip Switch poles omron A6H 4101 XTAL 27MHz Dip Switch poles TamaDevice omron HC 49 U A6H 8101 Connector CLK CLEANER Samtec IDT MMCX J P H ST TH1 1 58100010 211 Push Switch omron B3SN 3012 Clock Buffer MMCX Connector TH Samtec CDCLVC1102PW MMCX J P H ST TH1 inreviun ADR CLK CMD DDR3 SDRAM 1Gbit Data 0 15 DQS DM Micron MT41J64M16LA 15E ADR CLK CMD DDR3 SDRAM 1Gbit Data 0 15 DQS DM Micron MT41J64M16LA 15E ADR CLK CMD DDR3 SDRAM 1Gbit Data 0 15 DQS DM Micron MT41J64M16LA 15E Connector Samtec MMCX J P H ST TH1 pair MMCX Connector Samtec OSC 200MHz MMCX J P H ST TH1 TamaDevice pair CL20VBC LVDS BUFFER OSC 74 25MHz lt TamaDevice pair CDCLVD2102RGT CX104BC LVDS BUFFER Option OSC FPGA a TI omron p pair CDCLVD2102RGT XR2A 0811 N Xilinx Level Shifter SPI FLASH Spartan 6 1 STMicroelectronics SN74AVC41774 M25P64 VMF6P XC6SLX1 50T JTAG Connector 3FFG900 molex 87831 1420 Push Switch omron B3SN 3012 Level shifter USB Serial IC USB Connector TI x2 TI HIROSE SN74LVC2T45 TUSB3410RHB UX60 MB 5ST EEPROM IC Socket MICROCHIP omron Resonator 12MHz TamaDevice
36. ct on unstable locations Otherwise it may drop or fall resulting in injury to persons or failure If the product is dropped or damaged do not use it as is Otherwise a fire or electric shock may occur Do not touch the product with a metallic object Otherwise a fire or electric shock may occur Do not place the product in dusty or humid locations or where water may splash Otherwise a fire or electric shock may occur Do not get the product wet or touch it with a wet hand Otherwise the product may break down or it may cause a fire smoking or electric shock Do not touch a connector on the product gold plated portion Otherwise the surface of a connector may be contaminated with sweat or skin oil resulting in contact failure of a connector or it may cause a malfunction fire or electric shock due to static electricity TOKYO ELECTRON DEVICE LIMITED inreviunW N Caution Do not use or place the product in the following locations Humid and dusty locations Airless locations such as closet or bookshelf Locations which receive oily smoke or steam Locations exposed to direct sunlight Locations close to heating equipment Closed inside of a car where the temperature becomes high otaticky locations Locations close to water or chemicals Otherwise a fire electric shock accident or deformation may occur due to a short circuit or heat generation Do not place heavy things on the product Otherwise the
37. e CFI file is present in the same directory the FROM file GE Peqenecate the PEOM fils with the latest moftware Console LETTER T Cable UGH B G Figure 8 17 Writing into the Device 5 Rev 1 02 TOKYO ELECTRON DEVICE LIMITED inreviunW 6 Click OK 4 Programming Frome tins Device 1 Programming Propert hes category __ Dey FPA Property Levee ee Verily General GPLD PROM Properties rece Before Programming Att Gable INIT during programming Alter peoaerammgg Flash Figure 8 18 Writing into the Device 6 7 The write operation into the Flash memory will start Heundany Sean 5 mg D File Pih File E Available Operations are up me Verily Frese mi Check mi Cheer Device 22258 ocean Fle Single TP Sn B s SEI core pst detecked core will downlomded to the device operat fide bi apap teases
38. e replacement is offered for initial failure if such notification is received within two weeks after delivery of the product The specification of this product is subject to change without prior notice The product is subject to discontinuation without prior notice Rev 1 02 TOKYO ELECTRON DEVICE LIMITED inreviunW 1 Related Documents and Accessories Related documents All documents and reference designs relating to this board are available only for purchasing customers and can be downloaded from our website at Tokyo Electron Device Ltd TED SUPPORT WEB http ppg teldevice co jp eng index htm Mounting parts 7 x rubber foots 14 x X 6mm screws and 7 x X 10mm spacers Accessories Option board spacer set 6 x M2 6 X 10mm spacers Duracon and 12 screws with Duracon washers cable set 2 x MMCX SMA cables Samtec 174 035 1 015 1 0400 2 cables Samtec RF174 03SP1 03SP1 0400 AC adaptor 1 x AC adaptor Akizuki Denshi LTE GFP 451DA 1238 or equivalents 2 Overview The TB 6S LX150T IMG2 DDR3 8 channel GTP and Xilinx 6 evaluation board forms base for numerous Spartan 6 development platforms including the Consumer Video Kit 2 0 3 Feature XC6SLX150T 3FG900 FPGA 1x 57 standard FPGA Mezzanine Card FMC High Pin Count HPC connector 2x FMC Low Pin Count LPC connectors Due to limitations on the number of FPGA pins all defined FMC standard sig
39. inreviunW TB 6S LX150T IMG2 Hardware User Manual Rev 1 02 TOKYO ELECTRON DEVICE LIMITED inreviunW Revision History Rev 1 00 2011 01 20 Initial Release 1 01 2011 02 17 Modified register number of TDI TDO connection of FMC Yoshioka Modified configuration LED numbers Rev1 02 2011 03 15 Brash up all of sections Rev 1 02 TOKYO ELECTRON DEVICE LIMITED inreviunW Table of contents 1 Related Documents and 9 EMO ATCP RR 9 ONE 9 ee eB 10 9 Extemal Vew Hoard 11 6 Board 5 12 1 Description of 61868 14 7 1 Power Supply 14 7 2 21195 UU 17 7 3 reference nnne nasa rasa ratas ese 19 1 021 P N 19 7 3 1 1 Clock 61001 20 1 3 2 FB CLEANUP M 21 7 3 2 1 Clock 58100010 211 21 73 9 MGT reference clock 22 7 4 gt 23 7 4 1 lale uei M
40. inreviunW Table 7 9 HPC Column C amp D Pin to FPGA Pin Assignment BakNo PinN c D Bank No 12 1 secem y O MerrPo 101 B9 2 y 101 3 4 E NENNEN 5 2 2 _ MGTRxPO 101 Dio 6 MGTRXNO 101 cto Do MON 7 212 impeo E9 0o 0 0 m asn 11 aop 12 2 o pot o0 ms 14 tw9P 0o 0 imon 15 12 6 12 17 ___ 0 m LA4P s __ 0o m 19 20 ___ C O 2 NENNEN _____ 21 __ k5 18 P E us ler 1427 26 1 6 ma 0 LA27 N 27 LA26 N GND 28 GND O o 12 6 12 7 2 8 12 esev 9 1 40 _ 2 GBTCLKO M2C P n can be assigned to reference clock of 4 MGT tiles by IC37 For more details please refer to Figure 7 8 MG
41. mezzanine card By default the value is set to 10 3 TDI TDO The board provides a loopback structure for communication from FPGA mezzanine card By default this loopback function is not provided because the R472 resistor is not installed 4 2 PRSNT_M2C The board provides a structure to output to the FPGA mezzanine card By default it is to open Opa3 3V OPe33V 0P43 3V VREF A M2C GND MT GAD Figure 7 21 C2M PRSNT 2 L Table 7 19 2 PRSNT_M2C Settings Signal UH Lo PG C2M R466 R467 PRSNT M2C R464 R465 5 VREF A M2C The board provides a test pad TP29 to monitor the H1 pin VREF 2 of the connector Rev 1 02 TOKYO ELECTRON DEVICE LIMITED inreviunW 6 Power Supply The board provides a 12V output to the 12POV pin and a 3 3V output to the 3P3V and 3P3VAUX pins 3 3V and 2 5V output are also selectable for VADJ pins as shown in the following circuit diagram The LPC2 VADJ voltage supply is set by jumping across identical pins on jumpers JP6 and JP7 The power status can be monitored by the adjacent LED Caution Do not jumper more than two portions of JP6 and JP7 Always jumper the same portion of JP6 and JP7 LPC2 VADJ HSMY C181 10d Yellow TRIS LPC Figure 7 22 VADJ Rev 1 02 TOKYO ELECTRON DEVICE LIMITED 38 inreviunW 7 5 DDR3 SDRAM The b
42. nals are not connected For more information refer to the Connector Pinout Tables in this manual on pages 24 31 and 35 DDR3 SDRAM Chip Micron MT41J64M16LA 15E or equivalent 1 Gbits 800Mbps 4x4LVDS crosspoint switch Clocks see Figure 7 7 Clock Distribution Diagram Multiple onboard clock sources 200 MHz 27 MHz 74 25 MHz User populated clock chip in 8 pin dip External clock sources via single ended and differential MMCX connections with clock cleaners PLLclock generator programmable from the FPGA gt MMCX clock output gt switch selectable MGT clock source selection Push button switches dip switches and pin headers LEDs USB connection to PC via USB UART conversion device for character based terminal O 128 Mbit SPI Flash configuration ROM JI TPS 386000 Voltage Supervisor Rev 1 02 TOKYO ELECTRON DEVICE LIMITED TB 6S LX150T IMG2 Hardware User Manual 4 Block Diagram TB 6S LX150T IMG2 FMC LPC1 low pin count Samtec ASP 134603 01 GC 2 34 pair low pin count Samtec ASP 134603 01 GC 2 pair IO 34 pair Differential signal is Input only 4 pair IO 16 pair LA CLK 2 pair IO 34 pair HA 2 10 24 pair 10 22 pair high pin count Samtec ASP 134486 01 LVDS 4x4 CROSSPOINT SWITCH SN65LVDS250DBT Dip Switche poles omron 8101 OSC 27MHz Clock Generator TamaDevi
43. o FPGA Pin assignment H Bank No 1 5 0 5 2 __ Gt 3 ob 4 3 5 3 0 Fre riwoPcc 6 __ 0 6 7 1802 us 3 oD a 3 0 sve 9 0 H8 10 1 uw 3 __ 3 0 t2 aop 27 0 2 aon 13 3 4 3 0 1 2 15 0 m 3 __ 17 3 0 mep 8 0 A6 imen 19 3 1 ob msy B 3 3 v2 mop 21 3 vi iaon 2 __ 3 23 v6 3 3 R azp 2 O 3 rRe 23 iip 7 3 e 3 3 B 27 3 ian 29 iP N 3 29 3 3 P tage 3 P3 agn 3 3 ob Jz asn N 3 3 P2 33 3 Pi iain 34 180 R 3 5 3 3 T2 asp 6 3 Ti asn 3 ta2P u 3 NENNEN NENNEN NENNEN
44. o monitor the 1 pin 2 of the FMC connector Rev 1 02 TOKYO ELECTRON DEVICE LIMITED 33 inreviunW 6 Power Supply The board provides a 12V output to the 12POV pin and a 3 3V output to the 3P3V and 3P3VAUX pins 3 3V and 2 5V output are also selectable for VADJ pins as shown in the following circuit diagram The LPC1 VADJ voltage supply is set by jumping across the identical pins on jumpers JP4 and JP5 The power status can be monitored by the adjacent LED Caution Do not jumper more than two portions of JP4 and JP5 Always jumper the same portion of JP4 and JP5 LPC1 VADJ LED17 R455 HSMY C181 100 5 OPr3 JV Figure 7 19 VADJ Rev 1 02 TOKYO ELECTRON DEVICE LIMITED 7 4 3 LPC Low Pin Count LPC2 The FMC low pin count connector connects the following number of signals Low Speed LA 34 pair 68 single end and 2 clocks FPGA IO Bank3 cannot output LVDS signals It is a limitation of FPGA Table 7 17 LPC2 CN4 Column amp D Pin to FPGA Pin Assignment BankNo Pnn Pinno Bank No 1 recm p came 27 3 NENNEN GND ec 5 6 __ GND a Domen 7 GND 1 01 a 3 8 NENNEN 3 3 LSE acs 3 ___ 83
45. oard provides three independent 1 Gbit Micron DDR3 SDRAMs MT41J64M16LA 15E The following pins are connected A 12 0 DQU 7 0 DQL 7 0 ODT 2050 DQSU DQSL DQSL DMU DML CK CK CKE RAS CAS WE BA 2 0 RESET CS is hardwired low A 14 A 13 are memory address expansion bits The board addresses 1 Gb using A 12 0 Specifications 1Gbit 8Mword x 16bit x 8bank 1066 7 7 7 Please refer to the Micron data sheet Address Structure Bank 3bit Address 13bit Row address 13bit Column address 10bit Data Bus Structure Each byte data strobe with write and read DQS Each byte data mask DM T LM gl 0 APT OMG Sa 987 321 1 lt lt ue 4 I 2165 5 987 321 1027 Figure 7 23 DDR3 SDRAM Rev 1 02 TOKYO ELECTRON DEVICE LIMITED Table 7 20 DDR3 SDRAM assignment DDR3 Bank1 Bank4 Bank5 DDR3 Bank1 Bank4 Bank5 Pin Name 27 1 28 23 Pin EZE EZE pave m Ux Dui Apso 128 acm Loos Notice Please refer to Xilinx answer record 34055 Spartan 6 FPGA MCB What are the requirements RZQ and ZIO pins for information on how to use the peculiar signals RZQ ZIO of the Memory Controller Block MCB The default setting of RZQ is 100 Ohm pull down
46. ol Requrter Ced Deve Sata PROM Fite Formatter SPI Flagh Loren edaome PROGRESS End Gpee at Poni E lapsed time 4 Platform able 8 Meis Figure 8 14 Writing into the Device 2 3 Select a configuration file xxx mcs to write into the Flash memory Add Device DIN ME Fie name sample mes Places Files of type an Files Figure 8 15 Writing into the Device 3 Rev 1 02 TOKYO ELECTRON DEVICE LIMITED inreviunW 4 Select the onboard Flash M25P64 and click OK Select Attached SPL BPI Select the PROM attached ta FPGA PROM Data Width Figure 8 16 Writing into the Device 4 5 On the iMPACT Processes window double click Program IMPACT EMITE EA Wn iMPACT F x i 2 AES device do select 42 Boundary Scan BM uM us n Create PROM File PROM File Forma Urocerpe Operating me Disi Ohak Eb Bete Diet PROH fie Foemattec Flach Single c Dande Canis ote IHFO iHPACT CFI file is nor deregcred ensure amp cCoErecr Safe OORT igure LOB Please make sur
47. or holding down the reconfiguration switch SW2 for more than two seconds see Figure 8 21 below w m e cum k uu oc NAME Figure 8 21 Reconfiguration Switch 10 The board provides two LEDs 15 and 16 for configuration status monitoring see Figure 8 21 below Green LED15 indicates that the configuration process has been successfully completed Red LED16 indicates that the configuration process is in progress or failed 2016 1 LEDISHDONE LED _ Input 2 Figure 8 22 Configuration Status Rev 1 02 TOKYO ELECTRON DEVICE LIMITED inreviunW 8 3 Configuration Time Time required to load configuration data into the Flash memory device can be changed by setting the configuration clock on ISE Tool Due to the operational frequency of SPI Flash select 16MHz or below Method 1 Right click Generate Programming File 2 Choose Process Properties 3 Choose Configuration Options 4 Change the Value of Configuration Rate Configuration Clock Frequency MHz Setting Processes Process Properties Configuration Options x Design Summary Reports Constraints m I 56 263 H Implement Design ds Startup Options M H Gontieure Target Device Buspend Wake Options e Update Bitstream with Processor JTAG Pin TS Unused Pins UserID Code 8 Digit Hexadeci
48. rate File 5913 7 Generate Succeeded 0x007F FFFF E PROM File Formatter SPI Flash Single FPGA amp Console done Aj INFO iMPACT 501 1 Added Device xc6slxi5 0t successfully i idd one device 4068511NFO iMPACT Current time 9 22 16 26 26 2Total configuration bit size 33761696 Total configuration byte size 4220212 bytes 0 406534 4220212 bytes loaded up from Using user specified prom size of 8192 Writing file C sample sample mes Writing file C sample sample prm Writing file C sample sample cfi 010 lt Console Errors EN Warnings PROM File Generation Target SPI Flash 33 761 696 Bits used File sample in Location CXsample Figure 8 11 iMPACT Window 10 Rev 1 02 TOKYO ELECTRON DEVICE LIMITED inreviunW 8 2 Writing a Configuration File into the Flash Memory Connect a Platform USB cable to the JTAG connector CN3 as shown in Figure 8 13 After powering on the board start the ISE iMPACT applicaton and write a configuration file into the Flash memory by following the procedure described below Figure 8 12 Onboard JTAG Connector 1 Double click Boundary Scan and then click Initialize Chain shown by the arrow P GE PACT Houndary Scan Yew Gun Debug or k i P FT mag iMPACT D 8X 2 Dean moa zo Drest E Create PROM File PRIH
49. ribution 17 Figure 7 9 PLL MMCX P N 2 1 19 Figure 7 10 CLEANUP CLKP N nnne nennen 21 Figure 7 13 VITA 57 Standard Low Pin Count Connector 23 Figure 7 12 SDA SCL putent oho itu uu es 29 Figure 7 15 C2M PG _ 2 _ 2 _1 29 Figure 7 17 SDA SUL GAT O TDILTI DU crei etas nep 33 Figure 7 18 C2M PRSNT 2 1 33 Figure 7 20 SDA SCL GA1 0 37 Figure 7 21 PG C2M PRSNT 2 1 37 FOUE DORS SDRAM 39 42 Figure 8 1 Creating a Configuration File with ISE 122 47 Figure 8 2 iMPACT VV ING OW 47 FIGURE G 48 Figure 8 4 IMPACT Window 3 48 Figure 8 5 IMPACT Window 4 rna rna 49 FIgure 9 6 IMPACT VV ING OW D 49 Figure S IMPACT WINGOW G 50 Figure IMPAC T WINGOWN 50 ENE a REESE
50. ring power up or by pressing pushbutton SW3 Table 7 6 Clock Generator ICS810001DK 21LF IC settings E LLL Nes CLK SEL E E bit 1 Input clock selection bit 2 PLL coefficient bit 4 3 Frequency dividing value 00 4 0128 10 12 11 18 bit 6 5 Output clock generation block structure setting bit 7 Output clock enable ON Enable Output clock formula in nBP 1 0 211 ON ON Fout CLK P 0 0 1 02 TOKYO ELECTRON DEVICE LIMITED Example 148 5MHz output Condition Input clock 27MHz V 3 0 ALL OFF P 1000 M 1000 MF OFF x22 N 1 0 OFF OFF divide by 4 frequency 7 3 3 MGT reference clock selector reference clocks are selected by LVDS 4x4 crosspoint switch 1C37 SN65LVDS250DBT 4 clock sources are selected by SW7 FB_CLEANUP_CLKP FB_CLEANUP_CLKN HPC_CLK_M123_P from 1CS810001DK 21LF 123 M101 P M101 N to FPGA M245 P 245 N GBTCLKO_M2C_P from FMC_HPC CONNECTOR GBTCLKO M2C GBTCLK1_M2C_P GBTCLK1_M2C_N from FMC_HPC CONNECTOR PLL MMCX_CLK_P PLL MMCX_CLK_N HPC_CLK_M267_P from CDCLVD1204RGT HPC_CLK_M267_N 1 2 3 4 5 6 7 8 SN65LVDS250DBT Figure 7 11 MGT reference clock selector IC Table 7 7 MGT reference clock settings
51. s signal is used for reference clock of MGT 2 SCL SDA The board provides test points TP32 and TP33 with pullup resistors pad to enable EC communications with the FPGA mezzanine card 2 x ee an R510 4 Aa 2 gt spa SDA ERNAI GND TMS TRST L 12P DV GAJ PED GND PV Pass OP43 3V nan GND Lan ND 6236 C335 GND 3 0 47 uF i 1608 L47uF 1508 8515 GND ue HPC Address 00 0 R513 H M R514 10kohm 0 R515 N M 516 10 GND Figure 7 14 SDA SCL GA1 0 TDI TDO 3 GA 1 0 The board has the above circuit design for notification of an ID to the mezzanine card By default the value is set to 00 4TDI TDO The board provides a loopback structure for JTAG communication from the FPGA mezzanine card By default this loopback function is not provided because the R510 resistor is not installed 5 PG C2M PG M2C PRSNT M2C The board provides a structure to output to the FPGA mezzanine card It also provides similar structure for the column of F and H pins of the connector default it is set to open The PG M2C PRSNT 2 also has a similar structure PG GND GND GBTCLK P GBTCLKO GND
52. t device from the list below Select the device and click this button to remove it fram the list Auto Select PROM Ifyou select this option IMPACT will choose device density large enough to hold your specified data Figure 8 4 iMPACT Window 3 Rev 1 02 TOKYO ELECTRON DEVICE LIMITED inreviunW 5 Click the right pointing arrow Enter a name of directory and location in the Output File Name and Output File Location fields and then click OK PROM File Formatter Step Select Storage Target Siep 2 Add Storage Device s Step 3 Enter Data Storage Device Type Storage bits can ieneral File Detai Value Flash PROM Checksum Fill Non Volatile FPGA TETTE Value SPI Flash 64M Output File Mame sample Configure Single FPGA Output File Configure MultiBoot FPGA LER Flash Configure Single FPGA Configure MultiBoot FPGA Flash PROM File Property Configure From Paralleled PROMs File Format MCS Generic Parallel PROM Add Non Confiquratian Data Files Auto Select PROM Description In this step you will enter information to assist in setting up and generating a PROM file for the targeted storage dewice and mode s Checksum Fill When data is insufficient to fill the entire memory ofa PROM the walue specified here is used to calculate the checksum ofthe unused portions Output File This aiows you
53. y Indicates the possibility of serious injury or death if the product is handled Warning incorrectly Indicates the possibility of injury or physical damage in connection with houses or Caution household goods if the product is handled incorrectly The following graphical symbols are used to indicate and classify precautions in this manual Examples Turn off the power switch Do not disassemble the product Do not attempt this Rev 1 02 TOKYO ELECTRON DEVICE LIMITED TB 6S LX150T IMG2 Hardware User Manual inrevium a Rev 1 02 N Warning In the event of a failure disconnect the power supply If the product is used as is a fire or electric shock may occur Disconnect the power supply immediately and contact our sales personnel for repair If an unpleasant smell or smoking occurs disconnect the power supply If the product is used as is a fire or electric shock may occur Disconnect the power supply immediately After verifying that no smoking is observed contact our sales personnel for repair Do not disassemble repair or modify the product Otherwise a fire or electric shock may occur due to a short circuit or heat generation For inspection modification or repair contact our sales personnel Do not touch a cooling fan As a cooling fan rotates in high speed do not put your hand close to it Otherwise it may cause injury to persons Never touch a rotating cooling fan Do not place the produ
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