PCI-1750 32-channel Isolated Digital I/O Card User's Manual
Contents
1. Figure 3 4 Intemut source catrol Chapter 3 Function Description 17 Interrupt Group 1 Interrupt Group 0 o Disable interrupt o o Disable interrupt KENENNE CHINMEEENEN CHIEN 1 Ls see DIR A IDIE 0 Scuse bro DIA Table 3 2 Interrupt mode bit values Interrupt Triggering Edge Control The interrupt can be triggered by a rising edge or a falling ede of the interrupt signal as determined by the value in the triggering ede control bit in the interny control register as shown in Table 3 3 E0 or E1 Triggering edge of interrupt signal Table 3 3 Triggering edge contrd bit values Interrupt Flag Bit The iteng flag bit is a flag indicating the status of an intem It is a readable and writable bit Read the bit value to find the status of the intemrt write 1 to this bit to clear the intem This bit must be cleared in the ISR to service the next incoming interny FO amp F1 Interrupt status o mes o ponte Table 3 4 Item ut flaghbit values 18 PCI 1750 User s Manual APPENDIX Function of 8254 Counter Chip The Intel 8254 The PCI 1750 uses one Intel 8254 compatible programmable interval timer counter chip The popular 8254 offers three independent 16bit down counters Each counter has a clock input control gate and an output You can program each counter for maximum count values fran 2 to 65535 The 8254 has a maximum input clock frequency2. Address Decoder Interrupt Control Logic IDI 0 7 Isolation IDI 8 15 IDO 0 7 Isolation y 37 PIN M L D type m Ci t IDO 8 15 Connector le le x 8254 compatible Timer 10MHz Osc Timer N PII IRQ Timer1 Counter e ki Ro f Counter 2 4 Iso DI 15 Figure 2 2 Block Diagram PCI 1750 User s Manual Connector Pin Assignments j Do 4 o N ne mel o E IDI 1 IDI 6 4 o Greer DIS pig o IDI 7 p10 o 2 Fos D9 oj zero EP IDI 11 D14 8 o rpg PB IGND o 9 29 IDI 15 Counter2 com 10 o O og IND Doo U o o IGND pos eda 3394 221001 Dos Bio 31 1p03 Doe 4 o uc IDOS IDO 8 5 5 ns o 7 IDO 7 16 o L 34 Do9 IDO 10 O 35 17 O IDO 11 Ipo 14 418 o a IDO 13 come 9 a IDO 15 Description of pin use IDO 0 IDO 15 Isolated digital output pins IGD Isolated ground COM1 Camo pin for connecting inductive loads of isolated output channels IDO 0 IDO 7 COM2 Cammn pin for connecting inductive loads of isolated output channels IDO 8 IDO 15 Counter2 Inout pin of isolated counter shared with IDI 15 Warning Be careful when wiring digital input lines Never apply a negative voltage to the isolated input pins as this may
3. Figure 3 1 shows how to connect an external input source to one of the card s isolated ipt damels Warning Be careful when wiring digital inout cables Never apply a negative voltage to an isolated input pin as this may damage the PCI 1750 Note for wet ootacts A malfunction might occur in cases where the intemal resistance of a voltage source uncer wet amtacts is significant C5kW It is advisable to CITE a parallel 5 kW 0 5Wresistor to avoid a voltage rise inside the voltage source External Internal i ISO 5V i PO 5V i i Dry Contact Open High PNE i i Close Low ry Wet ExtGND Wet Contact 5 48Voc High Contact Contact i 0 2Voc Low Isolated Outputs Fach of 16 isolated digital output channels canes equipped with a Darlington transistor Every eight output channels share amm collectors and integral sugoressian dicces for inductive loads Channels 0 7 use COMI and channels 8 15 use COW as a common pin Chapter 3 Function Description 13 Note If an extemal voltage 5 48 V is applied to an isolated output channel IDO 0 IDO 15 while it is being used as an output channel the current will flow fran the extemal voltage source to the card Please take care that the current through each AD pin not exceed 200 mA Use the extended ground connector CN5 to shunt the current to the extemal voltage source ground Figu
4. Printed in Taiwan August 1998 Part No 2003175000 1st Edition Contents Chapter 1 General Information 1 TREVOSE LON nani 2 Chapter 2 Installation ccascssscestecsvecsctsscecsaccoaseseesss 5 Initial inspecLicn amp 2 ecco ee eoe eee Leere avi mae nonas ae a ere rase cn 6 Unpacking EC 6 location Of CODDECLOES idees eos ren anrea ka Vo euo CEU Roa PER nua ardua E 7 PCI 1750 Block Diagram e ee ee eee eee e eee eese eee esee oot 8 Connector Pin Assignments e eee ee eee ee eee ee ese sesso secus 9 Installation Instructions iie eee suceden veus ani ege durae proa d meae 10 Chapter 3 Qrati irradia 11 Operation C sess 12 Isolated Digital I O BOEES urinare 12 Timer and Counter siriaca 14 Interrupt FUNCLION 1c ce eene e eee ese cerea e eee e se eere zena zine zendte 16 Appendix A Function of 8254 Counter Chip 19 CHAPTER General Information Introduction The PCI 1750 offers 16 isolated digital input channels 16 isolated digital output channels one isolated counter and one timer with PCI bus interface With isolation protection of 2500 V the ECI 1750 is ideal for industrial applications where high voltage protectim is required The card s 16 bits are divided into two 8 bit I O ports This makes the PCI 1750 very easy to program This card also offers dual interrupt handling capability providing the user more fle
5. PCI 1750 32 channel Isolated Digital I O Card User s Manual Copyright This documentation and the software included with this product are copyrighted 1998 by Advantech Co Ltd All rights are reserved Advantech Co Itd reserves the right to make improvements in the products described in this manual at any time without notice No part of this manual may be reproduced copied translated or transmitted in any fom or by any means without the prior written permission of Advantech Co Ltd Informati provided in this manual is intended to be accurate and reliable However Advantech Co Itd assures no responsibility for its use nor for any infringe ments of the rights of third parties which may result fram its use Acknowledgments PC LabCard is a trademark of Advantech Co Ltd and PC are trademarks of International Business Machines Corporation MS DOS Windows Microsoft C and Quick BASIC are trademarks of Microsoft Corporation BASIC is a trademark of Dartmouth College Intel is a trademark of Intel Corporation TURBO C is a trademark of Borland Intemational CE notification The PCI 1750 developed by ADVANTECH CO LID has passed the CE test for environmental specifications when shielded cables are used for extemal wiring We recommend the use of shielded cables This kind of cable is available from Advantech Please omtact your local swplier for ordering infomatim
6. M2 Ml amp MO Select operating mode BCD M2 M1 MO Mode 0 0 0 0 programmable one shot 0 0 1 1 programmable one shot X 1 0 2 Rate generator X 1 1 3 Square wave rate generator 1 0 0 4 Software triggered strabe 1 0 1 5 Hardware triggered strobe Select binary or BD counting BCD Type 0 Binary counting 164its 1 Binary coded decimal BCD counting Appendix A Function of 8254 counter Chip 21 If you set the module for binary counting the count can be any number fram 0 up to 65535 If you set it for BCD Binary Coded Decimal counting the count can be any number fran 0 to 9999 If you set both SCI and SCO bits to 1 the counter omtrol register is in read back command mode The control register data format then becomes BASE 27 Dec 8254 control read back mode Bit D7 D6 D5 D4 D3 D2 D1 DO Value 1 1 CNT STA C2 CL CO X CNT 0 Latch count of selected counter s STA 0 Latch status of selected counter s C2 Cl amp CO Select counter for a reacthack operation C2 1 select Comter 2 Cl 1 select Counter 1 CO 1 select Conter 0 If you set both SCI and SCO to 1 and STA to 0 the register selected by C2 to CO omtains a byte which shows the status of the counter The data format of the counter read write register then becares BASE 24 25 26 Dec Status read back mode Bt D7 D6 D5 D4 D3 D2 D1 DO Value OUT NC RW1 RWO M2 M1 MO BCD OUT Current state of cou
7. for one period of the input clock The period fran one output pulse to the next equals the nmr of input counts in the counter register If you reload the counter register between output pulses the present period will nct be affected but the subsequent The gate input when low will force the output high When the gate input goes high the counter will start frm the initial count You can thus use the gate input to synchronize the counter With this mode the output will remain high until you load the count register You can also synchronize the output by software Appendix A Function of 8254 counter Chip 23 MODE 3 Square wave generator This mode is similar to Mode 2 except that the output will remain high until one half of the count has been ampleted for even num bers and will go low for the other half of the cont This is acoam lished by decreasing the counter by two cn the falling ecbe of each lock pulse When the counter reaches the terminal count the state of he output is changed the counter is reloaded with the full count and he whole process is repeated Q v cd ct H f the cant is odd ad the atat is high the first clock pulse after the count is loaded decrements the count by 1 Subsequent clock pulses decrement the count by 2 After timeout the output goes low and the full count is reloaded The first clock pulse following the reload decrements the counter b
8. cking materials for inspection by the carrier We will then make arrangements to repair or replace the unit Unpacking The PCI 1750 contains components that are sensitive and vulnerable to static electricity Discharge any static electricity cn your body to ground by touching the back of the system unit grounded metal before you touch the board Remove the PCI 1750 card from its protective packaging by grasping the rear panel Handle the card ally by its ecyes to avoid static discharge which could damage its integrated circuits Keep the antistatic package Whenever you remove the card fram the PC please store the card in this package for its protecticn You should also avoid contact with materials that hold static electrici ty such as plastic vinyl and styrofoam Check the product contents inside the packing There should be me card one CD ROM and this manual Make sure nothing is missing 6 PCI 1750 User s Manual Location of Connectors Figure 2 1 shows the names and locations of connectors on the board The PCI 1750 is a plug and play device The PCI BIOS assigns the system resources automatically at system start up ALL functions can be set by software No Jumpers or switches are used on this card CN5 CN6 Figure 2 1 Board connectors Chapter 2 Installation 7 PCI 1750 Block Diagram 8 PLX PCI 9050 Address Bus Data Bus
9. damage the PCI 1750 Chapter 2 Installation 9 Installation Instructions 10 The PCI 1750 can be installed in any PCI slot in the amputer How ev eycfer to the computer user s manual to avoid any mistakes and danger before you follow the installation procedure below 1 Tum off your computer and any accessories connected to the computer Warning TURN OFF your computer power supply whenever you install or remove any card or connect and disconnect cables 2 Disconnect the power cord and any other cables fram the back of the computer 3 Remove the cover of the ccmputer 4 Select an empty 5 VECI slot Remove the screw that secures the expansion slot cover to the system unit Save the screw to secure tre interface card retaining bracket 5 Carefully grasp the upper Q of the PCI 1750 Align the hole in the retaining bracket with the hole m the expansion slot and align the gold striped edge connector with the expansion slot socket Press the card into the socket gently but firmly Make sure the card fits the slot tidtly 6 Secure the PCI 1750 by screwing the mounting bracket to the back panel of omputer 7 Attach any accessories cable wiring terminal etc to the card 8 Replace the covercfyour computer Connect the cables you removed in step 2 9 Tum the computer power on PCI 1750 User s Manual CHAPTER Operation Operation This chapter describes the operation of the PCI 1750 Th
10. e driver software provided allows a user to access all of the card s functions without register level programming Please see the User s Manual for the driver bundled with this card for more information For users who prefer to implement their own bit level programming to drive the card s functions information useful for making such a program is included in this dager Isolated Digital I O Ports Introduction The PCI 1750 has 16 isolated digital inout channels designated JI 0 IDI 15 and 16 isolated digital output chanrels designated O 0 IDO 15 Data can be read from or written to the card s channels Interrupt function of the DIO signals Wo I O chamels IDI 0 and IDI 8 can be used to generate hard ware interrupts A user can program the interrupt amtrol register Base 32Dec to select the interrupt sources Refer to Section Interu Function for details about internyct control Power On Configuration The default configuration after power on hardware reset or software reset is to set all the isolated output charmels to low so that users reed not worry about damaging external devices during system start up or ES 12 PCI 1750 User s Manual Isolated Inputs Fach of 16 isolated digital input channels accacts dry omtacts or 5 48 V o voltage inputs All sixteen input channels share 3 ground pins and one extended ground terminal block CNS
11. eptable There are three types of counter cperation read load LSB read load MSB and read load LSB followed by MSB It is important that you make your read write operations in pairs and keep track of the byte acer Counter read back command The 8254 counter readkack comard lets you check the count value programmed mode and current states of the OUT pin and Null Count flag of the selected carter s You write this ommend to the control word register Format is as shown at the beginning of this sectian The reacHboack command can latch multiple counter output latches Simply set the ONT bit to 0 and select the desired counter s This single command is functionally equivalent to multiple counter latch commands one for each counter latched The readdoack camand can also latch status infomation for selected counter s by setting STA bit 0 The status must be latched to be read the status of a counter is accessed by a read from that counter The counter status format appears at the beginning of the chapter Appendix A Function of 8254 counter Chip 25 Counter latch operation Users often want to read the value of a counter without disturbing the count in progress You co this by latching the count value for the specific counter then reading the value The 8254 supports the counter latch operation in two ways The first way is to set bits RWl and RW to 0 This latches the count of the selec
12. ion voltage 2 500 Ve Throughput 10 KHz 16 Optically Isolated Outputs Output range Open collector 5 to 40 V e Sink Current 200 mA Max Isolation voltage 2 500 Ve Throughput 10 KHz One 16 bit Optically Isolated Counter Shares Pin with isolated inout 15 Throughput 1 MHz Max Isolation voltage 2 500 V e One 32 bit Timer 10 MHz internal clock source Chapter 1 General Information 3 Interrupt Source Isolated Inout 0 4 8 12 Carter and Tirer Dimensions 175 nm x 100 nm 6 9 x 3 9 Connectors One DB 37 female connector One 2 pin terminal block for extended ground Power consumption 5 V 850 mA Typical 5V 1 0A Maz Operating temperature 0 709 C 32 F 158 F Storage temperature 20 809 C 4 F 176 F Humidity 5 95 non condensing PCI 1750 User s Manual Installation CHAPTER Initial Inspection Before starting to install the PCI 1750 make sure there is ro visible damage on the card We carefully inspected the card both mechani cally and electrically before shipment It should he free of marks and in perfect order cn receipt As you unpack the PCI 1750 check it for signs of shipping damage damaged box scratches dents etc If it is dameged or fails to rest specification notify our service department or your local sales representative immediately Also call the carrier immediately and retain the shipping carton and pa
13. nter cutout NC Null oount is 1 when the last cant written to the canter register has been loaded into the counting element FCI 1750 User s Manual Counter operating modes MODE 0 Stop on terminal count The atot will be initially low after you set this mock of cgperatioan After you load the cant into the selected count register the output will remain low and the counter will count When the counter reaches the terminal count its output will go high and remain high until you reload it with the mode or a new count value The counter continues to decrement after it reaches the terminal count Rewriting a counter register during comting has the following results 1 Writing to the first byte stops the current outing 2 Writing to the second byte starts the new count MODE 1 Programmable one shot The output is initially high The output will go low on the cant following the rising ed of the gate input It will then co high an the terminal count If you load a new count value while the cutout is low the new value will not affect the duration of the me shot pulse until the sucoseding trigger You can read the current count at any time without affecting the one shot pulse The me shot is retriqgerable hus the output will remain low for the full count after any rising ed t the gate ipt amp ct MODE 2 Rate generator The output will be low
14. of 10 MHz The PCI 1750 provides 10 MHz input frequencies to the counter chip fran an arbosrd crystal oscillator On the PCI 1750 the 8254 chip s Timer 0 and Timer 1 are cascaded to be a 32 bit programmble timer Counter read write and control registers The 8254 progrenmable interval timer uses four registers at addresses BASE 24 Dec BASE 25 Dec BASE 26 Dec and BASE 27 Dec for read write and control of counter functions Register functions appear below Register Function BASE 24 Dec Counter 0 read write BASE 25 Dec Counter 1 read write BASE 26 Dec Counter 2 read write BASE 27 Dec Counter control word Since the 8254 counter uses a 16 bit structure each section of read write data is split into a least significant byte LS8 and most significant byte VSB To avoid errors it is important that you make read write qperations in pairs and keep track of the byte order The data fomat for the oontrol register appears below BASE 27 Dec 8254 control standard mode Bit D7 D6 D5 D4 D3 D2 D1 DO Value SC1 SCO RW1 RWO M2 M1 MO BCD 2 FCI 1750 User s Manual Description SC1 amp SCO Select counter Counter SCI SCO 0 0 0 1 0 2 1 0 Read back command 1 I RW1 amp RWO Select read write cperation Operation RW1 RWO Counter latch 0 0 Read write LSB 0 1 Read write MSB 1 0 Read write LSB first 1 1 then MSB
15. r Base 32 Dec The Interrupt Control Register Base 32 Dec controls the iteruc signal source edge and flay Able 3 1 shows the bit map of the interrupt contrdregister The regiter isa re a dable wr tabli register When writingtoit it is usdas a artrdregister and when reading frait it is ussdas a status register Interrupt Interrupt Group 1 Interrupt Group 0 ms or oe os oe 9 9 ov 99 Table 3 1 Interuct amtrdre gister bit map PCI 1750 User s Manual MOO and M01 tock bits of interrupt Group 0 M10 and M11 mob bits of interrupt Group 1 ED El triggering ed amtrol bits FO Fl flagbits Interrupt Source Control The rece bits written into the interrupt control register determine the alloweble sources of signal S generating an interrupt Bit 0 and bit 1 determine the interrupt source for interrupt group 0 and bit 4 and bit 5 determine the interrupt source for interrupt grap 1 as indicated in Figure 3 4 Table 3 2 shows the relationship between an interru source and the values in the moc bits M01 M00 a 00 IDIO gt 01 LL VCC 10 IDI4 11 i 5 A Timer 1 gt a n M wi CLK M11 M10 00 IDI8 gt gt 01 gt 10 IDI 12 gt 6 A 11 Counter 2 lt CINT A __
16. r timers is 10 MHz The output of both Timer 1 and Counter 2 can generate interrupts to the system refer to Section 3 3 The maximum and minimum timer interrupt frequency is 10 MHz 2x2 2 5 MHz and 10 MHz 65535 65535 0 002328 Hz respectively Chapter 3 Function Description 15 The gates of the canter timersare irterrally pulled to 45 Vkeeping the gate control always enabled Interrupt Function 16 Introduction Four input channels IDI 0 IDI 4 IDI 8 and IDI 12 and the output of Timer 1 and Counter 2 are connected to the interrupt circuitry The Interrupt Control Register of the PCI 1750 controls how the carbination of the six signals generates an interrupt Two interrupt request signals designated interrupt group 0 and interrupt group 1 can be generated at the same time and then the software can service these two request signals by ISR IDI 0 IDI 4 and Timer 1 are connected to interrupt port 0 IDI 8 IDI 12 and Courter 2 are am nected to interrupt port 1 The dal internt sources provide the card with more capability and flexibility IRQ Level The IRQ level is set automatically by the PCI plug and play BIOS and is saved in the PCI omtroller There is no need for users to set the FO level Only ore IR level is used by this card although it has two interruct sources Interrupt Control Registe
17. re 3 2 shows how to connect an extemal output load to the card s isolated cutouts Internal External Figure 3 2 Connecting an extemal output load Timer and Counter 14 Introduction The PCL 1750 includes one 8254 ompatible programmable timer counter chip which provides two 16 bit timers and one counter designated as Timer 0 Timer 1 and Counter 2 Timer 0 and Timer 1 are cascaded to be a 32 bit timer with its input omnected to a 10 Mz oscillator and its gate control pulled high enabled Counter 2 of the 8254 chip is a 16bit high speed 1 MHz isolated event counter it shares a pin with isolated IDI 15 The block diagram of the timer counter system of PCI 1750 is shown in Figure 3 3 PCI 1750 User s Manual Timers 0 and 1 are usually set in mock 3 Square wave generator to generate periodic watchdog interruots Counter 2 can be set in mode 0 stop on terminal count for measuring frequency or in mock 3 square wave generator to generate periodic watchdog interructs or to be used as an event counter For more details on the operating modes of the 8254 counter chip please refer to Appendix A CLK Timer 0 GATE lt TimeriRQ CLK Timer 1 GATE IDI 5 COUNTER lt Event counter IRQ OUT Cu Counter 2 GATE Figure 3 3 Block diagram of timer counter Timer Counter Frequency and Interrupt The input clock frequency of the counte
18. ted counter in a 16bit hold register The sod way is to perform a latch operation under the readback cammand Set bits SCI and SCO to 1 and CNT 0 The second method has the advantage of operating several counters at the sare time A subsequent read operation cn the selected counter will retrieve the latched value FCI 1750 User s Manual APPENDIX Register Format of PCI 1750 Register Format of PCI 1750 Decima Read Wie 2 23 Reserve ed Interrupt Status Interrupt Control 32 Register Register 28 PCI 1750 User s Manual
19. xibility in using the counter timer digital inputs or a ambinatim to generate interructs to the PC A user can easily configure the interrupts through software The PCI 1750 uses a PCI controller to interface the card to the PCI bus The controller fully implerents the PCI bus specification Rev 2 1 All bus relative omfigurations such as base addresses and interrupt assignments are autaratically omtrolled by software No junpers or DIP switches are required for user configuration Numbering Convention All mnbers given in this manual are in decimal format unless specifically noted otherwise In particular where a register address is given as Base 22 the decimal number 32 should be added to the base value Features 16 isolated digital input and 16 isolated digital output crarrels High voltage isolation on all channels 2500 V High sink current on isolated output channels 200 mA Channel D type 37 pin female connector Supports dry contact or 5 to 48 V e isolated ipt PCI 1750 User s Manual Dual interrupt handling capability Timer Counter interrupt capability generates watchdog timer internets Applications Digital I O crtrol Industrial ON OFF control Industrial and lab autaraticn Switch status sensing BCD interfacing Specifications 16 Optically Isolated Inputs Input range 5 to 48V or dry contact Isolat
20. y 3 Subsequent clock pulses decre ment the count by two until timeout then the whole process is repeated In this way if the count is odd the output will be high for NH1 2 counts and low for N 1 2 courts MODE 4 software triggered strobe After the mode is set the output will be high When the cant is loaded the counter will begin counting Cn terminal count the output will go low for one input clock period then go high again If you reload the count register during counting the new count will be loaded on the next CLK pulse The count will be inhibited while the GATE input is low MODE 5 Hardware triggered strobe The carter will start counting after the rising edge of the trigger input and will go low for one clock period when the terminal count is reached The carter is retrigoerable FCI 1750 User s Manual Counter operations Read write operation Before you write the initial count to each counter you must first specify the read write cperaticn type qoerating mode and counter type in the amtrol byte and write the amtrol byte to the omtrol register BASE 27 Dec Since the control byte register and all three carter read write registers have separate addresses and each control byte specifies the counter it applies to by X1 and SOO no instructions on the gperat ing sequence are required Any programing sequence following the 8254 convention is acc
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