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VM42/62 User's Manual

1. Available for Index 02 boards or later 1995 PEP Modular Computers Page 1 5 I O Ports Serial Mezzanine Interface Timers TICR General Purpose Watchdog Special Functions Real time clock backed up Serial EEPROM DMA Front Panel Functions Data Retention Short term backup for RTC and SRAM via on board Gold Cap Long term backup via VME 5V Stby line Power Requirements VM62 66 MHz VM62 50 MHz VM42 33 MHz 68040 VM42 25 MHz 3 3V 68040V Temperature Range Operating Humidity Board Size VMEbus Connector Front panel width Page 1 6 Chapter 1 Introduction VM62 A VM42 A User s Manual RISC controller in the 68EN360 with 14 dedicated DMA channels 4 multiprotocol SCCs up to 8 MBaud with one two supporting EEE 802 3 Ethernet up to 10 Mbit s 10Base5 10Base2 or 10BaseT 2 UARTSs RS232 XON XOFF RS232 up to 120 kBaud 4 independent baud rate generators CXC Interface 16 bit asyncronous data transfer with 4 IRQs independent DMA channel 3 serial interfaces Periodic Interrupt Timer programmable 4 16 bit or 2 32 bit programmable 512 ms time out for reset programmable Date year month week day Time hour minute second 1 kbit for board specific data serial number Internet address etc kbit for application purposes 2 independent channels supports single and dual address transfers between all offboard locations including DRAM FLASH AutoBahn memory CXC
2. Reserved 68EN360 internal RAM register 68EN360 s CS4 SRAM 68EN360 s CS5 CXC 68EN360 s CS6 RTC 68EN360 s CS7 1 VME IRQ MASK register 68EN360 s CS7 5 VME control status register 68EN360 s CS7 7 board control status register Reserved BERR_O Reserved BERR 0 Reserved BERR 0 Note In order to determine the base of the 68EN360 s internal memory map the module base address register MBAR must be set The location of this register is fixed in the address area Supervisor CPU Space at 3FF00H For more information please refer to the Software Configuration chapter in this manual Page 2 4 1995 PEP Modular Computers May 17 1996 VM62 A VM42 A User s Manual Chapter 2 Functional Description 2 2 6 DMA Transfers Memory to memory transfers with the 68EN360 DMAs are possible with any combination of on board and VME addresses In order to achieve address compatibility between CPU VME and DMA VME transfers it is recommended that the initialisation of CS2 be initialised to the standard VME address space as described in the Software Configuration chapter in this manual 2 3 VMEbus Interface The VM62 A VM42 A has a complete master interface for the P1 JI VMEbus connector It consists of a VMEbus arbiter requester system controller and buffers for data address control signals In addition the VM62 A VM42 A provides a VMEbus slave interface which consists of a programmable board address decoder a dua
3. 128Us timeout timer monitors VMEbus data transfer cycle lengths and generates a VMEbus BERR signal for error termination This timer is enabled disabled via the VME control status register which also supplies a timeout status bit in order to identify bus errors generated by the bus monitor 2 3 2 Dual Ported SRAM The VM62 A VM42 A provides on board SRAM of either 256 kByte or 1 Mbyte The SRAM is 16 bit wide and dual ported between the CPU DMA and VME accessible through an on board arbiter Read Modify Write cycles TAS instruction used for semaphores are supported in any direction The location of the dual ported SRAM as seen from the VME is programmable via the VME control status register There are 16 different base addresses possible that are all located in the VME standard supervisor user data space Enable disable is selected using a separate bit Note The lower 8 kBytes of dual ported SRAM should not be accessed from the VME because this area is reserved for mailbox interrupts FAIR according to VME 64 Specifications Rule 3 14 and Observation 3 17 May 17 1996 1995 PEP Modular Computers Page 2 5 Chapter 2 Functional Description VM62 A VM42 A User s Manual 2 3 3 Mailbox Interrupt An external VMEbus master may interrupt the VM62 A VM42 A by setting P IRQS pending mailbox IRQ in the VME control status register The address of this dual ported register seen from VME is identical to the base address
4. 15 234 ODA uad aas areas dc SU TS de Di Rien er oes iii essa 16 dr DOL TC ma NC 244 9 19 0359 EN UE SG EES EEE SE HOES Boe EH eS Ee 17 Sek TO AN EE cames cactus heed ee bebe eee ee eee a he be eee bese hr 17 DE CEPR dd a en SHOR ESSE EES a et toi ses ens 17 LOS TE REO 4a edu dad idv xd gd c4 3 cdd dera Edobx dde are debi E 4 ms 17 264 On board Bus Error Timer 2246626444440 diiidan ERR EGO Yo ha A dod Re ea 17 ID COMDBURBUDPIMANB EEE sup 18 PA RE EE a a ed sta 554603524 Os bee bh ood 45954 tu 2562 55 18 Figure 2 6 6 1 Watchdog LED Location 18 20 7 First SOL DC NO TSD sis ss sat d an RSR a RD de SR C9 Poe de dE ose 18 20e Doard LOMME BODIE eta sai saisis ee see eee bs vb meee eee be de es 19 ZB PEL ICS 2666 hs eee REG Rd EEEE TAT EEEE EEEE EEE G5 Hh Ss 20 Page 0 4 1995 PEP Modular Computers May 17 1996 3 4 VM62 A VMA2 A User s Manual Preface dd POUS TL PROUD 6 655 34 E E EE DEED AD dat end di CHE sas a CED 20 Figure 2 7 0 1 LED Port and Button Location 20 LA RESC DOD 6 bi eh oe he bb SEAS cons nen S E686 CERES SEES 5412345 4 20 20 SR NON 2a 3 be oO 4 ESS Se REGS ESSER SESH EERE EORTC eds EERE HE 20 Me SSS eee ee ee ee ee DE 524525 02 4 ee ee ee ee ee ee ee ee se ee ee al 20 25 Data Retention for RIC aud SRAM ss eee be cee eee eee bbe eS ee ee ER EEE amp 21 CU RC LC tests 23 J PRX ePXed PP SAP P3 EQPU ES ce dd se dido a pda de CONDUCTION Sa SS
5. 5 Pinouts VM62 A VM42 A User s Manual This page has been intentionally left blank Page 5 10 1995 PEP Modular Computers May 17 1996 VM62 A VM42 A User s Manual Chapter 6 Software Configuration 6 SOFTWARE CONFIGURATION 6 1 Initializing the 68EN360 Many components of the VM62 A VM42 A are controlled by the MC68EN360 Due to this fact this chip requires a special initialization sequence before any other software can be started The following list describes how the initialization must be performed on the VM62 A VMA2 A WARNING The order of the initialization listed below must not be changed otherwise erratic behaviour of the board may result 1 Set DPRBASE to 0x000000 0x7000001 L gt MBAR in CPU space Example move l t7 d1 select CPU space move l S7000001 d0 value to write to MBAR movec GL re select CPU space moves l d0 MBAR set MBAR 2 Clear reset status register OxFF B gt RSR 3 Set system protection register e bus monitor enabled 128 system clocks timeout 0x7 B gt SYPCR 4 Set module configuration register e bus request MC68040 arbitration ID 3 arbitration synchronous timing mode bus clear out arbitration ID 3 e SIMOO registers are Supervisor Data e BusClear in arbitration ID 3 e interrupt arbitration 3 0x60008CB3 L gt MCR 5 Set PLL enabled and lock access 0xC000 W gt PLLCR 6 Lock access to clock divider control register 0x8000 W gt CDVCR May 17 19
6. Available in 1996 if requested SI PBPRO RS485 optoisolated interface piggyback for 2 wire half duplex PROFIBUS connection with 9 pin D Sub connector MP AB100 AutoBahn interface piggyback complete with all control logic 128 kByte 32 9923 bit fast SRAM as buffer for AutoBahn data transfer with Spanceiver MC 100SX1451 of 50 100 MByte s CABLE VMA2 3 meter RS232 Serial Interface cable for VM42 A VM62 A with 9 pin 12383 232 female D Sub PC pinout to RJ12 connector Page 1 2 O 1995 PEP Modular Computers May 17 1996 VM62 A VM42 A User s Manual Chapter 1 Introduction Name Description Order No CXM SIO3 1 CXM module with 3 RJ45 connected RS232 ports for use with a CXC TBD backplane CXM SIO3 1 CXM module vvith 3 RJ45 connected RS232 ports compatible for direct 13692 connection to a CPU board CXM SIO3 2 CXM module with 2 RJ45 connected SC piggyback ports and one SI TBD piggyback interface no front panel delivered with SC piggyback for use with a CXC backplane CXM SIO3 2 CXM module with 2 RJ45 connected SC piggyback ports and one SI piggyback interface no front panel delivered with SC piggyback compatible for direct connection to a CPU board CXM SIO3 3 CXM module with 3 RJ45 connected SC piggyback ports for use with a CXC backplane CXM SIO3 3 CXM module with 3 RJ45 connected SC piggyback ports compatible for direct connection to a CPU board CXM SIO3 4 CXM module with 3 15 pin D Sub
7. HW 68 EN 360 Comment Function Compatible Port user defined No PBO Used on board SPI SEL for EEPROM Cannot be used on CXC See note 2 SPI Clk can be used if an SPI SEL other than PBO is used SPI TxD can be used if an SPI SEL other than PBO is used SPI RxD can be used if an SPI SEL other than PBO is used See 68360 User Manual Used on board SMC2 Transmit See note 1 Used on board SMCI Transmit See note 1 Used on board SMC2 Receive See note 1 Used on board SMCI Receive See note 1 May 17 1996 1995 PEP Modular Computers Page 2 13 Chapter 2 Functional Description VM62 A VM42 A User s Manual Notes Reserved Pins D On a standard VM62 A VM42 A board these signals are already used for UART ports at BU7 and BUS 2 On a standard VM62 A VM42 A board these signals are used for SPI to which the EEPROM is already connected PBO is chip select of the EEPROM 3 On PA13 a 24 MHz clock signal is routed via jumper J6 This signal is always needed for PEP standard software serial drivers Dual Functioning Signal Pins 4 These signals are routed both to the base board SI Interface connector STSC and the CXC connector and can only be used by one or the other and not both at the same time Due to this a conflict exists if the SCC4 port is to be used with the SI232 piggyback and CXC boards such as CXM SIO3 as both boards access this port T
8. by the 68EN360 Port C lines and are therefore also processed as internal requests PCO 1 2 3 2 4 2 External Autovector Requests Some 68EN360 external interrupt sources are routed to the IRQ lines of the 68EN360 and generated as autovectored interrupts Care must be taken that the relevant 68EN360 register is initialised with respect to the wiring see also the Software Configuration chapter in this manual Source 68EN360 Pin Autovector ABORT ACFAIL IRQ7 TICK IRQ6 Mailbox IRQ IRQ5 SYSFAIL IRQ3 AutoBahn IRQ2 IRQ2 AutoBahn IRQI IRQI May 17 1996 1995 PEP Modular Computers Page 2 7 Chapter 2 Functional Description VM62 A VM42 A User s Manual 2 4 3 VME Interrupt Mask Register Address CS7 1 PEP Default Address CD 00 00 01 Format Byte Access read write Value after HW reset O0 Value after PEP SW initialization Value of EEPROM CS7 1 Register Description Name Description EN IRQx Enable VME IRQx where x 1 to 7 SYSFAIL Enable VME SYSFAIL IRQ autovector 3 Page 2 8 1995 PEP Modular Computers May 17 1996 VM62 A VM42 A User s Manual Chapter 2 Functional Description 2 5 I O Ports 2 5 1 Ethernet Port The MC68EN360 is specified to support a full set of IEEE 802 3 Ethernet CSMA CD media access control and channel interface functions Since the 68EN360 requires an external interface adapter and transceiver function the Ethernet port
9. can be adapted to all standard Ethernet functions such as 10BaseT 10Bases and 10Base2 via a piggyback connected to the SI Interface on the VM62 A VM42 A 2 5 2 Serial Ports The VM62 A VM42 A provides 6 serial ports based on the 68EN360 communications processor The ports can be configured in the following way e 2 service debug ports SMC port RxD TxD only RS232 4 full MODEM ports multiprotocol channels SCC ports The service debug ports are configured as default on the VM62 A VM42 A These ports supply RxD TxD RS232 Interfaces software handshake XON XOFF capability The full MODEM ports supply RxD TxD RTS CTS CD DTR and RCLK TCLK Two of the full MODEM ports can be configured on the SI Interface with a variety of SI Modules RS232 RS485 isolated non isolated and so on Together with the two service debug ports a maximum of three four completely configured serial ports are available for the base board Three two serial ports may be configured via the CXC where three of the four full MODEM Interfaces are routed Figure 2 5 2 4 MC68EN360 Intelligent Controller Schematic CXC Interface Y 2x RS232 with Rx and Tx only The serial channel SCC4 is routed to both the SI Interface and the CXC and can only be used by one or the other and not both at the same time May 17 1996 1995 PEP Modular Computers Page 2 9 Chapter 2 Functional Description VM62 A VM42 A User
10. connected SC piggyback ports 8TE front panel for use with a CXC backplane CXM SIO3 4 CXM module with 3 15 pin D Sub connected SC piggyback ports 8TE front panel compatible for direct connection to a CPU board Each VM62 A VM42 A comes complete with 2 RS232 serial interfaces situated on the lower half of the front panel These interfaces are provided with TxD and RxD signals by the SMC1 and SMC2 channels of the QUICC controller The SCC1 channel of the QUICC provides the interface to one of the available SI xxx piggybacks All other channels SCC2 SCC3 and SCC4 of the QUICC are ported to the CXC interface except for the SI PB232 piggyback which has on board additional control provided by the SCC4 channel through the SI Interface As mentioned above a CXM SIO3 module is available in order to make all the serial interfaces accessible on the VM62 A VM42 A For more details please refer to the CXM SIO3 user s manual Important The VM62 A VM42 A must be ordered with a memory module DM60x and a front panel interface piggyback module SI xxx May 17 1996 1995 PEP Modular Computers Page 1 3 Chapter 1 Introduction VM62 A VMA2 A User s Manual Figure 1 2 0 1 VM62 A VM42 A Configuration Options gogg gogg ooog CPU Options Memory Piggybacks Page 1 4 1995 PEP Modular Computers May 17 1996 1 3 Specifications Main CPU I O Controller Memory DRAM FLASH SRAM EEPROM VMEbu
11. of the 68EN360 The first half of the EEPROM 1 kbit is reserved for factory data including Board ID codes Internet Ethernet addresses boot information etc The second half of the EEPROM is available for the user See also the Software Configuration chapter in this manual For more information on the EEPROM please refer to the XICOR X25C02 data sheet 2 6 3 TICK Generator The 68EN360 internal Periodic Interrupt Timer is used by the PEP real time operating system as TICK generator For more information please refer to the 6SEN360 User s Manual 2 6 4 On board Bus Error Timer The VM62 A VM62 A provides an on board bus error timer An 8us timeout timer monitors the cycle lengths of data transfers to and from locations beyond the bussizer including on board I O CXC SRAM AutoBahn and some VME After a timeout occurs it generates an on board BERR signal for error termination This timer is enabled disabled via the board control status register which also supplies a timeout status bit in order to identify bus errors generated by the on board bus error timer There are four cases of bus error Cause Timeout Enable Disable possible Reserved address BERRO 100ns None On board BERRI SUS Yes set in board control register VME BERR2 128us Yes set in VMEbus control register Chip selects 68EN360 programmable Yes set in 68EN360 register May 17 1996 1995 PEP Modular Computers Page 2 17 Chapter 2 Functional Description
12. operates as a slave to the CPU in so called Companion Mode In this mode the 68EN360 provides complete I O functionality The DMA channels can still obtain ownership of the CPU s system bus and therefore all on chip DMA channels can address the whole of the address space Moreover important functions for system integration such as memory controller clock generation interrupt controller etc are available in this mode meeting the requirements for the initialisation of the 68EN360 described later in this manual The programming of the 68EN360 begins by determining the block of on chip RAM and registers via the MBAR register This register is located at a fixed address and can only be accessed in CPU space 2 2 Address Decoder 2 2 1 Basic Structure The address decoder of the VM62 A VM42 A consists of two basic parts A primary address decoder pre decodes the select signals for the processor data bus in front of the bussizer and for the I O data bus behind the bussizer With reference to initial boot cycles the primary address decoder passes or enables a secondary address decoder stage The secondary address decoder stage is realised using the programmable chip slect logic of the MC68EN360 The 8 outputs of the 68EN360 chip select logic are used for the base addresses of the various memory and I O address ranges 2 2 2 Boot Decoding Due to the fact that the default boot memory used by the VM62 A VM42 A is FLASH memory which i
13. the front panel and the remaining four SCC channels may be optionally configured as shown below Figure 1 4 0 2 MC68EN360 Intelligent Controller Schematic CXC Interface l 2XRS232 with Rx and Tx only May 17 1996 1995 PEP Modular Computers Page 1 7 Chapter 1 Introduction VM62 A VMA2 A User s Manual Ethernet Interface S 0B2 SI IOB5 SI IOBT Three different piggybacks complete with all the associated control logic are available providing 10Base5 10Base2 or IOBaseT interfaces Note The SI I0B5 piggyback requires an external 12V power source to operate Fieldbus Interface SI PBPRO This is a fully optoisolated RS485 PROFIBUS interface piggyback with a 9 pin D Sub connector RS232 Serial Interface Two piggybacks are available with RJ45 connectors for MODEM compatible communication AutoBahn Interface MP AB100 This is realised via a piggyback containing all the necessary control logic 128 kByte high speed SRAM 10 ns as a memory buffer between the processor and the AutoBahn chip MC 100SX1451 for communication on the high speed serial data lines over pins b21 and b22 of the VMEbus DMA Channels 2 independent channels are provided by the QUICC chip and can be used by applications requiring data transfer between CXC modules DRAM FLASH memory dual ported SRAM and AutoBahn memory buffers This memory can be configured with different memory options allowing tremendous flexibility when custo
14. 00000 L 0x21 L 0xF000001 L 0x87000001 L 0x1F000006 L 0x9000001 L 0x1F000006 L 0xA000001 L 0x1F000006 L 0xBF70000 L O0x1FFFEO006 L 0xC000001 L Ox1FFFFS806 L 0xD000001 L 0x1 F000006 L gt GMR AVR BRO ORO BRI ORI BR2 OR2 BR3 OR3 BR4 OR4 BRS ORS BR6 OR6 BR7 OR7 May 17 1996 VM62 A VMA2 A User s Manual Chapter 6 Software Configuration 12 The system software normally determines the real sizes of the DRAM and SRAM installed and re programs the CS lines accordingly The simplest way to achieve this is to write a pattern to the first location and then search for that pattern at meaningful distances e g 256kB 512 kB 1 MB 2 MB 4 MB 8 MB 16 MB If the pattern is found at such an address the original pattern must be altered and then checked to see if the mirrored pattern changes in the same way If not the search must be contined or if yes the memory size is found Note The MC68040 normally operates in non serialised mode meaning that read accesses can occur before write accesses even if they are programmed in the opposite way It is therefore recommended that especially when changing the patterns a nop instruction should be inserted as this forces all pending cycles to be completed 13 Set vector and IRQ level for internal IRQ requester e vector base 0x40 e level 4 0x8040 L gt CICR 14 Set SDMA configuration register 0x770 W gt SDCR 15 If the card is in the first slot
15. 0000000 540000000 40080000 40200000 May 17 1996 1995 PEP Modular Computers Page 4 1 Chapter 4 Memory Piggybacks VM62 A VM42 A User s Manual Jumper J2 Flash Chip Size 1 2 4 Mbit Flash chips fitted 1 3 1 Mbit Flash chips fitted 4 2 DM601 4 2 1 Configuration The DM601 is a memory piggyback fitted with 16MByte DRAM and either 1 or AMByte Flash EPROM Two configurable jumpers are present on the board indicating if write protection is enabled or disabled and whether 1 MBit or 4MBit Flash EPROM chips are fitted Figure 4 2 1 1 DM601 Jumper Layout Component Side Jumper J1 Flash Write Protection Setting Description 1 MB Flash 4 MB Flash 29F010 29F040 Flash bank 1 write protected upper 512 kB 40080000 40100000 Flash bank 0 write protected lower 512 kB 40000000 40080000 Page 4 2 1995 PEP Modular Computers All Flash EPROM write protected No protection Default upper 2 MB 40200000 40400000 lower 2 MB 40000000 40200000 May 17 1996 VM62 A VMA2 A User s Manual Chapter 4 Memory Piggybacks Jumper J2 Flash Chip Size Setting Description 1 2 4 Mbit Flash chips fitted Mbit Flash chips fitted 4 3 DM602 In preparation 4 4 DM603 4 4 1 Configuration The DM603 is a memory piggyback fitted with 32MByte DRAM and 0 5MByte Flash EPROM A version of the DM603 with 2MByte Flash EPROM fitted will soon be available On
16. 17 1996 1995 PEP Modular Computers Page 1 9 VM62 A VMA2 A User s Manual Chapter 2 Functional Description 2 FUNCTIONAL DESCRIPTION Figure 2 0 0 1 VM62 A VM42 A Block Diagram 32 Bit P CPU 32 Bit 32 Bit 68 LC 040 68040V 68EN360 33 40 MHZ DRAM FLASH Companion pone 1 4 16 32 MB 0 5 1 2 4 MB Ba 50 66 80 MHz 25 33 40 MHZ Address Data Control 3 3V IRQ Clock Reset Handler Logic Logic 5V BUSSIZER Status Control Watchdog Logic Serial SPI EEPROM 1 Bit 2 Bit CXC Serial Parallel DMA Port 16 Bit Real Time Clock optional On board Gold Cap I I Backup aulo SCSI Logic switchover DMA VME 5V Stdby I ee Dual Port SRAM 256 1MB Ons optional 1 10Base2 5 T 3 RS232 ISo Functions I b21 b22 AutoBahn Interface 16 Bit VMEbus Interface Master Slave May 17 1996 Standard I O 1995 PEP Modular Computers 2 RS232 SCC1 SCC4 Additional I O Page 2 1 Chapter 2 Functional Description VM62 A VM42 A User s Manual 2 1 The 68EN360 QUICC on the VM62 A VM42 A Motorola s MC68EN360 is a 32 bit high performance communication controller combining powerful peripheral functions with system integration functions and an on chip microprocessor core CPU32 On the VM62 A VM42 A the on chip CPU core is disabled and replaced with a more powerful external CPU the MC68040 or MC68060 The 68EN360
17. 600 Jumper Layout Component Side cler 1 2x oboe Ge eee hee stada Cua ee 64s ei ee os ed pau esu qu d pd qui eee 2 BI LOBO ces ee 129 3099 9 eh EEE EASE OE 8 923 9 398 4 3 4 RE ACE EO ERE d 2 Figure 4 2 1 1 DM601 Jumper Layout Component Side eel 2 ho DRIDUMS 22 24 0434 RS Se eke eee ee hee ee wee ee ee ge ee he E ee 3 mE PO 66 5455 EE DG hae REED SEES SRE or ea ses ais Les eds GSS 245 d 252 5 sament 3 AL EUR 16 0 uu wee bor es Oe SSS SEHR 405 34 AR EOS 3 UE ESE ES ESE 3 Figure 4 4 1 1 DM603 Jumper Layout Component Side 3 May 17 1996 1995 PEP Modular Computers Page 0 5 Preface VM62 A VM42 A User s Manual Se FOS sea hw SEES 4B SHES S 4 3 4 ER CA ERC EK AES GES SEES EHS 5 1 DD oe eb he BO ee dde mt eS Eo NRA ORS Oe he ni eee l Figure 5 1 0 1 Main Board Connector Overview l AL VMEbus Connector STI os 0e ess ra vas mu nas ue ss dur aus a tons esteses 2 CRC LO CS oo hed e855 40556 46 ES dee dd tea vd qox ESQ a 3 Sa DRE DINE mia sa eE SE ES EEEE EEEE HE 3 ed oR E E 5 2 3 2241 RD RO 21 CC adu wax 9 bu Ca a ea res dr E cua ds ies d ivre q Figure 5 2 1 1 Standard Front Panel Pinouts LL LL Le 4 JS HB OS SS OD hi ee ete 443264 REE Box X4 a d 8 SE He odi aep Eee d 5 Figure 5 2 2 1 SI 10B2 Front Panel Pinouts 5 5 2 3 Ethetnet AUL IUBSSSOS SI TUBD 46444 de 44K KADER dedo C9 CEE Ta
18. 9 AutoBahn Boot ABOOT Setting Description Set Boot from MP memory interface enabled Open Boot from MP memory interface disabled Default 3 1 5 Jumper J14 Connection of Protective and Signal GND Setting Description Set Signal GND connected to Protective GND Note Care must be taken to avoid grounding current if this jumper is set May 17 1996 Signal GND not connected to Protective GND Default 1995 PEP Modular Computers Page 3 3 Chapter 3 Configuration VM62 A VM42 A User s Manual 3 2 Jumper Description Solder Side Figure 3 2 0 1 VM62 A VM42 A Jumper Layout Solder Side WARNING Solder jumpers are factory set and must not be altered by the user Alteration of jumper settings can result in damage to the board especially J131 134 Page 3 4 1995 PEP Modular Computers May 17 1996 VM62 A VM42 A User s Manual Chapter 3 Configuration 3 2 1 Jumpers J3 J4 and J5 CPU Bus Clock Setting Description J3 Set 25 MHz Open 33 3 MHz Set 40 MHz 3 2 2 Jumper J6 24 MHz Clock Communications Clock Setting Description Set Clock connected to 66GEN360 Default Open Clock not connected to 68EN360 Note Jumper J6 must be opened if the RCLK2 signal CXM pin c16 is required as it is not compatible with PEP standard software 3 2 3 Jumper J7 CPU Type Setting Description Set 68060 Processor Op
19. 96 1995 PEP Modular Computers Page 6 1 Chapter 6 Software Configuration VM62 A VM42 A User s Manual 7 Configure CLK lines e COM2 to full strength e COMI disabled e register access locked 8 Configure PEPAR register e set LOUTO 2 are PRTYO 2 e select RASIDD function e select VVE0 3 e select AMUX e select CASO 3 9 Configure GMR register set refresh counter period to 24 e set refresh cycle length to 3 set DRAM port size to 32 bit assert CS RAS on CPU space enable refresh 10 Configure autovector register e enable autovector on levels 2 3 5 and 7 11 Configure chip select lines e CSO e CSO e CSI e CSI e CS2 e CS2 e CS3 e CS3 e CS4 e CS4 e CSS e CSS e CS6 e CS6 e CST e CS7 Page 6 2 FLASH to 0x4000000 negate timing 040 size to 16 MByte port size 32 bit tcyc 3 DRAM to 0x0 burst acknowledge 040 size to 16 MByte port size 32 bit tcyc 0 bcyc 1 DMA VME to 0x87000000 size to 16 MByte port size external tcyc 1 AutoBahn to 0x9000000 size to 16 MByte port size external tcyc 1 SRAM to 0xA000000 size to 16 MByte port size external tcyc 1 CXC to OxBF70000 size to 8 kByte port size external tcyc 1 RTC to 0xC000000 size to 2 kByte port size external tcyc 1 on board control to OxD000000 size to 16 MByte port size external tcyc 1 1995 PEP Modular Computers 0x83 B gt CLKOCR 0x51C0 W gt PEPAR 0x18800100 L OxAC B 0x4000011 L 0x3F0
20. B A16 23 AMA GND A15 24 A07 IRQ7 Al4 25 A06 IRQ6 A13 26 A05 IRQ5 A12 27 A04 IRQ4 All 28 A03 IRQ3 A10 29 A02 IRQ2 A09 30 A01 IRQI A08 31 12V 5VSTDBY 12V 32 5V 5V 5V x Active signal low Page 5 2 1995 PEP Modular Computers May 17 1996 VM62 A VMA2 A User s Manual Chapter 5 Pinouts 5 1 2 CXC Connector ST3 For CXC connector pinouts please refer to the CXC Appendix 5 2 Front Panel The front panel connectors are dependent on which interface piggyback is mounted They are Standard Connectors e 2 RS232 serial interfaces BU7 and BUS A front panel is available with only the above standard RS232 connectors fitted SI DUMMY Piggyback Options e Ethernet 10Base2 SI I0B2 e Ethernet AUI 10Bases SI IOB5 e Ethernet 10BaseT SI 10BT e 2 RS232 serial interfaces SI PB232 e PROFIBUS interface SI PBPRO Each option is described in the following Sections May 17 1996 1995 PEP Modular Computers Page 5 3 Chapter 5 Pinouts VM62 A VM42 A User s Manual 5 2 1 Standard RS232 Connectors Figure 5 2 1 1 Standard Front Panel Pinouts Dependent on version ordered Watchdog LED Yellow General Purpose CPU HALT or RESET Green Red RESET Button ABORT Button Pin 1 BU7 RJ12 SMC1 Pin 6 Pin 1 BU8 RJ12 SMC2 Pin 6 6 pin RJ12 RS232 Serial Interface Connectors BU7 and BUS Signal Not Connected GND TxD RxD Not Connecte
21. Data Strobes LIST4 LISTI Serial data strobe outputs can be used to gate clocks to external devices that do not have a biult in Time Slot Assigner TSA BRG Baud Rate Generator BRGO4 BRGOI Baud rate generator output clock allows baud rate Out 4 1 generator to be used externally BRG Input Clock CLK2 CLK6 Baud rate generator input clock from which BRG will derive the baud rates PIP Port B 15 0 PB15 PBO PIP Data I O Pins Strobe Out STRBO This input causes the PIP output data to be placed on the PIP data pins Strobe In STRBI This input causes data on the PIP data pins to be latched by the PIP as input data SDMA SDMA _SDACK2 SDMA output signals used in RISC receiver to mark Acknowledge 2 1 _SDACKI1 fields in the Ethernet receive frame 2 5 4 AutoBahn Interface In preparation Page 2 16 1995 PEP Modular Computers May 17 1996 VM62 A VM42 A User s Manual Chapter 2 Functional Description 2 6 Special Functions 2 6 1 Real Time Clock The RTC V3021 3 wire serial interface is a 1 bit device which is accessible over the CS6 of the 68EN360 Its timekeeping features include e seconds minutes hours day of month month year week day and week number in BCD format leap year and week number correction e standby supply smaller than IuA See also the Software Configuration chapter in this manual and the V302 data sheet 2 6 2 EEPROM The serial EEPROM is a 1 bit device which is accessible over the SPI Interface 3 wire Interchip
22. EN 360 Port Comment DMA ACR Yes PB5 DMA REQ CXC Function Yes 68302 HW Compatible PB4 68 EN 360 Port SERI RCLK Yes PAS SERI TCLK Yes PAIO SERI TXD Yes PA3 SERI RXD Yes PA2 SERI RTS Yes PB13 SERI DTR Yes PB17 SERI CTS Yes PC6 SERI CD CXC Function Yes 68302 HW Compatible PC7 68 EN 360 Port Comment SER2_RCLK Yes PA13 Cannot be used if J6 is set See note 3 SER2_TCLK Yes PAI2 SER2 TXD Yes PA5 SER2 RXD Yes PA4 SER2_RTS Yes PB14 SER2_DTR Yes PB16 SER2_CTS Yes PC8 SER2_CD Page 2 12 Yes PC9 1995 PEP Modular Computers May 17 1996 VM62 A VM42 A User s Manual Chapter 2 Functional Description CXC 68302 HW 68 EN 360 Comment Function Compatible Port SER3 RCLK Yes PAIS Not usable if SI Module uses SCC4 See note 4 SER3_TCLK Yes PAI4 SER3 TXD Yes PA7 Not usable if SI Module uses SCC4 See note 4 SER3 RXD Yes PA6 Not usable if SI Module uses SCC4 See note 4 SER3 RTS Yes PB15 Not usable if SI Module uses SCC4 See note 4 SER3 DTR Yes PB9 Not usable if SI Module uses SCC4 See note 4 SER3 CTS Yes PC10 Not usable if SI Module uses SCC4 See note 4 SER3 CD PC11 Not usable if SI Module uses SCC4 See note 4 CXC 68302
23. ESET generator to VME J8 Open Boot from VME disabled J9 Open Boot from MP memory interface disabled Solder J3 Dependent on board CPU frequency J4 J5 J6 Set Clock connected to 68EN360 J7 Dependent on board CPU type J10 Open Write protection of EEPROM disabled JII Dependent on board SRAM size J12 J14 Open Signal GND not connected to Protective GND J131 J134 Dependent on board Processor power supply Note Jumpers J1 J2 J8 and JO are normal wire jumpers that can be configured by the user The other jumpers are solder jumpers and are factory set May 17 1996 1995 PEP Modular Computers Page 3 1 Chapter 3 Configuration VM62 A VM42 A User s Manual 3 1 Jumper Description Component Side Figure 3 1 0 1 VM62 A VM42 A Jumper Layout Component Side J2 J1 CXC Interface bale Page 3 2 1995 PEP Modular Computers May 17 1996 VM62 A VM42 A User s Manual Chapter 3 Configuration 3 1 1 Jumper J1 VME SYSCLK Setting Description Set SYSCLK connected to VME Default Open SYSCLK disconnected from VME 3 1 2 Jumper J2 VME SYSRES Setting Description Set On board RESET generator to VME Default Open On board RESET disconnected from VME 3 1 3 Jumper J8 VME Boot VBOOT Setting Description Set Boot from VME enabled Open Boot from VME disabled Default 3 1 4 Jumper J
24. SR Re NAN RTS x 9o 9 ia ss ce 3 1 Table 3 0 0 1 VM62 A VM42 A Default Jumper Settings l 3 1 Jumper Description Component Side acea pe bs aaaea es 2 Figure 3 1 0 1 VM62 A VM42 A Jumper Layout Component Side 2 LL Jumper DES NME TEL uixeackEREG x3 9 S24 4 493 5 4X 9d dod 3 5 iriki esa do 3 21 2 BOIL EU VI sus ee eed ee Re RR RU ie de ed REC da rations 3 LL spor ds VME Boot VYBOOI oon ae eben data She oS ERODES SEES P4 ss 3 3 1 4 Jumper J9 AutoBaha Boot ABOOT sois sumssitussvasivessas es h simiein 3 3 1 5 Jumper J14 Connection of Protective and Signal GND 3 a2 Mimpeor Description Solder SIJE sie xeu ss ess EGRE red 9E OA E R44 ee sees Figure 3 2 0 1 VM62 A VM42 A Jumper Layout Solder Side 4 3 241 dumper 1 JC CPU Bus Clock cect theese be RACE P woven Qa ERR En 2 3 2 2 Jumper J6 24 MHz Clock Communications Clock H Bar REDE I Voy Bo EE eee ee ea ee eee embod eee eet 3 3 244 Jumper J10 Serial EEPROM Write Protection 12 25 9224 zo x4 xSE CA RE RS 5 20 Jupe Il TI SRAM S576 ilz aqaedodsstaxkxdorbw texickrador4a d 4X4xx6vkbese 5 3 2 5 Jumpers J131 J134 Processor Power Supply i 22saskRwuRA AE UR OE SEY SES 6 Memory Pireva ono SR St hs OO ER ES oO EERE oo 9 o 4 1 D WO bea be 932252224 1 dli AO EPA Ce da ho GES 46 ud SES SO E 4 SEUS Ge ED P dd ds do tua 4 54 EO EHS l Figure 4 1 1 1 DM
25. VM62 A VM42 A User s Manual Note During VMEbus cycles the on board bus error timer is reset as soon as the VM62 A VM42 A gains VMEbus ownership This means that the time gap between a VMEbus request and the starting of the VMEbus cycle is monitored by the on board BERR timer VMEbus cycles themselves are monitored by the separate VMEbus BERR timer BUS monitor 2 6 5 VME Bus Error Timer The VM62 A VM42 A also provides a bus monitor for the VMEbus A 128Us timeout timer monitors VMEbus data transfer cycle lengths and generates a VMEbus BERR signal for error termination This timer is enabled disabled via the VME control status register which also supplies a timeout status bit in order to identify bus errors generated by the bus monitor 2 6 6 Watchdog Timer A 512ms watchdog timer triggers the on board and VME system reset generator at timeout Once enabled via the board control status register the watchdog timer cannot be reset by software It must be re triggered via the corresponding bit in the board control status register periodically within the timeout period Watchdog timer running is a status that is displayed by the yellow front panel LED Figure 2 6 6 1 Watchdog LED Location Watchdog LED Er Yellow 00 W 2 6 7 First Slot Detection FSD The VM62 A VMO2 A detects during power up whether the CPU in use is positioned in the far left slot of the system This is achieved using a 100k p
26. VM62 A VM42 A User s Manual Preface VM62 A VM42 A Intelligent Universal Controller Modules for Stand Alone and VMEbus Manual Order No 3368 User s Manual Issue 3 Unpacking and Special Handling Instructions This PepCard product is carefully designed for a long and fault free life nonetheless its life expectancy can be drastically reduced by improper treatment during unpacking and installation Observe standard anti static precautions when changing piggybacks ROM devices jumper settings etc If the product contains batteries for RTC or memory back up ensure that the board is not placed on conductive surfaces including anti static plastics or sponges These can cause shorts and damage to the batteries or tracks on the board When installing the board switch off the power mains to the chassis Do not disconnect the mains as the ground connection prevents the chassis from static voltages which can damage the board as it is inserted Furthermore do not exceed the specified operational temperature ranges of the board version ordered If batteries are present their temperature restrictions must be taken into account Keep all of the original packaging material for future storage or warranty shipments If it is necessary to store or ship the board re pack it as it was originally packed May 17 1996 1995 PEP Modular Computers Page 0 1 Preface VM62 A VM42 A User s Manual REVISION HISTORY VM62 A VM42 A User
27. able from 0 F in 1 Mbyte windows enabled with EN_DPR See Table on next page Page 2 6 1995 PEP Modular Computers May 17 1996 VM62 A VM42 A User s Manual Chapter 2 Functional Description BADR 3 0 VME Board Base Address 0000 00 00 00 0001 10 00 00 0010 20 00 00 0011 30 00 00 0100 40 00 00 0101 50 00 00 0110 60 00 00 0111 70 00 00 1000 80 00 00 1001 90 00 00 1010 A0 00 00 1011 BO 00 00 1100 CO 00 00 1101 D0 00 00 1110 SEO 00 00 1111 FO 00 00 2 4 Interrupt Control The interrupt control logic processes internal interrupt requests 68EN360 together with external requests VME and external autovectored interrupt requests The interrupt control logic is built up using the 68EN360 internal interrupt controlling and a 7 level VMEbus interrupt handler with the corresponding mask register 2 4 1 Internal Requests Internal requests are related to all interrupt requests caused by the 68EN360 sources including the 68EN360 system integration functions watchdog timer periodic interrupt timer and the communication processor module RISC controller timers DMAs SCCs and so on For more information please refer to the 68EN360 User s Manual In order to avoid conflicts regarding interrupt levels it is recommended to use IRQ level 4 for 68EN360 CPU internal requests and IRQ level 6 for 68EN360 SIM60 internal requests Note The 4 IRQ lines specified by CXC are supplied
28. ahn chip the Spanceiver MC100SX 1451 allows transfer rates of up to 100 Mbyte sec over the VMEbus using the VMEbus lines SERA and SERB PEP has also developed a cost effective VMEbus backplane series that support AutoBahn called VBP4A in 7 12 and 15 slot options These backplanes allow direct connection of the main power supply hence reducing cabling costs dramatically A CXM SIO3 module is available in order to make all three serial interfaces that are available on the CXC accessible on the VM62 A VM42 A This is achieved by using RS232 SC xxx or SI xxx interfaces For more details please refer to the CXM SIO3 user s manual AutoBahn and Spanceiver are trademarks of PEP Modular Computers May 17 1996 1995 PEP Modular Computers Page 1 1 Chapter 1 Introduction VM62 A VMA2 A User s Manual 1 2 Ordering Information Name Description Order No VM62 BASE VMEbus single board computer comprising MC68060 50 MHz MC68EN360 25 MHz 256 kByte dual ported SRAM with Gold Cap for backup configured for use with the AutoBahn interface piggyback up to 6 serial interfaces 2 available on the front panel as RS232 and an additional 4 divided between the CXC interface and SI Interface CXC Interface PEPbug 12349 VM62 BASE Same as order no 12349 but with 1 MByte dual ported SRAM VM42 BASE VMEbus single board computer comprising MC68040 33 MHz MC68EN360 33 MHz 256 kByte dual ported SRAM wit
29. and VME RESET button ABORT button HALT LED red Watchdog LED yellow General purpose LED green Typ 2LA 3V gt 50 hours Dependent on the battery installed on the system 5V Stby Automatic switching between 5V Stby and internal Gold Cap Typ 3QuA 3V To be defined 5 VV with DM600 and SITBS fitted 7W with DM600 and SITBS fitted 4 W with DM600 and SITBS fitted Standard 0 70 C Optionally E2 40 C to 85 C 0 to 95 non condensing Single height Eurocard 100 160 mm DIN 41612 style C 96 contacts P1 connector 4 TE 1 slot 1995 PEP Modular Computers May 17 1996 VM62 A VM42 A User s Manual Chapter 1 Introduction 1 4 Features CPU Options The Table below illustrates the capabilities of the available CPUs The 68060 processors operating at 50 MHZ deliver up to 100 MIPs while the 68040 processors operating at 33 MHz give performances up to 35 MIPs Table 1 4 0 1 CPU Configuration Processor Product MC68040 VM42 A MC68LC040 VM42 A MC68040V VM42 A MC68060 VM62 A MC68EC060 VM62 A planned project Mask E71M required 68EN360 25 33 MHZ the QUICC chip used in companion mode is tightly coupled to the CPU Working as an I O and system controller it provides all the necessary interfaces timers and clocks etc in addition to the DRAM memory controller Serial Channels Six are provided by the QUICC Two SMC channels are ported to
30. d Not Connected Page 5 4 1995 PEP Modular Computers May 17 1996 VM62 A VMA2 A User s Manual Chapter 5 Pinouts 5 2 2 Ethernet 10Base2 SI 10B2 SITB2 on board Figure 5 2 2 1 SI 10B2 Front Panel Pinouts Collision Transmit 10Base2 o BU3 SCC1 ETHERNET May 17 1996 1995 PEP Modular Computers Page 5 5 Chapter 5 Pinouts VM62 A VMA2 A User s Manual 5 2 3 Ethernet AUI 10BaseS SI 10B5 SITBS on board Figure 5 2 3 1 SI 10B5 Front Panel Pinouts Pin 8 r Pin 1 E Pin 9 ca e z BU3 SCC1 A Pin 15 LLI SE LL LLI e 15 pin D Sub Ethernet AIU 10BaseS Connector BU3 Signal Control In circuit Shield Control In circuit Data Out circuit A Data In circuit Shield Data In circuit Voltage Common Not Connected Not Connected DIN mM BR LR D Control In circuit Shield Data Out circuit B Data Out circuit Shield NO Data In circuit B 12 Volts Oo iN GND Not Connected UA Page 5 6 1995 PEP Modular Computers May 17 1996 VM62 A VMA2 A User s Manual Chapter 5 Pinouts 5 2 4 Serial RS232 Interface SI PB232 S1232 on board Figure 5 2 4 1 SI PB232 Front Panel Pinouts gt BU2 RJ45 SCC1 BU3 RJ45 SCCA Pin 8 SER 2 Pin 1 Pin 8 a LLI ND Pin 1 8 pin RJ45 Serial Interface Connector
31. e the CXC contains 4 IRQ capability 4 edge sensitive IRQs DMA capability 1 channel DREQ DACK serial ports 3 channels Full MODEM and a set of parallel port signals These special CXC functions are based on the 68EN360 resources For general CXC information including generic pinouts and a comparison of the 68 EN 360 and 68302 CPU pinouts on the CXC please refer to the CXC Specification User s Manual and the CXC Appendix attached to this manual Page 2 10 1995 PEP Modular Computers May 17 1996 VM62 A VM42 A User s Manual Chapter 2 Functional Description Table 2 5 3 1 CXC Pinouts using the 68 EN 360 Row A Row B Row C Signals Signals Signals PC3 RTS4 LIRQA L1ST4 PB2 SPIMOSI SPITXD RRJCT2 PC11 CD4 L1RSYNCA PB3 SPIMISO SPIRXD BRGO4 PB8 SMSYN1 DREQ2 PB16 BRGO3 STRBO PB9 _SMSYN2 _DACK2 PB17 RSTRT1 STRBI _CS CXC CSS of 68360 _CXC CS1 _CXC CS5 EE EC bao PB3 SPIMISO SPIRXD BRGO4 PB8 SMSYN1 DREQ2 _PB16 BRGO3 STRBO _PB9 _SMSYN2 _DACK2 PB17 RSTRTU STRBI __CS CXC CS5 of 68860 _LDS DO 5 May 17 1996 1995 PEP Modular Computers Page 2 11 CXC Function 68302 HW Compatible 68 EN 360 Port Comment Chapter 2 Functional Description VM62 A VM42 A User s Manual IRQ_1 Yes PCO IRQ 2 Yes PCI IRQ 3 Yes PC2 IRQ 4 CXC Function Yes 68302 HW Compatible PES 68
32. e DRAM and FLASH should be made at 0 and 4000000 AII other components addressed by the MC68EN360 should always be accessed over the mirrored area with Cxxxxxxx as described in Section 2 2 5 Address Map Page 6 4 1995 PEP Modular Computers May 17 1996
33. e configurable jumper is located on the board indicating whether the Flash EPROMS are write protected Figure 4 4 1 1 DM603 Jumper Layout Component Side Flash J1 C2 EPROM DRAM Jumper J1 Flash Write Protection Setting Description Open All Flash EPROM write protected Set No protection Default May 17 1996 1995 PEP Modular Computers Page 4 3 Chapter 4 Memory Piggybacks VM62 A VM42 A User s Manual This page has been intentionally left blant Page 4 4 1995 PEP Modular Computers May 17 1996 VM62 A VMA2 A User s Manual Chapter 5 Pinouts 3 5 PINOUTS 5 1 Main Board Figure 5 1 0 1 Main Board Connector Overview Pin 7 EE Pin ST5A Serial Piggyback MP Piggyback Memory Piggyback May 17 1996 1995 PEP Modular Computers Page 5 1 Chapter 5 Pinouts VM62 A VM42 A User s Manual 5 1 1 VMEbus Connector STI Pin Nr Row A Signal Row B Signal Row C Signal 1 D00 BBSY D08 2 DOI BCLR D09 3 D02 ACFAIL D10 4 D03 BGOIN DII 5 D04 BGOOUT D12 6 D05 BGIIN D13 7 D06 BGIOUT D14 8 D07 BG2IN D15 9 GND BG2OUT GND 10 SYSCLK BG3IN SYSFAIL 11 GND BG3OUT BERR 12 DS1 BRO SYSRESET 13 DSO BR1 LWORD 14 WRITE BR2 AMS IS GND BR3 A23 16 DTACK AMO A22 17 GND AMI A21 18 AS AM2 A20 19 GND AM3 A19 20 IACK GND A18 21 IACKIN SERA A17 22 IACKOUT SER
34. en 68040 Processor 3 2 4 Jumper J10 Serial EEPROM Write Protection Setting Description Set Write protection enabled Open Write protection disabled Default 3 2 5 Jumpers J11 and J12 SRAM Size Setting Description J11 J12 1 2 1 2 1 MByte 1 3 1 3 256 RByte May 17 1996 1995 PEP Modular Computers Page 3 5 Chapter 3 Configuration VM62 A VM42 A User s Manual 3 2 6 Jumpers J131 J134 Processor Power Supply Setting Description J131 J134 1 2 5 Volt 68040 68LC040 1 3 3 3 Volt 68040V 68060 WARNING Alteration of the settings of J151 J134 can result in damage to the board Page 3 6 1995 PEP Modular Computers May 17 1996 VM62 A VMA2 A User s Manual Chapter 4 Memory Piggybacks 4 MEMORY PIGGYBACKS 4 1 DM600 4 1 1 Configuration The DM600 is a memory piggyback fitted with 4MByte DRAM and either 1 or 4MByte Flash EPROM Two configurable jumpers are present on the board indicating if write protection is enabled or disabled and whether 1 MBit or 4MBit Flash EPROM chips are fitted Figure 4 1 1 1 DM600 Jumper Layout Component Side Jumper Jl FLASH Write Protection Setting Description 1 MB Flash 4 MB Flash 29F010 29F 040 All Flash EPROM vvrite protected No protection Default Flash bank 1 write protected upper 512 kB upper 2 MB 840080000 840200000 40100000 40400000 Flash bank 0 write protected lower 512 RB lower 2 MB 54
35. enable the VMEbus monitor If bit 4 in VCSR is set then set bit 5 in VCSR 16 Enable on board I O bus error timer Set bit 2 in BCSR May 17 1996 1995 PEP Modular Computers Page 6 3 Chapter 6 Software Configuration VM62 A VM42 A User s Manual Address List of Involved Registers MBAR Ox3FFOO CPU space RSR 0xC0001009 SYPCR 0xC0001022 MCR 0xC0001000 PLLCR 0xC0001010 CDVCR 0xC0001014 CLKOCR 0xC000100C PEPAR 0xC0001016 GMR 0xC0001040 AVR 0xC0001008 BRO 0xC0001050 ORO 0xC0001054 BR1 0xC0001060 ORI 0xC0001064 BR2 0xC0001070 OR2 0xC0001074 BR3 0xC0001080 OR3 0xC0001084 BR4 0xC0001090 ORA 0xC0001094 BR5 0xC00010A0 ORS 0xC00010A4 BR6 0xC00010B0 OR6 0xC00010B4 BR7 0xC00010CO0 OR7 OxC00010C4 CICR 0xC0001540 SDCR 0xC000151E VCSR OxCD000005 BCSR OxCD000007 6 2 Initialising the Cache Before the system enables any cache present they should be invalidated using Caves DE Furthermore the complete address range should not be cachable as caching only maRes sense on DRAM and FLASH EPROM Other areas should never be cached and must be switched to serialised in order to prevent the MC68040 MC68060 from mixing up read and write cycles The easiest way of doing this is to make use of the DTTO register in the following way move l 19907ER040 01 movec cibo c The code above sets all addresses below 80000000 to cacheable and non serialised whereas all addresses above are set to non cacheable and serialised Accesses to th
36. esesakseeAkb X ges rases Ekeexde444e kpkbdesx d memes 3 L4 S condary Address Decoder 445455 440c0mnneheedd ed on seciomdu i A SG EKO mE S 3 ZO ANGERS i314354 4 b044 4 k42xPb2 29A45442 1239495254 2 2793232443 53 sl Figure 2 2 5 1 VM62 A VM42 A Address Map 4 ns ia 9 232394 5 29424 bebe MT RU 23592 505x459 ci s 23 DIDIER anis dass onde nd eee RER D TT RD 4543322 29 126 1922352 2 594 3 43 gt Del Sym COUTO ais bbe es hed eee ES PS SER ESE IS EES Us ed a Es a EE PA 5 Po DE EL za iwsedor ne eem ss dee ss dun agite cru ewe E J 200 MaD ON SEE ER EAE P3 4 iesxESSAISASES S 6 2 3 4 VMEbus Control Status Register j4c456 o mac ee ee bo edu See Gees eR 3a HES EH 6 2g DEM LONE mn a ENS a 149493 4 48493 2943954547 ee ee ee ee 926 7 ee EN Rd ele E E EE EEEE E E E EEEE 7 24 2 External Autovect r REQUENS 2 45544 6846 8 ueE Pond betist ddaa ESE KE HODES 1 243 VME Interrupt Mask Register Lisa srsoiasasesi ete dris hie ets amer 8 et NEN ea Us GEM E4223 96 ES ENS 55255 MUSEU 48 1 9 53 229 X REEDS DEERE E X 9 ne E E ee ewes ee eee ere eet 9 Ce OL MS DES DL ENS OO aeree erara 9 Figure 2 5 2 1 MC68EN360 Intelligent Controller Schematic 9 DE NS HIE ea oe ADE ES i ES da E V doi xo do Ou SS e de dori e LG EEES En 10 Table 2 5 3 1 CXC Pinouts using the 68 EN 360 11 Table 2 5 3 2 Further Explanation of 68 EN 360 Mnemonics
37. est to the VMEbus grant Timeout 8us ACFAIL Read Write VME ACFAIL signal latched when active in order to bit 1 distinguish a level 7 NMI from an ABORT or ACFAIL LED_G Read Write Enables the green general purpose front panel LED bit 0 Note Information may be lost if the user writes to bit 7 May 17 1996 1995 PEP Modular Computers Page 2 19 Chapter 2 Functional Description VM62 A VM42 A User s Manual 2 6 9 Reset Sources Reset Source Identification Push button No SYSRES VME No Watchdog WDG bit on board Board Control Status Register Power monitor 4 65V Inside the 68EN360 2 7 Front Panel Functions Figure 2 7 0 1 LED Port and Button Location Watchdog LED Yellow General Purpose CPU HALT or RESET Green OOO Red U WH DQO RESET Switch RST AB ABORT Switch 2 7 1 RESET Button A RESET button is fitted to the front panel to avoid false operation The RESET button triggers the on board system reset generator as well as the VME if jumper J2 is set 2 7 2 ABORT Button Together with the RESET button an ABORT button is also fitted to the front panel The ABORT button generates a level 7 IRQ non maskable interrupt which is used for debugging purposes In this case bit 1 of the Board Control Status Register is not set remains 0 2 7 3 LED Port The front panel LED port consists of three LEDs with the following functions Red LED CPU in HALT
38. f the possibility of such claims prior to the purchase of or during any period since the purchase of the product Please remember that no PEP Modular Computers employee dealer or agent are authorized to make any modification or addition to the above terms either verbally or in any other form written or electronically transmitted without consent May 17 1996 O 1995 PEP Modular Computers Page 0 3 Preface VM62 A VM42 A User s Manual TABLE OF CONTENTS Page 1 IODPOUBNOHONH 224444286 6h ee ORE ST ess SEERA ter s EES ses 1 1 Unes mit sb dur it nr Mlle ti Es nie Gide l La DE CI a i493 33 5E bob x3 dog ES dCi lu dA or ni Eee SE ORES 2 Figure 1 2 0 1 VM62 A VM42 A Configuration Options 4 Ree eli 122295904935 5443 3 54 d EN eee eee ne ee mare ee ee eee dada Eq es EE P 5 oe ee Gee sas Oe se aw ee hehehe bees bbe bees 9442429232522 5425942125554 f Table 1 4 0 1 CPU Configuration ee LL 7 Figure 1 4 0 2 MC68EN360 Intelligent Controller Schematic RR da DU aa dde 9298 22 404 459 359545 359p ei 9 2 Functional Descriphon 4 664 sus sise ire sera RS ROO sues ss es d ss 2 1 Figure 2 0 0 1 VM62 A VM42 A Block Diagram 1 2 The GEN SO QUICC on h VMGZ A NAT 4 34 434347541343 3 dd Edad das sites 2 DE 00 E E E E E E T ga p RE UE A ma sa os ee EE EE E E E EE E E S 2 de CCR noe ua ne E eee eo or ous z 202mm UES DOUE 2
39. h Gold Cap for backup configured for use with the AutoBahn interface piggyback 6 serial interfaces 2 available on the front panel as RS232 and an additional 4 divided between the CXC interface and SI Interface CXC Interface PEPbug VM42 BASE Same as order no 12344 but with 1 MByte dual ported SRAM VM42 BASE Same as order no 12344 but with MC68040V 33 MHz 3 3 V technology VM42 BASE Same as order no 12346 but with 1 MByte dual ported SRAM Memory piggyback with 4 MByte DRAM and 1 MByte Flash EPROM Memory piggyback with 4 MByte DRAM and 4 MByte Flash EPROM Memory piggyback with 16 MByte DRAM and 1 MByte Flash EPROM Memory piggyback with 16 MByte DRAM and 4 MByte Flash EPROM Memory piggyback with 1 MByte DRAM and 1 MByte Flash EPROM Memory piggyback with 32 MByte DRAM and 512 kByte Flash EPROM SI 10B2 Memory piggyback with 32 MByte DRAM and 2 MByte Flash EPROM 10Base2 Thin Ethernet cheapernet interface with RG58 coax connector SI 10B5 10Base5 AUI Ethernet interface piggyback with 15 pin D Sub connector SI IOBT IOBaseT Twisted pair Ethernet interface piggyback with RJ45 connector SI DUMMY Front panel only fitted vvhen no SI piggybacR required SI PB232 Serial interface piggyback for 2 RS232 connections Modem interface with 2 RJ45 connectors SI PB232 ISO Serial interface piggyback for 1 RS232 optoisolated connection with 1 RJ45 connector
40. hapter 2 Functional Description VM62 A VM42 A User s Manual 2 2 5 Address Map The VM62 A VM42 A address map shown in the Table below is based on the recommended default initialisation of the 68EN360 chip select logic Figure 2 2 5 1 VM62 A VM42 A Address Map PEP Default Address Hex Device OO xx Xx Xx 04 xx XX xx 07 OO Ox xx 09 xx XX XX OA XX XX XX OB xx xx xx OC xx XX XX OD xx xx xx IX XX XX XX 2X XX XX XX 3X XX XX XX 4x XX XX XX 5x XX XX XX 6x XX XX XX 82 XX XX XX 83 XX XX XX 85 00 xx xx 87 XX XX XX 87 XX XX XX OX XX XX XX AX XX XX XX Bx xx xx xx CO xx xx xx C4 xx xx xx C7 xx xx xx CA XX XX XX CB F7 Ox xx CC xx xx xx CD 00 00 01 CD 00 00 05 CD 00 00 07 Dx xx xx xx Ex XX XX xx Fx XX XX xx DRAM 68EN360 s CS1 FLASH 68EN360 s CSO Reserved 6SEN360 internal RAM register DMA AutoBahn CS3 Reserved mirrored 65EN360 s CS4 Reserved mirrored 6SEN360 s CSS Reserved mirrored 65EN360 s CS6 Reserved mirrored 65EN360 s CS7 Reserved BERR 0 Reserved BERR 0 Reserved BERR 0 MP interface CS AUT Reserved BERR 0 Reserved BERR 0 The following address area is non cachable serialised VMEbus CS VMP user defined AM code VMEbus CS VMP user defined AM code VMEbus CS VMP short I O AM code VMEbus CS VMP user defined AM code DMA VME 68EN360 s CS2 Reserved BERR 0 Reserved BERR 0 Reserved BERR 0 Reserved mirrored DRAM Reserved mirrored FLASH
41. he SCC4 port can therefore not be used at the same time by SI piggybacks and CXC boards The CXC ports SERI SER2 and SER3 are equivalent to ports SCC2 SCC3 and SCC4 resp on the 68xx360 With regard to special CXC capabilities the CXC pinout on the VM62 A VM42 A has been developed to provide maximum compatibility between the standard CXC functions In addition all signals are available in order to configure 2 time division multiplexed channels via the CXC ISDN PCM GCI and so on Multi function pins with incompatible functions with regard to the 68302 and 68EN360 called user defined in the generic CXC specification are not part of the VM42 A VM62 A CXC specification Although the SMCs are configured on the base board these ports are also integrated on the CXC This is because of possible ISDN applications where SMCs can be integrated and other protocols supported by the 68EN360 Note If the RCLK2 signal CXM pin c16 is required jumper J6 24 MHz clock must be opened and the serial drivers delivered by PEP modified Page 2 14 1995 PEP Modular Computers May 17 1996 VM62 A VM42 A User s Manual Chapter 2 Functional Description Table 2 5 3 2 Further Explanation of 68 EN 360 Mnemonics Group Signal Name Mneumonic Function SCC Receive Data RXD4 RXDI Serial receive data input to the SCCs J Transmit Data TXD4 TXDI Serial transmit data output f
42. ion ability via the AutoBahn Spanceiver chip A combination of the high performance CPU Motorola MC68060 or 68040 and the Quad Integrated Communications Controller chip the Motorola MC68EN360 or QUICC not only enables a pure computation performance from approximately 35 MIPS to over 100 MIPS but dispenses with the usual restrictions associated with communications over serial interfaces Communication tasks are dealt with by the QUICC chip freeing the CPU from such time consuming chores Fieldbus protocol such as PROFIBUS are also handled by the QUICC In addition the QUICC used together with PEP s expanding CXC interface is ideally suited for communication tasks extending from 6 serial interfaces over LAN to WAN X 25 ISDN applications The EN version of the QUICC also supports Ethernet on 2 channels only one usable on the VM42 A VM62 A using PEP standard software The various I O interfaces are realised using piggybacks attached to the main board Five options are at the moment available They are Ethernet 10Base 2 e Ethernet 10Base 5 AUI e Ethernet 10BaseT e 2 RS232 serial interfaces PROFIBUS interface RS485 isolated half duplex 2 wires PEP s AutoBahn technology has solved one of the major problems that exist in information technology data transfer over the various bus systems Normally the data transfer rate over a bus system is below the data transfer capability of a modern CPU chip The AutoB
43. l ported RAM and a mailbox interrupt controller 2 3 1 System Controller The VM62 A VM42 A can act as a VME system controller with arbiter system clock driver power monitor with system reset driver ACK daisy chain driver and 7 level VMEbus interrupt controller Arbitration is single level FAIR on BR3 If the VM62 A VM42 A is used as system controller it has to be placed in slot 1 of the VMEbus backplane furthermost left slot There is no jumper setting necessary as the board provides a first slot detection function which is also readable within the VME control status register The ACK daisy chain driver is supplied by connecting the IACKIN and IACKOUT line IACK is connected via the VMEbus backplane for IACKIN of slot 1 VME SYSCLK and SYSRES can be routed from on board using jumpers leaving the choice of generating these signals by the system controller to the user SYSFAIL generates a maskable on board autovectored interrupt see also External Autovector Requests ACFAIL generates a non maskable autovector level 7 interrupt NMI in the same way as the ABORT button When an ACFAIL NMI is detected it can be differentiated from an ABORT by reading bit of the Board Control Status Register bit 1 is set to 1 for ACFAIL If this is the case the CPU should stay in the IRQ service routine and save any important data to non volatile memory The VM62 A VM42 A also provides a bus monitor for the VMEbus A
44. mising memory requirements for real time applications DRAM FLASH This memory complete with a 32 bit data wide access bus is placed on a piggyback with addressing capability for up to two memory banks of 64 MByte each On board 5 V FLASH memory provides the latest ROM technology allowing the user to take advantage of the on board programming facility to produce low cost upgrades by simply overwriting existing stored data SRAM This is a dual ported battery backed Gold Cap memory area with a 16 bit data wide access bus Users of the VMEbus and the on board CPU both have access to this memory The lower 8 kByte are reserved for the location monitor EEPROM Although a 2 kbit EEPROM is provided on board 1 kbit has been pre programmed with PEP production data boot info Ethernet registration etc leaving the remaining 1 kbit for user application code A write protect jumper prevents accidental erasure Page 1 8 O 1995 PEP Modular Computers May 17 1996 VM62 A VM42 A User s Manual Chapter 1 Introduction 1 5 Related Publications VITA VMEbus Specifications Revision Cl MPI Modpack and CXC Specification from PEP Version 1 5 or later Motorola M68060 Microprocessors User s Manual M68040 Microprocessors User s Manual MC68EN360 Quad Integrated Communications Controller User s Manual AutoBahn Spanceiver Data Sheet EM Microelectronic V3021 1 Bit Real Time Clock Data Sheet XICOR X25C02 SPI Serial EEPROM Data Sheet May
45. of the dual ported SRAM occupying the lower 8 kBytes odd byte addresses of the dual ported SRAM Setting P IRQS generates an autovector 5 interrupt on the CPU Typically the on board CPU resets P IRQS during the processing of the corresponding interrupt service routine Note Although every odd address of the 8k block of the VME control status register can be accessed from VME only the P IRQS bit can be set All other bits are write protected from the VME As the P IRQS bit is located at bit 7 within the register it can be directly used as a semaphore because read modify write TAS instruction is supported 2 3 4 VMEbus Control Status Register Address CS7 5 PEP Default Address CD 00 00 05 Format Byte Access read write Value after HW reset see table 1 6 5 4 3 2 1 0 087 5 Register Description Reset HW Reset PEP SW Description Slot 1 Other Slot 1 Other P_IRQ5 0 0 0 0 Pending mailbox IRQ bit 7 EN DPR Value Value Dual port RAM including mailbox stored in stored in bit 6 EEPROM EEPROM IRQ for VME requester enabled Base address fixed through BADRx bits EN BERR2 Enable bus monitor timer all VME bit 5 cycles timeout after 128Us FSD VMEbus First Slot Detection flag bit 4 system controller BADR3 Value Value VME address location of dual ported stored in stored in i l BADRO EEPROM EEPRoM RAM Equivalent to VME address lines bits 3 O A23 A20 programm
46. ontinuously reloaded via the 5V Stby line The 5V Stby current is typically 7mA for a few minutes when the Gold Caps are at the beginning of the loading phase fully empty May 17 1996 1995 PEP Modular Computers Page 2 21 Chapter 2 Functional Description VM62 A VM42 A User s Manual 2 9 Register Overview VME Interrupt Mask Register page 2 8 Address CS7 1 PEP Default Address CD 00 00 01 Format Byte Access read write Value after HW reset 0 Value after PEP SW initialization Value of EEPROM cer 1 VMEbus Control Status Register page 2 6 Address CS7 5 PEP Default Address CD 00 00 05 Format Byte Access read write Value after HW reset see table on page 2 6 7 6 5 4 3 2 1 0 0S7 5 Board Control Status Register page 2 14 Address CS7 7 PEP Default Address CD 00 00 07 Format Byte Access read write Value after HW reset 0 7 6 5 4 3 2 1 0 087 87 Page 2 22 1995 PEP Modular Computers May 17 1996 VM62 A VM42 A User s Manual Chapter 2 Functional Description May 17 1996 1995 PEP Modular Computers Page 2 23 VM62 A VMA2 A User s Manual Chapter 3 Configuration 9 3 CONFIGURATION The VM62 A VM42 A has twelve jumpers fitted to the board The list of default jumper settings is shown below Table 3 0 0 1 VM62 A VM42 A Default Jumper Settings Default Setting Description JI Set SYSCLR connected to VME J2 Set On board R
47. or RESET status Yellow LED Watchdog timer running status Green LED General purpose set via board control status register The green LED 1s free to be used by the customer It is set by the software during startup when the 68EN360 is initialized Page 2 20 1995 PEP Modular Computers May 17 1996 VM62 A VM42 A User s Manual Chapter 2 Functional Description 2 8 Data Retention for RTC and SRAM Short term data retention for RTC and SRAM is gained with two Gold Caps each with a value of 0 22 Farad In contrast to Lithium cells Gold Caps do not require servicing This short term backup is intended for short power failures or for reconfiguring systems An empty Gold Cap needs approximately three hours to charge up with backup times dependant on the temperature memory size and memory manufacturer tolerances A well charged Gold Cap provides a minimum of 10 hours backup time Laboratory tests at PEP indicate a typical backup time of week for both 256kB and IMByte SRAM plus RTC typical onboard backup current is 2UA Long term data retention is made via the VMEbus 5V Stby line With respect to the VM62 A VM42 A this voltage can drop to 2 5V with the typical current via the 5V Stby being 30UA at 3V Note The VM42 A VM62 A board can be removed from the system and then plugged in again without losing any information Data retention switches from the VME 5V Stby to the on board Gold Caps automatically The on board Gold Caps are c
48. r replaced parts reverts to PEP Modular Computers and the remaining part of the original guarantee or any new guarantee to cover the repaired or replaced items will be transferred to cover the new or repaired items Any extensions to the original guarantee are considered gestures of goodwill and will be defined in the Repair Report returned from PEP with the repaired or replaced item Other than the repair replacement or refund specified above PEP Modular Computers will not accept any liability for any further claims which result directly or indirectly from any warranty claim We specifically exclude any claim for damage to any system or process in which the product was employed or any loss incurred as a result of the product not functioning at any given time The extent of PEP Modular Computers liability to the customer shall not be greater than the original purchase price of the item for which any claim exists PEP Modular Computers makes no warranty or representation either express or implied with respect to its products reliability fitness quality marketability or ability to fulfill any particular application or purpose As a result the products are sold as is and the responsibility to ensure their suitability for any given task remains the purchaser s In no event will PEP be liable for direct indirect or consequential damages resulting from the use of our hardware or software products or documentation even if we were advised o
49. ra 6 Figure 5 2 3 1 SI I0B5 Front Panel Pinouts 6 24148 SEA RS232 DEDICO SPB232 Aue qd dece ER 3 3 4 934i 4 A3 Eo EAE Rd ded da 7 Figure 5 2 4 1 SI PB232 Front Panel Pinouts 7 242 Ethernet VO eset SI 10BT cross dama dod eig ESSE EEES EEES Da ce Ed 8 Figure 5 2 5 1 SI IOBT Front Panel Pinouts 8 3 20 PROFIBUS Interlace CSIE PBPRUD uua a ka Oe SS cons 463 574p CO RES PAS EE 9 Figure 5 2 6 1 SI PBPRO Front Panel Pinouts 9 6 Software Configuration 4 4 999 9 39 XO OROROR OX E o ses se 6 1 O1 TO EC the OS EN OU uada 6 eb RES dR EGS ad ace ere ESSE SSS delete ia l Bo TO RI CS nc beta be EE SO ee E E E E 419544 4 Appendix Controller eXtension Connector Appendix OS 9 Cabling Page 0 6 1995 PEP Modular Computers May 17 1996 VM62 A VM42 A User s Manual Chapter 1 Introduction 1 1 INTRODUCTION 1 1 Product Overview The computer user today requires high performance to meet high expectations At the same time the mass of data that has to be processed is dramatically increasing for instance the data that a modern graphic user interface generates Additionally there is a further demand on the communications ability and multi functionality of the computer The VM62 A VM42 A meets all the above requirements combining high computational performance with excellent communicat
50. rom the SCCs O Request to Send _RTS4 _RTS1 Request to send outputs indicate that the SCC is ready to transmit data O Clear to Send _CTS4 CTSI Clear to send inputs indicate to the SCC that data transmission may begin 7 Carrier Detect _CD4 CDI Carrier detect inputs indicate that the SCC should begin reception of data 7 Receive Start _RSTRTI This output from SCC1 identifies the start of a receive frame Can be used by an Ethernet CAM to perform address matching O Receive Reject RRJCTI This input to SCCI allows a CAM to reject the current Ethernet frame after it determines the frame address did not match 1 Clocks CLR8 CLRI Input clocks to the SCCs SMCs SI and the baud rate generators J IDMA DMA Request DREQ2 A request input to an IDMA channel to start an _DREQI IDMA transfer 1 DMA Acknowledge _DACK2 An acknowledgement output by the IDMA that an _DACKI IDMA transfer is in progress O DMA Done _DONE2 A bidirectional signal that indicates the last IDMA _DONEI transfer in a block of data 7 0 TIMER Timer Gate _TGATE2 An input to a timer that enables disables the counting _TGATEI function J Timer Input TIN4 TINI Time reference input to the timer that allows it to function as a counter J Timer Output _TOUT4 Output waveform pulse or toggle from the timer as a _TOUTI result of a reference value being reached O SPI SPI Master In SPIMISO Serial data input to the SPI master J serial data Slave Out output from an SPI sla
51. s BU2 and BU3 May 17 1996 1995 PEP Modular Computers Page 5 7 Chapter 5 Pinouts VM62 A VMA2 A User s Manual 5 2 5 Ethernet 10BaseT SI 10BT SITBT on board Figure 5 2 5 1 SI 10BT Front Panel Pinouts Collision Transmit 10BaseT Pin 8 BU3 RJ45 SCC1 Pin 1 ETHERNET S pin RJ45 Serial Interface Connector BU3 TD RD Not Connected Not Connected RD Not Connected Not Connected Configuration The SI IOBT piggyback has one configurable jumper that sets the shielding of the board The jumper settings are shown below Jumper J1 Shielding Setting Description 1 2 Shielded Default 1 3 Not Shielded Page 5 8 1995 PEP Modular Computers May 17 1996 VM62 A VMA2 A User s Manual Chapter 5 Pinouts 5 2 6 PROFIBUS Interface SI PBPRO SIPRO on board Figure 5 2 6 1 SI PBPRO Front Panel Pinouts Pin 1 BU3 SCC1 Pin 5 Pin 6 Pin 9 PROFIBUS Transmit Yellow 9 pin D Sub PROFIBUS Connector BUS Signal Description SHIELD Shield Protective Ground resp RP Reserved for power RxD TxD Receive Transmit Data CNTR Control DGND Data Ground VP Voltage Plus RP Reserved for power Receive Transmit 2 3 4 5 6 7 8 9 May 17 1996 Control 1995 PEP Modular Computers Page 5 9 Chapter
52. s Interface A24 D16 D8 Arbitration AM Codes A24 D16 Dual port SRAM I Mailbox IRQ Interrupt Control 7 Level VME IRQ Handler maskable via VME IRQ mask register System vectors May 17 1996 VM62 A VMA2 A User s Manual Chapter Introduction MC68060 66 or 50 MHZ 3 3V MC68040 33 or 25 MHZ MC68040V 33 or 25 MHZ 3 3V MC68LC040 33 or 25 MHz MC68EN360 25 or 33MHz used in companion mode 1 4 16 or 32 Mbyte 0 5 1 2 or 4 MByte 1 MByte or 256 kByte dual ported backed up using Gold Caps 2 kbit serial 1 kbit available for applications Master and slave with optional AutoBahn Interface 100 MBytes sec Single level BR3 release when done daisy chain Standard Superv User Prog Data HEX 39 3A 3D 3E User Defined HEX 10 17 18 1F Short I O HEX 29 2D System controller functions e Automatic First Slot Detection FSD e SYSRES disabled by jumper e SYSCLK disabled by jumper e ACFAIL e SYSFAIL e Power monitor e Bus monitor programmable e VME IRQ mask register Slave 1 Mbyte window software programmable base 1 out of 16 addresses Lower 8kBytes of the SRAM area ACFAIL gt Level 7 autovectored ABORT gt Level 7 autovectored TICK gt Level 6 autovectored SYSFAIL gt Level 3 autovectored maskable Mailbox IRQ gt Level 5 autovectored AutoBahn IRQ 2 gt Level 2 autovectored AutoBahn IRQ 1 gt Level autovectored 16 on board Interrupters Levels Vectors programmable
53. s Manual Brief Description of Changes PCB Index Date of Issue 01 0172 March 1995 Correction of Figure 3 2 0 1 Jumper Layout Solder Side 01 01 4 July 1995 Updated for board index 02 December 1995 General Corrections throughout Manual 01 01 4 June 1995 This document contains proprietary information of PEP Modular Computers It may not be copied or transmitted by any means passed to others or stored in any retrieval system or media without the prior consent of PEP Modular Computers or its authorized agents The information in this document is to the best of our knowledge entirely correct However PEP Modular Computers cannot accept liability for any inaccuracies or the consequences thereof nor for any liability arising from the use or application of any circuit product or example shown in this document PEP Modular Computers reserve the right to change modify or improve this document or the product described herein as seen fit by PEP Modular Computers without further notice Page 0 2 1995 PEP Modular Computers May 17 1996 VM62 A VMA2 A User s Manual Preface PEP Modular Computers Two Year Limited Warranty We grant the original purchaser of PEP products the following hardware and system warranty No other warranties that may be granted or implied by anyone on behalf of PEP are valid unless the consumer has the express written consent of PEP Modular Computers PEP Modular Computers warrants their own produc
54. s Manual The Ethernet port can be configured via the SI Interface with IOBaseT 10Base5 or 10Base2 SI Modules The following configurations are therefore possible for the serial ports Versions with Ethernet Port Port 68EN360 Resource Configured via Service Debug 1 SMCI Base board upper RJ12 Service Debug 2 SMC2 Base board lower RJ12 Ethernet SCCI Base board SI Module Full MODEM 2 SCC2 CXC Module Full MODEM 3 SCC3 CXC Module Full MODEM 4 SCC4 CXC Module The 10BaseX Modules do not make use of SCC4 and therefore can be used on the CXC Port Versions without Ethernet Port 68EN360 Resource Configured via Service Debug 1 SMCI Base board upper RJ12 Service Debug 2 SMC2 Base board lower RJ12 Full MODEM 1 SCCI Base board SI Module Full MODEM 2 SCC2 CXC Module Full MODEM 3 SCC3 CXC Module Full MODEM 4 SCC4 Base board SI Module or CXC Module Can only be used once 2 5 3 CXC Interface The Controller Extension Connector CXC is a local mezzanine interface The CXC contains a 16 bit data bus 7 address lines and 8 decoded chip select lines In total there are 8 control signals The base address of the CXC can be programmed via the CSS line of the 68EN360 The 8 CXC chip selects CXC_CSO CXC_CS7 occupy 256 Bytes each and have an address length of 400H 512 Bytes Furthermor
55. s completely reprogrammable a special boot decoder is provided The boot memory is jumper selectable the user having the choice between FLASH default VMEbus memory or the on board AutoBahn Interface The boot decoder redirects the physical address range OH to 1000000H from either FLASH DM60x VMEbus or MP piggyback providing the selected boot memory is initially accessed Note VMEbus boot memory must be located at VME base address OH in Standard Supervisor Program Data address space Page 2 2 1995 PEP Modular Computers May 17 1996 VM62 A VM42 A User s Manual Chapter 2 Functional Description 2 2 3 Primary Address Decoder The primary address decoder generates the following select signals Secondary address decoder 68EN360 DRAM FLASH VMEbus address range AutoBahn Interface address range Bussizer address range VME SRAM AutoBahn I O Reserved address range Bus Error 68EN360 DMA address range Interrupt Acknowledge Cycle 2 2 4 Secondary Address Decoder The secondary address decoder is built by the 68EN360 chip select logic and is therefore programmable The outputs are used as base address selects as shown below 68EN360 Chip Select Connected to CSO FLASH CS1 DRAM CS2 VME via 68EN360 DMA CS3 AutoBahn Interface CS4 SRAM CS5 CXC CS6 RTC CS7 Control Status Registers May 17 1996 1995 PEP Modular Computers Page 2 3 C
56. ts excluding software to be free from defects in workmanship and materials for a period of 24 consecutive months from the date of purchase This warranty is not transferable nor extendible to cover any other consumers or long term storage of the product This warranty does not cover products which have been modified altered or repaired by any other party than PEP Modular Computers or their authorized agents Furthermore any product which has been or is suspected of being damaged as a result of negligence misuse incorrect handling servicing or maintenance or has been damaged as a result of excessive current voltage or temperature or has had its serial number s any other markings or parts thereof altered defaced or removed will also be excluded from this warranty A customer who has not excluded his eligibility for this warranty may in the event of any claim return the product at the earliest possible convenience together with a copy of the original proof of purchase a full description of the application it is used on and a description of the defect to the original place of purchase Pack the product in such a way as to ensure safe transportation we recommend the original packing materials whereby PEP undertakes to repair or replace any part assembly or sub assembly at our discretion or to refund the original cost of purchase if appropriate In the event of repair refund or replacement of any part the ownership of the removed o
57. ull down resistor at the BG3IN pin BG3IN low system controller far left slot BGSIN high no system controller This information can be read from the VMEbus Control Status register and is valid until the next power down of the system Page 2 18 1995 PEP Modular Computers May 17 1996 VM62 A VM42 A User s Manual Chapter 2 Functional Description 2 6 8 Board Control Status Register Address CS7 7 PEP Default Address CD 00 00 07 Format Byte Access read write Value after HW reset 0 7 6 5 4 3 2 1 0 087 87 Register Description Access Description Read Write Set by watchdog timer when timout has been reached Used to differentiate between resets caused by the watchdog and resets caused by the reset button power up resets can be identified within the 68EN360 BERR2 Read Write Set by VMEbus BUS monitor when timeout has been bit 6 reached Used to identify BERR caused by this timer see also VMEbus Control Status register BERRI Read Write Set by on board bus error timer when timeout has been bit 5 reached Used to identify BERR caused by this timer EN_WDG Read Write Enable the watchdog timer It can only be set once and bit 4 remains enabled until the next reset TR_WDG Read Write Triggers the watchdog timer Watchdog timeout 512ms bit 3 EN BERRI Read Write Enables the on board bus error timer It also monitors all on bit 2 board I O cycles including the time from the VMEbus requ
58. ve O SPI Master Out SPIMOSI Serial data output from the SPI master O serial data Slave In input to an SPI slave 7 SPI Clock SPICLK Output clock from the SPI master O input clock to the SPI slave 7 SPI Select _SPISEL SPI slave select input 1 SMC SMC Receive Data SMRXD2 Serial data input to the SMCs 7 SMRXDI SMC Transmit Data SMTXD2 Serial data output from the SMCs O SMTXDI SMC Sync _SMSYN2 SMC syncronization signal _SMSYNI May 17 1996 1995 PEP Modular Computers Page 2 15 Chapter 2 Functional Description VM62 A VM42 A User s Manual Group Signal Name Mneumonic Function SI SI Receive Data LIRXDA Serial input to the Time Division Multiplexed TDM LIRXDB channel A or channel B SI Transmit Data LITXDA Serial output from the TDM channel A or channel B LITXDB SI Receive Clock LIRCLKA Input receive clock to TDM channel A or channel B LIRCLRB SI Transmit Clock LITCLRA Input transmit clock to TDM channel A or channel B LITCLRB SI Transmit Sync LITSYNCA Input transmit data sync signal to TDM channel A or Signals LITSYNCB channel B SI Receive Sync LIRSYNCA Input receive data sync signal to TDM channel A or Signals LIRSYNCB channel B IDL Interface LIRQA LIRQB IDL interface request to transmit on the D channel Request Output from the SI SI Output Clock LICLKOA Output serial data rate clock Can output a data rate LICLROB clock when the input clock is 2x the data rate SI

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