USER'S MANUAL - Oho
Contents
1. MUrSIUg o E 2 X P o is e gt E 5 kan oe 3 2 E amp T O IE ENEDIN GOP XC3S200 USER S MANUAL V1 2 onsdnd OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 12 Module Layout Top View CON3 H14 2MM TPS76325DBU nm TOBDX Ics XCF8018 SLO ZHNZST BE Ra _ 22 54 8 C4 C24 41 Bgt UBBT Br Ar mm oS WEN 960101 86670 031 037 0d DT z9 3 9e EGU zou 733 Tr 558 Up 1 Mos 8031 B EB u SU 0 0 1 6810 5031 7731 94r vu a R m 488 4 4b7 C25 18 140n 5 4 7u 470 4k7 470 nez 429 2 4 6 8 1012 14 10 CON2 O 1 x 2 2 aids BG o C2 D 3 3 ggg GOP XC3S200 USER S MANUAL V1 2 Page 25 of 29 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 13 Module Layout Bottom View TO LENS 6ZNS O Ics R1LUB408CSA MINISMDCQ75 T Li Mi A e D14 BATSAAW CON1 DILSND_N24 i 531 6 1 832. eal 1 83 EG E E mDuturztrttrtt GOP XC3S200 USER S MANUAL V1 2 Page 26 of 29 OHO Elektronik Rudolf Diesel Str 8 gt D 85221 Dachau Germany www oho elektronik de 14 Technical Specifications FPGA Xilinx XC3S200 4VAG100C Spartan 3 FPGA Supply Voltage on PIN24 3 5 5 5V Size 47x 23 5mm 1 85 x 0 925 Height PCB to Top max 8mm 0 315 Height PCB to Bottom max 12mm 0 472 Weight 12g GOP XC3S200 USER S MANUAL V1 2 Page 27 of 29 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 15 Literature gt 1 DS099 Spartan 3 Complete Data Sheet http www xilinx com support documentation data sheets ds099 pdf gt 2 DS097 Xilinx Parallel Cable IV http www xilinx com support documentation data sheets ds097 pdf gt 8 DS300 Platform Cable USB http www xilinx com support documentation data_sheets ds300 paf gt 4 DS593 Platform Cable USB II http www xilinx com support documentation data_sheets ds593 paf gt 5 L6925 High Efficiency Monolithic Synchronious Step Down Regulator http www st com stonline products literature ds 9301 16925d pdf 6 TPS76325 Low Power 150mA Low Dropout Linear Regulators http focus ti com lit ds symlink tps76325 pdf gt 7 TPS73233 Cap Free NMOS 250mA Low Dropout Regulator With Reverse Current Protection http focus ti com lit ds symlink tps73233 pdf gt 8 SN74CB3T 3245
3. AIL SWL 101 MJ INO 00 Tdf OWS TG GNZION ENEIIN 3 ENEIIN zv ENEJIN E cab TH 3 5 631 ENEJDIN TNDI S BOUHSINIH 5 to 1I cH NIG ENEIIN UNI GrCELESOV c Page 23 of 29 GOP XC3S200 USER S MANUAL V1 2 9TdGZW 40 shey sbueo 8dGZW 40 shex pos 8 55 45 VE ET TO 680072 80 9T NA ONS 4equnwN aiueunoo g gr JOC EdSdO9 41111 3D F NYHOVO Tzz98 4ejouzrepuew hg ubrs q 8 AS T s rq Iopnui MINOR LAAT3 0HO Page 24 of 29 MYbalud eva 1 4 al i Ma EX x ata a d 9g Ber 222 nue alr gag Ma Gl g TT 60 Ber Baro MurSlug 229 fs Ber QOO BAITUT 222 2 ese Oct 222 o i 258 250 TZNId 900cr rprz UNM TI 067671 3NOU Fr 8TNId bs N ls IND ZATION x1 ON9 j 3 3N San INAS HOD 081 81 IND jis 5 1 IN e Sa tg UQBT NEOSTESZSdL azo peer 83 3N N3 819 UNI ANGOIN ENEIIN GNZOIN ino NI 41 8 MUrS IUS SNTIIN EEZEZSCIL y Ssvd4g N3 UNI 83 jjer
4. 22 l O L31N 1 LS22 pin22 Connection to FPGA pin 86 via level shifter CON pin22 pin18 23 GCLK5 LS23 pin23 Connection to FPGA pin 88 via level shifter CON pin23 pin19 24 PIN 24 5V input voltage to the module GOP XC3S200 USER S MANUAL V1 2 Page 21 of 29 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 10 CON1 DIL Connector Layout GOP XC3S200 module top view for 24 pin and 20 pin emulation mode lt 23 5 mm gt 23 5 mm gt 24 PINS 000000000 TOP VIEW O PIN24 PIN23 PIN22 O PIN21 PIN28 PIN1S PIN18 Q PIN17 Q PIN16 Q PIN15 Q PIN14 PIN13 lt 4 7 mm O PIN20 PIN19 O PIN18 PIN17 O PIN16 O 45 O PIN14 PIN13 O PIN12 PIN11 47 mm D GOP XC3S200 USER S MANUAL V1 2 Page 22 of 29 o o eS 9 o E gt o gt o a LO ks Q co XE on o lt 3 gt o xD pa O Z T naauS NOHIVA TccS8 49 e5T1 0Png ve Eli La 69002 80 91 NEO SGUNN iuasunoo JOU EdSd09 28 1111 49jouz epueg hg ubisag MINOdLM414 0H0 l ENDI MIS Al 1 CY m E5 g HO LIANNDI 91r Sr CNTIIN 0 1 O T 60 10 cu prO O LIN by tr v ev bY 9t Ze
5. Connection to FPGA pin 16 via level shifter CON1 pind pind 6 I O_L40N 6 LS6 pin6 Connection to FPGA pin 14 via level shifter CON pin6 pin6 7 O P17 LS7 pin7 Connection to FPGA pin 17 via level shifter CON1 pin7 pin7 8 l O L24P 6 LS8 pin8 Connection to FPGA pin 15 via level shifter CON pin8 pin8 9 l O P21 LS9 pin9 Connection to FPGA pin 21 via level shifter CON1 pin9 pin9 10 VO 101 6 LS10 pin10 Connection to FPGA pin 22 via level shifter CON pin10 pin10 11 I O_LO1N 6 LS11 pin11 Connection to FPGA pin 23 via level shifter CON1 pin11 12 GND GND Power ground plane connection 13 GCLK1 LS13 pin13 Connection to FPGA pin 39 via level shifter CONI pin13 14 I O_LO1N 3 LS14 pin14 Connection to FPGA pin 54 via level shifter CON1 pin14 15 l O P17 LS15 pin15 Connection to FPGA pin 55 via level shifter CON pin15 pin11 16 1 0 140 3 LS16 pin16 Connection to FPGA pin 62 via level shifter CON 16 pin12 17 l O L24P 3 LS17 pin17 Connection to FPGA pin 60 via level shifter CON pin17 pin13 18 1 0 L24N 3 LS18 pin18 Connection to FPGA pin 61 via level shifter CON pin18 pin14 19 O P59 LS19 pin19 Connection to FPGA pin 59 via level shifter CON 19 pin15 20 WO L31P 1 LS20 pin20 Connection to FPGA pin 85 via level shifter CON pin20 pin16 21 GCLK4 LS21 pin21 Connection to FPGA pin 87 via level shifter CON pin21 pin17
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7. 8 Bit Fet Bus Switch http focus ti com lit ds symlink sn74cb3t3245 pdf gt 9 M25P80 http www numonyx com Documents Datasheets M25P80 pdf 10 M25P16 http www numonyx com Documents Datasheets M25P16 pdf GOP XC3S200 USER S MANUAL V1 2 Page 28 of 29 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 16 Assembly variants In newer batches of GOP XC3S200 modules a M25P16 serial flash will be assembled It s a 16Mbit flash instead of the former 8Mbit flash If your application still needs 8Mbit flash on the GOP_XC3S200 module please order the particular 8Mbit version it is still available 17 USER S MANUAL Revisions Version Date Comments V0 9 23 10 2005 Prerelease V1 0 19 04 2009 First Release minor edits V1 1 21 07 2009 Pictures with OHO DY1 modules V1 2 16 08 2009 Small corrections GOP XC3S200 USER S MANUAL V1 2 Page 29 of 29
8. of an VQ100 package some of the SRAM I Os are shared with other resources of the GOP XC3S200 module e 8 address lines of the SRAM are connected to 8 user leds These leds can be enabled by jumper CON 9 10 9 3 address lines of the SRAM share the SPI FLASH signals SCK SI SO It is up to the user to care about proper multiplexing and tristating of these signals when all affected resources are used GOP XC3S200 USER S MANUAL V1 2 Page 10 of 29 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 3 2 Test connector 7 Os are available to the front side test connector CON4 2 I Os are connected via level shifters TP8 and 5 I Os are directly connected to the FPGA TP2 TP3 TP4 TP5 TP6 PLEASE NOTE TP2 TP3 TP4 TP5 and TP6 do not have series resistors and so are not 5V tolerant Pin 6 of CON4 TP6 one of the non 5V tolerant contacts accesses global clock net GCLK2 Pin 7 of CON4 TP7 one of the 5V tolerant contacts accesses global clock net GCLK3 The test connector is primarily intended for probes of an oscilloscope or logic analyser But since a power supply is also provided on the connector it is ideally suited for small hardware extensions or debug modules like the 3 digit OHO_DY1 display module GOP XC3S200 USER S MANUAL V1 2 Page 11 of 29 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 3 3 JTAG Port Configur
9. out from XOSC1 39 GCLK1 LS13 pini3 Connection to the 24pin DIL plug to pin13 via level shifter LS pin 16 Not used for the 20pin DIL plug CON1 pin13 This is also an input to the global clock net GCLK1 40 DOUT DOUT sa lt 0 gt Multiple function pin SRAM pini Address sa0 input for SRAM FLASH pin5 Serial data input for FLASH 41 GND GND Gonnection to the GND Layer of the PCB 42 INIT INIT sa lt 4 gt Multiple function pin XCF01 ping FPGA configuration FLASH reset SRAM pin9 Address sa4 input for SRAM gt EN en se SRAM chip select has an external pullup R4 oe VO ON UM Soe SRAM output enable has an external pullup R1 45 VCCINT VCC1V2 Internal core Voltage 1 2V 46 VCCO 4 VCC3V3 LVCMOS33 LVTTL I O Voltage 3 3V 47 VO L27P 4 1047 tp8 Testconnector CON4 pin 8 via level shifter IC3 pin15 48 DIN DIN sa lt 2 gt Multiple function pin SRAM 6 Address sa2 input for SRAM FLASH pin2 Serial data output from FLASH 49 1 0 LO1P 4 1049 fcs FLASH chip select has an external pullup R18 50 1 0 LO1N 4 1050 sa lt 9 gt Sram address input A9 SRAM pin2 6106 51 DONE DONE FPGA configuration ready strobe 1 fpga configured 52 CCLK CCLK FPGA configuration clock 53 WO 01 3 1053 58 lt 15 gt Sram address input A15 SRAM pin3 Led7 54 0 LO1N 3 LS14 pini4 Connection to the 24pin DIL plug to pin14 via level shifter CON1 pin14 Not used for the 20pin DIL plug 55 O P17 LS15 pin15 Conne
10. pin mode of the module a 24 pin socket should be used e In 20 pin mode of the module a 20 pin socket should be used Please insure that pin 1 of the module is always pin 1 of a socket In the 20 pin mode an additional GND connection must be done via a 2mm jumper on jumper block CONS at position 1 2 see Layout Top View This adds GND to pin 10 For cases where additional GND connections are desired Pins 3 14 and 23 can be shorted to GND with solder jumpers JP1 JP3 JP2 respectively on the bottom side of the module These shorts should be soldered using a stereo microscope to insure that there are no other unwanted connections 4 FPGA Design Support VHDL and UCF design templates for 20 and 24 pin configurations are available GOP XC3S200 USER S MANUAL V1 2 Page 14 of 29 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 5 About GOP XC3S200 I O Voltage Levels The Spartan3 FPGA series offer a broad variety of I O voltage standards However on the GOP XC3S200 only the LVCMOSS3 and LVTTL standards are supported These standards are required for the level shifters 8 for conversion of pulluped 5V TTL levels as well as 5V CMOS levels These level shifters work bidirectionally without the need of controlling their direction Please note that the level shifter devices reduces the ability of the FPGA 1 Os to source current sink current is not affected The level shifters introduce a de
11. s have higher jitter than PLLs Vv VV VVV WV GOP XC3S200 USER S MANUAL V1 2 Page 6 of 29 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 2 5 GOP XC3S200 Board Pictures Top And Bottom View 111116 I VTT V TVT a a M 1443 Ame osa qu UPN T BARARRAAAARARAAAARARAAAA Ea NBD LI US HE E GOP XC3S200 USER S MANUAL V1 2 Page 7 of 29 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 2 6 XCS3S200 Board In A Lab Environment 2 7 XC3S200 Board with 5 stacked OHO DY1 modules GOP XC3S200 USER S MANUAL V1 2 Page 8 of 29 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 3 GOP XC3S200 Board Overview 2mm 14pin JTAG PORT CON3 0000000 9000000 L JP2 JP3 2 14 1 o 00 0000 00000000 H NH 9000000 E 2mm 14pin 2 54mm 9pin Solder Jumper Jumper Block Test Connector For Additional Ground CON2 CON4 Connections GOP XC3S200 USER S MANUAL V1 2 Page 9 of 29 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 3 1 YO Distribution 22 1 Os of the Xilinx XC3S200 4VQG100C FPGA are wired to a 24 pin DIL socket plug on the bottom of the module through level shifter devices
12. 74CB3T3245 which makes the FPGA I Os tolerant to input voltages up to 7V Pins 1 2 13 21 and 23 of the DIL plug access global clock nets GCLK6 GCLK7 GCLK1 GCLK4 and GCLK5 inside the FPGA These clock nets also can be used as general purpose I Os Please note that the level shifter devices reduces the ability of the FPGA I Os to source current but sink current is not affected As an option pullups to 5V can be enabled on pin 1 to pin 13 and pin 14 to pin 23 separately by setting jumpers on CON2 11 12 and 13 14 respectively Another point to note is that as long as the FPGA is not configured the DIL pins are disconnected from the FPGA they are floating This could be altered by RJ3 A crystal oscillator with an output frequency of 49 152MHz is connected to GCLKO of the FPGA This oscillator can be disabled completely by removing the jumper to its power supply at jumper block CON2 position 3 4 2 I Os are connected to user tactile switches SW1 and SW2 SW1 is a freely available while SW2 also reprogramms the FPGA if jumper CON 7 8 is set In this case reprogramming the FPGA is also possible by 1 028 Simply output a on this pin tristate otherwise Please do not output a 1 on this pin because this drives a 3 3V level to the 2 5V supply by the I O diode at signal PROG 8 30 FPGA I Os are connected to an asynchronous SRAM device organized as 512kByte x 8 with an access time of 55ns Due to the limited amount of I Os
13. 7P 4 1047 tp8 Testconnector CON4 pin 8 via level shifter to FPGA pin47 FPGA pin47 B S B 5V input voltage protected by a polyfuse 8 CON2 Configuration Jumper Options 1 2 Enable 20pin PAL GAL Emulation put GND to pin 10 of CON1 3 4 Enable XOSC1 crystal oscillator 49 152 MHz 5 6 Enable FPGA configuration from Platform FLASH otherwise JTAG only 7 8 Enable reprogram of the FPGA by SW2 or IO28 9 10 Enable User Leds 11 12 Enable pullups on Pint Pin2 Ping Pin4 Pin5 Pin6 Pin7 Ping Pin9 Pin10 Pin11 Pin13 to 5V or rather the voltage at Pin 24 of the module 13 14 Enable pullups on Pin14 Pin15 Pin16 Pin17 Pin18 Pin19 Pin20 Pin21 Pin22 Pin23 to 5V or rather the voltage at Pin 24 of the module GOP XC3S200 USER S MANUAL V1 2 Page 20 of 29 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 9 CON1 DIL Connector Pinout Table Pin FPGA pin Schema UCF function net name port Comment i routed to name 1 GCLK6 LS1 pint Connection to FPGA pin 89 via level shifter CONI pini pint 2 GCLK7 LS2 pin2 Connection to FPGA pin 90 via level shifter CON pin2 pin2 3 l O L31N 0 LS3 pin3 Connection to FPGA pin 92 via level shifter CON1 ping pin3 4 1 0 L31P 0 LS4 pin4 Connection to FPGA pin 91 via level shifter CON pin4 pin4 5 WO L24N 6 LS5 pin5
14. GOP_XC3S200 USER S MANUAL 1 2 OHO Elektronik www oho elektronik de Author M Randelzhofer OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de OHO Elektronik Michael Randelzhofer Rudolf Diesel Str 8 85221 Dachau Germany WEB www oho elektronik de EMAIL info oho elektronik de Phone 49 8131 339230 FAX 449 8131 339294 2005 2009 OHO Elektronik Michael Randelzhofer All rights reserved Disclaimer Under no circumstances OHO Elektronik Michael Randelzhofer is liable for conseguential costs losses damages lost profits Any schematics pcb or program parts are under the copyright of OHO Elektronik Michael Randelzhofer and can only be reproduced by permission of this company The contents of this USER S MANUAL are subject to change without notice However the main changes are listed in the revision table at the end of this document Products of OHO Elektronik Michael Randelzhofer are not designed for use in life support systems where malfunction of these products could result in personal injury The products of OHO Elektronik Michael Randelzhofer are intended for use in a laboratory test environment or for OEM s only They can generate radio freguency energy depending on the downloaded design and application which can disturb local radio or TV eguipment and so they have not been tested to be CE compliant If you encounter any technical problems or mist
15. PCB 11 0 140 7 1011 sd lt 5 gt Sram data I O bit5 SRAM pin27 12 l O L40N 7 1012 sd lt 6 gt Sram data I O bit6 SRAM pin28 13 0 L40P 6 1013 sd lt 7 gt Sram data I O bit7 SRAM pin29 14 I O_L40N_6 LS6 pin6 Connection to the 20 24pin DIL plug to pin6 via level CON1 pin6 pin6 shifter 15 0 L24P 6 LS8 pin8 Connection to the 20 24pin DIL plug to pin8 via level CON1 ping pin8 shifter 16 1 0 L24N 6 LS5 pin Connection to the 20 24pin DIL plug to pind via level CON1 pin5 pin5 shifter 17 O P17 LS7 pin7 Connection to the 20 24pin DIL plug to pin7 via level CON1 pin7 pin7 shifter 18 VCCINT VCC1V2 Internal core Voltage 1 2V 19 VCCO 6 VCC3V3 LVCMOS33 LVTTL I O Voltage 3 3V 20 GND GND Connection to the GND Layer of the PCB 21 O P21 LS9 pin9 Connection to the 20 24pin DIL plug to pin9 via level CON1 ping pin9 shifter 22 0 LO1P 6 LS10 pin10 Connection to the 24pin DIL plug to pin10 via level shifter CON pin10 pin10 Short to GND by CON 1 2 for 20pin DIL plug 23 0 LO1N 6 LS11 pin11 Connection to the 24pin DIL plug to pin11 via level shifter CONI pin11 Not used for the 20pin DIL plug 24 M1 M1 FPGA configuration mode bits GND M1 is connected to GND via R2 25 MO MO FPGA configuration mode bits 1 JTAG 0 conf FLASH M2 MO is connected to M2 via R7 CON pin6 Can be set to GND by CON2 jumper 5 6 26 M2 M2 FPGA configuration mod
16. S22 pin22 Connection to the 24pin DIL plug to pin22 via level shifter CON pin22 pin18 Connection to the 20pin DIL plug to pin18 via level shifter 87 GCLK4 LS21 pin21 Connection to the 24pin DIL plug to pin21 via level shifter CON pin21 pin17 Connection to the 20pin DIL plug to pin17 via level shifter 88 GCLK5 LS23 pin23 Connection to the 24pin DIL plug to pin23 via level shifter GOP XC3S200 USER S MANUAL V1 2 Page 18 of 29 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de CON pin23 pin19 Connection to the 20pin DIL plug to pin19 via level shifter 89 GCLK6 LS1 pint Connection to the 20 24pin DIL plug to pini via level CONI pini pint shifter 90 GCLK7 LS2 pin2 Connection to the 20 24pin DIL plug to pin2 via level CON pin2 pin2 shifter 91 0 L31P 0 LS4 pin4 Connection to the 20 24pin DIL plug to pin4 via level CON1 pin4 pin4 shifter 92 I O_L31N_0 LS3 pin3 Connection to the 20 24pin DIL plug to pin3 via level CON ping pin3 shifter 93 VCCINT VCC1V2 Internal core Voltage 1 2V 94 VCCO 0 VCC3V3 LVCMOS33 LVTTL I O Voltage 3 3V 95 GND GND Connection to the GND Layer of the PCB 96 0 LO1P 0 396 sa lt 13 gt Sram address input A13 SRAM pin18 Led5 97 WO LO1N 0 1097 58 lt 14 gt Sram address input A14 SRAM pin19 Led6 98 HSWAP EN HSWAP FPGA configuration signal put t
17. a mini module composed of an FPGA device and a configuration memory with a PAL GAL compatible 24 pin DIL footprint Many additional features make it useful and flexible 2 1 GOP XC3S200 Features XC3S200 4VAG100C FPGA a member of the XILINX Spartan 3 family Xilinx XCFO1S Platform Flash configuration device Xilinx Parallel Cable IV or Platform USB Cable compatible download connector 14pin 2mm an OHO Elektronik low cost programmer is also available 4 Mbit SRAM 512k x 8 tAC 55ns 8 or 16 Mbit user SPI FLASH 9 10 Operating voltage from 3 5V to 5 5V switching regulator for core voltage 1 2V Voltage translators for 5V I O compatibility selectable pullups to 5V Onboard Clock oscillator with 49 152 MHz for audio or RS232 applications 2 status leds 8 low current user leds 2 user tact switches 7 configuration jumper A 9 pin test connector for probing internal signals or interconnecting several GOP s Reverse plug in protection solder jumpers for additional ground connections Easy to reuse Professional design manufactured on a 6 layer PCB made in Germany GOP XC3S200 Applications VVVVVVVVVV VV WV Upgrade from PAL GAL devices redesigns Fast evaluation of Xilinx Spartan 3 FPGA s Hardware platform for VHDL VERILOG logic design courses Robotics High logic density applications at tight space constraints vy v v v v GOP XC3S200 USER S MANUAL V1 2 Page 5 of 29 OHO Elektronik Rudolf Diesel St
18. akes in this document please contact mrandelzhofer oho elektronik de serious hints are very appreciated Trademarks All brand names or product names mentioned are trademarks or registered trademarks of their respective holders PAL and GAL are registered trademarks of Lattice Semiconductor Corp GOP XC3S200 USER S MANUAL V1 2 Page 2 of 29 OHO Elektronik Rudolf Diesel Str 8 gt D 85221 Dachau Germany www oho elektronik de 1 Table of contents 1 Table Ot COntents uu u u E Ba amami EA A EEE TA RAN a REE 3 2 IMO OU COM u ea ne a Na aa aaa RA mD Ne a 5 21 GOP XG35200 Features sic Ko oo Wo meneh bau uM GM E 5 2 2 GOP XC33200 Applicaton ies cita aksara slama 5 2 3 Xilinx XC3S200 Features ooo W W Woo om Wan 6 2 4 Xilinx XC3S200 DisadvantageS ooooo oWo mo WoW oom mm mann 6 2 5 GOP XC3S200 Board Pictures Top And Bottom View oooooo W Woo WWW 7 26 GOP XC3S200 Board In A Lab Environment 8 2 7 GOP XC3S200 Board with 5 stacked OHO DY1 modules 8 3 GOP XC3S200 Board Overview oooo o W W Wo Woo WWW aan 9 3 1 YO Distribution NOON 10 3 2 WEST CR Er sa in utate tm nut Ka Kn kaa alan kan 11 99 TAG Pore st ae in tes u eaaa d E 12 34 PowerSu
19. ation of the FPGA is done by the Platform FLASH device XCFO1S if jumper CON2 5 6 is set Additionally the FPGA can be programmed through the JTAG port as well The platform FLASH device is also programmed by the JTAG interface The 2 devices FPGA and Plattform FLASH are connected in a JTAG chain The FPGA is the first device in the chain the Platform FLASH is the second The configuration status of the FPGA is shown by the red status led2 and the green status led1 If the FPGA is not configured red led2 is lit and the green led1 is dark If the FPGA is configured green led1 is lit and the red led2 is dark The FPGA JTAG chain is routed to the Xilinx standard 2mm 14pin JTAG port connector CONS by serial resistors enabling JTAG programming with 3 3V voltage levels The 2mm connector is supported by the parallel cable IV and platform USB cables see 2 and 3 Please notice the pin orientation of JTAG port CONS AMF EERE E iin m m els T TT 8 NN E LB l O 2 O 2 4 6 8 1012 14 4 2 5 7 83 1113 GOP XC3S200 USER S MANUAL V1 2 Page 12 of 29 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 3 4 Power Supply The module can be powered with supplies from 3 5 to 5 5 volts since core and auxiliary voltages are generated with on board regulators Standard connection for the supply is at DIL pin 24 while GND is on pin 12 in 24 p
20. ayer of the PCB 67 VO L24P 2 1067 sa lt 10 gt Sram address input A10 SRAM pin31 68 0 L24N 2 1068 sa lt 5 gt Sram address input A5 SRAM pin10 69 VCCINT VCC1V2 Internal core Voltage 1 2V 70 VCCO 2 VCC3V3 LVCMOS33 LVTTL I O Voltage 3 3V 71 VO L21P 2 1071 sa lt 6 gt Sram address input A6 SRAM pin11 72 VO_L21N_2 1072 sa lt 8 gt Sram address input A8 SRAM pin12 73 GND GND Connection to the GND Layer of the PCB 74 0 LO1P 2 1O74 58 lt 17 gt Sram address input A17 SRAM pin16 Led10 75 MO LO1N 2 1075 58 lt 16 gt Sram address input A18 SRAM pin15 Led9 76 TDO FTDO FPGA JTAG chain XCF01 pin4 FPGA TDO is connected to XCFO1 TDI 77 TCK FTCK FPGA JTAG chain XCF01 pin6 JTAG TCK via serial resistor to support 3 3V download CONS pin6 adapter 78 TMS FTMS FPGA JTAG chain XCF01 pind JTAG TMS via serial resistor to support 3 3V download CON3 pin4 adapter 79 0 01 1 379 sa lt gt Sram address input A7 SRAM pin13 80 l O LO1N 1 1080 sa lt 9 gt Sram address input A9 SRAM pin14 81 O P81 1081 sa lt 11 gt Sram address input A11 SRAM pin17 Led3 82 GND GND Connection to the GND Layer of the PCB 83 VCCO 1 VCC3V3 LVCMOS33 LVTTL I O Voltage 3 3V 84 VCCAUX VCC2V5 VCCAUX must be 2 5V 85 0 L31P 1 LS20 pin20 Connection to the 24pin DIL plug to pin20 via level shifter CON pin20 pin16 Connection to the 20pin DIL plug to pin16 via level shifter 86 l O L31N 1 L
21. ction to the 24pin DIL plug to pin15 via level shifter CON pin15 pin11 Connection to the 20pin DIL plug to pin11 via level shifter 56 GND GND Connection to the GND Layer of the PCB 57 VCCO 3 VCC3V3 LVCMOS33 LVTTL I O Voltage 3 3V GOP XC3S200 USER S MANUAL V1 2 Page 17 of 29 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 58 VCCAUX VCC2V5 VCCAUX must be 2 5V 59 O P59 LS19 pini9 Connection to the 24pin DIL plug to pin19 via level shifter CON pin19 pin15 Connection to the 20pin DIL plug to pin15 via level shifter 60 0 L24P 3 LS17 pin17 Connection to the 24pin DIL plug to pin17 via level shifter CON pin17 pin13 Connection to the 20pin DIL plug to pin13 via level shifter 61 W O L24N 3 LS18 pini8 Connection to the 24pin DIL plug to pin18 via level shifter CON pin18 pin14 Connection to the 20pin DIL plug to pin14 via level shifter 62 0 L40P 3 LS16 pin16 Connection to the 24pin DIL plug to pin16 via level shifter CON 16 pin12 Connection to the 20pin DIL plug to pin12 via level shifter 63 L40N 3 1063 sa lt 1 gt Sram address input A1 SRAM pin4 64 0 L40P 2 1064 swr Sram write enable SRAM pin5 65 l O L40N 2 1065 sa lt 3 gt Sram address input A3 SRAM pin7 66 GND GND Connection to the GND L
22. e bits 1 JTAG 0 conf FLASH MO M2 is connected to MO via R7 CON pin6 Can be set to GND by CON jumper 5 6 27 WO 01 5 1027 sw1 User tact switch1 shorts I027 to GND via 1000 serial SWI resistor needs pullup inside the FPGA GOP XC3S200 USER S MANUAL V1 2 Page 16 of 29 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 28 LO1N 5 1028 sw2 User tact switch2 shorts 1028 to GND via 1000 serial SW2 resistor needs pullup inside the FPGA Jumper CON2 7 8 enables reconfiguration by SW2 29 GND GND Connection to the GND Layer of the PCB 30 l O L28P 5 tp2 tp2 Testconnector CONA pin 2 not 5V tolerant 31 VCCO 5 VCC3V3 LVCMOS33 LVTTL I O Voltage 3 3V Alternatively 2 5V selectable by solder jumper RJ1 32 l O L28N 5 tp3 tp3 Testconnector CONA pin 3 not 5V tolerant 33 VCCAUX VCC2V5 VCCAUX must be 2 5V 34 I O_L381P_5 tp4 tp4 Testconnector CON4 pin 4 not 5V tolerant 35 MO L31N 5 55 tp5 Testconnector CONA pin 5 not 5V tolerant 36 GCLK2 tp6 tp6 Testconnector CON4 pin 7 not 5V tolerant This is also an input to the global clock net GCLK2 37 GCLK3 GIO37 tp7 Testconnector CON4 pin 7 via level shifter LS pin14 This is also an input to the global clock net GCLK3 38 GCLKO OSC osc Global clock net input GCLKO 49 152MHz clock input XOSC1
23. in mode In 20 pin mode pin 20 is used for VCC and pin 10 for GND An onboard switching voltage regulator produces the FPGA core voltage of 1 2V The regulator 5 can source up to 800mA Another low drop regulator generates the VCCAUX voltage of 2 5V sourcing up to 150mA 6 And finally a 250mA low drop regulator is responsible for the I O voltage of 3 3V 7 The module has a protection against reverse insertion or reverse power connection In that case the protection shorts the power supply by a polyfuse device The polyfuse recovers after deactivation of the power supply Burn through cycles of the polyfuse are limited For more information please consult the data sheet Even so care should be taken when plugging the module Consider that a short pulse of several amps can damage the environment in which the module is inserted ATTENTION Please note that a voltage above 6V on the module pins 12 and 24 will destroy the voltage regulators on the module Especially the switching regulator is sensitive to overvoltage Therefore the maximum of 5 5V module supply voltage must never be exceeded GOP_XC3S200 USER S MANUAL V1 2 Page 13 of 29 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 3 5 PAL GAL Emulation Of 24 Pin And 20 Pin Devices As a general hint the modules DIL plug should be protected mechanically with an additional adaptor like the supplied DIL sockets e In 24
24. lay of 0 25ns maximum Further on the shifters do not clamp the outputs to their VCC of 3 3V They can be lifted up by pullups to a maximum of 7V So as an option the GOP XC3S200 module supports pullups to 5V or rather the voltage at pin 24 They can be enabled on pin 1 to pin 13 and pin 14 to pin 23 separately by setting jumpers on CON 11 12 and 13 14 respectively With these jumpers enabled the I Os are nearly compatible to the IEE1284 standard So direct connection to a PC s parallel printer port is possible GOP XC3S200 USER S MANUAL V1 2 Page 15 of 29 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 6 Detailed XC3S200 4VQ100C FPGA Pinout Table Pin FPGA pin Schema UCF function net name port Comment routed to name 1 VO LO1P 7 31 sa lt 12 gt Sram address input AO SRAM pin20 Led4 2 O LOIN 7 32 sd lt 0 gt Sram data I O bitO SRAM pin21 3 GND GND Connection to the GND Layer of the PCB 4 IVO L21P 7 104 sd 1 Sram data I O bit1 SRAM pin22 5 0 L21N 7 105 sd lt 2 gt Sram data I O bit2 SRAM pin23 6 VCCO 7 VCC3V3 LVCMOS33 LVTTL I O Voltage 3 3V 7 VCCAUX VCC2V5 VCCAUX must be 2 5V 8 0 L23P 7 108 sd lt 3 gt Sram data I O bit3 SRAM pin25 9 1 0 L23N 7 109 sd lt 4 gt Sram data I O bit4 SRAM pin26 10 GND GND Connection to the GND Layer of the
25. o GND by R19 R19 0 I O pullups on power up 1 no I O pullups 99 PROG B PROG FPGA configuration reset signal active low can be driven XCFO1 pin7 by I O pin28 or SW2 if jumper on CON2 7 8 is set CON ping or always by XCF01 100 TDI FTDI FPGA JTAG chain CONS pin10 JTAG TDI via serial resistor to support 3 3V download adapter There is an UCF file definition for 24pin and another one for 20pin device usage GOP XC3S200 USER S MANUAL V1 2 Page 19 of 29 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 7 CON4 Test Connector Pinout Table Pin FPGApin Schema UCF function 61 name port Comment ii routedto name 1 GND GND Power ground plane connection 2 0 L28P 5 tp2 tp2 Testconnector CON4 pin 2 to FPGA pin30 FPGA pin30 not 5V tolerant 3 0 L28N 5 tp3 tp3 Testconnector CON4 pin 3 to FPGA pin32 FPGA pin32 not 5V tolerant 4 V O 31 5 tp4 tp4 Testconnector CON4 pin 4 to FPGA pin34 FPGA pin34 not 5V tolerant 5 WO L31N 5 tp5 tp5 Testconnector CON4 pin 5 to FPGA pin35 FPGA pin36 not 5V tolerant 6 GCLK2 tp6 tp6 Testconnector CON4 pin 7 to FPGA pin36 FPGA pin36 not 5V tolerant This is also an input to the global clock net GCLK2 7 GCLK3 GIO37 tp7 Testconnector CON4 pin 7 via level shifter to FPGA pin37 FPGA pin37 This is also an input to the global clock net GCLK3 8 0 L2
26. pblyunu m uuu 13 3 5 PAL GAL Emulation Of 24 Pin And 20 Pin Devices 14 4 FPGA Design SON ace aca cc tales at u u ng aa NE ANA AA 14 5 About GOP XC3S200 I O Voltage Levels eee eee een ekk 15 6 Detailed XC3S200 4VQ100C FPGA Pinout Table nn 16 7 GON4 Test Connector Pinout Table a 20 8 CON2 Configuration Jumper Options a ba maa 20 9 CONI1 DIL Connector Pinout Table Wo oom Wa 21 10 CON1 DIL Connector Layout 22 11 Schieimiall6S uuu u tatanan aminn ER ex BAE nel AANE ERA EA EA anaa 23 12 vues VENE vro Woo C 25 13 Module Layout Bottom View cm 26 14 Technical SpecIGallOflBusc uuu aa aa an 27 15 Bici ct 28 16 Assembly varianis sasae D rH 29 17 USER S MANUAL Revislons sa mbl kkal able aman 29 GOP XC3S200 USER S MANUAL V1 2 Page 3 of 29 OHO Elektronik Rudolf Diesel Str 8 gt D 85221 Dachau Germany www oho elektronik de GOP XC3S200 USER S MANUAL V1 2 Page 4 of 29 OHO Elektronik Rudolf Diesel Str 8 D 85221 Dachau Germany www oho elektronik de 2 Introduction The GOP XC3S200 is
27. r 8 gt D 85221 Dachau Germany www oho elektronik de 2 3 Xilinx XC3S200 Features Document 1 lists lots of goodies here are the best facts Modern SRAM based 90nm 200000 Gate low cost FPGA 3840 4 input function generators 1920 can be RAM or dual ported RAM or shift registers SelectRAM hierarchical memory 12 x 18kbit Blockram 30kbit distributed RAM 12 dedicated multipliers 18x18 4 Digital Clock Managers DCMs Lots of I O standards but GOP_XC3S200 supports LVCMOS33 and LVTTL only Wide multiplexers fast look ahead carry logic 8 global clock nets JTAG interface with user access Free powerful VHDL VERILOG schematics simulation design software available Webpack Unlimited reprogrammability V V Vv V V Vv V v v 2 4 Xilinx XC3S200 Disadvantages The following items are not relevant in most cases However they should be used as a checklist to query wheather an application is affected No single chip solution needs a configuration source like a platform FLASH 3 different supply voltages required core voltage 1 2V VCCAUX 2 5V I O voltage I Os are not 5V tolerant High quiescent current in the range of tens of milliamps for each of the supply voltages for XC3S200 Design is not protected against copyright theft configuration bitstream can be recorded Lower performance FPGA compared to the luxury Virtex2 pro or Virtex4 FPGA s especially not all LUTs have RAM shift register capabilities DLLs in the DCM
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