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XWAY™ PHY11G (PEF 7071) Version 1.5 User's Manual Hardware

1. z RMII o RGMII a RTBI amp a EQ d aS SerDes Control gt lt Ss Z2odszBob ane 5 289 o ae op 57095295 ggg FER E e m ea I x x x a O Figure 7 Functional High Level Block Diagram of XWAY PHY11G 3 1 Modes of Operation The XWAY PHY11G supports various MII types such as RMII RGMII SGMII and RTBI These can be combined with two MDI modes of operation namely those based on copper or fiber 1000BASE X This section outlines the supported combinations of these interfaces as illustrated in Table 9 Table 9 Mil and MDI Combinations Supported by XWAY PHY11G xMII Mode MDI Mode Chapter 3 2 1 Chapter 3 3 1 Copper Fiber Chapter 3 3 1 1 Chapter 3 3 1 1 10BASE T e 100BASE TX 1000BASE T 1000BASE X RMII X X Fiber is only RGMII X X X available in media nverter SGMI x x x applications RTBI X In general a particular combination of MIls and MDIs defines one of 2 different data flows Copper flow Media converter flow The flows can be configured via pin strapping see Chapter 3 4 1 or after an EEPROM boot see Chapter 3 4 2 and are controlled by means of the MDIO interface pins see Chapter 3 4 3 User s Manual Hardware Description 30 Revision 1 0 2012 02 17 gU L XW
2. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESD PDF LEAP wpc pr FON RO ROLH RO RO ROLH RO Field Bits Type Description RESD 15 5 RO Reserved Write as zero ignore on read PDF 4 ROLH Parallel Detection Fault Note that this bit latches high It is set to zero upon read of AN EXP See also IEEE 802 3 2008 28 2 4 1 5 1 Constants 0s NONE A fault has not been detected via the parallel detection function 1g FAULT A fault has been detected via the parallel detection function LPNPC 3 RO Link Partner Next Page Capable See also IEEE 802 3 2008 28 2 4 1 5 1 Constants Og UNABLE Link partner is unable to exchange next pages 1g CAPABLE Link partner is capable of exchanging next pages NPC 2 RO Next Page Capable See also IEEE 802 3 2008 28 2 4 1 5 1 Constants Og UNABLE Local Device is unable to exchange next pages lg CAPABLE Local device is capable of exchanging next pages PR 1 ROLH Page Received Note that this bit latches high It is set to zero upon read of AN EXP See also IEEE 802 3 2008 28 2 4 1 5 1 Constants 0s NONE A new page has not been received 1g RECEIVED A new page has been received LPANC 0 RO Link Partner Auto Negotiation Capable See also IEEE 802 3 2008 28 2 4 1 5 1 Constants Og UNABLE Link partner is unable to auto negotiate lg CAPABLE Link partner is auto negotiation capable User s Manual Hardware Description 97 Revision 1 0 2012
3. User s Manual 139 Revision 1 0 2012 02 17 Hardware Description gU L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s 5 3 EEPROM EEPROM Address Space MMD 0x1E This register file contains the EEPROM address space MMD 0x1E EEPROM Content Memory The EEPROM is indirectly addressable via MMD Ox1E EEPROM Offset EEPROM Content 1E 0000 1EFFFF 15 14 13 12 11 10 9 8 7 MMD Registers Reset Value 4 3 2 1 0 EEPRON 7 0 Memory Field Bits Type Description EEPROM 8 0 Memory EEPROM Content The EEPROM is indirectly addressable via MMD Ox1E User s Manual 140 Hardware Description Revision 1 0 2012 02 17 ae Leona XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MMD Registers 5 4 INTERNAL Internal Address Space MMD 0x1F This register file contains the PHY internal address space MMD 0x1F LED Configuration This register must be used to configure the complex functions of the LED behavior Complex functions are of a higher priority than direct LED functions as of registers MMD INTERNAL LEDxH L When the PHY enters a state which is defined to activate complex LED functions all LEDs are controlled according to the type of the complex function Offset 1F 01E0 LEDCH LED Configuration 15 14 13 12 11 10 9 8 7 Reset Value 00C5 FBF SBF NACS
4. 002 00 0c eee eee 71 Figure 33 EEE Low Power Idle Sequence 1 0 00 cette 72 Figure 34 LPI Mode Operation in XWAY PHY11G 00 0002 cece e 73 Figure 35 Block Diagram of a WoL Application liiis 74 Figure 36 The Magic Packet Format liiis hn 75 Figure 37 State Diagram for Power Down Mode Management lssslele een 77 Figure 38 Test Packet Format ocooooroccrrcnr esu hash eee han hne de 80 Figure 39 MAC Interface Near End Test Loop 0 annann nenene 81 Figure 40 MDI connector Near End Test Loop 0 0 00 rnaner 82 Figure 41 Echo Near End Test Loop 0 0 cece hr re 82 Figure 42 PCS Far End Test Loop nunana nananana nerne 83 Figure 43 Timing Diagram for the XWAY PHY11G Reset Sequence 0 00 eee 160 Figure 44 Timing Diagram for the MDIO Interface 0 2 llle ee 162 Figure 45 Transmit Timing Diagram of the RMIl 0 0 00 RR Ih 163 Figure 46 Transmit Timing Diagram of the RGMII 0 0c 164 Figure 47 Receive Timing Diagram of the RGMIl liiis RII 165 Figure 48 Transmit Timing Diagram of the RTBI o o occccccccocccc e n 167 Figure 49 Receive Timing Diagram of the RTBl llis n 168 User s Manual 8 Revision 1 0 2012 02 17 Hardware Description XWAY PHY11G PEF 7071 ul Lantiq Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s List of Figures Figure 50 Transmit Timing Diagram of the SGMIl
5. TPICP TPICN TPIDP TPIDN UU UU 00 Di Rear GND Remm Figure 57 Twisted Pair Common Mode Rejection and Termination Circuitry Table 66 Electrical Characteristics for supported Transformers Magnetics Parameter Symbol Values Unit Note Test Condition Min Typ Max Common mode de coupling Comm 800 1000 1200 pF 20 2 kV capacitance media end Common mode termination Remm 80 75 70 Q 10 resistance media end Calibration resistor Rea 15840 16000 16160 0 1 User s Manual 178 Revision 1 0 2012 02 17 Hardware Description ral XWAY PHY11G PEF 7071 E LANTIC Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Electrical Characteristics 6 8 6 SGMII Interface Figure 58 shows the external analog circuitry that may be used to properly set up an SGMII MAC to PHY connection All optional circuitry is considered Since the XWAY PHY11G fully implements CDR Clock and Data Recovery functionality it is not required to connect the MAC source clock However it may be required to wire the PHY source clock in case the MAC does not implement CDR If the MAC supports CDR the elements shaded in dark gray in the figure may be omitted The XWAY PHY11G does not directly generate the defined common mode offset voltage of 1 2 V since this is n
6. RXLPI RCVD 10 ROLH RXLPI Has Been Received Constants Oz INACTIVE LPI has not been received 1g ACTIVE LPI has been received TXLPI IND 9 RO TXLPI Indication Constants Og INACTIVE LPI is currently inactive 1 ACTIVE LPI is currently active RXLPI IND 8 RO RXLPI Has Been Received Constants Og INACTIVE LPI is currently inactive 1g ACTIVE LPI is currently active TXCKST 6 RO Transmit Clock Stoppable The PHY must set this bit to allow the MAC to stop the clocking during the LPI MODE The MAC may stop its clock during LPI if this bit is set to active Constants Og DISABLE The PHY is not able to accept stopped transmit clocks 1g ENABLE The PHY is able to accept a stopped transmit clock during LPI MODE User s Manual Hardware Description 135 Revision 1 0 2012 02 17 Lanr C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s EEE Capability Register This register is used to indicate the capability of the PCS to support EEE functions for each PHY type EEE CAP EEE Capability Register 15 14 13 12 11 10 Offset 03 0014 9 8 7 6 5 4 3 MMD Registers 2 Reset Value 1 EEE_ 10GB KR EEE_ 10GB KX4 EEE_ 1000 BKX EEE_ 10GB T EEE_ 1000 BT EEE_ 100B TX RO RO RO RO RO RO Field Bits Type Description EEE_10GBKR RO Support
7. RESH1 MODERESH IPGL TYPE RESL SIZE Resto STAR en i i i i i RO RW RO RW RW RO RW RO RW RW Field Bits Type Description RESH1 15 14 RO Reserved Write as zero ignore on read MODE 13 RW Mode of the TPG Configures the packet generation mode Constants Oz BURST Send bursts of 10 000 packets continuously 1g SINGLE Send a single packet RESHO 12 RO Reserved Write as zero ignore on read IPGL 11 10 RW Inter Packet Gap Length Configures the length of the inter packet gap in bit times Constants 00 BT48 Length is 48 bit times 01 BT96 Length is 96 bit times 10 BT960 Length is 960 bit times 11 BT9600 Length is 9600 bit times TYPE 9 8 RW Packet Data Type Configures the packet data type to be either predefined byte increment or random If pre defined the content of the register TPGDATA is used repetitively Constants 00 RANDOM Use random data as the packet content 01 BYTEINC Use byte increment as the packet content 10 PREDEF Use pre defined content of the register TRGDATA RESL1 7 RO Reserved Write as zero ignore on read User s Manual 128 Revision 1 0 2012 02 17 Hardware Description XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers Field Bits Type Description SIZE 6 4 RW Packet Size Configures the size of the generated Ethernet packets in bytes The size includes DA SA length type payload and FCS Constants 000 B64 Pack
8. 0 0 0 ee 169 Figure 51 Receive Timing Diagram of the SGMIl 2 0 0 eR Ih 170 Figure 52 Transmit Timing Diagram of the 1000BASE X Interface llle ese 171 Figure 53 Receive Timing Diagram of the 1000BASE X ssssseeeee rn 172 Figure 54 Equivalent Circuit for Crystal Specification lille 173 Figure 55 Tolerance Graph for the Forward Current Versus Voltage of the Supported LEDs 174 Figure 56 Schematic of a Typical Gigabit Ethernet Transformer Device llle eee eee 175 Figure 57 Twisted Pair Common Mode Rejection and Termination Circuitry llle sess 178 Figure 58 External Circuitry for SGMII liliis RR s 179 Figure 59 Simplified External Circuitry for SGMII aana auaa II 180 Figure 60 External Circuitry for a 1000BASE X Interface 0 0 00 00 eee o 181 Figure 61 Package Dimension Drawing of the VQFN48 Package 0 0 esee 182 Figure 62 Soldering Footprint for the VQFN48 Package 0 0 0 cee eh 183 Figure 63 Tape Reel Packing Dimension Drawing of VQFN48 sssssssee een 183 User s Manual 9 Revision 1 0 2012 02 17 Hardware Description soe XWAY PHY11G PEF 7071 EN Lantiq Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s List of Tables List of Tables Table 1 Abbreviations for Pin Types 0 0 0 eee eee eae 18 Table 2 Abbreviations for Buffer Types 0 0 0 te ne eee ae 18 Table 3 General PINS oeste REGE PR e
9. gU L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers Field Bits Type Description LED3DA 3 RW Direct Access to LED3 Write a logic 1 to this bit to illuminate the LED Note that LED3EN must be set to logic zero Constants Og OFF Switch off the LED lg ON Switch on the LED LED2DA 2 RW Direct Access to LED2 Write a logic 1 to this bit to illuminate the LED Note that LED2EN must be set to logic zero Constants Og OFF Switch off the LED lg ON Switch on the LED LED1DA 1 RW Direct Access to LED1 Write a logic 1 to this bit to illuminate the LED Note that LED1EN must be set to logic zero Constants Og OFF Switch off the LED 1g ON Switch on the LED LEDODA 0 RW Direct Access to LEDO Write a logic 1 to this bit to illuminate the LED Note that LEDOEN must be set to logic zero Constants Og OFF Switch off the LED lg ON Switch on the LED User s Manual 127 Revision 1 0 2012 02 17 Hardware Description gU L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers Test Packet Generator Control This register controls the operation of the integrated Test Packet Generator TPG Note that this module is only used for testing purposes TPGCTRL Offset Reset Value Test Packet Generator Control 1C 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
10. Configures the functional mode of the XWAY PHY11G The meaning of these bits depends on the FLOW setting FLOW Copper 00 RGMII the MAC connects to the XWAY PHY11G via RGMII 01 SGMII the MAC connects to the XWAY PHY11G via SGMII 10 RMII the MAC connects to the XWAY PHY11G via RMII 11 RTBI the MAC connects to the XWAY PHY11G via RTBI FLOW Converter 00 X2T1000 convert 1000BASE X to 1000BASE T 01 X2T1000A convert 1000BASE X with ANEG to 1000BASE T 10g reserved 11 reserved CONF 1 0 Used to specify the transmit and receive timing skew in the RGMII mode using the integrated delay generation on TX CLK RX CLK The meaning of these bits depends on the FLOW setting FLOW Copper X0g RGMII TXSKEW 1N5 Transmit timing skew is 1 5 ns X1g RGMII_TXSKEW_ONO Transmit timing skew is 0 0 ns OX RGMII RXSKEW 1N5 Receive timing skew is 1 5 ns 1X RGMII RXSKEW ONO Receive timing skew is 0 0 ns ANEG 1 0 Configures the auto negotiation behavior of the XWAY PHY11G The meaning of these bits depends on the FLOW setting FLOW Copper 00 DEFAULT advertise 10 100 1000 Mbit s in both full and half duplex 01 FASTHDX advertise 10 100 Mbit s in half duplex and 1000 Mbit s in in both full and half duplex 10 GIGAONLY advertise only 1000 Mbit s in both full and half duplex 11 FASTONLY advertise only 10 100 Mbit s in both full and half duplex FLOW Converter 00 reserv
11. D12 D11 1 DIO D9 108 1 D7 D6 DS D4 D3 D2 1 D1 DO Zz Z 1 1 1 1 1 i i 1 1 1 i 1 1 i i 1 i 1 1 1 1 i 1 1 1 l i li IDLE 1 PRE 1 zn 1 OP 1 PHYAD 1 REGAD 1 TA 1 DATA 1 IDLE 1 oe i a pi pi pia pig PHY drives the bi directional MDIO 1 1 1 1 1 1 1 IDLE PRE ST Too PHYAD ij REGAD 1 STA 1 DATA 14 IDLE i oe Se a pi pi e a re Figure 23 MDIO Read Frame Note that the read operation requires the PHY to return the read data to the higher level management entity This implies that the driver of the MDIO signal is changed from being the higher level management entity to being the PHY In order to take this driving condition transition into account a turn around time is defined The only period of time over which the PHY drives the MDIO signal is when returning the 16 bit read data value to the higher level management entity Both frames consist of several fields which are explained in more detail in Table 24 User s Manual 57 Revision 1 0 2012 02 17 Hardware Description gU L XWAY PHY11G PEF 7071 fe ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description Table 24 Definition of MDIO Frame Components Field Field Long Name Definition IDLE Idle Time This state is entered by both the higher level management entity and PHY when no transaction happens In this state all tristate drivers are inactive The in
12. Hardware Description UC Lantiq XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Electrical Characteristics Table 67 Electrical Characteristics for the SGMII External Components cont d Parameter Symbol Values Unit Note Test Condition Min Typ Max BIAS resistance 2 R 10 1 7k 10 Q VDDP 3 3V 10 1 1k 10 O VDDP 2 5V Termination resistance R3 10 100 10 Q Coupling capacitance C 10 100 10 nF FOSD SIGDET C TDP Transmission TX_DAT Line TDN 500 TX_DAT C C RDP Transmission RX_DAT Line RDN 500 RX_DAT C PHY 44 FO Module Figure 59 Simplified External Circuitry for SGMII User s Manual Hardware Description 180 Revision 1 0 2012 02 17 ae Leona XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Electrical Characteristics 6 8 7 1000BASE X Interface Figure 60 depicts the external analog circuitry that may be used to properly set up a 1000BASE X PHY to FO connection There are FO modules available that already integrate all coupling circuitry components in which case a straight connection is sufficient and the external coupling caps may be omitted Component values for this type of circuit are defined in Table 68 Many FO modules have open drain outputs which can cause conflict with the weak pull down nature of the SIGDET
13. PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description and Legacy LPI Configuration Register 1 The default value of this register ensures compliance with the IEEE 802 3az value In the LPI mode the MDI alternates between quiet and refresh signals LPI is terminated when any new valid frame from the xMII interface arrives or a wake up signal is received from the link partner The maximum number of IPG bytes that may be transmitted via MDI in the phase where the buffer is being emptied of the bytes that triggered LPI termination is determined by the IPG value in the MMD INTERNAL LEG LPI CFG2 register refer to Legacy LPI Configuration Register 2 If the incoming data includes more IPG bytes these will not be stored in this buffer and are subsequently not transmitted over the MDI 3 5 4 Wake on LAN WoL Wake on LAN WoL is an essential feature of the XWAY PHY11G By means of an integrated packet trace engine that is capable of monitoring and detecting WoL packets the PHY is able to wake a larger SoC from its power down state This is done by indicating such an event via the external interrupt sourced by the XWAY PHY11G This scenario is shown in Figure 35 Consequently the SoC can switch off everything except the interrupt controller in order to save the maximum amount of power The XWAY PHY11G can trace WoL packets in any of its supported speed modes 10 100 1000 Mbit
14. PHY11G This interface conforms to the SGMII specification v1 7 as defined in 13 The SGMII interface can operate at 1 25 Gbaud The net data rate is 1000 Mbit s Using repetition modes 10 Mbit s and 100 Mbit s are supported Also note that Chapter 6 8 6 specifies the external circuitry 6 6 9 1 Transmit Timing Characteristics Figure 50 shows the timing diagram of the transmit SGMII interface at the XWAY PHY11G It is referred to by Table 58 which specifies the timing requirements 1 frx cik ton tr ts kewT max SCP unipolar SCN unipolar son EK MK O X X diferential tskewTmin skew C T Figure 50 Transmit Timing Diagram of the SGMII Table58 Transmit Timing Characteristics of the SGMII Parameter Symbol Values Unit Note Test Condition Min Typ Max Transmit clock frequency fx cix 50 ppm 625 0 50 ppm MHz Transmit clock duty cycle Dep tete 48 50 52 Transmit rise time tr 100 200 ps 20 gt 80 Transmit fall time tr 100 200 ps 80962096 Clock to data skew at TX tekewT 250 550 ps Output timing jitter Jrx 240 ps Peak peak Time skew between pairs tekew 20 ps Output differential voltage Vop 150 400 mV Peak amplitude Output voltage ringing V aa 10 Output impedance single ended Ro 40 60 10 Output impedance differential Ro 80 120
15. XWAY PHY Ethernet Physical Layer Devices XWAY PHY11G Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s PEF 7071 Version 1 5 User s Manual Hardware Description Revision 1 0 2012 02 17 Edition 2012 02 17 Published by Lantiq Deutschland GmbH Am Campeon 3 85579 Neubiberg Germany 2012 Lantiq Deutschland GmbH All Rights Reserved Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics With respect to any examples or hints given herein any typical values stated herein and or any information regarding the application of the device Lantiq hereby disclaims any and all warranties and liabilities of any kind including without limitation warranties of non infringement of intellectual property rights of any third party Information For further information on technology delivery terms and conditions and prices please contact the nearest Lantiq Office www lantiq com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact the nearest Lantiq Office Lantiq components may be used in life support devices or systems only with the express written approval of Lantiq if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or sys
16. 0 9 MAX 11 x 0 5 5 5 0 65 5 5 11x 0 5 48x 10 1 5 A B C Index Marking Ed s i s 3 o A x lt Ja a Y Y SEATING PLANE 0 05 MAX i 3 ie Figure 61 Package Dimension Drawing of the VQFN48 Package Note The corners of the VQFN Package expose contacts that are residuals of the EPAD construction Such pins must not be connected and false contacts to signal lines on the PCB layer must be prevented Package description package handling PCB and board assembly information is available on request Figure 62 shows a recommended soldering footprint for the VQFN48 User s Manual 182 Revision 1 0 2012 02 17 Hardware Description XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Package Outline ie Lantiq e Package outline 7 x 7 lo p 1 Solder resist covering vias and segmenting thermal pad optional Figure 62 Soldering Footprint for the VQFN48 Package The XWAY PHY11G is packed and shipped according to the specifications outlined in Figure 63 93 Figure 63 Tape Reel Packing Dimension Drawing of VQFN48 183 Revision 1 0 2012 02 17 User s Manual Hardware Description nm L XWAY PH
17. 100 MHz User s Manual 176 Revision 1 0 2012 02 17 Hardware Description 6 8 4 RJ45 Plug 6 Lanti XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Electrical Characteristics Table 65 describes the electrical characteristics of the RJ45 plug to be used in conjunction with the XWAY PHY11G Table 65 Electrical Characteristics for Supported RJ45 Plugs Parameter Symbol Values Unit Note Test Condition Min Typ Max Crosstalk attenuation CTA 45 dB 30 MHz 40 dB 60 MHz 35 dB 100 MHz Insertion loss IL 1idB 1 MHz lt f lt 100 MHz Return loss RL 25 0 dB 1 MHz lt f lt 100 MHz User s Manual 177 Revision 1 0 2012 02 17 Hardware Description ral XWAY PHY11G PEF 7071 E CANTI Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Electrical Characteristics 6 8 5 Twisted Pair Common Mode Rejection and Termination Circuitry This section describes the external circuitry which is required to properly terminate the common mode of the Twisted Pair Interface TPI Also these external components are required to perform proper rejection of alien disturbers which are injected into the common mode of the TPI Figure 57 shows a typical external circuit and in particular the common mode components Table 63 defines the component values and their supported tolerances Transformer TPIAP TPIAN TPIBP TPIBN
18. 3 4 Configuration Control and Status Functions 00 000 e eee ees 42 3 4 1 Configuration of XWAY PHY11G via Pin Strapping 00 ee BB 43 3 4 2 Configuration of XWAY PHY11G via External EEPROM 0 0 cee eee eese 48 3 4 2 1 EEPROM Applications o oooooooooo 48 User s Manual 4 Revision 1 0 2012 02 17 Hardware Description gU L XWAY PHY11G PEF 7071 ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Table of Contents 3 4 2 2 EEPROM Detection 2 duis e lg rl Rr Rma ae ela EEE RA ERE EE 48 3 4 2 3 EEPROM COMON aii asas edens nn mk a ead eee RE e BAG RO UR DH RIRs a e Rd 49 3 4 2 4 EEPROM Frame Formats ccocooccoc nr 50 3 4 2 4 1 Frame Formats in 11 Bit Addressing Mode ocococccccccco ee 50 3 4 2 4 2 Frame Formats in 16 Bit Addressing Mode 0000s 52 3 4 2 4 3 EEPROM Access via MDIO 0 000 cee ee 54 3 4 3 Configuration and Control Via MDIO 0 0 eens 57 3 4 3 1 MDIO Interface iieri Seng eee es ead A eal eee 57 3 4 3 2 MDIO Address Space o 58 3 4 3 3 MDIO Interrupt i daai ee char edd ada aba RR ec had Ab be DER e baled d dete dde 60 3 4 4 LED Intetface zx cxx oe che Ex a RR EX e xU EGRE Sa AUN Me eR aoe Ne oe are e deb a n 62 3 4 4 1 Single Color LED Mode ooccccc hr 62 3 4 4 2 Bi Color LED Mode sssseeeee hh rrr 62 3 4 4 3 LED Operations dan taudi ea Tae tS ERE Rad ep aa e ps 63 3 4 4 3 1 LED Externally Controll
19. TPICN B B A D D A C C 4 Normal straight CAT5 cable TPIAP TPIAN TPIBP TPIDP TPIDN TPIBN TPICP TPICN with C D pair swap At A Bt D D B C C 1 Pin assignment according to TIA EIA 568 A B Polarity reversal errors caused by improper wiring are automatically corrected by the XWAY PHY11G This correction is done on all pairs in the receive direction for all supported twisted pair media modes In 10BASE T mode the polarity correction is based on the detection of valid link pulses In 100BASE TX the polarity of the receive signal is inherently corrected by the negation invariance of line code In the 1000BASE T mode polarity detection is part of the training sequence In all the modes the detected polarity is frozen once the link has been established and remains unchanged until the link is dropped 1 A subset of this feature is also known as MDI MDI X from 10BASE T and 100BASE TX User s Manual 39 Revision 1 0 2012 02 17 Hardware Description ss L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description 3 3 5 Transformerless Ethernet TLE Transformer Less Ethernet TLE is required for back plane or PICMG applications where the use of a transformer magnetics is not necessarily required in order to fulfill the galvanic decoupling requirements of the isolation specificati
20. This section defines the DC characteristics of the LED interface summarized in Table 45 Note that these characteristics only apply in LED driving mode During device startup when the LED pins are serving the soft pin strapping function these characteristics do not necessarily apply Table 45 DC Characteristics of the Transmit LED Interface Parameter Symbol Values Unit Note Test Condition Min Typ Max Output high voltage Vou 1 9 V Vopy 2 5 V lop 15 mA Output high voltage Vou 2 7 V Vooh 3 3 V lop 15 mA Output low voltage VoL 0 4 V lo 15 mA User s Manual 158 Revision 1 0 2012 02 17 Hardware Description fer L XWAY PHY11G PEF 7071 ee YT IC Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Electrical Characteristics 6 5 1 5 JTAG Interface The JTAG Interface comprises the set of pins TCK TDI TDO and TMS It operates in the VDDH power domain The DC characteristics for Vppp 2 5 V and Vppp 3 3 V are summarized in Table 46 and Table 47 respectively Table46 DC Characteristics of the JTAG Interface VDDH 2 5 V Parameter Symbol Values Unit Note Min Typ Max Test Condition Input high voltage Vin 1 8 Vppu 0 5 V Input low voltage Vi 0 7 V Output high voltage Von 2 1 V lop 4 mA Output low voltage VoL 0 4 V lo 4 mA Table 47 DC Characteristics of the JTAG Interface
21. VDDH 3 3 V Parameter Symbol Values Unit Note Min Typ Max Test Condition Input high voltage Vin 2 3 Vppu 0 5 V Input low voltage Vi 0 7 V B Output high voltage Vou 2 7 V lon 4 mA Output low voltage VoL x 0 4 V log 4 mA 6 5 2 Twisted Pair Interface The TPI conforms to the 10BASE T 100BASE TX and 1000BASE T specifications described in IEEE802 3 1 as well as ANSI X3 263 1995 4 6 5 3 SGMII Interface Since the SGMII interface implementation on the XWAY PHY11G is purely AC coupled there are no DC characteristics to be specified Instead Chapter 6 8 6 specifies the AC coupling external circuitry with an option to generate the common mode offset voltage required for DC coupled operation compliant with 13 with the SGMII link partner The AC characteristics which apply in SGMII mode are specified in Chapter 6 6 9 6 5 4 1000BASE X Interface Since the 1000BASE X interface implementation on the XWAY PHY11G is purely AC coupled there are no DC characteristics to be specified Instead Chapter 6 8 7 specifies the AC coupling external circuitry The AC characteristics which apply in 1000BASE X mode are specified in Chapter 6 6 10 User s Manual 159 Revision 1 0 2012 02 17 Hardware Description E L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Electrical Characteristics 6 6 AC Characteristics The following sections describe the AC
22. sio eds pk rax o RR EG aX pea URN ad ER E Edu RU ads 163 6 6 7 RGM Interface 2 xs t ve m cee dg vx vec ER rau helene EE RR E 164 6 6 7 1 Transmit Timing Characteristics lise eh 164 6 6 7 2 Receive Timing Characteristics 0 0 eee eee 165 6 6 8 IBI Interface vo ace Pee oe bad ede Y hd bead Ae ed AR ow ee e de or ie ares 167 6 6 8 1 Transmit Timing Characteristics llis 167 6 6 8 2 Receive Timing Characteristics 0 0 n 168 6 6 9 SGMII Interface cion kl bale chad ope eter Reis bl TR gud 169 6 6 9 1 Transmit Timing Characteristics liie eh 169 6 6 9 2 Receive Timing Characteristics lille 170 6 6 10 1000BASE X nerna En nnna a E et ete hh hn 171 6 6 10 1 Transmit Timing Characteristics 0 00 e 171 6 6 10 2 Receive Timing Characteristics 0 0 ee n 172 6 6 11 Twisted Pair Interface ce ee eee a ee 172 6 7 Isolation Requirements 00 000 e a a a a eee tees 172 6 8 External Circuitly coss ERR a de Saag Wada e wee deed aging Gea dogs 173 6 8 1 Crystal oered noe EPI phase Male ghee seh eee GE hot ede AE 173 6 8 2 BET 174 6 8 3 Transformer Magnetics oooocooccocoo cruci rinrk eai aia a eaa a 175 6 8 4 A 177 6 8 5 Twisted Pair Common Mode Rejection and Termination Circuitry o oooo oooooooo 178 6 8 6 etiim 179 6 8 7 1000BASE X Interface ooooooooc hr 181 7 Package Outline uses ppp ieee per dra qued 182 User s Manual 6 Revision 1 0
23. steps of 0 5 ns via MDIO If the integrated delay is not used for example because it is implemented externally by PCB wire delays it must be set to zero in which case all the timings are related directly to the RX CLK on the pin tcp tskew 3 tip ton ta e o tr o tr ne internal RX CLK Vin min il max 80 external delayed RX_CLK 20 RXD 4 0 gt ares foot a oros PAHO NX Figure 49 Receive Timing Diagram of the RTBI Table 57 Receive Timing Characteristics of the RTBI Parameter Symbol Values Unit Note Test Condition Min Typ Max Receive clock frequency RX CLK fg cik 50 ppm 125 0 50 ppm MHz Receive clock period RX CLK tcp 7 5 8 0 8 5 ns Receive clock high time RX CLK Ith 3 6 4 0 4 4 ns Receive clock low time RX CLK ti 3 6 4 0 4 4 ns Receive clock rise time RX CLK tr 750 0 ps 209608096 Receive clock fall time RX_CLK tr 750 0 ps 80962096 Clock to data skew at RX tekew 0 5 0 0 0 5 ns Integrated receive clock delay to 0 0 k 0 5 3 5 ns Adjustable via MDIO register User s Manual 168 Revision 1 0 2012 02 17 Hardware Description XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Lantiq Electrical Characteristics 6 6 9 SGMII Interface This section describes the AC characteristics of the SGMII Interface on the XWAY
24. 0 Delta output impedance dRo 10 96 1 Assuming BER 1e 12 and tracking BW 1 MHz User s Manual 169 Revision 1 0 2012 02 17 Hardware Description gU L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Electrical Characteristics 6 6 9 2 Receive Timing Characteristics Figure 51 shows the timing diagram of the receive SGMII interface on the XWAY PHY11G It is referred to by Table 59 which specifies the timing requirements Note that the integrated SGMII operates using a CDR Clock and Data Recovery and therefore does not require the 625 MHz differential receive clock Consequently there are no timing requirement related to this clock 1 frx H SIP unipolar SIN unipolar Figure 51 Receive Timing Diagram of the SGMII Table 59 Receive Timing Characteristics of the SGMII Parameter Symbol Values Unit Note Min Typ Max Test Condition Receive data rate fax 50 ppm 1250 0 50 ppm Mbit s Receive data jitter tolerance Jgx 500 ps Receive signal rise time ta 300 ps 20 80 Receive signal fall time te 300 ps 80 20 Input differential voltage Vio 50 500 mV Peak amplitude Input impedance single ended R 40 60 Q Input impedance differential R 80 120 0 User s Manual 170 Revision 1 0 2012 02 17 Hardware Description ae Leona XWAY PHY11G PEF 7071 Single Port Gi
25. 1 0 2012 02 17 Hardware Description ew Lant C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MMD Registers Field Bits Type Description BLINKF 3 0 RW Fast Blinking Configuration The Blink F Field selects in which PHY states the LED blinks with the pre defined fast frequency Constants 0000 NONE No Blinking 0001 LINK10 Blink when link is 10 Mbit s 0010 LINK100 Blink when link is 100 Mbit s 0011 LINK10X Blink when link is 10 100 Mbit s 0100 LINK1000 Blink when link is 1000 Mbit s 0101 LINK10_0 Blink when link is 10 1000 Mbit s 0110 LINK100X Blink when link is 100 1000 Mbit s 0111 LINK10XX Blink when link is 10 100 1000 Mbit s 10005 PDOWN Blink when device is powered down 1001 EEE Blink when device is in EEE mode 1010 ANEG Blink when auto negotiation is running 1011 ABIST Blink when analog self test is running 1100 CDIAG Blink when cable diagnostics are running Similar Registers The following registers are identical to the Register LEDOH defined above Table35 Similar Registers Register Short Name Register Long Name Offset Address Reset Value LED1H Configuration for LED Pin 1 1F 01E4 0020 LED2H Configuration for LED Pin 2 1F 01E6 0040 LEDSH Configuration for LED Pin 3 1F 01E8 0040 User s Manual 145 Revision 1 0 2012 02 17 Hardware Description Configuration for LED Pin 0 ET LANTI C XWAY PHY11G PEF
26. 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MMD Registers This register configures the behavior of the LED depending on pre defined states or events the PHY has entered into or raised Since more than one event or state can be active at the same time more than one function might apply simultaneously The priority from highest to lowest is given by the order PULSE BLINKS BLINKF CON LEDOL Configuration for LED Pin 0 15 13 12 11 10 Offset Reset Value 1F 01E3 0003 9 8 7 6 5 4 3 2 1 0 BLINKS PULSE RW RW Field Bits Type Description BLINKS 7 4 RW Slow Blinking Configuration The Blink S field selects in which PHY states the LED blinks with the pre defined slow frequency Constants 0000 NONE No Blinking 0001 LINK10 Blink when link is 10 Mbit s 0010 LINK100 Blink when link is 100 Mbit s 0011 LINK10X Blink when link is 10 100 Mbit s 0100 LINK1000 Blink when link is 1000 Mbit s 0101 LINK10_0 Blink when link is 10 1000 Mbit s 0110 LINK100X Blink when link is 100 1000 Mbit s 01115LINK10XX Blink when link is 10 100 1000 Mbit s 10005 PDOWN Blink when device is powered down 1001 EEE Blink when device is in EEE mode 1010 ANEG Blink when auto negotiation is running 1011 ABIST Blink when analog self test is running 1100 CDIAG Blink when cable diagnostics are running PULSE 3 0 RW Pulsing Configuration The pulse field is a mask field
27. 9 8 7 6 5 4 3 2 1 0 FREQ SNR LEN RO RO RO Field Bits Type Description FREQ 15 8 RO Frequency Offset of Link Partner ppm This register fields reports the measured frequency offset of the receiver in ppm as a signed 2 s complement number Note that a value of 128 0x80 indicates an invalid number SNR 7 4 RO Receive SNR Margin dB This register field reports the measured SNR margin of the receiver in dB The value saturates at a 14 dB SNR margin for very short links and 0 dB for very long links A value of 15 indicates an invalid number LEN 3 0 RO Estimated Loop Length Valid During Link Up This register field reports the estimated loop length compared to a virtually ideal CAT5e straight cable A value of 15 indicates an invalid number Constants 0000 L0 0 10 m 0001 L1 10 20m 0010 L2 20 30m 0011 L3 30 40m 0100 L4 40 50m 0101 L5 50 60 m 0110 L6 60 70m 0111 L7 70 80 m 1000 L8 80 90 m 1001 L9 90 100 m 1010 L10 100 110m 10115L11 110 120m 1100 L12 120 130 m 11015L13 130 140 m 1110 L14 140 m 1111 INVALID Invalid number for example when link is down User s Manual 108 Revision 1 0 2012 02 17 Hardware Description gU L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers Physical Layer Status 1 This register reports PHY lock information for example link up polarity reversals and port
28. EEE RXERR_LINK_FAIL_L Offset Reset Value Low Byte of the EEE Link Fail Counter 1F 01EB 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 z VAL RO Field Bits Type Description VAL 7 0 RO VAL Low byte of the EEE RXERR LINK FAIL counter A read access to this byte also clears the high byte of this counter User s Manual 148 Revision 1 0 2012 02 17 Hardware Description MII2 Control MII2 Control Register MII2CTRL MII2 Control 15 14 13 2 Len C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s 12 11 Offset 1F 01EC 10 9 8 7 6 5 MMD Registers Reset Value 0000 3 2 1 0 RXSKEW TXSKEW RW RW Field Bits Type Description RXSKEW 6 4 RW Receive Timing Skew RGMII Defines the receive timing skew in the RGMII mode using the integrated delay generation on RX CLK Note that this register is subject to default reset values which depend on the soft pin strappings Constants 000 SKEW_ONO 0 0 ns timing skew 001 SKEW_0N5 0 5 ns timing skew 010 SKEW 1NO 1 0 ns timing skew 011 SKEW_1N5 1 5 ns timing skew 100 SKEW_2N0 2 0 ns timing skew 101 SKEW_2N5 2 5 ns timing skew 110 SKEW 3NO 3 0 ns timing skew 111 SKEW_3N5 3 5 ns timing skew TXSKEW 2 0 RW Transmit Timing Skew RGMII Defines the transmit timing skew in the RGMII mode using the integrated delay generation on TX_CLK
29. EEPROM interface 1 C Two Wire Clocking Support of 25 MHz and 125 MHz input clock Support of 25 MHz crystal using integrated oscillator 25 MHz or 125 MHz clock output Ethernet e Auto negotiation with next page support Wake on LAN support Auto downspeed Support of auto MDIX at all copper media speeds e Support of auto polarity correction at all copper media speeds Various test features Test loops Dummy frame generation and frame error counters Analog self test Cable diagnostics Cable open short detection Cable length estimation External circuitry optimization Integrated termination resistors at twisted pair interface Integrated termination resistors at RGMII 1 10BASE T operation is only standard conform at Vppp 3 3 V This limitation does not apply to 10BASE Te Ethernet User s Manual 14 Revision 1 0 2012 02 17 Hardware Description aF XWAY PHY11G PEF 7071 E LANTIC Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Introduction Support of low cost transformers magnetics e Support of low cost crystal 1 2 3 Typical Applications This section introduces typical applications of the XWAY PHY11G sorted according to the medium type used in the application 1 2 3 1 Copper Application In applications using the copper medium the XWAY PHY11G is used to connect a 10 100 1000BASE T capable MAC unit to a twisted pair medium such as a CAT5 cable
30. PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description 3 2 Media Independent Interfaces MII This section describes the supported Mils of the XWAY PHY11G Each individual MII mode is investigated in detail and its particular requirements and properties are outlined 3 2 1 X speed Media Independent Interface xMII This section investigates all functional aspects of the xMII interface block 3 2 1 4 xMII Signal Multiplexing The XWAY PHY11G deals with the large variety of standard MAC interfaces Mlls by converting the different signaling schemes into native internal MII signals according to IEEE 802 3 1 This conversion is done by the xMII block on the XWAY PHY11G as illustrated in Figure 7 Table 10 summarizes the assignment of xMII pins to standard MAC interface signals according to Chapter 2 2 4 Table10 xMII Signal Multiplexing Logic Port xMII SerDes Pin Name I O RMII RGMII RTBI SGMII 1000BASE X TX CLK REFCLK TXC TXC SCP TXD3 TXD3 TXD38 SCN SIGDET TXD2 TXD2 TXD27 SOP TDP TXD1 TXD1 TXD1 TXD16 SON TDN TXDO TXDO TXDO TXDO5 SIP RDP TX CTL TX EN TX EN CTL TXD49 SIN RDN RX CLK O CLK50 RXC RXC RX CTL O CRS DV RX DV CTL RXD49 RXD3 O RXD3 RXD38 RXD2 O RX ER RXD2 RXD27 RXD1 O RXD1 RXD1 RXD16 RXDO O RXDO RXDO RXDO5 1 By default a free running 50 MHz clock is sourced at RX_CLK in RMII m
31. PHY 10 100 1000 Mbit s Functional Description 3 4 4 LED Interface The XWAY PHY11G supports up to three LED outputs These outputs are active high and drive LEDs directly with Vppp 2 5 V 3 3 V see Chapter 6 2 It is possible to connect one single color LED per interface pin as well as bi color LEDs The latter is achieved by combining two LED interface pins Both modes of operation are introduced in Chapter 3 4 4 1 and Chapter 3 4 4 2 respectively The behavior and event sensitivity of each LED can be configured individually as described in Chapter 3 4 4 3 The individual MDIO registers referred to in Chapter 3 4 4 3 are described in more detail in Chapter 4 3 4 4 1 Single Color LED Mode The external circuitry for a single color LED is depicted in Figure 27 The LEDx pin represents one of the available LED interface pins at the device The GND signal represents the common ground EPAD The LED pins are designed to source a certain amount of current out of the pad supply Vppp when becoming active high Besides the LED two individual resistors are depicted in the figure R gp denotes an optional series resistor which could be used depending on the selected LED type and PAD supply voltage Vopp Rerex and Corax denote external passive components required for the soft pin strapping configuration of the device The component values are selected such that the brightness of the LED is not affected More details on this type of pin strappin
32. RW RW RW Field Bits Type Description FBF 7 6 RW Fast Blink Frequency This register must be used to configure the fast blinking frequency Note that this setting implicitly defines the pulse stretching width Constants 00 01g 10g 11g F02HZ 2 Hz blinking frequency F04HZ 4 Hz blinking frequency F08HZ 8 Hz blinking frequency F16HZ 16 Hz blinking frequency SBF 5 4 RW Slow Blink Frequency This register must be used to configure the slow blinking frequency Constants 00 015 30 11g F02HZ 2 Hz blinking frequency F04HZ 4 Hz blinking frequency F08HZ 8 Hz blinking frequency F16HZ 16 Hz blinking frequency User s Manual Hardware Description 141 Revision 1 0 2012 02 17 amp LANTI C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MMD Registers Field Bits Type Description NACS 2 0 RW Inverse of SCAN Function This configuration defines in which state the complex SCAN should be activated The complex SCAN performs running off which turns back and forth between the first and last LED The speed is dependent on the MMD INTERNAL LEDCH FBF setting Constants 000 NONE No Function 001 LINK Complex function enabled when link is up 0105 PDOWN Complex function enabled when device is powered down 011 EEE Complex function enabled when device is in EEE mode 100 ANEG Complex function enabled when
33. Revision 1 0 2012 02 17 Hardware Description Lantiq XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s 6 6 6 RMII Interface Electrical Characteristics This section describes the AC characteristics of the RMII interface on the XWAY PHY11G This interface conforms to the RMII specification as defined by the RMII Consortium in 11 Figure 45 shows the timing diagram of the transmit MII interface on the XWAY PHY11G It is referred to by Table 53 which specifies the timing requirements at 10 Mbit s and 100 Mbit s respectively tcp hi A ten teL 4 y k tr 2 0 V 2n en 0 8 V avava DOY 20 V X 0 XK 08V ts Figure 45 Transmit Timing Diagram of the RMIl Table 53 Timing Characteristics of the RMII at 10 100 Mbit s Parameter Symbol Values Unit Note Min Typ Max Test Condition Reference clock period tcp 19 999 20 00 20 001 ns 50 ppm Reference clock frequency FREF 50 00 50 00 50 0 MHz x50 ppm 50 ppm 50 ppm Reference clock high time tcu 7 00 10 00 13 00 ns Reference clock low time teL 7 00 10 00 13 00 ns Reference clock duty cycle D tete 35 00 50 00 65 00 96 Rise time clock and data tr 1 00 5 00 ns Fall time clock and data te 1 00 5 00 ns Setup time subject to REFCLK jt 4 00 ns Hold time s
34. also use these bits for internal addressing The XWAY PHY11G supports this feature meaning that the DEVADR is OR combined with the corresponding memory address bits It is important to apply logic zeros wherever this overlap is present In 11 bit addressing mode there are overlays for EEPROMs with a capacity larger than 4 kb CRID 2 0 Specifies the Configuration Record ID The configuration record ID can be specified in case multiple PHYs source information from an EEPROM device in which case this contains multiple configuration record ID entries The CRID is part of the configuration record ID header allowing for storage of one distinct record for each PHY accessing the EEPROM see Chapter 3 4 2 4 for more details Note that in case the CRID is not found in the EEPROM the XWAY PHY11G uses the specified CRID as the MDIO address with the two MSBs set to zero User s Manual Hardware Description 46 Revision 1 0 2012 02 17 XWAY PHY11G PEF 7071 ru Lantiq Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description Table 18 Functions of Device Parameters controlled by Soft Pin Strapping EEPROM is Connected Device Parameter Function SPEED 1 0 Specifies the EEPROM Access Speed 00 STANDARD EEPROM is accessed at Fac 100 kHz serial clock speed 10 FASTMODE EEPROM is accessed at Fac 400 kHz serial clock speed 01 MEGASPEED EEPROM is accessed at Fac 1 MHz serial clock
35. auto negotiation error Constants Og INACTIVE Interrupt is masked out 1g ACTIVE Interrupt is activated User s Manual 124 Revision 1 0 2012 02 17 Hardware Description iz Lanti C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers Field Bits Type Description ANC 10 ROLH Auto Negotiation Complete Interrupt Status When active and masked in IMASK the MDINT is activated upon completion of the auto negotiation process Constants Og INACTIVE Interrupt is masked out 1g X ACTIVE Interrupt is activated RESH 9 8 ROLH Reserved Write as zeroes ignore on read RESL T 6 ROLH Reserved Write as zeroes ignore on read ADSC ROLH Link Speed Auto Downspeed Detect Interrupt Status When active and masked in IMASK the MDINT is activated upon detection of a link speed auto downspeed event Constants Og INACTIVE Interrupt is masked out 1g ACTIVE Interrupt is activated MDIPC ROLH MDI Polarity Change Detect Interrupt Status When active and masked in IMASK the MDINT is activated upon detection of an MDI polarity change event Constants Og INACTIVE Interrupt is masked out 1g ACTIVE Interrupt is activated MDIXC ROLH MDIX Change Detect Interrupt Status When active and masked in IMASK the MDINT is activated upon detection of an MDI MDIX cross over change event Constants Og INAC
36. bit 0 of the TXD 1 0 RMII transmit data vector It is synchronous with REFCLK RTBI Transmit Data Bits 0 and 5 This pin carries bits O and 5 of the double data rate RTBI transmit data vector It is synchronous with TBI TXCKL The bits are subject to the rising and falling edges respectively of TBI TXCLK HD SGMII Serial Input Positive Pin This is the positive signal of the differential input transmit pair of the SGMII SerDes interface In conjunction with SIN it samples a 1 25 Gbit s differential data signal Due to the integrated CDR no external MAC source synchronous clock is required This pin must be AC coupled For more details see Chapter 6 8 6 1000BASE X Receive Data Positive Pin This is the positive signal of the differential receive input pair of the 1000BASE X SerDes interface In conjunction with RDN it constitutes a 1 25 Gbit s differential data signal driven by the fiber optic module This pin must be AC coupled For more details see Chapter 6 8 7 15 TX CTL TX EN TXD49 SIN RDN LVTTL CMOS PD RGMII Transmit Control This pin is the transmit control signal for the TXD 3 0 RGMII transmit data vector It is synchronous with TXC RMII Transmit Enable This is the transmission enable signal driven by the MAC and which is synchronous with REFCLK The signal indicates valid data frames on TXD 1 0 to the PHY The signal polarity is active high RTB
37. bit data vector in both the transmit and receive directions The clock signal is always driven by the signal source that is the MAC in the transmit direction and the PHY in the receive direction The control and data signals change with both the rising and falling edges of the driving clock The nominal driving clock frequency at data speeds in gigabits is of 125 MHz Lower speeds of 10 Mbit s and 100 Mbit s can be achieved by reducing the clock frequency to 2 5 MHz and 25 MHz respectively At these speed grades the higher half of the data octet has no content Instead the XWAY PHY11G device accepts a replicated version of TXD 3 0 on the falling clock edge thus 1 HSTL logic drivers are not supported Instead standard LVTTL drivers are used User s Manual 33 Revision 1 0 2012 02 17 Hardware Description gU L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description reducing power consumption This is not possible for the TX_CTL and RX_CTL control signals as these still need to multiplex the GMII_TX_EN GMII_TX_ER and the GMII RX EN GMII RX DV signals In order to reduce the power consumption on this interface the RGMII specification defines a special coding of these control signals such that TX EN GMII TX EN TX ER GMII TX EN XOR GMII TX ER RX EN GMII RX EN RX ER GMII RX DV XOR GMII RX ER The TX CTL signal transports the TX EN subject to the rising edge whereas TX ER i
38. by selecting transformers with improved parameters Note that the IC side center taps of the transformer must not be connected and should be left open In particular transformer types which short all IC side center taps together must not be used en oO 2 5 lt 0 un Figure 56 Schematic of a Typical Gigabit Ethernet Transformer Device Table 64 Electrical Characteristics for Supported Transformers Magnetics Parameter Symbol Values Unit Note Test Condition Min Typ Max Turns ratio 1 tr 0 95 1 00 1 05 5 Differential to common DCMR 43 dB 30 MHz mode rejection 37 dB 60 MHz 33 dB 100 MHz Crosstalk attenuation CTA 45 dB 30 MHz 40 dB 60 MHz 35 dB 100 MHz Insertion loss IL 1 dB 0 1 MHz sf s 100 MHz 1 Also often referred to as magnetics User s Manual 175 Revision 1 0 2012 02 17 Hardware Description Er Lanti C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Electrical Characteristics Table 64 Electrical Characteristics for Supported Transformers Magnetics cont d Parameter Symbol Values Unit Note Test Condition Min Typ Max Return loss RL 18 0 dB 1MHzsfs30MHz 14 0 dB 31 MHz lt f lt 40 MHz 13 0 dB 41 MHz lt f lt 50 MHz 12 0 dB 51 MHz lt f lt 80 MHz 10 0 dB 81 MHz lt f lt
39. characteristics of the external interfaces 6 6 1 Reset The XWAY PHY11G supports an asynchronous hardware reset RSTN The timing requirements of the XWAY PHY11G related to the RSTN pin are listed in Table 48 The timing requirements refer to the signal sequence waveforms shown in Figure 43 After the power supply settling time all primary input signals to the XWAY PHY11G must be defined In particular the device reset RSTN must be held for a time t As shown in Figure 43 the reference clock either generated internally using an attached crystal or applied externally from an external crystal oscillator should be available at the latest before the reset is released This setup time is denoted as t e The maximum slope of the rising edge of the reset signal is constrained by the rise time t In case the integrated DC DC switching regulator is used to self supply the low voltage domains the reference clock must not be interrupted at all unless when powering down the system The XWAY PHY11G only starts booting its integrated device controller after the clock is running and the reset signal has been released After locking the PLL to the reference clock the device does soft pin strapping as well as an EEPROM scan only if an EEPROM is connected Since the default values inside the MDIO address space are modified by both procedures the first MDIO access is only allowed after a time tupio Once the device is powered up the clo
40. clock signals can be delayed using a programmable skew value in order to obtain a robust setup and hold the time relationships between the clock and the data control signals at the receiving pins The programmability of the skew value addresses the particularities of the given PCB environment in which the XWAY PHY11G device is embedded Supported test loops Chapter 3 6 3 can be activated at any time The speed at which the test loop operates depends on the state of the transceiver Activating a test loop during an active link implies that the currently selected link speed for example after auto negotiation Chapter 3 3 2 or auto downspeed Chapter 3 3 3 is used Otherwise the test loop is operated at the speed grade specified by the registers 0 13 and 0 6 User s Manual 36 Revision 1 0 2012 02 17 Hardware Description fer L XWAY PHY11G PEF 7071 Ee ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description 3 3 Media Functions This chapter describes the media functions supported by the XWAY PHY11G 3 3 1 Media Dependent Interfaces MDI This section describes the Media Dependent Interfaces MDIs that are supported by the XWAY PHY11G 3 3 1 1 Copper Interface The Twisted Pair Interface TPI of the XWAY PHY11G is fully compliant with IEEE 802 3 1 To facilitate low power implementation and reduce PCB costs the series resistors that are required to terminate the twisted pair link to nom
41. consumption Through implementation of a real voltage mode line driver the active nominal power of the device is significantly reduced when compared to other devices of the same kind Additionally this line driver technology does not require any center tap supply at the magnetics This further simplifies the magnetics as there is now no need to use common mode chokes The XWAY PHY11G supports further power savings at system level by means of the integrated Wake on LAN WoL feature This mode can be activated at all Ethernet speeds A WoL event is indicated to the SoC via an interrupt pin It is possible to configure the polarity and functionality of this interrupt Various events may be indicated via this interrupt so as to reduce the need for MDIO polling by the SoC The XWAY PHY11G provides a set of 3 freely configurable LED pins Although LEDs can also be directly driven by the SoC for example a network processor via MDIO registers the built in functionality covers application needs such as bi color LED support configurable blinking frequencies and configurable multiple function assignment per LED User s Manual 12 Revision 1 0 2012 02 17 Hardware Description ae Leona XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s 1 2 Overview Introduction This section gives an overview of the features and capabilities of the XWAY PHY11G Version 1 5 1 2 1 Logic Symbol Figure 1 shows the logic
42. dd ee eU I acer RARE fas 27 2 2 6 JTAG Sia CC Jm 28 2 2 7 Power Supply Pins ooo 29 3 Functional Description 2 000000 rr 30 3 1 Modes of Operation 0002 c cette rn 30 3 1 1 Copper FIOW eee rea cra Toh a a ieee AD eu pee id Gea ek Wed Mane Ae ee 31 3 1 2 Media Converter Flow 0 0 ee eee 31 3 2 Media Independent Interfaces MI 0 0 00 cee eee eae 32 3 2 1 X speed Media Independent Interface xMIl cee eae 32 3 2 1 1 xMII Signal Multiplexing 0 0 0 0 ccc eee eee 32 3 2 1 2 xMII Signal Conditioning 0 ce a 32 3 2 2 Reduced Media Independent Interface RMI 0 0 eee 33 3 2 3 Reduced Gigabit Media Independent Interface RGMII 0 00 cee 33 3 2 4 Serial Gigabit Media Independent Interface SGMII 1 2 0 0 0 ee eee 35 3 2 5 Reduced Ten Bit Interface RTBI 0 0 cette eee ee 35 3 3 Media FUNCIONS iru ER dul ee erar males ated n Phe Chale as 37 3 3 1 Media Dependent Interfaces MDI 0 0 cece eee 37 3 3 1 1 Copper Intetface s is aan Sheba aks eee meal Rh ERR CE Ren Rea lg PUR RC gene eee Roan ee Be Ae CR UR 37 3 3 1 2 Fiber Interface cu bee ee a ee 37 3 3 2 Auto NegotlallOli 2 tero IA Se a UR ae ie dte es E 38 3 3 3 A to Downspeed tc dda da site Pra DEIN LAR ee a PER ESAE EUR A 38 3 3 4 Auto Crossover and Polarity Reversal Correction 0 0000 aaaea 39 3 3 5 Transformerless Ethernet TLE oooccccccccco eee eae 40
43. external pull up low active MDINT or pull down high active MDINT resistor A value of 10 kQ is recommended In case multiple XWAY PHY11G devices are controlled by one higher level management entity these signals can be combined using a wired or After the XWAY PHY11G is reset the signal becomes active to indicate that it is ready to accept MDIO inputs The register MDIO PHY ISTAT needs to be read to deactivate this signal LED Interface 24 LEDO 1 0 A LEDO This is a freely configurable LED port that can be used to connect a preferably low current LED Note This pin reads in soft pin strapping information during reset 23 LED1 1 0 A LED1 This is a freely configurable LED port that can be used to connect a preferably low current LED Note This pin reads in soft pin strapping information during reset 22 LED2 1 0 A LED2 This is a freely configurable LED port that can be used to connect a preferably low current LED Note This pin reads in soft pin strapping information during reset User s Manual 27 Revision 1 0 2012 02 17 Hardware Description amp LANTI C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s External Signals Table 6 Control Interface Pins cont d Pin No Name Pin Buffer Function Type Type EEPROM C Two Wire Interface 43 SCL O LVTTL Serial Clock CMOS This is the serial clock
44. header which is a sequence of 6 consecutive FF Bytes Following this header is a repetition for 16 times of the target MAC address of the device to be woken up Note that this address can also be any standard broadcast address An optional field containing a 6 Byte wake up password follows The XWAY PHY11G scans for this password if it is configured Otherwise this field is ignored User s Manual 74 Revision 1 0 2012 02 17 Hardware Description FT L XWAY PHY11G PEF 7071 e 1 YTIC Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description The XWAY PHY11G is a pure PHY and does not include a MAC or have a MAC address The SoC must configure its own MAC address for example AA BB CC DD EE FF into the WoL packet monitoring engine of the XWAY PHY11G using the MDIO interface The same applies in case the optional password is intended to be used The configuration of the MAC address and the optional SecureOn password relevant for the WoL logic inside the XWAY PHY11G is performed via MDIO registers For the given example programming is done according to the steps illustrated in Table 29 Note that by definition a SecureOn password of 00 00 00 00 00 00 means that no SecureOn password is defined and therefore none is checked Ethernet Frame Header Magic Packet Header 6 times FF 16 times repeated MAC address of device which is to be woken up Optional 6 Byte Password
45. mapping The content of this register is only valid when the link is up PHYSTAT1 Offset Reset Value Physical Layer Status 1 114 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LSAD MDIC MDIA S D B RO ROSC RO RO RO RO RO RO RO RESH POLD POLC PPOLB POLA RESL Field Bits Type Description RESH 15 9 RO Reserved Write as zero ignored on read LSADS 8 ROSC Link Speed Auto Downspeed Status Monitors the status of the link speed auto downspeed controlled in PHYCTL1 LDADS Constants 03 NORMAL Did not perform any link speed auto downspeed 1 DETECTED Detected an auto downspeed POLD 7 RO Receive Polarity Inversion Status on Port D Constants 0s NORMAL Polarity normal 1 INVERTED Polarity inversion detected POLC 6 RO Receive Polarity Inversion Status on Port C Constants Oz NORMAL Polarity normal 1g INVERTED Polarity inversion detected POLB 5 RO Receive Polarity Inversion Status on Port B Constants Og NORMAL Polarity normal 1g INVERTED Polarity inversion detected POLA 4 RO Receive Polarity Inversion Status on Port A Constants Og NORMAL Polarity normal 1g INVERTED Polarity inversion detected MDICD 3 RO Mapping of MDI ports C and D Constants Og MDI Normal MDI mode 1 MDIX Crossover MDI X mode MDIAB 2 RO Mapping of MDI ports A and B Constants 0s MDI Normal MDI mode 1 MDIX Crossover MDI X mode User s Manual 109 Revision 1 0 201
46. of 10GBASE KR EEE Constants 0 DISABLED This PHY mode is not supported for EEE 1 ENABLE This PHY mode is supported for EEE EEE 10GBKX 4 RO Support of 10GBASE KX4 EEE Constants 0 DISABLED This PHY mode is not supported for EEE 1g ENABLE This PHY mode is supported for EEE EEE 1000BK X RO Support of 1000BASE KX EEE Constants Og DISABLED This PHY mode is not supported for EEE 1g ENABLE This PHY mode is supported for EEE EEE 10GBT RO Support of 10GBASE T EEE Constants Og DISABLED This PHY mode is not supported for EEE 1g X ENABLE This PHY mode is supported for EEE EEE 1000BT RO Support of 1000BASE T EEE Constants 0 DISABLED This PHY mode is not supported for EEE 1 ENABLE This PHY mode is supported for EEE EEE 100BTX RO Support of 100BASE TX EEE Constants Og DISABLED This PHY mode is not supported for EEE 1g ENABLE This PHY mode is supported for EEE User s Manual Hardware Description 136 Revision 1 0 2012 02 17 d Leona XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s EEE Wake Time Fault Count Register MMD Registers EEE WAKERR Offset Reset Value EEE Wake Time Fault Count Register 03 0016 0000 15 14 13 12 11 10 9 8 7 4 3 2 1 0 ERRCNT RO Field Bits Type Description ERRCNT 15 0 RO TXLPI Has Been Received This register is used by PHY types that support EEE to count wake time
47. of the BLINK or SCAN ISCAN LED functions can be selected by means of a global setting in the MMD INTERNAL LEDCH FBF register fast blinking frequency as well as in the MMD INTERNAL LEDCH SBF register slow blinking frequency Refer to LED Configuration for more information 3 4 4 3 3 LED Configuration in ICM The configuration of LEDs for ICM can be managed with the LED configuration registers Apart from the complex function registers MMD INTERNAL LEDCH and MMD INTERNAL LEDCL there is one such register for each LED port registers MMD INTERNAL LEDOH MMD INTERNAL LEDOL through MMD INTERNAL LED2H MMD INTERNAL LED2L The layout of this type of configuration register is defined in Chapter 4 Each supported direct function owns a field in these LED specific configuration registers The setup of the direct functions is independent for each LED The fields of the MMD INTERNAL LEDxx register allow several states events of the XWAY PHY11G to be mapped to the supported direct functions If a direct function is not desired a NONE must User s Manual 64 Revision 1 0 2012 02 17 Hardware Description gU L XWAY PHY11G PEF 7071 fes ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description be mapped Note that multiple events states can occur simultaneously The direct functions apply according to the priority as specified in Table
48. of the IC interface The maximum frequency PU of this interface is 1 MHZ The frequency is configurable via the soft pin strapping pins This clock is only active when an EEPROM is connected and during an access to the EEPROM The duty cycle is 50 44 SDA 1 0 LVTTL Serial Data Address CMOS This is the serial data address of the 1 C interface that shall PU optionally be connected to an external EEPROM supporting an lC or Two Wire interface An operational mode using an external EEPROM is useful in systems without a higher level management entity The XWAY PHY11G automatically detects a connected EEPROM by monitoring the SDA pin after reset or power up This pin must be connected to GND to indicate that no EEPROM is present If an EEPROM is present the soft pin strapping pins are used to define the speed and operational mode of the EEPROM interface 2 2 6 JTAG Interface This section describes the JTAG test pins used for boundary scan testing Table 7 JTAG Interface Pins Pin No Name Pin Buffer Function Type Type 21 TDO O LVTTL JTAG Serial Test Data Output CMOS 18 TDI LVTTL JTAG Serial Test Data Input 20 TMS CMOS JTAG Test Mode Select 19 TCK de JTAG Test Clock The TDI TDO and TMS signals are synchronized with this JTAG test clock Note If the JTAG interface is not used this pin must be tied to V py using a pull up resistor 1 JTAG reset is achieved by an internal po
49. on VDDP Ryppp 100 0 mV Peak value Power supply ripple on VDDH Ryppy 50 0 mV Peak value Power supply ripple on VDDR RyppR 100 0 mV Peak value 6 6 3 Input Clock Table 50 lists the input clock requirements for the case when no crystal is used that is when an external reference clock is applied at the XTAL1 pin of the XWAY PHY11G The table includes nominal frequency frequency deviation duty cycle and signal characteristics If a crystal is used with the integrated oscillator to generate the reference clock the clock requirements stated here are implicitly met as long as the specification for the crystal outlined in Chapter 6 8 1 is satisfied Table 50 AC Characteristics of Input Clock on XTAL1 Pin Parameter Symbol Values Unit Note Min Typ Max Test Condition Frequency with 25 MHz input foros 25 0 MHz Frequency with 125 MHz input foit25 125 0 MHz Frequency deviation 50 0 50 0 ppm l Duty cycle 40 0 50 0 60 0 96 Rise fall times 1 0 ns 1 More details on how to select the output frequency are given in Chapter 3 4 1 User s Manual Hardware Description 161 Revision 1 0 2012 02 17 ral XWAY PHY11G PEF 7071 E LANTIC Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Electrical Characteristics 6 6 4 Output Clock Table 51 lists the output clock requirements for the CLKOUT pin on the XWAY PH
50. one pin instead of just a single configuration bit The content of the bit vector is determined by the component value of the pull down resistor or capacitance used The component value of this resistor is measured by the XWAY PHY11G shortly after reset A schematic of the required external circuitry is shown in Figure 13 V LEDx e GND e Rerax Corax Figure 13 Soft Pin Strapping External Circuitry As shown in the figure a further saving in pin count is achieved by sharing the pins used to drive LEDs LEDx with the pin strapping configuration The choice of soft pin strapping configuration component values is such that normal LED operation is left unaffected The LED components are shown in gray in Figure 13 Note that the pin strapping passive components weakly tie the LEDx pin to the chip s ground More details on the external circuitry for using LEDs can be found in Chapter 3 4 4 A 4 bit vector is encoded by the appropriate choice the component values The relationship between component values and the soft pin strapping bit vector is shown in Table 14 Table 14 Soft Pin Strapping Mapping of Pull Down Capacitance Resistor Values to Configuration Bits Capacitance Value Resistor Value Soft Pin Strapping Configuration Bit Vector CBV 3 0 CBV 3 CBV 2 CBV 1 CBV 0 Not mounted 0 nF 11 00 KQ 0g 0g 0g Og 8 66 kQ 0g 0g Og 1p 6 81 kQ 0g 0g 1p Og 5 23 kQ 0g 0g 1g 1g 3 92 kO 0g
51. pin In such cases a pull up resistor Ry should be included to weakly pull the SIGDET signal to Vppp in a high impedance situation This is shown in Figure 60 by the area shaded in gray FA VDDP Rou SIGDET LOS C TDP Transmission TX_DAT Line TDN 500 TX_DAT C C RDP Transmission RX_DAT Line RDN 500 RX_DAT C PHY A FO Module Figure 60 External Circuitry for a 1000BASE X Interface Table 68 Electrical Characteristics for the 1000BASE X External Components Parameter Symbol Values Unit Note Test Condition Min Typ Max Coupling capacitance C 90 100 110 nF 10 Pull up resistance Ros 1 kQ 110 User s Manual 181 Revision 1 0 2012 02 17 Hardware Description fer L XWAY PHY11G PEF 7071 ZE ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Package Outline 7 Package Outline This section outlines all relevant packaging information The Lantiq XWAY PHY11G device is available in a 48 pin Very Thin Quad Flat Non leaded VOFN package with an exposed pad EPAD The pad pitch is 0 5 mm and the size of the EPAD is 5 2 x 5 2 mm The EPAD is used as the common ground and must be connected to the PCB ground plane The package is a lead free green package and its exact name for purposes of reference is PG VQFN48 15 Figure 61 contains the top side and bottom dimension drawings of the VQFN48 package _
52. read write operations INSTR DADR 7 1 DATA n 7 0 DATA n 1 7 0 DATA n x 7 0 jj m m Figure 19 Timing Diagram for a Burst Read 3 4 2 4 3 EEPROM Access via MDIO The XWAY PHY11G supports indirect access to the EEPROM via the MDIO interface A special type of handshaking between the higher level management entity and PHY is required for proper cycle time arbitration The flow charts in Figure 20 and Figure 21 illustrate this handshake mechanism for a write and a read cycle respectively Note that only single byte accesses are supported as opposed to EEPROM burst mode options for better compatibility and simplicity As can be seen from the flow charts the first action before any operation is to check whether the EEPROM is busy or ready to use This is done using the PHY EECTRL EXEC bit This bit could still be set from a past write cycle or other internal means preventing a current EEPROM access Any access to the EEPROM is performed via MMD on device 1E The entire EEPROM is mapped onto this indirect MDIO addressable space see also Chapter 3 4 3 2 A write cycle is simply executed by setting address and write data in conjunction with the control bits Once this is done the XWAY PHY11G takes care of storing the byte into the EEPROM A read cycle is similar but after issuing a read access the higher level management entity needs to wait until the data is read from the EEPROM This is done by ob
53. source address nibble The source address builds up to 00 03 19 FF FF F SA DATA 7 0 RW Data Byte to be Transmitted This is the content of the payload bytes in the frame User s Manual Hardware Description 130 Revision 1 0 2012 02 17 Ag Lanria XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Firmware Version Register MDIO Registers This register contains the version of the PHY firmware FWV Offset Reset Value Firmware Version Register 1E 8406 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 REL MAJOR MINOR L i i i RO RO RO Field Bits Type Description REL 15 RO Release Indication This parameter indicates either a test or a release version Constants Og TEST Indicates a test version 1 RELEASE Indicates a released version MAJOR 14 8 RO Major Version Number Specifies the main version release number of the firmware MINOR 7 0 RO Minor Version Number Specifies the sub version release number of the firmware Reserved Reserved for future use RES1F Offset Reset Value Reserved 1F 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RES RO Field Bits Type Description RES 15 0 RO Reserved Write as zero ignored on read User s Manual 131 Revision 1 0 2012 02 17 Hardware Description ew Lantiq XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s 5 MMD Registers This chapter defines the MM
54. speed 11 HIGHSPEED EEPROM is accessed at Fac 3 4 MHz serial clock speed SIZE 1 0 Specifies the EEPROM Scan Size This parameter defines the EEPROM scan size which is the address range of the EEPROM in which the configuration record more details in Chapter 3 4 2 3 is searched for during boot up or after reset of the XWAY PHY11G The physical size of the EEPROM is less important The configuration signature record may contain pointer addresses to an address beyond the limit specified here The scan starts at EEPROM address 0000 In order to yield a constant worst case scan time over all supported EEPROM scan sizes the address increment for the EEPROM configuration record scan is adjusted automatically depending on the scan size as follows ADRMODE 0g SIZE 1 0 00 lt 2 kb scan up to 256 byte addresses in steps of 32 SIZE 1 0 0154 kb scan up to 512 byte addresses in steps of 64 SIZE 1 0 10 8 kb scan up to 1024 byte addresses in steps of 128 SIZE 1 0 11516 kb scan up to 2048 byte addresses in steps of 256 ADRMODE 15 SIZE 1 0 00 32 kb scan up to 4096 byte addresses in steps of 512 SIZE 1 0 01 64 kb scan up to 8192 byte addresses in steps of 1024 SIZE 1 0 10 128 kb scan up to 16384 byte addresses in steps of 2048 SIZE 1 0 11 gt 256 kb scan up to 32768 byte addresses in steps of 4096 User s Manual Hardware Description 47 Revision 1 0 2012 02 17 E L XWAY PHY11G PEF 707
55. supply of the XWAY PHY11G This supply has to provide a nominal voltage of Vopp 2 5 V 3 3 V with a worst case tolerance of 5 at the respective corners Note For optimal power consumption the lowest possible voltage is selected in the system 17 VDDL PWR Low Voltage Domain Supply This is the group of supply pins for the low voltage domain which supplies mixed signal blocks in the PMA of the XWAY PHY11G The supply has to provide a nominal voltage of Vpp 1 0 V with a worst case tolerance of 5 8 13 40 VDDC PWR Core Voltage Domain Supply This is the group of supply pins for the core voltage domain It supplies the digital core blocks of the XWAY PHY11G This supply has to provide a nominal voltage of Vpp 1 0 V with a worst case tolerance of 15 EPAD VSS GND General Device Ground 1 The EPAD is the exposed pad at the bottom of the package This pad must be properly connected to the PCB ground plane User s Manual Hardware Description 29 Revision 1 0 2012 02 17 XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Lanrio Functional Description 3 Functional Description Figure 7 shows a block diagram of the XWAY PHY11G device It also outlines the relationship of the device pins to the main functional blocks The following sections describe the functionality of these blocks in more detail
56. switching regulator is used then a clock signal is required at XTAL1 during both normal mode and boundary scan mode 3 5 1 1 Power Supply Using Integrated Switching Regulator By using the integrated DC DC switching regulator the XWAY PHY11G can be powered using a single power supply This power supply can range from 2 5 V to 3 3 V As long as the applied nominal voltage remains in this range the device operates automatically and without the need for additional settings to be applied Only minor external circuitry is required to enable this feature An example schematic is shown in Figure 29 The electrical characteristics of the power supply are defined in Chapter 6 2 Voo 2 5 3 3 V Figure 29 External Circuitry using the Integrated Switching Regulator The required values for external components are listed in Table 28 Table 28 Switching Regulator External Component Values Parameter Symbol Values Unit Note Test Condition Min Typ Max DC DC buck inductance Loene 4 7 HH Imax 450 MA DC DC smoothing capacitance Cocpc 22 0 UF User s Manual 66 Revision 1 0 2012 02 17 Hardware Description XWAY PHY11G PEF 7071 Functional Description Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s ET LANTI q Table 28 Switching Regulator External Component Values cont d Parameter Symbol Values Unit Note Test Condi
57. takes effect when the auto negotiation process is disabled that is bit CTRL ANEN is set to zero This is the LSB CTRL SSL of the forced speed selection register SS In conjunction with the MSB CTRL SSM the following encoding is valid SS 0 10 Mbit s SS 1 100 Mbit s SS 2 1000 Mbit s SS 3 Reserved User s Manual 86 Revision 1 0 2012 02 17 Hardware Description 2 Len XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers Field Bits Type Description ANEN 12 RW Auto Negotiation Enable Allows enabling and disabling of the auto negotiation process capability of the PHY If enabled the force bits for duplex mode CTRL DPLX and the speed selection CTRL SSM CTRL SSL become inactive Otherwise the force bits define the PHY operation See also IEEE 802 3 2008 22 2 4 1 4 1 Constants 0 DISABLE Disable the auto negotiation protocol 1g ENABLE Enable the auto negotiation protocol PD 11 RW Power Down Forces the device into a power down state where power consumption is the bare minimum required to still maintain the MII management interface communication When activating the power down functionality the PHY terminates active data links None of the xMII interfaces work in power down mode See also IEEE 802 3 2008 22 2 4 1 5 1 Constants 0s NORMAL Normal operational mode 1 POWERDOWN Forces the device into power down mode ISOL 10 RW Iso
58. the XWAY PHY11G supports the op codes as shown in Table 30 Table 30 JTAG TAP Controller Op Codes Instruction Instruction Code JTAG Register Register Width Comment EXTEST 0000 0000g Boundary scan Allows for testing of external circuitry connected between XWAY PHY11G and other components on the same PCB The XWAY PHY11G drives a previously loaded using the PRELOAD instruction pattern to all its outputs and samples all its inputs SAMPLE PR ELOAD 0000 0001 Boundary scan Allows a snapshot to be taken of all pins within the boundary scan during normal mode of operation as well as for the values to be read out This instruction also allows for patterns to be loaded into the boundary scan test cells in advance of other JTAG test instructions IDCODE 0001 00015 Device ID 32 Returns the JTAG boundary scan ID according to Table 31 on TDO CLAMP 0000 0010 Bypass Allows the state of the signals driven from all XWAY PHY11G pins within the boundary scan to be determined from the boundary scan register Simultaneously the bypass register is selected as the serial path between TDI and TDO The signals determined from the boundary scan register remain unchanged while the CLAMP instruction is selected HIGHZ 0000 0011 Bypass Forces all outputs of the XWAY PHY11G into a high impedance state This prevents damage of components when testing according
59. the state of the TX EN signal is looped back to the COL signal within a minimum latency time See also IEEE 802 3 2008 22 2 4 1 9 1 Constants 0 DISABLE Normal operational mode 1g ENABLE Activates the collision test SSM RW Forced Speed Selection MSB See the description of SSL See also IEEE 802 3 2008 22 2 4 1 3 1 RES 5 0 RO Reserved Write as zero ignore on read User s Manual Hardware Description 88 Revision 1 0 2012 02 17 E L XWAY PHY11G PEF 7071 Ee ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers Status Register This register contains status and capability information about the device Note that all bits are read only A write access by the MAC does not have any effect See also IEEE 802 3 2008 22 2 4 2 1 STAT Offset Reset Value Status Register 01 7949 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CBTX CBTX CBT2 CBT2 F H F H RO RO RO RO RO RO RO RO RO RO RO ROLH RO ROLL ROLH RO CBT4 XBTF XBTH EXT RES MFPSANOK RF ANAB LS JD XCAP Field Bits Type Description CBT4 15 RO IEEE 100BASE T4 Specifies the 100BASE T4 ability See also IEEE 802 3 2008 22 2 4 2 1 1 Constants Og DISABLED PHY does not support this mode la ENABLED PHY supports this mode CBTXF 14 RO IEEE 100BASE TX Full Duplex Specifies the 100BASE TX full duplex ability See also IEEE 802 3 2008 22 2 4 2
60. the transmitted link code word was equal to logic ZERO MCF 10 0 RW Message or Unformatted Code Field See also IEEE 802 3 2008 28 2 3 4 1 User s Manual Hardware Description 98 Revision 1 0 2012 02 17 ET Lanm C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers Auto Negotiation Link Partner Received Next Page Register The auto negotiation link partner received next page register contains the next page link code word received from the link partner See also IEEE 802 3 2008 28 2 4 1 7 1 AN NPRX Auto Negotiation Link Partner Received 08 2001 Next Page Register 15 14 13 12 11 Offset Reset Value 10 9 8 7 6 5 4 3 2 1 0 NP ACK MP ACK2 TOGG MCF RO RO RO RO RO RO Field Bits Type Description NP 15 RO Next Page See IEEE 802 3 2008 28 2 3 4 1 Constants Og INACTIVE No next pages to follow lg ACTIVE Additional next page s will follow ACK 14 RO Acknowledge See also IEEE 802 3 2008 28 2 3 4 1 Constants 0s INACTIVE The device did not successfully receive its link partner s link code word 1g ACTIVE The device has successfully received its link partner s link code word MP 13 RO Message Page Indicates that the content of MCF is either an unformatted page or a formatted message See also IEEE 802 3 2008 28 2 3 4 1 Constant
61. this requires 12 to 16 address bits The larger storage space can be used for customized firmware code or for sharing among several devices by using I C functionality In contrast to the 11 bit addressing mode the 16 bit addressing mode uses two bytes following the IC instruction to encode the memory address The three LSBs of the device address are available for selecting one out of eight EEPROM devices attached to the same I C serial bus This device address is configurable using the soft pin strappings as described in Chapter 3 4 1 In order to clarify this further Table 23 lists the address mappings for all supported EEPROM sizes User s Manual 52 Revision 1 0 2012 02 17 Hardware Description gU L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description Table 23 Address Bit Mapping in 16 Bit Addressing Mode EEPROM Size IC Instruction Bit 1 Memory Content Address 2 Memory Content Address Byte Byte 7 5 3 211 7 6 4 3 2 10 7 654 3 2 1 0 32kb 1 O 1 O IX IX X O JO ADR 1 1 0 64 kb X X X0 JO ADR 12 0 128 kb X X X JO O ADR 13 0 256 kb X XX JO ADR 14 0 512 kb X X X ADR 15 0 Figure 17 shows the 4 byte frame format for a single byte write operation to a random address on the EEPROM For maximum compatibility this is the only write frame format supported Following a start b
62. to integrated termination resistors 28 TPIBP 1 0 A Differential Tx Rx Port for Twisted Pair B 29 TPIBN This is the twisted pair port B that can be directly connected to the corresponding transformer pins Note This port has a 100 O nominal impedance due to integrated termination resistors 31 TPICP 1 0 A Differential Tx Rx Port for Twisted Pair C 32 TPICN This is the twisted pair port C that can be directly connected to the corresponding transformer pins Note This port has a 100 O nominal impedance due to integrated termination resistors 33 TPIDP 1 0 A Differential Tx Rx Port for Twisted Pair D 24 TPIDN This is the twisted pair port D that can be directly connected to the corresponding transformer pins Note This port has 100 O nominal impedance due to integrated termination resistors User s Manual Hardware Description 20 Revision 1 0 2012 02 17 2 2 4 Table 5 Et Lanti C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s External Signals Media Independent Interface MII Pins This section describes the Media Independent Interface MII which connects the MAC to the XWAY PHY11G Multiplexed pins support several interface types such as RMII RGMII RTBI and SGMII Due to the pin limitations and the large number of supported interfaces the multiplexing of pins between the different interfaces can be complex This chapter gives a detailed view of each pin Tabl
63. vem internal delayed TXCLK YN YN YX Se To TXDI4 0 x tu ts Figure 48 Transmit Timing Diagram of the RTBI Table 56 Transmit Timing Characteristics of the RTBI Parameter Symbol Values Unit Note Test Condition Min Typ Max Transmit clock frequency TX CLK fr c k 50 ppm 125 0 50 ppm MHz Transmit clock period TX CLK tcp 7 2 8 0 8 8 ns Transmit clock high time TX CLK tj 3 6 4 0 4 4 ns Transmit clock low time TX CLK ti 3 6 4 0 4 4 ns Transmit clock rise time TX CLK tr 750 0 ps 20 gt 80 Transmit clock fall time TX_CLK tr 750 0 ps 80 gt 20 Setup time to 7 internal TX_CLK ts 1 0 ns Hold time to t internal TX_CLK ty 1 0 ns Integrated transmit clock delay tip 0 0 k 0 5 3 5 ns Adjustable via MDIO register User s Manual 167 Revision 1 0 2012 02 17 Hardware Description fer L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Electrical Characteristics 6 6 8 2 Receive Timing Characteristics Figure 49 shows the timing diagram of the receive RTBI interface on the XWAY PHY11G It is referred to by Table 57 which specifies the timing requirements Note that the clock to data skew time is subject to the internal version of the RX CLK The external clock on the pin is delayed by the integrated delay which is adjustable in
64. 0 ee ee 157 Table43 DC Characteristics of the Receive MII Interface 0 eee 158 Table 44 DC Characteristics of the Transmit MII Interface llis 158 Table 45 DC Characteristics of the Transmit LED Interface liliis 158 Table 46 DC Characteristics of the JTAG Interface VDDH 2 5 V 0 eee 159 Table 47 DC Characteristics of the JTAG Interface VDDH 3 8 V 0 0 ee ee 159 Table 48 AC Characteristics of the RSTN Pin ssssseeee 161 Table 49 AC Characteristics of the Power Supply 000 20 e eee eee 161 User s Manual 10 Revision 1 0 2012 02 17 Hardware Description soe L XWAY PHY11G PEF 7071 d ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s List of Tables Table 50 AC Characteristics of Input Clock on XTAL1 Pin 000 0c eee eee 161 Table 51 AC Characteristics of Output Clock on CLKOUT Pin 00020 eeees 162 Table 52 AC Characteristics of the MDIO Interface 220202 cee es 162 Table 53 Timing Characteristics of the RMII at 10 100 Mbit s llli 163 Table 54 Transmit Timing Characteristics of the RGMII 1 2 0 0 0 ee 164 Table 55 Receive Timing Characteristics of the RGMII 220000 c eee eee 165 Table 56 Transmit Timing Characteristics of the RTBI 0 0 ee 167 Table 57 Receive Timing Characteristics of the RTBI 0 000 ee eee 168 Table 58 Transmit Timing Characteristic
65. 0 1000 Mbit s MMD Registers Wake On LAN Address Byte 0 Wake On LAN Address Byte 0 WOLADO Offset Reset Value Wake On LAN Address Byte 0 1F 0783 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 z ADO RW Field Bits Type Description ADO 7 0 RW Address Byte 0 Defines byte 0 of the WOL designated MAC address to which the PHY is sensitive Similar Registers The following registers are identical to the Register WOLADO defined above Table 37 Similar Registers Register Short Name Register Long Name Offset Address Reset Value WOLAD1 Wake On LAN Address Byte 1 1F 0784 0000 WOLAD2 Wake On LAN Address Byte 2 1F 0785 0000 WOLAD3 Wake On LAN Address Byte 3 1F 0786 0000 WOLAD4 Wake On LAN Address Byte 4 1F 0787 0000 WOLAD5 Wake On LAN Address Byte 5 1F 0788 0000 User s Manual 152 Revision 1 0 2012 02 17 Hardware Description gU L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MMD Registers Wake On LAN SecureON Password Byte 0 Wake On LAN SecureON Password Byte 0 WOLPWO Offset Reset Value Wake On LAN SecureON Password Byte 0 1F 0789 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWO RW Field Bits Type Description PWO 7 0 RW SecureON Password Byte 0 Defines byte 0 of the WOL designated SecureON password to which the PHY is sensitive Similar Registers The foll
66. 02 17 2 Lanm C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers Auto Negotiation Next Page Transmit Register The auto negotiation next page transmit register contains the next page link code word to be transmitted when next page ability is supported On power up this register contains the default value of 0x2001 which represents a message page with the message code set to the null message See also IEEE 802 3 2008 28 2 4 1 6 1 AN NPTX Offset Reset Value Auto Negotiation Next Page Transmit 07 2001 Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NP RES MP ACK2TOGG MCF RW RO RW RW RO RW Field Bits Type Description NP 15 RW Next Page See IEEE 802 3 2008 28 2 3 4 1 Constants Og INACTIVE Last page 1g ACTIVE Additional next page s will follow RES 14 RO Reserved Write as zeroes ignore on read MP 13 RW Message Page Indicates that the content of MCF is either an unformatted page or a formatted message See IEEE 802 3 2008 28 2 3 4 1 Constants Og UNFOR Unformatted page 1g MESSG Message page ACK2 12 RW Acknowledge 2 See also IEEE 802 3 2008 28 2 3 4 1 Constants Oz INACTIVE Device cannot comply with message 1g ACTIVE Device will comply with message TOGG 11 RO Toggle See also IEEE 802 3 2008 28 2 3 4 1 Constants 0 ZERO Previous value of the transmitted link code word was equal to logic ONE 1g ONE Previous value of
67. 02 3 2008 this register is used for Power Sourcing Equipment PSE status functions see IEEE 802 3 2008 33 6 1 2 1 which are not supported by this PHY RES12 Offset Reset Value Reserved 0C 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RES RO Field Bits Type Description RES 15 0 RO Reserved Write as zero ignored on read 104 Revision 1 0 2012 02 17 User s Manual Hardware Description E L XWAY PHY11G PEF 7071 Ee ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers MMD Access Control Register The MMD access control register is used in conjunction with the MMDDATA register to access the MMD register space Each MMD maintains its own individual address register as described in IEEE 802 3 2008 clause 45 2 8 1 The DEVAD field directs any accesses of register MMDDATA to the appropriate MMD as described in IEEE 802 3 2008 clause 45 2 For additional insight into the operation and use of the MMD registers see IEEE 802 3 2008 clause 22 2 4 3 11 Annex 22D and clause 45 2 1 MMDCTRL Offset Reset Value MMD Access Control Register 0D 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ACTYPE RESH RESL DEVAD RW RO RO RW Field Bits Type Description ACTYPE 15 14 RW Access Type Function If the access of register MMDDATA is an address access ACT YPE 0 then itis directed to the address register within the MMD associated with the value in the DEVAD field Otherwise bot
68. 1 fe ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description 3 4 2 Configuration of XWAY PHY11G via External EEPROM This chapter describes the operation of the XWAY PHY11G with an externally connected EEPROM 3 4 2 1 EEPROM Applications Connection of an external EEPROM is used to enable the implementation of systems without any higher level management entity to drive the control and configuration information on the MDIO interface see Chapter 3 4 3 In addition it is not possible to completely configure XWAY PHY11G functionality using only the soft pin strapping interface see Chapter 3 4 1 In such applications the external EEPROM provides a cheap and efficient solution for storing all the configuration information that needs to be loaded by the XWAY PHY11G during startup The XWAY PHY11G supports various EEPROM devices by means of its 1 C interface see Chapter 2 2 5 pins SDA and SCL The devices supported are listed in Table 19 Devices from other silicon vendors that are not listed in Table 19 and which support I C may also be supported but are not tested by Lantiq Table 19 Supported EEPROM Devices Vendor Device Remark AMTEL AT24Cxx Proper size selection by customers CATALYST CAT24Cxx Proper size selection by customers STM M24Cxx Proper size selection by customers In the simplest application the EEPROM is only used to store configuration information of the XW
69. 1g 0g O 2 74 kO 0g 1p Og 1p 1 78 kO 0g 1p 1p Op 0 91 kQ 0g 1g 1g 1g 1 The encoding of soft pin strappings is such that the use of external capacitors is rarely needed User s Manual 43 Revision 1 0 2012 02 17 Hardware Description gU L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description Table 14 Soft Pin Strapping Mapping of Pull Down Capacitance Resistor Values to Configuration Bits Capacitance Value Resistor Value Soft Pin Strapping Configuration Bit Vector CBV 3 0 CBV 3 CBV 2 CBV 1 CBV 0 Mounted 100 nF 11 00 KQ 1g 0g 0g 0g 8 66 kO 1p 0g Og 1p 6 81 kO 1g 0g 1g O 5 23 kQ 1g 0g 1g 1g 3 92 kO 1p 1p Og Og 2 74 kO 1g 1p Og 1p 1 78 kO 1g 1g 1g O 0 91 kQ 1g 1g 1g 1g 1 A maximum tolerance of 10 on temperature and aging must be guaranteed Ceramic type capacitors are suggested 2 A maximum tolerance of 1 on temperature and aging must be guaranteed Resistances are taken from the E96 series The soft pin strapping configuration is read from all three LED pins after device reset It is possible to encode a total of 12 information bits Table 15 outlines the mapping of bits to the supported pin strapping device parameters In this table each row represents a bit vector read from one of the configuration pins Each column corresponds to a bit position in the configuration bit vector Note that this ta
70. 2 1 Constants Og DISABLED PHY does not support this mode la ENABLED PHY supports this mode CBTXH 13 RO IEEE 100BASE TX Half Duplex Specifies the 100BASE TX half duplex ability See also IEEE 802 3 2008 22 2 4 2 3 1 Constants 0 DISABLED PHY does not support this mode 1g ENABLED PHY supports this mode XBTF 12 RO IEEE 10BASE T Full Duplex Specifies the 10 BASE T full duplex ability See also IEEE 802 3 2008 22 2 4 2 4 1 Constants 0 DISABLED PHY does not support this mode la ENABLED PHY supports this mode XBTH 11 RO IEEE 10BASE T Half Duplex Specifies the 10BASE T half duplex ability See also IEEE 802 3 2008 22 2 4 2 5 1 Constants Og DISABLED PHY does not support this mode 1g ENABLED PHY supports this mode User s Manual 89 Revision 1 0 2012 02 17 Hardware Description XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers Field Bits Type Description CBT2F 10 RO IEEE 100BASE T2 Full Duplex Specifies the 100BASE T2 full duplex ability See also IEEE 802 3 2008 22 2 4 2 6 1 Constants Og DISABLED PHY does not support this mode 1 ENABLED PHY supports this mode CBT2H 9 RO IEEE 100BASE T2 Half Duplex Specifies the 100BASE T2 half duplex ability See also IEEE 802 3 2008 22 2 4 2 7 1 Constants Og DISABLED PHY does not support this mode 1 ENABLED PHY supports this mode EXT 8 RO Extended Statu
71. 2 0 eee eee 138 5 3 EEPROM EEPROM Address Space MMD 0x1E o o ooccooccocococ 140 5 4 INTERNAL Internal Address Space MMD OX1F 20 000 ee eae 141 6 Electrical Characteristics 00 0 eee 155 6 1 Absolute Maximum Ratings 0 0 tent eee ae 155 6 2 Operating Range uio reeled bie ela iG A bias ede beet Ria due hae ees 156 6 3 Recommended Operating Conditions 0 0 eee 156 6 4 Power Up Sequence 0 0 ell rn 156 6 5 DC Characteristics EEUU 157 6 5 1 Digital Interfaces cdc cban hehe del teehee Pan ed dae Bae RG de Pa ee dus 157 6 5 1 1 GPIO Interfaces cq EE 157 6 5 1 2 MII Receive Interface 1 issu gu ge kh ek ho Eu e heh e Roh n E Roh m ee ee 158 6 5 1 3 MII Transmit Interface 2 26 62 ee o kg RR RE 4G p eh n eee 158 6 5 1 4 LED Interface ee pce rp t PCR dia Ru CR ela Op RUN ea Re eae 158 6 5 1 5 JTAG Interface ssepe Abe peta Abad exque ied ad ba beefbbeere 159 6 5 2 Twisted Pair Interface lise RR hn hh nns 159 6 5 3 SOMI Interface 35d RE A Rt Rb ERR ES 159 6 5 4 1000BASE X Interface esaa o a rh 159 6 6 AG Characteristics 25222 2129024dGg elc m RR TAS REL ore REMO Ea Ru hae eed 160 6 6 1 ROSEE c 160 6 6 2 Power Supply eiae Ha Rete exem obe seq del a onte tne ese VE e De a dane ese ea 161 6 6 3 hienaeldcc TmT 161 6 6 4 Output Clo6k 1 2 es daa CEA UR A E ROUTE RU E bee Re eoe rete 162 6 6 5 MDIO Interface sautada siina bae beber ada dores 162 6 6 6 RMI Interface
72. 2 02 17 Hardware Description XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers i Lantri C Field Bits Type Description RESL 1 0 RO Reserved Write as zero ignored on read 110 User s Manual Hardware Description Revision 1 0 2012 02 17 ew Lantiq XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers Physical Layer Status 2 This register reports PHY lock information for example pair skews in the GbE mode The content of this register is only valid when the link is up Reset Value 0000 PHYSTAT2 Offset Physical Layer Status 2 124 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESD SKEWD RESC SKEWC RESB SKEWB RESA SKEWA RO RO RO RO RO RO RO RO Field Bits Type Description RESD 15 RO Reserved Write as zero ignored on read SKEWD 14 12 RO Receive Skew on Port D The skew is reported as an unsigned number of symbol periods RESC 11 RO Reserved Write as zero ignored on read SKEWC 10 8 RO Receive Skew on Port C The skew is reported as an unsigned number of symbol periods RESB 7 RO Reserved Write as zero ignored on read SKEWB 6 4 RO Receive Skew on Port B The skew is reported as an unsigned number of symbol periods RESA 3 RO Reserved Write as zero ignored on read SKEWA 2 0 RO Receive Skew on Port A The skew is reported as an unsigned number of
73. 2 through to Chapter 2 2 7 respectively Chapter 2 2 1 explains the terminology used for the pin and buffer types 2 2 1 Pin Identifications The abbreviations used in the following sub sections for the pin types and buffer types are explained in Table 1 and Table 2 respectively Table 1 Abbreviations for Pin Types Type Long Name Remarks Input pin O Output pin 1 0 Bi directional pin PWR Power supply pin GND Ground pin Table 2 Abbreviations for Buffer Types Type Long Name Remarks A Analog levels This buffer type is used for purely analog levels The exact electrical characteristics are specified in the corresponding sections of Chapter 6 HD High speed differential This buffer type is used for SerDes pins for example for SGMII or 1000BASE X These pins are properly terminated with a resistance of 50 75 Q and must be AC coupled More details on the mandatory and optional external circuitry are given in Chapter 6 8 6 PU Internal pull up resistor This buffer type includes a weak internal pull up resistor which pulls the signal to Vppp logic 18 when left unconnected or tristated high impedance PD Internal pull down resistor This buffer type includes a weak internal pull down resistor which pulls the signal to Vssp logic Og when left unconnected or tristated high impedance LVTTL Digital LVTTL levels LVTTL buffer types according to JESD8 B Note that this buffer is o
74. 2012 02 17 Hardware Description XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Table of Contents Lantiq References Terminology User s Manual Hardware Description Revision 1 0 2012 02 17 XWAY PHY11G PEF 7071 ul Lantiq Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s List of Figures List of Figures Figure 1 Logic Symbol of the XWAY PHY11G occ 13 Figure 2 XWAY PHY11G Used in Copper Applications 02000 ee 15 Figure 3 XWAY PHY11G Used in Media Converter Applications 0000 00 eee eee 15 Figure 4 XWAY PHY11G Used in 10 100 1000BASE T GBIC SFP Applicati0N 16 Figure 5 Transmit and Receive Terminology 0000 eee 16 Figure 6 Pin Diagram of the XWAY PHY11G Top View of VQFN48 Package 17 Figure 7 Functional High Level Block Diagram of XWAY PHY11G ooo 30 Figure 8 xMII Signal Conditioning between MAC and XWAY PHY11G occ 33 Figure 9 Twisted Pair Interface of XWAY PHY11G Including Transformer and RJ45 Plug 37 Figure 10 External Circuitry for the Transformerless Ethernet Application llle 40 Figure 11 External Circuitry for TLE when Connected to Current Mode Line Driver Based PHY 41 Figure 12 Overview of the Configuration FlOW oooocccoooccoo eee 42 Figure 13 Soft Pin Strapping External Circuitry 0 0 00 RIA 43 Figure 14 Timing Diag
75. 26 Also note that a direct function always has a lower priority than any supported complex function As an example the following mapping can be configured for LEDO LED1 and LED2 e LEDO PULSE NONE BLINKS LINK10 BLINKF LINK100 CON LINK1000 LED1 PULSE ACTIVITY TXACT RXACT BLINKS NONE BLINKF NONE CON NONE LED2 PULSE COL BLINKS NONE BLINKF NONE CON NONE In this example the LEDO indicates the speed of the PHY whereas LED1 indicates the transmit and receive activity LED2 reflects any collision in case of half duplex mode settings If any supported complex function CBLINK SCAN NACS is desired in cable diagnostics mode this can be set up using the registers MMD INTERNAL LEDCL CBLINK SCAN and MMD INTERNAL LEDCH NACS User s Manual 65 Revision 1 0 2012 02 17 Hardware Description gU L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description 3 5 Power Management This chapter introduces the power management and power supply functions of the XWAY PHY11G 3 5 1 Power Supply Because of its integrated DC DC switching regulator the XWAY PHY11G can be powered using a single power supply as described in Chapter 3 5 1 1 However the device can also be powered without the integrated DC DC switching regulator as described in Chapter 3 5 1 2 If the integrated DC DC
76. 40 5 1 1 register 10 in Table 40 3 1 Constants 0 OK Master slave manual configuration resolved successfully 1g NOK Master slave manual configuration resolved with a fault MSRES 14 RO Master Slave Configuration Resolution See IEEE 802 3 40 5 1 1 register 10 in Table 40 3 1 Constants Oz SLAVE Local PHY configuration resolved to SLAVE 1s MASTER Local PHY configuration resolved to MASTER LRXSTAT 13 RO Local Receiver Status Indicates the status of the local receiver See also IEEE 802 3 2008 40 5 1 1 register 10 in Table 40 3 1 Constants 0 NOK Local receiver not OK lg OK Local receiver OK RRXSTAT 12 RO Remote Receiver Status Indicates the status of the remote receiver See also IEEE 802 3 2008 40 5 1 1 register 10 in Table 40 3 1 Constants Oz NOK Remote receiver not OK 1g OK Remote receiver OK MBTFD 11 RO Link Partner Capable of Operating 1000BASE T Full Duplex See also IEEE 802 3 2008 40 5 1 1 register 10 in Table 40 3 1 Constants 0 DISABLED Link partner is not capable of operating 1000BASE T full duplex 1g ENABLED Link partner is capable of operating 1000BASE T full duplex User s Manual 102 Revision 1 0 2012 02 17 Hardware Description 2 Landi C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers Field Bits Type Description MBTHD 10 RO Link Partner Capable of Operating 1000BASE T Half Duplex See a
77. 5 1 00 1 05 V Ground Vas 0 00 0 00 0 00 V 6 3 Recommended Operating Conditions The recommended conditions for typical applications are to use nominal voltages of either 2 5 V or 3 3 V for Vp Vooh and Vppg Table 40 shows the supported operating ranges for these typical nominal voltage values However any other nominal voltage between 2 5 V and 3 3 V is also supported In order to optimize the overall power consumption of the XWAY PHY11G a supply voltage of 2 5 V is recommended The 3 3V supply is intended to support legacy systems with only 3 3 V supply lines At Vop 2 5 V it is not possible to fulfill the requirements according to the standard specified in IEEE 802 3 clause 14 3 1 2 1 1 as the peak voltage requirement in 10BASE T mode is slightly violated due to physical limitations The timing characteristics specified from this point onwards are only valid for nominal voltages of either 2 5 V or 3 3 V 6 4 Power Up Sequence It is recommended that the voltage domains are powered up simultaneously It is essential that the chip reset signal be asserted before or simultaneously with the voltage domains power up and that this signal remains asserted for as long as specified in the reset AC characteristics in Chapter 6 6 1 User s Manual 156 Revision 1 0 2012 02 17 Hardware Description gU L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Electrical Characteristics 6 5 DC Characteri
78. 6 Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EEE_ EEE_ EEE_ EEE_ EEE_ EEE_ 10GB 10GB 1000 10GB 1000 100B KR KX4 BKX T BT TX RO RO RO RO RO RO Field Bits Type Description EEE 10GBKR 6 RO Support of 10GBASE KR EEE Constants 0 DISABLED This PHY mode is not supported for EEE 1g ENABLE This PHY mode is supported for EEE EEE 10GBKX 5 RO Support of 10GBASE KX4 EEE 4 Constants Og DISABLED This PHY mode is not supported for EEE 1g ENABLE This PHY mode is supported for EEE EEE 1000BK 4 RO Support of 1000BASE KX EEE X Constants Og DISABLED This PHY mode is not supported for EEE 1g ENABLE This PHY mode is supported for EEE EEE 10GBT 3 RO Support of 10GBASE T EEE Constants 0 DISABLED This PHY mode is not supported for EEE 1g ENABLE This PHY mode is supported for EEE EEE 1000BT 2 RO Support of 1000BASE T EEE Constants Og DISABLED This PHY mode is not supported for EEE 1g ENABLE This PHY mode is supported for EEE EEE 100BTX 1 RO Support of 100BASE TX EEE Constants Og DISABLED This PHY mode is not supported for EEE 1g ENABLE This PHY mode is supported for EEE User s Manual 138 Revision 1 0 2012 02 17 Hardware Description gU L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MMD Registers EEE Auto Negotiation Link Partner Advertisement Register All of the bits in the EEE LP advertisement register are read only A write operation to the EEE LP advertisement register has n
79. 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description 3 5 5 Power Down Modes This section introduces the power down modes that are supported by the XWAY PHY11G These modes can be associated to states as shown in Figure 37 The functionality of each mode and the state transitions are discussed in detail in the subsequent sections PowerDown RESEURBOWEEDD Register 0 1121 PowerUp Register 0 1120 Timeout Activity_Detect Timeout PD_IDLE PD_FORCE Perform power savings while Perform auto negotiation Maximum possible power down only monitoring activity for according to IEEE 802 3 compliant to instantaneously connected link IEEE 802 3 22 2 4 1 5 partners Transceive Data LPI Deassert Stay in LP_Mode with IDLE REFRESH signaling according to IEEE 802 3az Figure 37 State Diagram for Power Down Mode Management 3 5 5 1 PD FORCE Mode The PD FORCE mode is entered by setting the register MDIO STD CTRL PD to logic 1 regardless of the current state of the device Active links are dropped when the PHY is leaving the DATA mode The sleep mode corresponds to power down as specified in IEEE 802 3 1 clause 22 2 4 1 5 The device still reacts to MDIO management transactions The interface clocks to the MAC are switched off No signal is transmitted on the MDI Since this mode is entered manually the device will wake neither itse
80. 802 3 2008 28 2 1 2 2 1 Constants 00000001 XBT_HDX Advertise 10BASE T half duplex 00000010 XBT_FDX Advertise 10BASE T full duplex 00000100 DBT_HDX Advertise 100BASE TX half duplex 00001000 DBT_FDX Advertise 100BASE TX full duplex 00010000 DBT4 Advertise 100BASE T4 00100000 PS_SYM Advertise symmetric pause 01000000 PS_ASYM Advertise asymmetric pause 10000000 RES Reserved for future technologies User s Manual 93 Revision 1 0 2012 02 17 Hardware Description amp Lanti C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers Field Bits Type Description SF 4 0 RW Selector Field The selector field is a five bit wide field for encoding 32 possible messages Selector field encoding definitions are shown in IEEE 802 3 2008 Annex 28A 1 Combinations not specified are reserved for future use Reserved combinations of the selector field are not to be transmitted See also IEEE 802 3 2008 28 2 1 2 1 1 Constants 000014IEEE802DOTS3 Select the IEEE 802 3 technology User s Manual Hardware Description 94 Revision 1 0 2012 02 17 E L XWAY PHY11G PEF 7071 fe ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers Auto Negotiation Link Partner Ability All of the bits in the auto negotiation link partner ability register are read only A write to the auto negotiation link partner ability register
81. ASE X specific auto negotiation according to IEEE 802 3 clause 37 1 is also supported A signal detect input is optionally available to indicate the signal status from the optics module to the XWAY PHY11G This input is used in the particular case of dual media applications for auto selection of the active interface The external circuitry and wiring connection to the optics User s Manual 37 Revision 1 0 2012 02 17 Hardware Description fer L XWAY PHY11G PEF 7071 fe ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description module is specified in Chapter 6 8 7 Accordingly Chapter 6 6 10 specifies the timing characteristics of this interface Note that the integrated SerDes is compatible with both 1000BASE X and the SGMII standard which in turn means that the differential high speed pins can operate in both modes depending on the configuration However since XWAY PHY11G integrates only one SerDes this means that only one of these interface modes can be operated at any one time The fiber interface supports only speeds of 1000 Mbit s it is only compatible with gigabit speed MIIs 3 3 2 Auto Negotiation The XWAY PHY11G supports self contained Auto Negotiation ANEG as a startup procedure to exchange capability information with the link partner Unless ANEG is manually disabled using the MDIO STD CTRL ANEN register the XWAY PHY11G will initiate each link up using an ANEG procedure This is
82. AY PHY11G In particular this contains the defaults for the internal MDIO registers This configuration is loaded by the XWAY PHY11G directly after reset or power up if an EEPROM has been detected In order to support the sharing of a larger EEPROM device by several master devices for example if an additional microcontroller also loads its configuration from the same device the XWAY PHY11G scans the EEPROM content for a particular signature that corresponds to its configuration record The XWAY PHY11G loads this configuration record and overrides its internal defaults A detailed description of the configuration record is given in Chapter 3 4 2 3 A more sophisticated type of application is used to enhance the functionality of the XWAY PHY11G by loading embedded firmware from the external EEPROM The integrated device controller on the XWAY PHY11G is able to execute code from the external EEPROM In order to reduce the load on the 1 C interface this code is loaded into the XWAY PHY11G before execution It is possible to change the existing functionality by modifying parts of the integrated firmware as well as to extend its functionality by adding new firmware blocks Dedicated support from Lantiq is required for this type of feature The externally embedded firmware is also stored within the configuration record Further details are specified in Chapter 3 4 2 3 3 4 2 2 EEPROM Detection The XWAY PHY11G automatically detects wh
83. AY PHY11G PEF 7071 fe ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description 3 1 1 Copper Flow In the copper flow the XWAY PHY11G operates as a standard multi speed twisted pair copper PHY according to the standards defining the 10BASE T e 100BASE TX and 1000BASE T modes of operation on the MDI All the xMII supported MII interface types may be used to connect to a MAC layer device Note that the data rate of the MDI can be restricted by the MII type used For example the RMII does not support the higher rates of the 1000BASE T mode while the RTBI only supports the 1000BASE T mode Refer to Table 9 for details 3 1 2 Media Converter Flow In this type of data flow configuration the XWAY PHY11G acts as an interface between a fiber based MDI and a copper based MDI In this configuration the device does not require a MAC connection It can operate fully unmanaged meaning that no management entity must be connected to the MDIO interface The media converter flow only supports the 1000 Mbit s data rate converting the flow of data between 1000BASE X and 1000BASE T The XWAY PHY11G uses auto negotiation to resolve the proper conversion configuration The copper MDI is forced into the correct speed mode by restricting the auto negotiation feature to using only 1000BASE T in full duplex and half duplex mode User s Manual 31 Revision 1 0 2012 02 17 Hardware Description uf Leona XWAY PHY11G
84. Address Bit Mapping in 16 Bit Addressing Mode s eel 53 Table 24 Definition of MDIO Frame Components o 58 Table 25 MDIO Indirect MMD Device Address Overview 00 00 eee eee 59 Table 26 Direct LED FUNCIONS cete det tem ea E OO a Ve ee EU RR qe 64 Table 27 Complex LED Functions 64 Table 28 Switching Regulator External Component Values 2000 cece eee eee 66 Table 29 Programming Sequence for the Wake On LAN Functionality 2 20000 76 Table 30 JTAG TAP Controller Op Codes 0 0000 cece eee ee 79 Table 31 JTAG Boundary Scan ID Loco 79 Table 32 Registers Address Space o 84 Table 33 Registers OVerviGW cc4 dce000 paid udi bed qpdend o Res Re REE Ree ee 84 Table 34 Registers OvervigW sasssa atiras ra men ak ox Ru RE ROMA ea ne RE RUD Ope E Ren ER RR RR 132 Table 35 Similar Registers 44 sh als er AA WE EGG ER Yee ed 145 Table 36 Similar Registers i2 bee x dta ha epg ar ada Ra RR bead Y Y E des Qa eS 147 Table 37 Similar Reglsters estaca Ape pe agb E nd dha EE ob E REY eto ades d gd 152 Table 38 Similar Registers iu sva ead aw atk a RR KL cR CU ae OE Gale Yos n Rua Ge E oe ae 153 Table 39 Absolute Limit Ratings l leise II 3 er 155 Table 40 Operating Range o oooocccocncon eh Rh hh hs 156 Table 41 DC Characteristics of the GPIO Interfaces VDDP 2 5 V 0 ee 157 Table42 DC Characteristics of the GPIO Interfaces VDDP 3 3 V 00
85. D No EEPROM is has been detected 1g DETECTED An EEPROM is has been detected User s Manual Hardware Description 117 Revision 1 0 2012 02 17 2 Landi C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers Field Bits Type Description SIZE 11 8 RW EEPROM Size Defines the size of the connected EEPROM After reset this register contains the size extracted from the soft pin strapping Constants 0000 SIZE1K SIZE1K 0001 SIZE2K SIZE2K 0010 SIZE4K SIZE4K 0011 SIZE8K SIZE8K 0100 SIZE16K SIZE16K 0101 SIZE32K SIZE32K 0110 SIZE64K SIZE64K 0111 SIZE128K SIZE128K 1000 SIZE256K SIZE256K 1001 SIZE512K SIZE512K 1010 SIZE1024K SIZE1024K ADRMODE RW EEPROM Addressing Mode Defines the device addressing mode of the connected EEPROM After reset this register contains the size extracted from the soft pin strapping Constants Og MODE11 11 bit addressing mode 1g MODE16 16 bit addressing mode DADR 6 4 RW EEPROM Device Address Defines the device address of the connected EEPROM After reset this register contains the size extracted from the soft pin strapping SPEED 3 2 RW EEPROM Speed Defines the device address of the connected EEPROM After reset this register contains the size extracted from the soft pin strapping Constants 00 FRQ 100KHZ EEPROM is accessed at 100 kHz 01 FRQ 400KHZ EEPROM is acces
86. D Registers MDIO Manageable Device Registers These registers are indirectly addressable using the MDIO registers MMDCTRL Page 105 and MMDDATA Page 106 Most of these registers are standardized registers which must be mapped to these MMD addresses for compliant operation MMD Registers Table 34 Registers Overview Register Short Name __ Register Long Name Offset Address Page Number EEE EEE CTRL1 EEE Control Register 1 03 0000 134 EEE STAT1 EEE Status Register 1 03 0001 135 EEE CAP EEE Capability Register 03 00144 136 EEE_WAKERR EEE Wake Time Fault Count Register 03 0016 137 ANEG EEE_AN_ADV EEE Auto Negotiation Advertisement Register 07 003C 138 EEE AN LPADV EEE Auto Negotiation Link Partner Advertisement 07 003D 139 Register EEPROM EEPROM EEPROM Content Memory 1E 0000 140 INTERNAL LEDCH LED Configuration 1F 01E0 141 LEDCL LED Configuration 1F 01E1 143 LEDOH Configuration for LED Pin 0 1F 01E2 144 LEDOL Configuration for LED Pin 0 1F 01E3 146 LED1H Configuration for LED Pin 1 1F 01E4 144 LED1L Configuration for LED Pin 1 1F 01E5 146 LED2H Configuration for LED Pin 2 1F 01E6 144 LED2L Configuration for LED Pin 2 1F 01E7 146 EEE RXERR LINK FA High Byte of the EEE Link Fail Counter 1F 01EA 148 IL_H EEE RXERR LINK FA Low Byte of the EEE Link Fail Counter 1F 01EB 148 IL L MIIZCTRL MII2 Control 1F 01EC 149 LEG LP
87. DC DC supply pin Ipc pcipc 400 0 400 0 mA ESD robustness HBM 1 5 KQ 100 pF Vesp HBM 2000 0 V According to EIA JESD22 A114 B ESD robustness Vesb com 500 0 V According to ESD association standard DS5 3 1 1999 1 That is any pin which is not a supply pin of one of the domains Von Vpop Vppc User s Manual 155 Revision 1 0 2012 02 17 Hardware Description fer L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Electrical Characteristics 6 2 Operating Range Table 40 defines the limit values of voltages and temperature that can be applied while still guaranteeing proper operation of the XWAY PHY11G As can be seen in the table the device only needs one power supply which can be arbitrarily chosen between 2 5 V and 3 3 V When the optional DC DC converter is not used an additional low voltage supply of 1 0 V is required Table 40 Operating Range Parameter Symbol Values Unit Note Min Typ Max Test Condition Ambient temperature under bias TA 40 0 85 0 C Pad supply voltage Vbpp 3 14 3 30 3 47 V 3 3 V supply 2 37 2 50 2 62 V 2 5 V supply High supply voltage VooH 3 14 3 30 3 47 V 3 3 V supply 2 37 2 50 2 62 V 2 5 V supply DC DC supply voltage VbpR 3 14 3 30 3 47 V 3 3 V supply 2 37 2 50 2 62 V 2 5 V supply Low supply voltage Von 0 95 1 00 1 05 V Core supply voltage Vbpc 0 9
88. Ethernet Packet Tail CRC xway_phy11g ip_magicpacket vsd Figure 36 The Magic Packet Format User s Manual 75 Revision 1 0 2012 02 17 Hardware Description ET LANTI C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description Table29 Programming Sequence for the Wake On LAN Functionality Step Register Access Remark 1 MDIO MMD WOLADO AA Program the first MAC address byte 2 MDIO MMD WOLAD1 BB Program the second MAC address byte 3 MDIO MMD WOLAD2 CC Program the third MAC address byte 4 MDIO MMD WOLAD3 DD Program the fourth MAC address byte 5 MDIO MMD WOLAD4 EE Program the fifth MAC address byte 6 MDIO MMD WOLAD5 FF Program the sixth MAC address byte 7 MDIO MMD WOLPWO 00 Program the first SecureON password byte 8 MDIO MMD WOLPW1 11 Program the second SecureON password byte 9 MDIO MMD WOLPW2 22 Program the third SecureON password byte 10 MDIO MMD WOLPW3 33 Program the fourth SecureON password byte 11 MDIO MMD WOLPW4 44 Program the fifth SecureON password byte 12 MDIO MMD WOLPW5 55 Program the sixth SecureON password byte 13 MDIO PHY IMASK WOL 1g Enable the Wake On LAN interrupt mask 14 MDIO MMD WOLCTRL WOL EN 1 Enable Wake On LAN functionality User s Manual Hardware Description 76 Revision 1 0 2012 02 17 fer L XWAY PHY11G PEF
89. G meets the isolation requirements specified in 1 clause 14 7 2 4 and clause 40 6 1 1 as well as in 4 clause 8 4 User s Manual 172 Revision 1 0 2012 02 17 Hardware Description gU L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Electrical Characteristics 6 8 External Circuitry This chapter specifies the component characteristics of the external circuitry connected to the XWAY PHY11G 6 8 1 Crystal In case no external reference clock as described in Chapter 6 6 3 is available the device must generate its own self contained clock using an external crystal parallel resonator connected to XTAL1 and XTAL2 The internal crystal oscillator internally generates a reference clock which conforms to the specification defined in Chapter 6 6 3 as long as the component specification outlined in this section is satisfied In order to specify the crystal an equivalent circuit is shown in Figure 54 This circuit is referred to by the component characteristics specification given in Table 62 Figure 54 Equivalent Circuit for Crystal Specification Table 62 Electrical Characteristics for Supported Crystals Parameter Symbol Values Unit Note Test Condition Min Typ Max Main resonant frequency Tres 25 MHz Total frequency stability 50 0 50 ppm Temperature range T 40 85 C Series capacitance C 15 30 fF ESR R4 30 7100 Shunt capacit
90. GMII Transmit Data Bit 3 CMOS This pin carries bit 3 of the TXD 3 0 RGMII transmit data vector It PD is synchronous with TXC RMII Not Used Should be connected to GND or driven with logic zero TXD38 RTBI Transmit Data Bits 3 and 8 This pin carries bits 3 and 8 of the double data rate RTBI transmit data vector It is synchronous with TBI TXCKL The bits are subject to the rising and falling edges respectively of the TBI TXCLK signal SCN O HD SGMII Serial Clock Negative Pin This is the negative signal of the differential clock pair of the SGMII SerDes interface In conjunction with SCP it provides a 625 MHz differential clock that is source synchronous with SOP SON If a MAC with CDR is used this pin can be left open The pin must be AC coupled For more details see Chapter 6 8 6 SIGDET LVTTL 1000BASE X Signal Detect CMOS The signal detect pin is used in dual media applications to detect whether a valid signal is present from the FO module The polarity of this pin can be programmed via the SDETP field in the Physical Layer Control 2 register User s Manual Hardware Description 22 Revision 1 0 2012 02 17 Table 5 ET Lanti C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s External Signals Media Independent Interface Pins cont d Pin No Name Pin Type Buffer Type Function 11 TXD2 TXD27 LVTTL CMOS PD RGMII Transmit D
91. I Transmit Data Bits 4 and 9 This pin carries bits 4 and 9 of the double data rate RTBI transmit data vector It is synchronous with TBI TXCKL The bits are subject to the rising and falling edges respectively of TBI TXCLK HD SGMII Serial Input Negative Pin This is the negative signal of the differential input transmit pair of the SGMII SerDes interface In conjunction with SIP it samples a 1 25 Gbit s differential data signal Due to the integrated CDR no external MAC source synchronous clock is required This pin must be AC coupled For more details see Chapter 6 8 6 1000BASE X Receive Data negative pin This is the negative signal of the differential receive input pair of the 1000BASE X SerDes interface In conjunction with RDP it constitutes a 1 25 Gbit s differential data signal driven by the fiber optic module This pin must be AC coupled For more details see Chapter 6 8 7 User s Manual Hardware Description 24 Revision 1 0 2012 02 17 Er Lanti C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s External Signals Table 5 Media Independent Interface Pins cont d Pin No Name Pin Buffer Function Type Type 48 RX_CTL O LVTTL RGMII Receive Control CMOS This is the receive control signal driven by the PHY and which is synchronous with RXC The signal encodes the RX DV and RX ER sig
92. I 15 0 RO Organizationally Unique Identifier Bits 3 18 This register holds the bits 3 18 of the OUI code for Lantiq Deutschland GmbH which is specified to be OUI AC 9A 96 See also IEEE 802 3 2008 22 2 4 3 1 1 PHY Identifier 2 This is the second of 2 PHY identification registers containing the LSBs of a 32 bit code This code specifies the Organizationally Unique Identifier OUI and the vendor s model and revision number See also IEEE 802 3 2008 22 2 4 3 1 1 PHYID2 Offset Reset Value PHY Identifier 2 03 A401 15 14 13 12 11 10 9 8 7 2 1 0 OUI LDN LDRN RO RO RO Field Bits Type Description OUI 15 10 RO Organizationally Unique Identifier Bits 19 24 This register holds the bits 19 24 of the OUI code for Lantiq Deutschland GmbH which is specified to be OUIZAC 9A 96 LDN 9 4 RO Lantiq Device Number Specifies the device number in order to distinguish between several Lantiq products LDRN 3 0 RO Lantiq Device Revision Number Specifies the device revision number in order to distinguish between several versions of this device User s Manual Hardware Description 92 Revision 1 0 2012 02 17 gU L XWAY PHY11G PEF 7071 fe ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers Auto Negotiation Advertisement This register contains the advertised abilities of the PHY during auto negotiation See also IEEE 802 3 2008 28 2 4 1 3 1 as wel
93. I CFGO Legacy LPI Configuration Register 0 1F 01ED 150 LEG_LPI_CFG1 Legacy LPI Configuration Register 1 1F 01EE 150 WOLCTRL Wake On LAN Control Register 1F 0781 151 WOLADO Wake On LAN Address Byte 0 1F 0783 152 WOLAD1 Wake On LAN Address Byte 1 1F 0784 152 WOLAD2 Wake On LAN Address Byte 2 1F 0785 152 WOLAD3 Wake On LAN Address Byte 3 1F 0786 152 WOLAD4 Wake On LAN Address Byte 4 1F 0787 152 User s Manual Hardware Description 132 Revision 1 0 2012 02 17 fer L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MMD Registers Table 34 Registers Overview cont d Register Short Name Register Long Name Offset Address Page Number WOLAD5 Wake On LAN Address Byte 5 1F 0788 152 WOLPWO Wake On LAN SecureON Password Byte 0 1F 0789 153 WOLPW1 Wake On LAN SecureON Password Byte 1 1F 078A 153 WOLPW2 Wake On LAN SecureON Password Byte 2 1F 078B 153 WOLPW3 Wake On LAN SecureON Password Byte 3 1F 078C 153 WOLPW4 Wake On LAN SecureON Password Byte 4 1F 078D 153 WOLPW5 Wake On LAN SecureON Password Byte 5 1F 078E 153 LEG_LPI_CFG2 Legacy LPI Configuration Register 2 1F 0EB5 154 LEG_LPI_CFG3 Legacy LPI Configuration Register 3 1F 0EB7 154 The registers are addressed wordwise Unused registers bits are written with zeros their values are ignored when read These unused bits are marked by in the following registe
94. I in bytes Constants 01000000 DEFAULT MII IDLE time is 64 bytes User s Manual 154 Revision 1 0 2012 02 17 Hardware Description fer L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Electrical Characteristics 6 Electrical Characteristics This chapter specifies the electrical characteristics of the the XWAY PHY11G 6 1 Absolute Maximum Ratings Table 39 shows the absolute maximum ratings for the XWAY PHY11G Attention Stresses above the maximum values listed in this table may cause permanent damage to the device Exposure to absolute maximum rating conditions for extended periods may affect device reliability Attention Maximum ratings are absolute ratings exceeding only one of these values may cause irreversible damage to the device Table 39 Absolute Limit Ratings Parameter Symbol Values Unit Note Min Typ Max Test Condition Storage temperature limits Tste 55 0 125 0 C DC voltage limits on pad supply pins Vobpp 0 5 4 0 V DC voltage limits on high supply pins VooH 0 5 40V DC voltage limits on DC DC supply pins Vbpr 0 5 40V DC voltage limits on low supply pins VopL 0 5 1 6 V DC voltage limits on core supply pins Vbpc 0 5 1 6 V DC voltage limits on any digital pin Voc 0 5 Vbpp 0 5 V DC current limits on any digital input pin Ipc digita 10 0 10 0 mA DC current limits on
95. Link Partner Ability 05 95 AN EXP Auto Negotiation Expansion 06 97 AN NPTX Auto Negotiation Next Page Transmit Register 07 98 AN NPRX Auto Negotiation Link Partner Received Next 084 99 Page Register GCTRL Gigabit Control Register 09 100 GSTAT Gigabit Status Register OA 102 RES11 Reserved OB 104 RES12 Reserved OCh 104 MMDCTRL MMD Access Control Register OD 105 MMDDATA MMD Access Data Register OE 106 XSTAT Extended Status Register OF 107 PHY PHYPERF Physical Layer Performance Status 10 108 PHYSTAT1 Physical Layer Status 1 114 109 PHYSTAT2 Physical Layer Status 2 124 111 PHYCTL1 Physical Layer Control 1 13 112 PHYCTL2 Physical Layer Control 2 14 114 ERRCNT Error Counter 15 116 EECTRL EEPROM Control Register 16 117 MIICTRL Media Independent Interface Control 174 119 MIISTAT Media Independent Interface Status 18 121 IMASK Interrupt Mask Register 19 122 ISTAT Interrupt Status Register 1A4 124 LED LED Control Register 1B 126 User s Manual Hardware Description 84 Revision 1 0 2012 02 17 6 Lanti XWAY PHY11G PEF 7071 C Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Table 33 Registers Overview cont d MDIO Registers Register Short Name Register Long Name Offset Address Page Number TPGCTRL Test Packet Generator Control 1C 128 TPGDATA Test Packet Generator Data 1D 130 FWV Firmware Version Register 1E 131 RES1F Reserved 1Fy 131 The registers are addre
96. NE 1110 1 1 00 FF Receive data error ZERO ONE 3 2 4 Serial Gigabit Media Independent Interface SGMII The Serial Gigabit Media Independent Interface SGMII implements a MAC interface that can be used for all supported speeds namely 10 Mbit s 100 Mbit s and 1000 Mbit s This interface is implemented according to the SGMII 13 specification The mapping of the standardized signals to the device pins is shown in Table 4 Note that the integrated SGMII uses Clock and Data Recovery CDR to extract the TXCLK clock from the TX data This significantly reduces cost and power The RXCLK is driven as specified by the standard but can be switched off via MDIO to reduce power in case the MAC also supports CDR The AC characteristics of the SGMII are described in Chapter 6 6 9 Supported test loops Chapter 3 6 3 can be activated at any time The external circuitry required to connect the XWAY PHY11G properly via SGMII is described in Chapter 6 8 6 3 2 5 Reduced Ten Bit Interface RTBI The Reduced Ten Bit Interface RTBI implements a MAC interface that can be used solely for speeds of 1000 Mbit s This interface is implemented according to the RGMIIv1 2 9 and RGMIIv2 0 10 specifications and is therefore referred to as an RTBI ID interface The mapping of the standardized signals to the device pins is shown in Table 4 The RTBI interface is simply a reduced version of the TBI interface In order to provide an RTBI to copper flow a Phy
97. Note that this register is subject to default reset values which depend on the soft pin strappings Constants 000 SKEW_ONO 0 0 ns timing skew 001 SKEW_0N5 0 5 ns timing skew 010 SKEW 1NO 1 0 ns timing skew 011 SKEW_1N5 1 5 ns timing skew 100 SKEW_2N0 2 0 ns timing skew 101 SKEW_2N5 2 5 ns timing skew 110 SKEW_3N0 3 0 ns timing skew 111 SKEW_3N5 3 5 ns timing skew User s Manual Hardware Description 149 Revision 1 0 2012 02 17 ew Lantiq XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MMD Registers Legacy LPI Configuration Register 0 Legacy LPI Configuration Register 0 LEG LPI CFGO Offset Reset Value Legacy LPI Configuration Register 0 1F 01ED 0020 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HOLDOFF 100BT RW Field Bits Type Description HOLDOFF 10 7 0 RW Data Hold Off Time 100BASE T OBT Defines the time between releasing the LPI request on the MII until the first data is transmitted via MII for the 100BASE T mode The time is calculated as HOLDOFF 100BT 1 x 16 x 40 ns Constants 00100000 DEFAULT 21 12 us Legacy LPI Configuration Register 1 Legacy LPI Configuration Register 1 LEG LPI CFG1 Offset Reset Value Legacy LPI Configuration Register 1 1F 01EE 0080 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HOLDOFF 1000BT RW Field Bits Type Description HOLDOFF 10 7 0 RW Data Hold Off Time 1000BASE T 00BT Define
98. ORA ache Supe d ere ERO 78 3 5 5 4 DATA MOd6G enirbREWershbeeci4eh Idee quor Reid Re m ga dud hee dae 78 3 5 5 5 EEE Mode UIDES 78 3 6 Testing Functions ana E Kaa E E VA ee eee eee ee 79 3 6 1 JTAG MONICE s EET 79 3 6 2 Payload Data TestsS eosa oia iia ida E Rer eed prc iae rm aped de ede 80 3 6 2 1 Test Packet Generator TPG 0 0 cc eee ae 80 3 6 2 2 Error Counters 22 cs ole a dor ea ee Rx n Ron A ee Pad 80 3 6 3 TeSt EOGODS ica dt a Ei Rls Sea E ROSE er C Rb DE EU Weve arte e Re UE Ae alee a aad aan E EE 81 3 6 3 1 Near End TestLoops 0 00 ccc cece eee teens 81 3 6 3 1 1 MAC Interface Test Loop iaa e eee E 81 3 6 3 1 2 MDI Test loop sc xd coed ceive ee tad sae a ead Sead a Keke Pe ae wana es 81 3 6 3 1 3 Echo Jest Loop e sii E EUER RARE Ra eed a m RA 82 3 6 3 2 Far End Test Loop o o ooo rrr 82 4 MDIO Registers iss scu LEVA aa LE ua aea Ru VAD a eae dee 84 4 1 STD Standard Management Registers ooooocccoccco rn 86 4 2 PHY PHY Specific Management Registers liie 108 User s Manual 5 Revision 1 0 2012 02 17 Hardware Description gU L XWAY PHY11G PEF 7071 d A YT IC Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Table of Contents 5 MMD Registers 2 2 iilo ela bela Pid saa REA A a Rad a rad eed 132 5 1 EEE Standard EEE Registers for MMD 0x03 0 0 eee eh 134 5 2 ANEG Standard Auto Negotiation Registers for MMD 0x07
99. PALLADIUM of Cadence Design Systems Inc VxWorks WIND RIVER of WIND RIVER SYSTEMS Last Trademarks Update 2012 01 04 User s Manual 3 Revision 1 0 2012 02 17 Hardware Description gU L XWAY PHY11G PEF 7071 ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Table of Contents Table of Contents Table of Contents 2 00 cc eee 4 List of Fig ureS 3 2240 nc innuere Ar reu teer Roe Re ae Adda od me ada 8 Listof Tables soos rie ewe gee ed beeen ie peda ND ERE ae alee 10 1 INTEOUCHION P 12 1 1 About XWAY PHY11G 0 hh rrr 12 1 2 eU C 13 1 2 1 Lode SymDO mec 13 1 2 2 Features ped A A RN Axe EA EA ERRARE AS 14 1 2 3 Typical Applications naana aaua 15 1 2 3 1 Copper Application cem ed Rep A Re aa a Le Fed eed Ro 15 1 2 3 2 Media Converter Application llli 15 1 2 3 3 Gigabit Interface Converter GBIC Application llli 15 1 2 4 Terminology and Nomenclature oooococccco sewa EEO A E a a a 16 2 External Signals eee Ru HER EAA aoe EEA eae AAA S 17 2 1 Pin Diagram rsr Ay A AA AS A 17 2 2 Pin Description o 18 2 2 1 Piri Id ntifications ilk esa D Re ee ee Re Rem ae RR Nr Rom e Vus ee E a 18 2 2 2 Genra PINE cir aetna Skeet tees eek RAP anes NE ata Ea 19 2 2 3 Media Dependent Interface MDI Pins 0 0 0 cette ee 20 2 2 4 Media Independent Interface MII Pins 00 eee 21 2 2 5 Control Interface PINS 22 sinl Mee Vide
100. PHY11G drives logic zero in this mode User s Manual Hardware Description 25 Revision 1 0 2012 02 17 Er Lanti C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s External Signals Table 5 Media Independent Interface Pins cont d Pin No Name Pin Type Buffer Type Function 4 RXD1 O RXD1 RXD16 LVTTL CMOS RGMII Receive Data Bit 1 This pin carries bit 1 of the RXD 3 0 RGMII receive data vector It is synchronous with RXC RMII Receive Data Bit 1 This pin carries bit 1 of the RXD 1 0 RMII receive data vector It is synchronous with REFCLK RTBI Receive Data Bit 1 and 6 This pin carries bit 1 and 6 of the double data rate RTBI receive data vector It is synchronous with RXC The bits are subject to the rising and falling edges respectively of RXC SGMII Not Used The XWAY PHY11G drives logic zero in this mode 5 RXDO RXDO RXDO5 LVTTL CMOS RGMII Receive Data Bit 0 This pin carries bit O of the RXD 3 0 RGMII receive data vector It is synchronous with RXC RMII Receive Data Bit 0 This pin carries bit O of the RXD 1 0 RMII receive data vector It is synchronous with REFCLK RTBI Receive Data Bit 0 and 5 This pin carries bit O and 5 of the double data rate RTBI receive data vector It is synchronous with RXC The bits are subject to the rising and falling edges respe
101. PIBN p TPICP TPICN 0 00 1 TPIDP TPIDN I i R cass LA Figure 31 Generic Schematic of the PoE PD Application As shown in the diagram additional external circuitry is required to extract power from the twisted pair This includes a PD circuit and a DC DC converter together with various external components that are usually not integrated The PD and DC DC devices could be integrated on one IC According to IEEE 802 3 clause 33 1 there are two alternative methods for supplying a PD The first involves supplying power via the common mode of the pairs 1 2 and 3 6 whereas the second involves the pairs 4 5 and 6 7 The PD is required to accept power from both alternatives but only one in parallel The polarity of the power injection is not specified Accordingly each PD must have a diode bridge rectifier to extract the power from both twisted pair combinations alternatively but independent of the driver polarity In turn the PD must signal to the PSE which type of power is required as several power classes are defined More details can be found in IEEE 802 3 clause 33 1 This signaling is done by means of a resistive value which is sensed by the PSE Each PD IC provides a pin to which this classificat
102. POLD RW Transmit Polarity Inversion Status on Port D Constants Oz NORMAL Polarity normal 1g INVERTED Polarity inversion POLC RW Transmit Polarity Inversion Status on Port C Constants 0s NORMAL Polarity normal 1g INVERTED Polarity inversion POLB RW Transmit Polarity Inversion Control on Port B Constants 03 NORMAL Polarity normal 1 INVERTED Polarity inversion User s Manual Hardware Description 112 Revision 1 0 2012 02 17 iz Lanti C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers Field Bits Type Description POLA RW Transmit Polarity Inversion Control on Port A Constants 0 NORMAL Polarity normal 1g INVERTED Polarity inversion MDICD RW Mapping of MDI Ports C and D Constants 0s MDI Normal MDI mode 1g MDIX Crossover MDI X mode MDIAB RW Mapping of MDI Ports A and B Constants 0s MDI Normal MDI mode 1g MDIX Crossover MDI X mode TXEEE10 RW Transmit Energy Efficient Ethernet 10BASE Te Amplitude This register bit allows enabling of the 10BASE Te energy efficient mode transmitting only with a 1 75 V nominal amplitude Constants Oz DISABLED Transmit the 10BASE T amplitude that is 2 3 V 1g ENABLED Transmit the 10BASE Te amplitude that is 1 75 V AMDIX RW PHY Performs Auto MDI MDI X or Uses Manual MDI MDI X Constants Oz MANUAL PHY uses m
103. RW Field Bits Type Description RESH 15 12 RO Reserved Write as zero ignored on read LEDSEN 11 RW Enable the integrated function of LED3 Write a logic O to this bit to disable the pre configured integrated function for this LED The LED remains off unless directly accessed via LED3DA Constants 0 DISABLE Disables the integrated LED function 1 ENABLE Enables the integrated LED function LED2EN 10 RW Enable the integrated function of LED2 Write a logic 0 to this bit to disable the pre configured integrated function for this LED The LED remains off unless directly accessed via LED2DA Constants 0 DISABLE Disables the integrated LED function 1g ENABLE Enables the integrated LED function LED1EN 9 RW Enable the Integrated Function of LED1 Write a logic O to this bit to disable the pre configured integrated function for this LED The LED remains off unless directly accessed via LED1DA Constants Og DISABLE Disables the integrated LED function 1g ENABLE Enables the integrated LED function LEDOEN 8 RW Enable the Integrated Function of LEDO Write a logic O to this bit to disable the pre configured integrated function for this LED The LED remains off unless directly accessed via LEDODA Constants Oz DISABLE Disables the integrated LED function 1g ENABLE Enables the integrated LED function RESL 7 4 RO Reserved Write as zero ignored on read User s Manual 126 Revision 1 0 2012 02 17 Hardware Description
104. Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description DUMMY WRITE TO ADDR READ INSTR INSTR DADR 7 1 ADR 7 0 DADR 7 1 DATA 7 0 ADR 10 8 Figure 15 Timing Diagram for a Random Address Single Byte Read A single byte random read as depicted in Figure 15 can easily be extended to a burst read Figure 16 shows the supported burst read frame structure Note that the initialization of a burst read access is the same as for a single byte read Therefore the figure only shows the protocol sequence starting from the read instruction Subsequent bytes are read from incrementing address locations for as long as the XWAY PHY11G keeps acknowledging the read bytes driven by the EEPROM The burst read access stops when the XWAY PHY11G does not acknowledge a read byte and instead issues the stop bit The XWAY PHY11G uses the burst read operation only for the external firmware load feature Normal configuration EEPROM access operations are done using single byte read write operations INSTR DADR 7 1 DATA n 7 0 DATA n 1 7 0 DATA n x 7 0 ff f Figure 16 Timing Diagram for a Burst Read 3 4 2 4 2 Frame Formats in 16 Bit Addressing Mode This addressing mode is used for the larger available EEPROM devices These devices are usually available in sizes ranging from 32 kb up to 512 kb Since the EEPROM devices are organized in 8 bit words
105. TAT Offset Reset Value Interrupt Status Register 1A 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WOL MSRENPRX NPTX ANE ANC RESH RESL ADSC jiu in DXMC LSPC LSTC ROLH ROLH ROLH ROLH ROLH ROLH ROLH ROLH ROLH ROLH ROLH ROLH ROLH ROLH Field Bits Type Description WOL 15 ROLH Wake On LAN Interrupt Status When active and masked in IMASK the MDINT is activated upon detection of a valid Wake On LAN event Constants Og INACTIVE Interrupt is masked out 1g ACTIVE Interrupt is activated MSRE 14 ROLH Master Slave Resolution Error Interrupt Status When active and masked in IMASK the MDINT is activated upon detection of a master slave resolution error during a 1000BASE T auto negotiation Constants Og INACTIVE Interrupt is masked out 1g ACTIVE Interrupt is activated NPRX 13 ROLH Next Page Received Interrupt Status When active and masked in IMASK the MDINT is activated upon reception of a next page in STD AN_NPRX Constants Og INACTIVE Interrupt is masked out 1 ACTIVE Interrupt is activated NPTX 12 ROLH Next Page Transmitted Interrupt Status When active and masked in IMASK the MDINT is activated upon transmission of the currently stored next page in STD AN_NPTX Constants Og INACTIVE Interrupt is masked out 1g ACTIVE Interrupt is activated ANE 11 ROLH Auto Negotiation Error Interrupt Status When active and masked in IMASK the MDINT is activated upon detection of an
106. TIVE Interrupt is masked out 1g X ACTIVE Interrupt is activated DXMC ROLH Duplex Mode Change Interrupt Status When active and masked in IMASK the MDINT is activated upon detection of a full or half duplex change Constants Og INACTIVE Interrupt is masked out 1g ACTIVE Interrupt is activated LSPC ROLH Link Speed Change Interrupt Status When active and masked in IMASK the MDINT is activated upon detection of link speed change Constants Og INACTIVE Interrupt is masked out 1g ACTIVE Interrupt is activated LSTC ROLH Link State Change Interrupt Status When active and masked in IMASK the MDINT is activated upon detection of link status change Constants Og INACTIVE Interrupt is masked out 1 ACTIVE Interrupt is activated User s Manual Hardware Description 125 Revision 1 0 2012 02 17 gU L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers LED Control Register This register contains control bits to allow for direct access to the LEDs A directly controlled LED must disable the integrated LED function as specified by the more sophisticated LED control registers in page LED LED Offset Reset Value LED Control Register 1B OFOO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LED3 LED2 LED1 LEDO LED3 LED2 LED1 LEDO ee EN EN EN EN ids DA DA DA DA RO RW RW RW RW RO RW RW RW
107. This pin carries bits 1and 6 of the double data rate RTBI transmit data vector It is synchronous with TBI TXCKL The bits are subject to the rising and falling edges respectively of TBI TXCLK SON TDN HD SGMII Serial Output Negative Pin This is the negative signal of the differential output receive pair of the SGMII SerDes interface In conjunction with SOP it provides a 1 25 Gbit s differential data signal that is source synchronous with the differential 625 MHz clock SCP SCN This pin must be AC coupled For more details see Chapter 6 8 6 1000BASE X Transmit Data Negative Pin This is the negative signal of the differential transmit output pair of the 1000BASE X SerDes interface In conjunction with TDP it provides a 1 25 Gbit s differential data signal to the fiber optic module This pin must be AC coupled For more details see Chapter 6 8 7 User s Manual Hardware Description 23 Revision 1 0 2012 02 17 Table 5 Er Lanti C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s External Signals Media Independent Interface Pins cont d Pin No Name Pin Type Buffer Type Function 14 TXDO TXDO TXD05 SIP RDP LVTTL CMOS PD RGMII Transmit Data Bit 0 This pin carries bit O of the TXD 3 0 RGMII transmit data vector It is synchronous with TXC RMII Transmit Data Bit 0 This pin carries
108. WAY PHY11G The XWAY PHY11G is an ultra low power multi mode Gigabit Ethernet GbE PHY IC supporting speeds of 10 100 and 1000 Mbit s in full duplex or half duplex mode It can be used in various data flows based on twisted pair and fiber optic communication links The main application is the copper mode where Media Independent Interface MII data is converted to a Media Dependent Interface MDI based on the 10BASE T e 100BASE TX and 1000BASE T Ethernet standards according to 1 The XWAY PHY11G supports a number of features for convenience and reliability including auto negotiation Chapter 3 3 2 auto MDIX auto downspeed Chapter 3 3 3 and cable wiring fault correction In addition the integrated cable diagnostics mode the test packet generator and the various test loops can be used for analysis and debugging of the target system The XWAY PHY11G includes an integrated serializer deserializer SerDes that can be used to operate a fiber link in conjunction with a 1000BASE X fiber module This capability enables media converter data flow applications The MII pins of the XWAY PHY11G can be re assigned to form one of several standard MII interfaces such as RMII RGMII RTBI and SGMII In RGMII mode the integrated delay function for the TX and RX clock simplifies PCB design In SGMII mode the PHY does not require a receive clock and instead uses the integrated Clock and Data Recovery CDR Configuration management of t
109. X 0 FLOW 5 4 RW Data Flow Configuration This register field controls the data flow of the Ethernet frames in the PHY The MAC interface type is selected by MODE Constants 00 COPPER MAC interface to twisted pair 11 CONVERTER Media converter fiber to twisted pair MODE 3 0 RW MII Interface Mode This register field controls the operation of the MII interface depending on the FLOW configuration Constants FLOW COPPER 0000 RGMII RGMII mode 0001 SGMII SGMII mode 0010 RMII RMII mode that is link speed is forced to 10 100 Mbit s only 0011 RTBI RTBI mode that is link speed is forced to 1000 Mbit s only 0100 GMII G MII mode that is MII in 10 100 Mbit s and GMII in 1000 Mbit s speed modes 0101 TBI TBI mode that is link speed is forced to 1000 Mbit s only 01105SGMIINC SGMII mode without serial clock 1111 TEST Test mode for SGMII FLOW CONVERTER 0000 CONV_X2T1000 Convert 1000BASE X without ANEG to 1000BASE T Continuous signal detection is needed to start ANEG on the 1000BASE T interface 00015CONV X2T1000A Convert 1000BASE X with ANEG to 1000BASE T Successful 1000BASE X negotiation is needed to start ANEG on the 1000BASE T interface User s Manual Hardware Description 120 Revision 1 0 2012 02 17 Sd Leona XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers Media Independent Interface Status This register contains st
110. Y11G PEF 7071 ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s References References 1 2 3 IEEE 802 3 2008 Carrier sense multiple access with collision detection CSMA CD access method and physical layer specifications IEEE Computer Society December 2008 IEEE 802 3az Amendment 5 Media Access Control Parameters Physical Layers and Management Parameters for Energy Efficient Ethernet September 2010 IEEE 802 3at Amendment 3 Data Terminal Equipment DTE Power via the Media Dependent Interface MDI Enhancements October 2009 4 ANSI X3 263 1995 Fiber Distributed Data Interface FDDI Token Ring Twisted Pair Physical Layer Medium Dependent TP PMD ANSI 1995 5 ANSI TIA EIA 568 A 1995 6 ISO IEC 11801 1995 7 IEC 60950 1991 General Safety B IEEE Std 1149 1 2001 IEEE Standard Test Access Port and Boundary Scan Architecture IEEE ANSI 2001 9 Hewlett Packard Reduced Gigabit Media Independent Interface RGMII Version 1 3 12 10 2000 10 Hewlett Packard Reduced Gigabit Media Independent Interface RGMII Version 2 0 04 01 2002 11 RMII Consortium RMII Specification Rev 1 2 1997 12 SFF Committee SFF 8053 Specification for GBIC Gigabit Interface Converter Rev 5 5 September 27 2000 13 CISCO Systems Serial GMII Specification July 2001 Rev 1 7 14 AMD White Paper on Magic Packet Technology White Paper c 1998 Adv
111. Y11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Interrupt Mask Register MDIO Registers This register defines the mask for the Interrupt Status Register ISTAT Each masked interrupt is able to activate the MDINT pin to the management device The information about the interrupt source can be extracted by reading the ISTAT register A read operation on the ISTAT register simultaneously clears the interrupts deactivating MDINT IMASK Interrupt Mask Register 15 14 13 12 11 Offset Reset Value 19 0000 10 9 8 7 6 5 4 3 2 1 0 WOL MSRE NPRX NPTX ANE MDIP MDIX ANC RESH RESL X ADSC C C DXMC LSPC LSTC RW RW RW RW RW RW RO RO RW RW RW RW RW RW Field Bits Type Description WOL 15 RW Wake On LAN Event Mask When active and masked in IMASK the MDINT is activated upon detection of a valid Wake On LAN event Constants Og INACTIVE Interrupt is masked out 1g ACTIVE Interrupt is activated MSRE RW Master Slave Resolution Error Mask When active MDINT is activated upon detection of a master slave resolution error during a 1000BASE T auto negotiation Constants Og INACTIVE Interrupt is masked out 1g X ACTIVE Interrupt is activated NPRX 13 RW Next Page Received Mask When active MDINT is activated upon reception of a next page in STD AN NPRX Constants Og INACTIVE Interrupt is ma
112. Y11G including nominal frequency frequency deviation duty cycle and signal characteristics Table 51 AC Characteristics of Output Clock on CLKOUT Pin Parameter Symbol Values Unit Note Min Typ Max Test Condition Frequency at 25 MHz Fanos 25 0 MHz Frequency at 125 MHz fokt25 125 0 MHz Frequency deviation 50 0 50 0 ppm l Duty cycle 49 0 50 0 51 0 96 Rise fall times 1 0 ns 6 6 5 MDIO Interface Figure 44 shows a timing diagram of the MDIO interface for a clock cycle in the read write and turn around modes The timing measurements are annotated and their absolute values defined in Table 52 Ri len a ta i tcp Vin min Vi max tp t ts ta gt 9 3 Figure 44 Timing Diagram for the MDIO Interface Table 52 A AC Characteristics of the MDIO Interface Parameter Symbol Values Unit Note Min Typ Max Test Condition MDC high time tcu 10 0 ns Given timings are MDC low time teL 10 0 ns all subject to the MDC clock period top 40 0 ns Hid armen MDC clock frequency tcp 25 0 MHZ XWAY PHY11 MDC rise time tr 5 0 ns G MDC fall time tr 5 0 ns MDIO read delay to 0 0 10 0 ns MDIO high Ohmic Z delay tz 0 0 10 0 ns MDIO setup time ts 4 0 ns MDIO hold time ty 4 0 ns User s Manual 162
113. airs in a CAT5 or equivalent cable type pair A is connected to pair B and pair C to D This shorting of near end twisted pairs must be enabled using specialized termination circuitry Note that no additional resistors are required since the ports of the XWAY PHY11G are already inherently terminated Figure 40 shows a high level block diagram where the test loop data path is marked by the area shaded in gray This test loop can be applied to all the supported MAC interfaces described in Chapter 3 2 The test loop mode is activated by setting MDIO PHY PHYCTL1 TLOOP RJ45 The test loop is activated at the next link up User s Manual 81 Revision 1 0 2012 02 17 Hardware Description ral XWAY PHY11G PEF 7071 E CANTI Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description Figure 40 MDI connector Near End Test Loop 3 6 3 1 3 Echo Test Loop The DEC Digital Echo Canceler test loop allows for the transmit signal to be looped back via the Digital Echo Canceler DEC This loop back is similar to the functionality of the MDI test loop as described in Chapter 3 6 3 1 2 except that it does not require a special termination circuitry at the MDI connector The user of this test loop has the option to terminate each twisted pair with a 100 O resistor When executing this test the PMA trains the DEC to the echo that is inherently present because of non ideal line terminations Sin
114. al XWAY PHY11G PEF 7071 E CANTI Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Introduction Network Processor Transformer XWAY PHY11G MAC PEF 7071 10 100 1000bT PEF 7072 GBIC Switch Router Board SFP Module Figure4 XWAY PHY11G Used in 10 100 1000BASE T GBIC SFP Application 1 2 4 Terminology and Nomenclature Throughout this document the terms transmit TX and receive RX are used to specify the data and signal flow directions Unless stated otherwise the TX direction refers to the flow of data and signals from the MII to the MDI that is from the MAC interface to the transmission medium The transmission of data actually refers to the transport of data towards the next lower layer in the OSI reference model The RX direction refers to the flow of data and signals in the opposite directions Transmit TX Receive RX Figure5 Transmit and Receive Terminology Abbreviations are used throughout this document Each abbreviation is explained once at its first appearance in the text and is also included in a consolidated list of acronyms in Terminology When referring to registers the document uses the following nomenclature Address Space Sub Space Register Register Element As an example MDIO STD CTRL PD refers to the PD bit inside the CTRL register which is located inside the STD register s space of the MDIO address space see
115. also Chapter 4 Alternatively the text uses register references according to IEEE802 3 2005 These references are only applicable to the MDIO address space Such references use the format Register Number Register Bit Number As an example the reference 0 11 refers to the same MDIO STD CTRL PD bit User s Manual 16 Revision 1 0 2012 02 17 Hardware Description Ag Lantiq XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s 2 External Signals This chapter describes the external signals of the XWAY PHY11G 2 1 Pin Diagram External Signals Figure 6 shows the pin diagram of the XWAY PHY11G when taking a top view of the VQFN48 package The pins and the common ground pad EPAD are visible on the bottom side of the package The latter is illustrated using dashed lines The subsequent sections describe each of these pins in more detail XTAL2 VDDR REGO VDDC MDC MDIO SCL SDA VDDP CLKOUT MDISTE ae aN EPAD GND RX_CTL LEDO LED1 LED2 TDO TMS TCK Figure 6 Pin Diagram of the XWAY PHY11G Top View of VQFN48 Package User s Manual 17 Hardware Description Revision 1 0 2012 02 17 fer L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s External Signals 2 2 Pin Description In this section all the XWAY PHY11G pins are grouped according to their functionality and described in detail in Chapter 2 2
116. ance Co 7 pF Load capacitance 2C 33 0 pF Drive level Pave 0 1 mW 1 Refers to the sum of all effects e g general tolerances aging temperature dependency User s Manual 173 Revision 1 0 2012 02 17 Hardware Description 2s L XWAY PHY11G PEF 7071 z d A YT IC Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Electrical Characteristics 6 8 2 LED This section specifies the electrical characteristics of the LEDs which are supported Note that the requirements specified here are given to guarantee proper operation of the pin strapping Chapter 3 4 1 which shares the LED pins Nevertheless the requirements are selected to fit almost every LED available on the target market Ic mA Low Current LED 10 SS Conventional LED NNW 10 A AQ UW NSSSSSSSNS SNR 10 RA 10 SS 10 ES 10 0 1 0 2 0 3 0 V V Figure 55 Tolerance Graph for the Forward Current Versus Voltage of the Supported LEDs Note that LED devices also significantly contribute to the system power consumption A conventional LED has an operating point of Ve 2 0 V and lg 20 0 mA This results in a power consumption of 40 mW per LED Three LEDs would consume up to 120 mW which is already as high as 3096 of the maximum power consumption of the entire XWAY PHY11G device Using low current LEDs would improve this figure to 12 mW that is only 3 of the device power consumption Figure 55 shows a tole
117. ance Micro Devices User s Manual 184 Revision 1 0 2012 02 17 Hardware Description gU L XWAY PHY11G PEF 7071 fe ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Terminology Terminology A ADS Auto Downspeed ANEG Auto Negotiation ANSI American National Standards Institute B BER Bit Error Rate BW Bandwidth C CAT5 Category 5 Cabling CCR Configuration Content Record CDR Clock and Data Recovery CRC Cyclic Redundancy Check CSR Configuration Signature Record CRS Carrier Sense D DEC Digital Echo Canceler E ECM Externally Controlled Mode LED EEE Energy Efficient Ethernet EEPROM Electrically Erasable Programmable ROM EMI Electro Magnetic Interference ESD Electro Static Discharge F FO Fiber Optic G GbE Gigabit Ethernet GBIC Gigabit Interface Converter GMII Gigabit Media Independent Interface GPIO General Purpose Input Output H HBM Human Body Model HSTL High Speed Transceiver Logic HYB Hybrid I FG Internally Integrated Circuit Interface also I2C IC Integrated Circuit ICM Internally Controlled Mode LED IEEE Institute of Electrical and Electronics Engineers User s Manual 185 Revision 1 0 2012 02 17 Hardware Description gU L XWAY PHY11G PEF 7071 fe ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Terminology IPG Inter Packet Gap J JTAG Joined Test Action Group L LAN Local Area Network LED Light Emitting Diode LPI Low Power Idle LSB L
118. anual MDI MDI X lg AUTO PHY performs Auto MDI MDI X User s Manual Hardware Description 113 Revision 1 0 2012 02 17 gU L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Physical Layer Control 2 This register controls the PHY functions PHYCTL2 Offset Physical Layer Control 2 14 15 14 13 12 11 10 9 8 7 6 5 MDIO Registers Reset Value 8006 3 2 1 0 CLKS SDET STIC RESL LSADS RESH EL P KY ADCR PSCL ANPD LPI RW RO RW RW RW RO RW RW RW RW Field Bits Type Description LSADS 15 14 RW Link Speed Auto Downspeed Control Register Constants failed link ups failed link ups failed link ups Link speed auto downspeed is a functionality which allows an Ethernet link to be established even in non standard harsh cable environments 00 OFF Do not perform link speed auto downspeed 01 ADS2 Perform auto downspeed of link speed after 2 consecutive 10 ADS3 Perform auto downspeed of link speed after 3 consecutive 11 ADSA Perform auto downspeed of link speed after 4 consecutive RESH 13 11 RO Reserved Write as zero ignored on read CLKSEL 10 RW Clock Out Frequency Selection Constants Allows specification of the frequency of the clock out pin Oz CLK25M CLKOUT frequency is 25 MHz lg CLK125M CLKOUT frequency is 125 MHz SDETP 9 RW Signal Detection Polarity for the 1000BASE X PHY Constants Allows spe
119. at configuration is only performed once after hardware reset or power up A simple software reset does not restart the configuration sequence MDIO configuration and control access can only start after the configuration sequence has finished The XWAY PHY11G indicates the time at which this is possible by clearing the MDIO reset register MDIO STD CTRL RST 0p Reset or Power Up connected ye t Pin Strapping Soft Pin Strapping EEPROM context normal context Scan EEPROM for Signature and CRID Signature Found Use PHYADR CRID Config Default PHYADR CSR Field Config CCR Figure 12 Overview of the Configuration Flow User s Manual 42 Revision 1 0 2012 02 17 Hardware Description gU L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description 3 4 1 Configuration of XWAY PHY11G via Pin Strapping This section describes the configuration of the XWAY PHY11G by means of pin strapping The limited pin count of the device means that reserving enough pins to encode all the configuration bits by simply pulling these pins to Vppp or Vsg in order to encode a logic one or zero respectively is not an affordable option Instead the device supports soft pin strapping using external resistors and capacitors Using this technology an entire bit vector can be read on
120. ata Bit 2 This pin carries bit 2 of the TXD 3 0 RGMII transmit data vector It is synchronous with TXC RMII Not Used Should be connected to GND or driven with logic zero RTBI Transmit Data Bits 2 and 7 This pin carries bits 2 and 7 of the double data rate RTBI transmit data vector It is synchronous with TBI TXCKL The bits are subject to the rising and falling edges respectively of TBI TXCLK SOP TDP HD SGMII Serial Output positive pin This is the positive signal of the differential output receive pair of the SGMII SerDes interface In conjunction with SON it provides a 1 25 Gbit s differential data signal that is source synchronous with the differential 625 MHz clock SCP SCN This pin must be AC coupled For more details see Chapter 6 8 6 HD 1000BASE X Transmit Data positive pin This is the positive signal of the differential transmit output pair of the 1000BASE X SerDes interface In conjunction with TDN it provides a 1 25 Gbit s differential data signal to the fiber optic module This pin must be AC coupled For more details see Chapter 6 8 7 12 TXD1 TXD1 TXD16 LVTTL CMOS PD RGMII Transmit Data Bit 1 This pin carries bit 1 of the TXD 3 0 RGMII transmit data vector It is synchronous with TXC RMII Transmit Data Bit 1 This pin carries bit 1 of the TXD 1 0 RMII transmit data vector It is synchronous with REFCLK RTBI Transmit Data Bits 1 and 6
121. atus information of the MII interface Reset Value 0000 MIISTAT Media Independent Interface Status Offset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESH PHY PS DPX EEE SPEED RO RO RO RO RO RO Field Bits Type Description RESH 15 8 RO Reserved Write as zero ignored on read PHY T 6 RO 00 01 10g 11g Active PHY Interface Constants TP The twisted pair interface is the active PHY interface FIBER The fiber interface is the active PHY interface MII2 The second MII interface is the active PHY interface SGMII The SGMII interface is the active PHY interface PS 5 4 RO 005 015 10g 11g Resolved Pause Status for Flow Control Constants NONE No PAUSE TX Transmit PAUSE RX Receive PAUSE TXRX Both transmit and receive PAUSE DPX RO 0g 1g Duplex mode at which the MII currently operates Constants HDX Half duplex FDX Full duplex EEE RO 0s 1g Resolved Energy Efficient Ethernet Mode Constants OFF EEE is disabled after auto negotiation resolution ON EEE is enabled after auto negotiation resolution SPEED 1 0 RO 00 01g 10g 11g PHY Speed at which the MII Currently Operates Constants TEN 10 Mbit s FAST 100 Mbit s GIGA 1000 Mbit s RES Reserved for future use User s Manual Hardware Description 121 Revision 1 0 2012 02 17 ET LANTI C XWAY PH
122. auto negotiation is running 101 ABIST Complex function enabled when analog self test is running 110 CDIAG Complex function enabled when cable diagnostics are running 111 TEST Complex function enabled when test mode is running User s Manual Hardware Description 142 Revision 1 0 2012 02 17 ET LANTI C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s LED Configuration MMD Registers The register must be used to configure the complex functions of the LED behavior Complex functions are of a higher priority than direct LED functions as of registers MMD INTERNAL LEDxH L When the PHY enters a state which is defined to activate complex LED functions all LEDs are controlled according to the type of the complex function LEDCL LED Configuration 15 14 13 12 11 Offset Reset Value 1F 01E1 0067 10 9 8 7 6 5 4 3 2 1 0 SCAN CBLINK RW RW Field Bits Type Description SCAN 6 4 RW Complex SCAN Configuration This configuration defines in which state the complex SCAN should be activated The complex SCAN performs running on which turns back and forth between the first and last LED The speed is dependent on the MMD INTERNAL LEDCH FBF setting Constants 000 NONE No Function 001 LINK Complex function enabled when link is up 0105 PDOWN Complex function enabled when device is powered down 011 EEE Complex function enabled when
123. ble is only valid in the case that no EEPROM is connected to the XWAY PHY11G If a configuration EEPROM is connected the soft pin strapping device parameters are mapped to different functions as described in Table 17 Chapter 3 4 2 gives more details on EEPROM based device configuration Table 15 Mapping of Configuration Pins Bits to Device Parameters No EEPROM Connected Configuration Pin CBV 3 0 associated by resistor value according to Table 14 CBV 3 CBV 2 CBV 1 CBV 0 LEDO MDIOADR 3 MDIOADR 2 MDIOADR 1 MDIOADR O LED1 MDIOADR 4 MODE 1 MODE O FLOW LED2 CONF 1 CONF 0 ANEG 1 ANEG 0 The functions of the device parameters mapped in Table 15 are described in Table 16 Table 16 Functions of Device Parameters Controlled by Soft Pin Strapping No EEPROM Connected Device Parameter Function MDIOADR 4 0 Sets the MDIO PHY address to which the XWAY PHY11G responds during MDIO transactions FLOW Specifies the signal flow of the XWAY PHY11G Og Copper MAC interface to twisted pair mode 1g Converter converts fiber 1000BASE X SerDes to twisted pair User s Manual 44 Revision 1 0 2012 02 17 Hardware Description XWAY PHY11G PEF 7071 ul Lantiq Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description Table 16 Functions of Device Parameters Controlled by Soft Pin Strapping No EEPROM Connected Device Parameter Function MODET1 0
124. by which certain events can be combined e g TXACT RXACT to generate a pulse on the LED in case such an event has been detected Constants 0000 NONE No pulsing 0001 TXACT Transmit activity 0010 RXACT Receive activity 0100 COL Collision 1000 RES Reserved User s Manual Hardware Description 146 Revision 1 0 2012 02 17 gU L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MMD Registers Similar Registers The following registers are identical to the Register LEDOL defined above Table 36 Similar Registers Register Short Name Register Long Name Offset Address Reset Value LED1L Configuration for LED Pin 1 1F 01E5 0000 LED2L Configuration for LED Pin 2 1F 01E7 0000 User s Manual 147 Revision 1 0 2012 02 17 Hardware Description gU L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MMD Registers High Byte of the EEE Link Fail Counter High Byte of the EEE Link Fail Counter EEE_RXERR_LINK_FAIL_H Offset Reset Value High Byte of the EEE Link Fail Counter 1F 01EA 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VAL RO Field Bits Type Description VAL 7 0 RO VAL High byte of the EEE RXERR LINK FAIL counter A read access to the low byte also clears the high byte of this counter Low Byte of the EEE Link Fail Counter Low Byte of the EEE Link Fail Counter
125. ce there is no far end signal and the echo is canceled out at the summation point the synthesized echo replica signal at the output of the DEC is used as a receive signal This setup allows for the complete transceiver to be tested in 1000BASE T mode without the need for additional hardware to be attached Figure 41 shows a high level block diagram where the test loop data path is marked by the area shaded in gray This test loop can be applied to all the supported MAC interfaces described in Chapter 3 2 but is only applicable to 1000BASE T The test loop is activated by setting MDIO PHY PHYCTL1 TLOOP ECHO and by activating the 1000BASE T forced mode using MDIO STD CTRL SSM 1g and MDIO STD CTRL SSL Og 4 SE bets PRF TXFEXDACESDR 28 en alos r 2 c xTC DEC ICD PMA HYB c i JE he p l 2 S EQ 2 j IRXFIHADCIHAG El p c p m nm ew we o ss E Figure 41 Echo Near End Test Loop 3 6 3 2 Far End Test Loop The PCS far end test loop allows for the receive data at the output of the receive PCS to be fed back into the transmit path that is the input of the transmit PCS The received data is also available at the xMII interface output however all xMII transmit data is ignored in this test mode Figure 42 shows a high level block diagram where the test loop data path is marked by the area shaded in gray This
126. cification of the signal detection polarity of the SIGDET input Although this bit is reset to 0 its actual value depends on the soft pin strapping configuration if no EEPROM is detected 0 LOWACTIVE SIGDET input is low active 1 HIGHACTIVE SIGDET input is high active STICKY 8 RW Sticky Bit Handling Constants Og OFF Sticky bit handling is disabled 1g ON Sticky bit handling is enabled Allows enabling disabling of the sticky bit handling for all PHY specific MDIO register bits of type RW except for the TPGCTRL register This means that the current content of these registers is left untouched during a software reset if sticky bit handling is enabled User s Manual 114 Hardware Description Revision 1 0 2012 02 17 iz Lanti C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers Field Bits Type Description RESL 7 4 RO Reserved Write as zero ignored on read ADCR RW ADC Resolution Boost Allows for the ADC resolution to be increased Constants Og DEFAULT Default ADC resolution 1g BOOST ADC resolution boost PSCL RW Power Consumption Scaling Depending on Link Quality Allows enabling disabling of the power consumption scaling dependent on the link quality Constants Og OFF PSCL is disabled 1g ON PSCL is enabled ANPD RW Auto Negotiation Power Down Allows enabling disabling of the power dow
127. ck output is continuously driven irrespective of the status of the reset pin tpower tret gt gt 4 j 2 5 3 3 V VDDP VDDR VDDH VDDL VDDC XTAL1 REFCLK RSTN STATE UNDEFINED Pin Str EEPROM ACTIVE OE i MDINT X Y MDO X Y XXXX XXXIX treset tmDio Figure 43 Timing Diagram for the XWAY PHY11G Reset Sequence 1 Figure 43 shows an active low MDINT signal However MDINT can be configured to either active low or active high depending on the external configuration Refer to Chapter 3 4 3 3 MDIO Interrupt for more information User s Manual 160 Revision 1 0 2012 02 17 Hardware Description ew Lantiq XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Electrical Characteristics Table 48 AC Characteristics of the RSTN Pin Parameter Symbol Values Unit Note Min Typ Max Test Condition Power supply settling time tpower x 50 0 ms Reset time sat 100 0 ns Rise time tr 10 0 ns First MDIO access after reset release tupio 300 0 ms 6 6 2 Power Supply Table 49 lists the AC characteristics of the power supplies Table 49 AC Characteristics of the Power Supply Parameter Symbol Values Unit Note Min Typ Max Test Condition Power supply ripple on VDDL RvppL 30 0 mV Peak value Power supply ripple on VDDC Ryppc 30 0 mV Peak value Power supply ripple
128. ctively of RXC SGMII Not Used The XWAY PHY11G drives logic zero in this mode User s Manual Hardware Description 26 Revision 1 0 2012 02 17 fer L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s External Signals 2 2 5 Control Interface Pins This section specifies the MDIO Interface according to clause 22 in 1 The AC characteristics of this interface are defined in Chapter 6 6 5 Table 6 Control Interface Pins Pin No Name Pin Buffer Function Type Type 41 MDC LVTTL MDIO Management Data Clock CMOS This is the MDIO data clock signal with which the serial PD management interface signals on MDIO are synchronized All MDIO signals are subject to change at the rising edge of MDC 42 MDIO 1 0 LVTTL MDIO Management Data Input Output CMOS The management data input output pin carries control information PU written by the higher level management entity to the PHY This includes command address and write information The MDIO is registered on the rising edge of MDC The pin is pulled up in input mode only 47 MDINT O LVTTL MDIO Management Interrupt CMOS This pin can be used to drive an interrupt signal to the higher level management entity The event for which this interrupt should be issued is configurable via the MDIO registers If no interrupt is active then the pin is in a high impedance state The polarity of the pin can be set via an
129. dance dRo 10 96 1 Assuming BER 1e 12 and tracking BW 1 MHz User s Manual 171 Revision 1 0 2012 02 17 Hardware Description gU L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Electrical Characteristics 6 6 10 2 Receive Timing Characteristics Figure 53 shows the timing diagram of the receive 1000BASE X interface on the XWAY PHY11G It is referred to by Table 61 which specifies the timing requirements 1 fax tr tr k RDP unipolar RDN unipolar Figure 53 Receive Timing Diagram of the 1000BASE X Table 61 Receive Timing Characteristics of the 1000BASE X Parameter Symbol Values Unit Note Min Typ Max Test Condition Receive data rate fax 50 ppm 1250 0 50 ppm Mbit s Receive data jitter tolerance Jgx 500 ps Receive signal rise time tr 300 ps 20 80 Receive signal fall time tr 300 ps 80 20 Input differential voltage Vip 50 500 mV Peak amplitude Input impedance single ended R 40 60 0 Input impedance differential R 80 1200 6 6 11 Twisted Pair Interface The AC characteristics for the TPI on pins VxpA VxnA VxpB VxnB VxpC VxnC VxpD and VxnD are specified in 1 and 4 Since the XWAY PHY11G conforms to these standards the values and limits specified there apply to this specification as well 6 7 Isolation Requirements The XWAY PHY11
130. device is in EEE mode 100 ANEG Complex function enabled when auto negotiation is running 101 ABIST Complex function enabled when analog self test is running 110 CDIAG Complex function enabled when cable diagnostics are running 111 TEST Complex function enabled when test mode is running CBLINK RW Complex Blinking Configuration This configuration defines in which state the complex blinking should be activated The complex blinking performs a blinking at the fast blinking frequency on all LEDs simultaneously This function can be used to indicate a special mode of the PHY such as cable diagnostics or test The speed is dependent on the MMD INTERNAL LEDCH FBF setting Constants 000 NONE No Function 001 LINK Complex function enabled when link is up 010 PDOWN Complex function enabled when device is powered down 011 EEE Complex function enabled when device is in EEE mode 100 ANEG Complex function enabled when auto negotiation is running 101 ABIST Complex function enabled when analog self test is running 110 CDIAG Complex function enabled when cable diagnostics are running 111 TEST Complex function enabled when test mode is running User s Manual Hardware Description 143 Revision 1 0 2012 02 17 gU L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MMD Registers Configuration for LED Pin 0 This register configures the behavior of the LED dependi
131. dicate another function e g ON or BLINK slow The length of the pulse stretching depends on the global setting used for the fast blinking frequency BLINKF 2 LED blinks with a globally configured fast frequency BLINKS 3 LED blinks with a globally configured slow frequency CON 4 LED is constantly ON can be configured to indicate link speed EEE mode ANEG analog self test cable diagnostics or the currently active interface copper fiber or other NONE 5 No direct function is applied to the LED the LED is OFF might be over ruled by a low concurrently running complex function 1 Pulse stretching is used to make short events visible by extending the lighting time of the LED following this event Table27 Complex LED Functions Function Priority Description CBLINK 1 All LEDs blink simultaneously with the globally configured fast frequency In high particular in order to distinguish this mode properly from concurrently running direct functions all even numbered LEDs have their blinking phase shifted by 180 with respect to the odd numbered LEDs SCAN 2 Scan sequence this is a walking light running fast between LEDO to LED2 backwards and forwards The speed is selected for the fast blink frequency NACS 3 Reversed scan sequence similar to the SCAN function but all LED outputs are inverted NONE 4 No complex function is applied to the LEDs low The speed or frequency of any
132. e 1 0 V voltage domains for example VDDL and VDDL Note that the integrated DC DC switching regulator supports soft starting such that PoE is enabled The power class advertised by the PD to the PSE depends largely on the power consumption of the whole system The XWAY PHY11G itself must also be taken into account Regardless of the current power consumption of the XWAY PHY11G it is recommended that a figure of 1 W is assigned to the PHY 3 5 2 2 Power Sourcing Equipment PSE The generic PSE circuit diagram is similar to that of the PD except that the PSE must only inject the supply into one of the two twisted pair alternatives pairs 1 2 and 3 6 or 4 5 and 6 7 The PSE also does not require polarity invariance measures since it defines the supply polarity However the PSE must be supplied properly to guarantee proper operation regardless of which type of PD is connected Otherwise the PSE has to switch itself off if it detects a PD of too high a power class There are 2 types of PSE system in band and mid span A mid span device does not include a PHY The pairs that are not used for PoE are routed straight through whereas the pairs that are used are routed through another transformer into which the PSE device can inject power The disadvantage of a mid span device is that additional magnetics are required Besides the mid span application is beyond the scope of this specification as a mid span device does not require an
133. e 10 gives an overview of MII pin multiplexing Media Independent Interface Pins Pin No Name Pin Type Buffer Type Function TX CLK REFCLK TXC LVTTL CMOS PD RGMII Transmit Clock The TXC signal is a continuous clock signal and provides the timing reference for the transfer of TX EN CTL and TXD 3 0 The nominal frequency of this clock is 125 MHz for 1000 Mbit s 25 MHz for 100 Mbit s and 2 5 MHz for 10 Mbit s Depending on the speed selection this clock is assumed to be properly adjusted by the MAC The frequency deviation is assumed to be smaller than 50 ppm RMII Reference Clock for the Transmit and Receive MAC I F The REFCLK signal is used by the MAC and the PHY MII for synchronous data transfers The nominal frequency of this clock is 50 MHz The XWAY PHY11G optionally provides a suitable free running 50 MHz clock on RX_CLK RTBI Transmit Clock The TXC signal is a continuous clock signal and provides the timing reference for the transfer of TX EN CTL and TXD 3 0 The nominal frequency of this clock is 125 MHz since RTBI is only defined for 1000 Mbit s The frequency deviation is assumed to be smaller than 50 ppm SCP HD SGMII Serial Clock Positive Pin This is the positive signal of the differential clock pair of the SGMII SerDes interface In conjunction with SCN it provides a 625 MHz differential clock that is source synchronous with SOP SON I
134. e ee ere a a ree ee ae aida 19 Table 4 Twisted Pair Interface Pins 0 0 ce eee 20 Table 5 Media Independent Interface Pins 0 0 0 0 cc ce eens 21 Table 6 Control Interface PINS 220 006 icc beeen eee eee dee ee eee ee bd eee eee 27 Table 7 JTAG Interface PINS ao or ees erret e rec ei es rre eet 28 Table 8 Power Supply Pins o 29 Table 9 MII and MDI Combinations Supported by XWAY PHY11G ooo 30 Table 10 xMII Signal Multiplexing 0 0 0 0 eee A ae 32 Table 11 Transmit Control Encoding erasian na ena E a a a a a a E a a 34 Table 12 Receive Control Encoding 0 000 cece Rh hh 34 Table 13 Supported Twisted Pair Mappings llli 39 Table 14 Soft Pin Strapping Mapping of Pull Down Capacitance Resistor Values to Configuration Bits 43 Table 15 Mapping of Configuration Pins Bits to Device Parameters No EEPROM Connected 44 Table 16 Functions of Device Parameters Controlled by Soft Pin Strapping No EEPROM Connected 44 Table 17 Mapping of Configuration Pins Bits to Device Parameters EEPROM is Connected 46 Table 18 Functions of Device Parameters controlled by Soft Pin Strapping EEPROM is Connected 46 Table 19 Supported EEPROM Devices llle rrr 48 Table 20 Configuration Signature Record CSR 0 en 49 Table 21 Configuration Content Record 0 0 eh hh 50 Table 22 Address Bit Mapping in 11 Bit Addressing Mode sellers 51 Table 23
135. e market In order to comply with almost all EEPROM devices currently available on the market and in particular with larger sizes two addressing modes are supported 11 bit addressing and 16 bit addressing Note that this addressing relates to the EEPROM internal data addressing and not to the I C device address mode For the latter the XWAY PHY11G only supports the standard 7 bit device address mode In compliance with most of the available EEPROM devices the default value of the device address is DADR 7 1 1010XXX The last three bits are configurable using the soft pin strappings see Chapter 3 4 1 which also contain a configuration bit for the addressing mode The following sections specify the frame formats for both addressing modes Mixed addressing mode operation is not supported by the XWAY PHY11G 3 4 2 4 1 Frame Formats in 11 Bit Addressing Mode This addressing mode is used for the smallest available EEPROM devices These devices are usually available in sizes ranging from 1 kb to 16 kb Since the EEPROM devices are organized in 8 bit words this requires between 7 and 11 address bits However only one address byte is defined following the I C instruction Therefore for larger EEPROM configurations it is common practice to use up to 3 LSBs of the device address within the 1 C instruction to map these missing 3 bits This is also illustrated in the frame structures specified in this chapter In order to clarify this further Tab
136. east Significant Bit M MAC Media Access Controller MDI Media Dependent Interface MDIO Management Data Input Output MDIX Media Dependent Interface Crossover MII Media Independent Interface MMD MDIO Manageable Device MoCA Multimedia over Coax Alliance MSB Most Significant Bit N NAS Network Attached Storage NP Next Page O OSI Open Systems Interconnection OUI Organizationally Unique Identifier P PCB Printed Circuit Board PCS Physical Coding Sublayer PD Powered Device PHY Physical Layer device PICMG PCI Industrial Computer Manufacturers Group PLL Phase Locked Loop PMA Physical Media Attachment PoE Power over Ethernet PON Passive Optical Network PSE Power Sourcing Equipment R RGMII Reduced pin count Gigabit Media Independent Interface RMII Reduced pin count Media Independent Interface RTBI Reduced pin count Ten Bit Interface RX Receive S User s Manual 186 Revision 1 0 2012 02 17 Hardware Description SFP SGMII SMD SoC TAP TBI TPG TPI TX VQFN WLAN WoL xMII User s Manual XWAY PHY11G PEF 7071 Eu Lantiq Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Small Form Factor Pluggable Serial Gigabit Media Independent Interface Surface Mounted Device System on Chip Test Access Port Ten Bit Interface Test Packet Generator Twisted Pair Interface Transmit Very Thin Quad Flat Non leaded Wireless Local Area Network Wake on LAN Terminology Symbolic shortenin
137. ed 01 reserved 10 reserved 11 reserved 1 The initial duplex mode is determined by the default value of MDIO STD CTRL DPLX User s Manual Hardware Description 45 Revision 1 0 2012 02 17 Lanr XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s C Functional Description Table 17 Mapping of Configuration Pins Bits to Device Parameters EEPROM is Connected Configuration Pin CBV 3 0 associated by resistor value according to Table 14 BV 3 BV 2 BV 1 BV 0 LEDO OB SPEED 1 SPEED 0 ADRMODE LED1 SIZE 1 DEVADR 2 DEVADR 1 DEVADR 0 LED2 SIZE 0 CRID 2 CRID 1 CRID 0 The functions of the device parameters mapped in Table 17 are defined in Table 18 Table 18 Functions of Device Parameters controlled by Soft Pin Strapping EEPROM is Connected Device Parameter Function ADRMODE Specifies the EEPROM Addressing Mode Og 11 bit EEPROM addressing mode see also Chapter 3 4 2 4 1 1g 16 bit EEPROM Addressing Mode see also Chapter 3 4 2 4 2 DEVADR 2 0 Specifies the EEPROM Device Address The device address can be specified in case multiple EEPROM devices are connected to the same IC bus The valid mapping of device address bits into the frame is specific to the ADRMODE see Chapter 3 4 2 4 for more details In general the DEVADR bits are mapped MSB aligned into bits 3 1 of the 1 C instruction field Note that some larger devices in 11 bit mode
138. ed Mode ECM 0 0 00 eee 63 3 4 4 3 2 LED Functions in Internally Controlled Mode ICM 0 00 cece ee 63 3 4 4 3 3 LED Configuration in ICM 00 eee 64 3 5 Power Management 6 0 ccc E ee A eee 66 3 5 1 Power Supply Ki aens iaaa diia beet ctos dep a ed dk bok bath Re teh dete d ae dean dts 66 3 5 1 1 Power Supply Using Integrated Switching Regulator 0 0 0 cece eee 66 3 5 1 2 Power Supply Without Using Integrated Switching Regulator o ooooooocooooo 68 3 5 2 Power Over Ethernet POE 00 c cette hh hn 68 3 5 2 1 Powered Device PD 24 0 2 c4 4 4 ee eee gg e eR Gp hi4 P eee ee ee ee ee eb 69 3 5 2 2 Power Sourcing Equipment PSE lt sea cerasana kri aa nET rn 70 3 5 3 Energy Efficient Ethernet cerises eea 00 une a e a hh hne 71 3 5 3 1 EEE Tor TOBASESTE i ice ttd er doi e RR ed Ten a RD dde 72 3 5 3 2 EEEfor100BASE TX cion oia ar tke PLE eee Bae a RS E EY d 72 3 5 3 3 EEE for TODOBASE T iii e ARES MER he bebe ec 72 3 5 3 4 Auto Negotiation for EEE Modes 0 cee en 73 3 5 3 5 Support of Legacy MACS essas ies nent eae 73 3 5 4 Wake on LAN WoL 6 0 0 0020 cee eee E es 74 3 5 5 Power Down Mode s s 2 2 2 beet idee aa eee ROI Rub Ced abel E Rcge e Red Aa eee 77 3 5 5 1 PB FORCE Mode 22e va dr A Pande oes Ga eee aa Rx dan eek A Sab ees 77 3 5 5 2 ANEG MOGE eas ar tana ee a aang al eee ee Re a eee REA VR 78 3 5 5 3 PD IDLE MOdG iile rye ERU ge uera E eal Gia ging AD
139. ed for future use 1 This is the byte wise EEPROM address The scheme is independent of the address mode used 11 16 User s Manual 49 Revision 1 0 2012 02 17 Hardware Description Eo Lantiq XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description Table 21 Configuration Content Record Address Content Comment 7 6 5 4 3 2 1 0 CCR_ADR 0 NOCE 7 0 Number of configuration entries A value of 00 corresponds to 1 entry A value of FF corresponds to 256 entries CCR ADR 1 ADDR 1 7 0 Address MDIO address and CCR ADR 2 DATA 1 15 8 configuration data word MDIO data for try 1 CCR ADR 3 DATA 1 7 0 SN CCR ADR 4 ADDR 2 7 0 Address MDIO address and CCR ADR 5 DATA 2 15 8 configuration data word MDIO data for try 2 CCR ADR 6 DATA 2 7 0 I CCR ADR CCR ADR ADDR NOCE 7 0 Address MDIO address and 3 NOCE 1 configuration data word MDIO data for CCR ADR DATA NOCE 15 8 entry ZNOCE 3 NOCE 2 CCR ADR DATA NOCE 7 0 3 NOCE 3 1 This is the byte wise EEPROM address The scheme is independent of the address mode used 11 16 3 4 2 4 EEPROM Frame Formats This chapter specifies the EEPROM frame formats supported In particular a subset of the I C protocol is represented which is supported by most of the EEPROM devices on th
140. efault reset values which depend on soft pin strappings Constants 000 SKEW 0NO 0 0 ns timing skew 001 SKEW_0N5 0 5 ns timing skew 010 SKEW 1NO 1 0 ns timing skew 011 SKEW 1N5 1 5 ns timing skew 100 SKEW 2NO 2 0 ns timing skew 1015 SKEW 2N5 2 5 ns timing skew 110 SKEW_3N0 3 0 ns timing skew 111 SKEW 3N5 3 5 ns timing skew V25 33 11 RW Power Supply Control for MII Pins Required for standard compliant operation of RGMII Constants Og X V33MII is operated at 3 3 V 1g V25MII is operated at 2 5 V User s Manual 119 Revision 1 0 2012 02 17 Hardware Description 2 Landi C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers Field Bits Type Description TXSKEW 10 8 RW Transmit Timing Skew RGMII Defines the transmit timing skew in the RGMII mode using the integrated delay generation on TX CLK Note that this register is subject to default reset values which depend on soft pin strappings Constants 000 SKEW_ONO 0 0 ns timing skew 001 SKEW_0N5 0 5 ns timing skew 010 SKEW 1NO 1 0 ns timing skew 011 SKEW_1N5 1 5 ns timing skew 100 SKEW 2NO 2 0 ns timing skew 101 SKEW 2N5 2 5 ns timing skew 110 SKEW_3N0 3 0 ns timing skew 111 SKEW 3N5 3 5 ns timing skew CRS 7 6 RW CRS Sensitivity Configuration Constants 00 TXRX_RX HDX TX RX FDX RX 01 TXRX 0 HDX TX RX FDX 0 10 RX RXHDX RX FDX RX 11 RX 0 HDX RX FD
141. et length is 64 bytes 001 B128 Packet length is 128 bytes 010 B256 Packet length is 256 bytes 011 B512 Packet length is 512 bytes 100 B1024 Packet length is 1024 bytes 101 B1518 Packet length is 1518 bytes 110 B9600 Packet length is 9600 bytes RESLO 3 2 RO Reserved Write as zero ignore on read START 1 RW Start or Stop TPG Data Generation Starts the TPG data generation Depending on the MODE the TPG sends only 1 single packet or chunks of 10 000 packets until stopped Constants Og STOP Stops the TPG data generation 1g START Starts the TPG data generation EN 0 RW Enable the TPG Enables the TPG for data generation Constants Oz DISABLE Disables the TPG 1 ENABLE Enables the TPG User s Manual Hardware Description 129 Revision 1 0 2012 02 17 Test Packet Generator Data Er Lanti C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers Specifies the payload data to be used when sending a non random data packet All payload data bytes are sent with this value TPGDATA Test Packet Generator Data Offset Reset Value 1D 00AA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DA SA DATA RW RW RW Field Bits Type Description DA 15 12 RW Destination Address Configures the destination address nibble The Source Address builds up to 00 03 19 FF FF F DA SA 11 8 RW Source Address Configures the
142. ether or not an external EEPROM is connected by sensing the SDA pin during startup Since the SDA pin is equipped with an internal pull up resistor to comply with the 12C specification it is assumed that an EEPROM is connected when this pin is sensed as being at logic 1 after reset In case no external EEPROM is connected it is required that this pin be pulled to ground and thus sensed internally as being at 0 after reset Attention The SDA pin must not be left floating In case an EEPROM has been detected the soft pin strapping pins are used to properly configure the EEPROM This includes information about speed address mode and slave device address Refer to Chapter 3 4 1 for more information If the XWAY PHY11G evaluates the SDA pin and detects an EEPROM device it tries to access the EEPROM device by initiating a single byte read If the device is present and understands the C format it will acknowledge User s Manual 48 Revision 1 0 2012 02 17 Hardware Description fer L XWAY PHY11G PEF 7071 fe ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description the read instruction after a certain amount of time The XWAY PHY11G waits for this acknowledgement and if none is received before a time out the attempt to access the EEPROM is aborted and no compatible device is assumed to be connected to the 1 C interface However if the acknowledgement is successfully received the XWAY PHY11G sta
143. exchanged capabilities The result is combined with the speed resolution Whether or not a link is able to operate EEE is reported in the MDIO PHY MIISTAT EEE register refer to Media Independent Interface Status 3 5 3 5 Support of Legacy MACs An EEE aware MAC should be able to assert LPI as described in Table 22 1 of the IEEE 802 3az standard 2 In contrast a legacy MAC is incapable of this and simply indicates a normal inter frame when it does not have frames to send as described in Table 22 1 of the IEEE 802 3 standard 1 However the XWAY PHY11G allows for low power operation to be achieved even when a legacy MAC is used This is done by observing the continuous presence of normal inter frame signal combinations at its xMII input and by switching to LPI mode Therefore the LPI mode operates in the same way as required by the IEEE 802 3az standard 2 except for the way in which the mode is triggered The LPI mode operation in the XWAY PHY11G is shown in Figure 34 The LPl unaware MAC can resume transmission of frames without any early warning and it is necessary for the XWAY PHY11G to wake up and send these incoming frames without losing any of the data contained To temporarily hold the bytes arriving immediately after LPI an internal buffer is employed This buffer is emptied gradually over the MDI after LPI mode is left This is achieved by shortening the IPG without whic
144. f a MAC with CDR is used this pin can be left open The SCP pin must be AC coupled For more details see Chapter 6 8 6 User s Manual Hardware Description 21 Revision 1 0 2012 02 17 amp LANTI C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s External Signals Table 5 Media Independent Interface Pins cont d Pin No Name Pin Buffer Function Type Type 6 RX_CLK O LVTTL RGMII Receive Clock CMOS The RXC signal is a continuous clock signal and provides the timing reference for the transfer of RX EN CTL and RXD 3 0 The nominal frequency of this clock is 125 MHz for 1000 Mbit s 25 MHz for 100 Mbit s and 2 5 MHz for 10 Mbit s The frequency deviation is smaller than 50 ppm CLK50 RMII Optional 50 MHz Reference Clock for the RMII This pin optionally provides a free running reference clock for the RMII This clock can be wired to the MAC and the TX CLK of the XWAY PHY11G device The nominal frequency of this clock is 50 MHz RXC RTBI Receive Clock The TXC signal is a continuous clock signal and provides the timing reference for the transfer of RX DV CTL and RXD 3 0 The nominal frequency of this clock is 125 MHz since RTBI is only defined for 1000 Mbit s The frequency deviation is assumed to be smaller than 50 ppm SGMII Not Used The XWAY PHY11G drives logic zero in this mode 10 TXD3 LVTTL R
145. faults where the PHY fails to complete its normal wake sequence within the time required for the specific PHY type The definition of the fault event to be counted is defined for each PHY and may occur during a refresh or a wake up as defined by the PHY This 16 bit counter is reset to all zeroes when the EEE wake error counter is read by the management function or upon execution of the PCS reset It is held at all ones in case of overflow User s Manual Hardware Description 137 Revision 1 0 2012 02 17 ET LANTI C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MMD Registers 5 2 ANEG Standard Auto Negotiation Registers for MMD 0x07 This register file contains the auto negotiation registers for MMD device 0x07 only supporting EEE specifics EEE Auto Negotiation Advertisement Register This register defines the EEE advertisement that is sent in the unformatted next page following an EEE technology message code as defined in 28C 12 The 11 bits 7 60 10 to 7 60 0 in the EEE advertisement register correspond to the bits in the unformatted next page For PHYs that negotiate extended next page support the 11 bits 7 60 10 to 7 60 0 in the EEE advertisement register correspond to bits U10 to UO respectively of the extended next page unformatted code field EEE AN ADV Offset Reset Value EEE Auto Negotiation Advertisement 07 003C 000
146. g configuration can be found in Chapter 3 4 1 p LEDx Y ls ct GND Figure 27 Single Color LED External Circuitry 3 4 4 Bi Color LED Mode The external circuitry for a bi color LED is depicted in Figure 28 The LEDx and LEDy pins represent any two of the available LED interface pins at the device The GND signal represents the common ground EPAD The LEDx and LEDy pins are designed to source a certain amount of current out of the pad supply Vppp when becoming active high Besides the LEDs three individual resistors are depicted in the figure R p denotes an optional series resistor which might be used depending on the selected LED type and PAD supply voltage Vppp Rorex Rerey and Corex Ccrey denote external passive components required for the soft pin strapping configuration of the device The component values are selected such that the brightness of the LED is not affected More details on this type of pin strapping configuration can be found in Chapter 3 4 1 1 Bi color LEDs are also available as monolithic 2 pin devices as indicated in Figure 28 User s Manual 62 Revision 1 0 2012 02 17 Hardware Description gU L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description ppe LEDy LEDx e L3 OO Riep XN APR fo ic ls ls GND e Figure 28 Bi Color LED External Circuitry 3 4 4 3 LED Operations Irrespective
147. g which denotes the set of supported MII Interfaces e g RGMII and SGMII 187 Hardware Description Revision 1 0 2012 02 17 www lantiq com Published by Lantiq Deutschland GmbH
148. gabit Ethernet PHY 10 100 1000 Mbit s 6 6 10 1000BASE X Interface This section describes the AC characteristics of the 1000BASE X interface on the XWAY PHY11G This interface conforms to the specifications given in IEEE802 3 clause 36 see 1 The 1000BASE X interface can operate at 1 25 Gbaud The net data rate is 1000 Mbit s Also note that Chapter 6 8 7 describes the external circuitry 6 6 10 1 Transmit Timing Characteristics Figure 52 shows the timing diagram of the transmit 1000BASE X interface on the XWAY PHY11G It is referred to by Table 60 which specifies the timing requirements Electrical Characteristics 1 fax tr ies gt A TDP unipolar TDN unipolar TD P N differential tskew Figure 52 Transmit Timing Diagram of the 1000BASE X Interface Table 60 Transmit Timing Characteristics of the 1000BASE X Interface Parameter Symbol Values Unit Note Min Typ Max Test Condition Transmit data rate fax 50 ppm 1250 0 50 ppm Mbit s Transmit rise time tr 100 200 ps 20 80 Transmit fall time tr 100 200 ps 80 20 Output data jitter du 240 ps Peak peak Time skew between pairs tekew 20 ps Output differential voltage Vop 150 400 mV Peak amplitude Output voltage ringing V ing 10 Output impedance single ended Ro 40 60 0 Output impedance differential Ro 80 120 10 Delta output impe
149. gnal LPI then the PHY can also not become quiet However LPI requests are passed from one end of the link to the other regardlessly and system energy savings can be achieved even if the PHY link does not become quiet The 1000BASE T LPI is symmetric on the PHY layer but remains asymmetric transmit and receive independently at xMII level and above Note that the XWAY PHY11G indicates a receive LPI by asserting RX DV Op RX ER 1g and RXD 01 at the GMII or an equivalent interface The wake time for 1000BASE T is of 16 5 us User s Manual 72 Revision 1 0 2012 02 17 Hardware Description 2s L XWAY PHY11G PEF 7071 pS T A YT IC Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description 3 5 3 4 Auto Negotiation for EEE Modes Itis imperative that EEE capability is advertised since except for 10BASE Te a compliant link partner is required Similarly to 1000BASE T auto negotiation the XWAY PHY11G automatically advertises EEE capability if this is enabled using next pages EEE capability is stored in the MMD ANEG EEE AN ADV registers refer to EEE Auto Negotiation Advertisement Register Setting this register to zero disables EEE After a successful negotiation the link partners capabilities are stored in the MMD ANEG EEE AN LPADV register refer to EEE Auto Negotiation Link Partner Advertisement Register After a successful auto negotiation the XWAY PHY11G performs an auto resolution on the
150. h the DEVAD field and the MMD s address register direct the register MMDDATA data accesses to the appropriate registers within that MMD The function field can be set to any of the constants defined ADDRESS DATA DATA PI DATA PIWR Constants 00 ADDRESS Accesses to register MMDDATA access the MMD individual address register 01 DATA Accesses to register MMDDATA access the register within the MMD selected by the value in the MMD s address register 10 DATA PI Accesses to register MMDDATA access the register within the MMD selected by the value in the MMD s address register After this access is complete for both read and write accesses the value in the MMD address field is incremented 11 DATA PIWR Accesses to register MMDDATA access the register within the MMD selected by the value in the MMD s address register After this access is complete for write accesses only the value in the MMDs address field is incremented For read accesses the value in the MMDs address field is not modified RESH 13 8 RO Reserved Write as zero ignored on read RESL 7 5 RO Reserved Write as zero ignored on read DEVAD 4 0 RW Device Address The DEVAD field directs any accesses of register MMDDATA to the appropriate MMD as described in IEEE 802 3 2008 clause 45 2 1 User s Manual 105 Revision 1 0 2012 02 17 Hardware Description MMD Access Data Register ET LANTI C XWAY PHY11G PEF 7071 Single Port Gigabit Et
151. h the buffer might not be properly emptied within a reasonable amount of time To achieve this not all incoming IPG bytes are transmitted over the MDI and some are discarded n consecutive inter subsequent inter je gt gt new frames frame cycles frame cycles wae U U TT E ESEST ET AE AAA oX 3 A JL X eiie T valid data TX ER SS 2 S _ TX_EN A hold off period E N y N mS MDI noma J X ter fmin irs X normal TX Figure 34 LPI Mode Operation in XWAY PHY11G To activate this feature the LPI bit in the MDIO PHY PHYCTL2 register needs to be set to 1 refer to Physical Layer Control 2 In addition the IDLE value in the MMD INTERNAL LEG LPI CFG3 register should be programmed to indicate the number of inter frame bytes that should arrive at the MII input before the LPI is activated refer to Legacy LPI Configuration Register 3 The Tw phy value in the IEEE 802 3az standard Table 78 4 defines a minimum time between when a new frame is received from the MAC terminating the LPI mode until when MDU transmission can start This value is reflected in the HOLDOFF 100BT and HOLDOFF 1000BT values in the MMD INTERNAL LEG LPI CFGO0 and MMD INTERNAL LEG LPI CFG1 registers for the 100 Mbit s and 1000 Mbit s modes respectively refer to Legacy LPI Configuration Register 0 User s Manual 73 Revision 1 0 2012 02 17 Hardware Description fer L XWAY
152. h the higher level management entity and the PHY disable their tristate drivers and that MDIO is in high impedance The times of the second bit is used by the XWAY PHY11G to drive a logic zero DATA Read Write Data The data field is 16 bits wide The MSB is sent first and the LSB is sent last in both read and write transactions 3 4 3 2 MDIO Address Space Configuration and control operations as well as extraction of status information can be handled via the MDIO interface This interface allows for registers located in the MDIO address space to be read from and written to The MDIO interface can only address up to 32 addresses The first 16 addresses from 00 to OF are mostly defined by the IEEE 802 3 standard 1 and cannot be used for device specific configuration Only the last 16 addresses from 10 to 1F are to be used Since a range of 16 addresses is not sufficient to manage the XWAY PHY11G an indirect addressing scheme is used This scheme is depicted in Figure 24 which shows the layout of the MDIO address space looking from the higher level management entity via the MDIO interface towards the PHY As shown in the figure the direct address region from 00 to OF holds all IEEE 802 3 standard 1 registers The address range from 10 to 1F spans an address range for PHY specific registers that can be accessed directly via MDIO as well The XWAY PHY11G address space is extended by means of an indirect me
153. has no effect This register contains the advertised ability of the link partner see also IEEE 802 3 2008 Tables 28 3 and 28 4 1 The bit definitions are a direct representation of the received link code word see also IEEE 802 3 2008 Figure 28 7 1 See also IEEE 802 3 2008 22 2 4 3 3 1 AN_LPA Offset Reset Value Auto Negotiation Link Partner Ability 05 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NP ACK RF TAF SF RO RO RO RO RO Field Bits Type Description NP 15 RO Next Page Next page request indication from the link partner See also IEEE 802 3 2008 28 2 1 2 6 Constants Og INACTIVE No next page s will follow 1g ACTIVE Additional next pages will follow ACK 14 RO Acknowledge Acknowledgement indication from the link partner s link code word See also IEEE 802 3 2008 28 2 1 2 5 1 Constants 0s INACTIVE The device did not successfully receive its link partner s link code word 1g ACTIVE The device has successfully received its link partner s link code word RF 13 RO Remote Fault Remote fault indication from the link partner See also IEEE 802 3 2008 28 2 1 2 4 1 Constants Og NONE Remote fault is not indicated by the link partner 1g FAULT Remote fault is indicated by the link partner TAF 12 5 RO Technology Ability Field Indicates the link partner capabilities as received from the link partner s link code word See also IEEE 802 3 2008 28 2 1 2 2 1 Constant
154. he CRID must match the value specified by the pin strapping configuration see also Chapter 3 4 1 The first address contained in the CSR is the PHYADR used to address the MDIO messages to the correct device in case the MDIO is shared More details can be found in Chapter 3 4 3 1 If no CSR is found during the scan process the MDIO address is set internally to PHYADR 4 3 005 PHYADR 2 0 CRID 2 0 The subsequent field contains the Configuration Content Record CCR base address CCR ADR which is a 16 bit pointer address pointing to the start address location of the CCR on the same EEPROM as defined in Table 21 In case no CCR exists the CCR ADR must be set to FFFF The 2 bytes following the CCR ADR field are reserved for internal use and must be set to FFFF Table 20 Configuration Signature Record CSR Address Content Comment 7 6 5 4 3 2 1 0 k STEP 0 1 1 1 0 1 1 1 0 Configuration Record Signature k STEP 1 1 1 0 0 0 4 0 0 o EFE amp CO DE TF k STEP 2 1 1 0 1 1 1 1 0 k STEP 3 0 0 0 1 1 1 1 1 k STEP 4 0 0 0 0 O0 CRID 2 0 Configuration record ID k STEP 5 0 0 0 PHYADR 4 0 PHY MDIO address k STEP 6 CCR_ADR 15 8 Configuration Content Record CCR k STEP 7 CCR ADR T 0 base address This vector must be set to CCR ADR FFFF if no CCR exists k STEP 8 1 1 1 1 1 1 1 1 Reserved for future use k STEP 9 1 1 1 1 1 1 1 1 Reserv
155. he XWAY PHY11G can be done using its MDIO interface Alternatively the device can be pre configured by means of an external I1 C based EEPROM Simple basic settings can be made using the novel soft pin strapping feature available for the LED pins see Chapter 3 4 1 The device also integrates a standard Test Access Port TAP for boundary scan The XWAY PHY11G is encased in the industry s smallest package VQFN48 for a GbE PHY device with a given feature set and considering the level of integration It therefore provides an ideal solution for footprint sensitive applications such as SFP copper modules or LAN on Motherboard Furthermore the XWAY PHY11G design supports a reduced external bill of materials for example through the integration of termination resistances at both the MDI and MII The CLKOUT pin can optionally be used to provide a 25 125 MHz reference clock allowing for multiple PHY devices to be cascaded while using only one crystal With an effectiveness of more than 80 the XWAY PHY11G is tailored for energy efficiency It can be operated from a single power supply ranging from 2 5 V to 3 3 V in which case the 1 0 V domains are self supplied using the device s integrated DC DC switching regulator By supporting the Energy Efficient Ethernet EEE standard as defined in the IEEE 802 3az standard 2 the PHY is able to reduce active power consumption during periods of low link utilization to as little as 1096 of the nominal
156. hernet PHY 10 100 1000 Mbit s MDIO Registers The MMD access data register is used in conjunction with the MMD access control MMDCTRL register to access the MMD register space For more information on MMD access refer to IEEE 802 3 2008 clause 22 2 4 3 12 clause 45 2 and Annex 22D 1 MMDDATA MMD Access Data Register Reset Value 0000 Offset OE 15 14 13 12 11 9 8 7 6 5 4 3 2 1 0 ADDR DATA RW Field Bits Type Description ADDR DATA 15 0 RW Address or Data Register This register accesses either a specific MMD address register or the data content of the MMD register to which this address register points Which of the functions is currently valid is defined by the MMDCTRL register User s Manual Hardware Description 106 Revision 1 0 2012 02 17 uf Leona XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers Extended Status Register This register contains extended status and capability information about the PHY Note that all bits are read only A write access does not have any effect XSTAT Offset Extended Status Register OF Reset Value 3000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MBXF MBXH MBTF MBTH RESH RESL RO RO RO RO RO RO Field Bits Type Description MBXF 15 RO 1000BASE X Full Duplex Capability Specifies whether the PHY is capable of operati
157. ia MDIO If a higher level management entity exists in the system this can configure and control the XWAY PHY11G completely by means of the MDIO interface according to IEEE 802 3 1 3 4 3 1 MDIO Interface The XWAY PHY11G supports an MDIO interface according to IEEE 802 3 1 giving a higher level management entity control over internal functions This control is provided by means of MDIO registers The XWAY PHY11G provides the set of IEEE standard registers according to 1 Additionally extended register pages are supported All registers are described in Chapter 4 The MDIO interface is a serial interface using only 2 pins which are named MDC and MDIO See Chapter 2 2 5 for more information The clock pin MDC is always driven by the higher level management entity The bi directional signal MDIO carries the control information and is driven by both the higher level management entity and the PHY depending on whether a write or a read operation is being executed The MDIO communication between the higher level management entity and PHY is organized in frames that are defined by IEEE 802 3 1 Figure 22 and Figure 23 illustrate the write and read frames respectively Chapter 6 6 5 defines the AC characteristics of this interface STA drives the bi directional MDIO 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 i 1 1 1 1 1 1 1 1 1 i 1 1 1 1 0 1 A amp 1 A3 A2 AL ao R4 R3 R2 RL RO 1 o DIS DI4 D13
158. ia the MDI The remotely powered device does not require a power supply thereby mainly saving on installation costs since only the Ethernet connection CAT5 cable or better needs to be equipped One example of such an application is for WLAN routers or NAS devices According to the standard such devices can be remotely powered if they consume less than 15 4 W As there is a strong demand for higher power applications an enhancement of the PoE standard has been developed IEEE 802 3at 3 that is able to provide up to 50 W via remote powering The increase in power level is practically the only difference between the two standard versions The IEEE 802 3at standard defines two kinds of devices the Powered Device PD and the Power Sourcing Equipment PSE The former extracts electrical power from the common mode of some of the twisted pairs inside the CATS or better cable whereas the latter acts as a source of electrical power The two types of devices and their application together with the XWAY PHY11G are illustrated in Chapter 3 5 2 1 and Chapter 3 5 2 2 respectively User s Manual 68 Revision 1 0 2012 02 17 Hardware Description ral XWAY PHY11G PEF 7071 E LANTIC Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description 3 5 2 1 Powered Device PD Figure 31 shows a generic schematic diagram of a system using a PD XWAY PHY11G Transformer TPIAP TPIAN py 3 TPIBP T
159. ics 6 5 1 2 MII Receive Interface This section defines the DC characteristics of the MII receive interface Depending on the MII mode this interface comprises the set of pins RX_CLK RXD 3 0 RX_CTL and MII_TXC The DC characteristics summarized in Table 43 are valid for Vppp 2 5 V and Vppp 3 3 V Table 43 DC Characteristics of the Receive MII Interface Parameter Symbol Values Unit Note Min Typ Max Test Condition Output high voltage R GMII mode Vou 2 1 V lop 1 mA Vopp 2 37 V Output high voltage MII mode Vou 24 V lop 4 mA Vopp 3 13 V Output low voltage VoL x 0 4 V lo 4 mA 6 5 1 3 MII Transmit Interface This section defines the DC characteristics of the MII transmit interface Depending on the MII mode this interface comprises the set of pins TX CLK TXD 3 0 TX CTL The DC characteristics summarized in Table 44 are valid for Vppp 2 5 V and Vppp 3 3 V Note that these pins are multiplexed with a SerDes interface for example SGMII or 1000BASE X depending on the operational mode of the XWAY PHY11G This chapter specifies the DC characteristics for the case that these pins operate in one of the non SerDes modes Table 44 DC Characteristics of the Transmit MII Interface Parameter Symbol Values Unit Note Min Typ Max Test Condition Input high voltage Vin 1 7 V Input low voltage Vi 0 9 V 6 5 1 4 LED Interface
160. inally 100 O are integrated into the device As a consequence the TPI pins see Chapter 2 2 3 can be directly connected via the transformer to the RJ45 plug Additional external circuitry is only required for proper common mode termination and rejection The electrical characteristics of the transformer and the plug are outlined in Chapter 6 8 3 and Chapter 6 8 4 respectively A high level schematic of the TPI circuitry is shown in Figure 9 taking these components into account The twisted pair wires are connected to the RJ45 plug pins according to the specification in 5 The common mode external circuitry is described in Chapter 6 8 5 Note that the twisted pair port C is terminated with high precision high ohmic resistors Rea which are in turn connected to the common mode ground This configuration is only required for the port C and is used to auto calibrate the IC after reset Transformer ol sk TPIAP TPIAN TPIBP TPIBN TPICP TPICN TPIDP TPIDN UU UU 00 DI Rear GND Remm Figure 9 Twisted Pair Interface of XWAY PHY11G Including Transformer and RJ45 Plug 3 3 1 2 Fiber Interface Using the integrated SerDes module the XWAY PHY11G supports fiber based PHY Ethernet applications compliant with IEEE 802 3 clause 36 1 1000BASE X 1000B
161. infrastructure The connection between MAC and PHY can be established using one of the supported xMII interface types RGMII RTBI or SGMII Network Processor Transformer XWAY MAC PHY11G 10 100 1000bT PEF 7071 25MHz Figure2 XWAY PHY11G Used in Copper Applications 1 2 3 2 Media Converter Application In media converter applications the PHY is used to interface between fiber and copper media The fiber medium can be connected using a fiber or SFP module which is connected via a 1000BASE X or SGMII interface The copper medium is connected via a twisted pair interface RJ45 using a transformer for galvanic de coupling Only one instance of the XWAY PHY11G device is required to address this application Stand alone operation is possible using the EEPROM see Chapter 3 4 2 self configuration capability Fiber Module Transformer SFP Module 1000bX XWAY PHY11G PEF 7071 M foe 25MHz Figure3 XWAY PHY11G Used in Media Converter Applications 1 2 3 3 Gigabit Interface Converter GBIC Application The GBIC 12 application is used to support a 10 100 1000BASE T GBIC SFP module implementation as illustrated in Figure 4 The MDIO interface of the XWAY PHY11G device is now not available but an EEPROM can optionally be used to upload customer specific configuration settings see Chapter 3 4 2 User s Manual 15 Revision 1 0 2012 02 17 Hardware Description r
162. ing the MDIO PHY PHYCTL1 TXEEEL10 bit In order to maintain maximal inter operability the XWAY PHY11G detects links with marginal characteristics and automatically switches back to the 10BASE T mode Thus the legacy performance requirements are also supported even though the transmitter is set up for 10BASE Te 3 5 3 2 EEE for 100BASE TX During periods of low link utilization an EEE compliant MAC can assert Low Power Idle LPI It does so by asserting TX EN 0g TX ER 1 and TXD 0001 at the MII or an equivalent interface The XWAY PHY11G initiates LPI signaling and enters a low power mode Similarly the XWAY PHY11G senses LPI signaling on its receive side and switches off the receive path Any wake attempt will cause the XWAY PHY11G to return to the normal mode of operation in transmit or receive Note that the XWAY PHY11G indicates a receive LPI by asserting RX DV 0g RX ER 1g and RXD 00015 at the MII or equivalent interface The wake time for 100BASE TX is of 30 us 3 5 3 3 EEE for 1000BASE T During periods of low link utilization an EEE compliant MAC can assert Low Power Idle LPI It does so by asserting TX EN 0g TX ER 1g and TXD 01 at the Gigabit MII or an equivalent interface In 1000BASE T LPI mode the transmit function of the XWAY PHY11G enters a quiet mode only after the XWAY PHY11G transmits sleep and receives sleep from the link partner If the link partner chooses not to si
163. ion resistor can be connected After the initial classification done by the PSE with low voltages to prevent damage of non PoE compliant PDs the PSE drives the required power to the line The PD indicates the availability of power to the DC DC converter by means of the Pgood power good signal The DC DC converter is required to transform the line voltage gt 20 V to the User s Manual 69 Revision 1 0 2012 02 17 Hardware Description fer L XWAY PHY11G PEF 7071 fe ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description chip power supply voltages required by the system Since the DC DC can only start once the power is stable the Pgood indication is usually a necessary requirement Note that the DC DC converter must implement soft start functionality to prevent the start current from becoming exhaustively large Once the DC DC provides the nominal voltage to the system the remotely powered devices ICs power up just as they would if a power source is applied in normal operating conditions In the simplified generic schematic of Figure 31 the board voltage provided by the DC DC of the PD is fed to the XWAY PHY11G to supply the 2 5 V 3 3 V voltage domain and in particular VDDP VDDH and VDDR All these domains must be properly blocked with adequate capacitance and filtering techniques The integrated DC DC switching regulator see also Chapter 3 5 1 1 of the XWAY PHY11G can in turn be used to supply th
164. it a falling edge on SDA while SCL is active high the l C instruction is sent containing the default device address DADR 7 1 1010XXX that is applicable to almost all EEPROM devices available The last bit in the instruction is a read write bit which is set to low to indicate a write transaction The instruction byte is followed by an acknowledgement driven by the EEPROM Following this acknowledgement the XWAY PHY11G drives the memory address bytes ADR 15 8 and ADR 7 0 both of which are also separately acknowledged by the EEPROM The last of the four bytes in the write operation frame contains the data byte to be written DATA 7 0 After a successful write operation this byte is acknowledged by the EEPROM and the XWAY PHY11G ends the write frame with a stop bit a rising edge on SDA while SCL is active high INSTR DADR 7 1 ADR 15 8 ADR 7 0 DATA 7 0 Figure 17 Timing Diagram for a Random Address Single Byte Write Figure 18 shows a read frame similar to the write frame protocol illustrated in Figure 17 In general a read frame starts with a dummy write frame which lasts up to the write address This is required to set the current address on the EEPROM After acknowledgement of the address byte ADR 7 0 the XWAY PHY11G terminates the current dummy write by setting a new start bit The instruction byte is repeated except that the read write bit is now set to active high to indicate that this instruction corre
165. it Ethernet PHY 10 100 1000 Mbit s MDIO Registers Field Bits Type Description LS ROLL Link Status Indicates the link status of the PHY to the link partner See also IEEE 802 3 2008 22 2 4 2 13 1 Constants Og INACTIVE The link is down No communication with link partner possible 1g ACTIVE The link is up Data communication with link partner is possible JD ROLH Jabber Detect Indicates that a jabber event has been detected See also IEEE 802 3 2008 22 2 4 2 14 1 Constants 0s NONE No jabber condition detected lg DETECTED Jabber condition detected XCAP RO Extended Capability Indicates the availability and support of extended capability registers See also IEEE 802 3 2008 22 2 4 2 15 1 Constants 0 DISABLED Only base registers are supported 1 ENABLED Extended capability registers are supported User s Manual Hardware Description 91 Revision 1 0 2012 02 17 ae Leona XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers PHY Identifier 1 This is the first of two PHY identification registers containing the MSBs of a 32 bit code This code specifies the Organizationally Unique Identifier OUI and the vendor s model and revision number PHYID1 PHY Identifier 1 Offset 02 Reset Value D565 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OUI RO Field Bits Type Description OU
166. l as IEEE 802 3 2008 Table 28 2 1 AN_ADV Offset Reset Value Auto Negotiation Advertisement 04 01E1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NP RES RF TAF SF L i i i RW RO RW RW RW Field Bits Type Description NP 15 RW Next Page Next page indication is encoded in bit AN_ADV NP regardless of the selector field value or link code word encoding The PHY always advertises NP if a 1000BASE T mode is advertised during auto negotiation See also IEEE 802 3 2008 28 2 1 2 6 1 Constants 0 INACTIVE No next page s will follow 1g ACTIVE Additional next page s will follow RES 14 RO Reserved Write as zero ignore on read RF 13 RW Remote Fault The remote fault bit allows indication of a fault to the link partner See also IEEE 802 3 2008 28 2 1 2 4 1 Constants Og NONE No remote fault is indicated 1g FAULT A remote fault is indicated TAF 12 5 RW Technology Ability Field The technology ability field is an eight bit wide field containing information indicating supported technologies as defined by the following constants specific to the selector field value These bits are mapped to individual technologies such that abilities are advertised in parallel for a single selector field value In converter mode the field is always forced to value 0x60 The TAF encoding for the IEEE 802 3 selector AN ADV SF 0x1 is described in IEEE 802 3 2008 Annex 28B 2 and in Annex 28D 1 See also IEEE
167. late The isolation mode isolates the PHY from the MAC MAC interface inputs are ignored whereas MAC interface outputs are set to tristate high impedance See also IEEE 802 3 2008 22 2 4 1 6 1 Constants 0s NORMAL Normal operational mode 1g ISOLATE Isolates the PHY from the MAC ANRS 9 RWSC Restart Auto Negotiation Restarts the auto negotiation process on the MDI This bit does not take any effect when auto negotiation is disabled using CTRL ANEN Note that this bit is self clearing after the auto negotiation process is initiated See also IEEE 802 3 2008 22 2 4 1 7 1 Constants 0 NORMAL Stay in current mode 1g RESTART Restart auto negotiation DPLX 8 RW Forced Duplex Mode Note that this bit only takes effect when the auto negotiation process is disabled that is bit CTRL ANEN is set to zero This bit controls the forced duplex mode It allows forcing of the PHY into full or half duplex mode Note that this bit does not take effect in loop back mode that is when bit CTRL LB is set to one See also IEEE 802 3 2008 22 2 4 1 8 1 Constants 0s HD Half duplex 1g FD Full duplex User s Manual Hardware Description 87 Revision 1 0 2012 02 17 XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers Field Bits Type Description COL RW Collision Test Allows testing of the COL signal at the xMII interface When the collision test is enabled
168. le 22 lists the address mappings for all supported EEPROM sizes User s Manual 50 Revision 1 0 2012 02 17 Hardware Description gU L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description Table 22 Address Bit Mapping in 11 Bit Addressing Mode EEPROM Size IC Instruction Bit Memory Content Address Byte 7 6 5 4 3 2 1 7 6 5 4 3 2 1 0 1 kb 1 0 1 0 DADR 2 0 0 ADR 6 0 2 kb DADR 2 0 ADR 7 0 4 kb DADR 2 1 ADR 8 0 8 kb 2 ADR 9 0 16 kb ADR 10 0 1 DADR 2 Figure 14 shows the 3 byte frame format for a single byte write operation to a random address on the EEPROM For maximum compatibility this is the only write frame format supported Following a start bit a falling edge on SDA while SCL is active high the l C instruction is sent containing the default device address DADR 7 1 1010XXXg that is applicable to almost all EEPROM devices available The last bit in the instruction is a read write bit which is set to low to indicate a write transaction The instruction byte is followed by an acknowledgement driven by the EEPROM Following this acknowledgement the XWAY PHY11G drives the memory address byte ADR 7 0 which also needs to be acknowledged by the EEPROM The last of the three bytes in the write operation frame contains the data byte to be written DATA 7 0 After a successful write operation
169. lf nor any link partner Leaving the PD FORCE mode is only possible by setting the register MDIO STD CTRL PD 0p User s Manual 77 Revision 1 0 2012 02 17 Hardware Description fer L XWAY PHY11G PEF 7071 fes ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description 3 5 5 2 ANEG Mode In the Auto Negotiation ANEG mode the PHY tries to establish a connection to a potential link partner The PHY remains in this state for a reasonably long time until a successful link partner has been detected either through parallel detection or by an auto negotiation process itself After a successful link partner detection the PHY enters the DATA mode by performing a link up However since in most Ethernet systems the default mode is still an open port no link partner is connected the idle power consumption during ANEG mode contributes significantly to the power budget The XWAY PHY11G supports an optimized power down mode during auto negotiation Whenever no link partner is detected for a certain amount of time the PHY moves into the PD IDLE mode Chapter 3 5 5 3 It only comes back from the PD IDLE mode into the ANEG mode after a time out or whenever a signal is detected coming from the link partner Returning to ANEG mode after a time out is required to wake up link partners that use similar power saving schemes for example another XWAY PHY11G 3 5 5 3 PD IDLE Mode This is a sub state supporting power savi
170. lso IEEE 802 3 2008 40 5 1 1 register 10 in Table 40 3 1 Constants Og DISABLED Link partner is not capable of operating 1000BASE T half duplex 1 ENABLED Link partner is capable of operating 1000BASE T half duplex RES 9 8 RO Reserved Write as zero ignore on read IEC 7 0 ROSC Idle Error Count Indicates the idle error count This field contains a cumulative count of the errors detected when the receiver is receiving idles and PMA_TXMODE indicate is equal to SEND_N indicating that both local and remote receiver status have been detected to be OK The counter is incremented every symbol period that rxerror_status is equal to ERROR These bits are reset to all zeroes when the GSTAT register is read by the management function or upon execution of the PCS reset function and are to be held at all ones in case of overflow User s Manual Hardware Description 103 Revision 1 0 2012 02 17 XWAY PHY11G PEF 7071 iir Leorig Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers Reserved In IEEE 802 3 2008 this register is used for Power Sourcing Equipment PSE control functions see Reserved IEEE 802 3 2008 33 6 1 1 1 which are not supported by this PHY RES11 Offset Reset Value Reserved OB 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RES RO Field Bits Type Description RES 15 0 RO Reserved Write as zero ignored on read Reserved Reserved In IEEE 8
171. measurements The test packet is limited to layer 2 functionality with restricted configuration possibilities determined by MDIO PHY TPGCTRL The basic test packet structure is shown in Figure 38 IPGL 1 0 SIZE 2 0 Packet N 1 IPG Packet N IPG Packet N 1 7 octets Preamble 1 octet SFD 6 octets 00 03 19 FF F DA 3 0 6 octets 00 03 19 FF F SA 3 0 2 octets Length Type SIZE 2 0 Payload 64 128 256 512 1024 1518 9600 14 octets E Random DATA 7 0 TYP 2 octets FCS Figure 38 Test Packet Format 3 6 2 2 Error Counters The XWAY PHY11G incorporates a general purpose error counter accessible via the MDIO PHY ERRCNT MDIO management registers MDIO PHY ERRCNT SEL allows an error source to be selected The number of errors are counted and written to MDIO PHY ERRCNT COUNT This counter is cleared upon read access and saturates at the value MDIO PHY ERRCNT COUNT FF This prevents ambiguous monitoring results created by an overflow The error counter is only applicable to the twisted pair PHY modes User s Manual 80 Revision 1 0 2012 02 17 Hardware Description fer L XWAY PHY11G PEF 7071 Ee ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description 3 6 3 Test Loops The XWAY PHY11G supports several test loops to support system integration The individual loop back functions are covered in the following sectio
172. mory access based on MMD registers Note that this method is defined in the IEEE 802 3 standard 1 in clause 22 and Annex 22D It is used to access EEE registers as well as provide seamless access to a potentially externally connected EEPROM and to all XWAY PHY11G internal registers Note that access to internal registers is prohibited except for the special addresses defined in Chapter 5 User s Manual 58 Revision 1 0 2012 02 17 Hardware Description XWAY PHY11G PEF 7071 C Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description MDIO Address Space 00 01 024 03 04 05 06 07 08 09 OA OB 0C IEEE 802 3 Standard Registers 0D MMDCTRL OE MMDDATA OF 10 11y 124 13 14 15 16 i75 18 19 1A 1B iC dB 1E diu PHY Specific Registers 16 bit 0000 0001 0002 MMD 034 MMD 074 MMD 1E MMD 1Fy EEE Registers Aneg EEPROM Internal Registers Access Reisters MMD Address 16 bit 16 bit 00 8bit O0 8 bit Figure 24 Layout of the MDIO Address Space In order to simplify the software design the most frequently used status and control registers are placed directly in the MDIO address range using the PHY specific registers Part of the functionality for example EEE is located in the MMD address range by standard definition Some PHY specific registers are located in the user defined MMD addresses 1E and 1F An overvie
173. n modes during auto negotiation looking for a link partner Constants Og OFF ANPD is disabled 1g ON ANPD is enabled LPI RW Enable EEE Activation with Legacy MACs Enables activation of EEE when connected to a legacy MAC Constants 0 DISABLE EEE is disabled 1 ENABLE EEE is enabled User s Manual Hardware Description 115 Revision 1 0 2012 02 17 Error Counter 2 Len XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers This register controls the error counter It allows the number of errors detected in the PHY to be counted for monitoring purposes ERRCNT Error Counter Offset Reset Value 15 0000 15 14 13 11 9 8 7 6 5 4 3 2 1 0 RES SEL COUNT RO RW ROSC Field Bits Type Description RES 15 12 RO Reserved Write as zero ignored on read SEL 11 8 RW Select Error Event Configures the error event to which the error counter is sensitive Constants 0000 RXERR Receive errors are counted 0001 RXACT Receive frames are counted 0010 ESDERR ESD errors are counted 0011 SSDERR SSD errors are counted 0100 TXERR Transmit errors are counted 0101 TXACT Transmit frames events get counted 0110 COL Collision events get counted COUNT 7 0 ROSC Counter State This counter state is updated each time the selected error event has been detected The counter state is reset every time a read operation on this register is
174. nals of the GMII according to the RGMII specification The signal polarity is active high CRS DV RMII Carrier Sense and Data Valid This is the carrier sense data valid signal driven by the PHY and which is synchronous with REFCLK The signal encodes the RX DV and CRS signals of the RMII according to the RMII specification The signal polarity is active high RTBI Not Used The XWAY PHY11G drives logic zero in this mode 7 SGMII Not Used The XWAY PHY11G drives logic zero in this mode 1 RXD3 O LVTTL RGMII Receive Data Bit 3 CMOS This pin carries bit 3 of the RXD 3 0 RGMII receive data vector It is synchronous with RXC RMII Not Used The XWAY PHY11G drives logic zero in this mode RXD38 RTBI Receive Data Bits 3 and 8 This pin carries bits 3 and 8 of the double data rate RTBI receive data vector It is synchronous with RXC The bits are subject to the rising and falling edges respectively of RXC g SGMII Not Used The XWAY PHY11G drives logic zero in this mode 3 RXD2 O LVTTL RGMII Receive Data Bit 2 CMOS This pin carries bit 2 of the RXD 3 0 RGMII receive data vector It is synchronous with RXC E RMII Not Used The XWAY PHY11G drives logic zero in this mode RXD27 RTBI Receive Data Bits 2 and 7 This pin carries bits 2 and 7 of the double data rate RTBI receive data vector It is synchronous with RXC The bits are subject to the rising and falling edges respectively of RXC 7 SGMII Not Used The XWAY
175. ng 1000BASE X full duplex Constants 0 DISABLED PHY does not support this mode 1 ENABLED PHY supports this mode MBXH 14 RO 1000BASE X Half Duplex Capability Specifies whether the PHY is capable of operating 1000BASE X half duplex Constants Og DISABLED PHY does not support this mode la ENABLED PHY supports this mode MBTF 13 RO 1000BASE T Full Duplex Capability Specifies whether the PHY is capable of operating 1000BASE T full duplex Constants 0 DISABLED PHY does not support this mode 1 ENABLED PHY supports this mode MBTH 12 RO 1000BASE T Half Duplex Capability Specifies whether the PHY is capable of operating 1000BASE T full duplex Constants 0 DISABLED PHY does not support this mode 1g ENABLED PHY supports this mode RESH 11 8 RO Reserved Ignore when read RESL 7 0 RO Reserved Ignore when read User s Manual Hardware Description 107 Revision 1 0 2012 02 17 gU L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers 4 2 PHY PHY Specific Management Registers This chapter describes the PHY specific management registers Physical Layer Performance Status This register reports the PHY performance in the current mode of operation The content of this register is only valid when the link is up PHYPERF Offset Reset Value Physical Layer Performance Status 104 80FF 15 14 13 12 11 10
176. ng methodologies during auto negotiation see also Chapter 3 5 5 2 3 5 5 4 DATA Mode The DATA mode is used to establish and maintain a link connection Once this connection is dropped the PHY moves back into ANEG mode During DATA mode the PHY is linked up and data can be transmitted and received If the EEE mode Chapter 3 5 5 5 of operation has been negotiated during the ANEG mode the PHY moves into and out of the EEE mode whenever instructed to by the MAC s LPI agent 3 5 5 5 EEE Mode This is the Energy Efficient Ethernet EEE low power mode which is entered after an LPI assert command from the MAC s LPI agent More details can be found in Chapter 3 5 3 User s Manual 78 Revision 1 0 2012 02 17 Hardware Description 3 6 Lanr C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Testing Functions Functional Description This section describes the test and verification features supported for the XWAY PHY11G 3 6 1 JTAG Interface The XWAY PHY11G integrates a JTAG port according to IEEE 1149 1 8 which defines a test access port and a boundary scan architecture The JTAG interface of the XWAY PHY11G consists of a 4 pin Test Access Port TAP as specified in Chapter 2 2 6 It includes the mandatory signals TMS TCK TDI and TDO When using JTAG mode with the internal DC DC switching regulator a clock signal needs to be applied at XTAL The integrated TAP controller of
177. ng on pre defined states or events the PHY has entered into or raised Since more than one event state can be active at the same time more than one function might apply simultaneously The priority from highest to lowest is given by the order PULSE BLINKS BLINKF CON LEDOH Offset Reset Value Configuration for LED Pin 0 1F 01E2 0070 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CON BLINKF RW RW Field Bits Type Description CON 7 4 RW Constant On Configuration The Constant ON field selects in which PHY states the LED is constantly on Constants 0000 NONE LED does not light up constantly 0001 LINK10 LED is on when link is 10 Mbit s 0010 LINK100 LED is on when link is 100 Mbit s 0011 LINK10X LED is on when link is 10 100 Mbit s 0100 LINK1000 LED is on when link is 1000 Mbit s 0101 LINK10_0 LED is on when link is 10 1000 Mbit s 0110 LINK100X LED is on when link is 100 1000 Mbit s 01115LINK10XX LED is on when link is 10 100 1000 Mbit s 10005PDOWN LED is on when device is powered down 1001 EEE LED is on when device is in EEE mode 1010 ANEG LED is on when auto negotiation is running 1011 ABIST LED is on when analog self test is running 1100 CDIAG LED is on when cable diagnostics are running 1101 COPPER LED is on when the COPPER interface is selected 1110 FIBER LED is on when the FIBER or an interface other than copper is selected 1111 RESERVED Reserved for future use User s Manual 144 Revision
178. nly supported when the pad supply Vppp is nominally 3 3 V CMOS Digital CMOS 2v5 levels CMOS 2v5 buffer types according to JESD8 5 Note that this buffer is only supported when the pad supply Vppp is nominally 2 5 V Note Several pins are marked as having LVTTL CMOS buffer type This nomenclature defines that when Vppp 3 3 V the pin operates in LVTTL buffer type mode and when Vppp 2 5 V the pin operates in CMOS2v5 buffer type mode Note In CMOS mode the input pins must not be driven with LVTTL levels User s Manual 18 Revision 1 0 2012 02 17 Hardware Description 2 2 2 2 Lanr C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s General Pins This section describes the group of general pins required for the correct operation of the XWAY PHY11G including the clock reset and DC DC converter interfaces External Signals Table 3 General Pins Pin No Name Pin Buffer Function Type Type 16 RSTN LVTTL Reset CMOS Asynchronous low active reset of the device to default PU 36 XTAL1 A Crystal Mode Crystal Oscillator Pin 1 A 25 MHz crystal must be connected between XTAL1 and XTAL2 Additional load capacitances must also be used to tie both pins to GND REFCLK LVTTL Reference Mode Clock Input CMOS The clock input for the XWAY PHY11G This clock input can be PU either a 25 MHz or a 125 MHz clock The reference clock must ha
179. ns as well as how to enable and disable them 3 6 3 1 Near End Test Loops The near end test loops are used to verify system integration of an XWAY PHY11G device They allow for closed loop backs of data and signals at different OSI reference layers The following sections describe these loop backs in descending order of OSI abstraction layer 3 6 3 1 1 MAC Interface Test Loop The MAC interface test loop allows raw xMII transmit data to be looped back to the xMII receive port In the high level block diagram in Figure 39 the test loop data path is marked by the area shaded in gray This test loop can be applied to all the supported MAC interfaces described in Chapter 3 2 If required the conversion of data and control information is handled internally There are two methods for setting up this test loop The first uses the IEEE loop back setting MDIO STD CTRL LB 7 1g In this mode the MII speed must be configured manually using the MDIO STD CTRL SS speed selection bits Also the PHY is not operable towards the MDI The second method uses the MDIO PHY PHYCTLI TLOOP NETL XWAY PHY11G proprietary test loop setting The test loop is activated at the next link up to PMA PHY from PMA Figure 39 MAC Interface Near End Test Loop 3 6 3 1 2 MDI Test Loop The MDI test loop allows for loop back of the signal at the MDI connector for example RJ45 or SMB Referring to the four available twisted p
180. o effect After the AN process has been completed this register reflects the contents of the link partner s EEE advertisement register The definitions are the same as for the EEE AN advertisement register EEE_AN_LPADV Offset Reset Value EEE Auto Negotiation Link Partner 07 003D 0000 Advertisement Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EEE EEE EEE EEE EEE EEE_ 10GB 10GB 1000 10GB 1000 100B KR KX4 BKX T BT TX RO RO RO RO RO RO Field Bits Type Description EEE 10GBKR 6 RO Support of 10GBASE KR EEE Constants Og DISABLED This PHY mode is not supported for EEE 1 ENABLE This PHY mode is supported for EEE EEE 10GBKX 5 RO Support of 10GBASE KX4 EEE 4 Constants Og DISABLED This PHY mode is not supported for EEE 1 ENABLE This PHY mode is supported for EEE EEE 1000BK 4 RO Support of 1000BASE KX EEE X Constants 0 DISABLED This PHY mode is not supported for EEE 1g ENABLE This PHY mode is supported for EEE EEE 10GBT 3 RO Support of 10GBASE T EEE Constants Og DISABLED This PHY mode is not supported for EEE 1g ENABLE This PHY mode is supported for EEE EEE 1000BT 2 RO Support of 1000BASE T EEE Constants Og DISABLED This PHY mode is not supported for EEE 1g ENABLE This PHY mode is supported for EEE EEE 100BTX 1 RO Support of 100BASE TX EEE Constants 0 DISABLED This PHY mode is not supported for EEE 1 ENABLE This PHY mode is supported for EEE
181. ode 3 transmit jitter test in SLAVE mode 100 DIST Test mode 4 transmitter distortion test 101 RESDO Reserved operations not identified 110 CDIAG Cable diagnostics 111 ABIST Analog build in self test MSEN 12 RW Master Slave Manual Configuration Enable See also IEEE 802 3 2008 40 5 1 1 1 Constants 0 DISABLED Disable master slave manual configuration value 1g ENABLED Enable master slave manual configuration value MS 11 RW Master Slave Config Value Allows forcing of master or slave mode manually when AN GCTRL MSEN is set to logical one See also IEEE 802 3 2008 40 5 1 1 1 Constants Og SLAVE Configure PHY as SLAVE during master slave negotiation only when AN GCTRL MSEN is set to logical one 1 MASTER Configure PHY as MASTER during master slave negotiation only when AN GCTRL MSEN is set to logical one MSPT 10 RW Master Slave Port Type Defines whether the PHY advertises itself as a multi or single port device which in turn impacts the master slave resolution function See also IEEE 802 3 2008 40 5 1 1 1 Constants Og SPD Single port device 1g MPD Multi port device User s Manual 100 Revision 1 0 2012 02 17 Hardware Description XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers Field Bits Type Description MBTFD 9 RW 1000BASE T Full Duplex Advertises the 1000BASE T full duplex capability always forced to 1 in converte
182. ode and can be used as REFCLK 3 2 1 2 xMII Signal Conditioning To reduce the cost in materials and effort for the PCB layout the XWAY PHY11G supports extended signal conditioning on the xMII as depicted in Figure 8 The high speed MAC interface signals are internally conditioned such that only a straight strip wire is required to connect a MAC device to the XWAY PHY11G in the receive direction In particular this means that configurable series termination resistors are integrated into the driving pad Additionally the RX CLK and TX CLK pins implement an adjustable delay line that allows for skewing of the clock with respect to the data This guarantees correct data samplings in both the MAC and PHY devices For MAC devices that do not support internal signal conditioning an appropriately dimensioned series resistance needs to be included on the PCB Signal conditioning on the xMII is valid for all non SerDes interfaces such as MII GMII RGMII TBI and RTBI However the integrated delay is only intended for use with the RGMII and RTBI In all other modes the integrated ingress and egress delays are set to zero but can be modified via the MDIO interface User s Manual 32 Hardware Description Revision 1 0 2012 02 17 ro L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description Figure 8 xMII Signal Conditi
183. of the LED type used single color or bi color the LED pins can be operated in various modes Basically two major modes can be distinguished Internally Controlled Mode ICM and Externally Controlled Mode ECM In ECM the higher level management entity is able to control the LEDs via register access in the MDIO register space In ICM the XWAY PHY11G itself controls the functions of the LEDs These functions are introduced in Chapter 3 4 4 3 2 and can be configured by the higher level management entity via MDIO configuration registers as described in Chapter 3 4 4 3 3 The configuration scheme is defined such that combined and direct drive LED functionality can be set up 3 4 4 3 1 LED Externally Controlled Mode ECM In ECM the LEDs can be directly driven by register bits mapped onto the MDIO address space The higher level management entity is able to directly change the LED outputs This feature enables the higher level management entity to control the LED pins itself and the XWAY PHY11G only acts as the LED driver This mode also acts as a simple testing feature for the LEDs Note that ECM is not enabled by default and needs to be enabled in advance To enable the ECM the higher level management entity needs to set the register MDIO PHY LED LED 2 0 EN Og The LED can be illuminated by setting MDIO PHY LED LED 2 0 DA 1g 3 4 4 3 2 LED Functions in Internally Controlled Mode ICM LED functions are ac
184. oning between MAC and XWAY PHY11G 3 2 2 Reduced Media Independent Interface RMII The Reduced Media Independent Interface RMII implements a MAC interface with a reduced pin count but only supporting speeds of 10 Mbit s and 100 Mbit s If the MAC interface is configured in RMII mode then the XWAY PHY11G device does not negotiate 1000 Mbit s functionality and therefore behaves like a fast Ethernet PHY The RMII is fully compliant with the specification of the RMII consortium 11 The pin to signals mapping is defined in Table 10 As a special feature of the XWAY PHY11G the RX CLK pin drives a continuous 50 MHz clock that can be used as the reference clock CLK50 This clock is free running and not locked to the receiver clock The elastic buffering as required by 11 is performed in the PHY The RX CLK pin can be connected to the REFCLK pins of both the PHY and the MAC devices 3 2 3 Reduced Gigabit Media Independent Interface RGMII The RGMII implements a MAC interface that can be used for all supported speeds that is at 10 Mbit s 100 Mbit s and 1000 Mbit s but with a reduced pin count when compared to a GMII This interface is implemented according to the RGMIIv1 2 9 and RGMIIv2 0 10 specification and is therefore referred to as RGMII ID The mapping of standardized signals to device pins is defined in Table 4 The transfer of data between the MAC and PHY devices is handled via a clock signal a control signal and a four
185. ons In such applications removing the transformer reduces both the external bill of materials and the space requirements on the PCB As the XWAY PHY11G incorporates a novel type of voltage mode line driver the only stringent requirement is to use AC coupling AC coupling can be achieved using simple SMD type series capacitors the value of which is selected such that the high pass characteristics correspond to an equivalent transformer based standard application recommended C 100 NF The external circuitry for TLE is shown in Figure 10 Note that the RJ45 connector is shown only for illustration purposes Back plane applications use different connectors XWAY PHY11G TPIAP TPIAN TPIBP TPIBN TPICP TPICN TPIDP TPIDN UU UU 00 Figure 10 External Circuitry for the Transformerless Ethernet Application If the XWAY PHY11G is to be connected to current mode line driver based Ethernet PHYs of another vendor the circuitry for the current mode line driver must be properly selected Proper selection of transformerless external circuitry for a current mode line driver based PHY is beyond the scope of this document However Figure 11 outlines the circuitry for such a configuration In particular two separate PCB designs are shown one for each type of line driver technology only channel A for simplicity Both PCBs can be connected by means of a back plane connector The c
186. ot required for an AC coupled interface If a MAC requires this offset voltage for proper DC coupled operation this offset can be injected using the resistive dividers R4 and R5 marked by the regions shaded in light gray in the figure If the MAC is purely AC coupled these components can be omitted Also the MAC may have properly terminated inputs and therefore the termination resistors R4 are not necessary Component values for this type of circuit are defined in Table 67 The simplest circuitry is used when the XWAY PHY11G is connected to a MAC with CDR and AC coupled well terminated differential pins This configuration is shown in Figure 59 VDDP e e e d SCP Transmission SCLkP Line Impedance Y A 500 single ended A SCN 500 differential J SCLKN Y SOP Transmission SRXP Line Impedance 7 Y 500 single ended SON 500 differential o SRXN ZA SIP Transmission JsTXP Line Impedance Y p 500 single ended Z SIN 500 differential L_ STXN C Y VSSP e e e PHY optional optional optional Y MAC Figure 58 External Circuitry for SGMII Table 67 Electrical Characteristics for the SGMII External Components Parameter Symbol Values Unit Note Test Condition Min Typ Max BIAS resistance 1 Ry 10 1k 10 Q VDDP 3 3 V 10 1k 10 O VDDP 2 5 V User s Manual 179 Revision 1 0 2012 02 17
187. owing registers are identical to the Register WOLPWO defined above Table 38 Similar Registers Register Short Name Register Long Name Offset Address Reset Value WOLPW1 Wake On LAN SecureON Password Byte 1 1F 078A 0000 WOLPW2 Wake On LAN SecureON Password Byte 2 1F 078B 0000 WOLPW3 Wake On LAN SecureON Password Byte 3 1F 078C 0000 WOLPW4 Wake On LAN SecureON Password Byte 4 1F 078D 0000 WOLPW5 Wake On LAN SecureON Password Byte 5 1F 078E 0000 User s Manual 153 Revision 1 0 2012 02 17 Hardware Description gU L XWAY PHY11G PEF 7071 Ee ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MMD Registers Legacy LPI Configuration Register 2 Legacy LPI Configuration Register 2 LEG_LPI_CFG2 Offset Reset Value Legacy LPI Configuration Register 2 1F 0EB5 000E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 z IPG li RW Field Bits Type Description IPG 7 0 RW IPG Storage Length Defines the maximum IPG length to be stored in the LPI buffer Constants 00001110 DEFAULT Maximum IPG length is 14 bytes Legacy LPI Configuration Register 3 Legacy LPI Configuration Register 3 LEG LPI CFG3 Offset Reset Value Legacy LPI Configuration Register 3 1F 0EB7 0040 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IDLE RW Field Bits Type Description IDLE 7 0 RW MII IDLE Time Defines the MII IDLE time until TX LPI is indicated via MI
188. performed or the error event is changed The counter saturates at value OxFF User s Manual Hardware Description 116 Revision 1 0 2012 02 17 Sd Leona XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers EEPROM Control Register This register controls the external EEPROM via indirect accesses in the MDIO address space It can be used to perform read and write accesses to the external EEPROM connected to the PHY The actual reset value of this register depends on the soft pin strapping settings EECTRL Offset Reset Value EEPROM Control Register 16 0000 15 14 13 12 11 10 7 5 3 2 1 0 EESC CSRD EEDE ADRM AN EEAF ET T SIZE ODE DADR SPEED RDWREXEC RW ROLH ROLH ROLH RW RW RW RW RO RO Field Bits Type Description EESCAN 15 RW Enable Disable EEPROM Configuration Scan Also After SW Reset Constants Oz DISABLE EEPROM configuration scan is done only after hardware reset 1g ENABLE EEPROM configuration scan is also done after software reset EEAF 14 ROLH EEPROM Access Failure Indication Constants 0 UNDETECTED No EEPROM access error read or write has been detected 1 DETECTED An EEPROM access error read or write has been detected CSRDET 13 ROLH Configuration Signature Record Detect Indication Constants Os UNDETECTED CSR has not been found 1 DETECTED CSR has been detected EEDET 12 ROLH EEPROM Detect Indication Constants 0 UNDETECTE
189. power IDLE assert 1011 0 1 02 0E Reserved 1011 0 1 OF Carrier extend 1011 0 1 10 FE Reserved 1011 0 1 1Fy Carrier extend error 1011 0 1 20 FFy Reserved 1111 1 0 00 F Fy Transmit data frame 1110 1 1 00 F Fy Transmit error propagation Table 12 Receive Control Encoding RX_CTL GMII_RX_DV GMII_RX_ER RXD 7 0 Description PHY Status 1010 0 0 Xxx0xxx0g Normal inter frame Link down XXX1xxx1g Link up 1010 0 0 x00xx00x Normal inter frame RX_CLK 2 5 MHz x01xx01xg RX CLK 25 MHz x10xx10xg RX CLK 125 MHz X11xx11xg Reserved User s Manual 34 Revision 1 0 2012 02 17 Hardware Description ET LANTI C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description Table 12 Receive Control Encoding cont d RX CTL GMII RX DV GMII RX ER RXD 7 0 Description PHY Status 1010 0 0 OxxxOXXXg Normal inter frame Half duplex mode 1XXX1XXXp Full duplex mode 1011 0 1 00 Reserved 1011 0 1 01 Low power IDLE assert 1011 0 1 02 0D Reserved 1011 0 1 OE False carrier indication False carrier present 1011 0 1 OF Carrier extend EXTEND 1011 0 1 10 FE Reserved 1011 0 1 1F4 Carrier extend error ZERO ONE 1011 0 1 20 FE4 Reserved 1011 0 1 FF Carrier sense PLS Carrier Indicate 1111 1 0 00 F Fy Receive data frame ZERO O
190. r diagrams User s Manual 133 Revision 1 0 2012 02 17 Hardware Description Er Lanr C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MMD Registers 5 1 EEE Standard EEE Registers for MMD 0x03 This section describes the EEE registers for MMD device 0x03 EEE Control Register 1 EEE Control Register 1 EEE CTRL1 EEE Control Register 1 Offset Reset Value 03 0000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 RXCK ST RW Field Bits Type Description RXCKST 10 RW Receive Clock Stoppable The MAC can set this bit to active to allow the PHY to stop the clocking during the LPI MODE Constants Og DISABLE The PHY must not stop the xMII clock during LPI MODE 1g ENABLE The PHY can stop the xMII clock during LPI MODE User s Manual Hardware Description 134 Revision 1 0 2012 02 17 Sd Leona XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s EEE Status Register 1 EEE Status Register 1 EEE STAT1 EEE Status Register 1 15 14 13 12 11 10 MMD Registers Offset Reset Value 03 0001 0000 9 8 7 6 5 4 3 2 1 0 TXLP RXLP TXLP RXLP TXCK LRC IRC LIN IN 4 VD VD D D sT ROLH ROLH RO RO RO Field Bits Type Description TXLPI RCVD 11 ROLH TXLPI Has Been Received Constants 0s INACTIVE LPI has not been received 1g ACTIVE LPI has been received
191. r mode See also IEEE 802 3 2008 40 5 1 1 1 Constants Og DISABLED Advertise PHY as not 1000BASE T full duplex capable la ENABLED Advertise PHY as 1000BASE T full duplex capable MBTHD 8 RW 1000BASE T Half Duplex Advertises the 1000BASE T half duplex capability always forced to 1 in converter mode See also IEEE 802 3 2008 40 5 1 1 1 Constants 0 DISABLED Advertise PHY as not 1000BASE T half duplex capable 1 ENABLED Advertise PHY as 1000BASE T half duplex capable RES 7 0 RO Reserved Write as zero ignore on read User s Manual Hardware Description 101 Revision 1 0 2012 02 17 E L XWAY PHY11G PEF 7071 Ee ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers Gigabit Status Register This is the status register used to reflect the Gigabit Ethernet status of the PHY See also IEEE 802 3 2008 40 5 1 1 1 GSTAT Offset Reset Value Gigabit Status Register 0A 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSFAMSRE LRXS RRXS MBTF MBTH ULT S TAT TAT D D RES EE L i ROLH RO RO RO RO RO RO ROSC Field Bits Type Description MSFAULT 15 ROLH Master Slave Manual Configuration Fault This is a latching high bit It is cleared upon each read of GSTAT This bit will self clear on auto negotiation enable or auto negotiation complete This bit will be set to active high if the number of failed master slave resolutions reaches 7 See also IEEE 802 3 2008
192. racteristics Table 55 Receive Timing Characteristics of the RGMII cont d Parameter Symbol Values Unit Note Test Condition Min Typ Max Clock to data skew at RX ow 0 5 0 0 0 5 ns Integrated receive clock delay tip 0 0 k 0 5 3 5 ns Adjustable via MDIO register User s Manual Hardware Description 166 Revision 1 0 2012 02 17 gU L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Electrical Characteristics 6 6 8 RTBI Interface This section describes the AC characteristics of the RTBI interface at the XWAY PHY11G Unless no HSTL voltages are supported this interface conforms to the RGMII specification v1 3 and v2 0 as defined in 9 and 10 respectively The RTBI interface can operate at 1000 Mbit s 6 6 8 1 Transmit Timing Characteristics Figure 48 shows the timing diagram of the transmit RTBI interface on the XWAY PHY11G It is referred to by Table 56 which specifies the timing requirements Note that the setup and hold times are subject to the internal version of the TX CLK which is the external clock delayed by the integrated delay This delay is adjustable in steps of 0 5 ns via MDIO If the integrated delay is not used for example because it is implemented externally by PCB wire delays it must be set to zero in which case all the timings are related directly to the TX CLK on the pin tcp y tip tcu teL hi te Hr W M atpinTx CLK S NIE EN TEN
193. ram for a Random Address Single Byte Write llle 51 Figure 15 Timing Diagram for a Random Address Single Byte Read 00 0 ee 52 Figure 16 Timing Diagram for a Burst Read 0 eee 52 Figure 17 Timing Diagram for a Random Address Single Byte Write l l 53 Figure 18 Timing Diagram for a Random Address Single Byte Read lilsill leise 53 Figure 19 Timing Diagram for a BurstRead ooocccoocccco eee 54 Figure 20 Flow Chart for an Indirect EEPROM Write Cycle Via MDIO MMD Access o 55 Figure 21 Flow Chart for an Indirect EEPROM Read Cycle Via MDIO MMD Access 56 Figure 22 MDIO Write Frame 2 0 004 2 e db RR a a A 57 Figure 23 MDIO Read Frame 0 00 c lh hh hh 57 Figure 24 Layout of the MDIO Address Space oooccccocccoco eee 59 Figure 25 External Circuitry for an Active High MDINT ssssseee Rh 60 Figure 26 External Circuitry for an Active Low MDINT 0 000 002 Ie 61 Figure 27 Single Color LED External Circuitry lille RI III 62 Figure 28 Bi Color LED External Circuitry lise RR RI 63 Figure 29 External Circuitry using the Integrated Switching Regulator llle 66 Figure 30 External Circuitry without using the Integrated Switching Regulator o 68 Figure 31 Generic Schematic of the PoE PD Application llle 69 Figure 32 Generic Schematic of the PoE PSE Application
194. rance graph with typical U I characteristics of the supported LED types The tolerance values referred to by this figure are listed in Table 63 Table 63 Electrical Characteristics for Supported LEDs Parameter Symbol Values Unit Note Test Condition Min Typ Max Temperature range T 40 0 85 0 C Forward current lE 10 A V s1 4V Forward current low current LEDs 2 0 mA 14 V lt V lt 25V Forward current conventional LEDs 20 0 mA 14 V lt V lt 25V Forward voltage nominal Ve 1 6 1 9 22 V Nominal forward voltage where LED is emitting light 1 Low current LEDs are preferred in order to reduce the system power consumption User s Manual 174 Revision 1 0 2012 02 17 Hardware Description Er Lanti XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s 6 8 3 Transformer Magnetics Electrical Characteristics This section specifies the electrical characteristics of the transformer devices that are supported The specifications listed here guarantee proper operation according to IEEE 802 3 1 A typical Gigabit Ethernet capable transformer device is depicted in Figure 56 Table 64 lists the characteristics of the supported transformer devices Note that these characteristics represent the bare minimum for achieving standard performance Since the transformer significantly impacts the link performance it is possible to increase the loop reach
195. recommended by the IEEE and essentially required for the 1000BASE T mode ANEG is done after the following events Power up e Software power up MDIO STD CTRL PD 0 Hardware reset Software reset MDIO STD CTRL RST 0g Command to restart ANEG MDIO STD CTRL ANRS f1g Link down Unless otherwise configured the XWAY PHY11G carries out an auto crossover detect enable procedure prior to the start of the ANEG process This ensures optimal interoperability even in inadequate cable infrastructure environments However if ANEG is disabled the auto crossover procedure is still done during link up More details are given in Chapter 3 3 4 The implementation of the ANEG procedure is compliant with the standards given in IEEE 802 3 clause 28 1 If the link partner does not support ANEG the XWAY PHY11G extracts the link speed configuration using parallel detection Once this is detected the PHY links up at the speed of the link partner Since the duplex mode cannot be extracted during parallel detection the duplex mode is set to half duplex which also works in case the link partner operates in full duplex mode Since ANEG is a mandatory feature for 1000BASE T transceivers the XWAY PHY11G only does parallel detection for 10BASE T and 100BASE TX The default advertisements during ANEG are according to standard Chapter 3 4 specifies how these settings can be overwritten with other values The XWAY PHY11G support
196. rsion of the RX CLK The external clock on the pin is delayed by the integrated delay which is adjustable in steps of 0 5 ns via MDIO If the integrated delay is not used for example because it is implemented externally by PCB wire delays it must be set to zero in which case all the timings are related directly to the RX CLK on the pin top tskew 3 4 N t t t IB e tr 1 i tr CH BE internal RX_CLK M cu il max O external delayed RKCLK AY IN YN Y ON 209 Figure 47 Receive Timing Diagram of the RGMII Table 55 Receive Timing Characteristics of the RGMII Parameter Symbol Values Unit Note Test Condition Min Typ Max Receive clock frequency RX CLK fg cik 50 ppm 125 0 50 ppm MHz For 1000 Mbit s speed 25 0 MHz For 100 Mbit s speed 2 5 MHz For 10 Mbit s speed Receive clock period TX CLK top 7 5 8 0 8 5 ns For 1000 Mbit s speed 39 5 40 0 40 5 ns For 100 Mbit s speed 399 5 400 0 400 5 ns For 10 Mbit s speed Duty cycle top t top 45 0 50 0 55 0 Speed independent Receive clock rise time TX_CLK tr 750 0 ps 20 80 Receive clock fall time TX_CLK te 750 0 ps 80 20 User s Manual 165 Revision 1 0 2012 02 17 Hardware Description XWAY PHY11G PEF 7071 EN Lantiq Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Electrical Cha
197. rts scanning the EEPROM content for a specific signature at the beginning of the Configuration Signature Record CSR The setup of the CSR is specified in Table 20 The signature is a sequence of predefined bytes EE CO DE TF The XWAY PHY11G scans the entire EEPROM at address locations of k STEP within the range of the predefined EEPROM size see SIZE 3 0 in Chapter 3 4 1 Table 17 The STEP size is equal to SIZE 64 so that for a 1 kb EEPROM the STEP size is STEP 8 bytes If no signature is found the XWAY PHY11G aborts the search and skips any further EEPROM read operations If a signature is detected the XWAY PHY11G reads the CSR Note that the CSR contains the PHYADR that is used for MDIO communication see Chapter 3 4 3 1 The MDIO address is used only after the CSR has been successfully read by the XWAY PHY11G Before this the MDIO address is by default at logic 000005 3 4 2 3 EEPROM Content Table 20 depicts the Configuration Signature Record CSR containing the signature as well as several addresses The signature is used to identify a part of the EEPROM content to be dedicated to the XWAY PHY11G in case several different devices share the same memory The subsequent byte contains the CRID that is dedicated to a single XWAY PHY11G in case multiple XWAY PHY11G devices retrieve configuration data from the same EEPROM The subsequent fields are only evaluated if the CSR and the configuration record ID match T
198. s 0 UNFOR Unformatted page la MESSG Message page ACK2 RO Acknowledge 2 See also IEEE 802 3 2008 28 2 3 4 1 Constants Oz INACTIVE Device cannot comply with message 1g ACTIVE Device will comply with message TOGG 11 RO Toggle See also IEEE 802 3 2008 28 2 3 4 1 Constants 0 ZERO Previous value of the transmitted link code word was equal to logic ONE 1g ONE Previous value of the transmitted link code word was equal to logic ZERO MCF 10 0 RO Message or Unformatted Code Field See also IEEE 802 3 2008 28 2 3 4 1 User s Manual Hardware Description 99 Revision 1 0 2012 02 17 gU L XWAY PHY11G PEF 7071 Ee ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers Gigabit Control Register This is the control register used to configure the Gigabit Ethernet behavior of the PHY See also IEEE 802 3 2008 40 5 1 1 1 GCTRL Offset Reset Value Gigabit Control Register 094 0300 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM MsEN Ms MsPrMBTF MBTH RES l l RW RW RW RW RW RW RO Field Bits Type Description TM 15 13 RW Transmitter Test Mode This register field allows enabling of the standard transmitter test modes See also IEEE 802 3 2008 Table 40 7 1 Constants 000 NOP Normal operation 001 WAV Test mode 1 transmit waveform test 010 JITM Test mode 2 transmit jitter test in MASTER mode 011 JITS Test m
199. s 00000001 XBT_HDX Link partner advertised 10BASE T half duplex 00000010 XBT_FDX Link partner advertised 10BASE T full duplex 00000100 DBT_HDX Link partner advertised 100BASE TX half duplex 00001000 DBT_FDX Link partner advertised 100BASE TX full duplex 00010000 DBT4 Link partner advertised 100BASE T4 001000005PS SYM Link partner advertised symmetric pause 01000000 PS_ASYM Link partner advertised asymmetric pause 10000000 RES Reserved for future technologies should be zero User s Manual 95 Revision 1 0 2012 02 17 Hardware Description gU L XWAY PHY11G PEF 7071 fes ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers Field Bits Type Description SF 4 0 RO Selector Field The selector field represents one of the 32 possible messages Note that it must fit to the advertised selector field in AN_ADV SF Selector field encoding definitions are shown in IEEE 802 3 2008 Annex 28A 1 Constants 00001 IEEE802DOT3 Select the IEEE 802 3 technology User s Manual 96 Revision 1 0 2012 02 17 Hardware Description i Leona XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Auto Negotiation Expansion MDIO Registers This is the auto negotiation expansion register indicating the status of the link partner s auto negotiation See also IEEE 802 3 2008 28 2 4 1 5 AN EXP Auto Negotiation Expansion Offset Reset Value 06 0004
200. s Since WoL is a standby system feature it can happen that the residual power consumption of the XWAY PHY11G is critical Therefore it is recommended to put the PHY into a lower power state for example 10BASE T or 100BASE T before the SoC enters its power down state If the link supports EEE see also Chapter 3 5 3 this is not required since the PHY can be put into low power mode by means of an LPI assert signal Once a WoL packet is detected the XWAY PHY11G issues a wake up indication to the SoC by activating the MDINT signal see also Chapter 3 4 3 3 25 MHz 2 5 3 3 V Network Processor or SOC Transformer MAC 10 100 1000bT XWAY PHY11G A B C D E F Figure 35 Block Diagram of a WoL Application The most commonly used WoL packet is a magic packet 14 A magic packet is a deterministic packet that contains the MAC address of the device that is to be woken up A magic packet can be encapsulated into any type of higher layer protocol for example TPC IP or UDP Regardless of the higher layer protocol used the setup of the core magic packet is always the same The format of a magic packet is shown in Figure 36 for an example with a MAC address of AA BB CC DD EE FF and an optional password of 00 11 22 33 44 55 The example magic packet is shown encapsulated in the content of a conventional Ethernet MAC frame structure The magic packet itself contains of a
201. s The extended status registers are used to specify 1000 Mbit s speed capabilities in the register XSTAT See also IEEE 802 3 2008 clause 22 2 4 2 16 1 Constants 0 DISABLED No extended status information available in register 15 1 ENABLED Extended status information available in register 15 RES 7 RO Reserved Ignore when read MFPS 6 RO Management Preamble Suppression Specifies the MF preamble suppression ability See also IEEE 802 3 2008 22 2 4 2 9 1 Constants 0 DISABLED PHY requires management frames with preamble 1 ENABLED PHY accepts management frames without preamble ANOK 5 RO Auto Negotiation Completed Indicates whether the auto negotiation process is completed or in progress See also IEEE 802 3 2008 22 2 4 2 10 1 Constants Oz RUNNING Auto negotiation process is in progress 1g COMPLETED Auto negotiation process is completed RF 4 ROLH Remote Fault Indicates the detection of a remote fault event See also IEEE 802 3 2008 22 2 4 2 11 1 Constants Og INACTIVE No remote fault condition detected 1g ACTIVE Remote fault condition detected ANAB 3 RO Auto Negotiation Ability Specifies the auto negotiation ability See also IEEE 802 3 2008 22 2 4 2 12 1 Constants 0 DISABLED PHY is not able to perform auto negotiation 1 ENABLED PHY is able to perform auto negotiation User s Manual Hardware Description 90 Revision 1 0 2012 02 17 6 Lanti C XWAY PHY11G PEF 7071 Single Port Gigab
202. s Next Page NP exchange since this is mandatory for advertising 1000BASE T capabilities By default NPs are exchanged autonomously and do not require interaction with any management device If no NPs are intended to be transmitted by the management device the MDIO STD AN NPTX NP register bit should be set to logic 1p If the XWAY PHY11G is configured in a particular MAC interface mode which does not support all PHY speeds the ANEG capability registers are automatically restricted to the MAC speeds possible More details about the MAC interfaces and the supported speed modes are listed in Table 9 When the XWAY PHY11G is configured to operate with a MAC via the SGMII the SGMII also incorporates auto negotiation on the MAC to PHY interface This auto negotiation is automatically initiated by the XWAY PHY11G whenever there are link speed changes on the TPI This means that after ANEG is completed on the TPI side the link speed is advertised to the MAC via the SGMII ANEG capability 3 3 3 Auto Downspeed The Auto Downspeed ADS feature ensures maximum interoperability even in harsh or inadequate cable infrastructure environments In particular ADS is applied during 1000BASE T training This is necessary because the information available about the cabling during ANEG is insufficient It is possible to advertise 1000BASE T User s Manual 38 Revision 1 0 2012 02 17 Hardware Description gU L XWAY PHY11G PEF 7071 fe ANTIQ Single Por
203. s driven by the falling edge ofthe TX CLK The RX CTL signal is defined in the same way as TX CTL The exact encoding for TX CTL and RX CTL is depicted in Table 11 and Table 12 respectively As can be seen in Table 12 the XWAY PHY11G supports in band status via RGMII The AC characteristics of the RGMII are specified in Chapter 6 6 7 In order to simplify PCB design the XWAY PHY11G supports XMII signal conditioning between MAC and PHY as described in Chapter 3 2 1 2 The clock signals can be delayed using a programmable skew value in order to obtain a robust setup and hold the time relationships between the clock and the data control signals at the receiving pins The programmability of the skew value addresses the particularities of the given PCB environment in which the XWAY PHY11G device is embedded Supported test loops Chapter 3 6 3 can be activated at any time The speed at which the test loop operates depends on the state of the transceiver Activating a test loop during an active link implies that the currently selected link speed for example after auto negotiation Chapter 3 3 2 or auto downspeed Chapter 3 3 3 is used Otherwise the test loop is operated at the speed grade specified by the registers 0 13 and 0 6 Table11 Transmit Control Encoding TX CTL GMII TX EN GMII TX ER TXD 7 0 Description 1010 0 0 00 F Fy Normal inter frame 1011 0 1 00 Reserved 1011 0 1 01 Low
204. s of the SGMII 0020 169 Table 59 Receive Timing Characteristics of the SGMII 00 200 c eee eee 170 Table 60 Transmit Timing Characteristics of the 1000BASE X Interface 0200005 171 Table 61 Receive Timing Characteristics of the 1000BASE X 0002 eee eee ees 172 Table 62 Electrical Characteristics for Supported Crystals 020000 e eee eee 173 Table 63 Electrical Characteristics for Supported LEDs 02000 cece eee ees 174 Table 64 Electrical Characteristics for Supported Transformers Magnetics suus 175 Table 65 Electrical Characteristics for Supported RJ45 Plugs 0 000 eee eee ee eae 177 Table 66 Electrical Characteristics for supported Transformers Magnetics o oooooooo 178 Table 67 Electrical Characteristics for the SGMII External Components 2 2005 179 Table 68 Electrical Characteristics for the 1000BASE X External Components 181 User s Manual 11 Revision 1 0 2012 02 17 Hardware Description gU L XWAY PHY11G PEF 7071 fes ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Introduction 1 Introduction This document specifies the functionality of the Lantiq XWAY PHY11G Version 1 5 Gigabit Ethernet GbE transceiver integrated circuit It describes all aspects required for the development of systems based on XWAY PHY11G technology 1 1 About X
205. s the time between releasing the LPI request on the MII until the first data is transmitted via MII for the 1000BASE T mode The time is calculated as HOLDOFF 1000BT 1 x 16 x 8 ns Constants 10000000 DEFAULT 16 51 us User s Manual Hardware Description 150 Revision 1 0 2012 02 17 ET Lanr C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Wake On LAN Control Register Wake On LAN Control Register WOLCTRL Wake On LAN Control Register MMD Registers Offset Reset Value 1F 0781 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPWD _EN RES EN RW RO RW Field Bits Type Description SPWD EN 2 RW Secure ON Password Enable If enabled checks for the Secure ON password after the 16 MAC address repetitions Constants 0 DISABLED Secure On password check is disabled 1g ENABLED Secure On password check is enabled RES 1 RO Reserved Must always be written to zero EN 0 RW Enables the Wake On LAN functionality If Wake On LAN is enabled the PHY scans for the configured magic packet and indicates its reception via the register bit ISTAT WOL and optionally also via interrupt Constants 0 DISABLED Wake On LAN functionality is disabled 1g ENABLED Wake On LAN functionality is enabled User s Manual Hardware Description 151 Revision 1 0 2012 02 17 gU L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 10
206. sed at 400 kHz 10 FRQ_1_0MHZ EEPROM is accessed at 1 MHz 11 FRQ 3 4MHZ EEPROM is accesses at 3 4 MHz RDWR RO EEPROM Read Write Control Constants Og READ Read access to the external EEPROM 1g WRITE Write access to the external EEPROM EXEC RO Execute EEPROM Read Write Control This register is used to initiate an external EEPROM access The bit remains set until the access is completed Constants Oz IDLE No access to the external EEPROM is currently pending 1g EXECUTE Access to the external EEPROM is currently pending User s Manual Hardware Description 118 Revision 1 0 2012 02 17 gU L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers Media Independent Interface Control This register controls the MII interface in its various operational modes MIICTRL Offset Reset Value Media Independent Interface Control 17 8000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 iri RXSKEW e TXSKEW CRS FLOW MODE L l l l l l RW RW RW RW RW RW RW Field Bits Type Description RXCOFF 15 RW Receive Clock Control Allows disabling of the RXCLK Constants Og OFF RXCLK is inactive when link is down lg ON RXCLK is active also then link is down RXSKEW 14 12 RW Receive Timing Skew RGMII Defines the receive timing skew in the RGMII mode using the integrated delay generation on RX CLK Note that this register is subject to d
207. serving the PHY EECTRL EXEC bit After this the read byte can be loaded from STD MMDDATA Note that it would make sense to check on the availability of an external EEPROM using the PHY EECTRL EEDET bit This is set to active when an external EEPROM has been detected by the XWAY PHY11G User s Manual 54 Revision 1 0 2012 02 17 Hardware Description fer L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description PHY EECTRL EXEC 18 STD MMDCTRL ACTYPE 0 STD MMDCTRL DEVAD 1Ex STD MMDDATA ADR STD MMDCTRL ACTYPE 1 STD MMDDATA WRD Figure 20 Flow Chart for an Indirect EEPROM Write Cycle Via MDIO MMD Access User s Manual 55 Revision 1 0 2012 02 17 Hardware Description XWAY PHY11G PEF 7071 Functional Description Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s ir Leona PHY EECTRL EXEC 18 Y STD MMDCTRL ACTYPE 0 STD MMDCTRL DEVAD 1EH STD MMDDATA ADR STD MMDCTRLACTYPE 1 PHY EECTRL EXEC 718 no Y RDD STD_MMDDATA Flow Chart for an Indirect EEPROM Read Cycle Via MDIO MMD Access Figure 21 Revision 1 0 2012 02 17 56 User s Manual Hardware Description ral XWAY PHY11G PEF 7071 E LANTIC Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description 3 4 3 Configuration and Control V
208. set internally after each successful 1000BASE T link up In all flow and mode settings that support only speeds of 1000 Mbit s the ADS feature is automatically disabled 3 3 4 Auto Crossover and Polarity Reversal Correction In order to maximize interoperability even in inadequate wiring environments the XWAY PHY11G supports auto crossover and polarity reversal detection and correction Both features are enabled by default Auto crossover detection and correction operates at all supported twisted pair speeds The supported pair mappings detectable and correctable by the device are listed in Table 13 However in 10BASE T and 100BASE TX pairs C and D are not used Consequently mode 2 and 3 as well as 1 and 4 are identical However in 1000BASE T all modes are applicable The auto crossover functionality is fully compliant with IEEE 802 3 1 clause 40 4 4 in 1000BASE T mode In the 10BASE T and 100BASE TX modes this functionality depends on the detection of valid link pulses Table 13 Supported Twisted Pair Mappings Crossover Modes on a RJ45 RJ45 Pinning Description 1 2 3 4 5 6 7 8 1 Normal straight CAT5 cable TPIAP TPIAN TPIBP TPICP TPICN TPIBN TPIDP TPIDN A A B C C B D D 2 Fast Ethernet only MDI X TPIBP TPIBN TPIAP TPICP TPICN TPIAN TPIDP TPIDN B B A C C A D D 3 Full Gigabit Ethernet MDI X TPIBP TPIBN TPIAP TPIDP TPIDN TPIAN TPICP
209. sical Coding Sublayer PCS is integrated as defined in IEEE 802 3 clause 36 1 This is because the RTBI interface is not a real MAC interface but already encoded data Therefore the XWAY PHY11G integrates this PCS module in order to convert the TBl based signals back to an on chip GMII interface which is a defined interface for the copper media PHY The auto negotiation of the MAC communicates with the intermediate PCS module instead of with the link partner This scenario is similar to a GBIC application The XWAY PHY11G performs auto negotiation on both sides and ensures that important information is passed to either side for example pause duplex mode In RTBI mode the speed is naturally fixed to 1000 Mbit s Hence the auto negotiation functionality of the PHY is forced to this speed for the copper media The same concept as described for copper is also used for fiber The XWAY PHY11G operates the intermediate PCS in a manner that is transparent to the MAC 1 HSTL logic drivers are not supported Instead standard LVTTL drivers are used User s Manual 35 Revision 1 0 2012 02 17 Hardware Description fer L XWAY PHY11G PEF 7071 fe ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description The AC characteristics of the RTBI are described in Chapter 6 6 8 In order to simplify PCB design the XWAY PHY11G supports XMII signal conditioning between MAC and PHY as described in Chapter 3 2 1 2 The
210. sked out 1g X ACTIVE Interrupt is activated NPTX 12 RW Next Page Transmitted Mask When active MDINT is activated upon transmission of the currently stored next page in STD AN NPTX Constants Og INACTIVE Interrupt is masked out 1 ACTIVE Interrupt is activated ANE 11 RW Auto Negotiation Error Mask When active MDINT is activated upon detection of an auto negotiation error Constants Og INACTIVE Interrupt is masked out 1 ACTIVE Interrupt is activated User s Manual Hardware Description 122 Revision 1 0 2012 02 17 amp Lanr C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers Field Bits Type Description ANC 10 RW Auto Negotiation Complete Mask When active MDINT is activated upon completion of the auto negotiation process Constants Og INACTIVE Interrupt is masked out 1g X ACTIVE Interrupt is activated RESH 9 8 RO Reserved Write as zeroes ignore on read RESL T 6 RO Reserved Write as zeroes ignore on read ADSC RW Link Speed Auto Downspeed Detect Mask When active MDINT is activated upon detection of a link speed auto downspeed event Constants 0 INACTIVE Interrupt is masked out 1g ACTIVE Interrupt is activated MDIPC RW MDI Polarity Change Detect Mask When active MDINT is activated upon detection of an MDI polarity change event Cons
211. sponds to a read access Following acknowledgement of the read request the EEPROM drives the desired read data byte DATA 7 0 For a single read operation the XWAY PHY11G does not acknowledge this byte indicating that no further read is required The read access is completed by the XWAY PHY11G driving the stop bit to SDA DUMMY WRITE TO ADR READ INSTR INSTR DADR 7 1 ADR 15 8 ADR 7 0 DADR 7 1 DATA 7 0 Figure 18 Timing Diagram for a Random Address Single Byte Read User s Manual 53 Revision 1 0 2012 02 17 Hardware Description fer L XWAY PHY11G PEF 7071 ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description A single byte random read as depicted in Figure 18 can easily be extended to a burst read Figure 19 shows the supported burst read frame structure Note that the initialization of a burst read access is the same as for a single byte read Therefore the figure only shows the protocol sequence starting from the read instruction Subsequent bytes are read from incrementing address locations for as long as the XWAY PHY11G keeps acknowledging the read bytes driven by the EEPROM The burst read access stops when the XWAY PHY11G does not acknowledge a read byte and instead issues the stop bit The XWAY PHY11G uses the burst read operation only for the external firmware load feature Normal configuration EEPROM access operations are done using single byte
212. ssed wordwise User s Manual Hardware Description 85 Revision 1 0 2012 02 17 gU L XWAY PHY11G PEF 7071 fe ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers 4 1 STD Standard Management Registers This section describes the IEEE 802 3 standard management registers Control This register controls the main functions of the PHY See also IEEE 802 3 2008 22 2 4 1 1 CTRL Offset Reset Value Control 00 9040 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RST LB SSL ANEN PD ISOL ANRS DPLX COL SSM RES RWSC RW RW RW RW RW RWSC RW RW RW RO Field Bits Type Description RST 15 RWSC Reset Resets the PHY to its default state Active links are terminated Note that this is a self clearing bit which is set to zero by the hardware after reset has been done See also IEEE 802 3 2008 22 2 4 1 1 1 Constants 0s NORMAL Normal operational mode 1g RESET Resets the device LB 14 RW Loop Back This mode enables looping back of MII data from the transmit to the receive direction No data is transmitted to the medium via MDI The device operates at the selected speed The collision signal remains de asserted unless otherwise forced by the collision test See also IEEE 802 8 2008 22 2 4 1 2 1 Constants Oz NORMAL Normal operational mode 1g ENABLE Closes the loop back from TX to RX at xMII SSL 13 RW Forced Speed Selection LSB Note that this bit only
213. stics The following sections describe the DC characteristics of the XWAY PHY11G external interfaces 6 5 1 Digital Interfaces This section describes the DC characteristics of the digital interfaces 6 5 1 1 GPIO Interfaces This chapter defines the DC characteristics of the GPIO Interface consisting of the following interfaces MDIO MDC MDIO EEPROM II C SCL SDA Management interrupt MDINT Clock outputs CLKOUT Chipreset RSTN The DC characteristics for Vppp 2 5 V are summarized in Table 41 The DC characteristics for Vppp 3 3 V are summarized in Table 42 Table41 DC Characteristics of the GPIO Interfaces VDDP 2 5 V Parameter Symbol Values Unit Note Min Typ Max Test Condition Input high voltage Vin 1 8 Vppp 0 5 V Input low voltage Vi 0 7 V Output high voltage Vou 2 0 m V lon 4 mA Output low voltage VoL 0 4 V lo 4 mA Table 42 DC Characteristics of the GPIO Interfaces VDDP 3 3 V Parameter Symbol Values Unit Note Min Typ Max Test Condition Input high voltage Vin 2 3 Vppp 0 5 V Input low voltage Vi 0 7 V Output high voltage Vou 2 7 V lon 4 mA Output low voltage VoL 0 4 V lo 4 mA User s Manual 157 Revision 1 0 2012 02 17 Hardware Description gU L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Electrical Characterist
214. symbol of the XWAY PHY11G MDC MDIO MDINT LED 2 0 SCL SDA Config Control amp Status TX CLK TX CTL RX CLK RX CTL TXD 3 0 RXD 3 0 MAC PHY Data Interfaces RGMII RTBI SGMII Reset amp Clock XWAY PHY11G PEF 7071 JTAG TPIAP TPIAN TPIBP TPIBN TPICP TPICN TPIDP TPIDN Twisted Pair Interface Figure 1 Logic Symbol of the XWAY PHY11G User s Manual Hardware Description 13 Revision 1 0 2012 02 17 gU L XWAY PHY11G PEF 7071 fes ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Introduction 1 2 2 Features This section outlines the features of the XWAY PHY11G Version 1 5 General Flexible power supply Vppy 2 5 V 3 3 V Single power supply optionally using the integrated DC DC converter Low power consumption of 400 mW in Gigabit Ethernet mode e Configurable startup mode using sophisticated pin strappings Flexible architecture using an integrated device controller Interfaces Twisted pair interface 10BASE T e 100BASE TX 1000BASE T Support of Power over Ethernet PoE see Chapter 3 5 2 Support of transformerless Ethernet for backplane applications Data interfaces xMII1 RMII RGMII RTBI SGMII 1000BASE X SerDes at 1 25 Gbaud Jumbo packets of up to 10 kB e Control interfaces MDIO JTAG interface for boundary scan Support of stand alone operational mode using
215. symbol periods User s Manual Hardware Description 111 Revision 1 0 2012 02 17 amp Lanti C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Physical Layer Control 1 MDIO Registers This register controls the PHY functions PHYCTL1 Physical Layer Control 1 15 14 13 12 11 Offset Reset Value 13 0001 10 9 8 7 6 5 4 3 2 1 0 TLOOP TXOF TXADJ POLD POLC POLB POLA MDIC MDIA TXEE AMDI D B E10 X RW RW RW RW RW RW RW RW RW RW RW Field Bits Type Description TLOOP 15 13 RW Test Loop Configures predefined test loops Constants 000g OFF Test loops are switched off normal operation 001 NETL Near end test loop 010 FETL Far end test loop 011 ECHO Echo test loop 100 RJTL RL45 connector test loop TXOFF 12 RW Transmitter Off This register bit allows turning off of the transmitter This feature might be useful for return loss measurements Constants Og ON Transmitter is on lg OFF Transmitter is off TXADJ 11 8 RW Transmit Level Adjustment Transmit level adjustment can be used to fine tune the transmit amplitude of the PHY The amplitude adjustment is valid for all supported speed modes The adjustment is performed in digits One digit represents 3 125 percent of the nominal amplitude The scaling factor is gain 1 sighned TXADJ 2 7
216. t Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description during ANEG even though it might happen that both link partners are connected via a CAT 3 cable which does not support the 4 pair Gigabit Ethernet mode In order to avoid continuous link up failures in such a situation the XWAY PHY11G operates a detection algorithm to identify this situation As a consequence Gigabit capability indication is cleared from the ANEG registers After the resulting link down the next ANEG process does not advertise 1000BASE T anymore such that even when the link partner does not implement this kind of ADS algorithm the next link up will be done at the next advertised speed below 1000 Mbit s It can also happen that the existing cable infrastructure is adequate but that the integrity of received signals is not suitable for a 1000BASE T link up for example due to increased alien noise or over length cables If such a condition is detected the XWAY PHY11G also does an ADS procedure Finally it can also happen that even though the XWAY PHY11G is able to link up properly for example in slave mode the link partner is not able to In this situation ADS criterion described previously does not become active but the link also never comes up In order to address this corner situation the XWAY PHY11G counts the number of attempts to link up to 1000BASE T If this number is greater than 3 the ADS procedure is carried out This number is re
217. tants Og INACTIVE Interrupt is masked out 1g ACTIVE Interrupt is activated MDIXC RW MDIX Change Detect Mask When active MDINT is activated upon detection of an MDI MDIX cross over change event Constants Og INACTIVE Interrupt is masked out 1g X ACTIVE Interrupt is activated DXMC RW Duplex Mode Change Mask When active MDINT is activated upon detection of full or half duplex change Constants Og INACTIVE Interrupt is masked out 1g ACTIVE Interrupt is activated LSPC RW Link Speed Change Mask When active MDINT is activated upon detection of link speed change Constants Og INACTIVE Interrupt is masked out 1 ACTIVE Interrupt is activated LSTC RW Link State Change Mask When active MDINT is activated upon detection of link status change Constants Og INACTIVE Interrupt is masked out 1g ACTIVE Interrupt is activated User s Manual Hardware Description 123 Revision 1 0 2012 02 17 gU L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers Interrupt Status Register This register defines the Interrupt Status Register ISTAT Each masked interrupt IMASK is able to activate the MDINT pin to the management device The information about the interrupt source can be extracted by reading the ISTA register A read operation on the ISTAT register simultaneously clears the interrupts and this deactivates MDINT IS
218. tem Life support devices or systems are intended to be implanted in the human body or to support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered gU L XWAY PHY11G PEF 7071 fe ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s XWAY PHY11G Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Revision History 2012 02 17 Revision 1 0 Previous Revision none Page Subjects major changes since last revision Trademarks of Lantiq CONVERGATE COSIC DUALFALC DUSLIC ELIC EPIC FALC GEMINAX ISAC IWORX OCTALFALC OCTAT QUADFALC SCOUT SEROCCO SICOFI SLIC SMINT SOCRATES VINAX VINETIC XWAY Other Trademarks ARM Bluetooth of Bluetooth SIG Inc CAT iq of DECT Forum EPCOS of Epcos AG HYPERTERMINAL of Hilgraeve Incorporated IEC of Commission Electrotechnique Internationale IrDA of Infrared Data Association Corporation ISO of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION MATLAB of MathWorks Inc NUCLEUS of Mentor Graphics Corporation MIPS of MIPS Technologies Inc USA muRata of MURATA MANUFACTURING CO SOLARIS of Sun Microsystems Inc Samtec of Samtec Inc TEAKLITE of CEVA Inc TEKTRONIX of Tektronix Inc UNIX of X Open Company Limited VERILOG
219. ter operable with all types of management device IC the MDINT pin of the XWAY PHY11G is in tristate when inactive The active level of the MDINT pin can be customized by means of an external pull up or pull down resistor If the MDINT polarity is active high an external pull down resistor must be connected to ground Otherwise if the MDINT polarity is active low an external pull up resistor must be connected to VDDP After reset of the XWAY PHY11G the MDINT is tristated by default During this time period the XWAY PHY11G detects the target polarity of the MDINT by reading out the pull up down resistor The external circuitry for the MDINT pin in an active high and active low state is depicted in Figure 25 and Figure 26 respectively read polarity after reset drive polarity when active gt MDINT to Management Device enable driver when active Figure 25 External Circuitry for an Active High MDINT User s Manual 60 Revision 1 0 2012 02 17 Hardware Description XWAY PHY11G PEF 7071 Functional Description Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s gt MDINT to Management Device read polarity after reset drive polarity when active enable driver when active Figure 26 External Circuitry for an Active Low MDINT 61 User s Manual Hardware Description Revision 1 0 2012 02 17 fer L XWAY PHY11G PEF 7071 fe ANTIQ Single Port Gigabit Ethernet
220. ternal pull up resistor of the MDIO pin on the XWAY PHY11G pulls the MDIO signal to logic one PRE Preamble The preamble is defined as a sequence of logic ones Since this field of the frame is optional the XWAY PHY11G does not require a preamble to be inserted If inserted it can be of arbitrary length ST Start of Frame The ST field is required to determine a new frame start by means of a two bit logic 015 pattern OP Operation Code The operation code field indicates a read or write operation to the PHY by means of a two bit logic 105 or 015 pattern respectively PHYAD Physical Layer Address The physical layer address field is used by the higher level management entity to select one out of a maximum of 32 PHY devices Each PHY needs to have a priori knowledge about its address Chapter 3 4 1 describes how this address can be configured to an XWAY PHY11G device REGAD Register Address This field represents a vector of five bits which define the register address for one out of 32 registers in the MDIO address space In the XWAY PHY11G this address space covers the standard IEEE 802 3 1 registers plus extended and custom registers Chapter 4 describes all register configurations TA Turnaround The turnaround is a two bit time field that separates the DATA field from the others to avoid contention during read operations During read transactions the time of the first bit is used to ensure that bot
221. test loop can be applied to all the supported MAC interfaces described in Chapter 3 2 The test is also applicable to all supported types of MDI physical layer standards as described in Chapter 3 3 This test loop is activated by setting the bit MDIO PHY PHYCTL1 TLOOP FETL Note that the test loop is only operable when the link is operational It is activated at the next link up User s Manual 82 Revision 1 0 2012 02 17 Hardware Description XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description RJ45 Connector Figure 42 PCS Far End Test Loop User s Manual Hardware Description 83 Revision 1 0 2012 02 17 aF XWAY PHY11G PEF 7071 E LANTIC Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s MDIO Registers 4 MDIO Registers This chapter defines all the MDIO registers needed to operate the XWAY PHY11G Table 32 Registers Address Space Module Base Address End Address Note MDIO Registers 00 1F Addresses are word aligned Table 33 Registers Overview Register Short Name Register Long Name Offset Address Page Number STD CTRL Control 00 86 STAT Status Register 01 89 PHYID1 PHY Identifier 1 024 92 PHYID2 PHY Identifier 2 03 92 AN ADV Auto Negotiation Advertisement 04 93 AN LPA Auto Negotiation
222. this byte is acknowledged by the EEPROM and the XWAY PHY11G ends the write operation frame with a stop bit In accordance with 1 C this stop bit is a rising edge on SDA while SCL is active high Table 22 showed how some devices exceed the address byte and therefore have to use parts of the device address This is indicated in Figure 14 by showing the assignment of the ADR 10 8 bits INSTR DADR 7 1 ADR 7 0 DATA 7 0 a ADR 10 8 Figure 14 Timing Diagram for a Random Address Single Byte Write Figure 15 shows a read frame similar to the write frame operation illustrated in Figure 14 In general a read frame starts with a dummy write frame which lasts up to the write address This is required to set the current address on the EEPROM After acknowledgement of the address byte ADR 7 0 the XWAY PHY11G terminates the current dummy write by setting a new start bit The instruction byte is repeated except that the read write bit is now set to active high to indicate that this instruction corresponds to a read access Following acknowledgement of the read request the EEPROM drives the desired read data byte DATA 7 0 For a single read operation the XWAY PHY11G does not acknowledge this byte indicating that no further read is required The read access is completed by the XWAY PHY11G driving the stop bit to SDA User s Manual 51 Revision 1 0 2012 02 17 Hardware Description E L XWAY PHY11G PEF 7071 Ee ANTIQ
223. tics of the RGMII Parameter Symbol Values Unit Note Test Condition Min Typ Max Transmit clock frequency TX CLK fr cik 50 ppm 125 0 50 ppm MHz For 1000 Mbit s speed 25 0 MHz For 100 Mbit s speed 2 5 MHz For 10 Mbit s speed Transmit clock period TX CLK tcp 7 2 8 0 8 8 ns For 1000 Mbit s speed 36 0 40 0 44 0 ns For 100 Mbit s speed 360 0 400 0 440 0 ns For 10 Mbit s speed Duty cycle tutor t tcp 45 0 50 0 55 01 Speed independent Transmit clock rise time TX CLK tr 750 0 ps 20 gt 80 Transmit clock fall time TX_CLK tr 750 0 ps 80 gt 20 Setup time to 7 internal TX_CLK ts 1 0 ns User s Manual 164 Revision 1 0 2012 02 17 Hardware Description gU L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Electrical Characteristics Table 54 Transmit Timing Characteristics of the RGMII cont d Parameter Symbol Values Unit Note Test Condition Min Typ Max Hold time to 1 internal TX CLK ty 1 0 ns Integrated transmit clock delay tip 0 0 k 0 5 3 5 ns Adjustable via MDIO register 6 6 7 2 Receive Timing Characteristics Figure 47 shows the timing diagram of the receive RGMII interface on the XWAY PHY11G It is referred to by Table 55 which specifies the timing requirements Note that the clock to data skew time is subject to the internal ve
224. tion Min Typ Max DC DC spike filter resistance Rpcpc 5 0 Q DC DC spike filter capacitance Cpcpc2 333 0 pF Revision 1 0 2012 02 17 67 User s Manual Hardware Description E L XWAY PHY11G PEF 7071 fe ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description 3 5 1 2 Power Supply Without Using Integrated Switching Regulator When the integrated DC DC switching regulator is not used for example when both power supply voltages are already available in the system the XWAY PHY11G can be powered by a dual power supply as shown in Figure 30 The electrical characteristics of the power supply are defined in Chapter 6 2 VDDH VDDP VDDR VDDL VDDC REGO Short to VDDR Vop 1 0 V Vpp72 5 3 3 V vss Figure 30 External Circuitry without using the Integrated Switching Regulator In external supply mode the integrated DC DC is internally switched off as the XWAY PHY11G automatically detects whenever the switching regulator output pin is shorted to VDDR In this case neither additional pin strappings nor register settings are required Note that Figure 30 is only a generic schematic and does not show power supply blocking for reasons of simplicity 3 5 2 Power Over Ethernet PoE Power Over Ethernet PoE is a standardized method described in IEEE 802 3af and in particular in IEEE 802 3 clause 33 1 for remotely powering devices v
225. tivities to be applied to the LED pins according to a given configuration These activities are applied in a given priority It is possible to map multiple activities to the same LED pin in order to be able to multiplex different types information The configuration of these LED functions is described in Chapter 3 4 4 3 3 There are two types of LED function direct and complex LED functions Direct LED functions can be applied to a single LED whereas complex LED functions use the context of all LEDs Table 26 lists all the supported direct LED functions and their associated priorities when compared with each other Table 27 lists all the supported User s Manual 63 Revision 1 0 2012 02 17 Hardware Description gU L XWAY PHY11G PEF 7071 ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description complex LED functions and their priorities when compared to each other The complex LED functions have a higher priority than that of the direct LED functions Table 26 Direct LED Functions Function Priority Description PULSE 1 The LED is switched on off shortly in reaction to a certain event or state transition high The corresponding ON and OFF time is determined by the pulse stretching configuration Note that each new event will cause an ON OFF sequence unless if this event happens during a running PULSE function The ON OFF sequence is necessary to make the PULSE function visible on LEDs which already in
226. to IEEE 1149 1 with components not following this standard BYPASS 1111 11115 Bypass Bypasses the integrated TAP controller by connecting TDI to TDO via a single register i e with one TCK period delay RESERVED Remaining As specified in Table 30 the IDCODE instruction returns the device ID on the TDO pin The encoding of this device ID is given in Table 31 Table31 JTAG Boundary Scan ID Description Device Version 31 28 Device Code 27 12 Manufacture Code 11 1 Mandatory LSB Value 0001 0000 0001 11001100 0000 1000 001 1p User s Manual 79 Revision 1 0 2012 02 17 Hardware Description gU L XWAY PHY11G PEF 7071 ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description 3 6 2 Payload Data Tests This chapter specifies several payload data test features that are integrated in the XWAY PHY11G 3 6 2 1 Test Packet Generator TPG The integrated Test Packet Generator TPG allows for test packets to be sent even when no MAC is connected to the MII or when the connected MAC is inactive This is done by multiplexing the TPG output into the transmit data path of the MAC interface The TPG is controlled by MDIO PHY TPGCTRL and MDIO PHY TPGDATA refer to Test Packet Generator Control and Test Packet Generator Data It can be effectively used in the following applications e Electrical characteristics test for 1OBASE T and 100BASE TX BER
227. ubject to REFCLK ty 2 00 ns User s Manual 163 Revision 1 0 2012 02 17 Hardware Description fer L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Electrical Characteristics 6 6 7 RGMII Interface This section describes the AC characteristics of the RGMII interface on the XWAY PHY11G Unless no HSTL voltages are supported this interface conforms to the RGMII specification v1 3 and v2 0 as defined in 9 and 10 respectively The RGMII interface can operate at speeds of 10 Mbit s 100 Mbit s and 1000 Mbit s 6 6 7 1 Transmit Timing Characteristics Figure 46 shows the timing diagram of the transmit RGMII interface on the XWAY PHY11G It is referred to by Table 54 which specifies the timing requirements Note that the setup and hold times are subject to the internal version of the TX CLK which is the external clock delayed by the integrated delay The delay is adjustable in steps of 0 5 ns via MDIO If the integrated delay is not used for example because it is implemented externally by PCB wire delays it must be set to zero in which case all the timings are related directly to the TX CLK on the pin tcp 4 tip tcH teL y tr Hr 4 x at pin TX CLK JN TEEN TEN vm internal delayed TXCLK A YN YN NS TXD 3 0 TX_CTL Figure 46 Transmit Timing Diagram of the RGMII Table 54 Transmit Timing Characteris
228. urrent mode line driver must provide a current sinking voltage source in addition to AC coupling User s Manual 40 Revision 1 0 2012 02 17 Hardware Description ral XWAY PHY11G PEF 7071 E LANTIC Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description Current Mode Backplane O o oO c c o o 3 party PHY Figure 11 External Circuitry for TLE when Connected to Current Mode Line Driver Based PHY User s Manual 41 Revision 1 0 2012 02 17 Hardware Description fer L XWAY PHY11G PEF 7071 ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description 3 4 Configuration Control and Status Functions This chapter investigates control and configuration of the XWAY PHY11G It distinguishes between control and configuration operations Configuration of the device can be done either via pin strappings Chapter 3 4 1 or via configuration content on an external EEPROM Chapter 3 4 2 Configuration and control can be done using the MDIO interface Chapter 3 4 3 1 according to IEEE 802 3 1 Furthermore the chapter outlines how status information can be extracted from the XWAY PHY11G either using the LED pins Chapter 3 4 4 or by using a higher level management entity on the MDIO interface together with an external interrupt Chapter 3 4 3 3 Figure 12 illustrates the configuration flow in the form of a flow chart Note th
229. used for saving energy depends on the PHY speed this section is divided into 3 subsections corresponding to the various speeds of 10BASE Te 100BASE TX and 1000BASE T Except for 10BASE Te the general idea of EEE is to save power during periods of low link utilization Instead of sending an active idle the transmitters are switched off for a short period of time 20 ms The link is kept active by means of a frequent refresh cycle initiated by the PHY itself during low power mode This sequence is repeated until a wake request is generated by one of the link partners MACs An EEE compliant MAC must grant the PHY a time budget of wake time before the first packet is transmitted The basic principle is shown in Figure 33 User s Manual 71 Revision 1 0 2012 02 17 Hardware Description ro L XWAY PHY11G PEF 7071 fe ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description Active Low Power Idle Active Ts Tg Tr Figure 33 EEE Low Power Idle Sequence 3 5 3 1 EEE for 10BASE Te 10BASE Te is a fully inter operable version of the legacy 10BASE T It is optimized for CAT5 and better cabling infrastructure Since these cables have better insertion loss properties the amplitude of 1OBASE T can be reduced thus saving on energy Specifically the 10BASE Te transmission amplitude has been reduced to the range of 1 54 V 1 92 V instead of 2 2 V 2 8 V for 10BASE T The 10BASE Te mode can be activated us
230. ve a frequency accuracy of 50 ppm The device automatically detects the frequency and adjusts its internal PLL accordingly 37 XTAL2 O A Crystal Mode Crystal Oscillator Pin 2 See XTAL1 XTAL2 Reference Mode Not used Must be left unconnected in this mode 46 CLKOUT O LVTTL NORMAL Clock Output CMOS After de assertion of the reset signal RSTN this pin outputs a clock signal that can have a frequency of either 25 MHz or 125 MHz The frequency is selected via the CLKSEL field in the Physical Layer Control 2 MDIO register default 25 MHz 39 REGO O A Integrated DC DC Regulator Output Provides a current output to self supply the 1 0 V domains Vppc Vop of the XWAY PHY11G from the Vppr supply User s Manual Hardware Description 19 Revision 1 0 2012 02 17 2 2 3 2 Len C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s External Signals Media Dependent Interface MDI Pins This section describes the twisted pair Media Dependent Interface MDI which directly connects to the transformer device No external termination resistors are required Table 4 Twisted Pair Interface Pins Pin No Name Pin Buffer Function Type Type 26 TPIAP 1 0 A Differential Tx Rx Port for Twisted Pair A 27 TPIAN This is the twisted pair port A that can be directly connected to the corresponding transformer pins Note This port has a 100 Q nominal impedance due
231. w of all pages is listed in Table 25 Table25 MDIO Indirect MMD Device Address Overview MMD MMD Name Description 00 02 Unused 03 EEE Contains some standard registers required for EEE operation 04 06 Unused 07 ANEG Contains some standard registers required for EEE auto negotiation operation 04 06 Unused 1E EEPROM Allows seamless indirect access to externally connected if present EEPROM 1F Internal Allows seamless indirect access to PHY internal registers User s Manual Hardware Description 59 Revision 1 0 2012 02 17 gU L XWAY PHY11G PEF 7071 ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description 3 4 3 3 MDIO Interrupt The XWAY PHY11G allows for an interrupt to be driven to the management device This interrupt is named MDINT and can be used by the management device to get notification of pre configured events These events can be configured in the MDIO register MDIO PHY IMASK see also Chapter 4 which allows for a mask to be set onto the event vector that can cause the MDIO interrupt to be asserted The actual interrupt status is reported in the MDIO register MDIO PHY ISTAT Note that without any active mask bit in MDIO PHY IMASK the PHY will issue an interrupt after reset when it is ready to receive MDIO transfers Since there are many types of management devices the interrupt polarity is not standardized In order to be flexible and in
232. wer on reset module and therefore a TRST input is unnecessary User s Manual Hardware Description 28 Revision 1 0 2012 02 17 2 2 7 2 Len Power Supply Pins C XWAY PHY11G PEF 7071 Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s External Signals This section specifies the power supply pins of the XWAY PHY11G The operating ranges of the power domains are specified in Chapter 6 2 Table 8 Power Supply Pins Pin No Name Pin Type Buffer Type Function 25 30 35 VDDH PWR High Voltage Domain Supply This is the group of supply pins for the high voltage domain which supplies the line driver in the PMA of the XWAY PHY11G This supply has to provide a nominal voltage of Vpp 2 5 V 3 3 V with a worst case tolerance of 5 at the respective corners Note For optimal power consumption the lowest possible voltage is selected in the system 38 VDDR PWR Regulator Voltage Domain Supply This is the group of supply pins for the DC DC switching regulator voltage domain which supplies the integrated DC DC converter of the XWAY PHY11G This supply has to provide a nominal voltage of Vopr 2 5 V 3 3 V with a worst case tolerance of 15 at the respective corners Note For optimal power consumption the lowest possible voltage is selected in the system 2 7 45 VDDP PWR Pad Voltage Domain Supply This is the group of supply pins for the pad
233. y interaction whatsoever with a PHY Although not a likely application the XWAY PHY11G can be used in PSE systems of the in band PoE type A generic example of such an application is shown in Figure 32 User s Manual 70 Revision 1 0 2012 02 17 Hardware Description E L XWAY PHY11G PEF 7071 e ANTIQ Single Port Gigabit Ethernet PHY 10 100 1000 Mbit s Functional Description XWAY PHY11G Transformer ilt 30 UU 00 00 POE PSE Figure 32 Generic Schematic of the PoE PSE Application Note that the PSE adds complexity to the design because of the high voltage supply of the PoE Typically 48 V are used to supply the remote PD It is recommended to avoid cross connecting any of the PSE signals with any of the XWAY PHY11G signals unless these are galvanically de coupled This applies to the common mode supply injection at the center taps of the transformers which is only done on the line side of the transformer Some PSE devices support an IC interface for management interaction This interface can only be connected to the XWAY PHY11G when using an opto coupler 3 5 3 Energy Efficient Ethernet The IEEE 802 3az standard 2 describing Energy Efficient Ethernet EEE operation is also implemented in the XWAY PHY11G Since the method

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