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ModelSim User's Manual - Institut für Informatik

1. ftop clk top prw top pstrb top prdy top paddr top pdata topsa top sstrb top srdy D ns to 966 ns 00000010 click a value here to interval measurement Click and drag with scroll the window to the center mouse that value selected cursor is bold button to zoom in ModelSim User s Manual on an area of the display When the Wave window is first drawn there is one cursor located at time zero Clicking anywhere in the waveform display brings that cursor to the mouse location You can add cursors to the waveform pane with the Cursor gt Add Cursor menu selection or the Add Cursor button shown below The selected cursor is drawn as a bold solid line all other cursors are drawn with thin dashed lines Remove cursors by selecting them and selecting Cursor gt Delete Cursor or the Delete Cursor button shown below Add Cursor Delete Cursor add a cursor to the center delete the selected cursor of the waveform window from the window Wave window UM 201 Finding a cursor The cursor value on the Goto list corresponds to the simulation time of that cursor Choose a specific cursor view by selecting Cursor gt Goto You can also select cursors by clicking a value in the cursor value pane Alternatively you can click a value with your second mouse button and type the value to which you want to scroll Making cursor measurements Each cursor is displayed with a time box showing the precise simulatio
2. VHDL settings tab ia Load Design OP Xx besa VHDL Verlog Libraries SDF Generics o Name Value Override Instance Add Delete Edit VITAL TEXTIO Files STD_INPUT T Disable Timing Checks Browse r Use Vital 2 2b SDF Mapping default is Vital 95 STD_OUTPUT Tl Disable Glitch Generation Browse Cancel The VHDL tab includes these options Generics The Add button opens a dialog box shown below that allows you to specify the value of generics within the current simulation generics are then added to the Generics list You can also select a generic on the listing to Delete or Edit ModelSim User s Manual Simulating with the graphic interface UM 221 From the Specify a Generic dialog box you can Specify a Generic ojx set the following options 3 Generic Name tph_hi e Generic Name g lt Name gt lt Value gt Valuelirns tt ttst lt i sS s S SOSOCOC The name of the generic parameter Type it in as it appears in the VHDL source case is ignored Value OK Cancel Specifies a value for all generics in the design with the given name above that have not received explicit values in generic maps such as top level generics and generics that would otherwise receive their default value The value must be appropriate for the declared data type of the generic parameter No spaces are allowed in the speci
3. pulse_e_style_onevent This option selects the on event style of propagating pulse errors see pulse_e lt percent gt A pulse error propagates to the output as an X and the on event style is to schedule the X to occur at the same time and for the same duration that the pulse would have occurred if it had propagated through normally The on event style is the default for propagating pulse errors sdf_nocheck_celltype By default the SDF annotator checks that the CELLTYPE name in the SDF file matches the module or primitive name for the CELL instance It is an error if the names do not match The sdf_nocheck_celltype option disables this error check sdf_verbose This option displays a summary of the design objects annotated for each SDF file show_cancelled_e This option causes Vsim to drive a pulse error state X for the duration of negative pulses on specify path delays By default Vsim filters negative pulses transport_int_delays By default interconnect delays operate in inertial mode pulses smaller than the delay are filtered The transport_int_delays option selects transport mode with pulse control for single source nets one interconnect path In transport mode narrow pulses are propagated through interconnect delays This option works independent from multisource_int_delays transport_path_delays By default path delays operate in inertial mode pulses smaller than the delay are filtered The transport
4. Height Window menu set the waveform height in pixels for the selected item Initial Layout restore all windows to the size and placement of the initial full screen layout Cascade cascade all open windows Tile Horizontally tile all open windows horizontally Tile Vertically tile all open windows vertically Icon Children icon all but the Main window Icon All icon all windows Deicon All ModelSim User s Manual deicon all windows Wave window UM 185 lt window_name gt list of the currently open windows select a window name to switch to or show that window if it is hidden when the source window is available the source file name is also indicated open additional windows from the View menu UM 128 in the Main window ModelSim User s Manual UM 186 7 Graphic Interface The Wave window toolbar The Wave window toolbar gives you quick access to these ModelSim commands and functions waye default File Edit Cursor Zoom Compare Bookmark Format Window oh tae RHA eX QAQQQHE FF ELELEL HM Whe ea gt S X x S c yo o N x oS L Sf FS FCFESLESZ FE eos SLFS Ser SF FHL FS amp AS lt Ss e O O C L V Pe SSIES A S LL L Lee S ay YS N N S FF F F S Q gt a N KA S x K Pes S pe S ES FF oO amp d se amp F X o os ES Ds amp Wave window toolbar buttons Button Menu equivalent Other options
5. Preference variables located in INI files UM 283 Variable name Value range Purpose Default WLFCompress 0 1 turns WLF file compression on 1 or off 0 WLFDeleteOnQuit 0 1 specifies whether a WLF file should be deleted when the simulation ends if set to 0 the file is not deleted if set to 1 the file is deleted WLFSaveAllRegions specifies whether to save all design hierarchy in the WLF file 1 or only regions containing logged signals 0 WLESizeLimit WLF file size limit limits WLF file by size as closely as possible to the specified number of megabytes if both size and time limits are specified the most restrictive is used setting to 0 results in no limit WLFTimeLimit WLF file time limit limits WLF file by time as closely as possible to the specified amount of time If both time and size limits are specified the most restrictive is used setting to 0 results in no limit Spaces in path names For the Src_Files and Work_Libs variables each element in the list is enclosed within curly braces This allows spaces inside elements since Windows allows spaces inside path names For example a source file list might look like Src_Files SMODELSIM_PROJECT counter v MODELSIM_PROJECT tb counter v Where the file tb counter v contains a space character between the b and c Setting variables in INI files Edit the initialization file directly with any text editor to change or
6. Task syswrite Virtual items Function get_hit indicated by an orange diamond icon E lt 0 cache_set only virtual signals buses and functions E 1 cache_set only see Virtual Objects User defined I s2 cache_setfonly buses and more UM 110 for more I s3 cache_set only information Viewing the hierarchy sim top Whenever you see a tree view as in the Structure window displayed here you can use the mouse to collapse or expand the hierarchy Select the symbols as shown below to change the view of the structure Description click a plus box to expand the item and view the structure click a minus box to hide a hierarchy that has been expanded ModelSim User s Manual UM 122 7 Graphic Interface ModelSim User s Manual Finding items within tree windows You can open the Find dialog box within all windows except the Dataflow windows by selecting Edit gt Find or by using lt control s gt Unix or lt control f gt Windows Options within the Find dialog box allow you to search unique text string fields within the specific window See also e Finding items by name in the List window UM 149 e Finding HDL items in the Signals window UM 160 and e Finding items by name or value in the Wave window UM 199 Main window UM 123 Main window The Main window is pictured below as it appears when ModelSim is first invoked Note that your operating system graphic
7. continue simulation lt Fll gt single step lt F12 gt step over The Main window allows insertions or pastes only after the prompt therefore you don t need to set the cursor when copying strings to the command line Dataflow window UM 135 Dataflow window The Dataflow window allows you to trace VHDL signals or Verilog nets and registers through your design Double click an item with the left mouse button to move it to the center of the Dataflow display VHDL signals or processes in the Dataflow window e A signal is displayed in the center of the window with all the processes that drive the signal on the left and all the processes that read the signal on the right e A process is displayed with all the signals read by the process shown as inputs on the left of the window and all the signals driven by the process on the right Verilog nets registers or processes in the Dataflow window e A net or register is displayed in the center of the window with all the processes that drive the net or register on the left and all the processes triggered by the net or register on the right e A process is displayed with all the nets or registers that trigger the process shown as inputs on the left of the window and all the nets or registers driven by the process on the right lt dataflow OF x File Window lt dataflow OF Xx File Window See Eee paddr testbench test sum cin
8. vpi_free_object systf_handle void vlog_startup_routines RegisterMyTfs 0 hello v module hello initial hello endmodule Compile the VPI code for the Solaris operating system gcc c I lt install_dir gt include hello c ld G o hello sl hello o ale le Compile the Verilog code vlib work a J a J vlog hello v Simulate the design vsim c pli hello sl hello Loading work hello Loading hello sl VSIM 1 gt run all Hello world VSIM 2 gt quit gt Note A general VPI example can be found in lt install_dir gt modeltech examples vpi ModelSim User s Manual Verilog PLIVPI UM 93 The PLI callback reason argument The second argument to a PLI callback function is the reason argument The values of the various reason constants are defined in the veriuser h include file See IEEE Std 1364 for a description of the reason constants The following details relate to ModelSim Verilog and may not be obvious in the IEEE Std 1364 Specifically the simulator passes the reason values to the misctf callback functions under the following circumstances reason_endofcompile For the completion of loading the design reason_finish For the execution of the finish system task or the quit command reason_startofsave For the start of execution of the checkpoint command but before any of the simulation state has been saved This allows the PLI application to prepare for the save but
9. Detecting infinite zero delay loops UM 299 Detecting infinite zero delay loops Simulations use steps that advance simulated time and steps that do not advance simulated time Steps that do not advance simulated time are called delta cycles Delta cycles are used when signal assignments are made with zero time delay If a large number of delta cycles occur without advancing time it is usually a symptom of an infinite zero delay loop in the design In order to detect the presence of these loops ModelSim defines a limit the iteration_limit on the number of successive delta cycles that can occur When the iteration_limit is exceeded vsim stops the simulation and gives a warning message The iteration_limit default value is1000 When you get an iteration_limit warning first increase the iteration limit and try to continue simulation You can set the iteration_limit from the Options gt Simulation menu or by modifying the modelsim ini file See Projects and system initialization UM 15 for more information on modifying the modelsim ini file If the problem persists look for zero delay loops Run the simulation and look at the source code when the error occurs Use the step button to step through the code and see which signals or variables are continuously oscillating Two common causes are a loop that has no exit or a series of gates with zero delay where the outputs are connected back to the inputs http www model com resource
10. Incremental siege Library usage Verilog XL compatible sampik options Verilog XL uselib compiler directive Simulation Simulation jose tak anit Event order issues f Verilog XL compatible sitniilater options Cell Libraries Delay modes System Tasks IEEE Std 1364 aytem tasks ModelSim User s Manual Clee eG a ce ie UM 42 UM 45 UM 45 UM 45 UM 45 UM 46 UM 46 UM 47 UM 47 UM 48 UM 49 UM 50 UM 50 UM 50 UM 50 UM 51 UM 51 UM 52 UM 52 UM 52 UM 52 UM 53 UM 54 UM 54 UM 55 Cie ee eneic 4 Ce ee e e ee ake m Cc 4 amp Nn a UM 57 UM 61 UM 62 UM 64 UM 65 UM 67 UM 69 UM 70 UM 70 UM 71 UM 75 UM 75 UM 77 E Cc ese ie C GOC ec JM 77 UM 5 Verilog XL compatible system tasks UM 80 init_signal_spy UM 82 Compiler Directives f UM 84 IEFE Std 1364 conijiles directives UM 84 Verilog XL compatible compiler directives UM 85 Verilog PLI VPI UM 86 Registering PLI ere UM 86 Registering VPI applications UM 88 Compiling and linking PLI VPI eo UM 89 The PLI callback reason argument UM 93 The sizetf callback function UM 94 PLI object handles UM 94 Third party PLI apritei UM 95 Support for VHDL objects UM 96 IEEE Std 1364 ACC routines UM 97 IEEE Std 1364 TF routines CR os 2 Bop we PP Bee 2 Slee f ee e UM98 Verilog XL co
11. Signal Name Specifies the signal or net for the applied stimulus Value Initially displays the current value which can be changed by entering a new value into the field A value can be specified in radixes other than decimal by using the form for VHDL and Verilog respectively base value or blo d h value 16 EE or h EE for example specifies the hexadecimal value EE Kind Freeze Freezes the signal or net at the specified value until it is forced again or until it is unforced with a noforce command CR 86 Freeze is the default for Verilog nets and unresolved VHDL signals and Drive is the default for resolved signals If you prefer Freeze as the default for resolved and unresolved signals you can change the default force kind in the modelsim ini file see Projects and system initialization UM 15 e Kind Drive Attaches a driver to the signal and drives the specified value until the signal or net is forced again or until it is unforced with a noforce command CR 86 This value is illegal for unresolved VHDL signals Signals window UM 159 Kind Deposit Sets the signal or net to the specified value The value remains until there is a subsequent driver transaction or until the signal or net is forced again or until it is unforced with a noforce command CR 86 Delay For Allows you to specify how many time units from the current time the stimulus is to be applied Cancel After Cancels the force command
12. UM 59 5 Verilog Simulation Chapter contents Compilation UM 61 Incremental dripte UM 62 Library usage UM 64 Verilog XL compatible ae apims UM 65 Verilog XL uselib compiler directive UM 67 Simulation UM 69 Invoking the simulator UM 69 Simulation resolution limit UM 70 Event order issues UM 70 Verilog XL compatible maitot apsis UM 71 Cell Libraries S SDF timing annotation aa UM 75 Delay modes e o UM 75 System Tasks UM 77 IEEE Std 1364 gam iik UM 77 Verilog XL compatible system tasks UM 80 init_signal_spy UM 82 Compiler Directives aa a a UM 84 IEEE Std 1364 compiler ree toe ee ee UM 84 Verilog XL compatible compiler directives UM 85 Verilog PLI VPI UM 86 Registering PLI appicaions UM 86 Registering VPI applications UM 88 Compiling and linking PLI VPI inplicaions UM 89 The PLI callback reason argument 2 oe ee UM 93 The sizetf callback function UM 94 PLI object handles i 4 UM 94 Third party PLI applications UM 95 Support for VHDL objects UM 96 IEEE Std 1364 ACC routines UM 97 IEEE Std 1364 TF routines soe ee ee UM 98 Verilog XL compatible routines UM 100 64 bit support in the PLI UM 100 PLI VPI tracing a UMA 100 This chapter describes how to compile and simulate Verilog designs with ModelSim Verilog ModelSim Verilog implements the Verilog language as
13. tile all open windows horizontally Tile Vertically tile all open windows vertically Icon Children icon all but the Main window Icon All icon all windows Deicon All deicon all windows lt window_name gt list of the currently open windows select a window name to switch to or show that window if it is hidden when the source window is available the source file name is also indicated open additional windows from the View menu UM 128 in the Main window Selecting HDL item types to view The View gt Filter menu selection allows you to specify which HDL items are shown in the Signals window Multiple options ice Ol x can be selected Input Ports Output Ports InOut Ports Internal Signals ModelSim User s Manual UM 158 7 Graphic Interface Forcing signal and net values ModelSim User s Manual The Edit gt Force command displays a dialog box that allows you to apply stimulus to the selected signal or net Multiple signals can be selected and forced the force dialog box remains open until all of the signals are either forced skipped or you close the dialog box To cancel a force command use the Edit gt NoForce command See also the force command CR 76 Force Selected Signal Signal Name ZAA Vauel 0 Kind Freeze C Drive Deposit Delay For 0 Cancel After OK Cancel The Force dialog box includes these options
14. Button Menu equivalent Other equivalents Compile Source File File gt Compile use vcom or vlog command at the a open the Compile HDL Source VSIM prompt File dialog see vcom CR 129 or vlog CR 162 command Open Source File File gt Open select an HDL item in the Aa open the Open File dialog box Structure window the associated you can open any text file for source file is loaded into the editing in the Source window Source window Save Source File File gt Save none save the file in the Source window Cut Edit gt Cut see Mouse and keyboard cut the selected text within the shortcuts UM 133 Source window ModelSim User s Manual Source window toolbar buttons Source window UM 167 Button Menu equivalent Other equivalents Copy copy the selected text within the 5 Source window Edit gt Copy see Mouse and keyboard shortcuts UM 133 Paste paste the copied text to the cursor location Edit gt Paste see Mouse and keyboard shortcuts UM 133 Find find the specified text string within the source file match case option Edit gt Find lt control f gt Windows Step steps the current simulation to the next HDL statement Main window Run gt Step use step command at the V SIM prompt see step CR 114 command Step Over Main window Run gt Step Over use the step over command at the VSIM prompt see step CR 114
15. Main window transcript Paste Edit gt Paste see Mouse and keyboard a paste the copied text to the cursor shortcuts UM 133 location Restart Run gt Restart restart lt arguments gt reload the design elements and resets the simulation time to see restart CR 104 zero with the option of using current formatting breakpoints and WLF file Run Length none run lt specific run length gt O5j specify the run length for the current simulation see run CR 107 ModelSim User s Manual UM 132 7 Graphic Interface Main window toolbar buttons Button Menu equivalent Command equivalents Run run the current simulation for the specified run length Run gt Run lt default_run_length gt run no arguments see run CR 107 m Continue Run continue the current simulation run until the end of specified run length or until it hits a breakpoint or specified break event Run gt Continue run continue see run CR 107 Run All run the current simulation forever or until it hits a breakpoint or specified break event Run gt Run All run all see run CR 107 see Assertion settings tab UM 227 s Break stop the current simulation run Step step the current simulation to the next HDL statement Run gt Step step see step CR 114 Step Over HDL statements are executed but treated as simple statements instead of entered and traced l
16. and vlog sections of the local modelsim ini file When you make changes in the compiler options dialog or use the vymap command the tool updates the appropriate sections of the file The pref tcl file references the default ini file via the GetPrivateProfileString Tcl command The ini file that is read will be the default file defined at the time pref tcl is loaded UM 31 3 Design libraries Chapter contents Design library contents UM 32 Design unit information UM 32 Design library types UM 32 Working with design libraries UM 33 Creating a library UM 33 Managing library contents UM 34 Assigning a logical name to a design fibres UM 37 Moving a library UM 39 Specifying the resource libraries UM 40 VHDL resource libraries UM 40 Predefined libraries 5 UM 40 Alternate IEEE libraries polist UM 41 VITAL 2000 library UM 41 Regenerating your design Hios UM 41 Importing FPGA libraries UM 42 VHDL contains libraries which are objects that contain compiled design units libraries are given names so they may be referenced Verilog designs simulated within ModelSim are compiled into libraries as well ModelSim User s Manual UM 32 3 Design libraries Design library contents A design library is a directory that serves as a repository for compiled design units The design units contained in a design library consist of VHDL entities packages architectures and configuratio
17. vpiSizedFunc systf_data tfname Smyfunc systf_data calltf MyFuncCalltf systf_data compiletf MyFuncCompiletf systf_data sizetf MyFuncSizetf systf_data user_data 0 vpi_register_systf amp systf_data callback reason cbEndOfCompile callback cb_rtn MyEndOfCompCB callback user_data 0 void vpi_register_cb amp callback callback reason cbStartOfSimulation callback cb_rtn MyStartOfSimCB callback user_data 0 void vpi_register_cb amp callback void vlog_startup_routines RegisterMySystfs 0 last entry must be 0 Loading VPI applications into the simulator is the same as described in Registering PLI applications UM 86 ModelSim User s Manual Verilog PLI VP UM 89 PLI and VPI applications can co exist in the same application object file In such cases the applications are loaded at startup as follows e If an init_usertfs function exists then it is executed and only those system tasks and functions registered by calls to mti_RegisterUserTF will be defined e If an init_usertfs function does not exist but a veriusertfs table does exist then only those system tasks and functions listed in the veriusertfs table will be defined e If an init_usertfs function does not exist and a veriusertfs table does not exist but a vlog_startup_routines table does exist then only those system tasks and functions and callbacks registered by functions in the vlog_sta
18. 10ns 10 ns Time values without units are taken to be in the UserTimeScale Return values are always in the current Time Scale Units All time values are converted to a 64 bit integer value in the current Time Scale This means that values smaller than the current Time Scale will be truncated to 0 Command Description intToTime lt intHi32 gt lt intLo32 gt converts two 32 bit pieces high and low order into a 64 bit quantity Time in ModelSim is a 64 bit integer RealToTime lt real gt converts a lt real gt number to a 64 bit integer in the current Time Scale scaleTime lt time gt lt scaleFactor gt Command returns the value of lt time gt multiplied by the lt scaleFactor gt integer Description eqTime lt time gt lt time gt evaluates for equal neqTime lt time gt lt time gt evaluates for not equal gtTime lt time gt lt time gt evaluates for greater than gteTime lt time gt lt time gt evaluates for greater than or equal ItTime lt time gt lt time gt evaluates for less than lteTime lt time gt lt time gt evaluates for less than or equal All relation operations return 1 or 0 for true or false respectively and are suitable return values for TCL conditional expressions For example if eqTime SNow 1750ns ModelSim User s Manual UM 264 10 Tcl and macros Arithmetic Command Description addTim
19. Graphic Interface ModelSim User s Manual Disable debugging data Models compiled with this option do not use any of the ModelSim debugging features Consequently your user will not be able to see into the model This also means that you cannot set breakpoints or single step within this code Don t compile with this option until you re done debugging Same as the nodebug switch for the vlog command CR 162 See Source code security and nodebug UM 297 for more details Edit the NoDebug UM 279 variable in the modelsim ini file to set a permanent default Convert Verilog identifiers to upper case Converts regular Verilog identifiers to uppercase Allows case insensitivity for module names Same as the u switch for the vlog command CR 162 Edit the UpCase UM 280 variable in the modelsim ini file to set a permanent default Disable loading messages Disables loading messages in the Main window Same as the quiet switch for the vlog command CR 162 Edit the Quiet UM 279 variable in the modelsim ini file to set a permanent default Show source lines with errors Causes the compiler to display the relevant lines of code in the transcript Same as the source switch for the vlog command CR 162 Edit the Show_source UM 279 variable in the modelsim ini file to set a permanent default Other Verilog Options Library Search Specifies the Verilog source library directory to search for undefined modules Same as the y
20. Icon Children icon all but the Main window Icon All icon all windows Deicon All deicon all windows lt window_name gt list of the currently open windows select a window name to switch to or show that window if it is hidden when the source window is available the source file name is also indicated open additional windows from the View menu UM 128 in the Main window Finding items in the Structure window The Find dialog box allows you to search for text strings in the Structure window Select Edit gt Find Structure window to bring up the Find dialog box Enter the value to search for in the Find Find in structure x field Specify whether Find Find Next you are looking for an Instance pee Entity Module or Field Direction Close Architecture Also Instance specify which direction Pe Down to search Check Auto Entity Module C Up Wrap to have the C Archi rchitecture search continue at the M Auto Wrap top of the window ModelSim User s Manual Variables window UM 175 Variables window The Variables window is divided into two window panes The left pane lists the names of HDL items within the current process The right pane lists the current value s associated with each name The pathname of the current process is displayed at the bottom of the window The internal variables of your design can remain hidden if you wish see Source code security and nodebug UM 297 H
21. It is an ASCII file containing header information variable definitions and variable value changes VCD is in common use for Verilog designs and is controlled by VCD system task calls in the Verilog source code ModelSim provides simulator command equivalents for these system tasks and extends VCD support to VHDL designs the ModelSim commands can be used on either VHDL or Verilog designs gt Note If you need vendor specific ASIC design flow documentation that incorporates VCD please contact your ASIC vendor ModelSim User s Manual UM 248 9 Value Change Dump VCD Files ModelSim VCD commands and VCD tasks ModelSim VCD commands map to IEEE Std 1364 VCD system tasks and appear in the VCD file along with the results of those commands The table below maps the VCD ModelSim User s Manual commands to their associated tasks VCD commands VCD system tasks ved add CR 119 dumpvars ved checkpoint CR 120 dumpall ved file CR 122 4 dumpfile ved flush CR 124 dumpflush ved limit CR 125 dumplimit ved off CR 126 dumpoff ved on CR 127 dumpon ModelSim versions 5 5 and later support multiple VCD files This functionality is an extension of the IEEE Std 1364 specification The tasks behave the same as the IEEE equivalent tasks such as dumpfile dumpvar etc The difference is that fdumpfile can be called multiple times to create more than one VCD f
22. Load Wave Format File gt Load Format do wave do run a Wave window format DO file previously saved with Save Format w see do command CR 64 Save Wave Format saves the current Wave window display and signal preferences to a do macro file File gt Save Format none Print Waveform prints a user selected range of the current Wave window display to a printer or a file File gt Print File gt PrintPostscript o none Cut Edit gt Cut right mouse in pathname pane gt Cut cut the selected signal from the Wave window Copy Edit gt Copy right mouse in pathname pane gt copy the selected signal in the signal name pane ModelSim User s Manual Copy Wave window toolbar buttons Wave window UM 187 Button Menu equivalent Other options Paste Edit gt Paste right mouse in pathname pane gt paste the copied signal above Paste another selected signal Add Cursor Cursor gt Add Cursor none add a cursor to the center of the waveform pane Delete Cursor Cursor gt Delete Cursor none delete the selected cursor from the window Find Previous Transition locate the previous signal value change for the selected signal Edit gt Search Search Reverse keyboard Shift Tab Find Next Transition locate the next signal value change for the selected signal Edit gt Search Search Forward keyboard Tab Zoom in 2x zoom in by
23. ModelSim User s Manual 6 WLF files datasets and virtuals UM 103 Chapter contents WLF files datasets Saving a simulation to a WLF file Opening datasets Viewing dataset structure Managing datasets Using datasets with ModelSim commands Restricting the dataset prefix display Virtual Objects User defined buses and more Virtual signals Virtual functions Virtual regions Virtual types Dataset WLF file and virtual commands JM 104 M 104 M 105 M 106 M 108 M 108 M 109 4 4 4 4 Ge Ele Ce ec 4 M 110 M 110 M 111 M 112 M 112 qQaaqqc f M 113 A ModelSim simulation can be saved to a wave log format WLF file using the w1 lt filename gt argument to the vsim command CR 168 for future viewing or comparison to a current simulation We use the term dataset to refer to a WLF file that has been reopened for viewing With ModelSim release 5 3 and later you can open more than one WLF file for simultaneous viewing You can also create virtual signals that are simple logical combinations of or logical functions of signals from different datasets ModelSim User s Manual UM 104 6 WLF files datasets and virtuals WLF files datasets waye default Wave log format WLF files store saved simulation data Any number of WLF files can be reloaded for viewing or comparing to the active simulation The term dataset refers to a logical n
24. UM 233 Specifying SDF files for simulation Instance specification SDF specification with the GUI Errors and warnings VHDL VITAL SDF SDF to VHDL generic hice Resolving errors UM 7 JM 176 Z k jk oo M 178 M 179 M 179 M 180 M 180 M 181 M 182 M 186 M 189 M 190 M 191 M 192 M 197 M 198 M 199 M 200 M 201 M 201 M 201 M 203 M 205 M 206 JM 211 JM 212 JM 213 JM 217 M 218 M 220 M 222 M 223 M 224 M 225 M 226 M 230 M 230 JM 232 osesgqogcgqggcgggggggggggggggCgs eee 4 4 4 4 4 Sssgoocgcgccgcs 4 one E JM 234 JM 234 JM 235 JM 235 JM 236 JM 236 JM 237 eee ec eed ModelSim User s Manual UM 8 Table of Contents Wettlog SDP o s e c s 2 ow a s UM 238 The sdf_annotate system task UM 238 SDF to Verilog construct matching UM 239 Optional edge specifications UM 241 Optional conditions UM 242 Rounded timing values UM 243 SDF for Mixed VHDL and Verilog Designs UM 244 Interconnect delays UM 244 Troubleshooting Joe OR Ee howe eR ee ee Re OS UM 245 Mistaking a component or module name for an instance label UM 246 Forgetting to specify the instance UM 246 9 Value Change Dump VCD Files UM 247 ModelSim VCD commands and VCD tasks UM 248 Creating a VCD file UM 249 Flow for four state VCD file UM 249 A VCD file from source to output UM 250 VCD simulator commands UM 250 VCD output UM 251 10 Tcl and mac
25. UM 245 Specifying the wrong instance UM 245 Mistaking a component or module name ns an instance Tab l UM 246 Forgetting to specify the instance UM 246 This chapter discusses ModelSim s implementation of SDF Standard Delay Format timing annotation Included are sections on VITAL SDF and Verilog SDF plus troubleshooting Verilog and VHDL VITAL timing data can be annotated from SDF files by using the simulator s built in SDF annotator SDF and ModelSim SDF timing annotations can be applied only to your FPGA vendor s libraries all other libraries will simulate without annotation ModelSim User s Manual UM 234 8 Standard Delay Format SDF Timing Annotation Specifying SDF files for simulation ModelSim supports SDF versions 1 0 through 3 0 The simulator s built in SDF annotator automatically adjusts to the version of the file Use the following vsim CR 168 command line options to specify the SDF files the desired timing values and their associated design instances sdfmin lt instance gt lt filename gt sdftyp lt instance gt lt filename gt sdfmax lt instance gt lt filename gt Any number of SDF files can be applied to any instance in the design by specifying one of the above options for each file Use sdfmin to select minimum sdftyp to select typical and sdfmax to select maximum timing values from the SDF file Instance specification ModelSim User s Manual The instance paths in t
26. UM 313 issues UM 70 P Packages standard UM 40 textio UM 40 util UM 54 vital_memory UM 41 Parameters using with macros UM 269 pathnames dealing with spaces CR 9 Pathnames in VSIM commands CR 10 PathSeparator ini file variable UM 282 pause command CR 95 PLI specifying which apps to load UM 87 Veriuser entry UM 87 PLI VPI UM 86 tracing UM 100 PLIOBJS environment variable UM 87 UM 276 Popup toggling Waveform popup on off UM 179 UM 198 Postscript saving a waveform in UM 206 Precedence of variables UM 288 pref tcl file UM 287 Preference variables editing UM 287 located in ini files UM 278 located in Tcl files UM 287 Process window UM 152 Process without a wait statement UM 214 Processes displayed in Dataflow window UM 135 values and pathnames in Variables window UM 175 Programming Language Interface UM 86 projects accessing from the command line UM 26 adding files to UM 21 changing compile order UM 24 compiling the files UM 22 creating UM 19 customizing settings UM 24 differences in 5 5 UM 17 loading a design UM 23 MODELSIM environment variable UM 275 ModelSim User s Manual UM 314 Index override mapping for work directory with vcom CR 132 override mapping for work directory with vlog CR 164 overview UM 16 setting compiler options in UM 25 propagation preventing X propagation CR 171 protect compiler directive UM 297 Pulse error state CR 176 UM 74 pwd command CR 98 Q QuickSim II logfil
27. Verilog specify Verilog style colorizing Highlighting VHDL Highlighting specify VHDL style colorizing Freeze File maintain the same source file in the Source window useful when you have two Source windows open one can be updated from the Structure window UM 172 the other frozen Freeze View disable updating the source view from the Process window UM 152 Window menu Initial Layout restore all windows to the size and placement of the initial full screen layout Cascade cascade all open windows Tile Horizontally tile all open windows horizontally Tile Vertically tile all open windows vertically Icon Children icon all but the Main window ModelSim User s Manual UM 166 7 Graphic Interface Icon All icon all windows Deicon All deicon all windows lt window_name gt list of the currently open windows select a window name to switch to or show that window if it is hidden when the source window is available the source file name is also indicated open additional windows from the View menu UM 128 in the Main window The Source window toolbar Buttons on the Source window toolbar give you quick access to these ModelSim commands and functions i source proc File Edit Object Options Window Ssi BBA OO y Y g So R K 2 S D Ve A eS oR Q D A x0 N4 S pe o amp S K4 amp fo amp Source window toolbar buttons
28. W and2 andgfonly Loading work xorgfonly or2 orgfonl Loading work andg only A glony Loading work orgfonly VSIM 55 gt wm title ModelSim Test Compare VSI 55 Project test NN feet e Project tab Shows all files that are included in the open project See Chapter 2 Projects and system initialization for details Library tab Shows compiled design units in the specified library See Managing library contents UM 34 for details W Package gates Structure tabs Shows a hierarchical view of the active simulation and any open datasets This is the same data that is displayed in the Structure window UM 172 There is one tab for the current simulation and one tab for each open dataset See Viewing dataset structure UM 106 for details ModelSim User s Manual Transcript Main window The transcript portion of the Main window maintains a running history of commands that are invoked and messages that occur as you work with ModelSim When a simulation is running the transcript displays a VSIM prompt allowing you to enter command line commands from within the graphic interface You can scroll backward and forward through the current work history by using the vertical scrollbar You can also use arrow keys to recall previous commands or copy and paste using the mouse within the window see The following mouse actions and special keystrokes can be used to edit commands in the entry region of the Mai
29. deicon all windows lt window_name gt list of the currently open windows select a window name to switch to or show that window if it is hidden when the source window is available the source file name is also indicated open additional windows from the View menu UM 128 in the Main window ModelSim User s Manual Dataflow window UM 137 Tracing HDL items with the Dataflow window The Dataflow window is linked with the Signals window UM 155 and the Process window UM 152 To examine a particular process in the Dataflow window click on the process name in the Process window To examine a particular HDL item in the Dataflow window click on the item name in the Signals window With a signal in the center of the Dataflow window you can e click once on a process name in the Dataflow window to make the Source Process Signals and Variable windows update to show that process e click twice on a process name in the Dataflow window to move the process to the center of the Dataflow window With a process in the center of the Dataflow window you can e click twice on an item name to move that item to the center of the Dataflow window The backward and forward buttons on the toolbar are analogous to Back and Forward buttons in a web browser They move backward or forward through previous views of the dataflow move backward through dataflow views move forward through dataflow views The Dataflow w
30. gt ioj x Deltas ExpandDeltas Colapse Delas No Deltas Trigger On Mi Siana chande Strobe Period 0 ns T Strobe First Strobe at fo ns Trigger Gating I Use Gating Expression Use Expression Builder Expression On Duration fo ns OK Cancel Apply The Triggers tab includes the following options e Deltas Expand Deltas When selected with the Trigger on Signals check box displays a new line for each time step on which items change including deltas within a single unit of time resolution e Deltas Collapse Deltas Displays only the final value for each time unit e Deltas No Deltas Hides simulation cycle delta column e Trigger On Signal Change Triggers on signal changes Defaults to all signals Individual signals can be excluded ModelSim User s Manual UM 144 7 Graphic Interface from triggering by using the Prop gt Signals Props dialog box or by originally adding them with the notrigger option to the add list command CR 32 Trigger On Strobe Triggers on the Strobe Period you specify specify the first strobe with First Strobe at Trigger Gating Use Gating Expression Enables triggers to be gated on a value of 1 or off a value of 0 by the specified Expression Trigger Gating On Duration The duration for gating to remain open after the last list row in which the expression evaluates to true expressed in x number of default timesc
31. gt q 0 IOPATH a y 3 4 buf ul y a The IOPATH construct usually annotates path delays If the module contains no path delays then all primitives that drive the specified output port are annotated INTERCONNECT and PORT are matched to input ports SDF Verilog INTERCONNECT ul y u2 a 5 input a PORT u2 a 5 inout a Both of these constructs identify a module input or inout port and create an internal net that is a delayed version of the port This is called a Module Input Port Delay MIPD All primitives specify path delays and specify timing checks connected to the original port are reconnected to the new MIPD net PATHPULSE and GLOBALPATHPULSE are matched to specify path delays SDF Verilog PATHPULSE a y 5 10 a gt y 0 GLOBALPATHPULSE a y 30 60 a gt y 0 If the input and output ports are omitted in the SDF then all path delays are matched in the cell ModelSim User s Manual UM 240 8 Standard Delay Format SDF Timing Annotation DEVICE is matched to primitives or specify path delays SDF Verilog DEVICE y 5 and ul y a b DEVICE y 5 a gt y 0 b gt y 0 If the SDF cell instance is a primitive instance then that primitive s delay is annotated If it is a module instance then all specify path delays are annotated that drive the output port specified in the DEVICE construct all path delays are an
32. lt fname gt options vcom novital VitalTimingCheck novital VitalAND design vhd The novital switch only affects calls to VITAL functions from the design units currently being compiled Pre compiled design units referenced from the current design units will still call the built in functions unless they too are compiled with the novital option ModelSim VITAL built ins will be updated in step with new releases of the VITAL packages ModelSim User s Manual UM 54 4 VHDL Simulation Util package The util package is included in ModelSim versions 5 5 and later and serves as a container for various VHDL utilities The package is part of the modelsim_lib library which is located in the modelsim tree and mapped in the default modelsim ini file To access the utilities in the package you would add lines like the following to your VHDL code library modelsim_lib use modelsim_lib util all get_resolution ModelSim User s Manual get_resolution returns the current simulator resolution as a real number For example 1 femtosecond corresponds to le 15 Syntax resval get_resolution j Returns Name Description resval real The simulator resolution represented as a real Arguments None Related functions to_real UM 56 to_time UM 57 Example If the simulator resolution is set to 10ps and you invoke the command resval get_resolution the value returned to resval would be le 11 Util p
33. lt opt ions gt can be one or more of force nobreakpoint nolist nolog and nowave Example DefaultRestartOptions nolog force Note You can also set these defaults in the modelsim tcl file The Tcl file settings will override the ini file settings VHDL93 You can make the VHDL93 standard the default by including the following line in the INT file vcom Turn on VHDL 1993 as the default Default is off VHDL 1987 VHDL93 1 Opening VHDL files You can delay the opening of VHDL files with an entry in the ZNI file if you wish Normally VHDL files are opened when the file declaration is elaborated If the DelayFileOpen option is enabled then the file is not opened until the first read or write to that file vsim DelayFileOpen 1 Preference variables located in Tcl files UM 287 Preference variables located in Tcl files ModelSim Tcl preference variables give you control over fonts colors prompts window positions and other simulator window characteristics Preference files which contain Tcl commands that set preference variables are loaded before any windows are created and so will affect all windows For complete documentation on Tcl preference variables see the following URL http www model com resources pref_variables frameset htm When ModelSim is invoked for the first time default preferences are loaded from the pref tcl file See System initialization UM 27 for more details Customized vari
34. simulated All entities configurations and modules that exist in the specified library are displayed in the list box Architectures can be viewed by selecting the box before any name ModelSim User s Manual Simulating with the graphic interface UM 219 e Simulate lt configuration gt lt module gt lt entity gt lt architecture gt Specifies the design unit s to simulate You can simulate several Verilog top level modules or a VHDL top level design unit in one of three ways 1 Type a design unit name configuration module or entity into the field separate additional names with a space Specify library design units with the following syntax lt library_name gt lt design_unit gt 2 Click on a name in the Design Unit list below and click the Add button 3 Leave this field blank and click on a name in the Design Unit list single unit only e Simulator Resolution time lt multiplier gt lt time_unit gt The drop down menu sets the simulator time units original default is ns Simulator time units can be expressed as any of the following Simulation time units Ifs 10fs or 100fs femtoseconds Ips 10ps or 100ps picoseconds Ins 10ns or 100ns nanoseconds lus 10us or 100us microseconds lms 10ms or 100ms milliseconds lsec 10sec or 100sec seconds See also Selecting the time resolution UM 46 ModelSim User s Manual UM 220 7 Graphic Interface
35. top p HASSIGN H15 ftop c sD line__34 top c s1 line__34 cout top c s2 line__34 ftop c s3 line__34 signal net register process Link to active cursor in Wave window In versions 5 5 and later the value of a signal net or register in the Dataflow window is linked to the active cursor in the Wave window As you move the active cursor in the Wave window the value of the signal net or register in the Dataflow window will update ModelSim User s Manual UM 136 7 Graphic Interface Dataflow window menu bar The following menu commands and button options are available from the Dataflow window menu bar File menu Save Postscript save the current dataflow view as a Postscript file see Saving the Dataflow window as a Postscript file UM 138 Selection Selection gt Follow Selection updates the Dataflow window when the Process window UM 152 or Signals window UM 155 changes Selection gt Fix Selection freezes the view selected from within the Dataflow window Close close this copy of the Dataflow window Window menu Initial Layout restore all windows to the size and placement of the initial full screen layout Cascade cascade all open windows Tile Horizontally tile all open windows horizontally Tile Vertically tile all open windows vertically Icon Children icon all but the Main window Icon All icon all windows Deicon All
36. top pdata LLLLLELLI LEZ Z ss a top stw 0 top sstrb 1 top stdy 1 top saddr ooo00000 top sdata LELLLLIL IL LLLE el 900 ns 425 ns ziya gt A Ons to 815 ns Pathname pane The pathname pane displays signal pathnames Signals can be displayed with full pathnames as shown here or with only the leaf element displayed You can increase top clk the size of the pane by clicking and dragging on the right top prwy border The selected signal is highlighted top pstrb The white bar along the left margin indicates the selected top prdy dataset see Splitting Wave window panes UM 190 top paddr top pdata Htop srw top sstrb top srdy top saddr top sdata ModelSim User s Manual Wave window UM 179 Values pane A values pane displays the values of the displayed signals The radix for each signal can be symbolic binary octal decimal unsigned hexadecimal ASCII or default The default radix can be set by selecting Options gt Simulation Main window see Setting default simulation options UM 226 The data in this pane is similar to that shown in the Signals window UM 155 except that the values change dynamically whenever a cursor in the waveform pane below is moved Waveform pane The waveform pane displays the waveforms that correspond to the displayed signal pathnames It also displays up to 20 cursors Signal values can be displayed in analog
37. vital2 2b option and by mapping library vital to lt install_dir gt modeltech vital2 2b ModelSim VITAL compliance A simulator is VITAL compliant if it implements the SDF mapping and if it correctly simulates designs using the VITAL packages as outlined in the VITAL Model Development Specification ModelSim is compliant with the IEEE 1076 4 VITAL ASIC Modeling Specification In addition ModelSim accelerates the VITAL_Timing and VITAL_Primitives packages The procedures in these packages are optimized and built into the simulator kernel By default vsim CR 168 uses the optimized procedures The optimized procedures are functionally equivalent to the IEEE 1076 4 VITAL ASIC Modeling Specification VITAL v3 0 VITAL compliance checking ModelSim User s Manual If you are using VITAL 2 2b you must turn off the compliance checking either by not setting the attributes or by invoking vcom CR 129 with the option novitalcheck Compiling and Simulating with accelerated VITAL packages UM 53 Compiling and Simulating with accelerated VITAL packages vcom CR 129 automatically recognizes that a VITAL function is being referenced from the ieee library and generates code to call the optimized built in routines Invoke with the novital option if you do not want to use the built in VITAL routines To exclude all VITAL functions use novital all vcom novital all design vhd To exclude selected VITAL functions use one or more novital
38. which refers to the last element in the list Ireplace list_name first last val1 val2 replaces elements first through last with val1 val2 etc Two other commands Isearch and Isort are also available for list manipulation See the Tcl man pages Help gt Tcl Man Pages for more information on these commands ModelSim Tcl commands These additional commands enhance the interface between Tcl and ModelSim Only brief descriptions are provided here for more information and command syntax see the Commands CR 25 Command Description alias CR 39 creates a new Tcl procedure that evaluates the specified commands used to create a user defined alias find CR 74 locates incrTcl classes and objects Ishift CR 83 takes a Tcl list as argument and shifts it in place one place to the left eliminating the Oth element Isublist CR 84 returns a sublist of the specified Tcl list that matches the specified Tcl glob pattern project CR 96 echoes to the Main window the current names and values of all environment variables ModelSim User s Manual ModelSim Tcl time commands Conversions Relations ModelSim Tcl time commands UM 263 ModelSim Tcl time commands make simulator time based values available for use within other Tcl procedures Time values may optionally contain a units specifier where the intervening space is also optional If the space is present the value must be quoted e g
39. window with the error highlighted ModelSim OF Xx File Edit Design View Project Run Compare Macro Options Window Help El Zl feval compile Main vcom work test 87 explicit novital nowarn 1 f adder vhd nowarn 2 nowarn 3 nowarn 4 nowarn 5 E modelsim55_se exam ples adder vhd fa counter vhd f Model Technology ModelSim SE EE vecom 5 5 Alpha Compiler 20 00 07 Sep 13 2000 Loading package standard Loading package std_logic_1164 ae fi source_edit adder yhd Compiling entity adder Compiling architecture rtl of oor File Edit Object Options Window ERROR Could not find test gate 7 Ba erT ERROR E modelsim55_se examples ad oe j 3 amp d LPS d expands hame work gates description of adder using componen ERROR E modelsim5S_se examples a field gates ROP F frandeleimA se evarnles fad lt No Design Loaded gt architecture structural of adder is signal xorl_out andl out andZ_ out orl out std_logic double click on the error in the Main window and the error is highlighted and ready to edit in the Source window xorl xorg port mapt inl gt a in gt bh outl gt xorl_out et ee nun man e man ModelSim User s Manual Compiling with the graphic interface UM 213 Setting default compile options Select Options gt Compile Main window to bring up the Compiler Options dialog box shown below
40. 141 Prop menu Display Props set display properties for all items in the window delta settings trigger on selection strobe period label size and dataset prefix Signal Props set label radix trigger on off and field width for the selected item Window menu Initial Layout restore all windows to the size and placement of the initial full screen layout Cascade cascade all open windows Tile Horizontally tile all open windows horizontally Tile Vertically tile all open windows vertically Icon Children icon all but the Main window Icon All icon all windows Deicon All deicon all windows lt window_name gt list of the currently open windows select a window name to switch to or show that window if it is hidden when the source window is available the source file name is also indicated open additional windows from the View menu UM 128 in the Main window ModelSim User s Manual UM 142 7 Graphic Interface Setting List window display properties Before you add items to the List window you can set the window s display properties To change when and how a signal is displayed in the List window select Prop gt Display Props List window The resulting Modify Display Properties dialog box contains options for Trigger Settings and Window Properties Window Properties tab Modify Display Properties list Window Properties Tigges Signal Names fo Path E
41. 19 or you can type them in ModelSim User s Manual UM 232 7 Graphic Interface Graphic interface commands The following commands provide control and feedback during simulation Only brief descriptions are provided here for more information and command syntax see the ModelSim Command Reference Window control and Description feedback commands batch_mode CR 40 returns a if ModelSim is operating in batch mode otherwise returns a 0 it is typically used as a condition in an if statement configure CR 51 invokes the List or Wave widget configure command for the current default List or Wave window notepad CR 89 a simple text editor used to view and edit ASCII files or create new files write preferences CR 191 saves the current GUI preference settings to a Tcl preference file ModelSim User s Manual UM 233 8 Standard Delay Format SDF Timing Annotation Chapter contents Specifying SDF files for simulation UM 234 Instance specification UM 234 SDF specification with the GUI UM 235 Errors and warnings UM 235 VHDL VITAL SDF UM 236 SDF to VHDL generic mahiak UM 236 Resolving errors UM 237 Verilog SDF UM 238 The sdf_annotate syste wk UM 238 SDF to Verilog construct matching UM 239 Optional edge specifications UM 241 Optional conditions UM 242 Rounded timing values UM 243 SDF for Mixed VHDL and Verilog Designs UM 244 Interconnect delays UM 244 Troubleshooting
42. 9 do echo Removing Sf exec rm Sf Provide file root argument and load_wave restores all saved widows Default file root is wave proc load_wave fileroot wave global vsimPriv foreach f lsort glob fileroot 1 9 do echo Loading Sf view new wave do f if file exists windowSet_Sfileroot do do windowSet_S fileroot do ModelSim User s Manual Macros DO files UM 269 Macros DO files ModelSim macros also called DO files are simply scripts that contain ModelSim and optionally Tcl commands You invoke these scripts with the Macro gt Execute Macro Main window menu selection or the do command CR 64 Creating DO files You can create DO files like any other Tcl script by typing the required commands in any editor and saving the file Alternatively you can save the Main window transcript to a DO file see Saving the Main window transcript file UM 125 The following is a simple DO file that was saved from the Main window transcript It is used in the dataset exercise in the ModelSim Tutorial This DO file adds several signals to the Wave window provides stimulus to those signals and then advances the simulation add wave ld add wave rst add wave clk add wave d add wave q force freeze clk 0 0 1 50 ns r 100 force rst 1 force rst 0 10 force ld 0 force d 1010 run 1700 force ld 1 run 100 force ld 0 run 400 force rst 1 run 200 force rst 0 10 run 1
43. A o Deltas ExpandDeltas Collapse Deltas No Deltas Trigger On IV Signals Strobe Trigger Gating Fe N Use Expression Builder Expression ooo On Duration ons o OK Cancel Apply Check the Trigger Gating Expression check box Then click on Use Expression Builder Select the signal in the List window that you want to be the enable signal by Strobe Period 0 ns First Strobe at 0 ns ModelSim User s Manual UM 306 C Tips and Techniques ModelSim User s Manual clicking on its name in the header area of the List window Then click Insert Selected Signal and rising in the Expression Builder Expression Builder OO Expression Builder Insert Selected Signal me we fof mele os I mja ef sje AA Clear Save Test Ok Cancel Click OK to close the Expression Builder You should see the name of the signal plus rising added to the Expression entry box of the Modify Display Properties dialog box Leave the On Duration field zero for now Click the OK button If you already have simulation data in the List window the display should immediately switch to showing only those cycles for which the gating signal is rising If that isn t quite what you want you can go back to the expression builder and play with it until you get it the way you want it If you want the enable signal to work like a One Shot that would di
44. Annotation for details Verilog models may contain both distributed delays and path delays The delays on primitives UDPs and continuous assignments are the distributed delays whereas the port to port delays specified in specify blocks are the path delays These delays interact to determine the actual delay observed Most Verilog cells use path delays exclusively with the distributed delays set to zero For example module and2 y a b input a b output y and y a b specify a gt y 5 b gt y 5 endspecify endmodule In the above two input and gate cell the distributed delay for the and primitive is zero and the actual delays observed on the module ports are taken from the path delays This is typical for most cells but a complex cell may require non zero distributed delays to work properly Even so these delays are usually small enough that the path delays take priority over the distributed delays The rule is that if a module contains both path delays and distributed delays then the larger of the two delays for each path shall be used as defined by the IEEE Std 1364 This is the default behavior but you can specify alternate delay modes with compiler directives and options These options and directives are compatible with Verilog XL Compiler delay mode options take precedence over delay mode directives in the source code ModelSim User s Manual UM 76 5 Verilog Simulation ModelSim User s Manu
45. Baw Scaling Orientation C Fixed 500 ns per page Portrait Fitto fi page s wide Landscape Ok Cancel Paper Size Select your output page size from a number of options also choose the paper width and height Margins Specify the page margins changing the Margin will change the Scale and Page specifications Label width Specify Auto Adjust to accommodate any length label or set a fixed label width Cursors Turn printing of cursors on or off Grid Turn printing of grid lines on or off ModelSim User s Manual UM 210 7 Graphic Interface e Color Select full color printing grayscale or black and white e Scaling Specify a Fixed output time width in nanoseconds per page the number of pages output is automatically computed or select Fit to to define the number of pages to be output based on the paper size and time settings if set the time width per page is automatically computed e Orientation Select the output page orientation Portrait or Landscape ModelSim User s Manual Compiling with the graphic interface UM 211 Compiling with the graphic interface You can use a project or the Compile HDL Source Files dialog box to compile VHDL or Verilog designs For information on compiling in a project see Getting started with projects UM 18 To open the Compile HDL Source Files dialog select the Compile button Main window or Design gt Compile ModelSim Fi
46. CR 76 after the specified period of simulation time e OK When you click the OK button a force command CR 76 is issued with the parameters you have set and is echoed in the Main window If more than one signal is selected to force the next signal down appears in the dialog box each time the OK button is selected Unique force parameters can be set for each signal Adding HDL items to the Wave and List windows or a WLF file Before adding items to the List or Wave window you may want to set the window display properties see Setting List window display properties UM 142 Once display properties have been set you can add items to the windows or WLF file in several ways Adding items with the Signals window View menu Use the View menu with either the Wave List or Log selection to add HDL items to the Wave window UM 178 List Wave gt window UM 139 or a wave log format List gt WLF file respectively Log gt Selected Signals Signals in Region Signals in Design The WLF file is written as an archive file in binary format and is used to drive the List and Wave windows at a later time Once signals are added to the WLF file they cannot be removed If you begin a simulation by invoking vsim CR 168 with the view lt WLF_fileame gt option ModelSim reads the WLF file to drive the Wave and List windows Filter Choose one of the following options ModelSim opens the target window for you e Sel
47. Drag and drop of HDL items is possible between the following windows Using the left mouse button click and release to select an item then click and hold to drag it e Drag items from these windows Dataflow List Signals Source Structure Variables and Wave windows e Drop items into these windows Dataflow List and Wave windows gt Note Drag and drop works to rearrange items within the List and Wave windows as well Command history Avoid entering long commands twice use the down and up keyboard arrows to move through the command history for the current simulation ModelSim User s Manual Common window features UM 119 Automatic window updating Selecting an item in the following windows automatically updates other related ModelSim windows as indicated below Select an item in this window To update these windows Dataflow window UM 135 Process window UM 152 with a process selected in the center of Signals window UM 155 the window Source window UM 163 Structure window UM 172 Variables window UM 175 Process window UM 152 Dataflow window UM 135 Signals window UM 155 Structure window UM 172 Variables window UM 175 Signals window UM 155 Dataflow window UM 135 Structure window UM 172 Process window UM 152 Signals window UM 155 Source window UM 163 Finding names and locating cursors Find HDL ite
48. Important You must end a simulation session with a quit or quit sim command in order to produce a valid WLF file If you don t end the simulation in this manner the WLF file will not close properly and ModelSim will issue the error message bad magic number when you try to open the dataset in subsequent sessions WLF files datasets UM 105 Opening datasets To open a dataset select either File gt Open gt Dataset Main window or File gt Open Dataset Wave window Dataset Pathname O Browse Logical Name for Dataset The Open Dataset dialog box includes the following options Dataset Pathname Identifies the path and filename of the WLF file you want to open e Logical Name for Dataset This is the name by which the dataset will be referred By default this is the name of the WLF file A Important You must end a simulation session with a quit or quit sim command in order to produce a valid WLF file If you don t end the simulation in this manner the WLF file will not close properly and ModelSim will issue an error when you try to open the dataset in subsequent sessions ModelSim User s Manual UM 106 6 WLF files datasets and virtuals Viewing dataset structure In versions 5 5 and later each dataset you open creates a Structure tab in the Main window workspace The tab is labeled with the name of the dataset and displays the same data as the Structure window UM 172 T
49. Limitations e When mirroring the value of a Verilog register wire onto a VHDL signal the VHDL signal must be of type bit bit_vector std_logic or std_logic_vector e Mirroring slices or single bits of a vector is not supported If you do reference a slice or bit of a vector the function will assume that you are referencing the entire vector ModelSim User s Manual UM 56 4 VHDL Simulation to_real ModelSim User s Manual Example library modelsim_lib use modelsim_lib util all entity top is end architecture signal top_sigl std_logic begin spy_process process begin init_signal_spy top uut inst1 sigl top_sigl 1 wait end process spy_process end In this example the value of top uut inst1 sigi will be mirrored onto top_sigl to_real converts the physical type time value into a real value with respect to the current simulator resolution The precision of the converted value is determined by the simulator resolution For example if you were converting 1900 fs to a real and the simulator resolution was ps then the real value would be 2 0 i e 2 ps Syntax realval to_real timeval Returns Name Type Description realval real The time value represented as a real with respect to the simulator resolution Arguments Name Description timeval The value of the physical type time Related functions get_resolution UM 54 to_time UM 57
50. M 153 JM 155 JM 156 JM 157 JM 158 JM 159 JM 160 JM 160 JM 162 JM 163 M 164 M 166 M 168 M 170 M 170 M 170 M 171 M 172 M 173 M 174 JM 175 E CCEE 4 4 4 4 4 4 4 4 ecaagocad ae 4 4 4 4 4 4 Ssgoocgccgcs cocos E The Variables window menu bar Wave window Pathname pane Values pane Waveform pane Cursor panes HDL items you can view Adding HDL items in the Wave window The Wave window menu bar The Wave window toolbar Using Dividers Splitting Wave window panes f Combining items in the Wave window Editing and formatting HDL items in the Wave window Setting Wave window display properties Setting signal breakpoints Finding items by name or value in the Wave window Using time cursors in the Wave window Finding a cursor Making cursor measurements Zooming changing the waveform display range Saving zoom range and scroll position with bookmarks Wave window mouse and keyboard shortcuts Saving waveforms Compiling with the graphic interface 5 Locating source errors during compilation Setting default compile options Simulating with the graphic interface Design selection tab VHDL settings tab Verilog settings tab Libraries settings tab SDF settings tab SDF options Setting default shoiilsioi options ModelSim tools The GUI Fxoresicd Builder 5 Graphic interface commands 8 Standard Delay Format SDF Timing Annotation
51. Main window command history out ConcurrentFileLimit any positive controls the number of VHDL files open 40 integer concurrently this number should be less than the current limit setting for max file descriptors 0 unlimited DatasetSeparator any single the dataset separator for fully rooted character contexts for example sim top must not be the same character as PathSeparator DefaultForceKind freeze drive or defines the kind of force used when not drive for deposit otherwise specified resolved signals freeze for unresolved signals ModelSim User s Manual Preference variables located in INI files UM 281 Variable name Value range Purpose Default DefaultRadix symbolic binary any radix may be specified as a number or symbolic octal decimal name i e binary can be specified as binary unsigned or 2 hexadecimal ascii DefaultRestartOptions one or more of sets default behavior for the restart commented force command out nobreakpoint nolist nolog nowave DelayFileOpen 0 1 if 1 open VHDL87 files on first read or off 0 write else open files when elaborated GenerateFormat Any non quoted control the format of a generate statement s__ d string containing label don t quote it at a minimum a s followed by a d IgnoreError 0 1 if 1 ignore assertion errors off 0 IgnoreFailure 0 1 if 1 ignore assertion failures off 0 IgnoreNote 0 1 if 1 ignore ass
52. Manual UM 198 7 Graphic Interface Child Row Margin Specifies the distance in pixels between child signals Waveform Popup Toggles on off the popup that displays when you rest your mouse pointer on a signal or comparison object Dataset Prefix Specifies how signals from different datasets are displayed Always Show Dataset Prefixes All dataset prefixes will be displayed along with the dataset prefix of the current simulation sim Show Dataset Prefixes if 2 or more Displays all dataset prefixes if 2 or more datasets are displayed sim is the default prefix for the current simulation Never Show No Dataset Prefixes No dataset prefixes will be displayed This selection is useful if you are running only a single simulation Sorting a group of HDL items Select Edit gt Sort to sort the items in the pathname and values panes Setting signal breakpoints ModelSim User s Manual You can set signal breakpoints a k a when breakpoints see the when command CR 181 or Setting signal breakpoints UM 160 for more details using a pop up menu Start by selecting a signal and then clicking your second mouse button Select Signal Breakpoints from the pop up menu and you ll see six items Add Creates a signal breakpoint on the selected signal Edit Breakpoints Opens the Edit When dialog See Setting signal breakpoints UM 160 for more information Edit All Breakpoints Opens the Breakpoints dialog See Setting file
53. ModelSim User s Manual UM 22 2 Projects and system initialization Step 3 Compile the files 1 To compile the files right click in the Project tab and select Compile All You can also select Project gt Compile All from the menu bar vi Modeiearil ModelSim gt a counter v T uc tcounter v Compile Out of Date Files Add file to Project Sort by Compile Order Select All Close Project Project ba Project test lt No Design Loaded gt lt No Context gt f An asterisk next to a file denotes that that file has changed since the last compilation Compile Out of Date Files will compile only files that have changed 2 Once compilation is finished click the Library tab and you ll see the two compiled designs ModelSim ojx File Edit nate view Project Run Compare Macro sls Window Help aif Top level modules aj f test counter vlog work work E modelsim55_011801 exam ples counter v Model Technology ModelSim SE EE vlog 5 5 Beta 4 Compiler 2001 01 Jan 18 2001 Compiling module counter Top level modules counter vsim work counter vsim work counter Loading work counter quit sim Library work M counter M test_counter ModelSim gt Project test lt No Design Loaded gt lt No Context gt ai a ModelSim User s Manual Getting started with projects UM 23 Step 4 Simu
54. OK accepts the changes made and closes the dialog box Apply makes the changes with the dialog box open so you can test your settings Cancel closes the dialog box and makes no changes The options found on each tab of the dialog box are detailed below Changes made in the Compiler Options dialog box become the default for all future simulations VHDL compiler options tab Compiler Options VHDL Wetlog I Use 1993 Language Syntax T Disable loading messages T Don t put debugging info in library I Show source lines with errors V Use explicit declarations only gt Check for Flag Warnings On T Synthesis IV Unbound component IV Vital Compliance I Process without a WAIT statement Optimize for M Null Range I StdLogicl164 IV No space in time literal e g 5ns Vv Vital IV Multiple drivers on unresolved signals OK Cancel Apply Use 1993 language syntax Specifies the use of VHDL93 during compilation The 1987 standard is the default Same as the 93 switch for the veom command CR 129 Edit the VHDL93 UM 286 variable in the modelsim ini file to set a permanent default Don t put debugging info in library Models compiled with this option do not use any of the ModelSim debugging features Consequently your user will not be able to see into the model This also means that you cannot set breakpoints or single step within this code Don t compile with this option until you re done deb
55. Simulation Library usage ModelSim User s Manual All modules and UDPs in a Verilog design must be compiled into one or more libraries One library is usually sufficient for a simple design but you may want to organize your modules into various libraries for a complex design If your design uses different modules having the same name then you are required to put those modules in different libraries because design unit names must be unique within a library The following is an example of how you may organize your ASIC cells into one library and the rest of your design into another ole vlib work vlib asiclib vlog work asiclib and2 v or2 v ole oe Compiling module and2 Compiling module or2 Top level modules and2 or2 vlog top v Compiling module top Top level modules top Note that the first compilation uses the work asiclib option to instruct the compiler to place the results in the asiclib library rather than the default work library Since instantiation bindings are not determined at compile time you must instruct the simulator to search your libraries when loading the design The top level modules are loaded from the library named work unless you specify an alternate library with the lib option All other Verilog instantiations are resolved in the following order e Search libraries specified with Lf options in the order they appear on the command line e Search the library specified in the Verilo
56. Source window UM 164 Structure window UM 173 ModelSim User s Manual tearing off or pinning menus UM 120 Variables window UM 176 Wave window UM 182 Messages bad magic number UM 104 echoing CR 67 redirecting UM 282 turning off assertion messages UM 285 turning off warnings from arithmetic packages UM 285 MGC_LOCATION_MAP variable UM 275 mnemonics assigning to signal values CR 159 MODEL_TECH environment variable UM 275 MODEL_TECH_TCL environment variable UM 275 Modeling memory in VHDL UM 301 modelsim command CR 85 ModelSim commands CR 25 CR 187 comments in commands CR 6 MODELSIM environment variable UM 275 modelsim ini default to VHDL93 UM 286 hierarchial library mapping UM 284 opening VHDL files UM 286 setting restart command defaults UM 286 to specify a startup file UM 285 turning off arithmetic warnings UM 285 turning off assertion messages UM 285 using environment variables in UM 284 using to create a transcript file UM 284 using to define force command default UM 285 using to delay file opening UM 286 modelsim tcl file UM 287 modelsim_lib UM 54 MODELSIM_TCL environment variable UM 275 Mouse shortcuts Main window UM 133 UM 293 Source window UM 293 Wave window UM 205 UM 291 MPF file loading from the command line UM 26 MTITF_LIMIT environment variable UM 275 Multiple drivers on unresolved signal UM 214 multiple simulations UM 103 multi source interconnect delays CR 175 N n simulator state variable UM 289 Name
57. Use a qualified expression to specify the type as in WRITE L string hello e Call a procedure that is not overloaded as in WRITE_STRING L hello The WRITE_STRING procedure simply defines the value to be a STRING and calls the WRITE procedure but it serves as a shell around the WRITE procedure that solves the overloading problem For further details refer to the WRITE_STRING procedure in the io_utils package which is located in the file modeltech examples io_utils vhd ModelSim User s Manual UM 50 4 VHDL Simulation Reading and writing hexadecimal numbers The reading and writing of hexadecimal numbers is not specified in standard VHDL The Issues Screening and Analysis Committee of the VHDL Analysis and Standardization Group ISAC VASG has specified that the TextIO package reads and writes only decimal numbers To expand this functionality ModelSim supplies hexadecimal routines in the package io_utils which is located in the file nodeltech examples fio_utils vhd To use these routines compile the io_utils package and then include the following use clauses in your VHDL source code use std textio all use work io_utils all Dangling pointers Dangling pointers are easily created when using the TextIO package because WRITELINE de allocates the access type pointer that is passed to it Following are examples of good and bad VHDL coding styles Bad VHDL because L1 and L2 both point to the same buff
58. VCD file name with the ved file command CR 122 and add items to the file with the ved add command CR 119 VSIM 1 gt vcd file myvcdfile vcd VSIM 2 gt vcd add test_counter dut VSIM 3 gt run VSIM 4 gt quit f There will now be a VCD file in the working directory ModelSim User s Manual UM 250 9 Value Change Dump VCD Files A VCD file from source to output The following example shows the VHDL source a set of simulator commands and the resulting VCD output VHDL source code The design is a simple shifter device represented by the following VHDL source code library IEEE use IEEE STD_LOGIC_1164 all entity SHIFTER_MOD is port CLK RESET data_in IN STD_LOGIC Q INOUT STD_LOGIC_VECTOR 8 downto 0 END SHIFTER_MOD architecture RTL of SHIFTER_MOD is begin process CLK RESET begin if RESET 1 then Q lt others gt 0 elsif CLK event and CLK 1 then Q lt Q Q left 1 downto 0 amp data_in end if end process end VCD simulator commands At simulator time zero the designer executes the following commands and quits the simulator at time 1200 ved files output vcd ved add r force reset 1 0 force data_in 0 0 force clk 0 0 run 100 force clk 1 0 0 50 repeat 100 run 100 vcd off force reset 0 0 force data_in 1 0 run 100 vcd on run 850 force reset 1 0 run 50 ved checkpoint ModelSim User s Manual VCD output A VCD file fro
59. Variables or Variables in Region in the Wave window UM 178 List window UM 139 or WLF file ModelSim User s Manual Window menu Variables window UM 177 Initial Layout restore all windows to the size and placement of the initial full screen layout Cascade cascade all open windows Tile Horizontally tile all open windows horizontally Tile Vertically tile all open windows vertically Icon Children icon all but the Main window Icon All icon all windows Deicon All deicon all windows lt window_name gt list of the currently open windows select a window name to switch to or show that window if it is hidden when the source window is available the source file name is also indicated open additional windows from the View menu UM 128 in the Main window ModelSim User s Manual UM 178 7 Graphic Interface Wave window The Wave window like the List window allows you to view the results of your simulation In the Wave window however you can see the results as HDL waveforms and their values The Wave window is divided into a number of window panes All window panes in the Wave window can be resized by clicking and dragging the bar between any two panes waye default File Edit Cursor Zoom Compare Bookmark Format Window SUS sBB RH eT RIA lesi 3H top clk 0 top prw 0 0 1 iM inde top pstrb top prdy top paddr oo000000 i 00000010 y0
60. Welcome to ModelSim screen that opens the first time you start ModelSim If this screen is not available you can enable it by selecting Help gt Enable Welcome Main window Welcome to ModelSim Torx Create a New Project Specify a name for the new project and it will be created and opened Create a Project T Do not show this dialog again You can also use the File gt New gt Project Main window command to create a new project 2 Clicking the Create a Project button opens the Create Project dialog box Create Project Project Name test gt Project Location E modelsim55 proj Browse m Default Library Name work Ok Cancel ModelSim User s Manual UM 20 2 Projects and system initialization 3 Specify a Project Name and Project Location The location is where the project mpf file and any copied source files will be stored You can leave the Default Library Name set to work or specify a different name if desired The name that is specified will be used to create a working library subdirectory within the Project Location After selecting OK you will see a blank Project tab in the workspace area of the Main window You can hide or show the workspace at any time using the View gt Hide Show Workspace command l ModelSim iofx Fie Edit Design View Project Run Macro Options Window Help XI Reading E modelsim55_se win32
61. and makes no changes The options found on each tab are detailed below gt Note Changes made in the Simulation Options dialog box are the default for the current simulation only Options can be saved as the default for future simulations by editing the simulator control variables in the modelsim ini file the variables to edit are noted in the text below You can use Notepad see notepad command CR 89 to edit the variables in modelsim ini if you wish See also Projects and system initialization UM 15 for more information Default settings tab M Simulation Options Default Radix Suppress Warnings Symbolic T From Synopsys Packages C Binary I From IEEE Numeric Std Packages C Octal Deana Default Run Default Force Type jo ns C Unsigned C Freeze Hexadecimal TEE Drive Iteration Limit C ASCII 1000 2 Deposit OK Cancel Apply The Defaults tab includes these options Default Radix Sets the default radix for the current simulation run You can also use the radix CR 101 command to set the same temporary default A permanent default can be set by editing the DefaultRadix UM 281 variable in the modelsim ini file The chosen radix is used for all commands force CR 76 examine CR 71 change CR 50 are examples and for displayed values in the Signals Variables Dataflow List and Wave windows ModelSim User s Manual Simulating with the graphic interface UM 227 Su
62. are valid with one exception the run command CR 107 cannot be used The Edit All Breakpoints command opens the Breakpoints dialog box See Setting file line breakpoints UM 168 for details ModelSim User s Manual UM 162 7 Graphic Interface Defining clock signals Select Edit gt Clock to define clock signals by Name Period Duty Cycle Offset and whether the first rising edge is rising or falling You can also specify a simulation period after which the clock definition should be cancelled Define Clock Clock Name EIEC tana Offset 0 First Edge Duty 50 Rising Period 100 C Faling Cancel Logic Values High 1 Low 0 OK Cancel For clock signals starting on the rising edge the definition for Period Offset and Duty Cycle is as follows Period High Value Low Value Offset High Time Duty Cycle High Time Period If the signal type is std_logic std_ulogic bit verilog wire verilog net or any other logic type where 1 and 0 are valid then 1 is the default High Value and 0 is the default Low Value For other signal types you will need to specify a High Value and a Low Value for the clock ModelSim User s Manual Source window UM 163 Source window The Source window allows you to view and edit your HDL source code When you first load a design the source file will display automatically if the Source window is open Alternatively you can selec
63. both VHDL and Verilog compile options Simulation set various simulation options Edit Preferences set various preference variables see http www model com resources pref_variables frameset htm Save Preferences save current ModelSim settings to a Tcl preference file http www model com resources pref_variables frameset htm Window menu Initial Layout restore all windows to the size and placement of the initial full screen layout Cascade cascade all open windows Tile Horizontally tile all open windows horizontally Tile Vertically tile all open windows vertically Icon Children icon all but the Main window Icon All icon all windows Deicon All deicon all windows ModelSim User s Manual UM 130 7 Graphic Interface lt window_name gt list of the currently open windows select a window name to switch to or show that window if it is hidden when the source window is available the source file name is also indicated open additional windows from the View menu UM 128 in the Main window Help menu About ModelSim display ModelSim application information e g software version Release Notes view current release notes with the ModelSim notepad CR 89 Enable Welcome enable the Welcome screen for starting a new project or opening an existing project when ModelSim is initiated Welcome Menu open the Welcome screen Info
64. case sensitivity VHDL vs Verilog CR 11 Names alternative signal names in the List window label CR 33 alternative signal names in the Wave window la bel CR 36 Negative pulses driving an error state CR 176 UM 74 negative timing checks UM 80 Nets adding to the Wave and List windows UM 159 applying stimulus to CR 76 displaying drivers of CR 65 displaying values in Signals window UM 155 examining values CR 71 forcing signal and net values UM 158 saving values as binary log file UM 159 viewing waveforms UM 178 Next and previous edges finding UM 205 UM 292 No space in time literal UM 214 NoCaseStaticError ini file variable UM 279 NoDebug ini file variable WCOM UM 279 NoDebug ini file variable VLOG UM 280 noforce command CR 86 NoIndexCheck ini file variable UM 28 1 nolog command CR 87 NoOthersStaticError ini file variable UM 279 notepad command CR 89 Notepad windows text editing UM 133 UM 293 noview command CR 90 NoVital ini file variable UM 279 NoVitalCheck ini file variable UM 279 Now simulator state variable UM 289 now simulator state variable UM 289 special considerations UM 290 nowhen command CR 91 numeric_bit package UM 41 numeric_std package UM 41 NumericStdNoWarnings ini file variable UM 282 O onbreak command CR 92 onElabError command CR 93 onerror command CR 94 Optimize for std_logic_1164 UM 215 Optimize_1164 ini file variable UM 279 order of event changing in Verilog CR 162 order of events
65. command ModelSim User s Manual UM 168 7 Graphic Interface Setting file line breakpoints ModelSim User s Manual You can set breakpoints three different ways e Using the command line see the bp CR 46 breakpoint command for details e Using your mouse in the Source window e Using the Edit gt Breakpoints menu selection Setting breakpoints with your mouse To set a breakpoint with your mouse click on a green line number at the left side of the window breakpoints can be set only on executable lines The breakpoints are toggles click once to create the colored dot click again to disable or enable the breakpoint To delete the breakpoint completely click the colored dot with your right mouse button and select Remove Breakpoint Setting breakpoints with the Edit gt Breakpoints command Selecting Edit gt Breakpoints Source window opens the dialog box shown below Breakpoint s Amp E modelsim55_se examples mixedHDL proc v 23 bp E modelsim55_se examples mixedHDL proc v 43 Add BP V when label 11 cond top sdata echo Break on top sdata stop Add when V when label 15 cond top srw echo Break on top srw stop Edit Selected I when abel 26 cond top p read a echo Break on top p read a Delete Selected Delete All BP The Breakpoints dialog box allows you to create and manage both file line and signal breakpoints a k a when breakpoints For details on signal break
66. command CR 117 Transcript file redirecting with 1 CR 170 saving UM 125 UM 284 TranscriptFile variable in ini file UM 282 Tree windows VHDL and Verilog items in UM 121 viewing the design hierarchy UM 121 TreeUpdate command CR 189 Triggers setting in the List window UM 143 UM 305 TSCALE disabling warning CR 175 TSSI CR 194 tssi2mti command CR 118 type converting real to time UM 57 converting time to real UM 56 U u UM 66 Jnbound Component UM 214 UnbufferedOutput ini file variable UM 282 Use 1076 1993 language standard UM 213 Use clause specifying a library UM 40 Use explicit declarations only UM 214 User defined bus UM 110 UM 121 UserTimeUnit ini file variable UM 282 util package UM 54 ce V v CR 164 UM 66 Values describe HDL items CR 62 examine HDL item values CR 71 of HDL items UM 170 replacing signal values with strings CR 159 Variable settings report CR 14 Variables environment variables UM 275 LM_LICENSE_FILE UM 275 loading order at ModelSim startup UM 27 personal preferences UM 274 precedence between ini and tcl UM 288 setting environment variables UM 275 simulator state variables current settings report UM 274 iteration number UM 289 name of entity or module as a variable UM 289 resolution UM 289 simulation time UM 289 Variables window UM 175 Variables HDL changing value of on command line CR 50 changing value of with the GUI UM 175 describing CR 62 examining values CR 71 Variables
67. defined by the IEEE Std 1364 and it is recommended that you obtain this specification as a reference manual In addition to the functionality described in the IEEE Std 1364 ModelSim Verilog includes the following features e Standard Delay Format SDF annotator compatible with many ASIC and FPGA vendor s Verilog libraries ModelSim User s Manual UM 60 5 Verilog Simulation Value Change Dump VCD file extensions for ASIC vendor test tools Dynamic loading of PLI VPI applications Compilation into retargetable executable code Incremental design compilation Extensive support for mixing VHDL and Verilog in the same design including SDF annotation Graphic Interface that is common with ModelSim VHDL Extensions to provide compatibility with Verilog XL The following IEEE Std 1364 functionality is partially implemented in ModelSim Verilog Verilog Procedural Interface VPI see lt install_dir gt modeltech docs technotes Verilog_VPI note for details Many of the examples in this chapter are shown from the command line For compiling and simulating within a project or ModelSim s GUI see Getting started with projects UM 18 Compiling with the graphic interface UM 211 Simulating with the graphic interface UM 217 Model Sim variables ModelSim User s Manual Several variables are available to control simulation provide simulator state feedback or modify the appearance of the ModelSim GUI To take effect som
68. delays UM 244 mixed VHDL and Verilog designs UM 244 specification with the GUI UM 235 troubleshooting UM 245 Verilog sdf_annotate system task UM 238 optional conditions UM 242 optional edge specifications UM 241 rounded timing values UM 243 SDF to Verilog construct matching UM 239 VHDL Resolving errors UM 237 SDF to VHDL generic matching UM 236 Searching List window signal values transitions and names UM 149 values and names UM 119 Verilog libraries UM 64 waveform signal values edges and names UM 170 UM 174 UM 199 searchlog command CR 109 sequencing differences in event order UM 70 Shared objects loading FLI applications see ModelSim FLI Reference manual loading PLI VPI applications UM 89 shift command CR 111 Shortcuts command history CR 7 UM 293 command line caveat CR 7 UM 293 List window UM 150 UM 292 Main window UM 293 Main windows UM 133 Source window UM 293 text editing UM 133 UM 293 Wave window UM 205 UM 291 show command CR 112 Show source lines with errors UM 214 Show_source ini file variable VCOM UM 279 VLOG UM 280 Show_VitalChecksWarning ini file variable UM 279 Show_Warning 1 ini file variable UM 279 Show_Warning ini file variable UM 279 Show_Warning3 ini file variable UM 279 Show_Warning4 ini file variable UM 279 Show_Warning5S ini file variable UM 279 signal breakpoints UM 160 Signal names viewing without hierarchy UM 197 Signal spy UM 55 Signal transitions searching for UM 201 Signals
69. feature of the Wave and List Signal Search dialog boxes and the List trigger properties dialog box It aids in building a search expression that follows the GUI_expression_format CR 16 To locate the Builder select Edit gt Search List or Wave window e select the Search for Expression option in the resulting dialog box e select the Builder button Expression Builder r Expression Expression Builder Insert Selected Signal a The Expression Builder dialog box provides an array of buttons that help you build a GUI expression For instance rather than typing in a signal name you can select the signal in the associated Wave or List window and press Insert Reference Signal in the Expression Builder The result will be the full signal name added to the expression field All Expression Builder buttons correspond to the Expression syntax CR 19 ModelSim tools UM 231 To search for when a signal reaches a particular value Select the signal in the Wave window and click Insert Reference Signal and Then click the value buttons or type a value To evaluate only on clock edges Click the amp amp button to AND this condition with the rest of the expression Then select the clock in the Wave window and click Insert Reference Signal and rising You can also select the falling edge or both edges Operators Other buttons will add operators of various kinds see Expression syntax CR
70. gt run all Hello world VSIM 2 gt quit In this example the simulator was run without the graphic interface by specifying the c option After the design was loaded the simulator command run all was entered meaning to simulate until there are no more simulator events Finally the quit command was entered to exit the simulator By default a log of the simulation is written to the file transcript in the current directory ModelSim User s Manual UM 62 5 Verilog Simulation Incremental compilation ModelSim User s Manual By default ModelSim Verilog supports incremental compilation of designs thus saving compilation time when you modify your design Unlike other Verilog simulators there is no requirement that you compile the entire design in one invocation of the compiler You are not required to compile your design in any particular order because all module and UDP instantiations and external hierarchical references are resolved when the design is loaded by the simulator Incremental compilation is made possible by deferring these bindings and as a result some errors cannot be detected during compilation Commonly these errors include modules that were referenced but not compiled incorrect port connections and incorrect hierarchical references The following example shows how a hierarchical design can be compiled in top down order Contents of top v module top or2 nl aysb 4 and2 n2 nl c endmodule
71. i gt 0 lappend b lindex Sa i incr i 1 This example uses the Tcl for command to copy a list from variable a to variable b reversing the order of the elements along the way set bm for set i expr llength a 1 Si gt 0 incr i 1 lappend b lindex a i This example uses the Tcl foreach command to copy a list from variable a to variable b reversing the order of the elements along the way the foreach command iterates over all of the elements of a list set bn foreach i a set b linsert b 0 i ModelSim User s Manual UM 266 10 Tcl and macros Example 2 ModelSim User s Manual This example shows a list reversal as above this time aborting on a particular element using the Tcl break command set b wi foreach i a if i ZZZ break set b linsert Sb 0 i This example is a list reversal that skips a particular element by using the Tcl continue command set b foreach i a if i ZZZ continue set b linsert b 0 i The last example is of the Tcl switch command switch x a incr t1 b incr t2 CG TINeY 35 This next example shows a complete Tcl script that restores multiple Wave windows to their state in a previous simulation including signals listed geometry and screen position It also adds buttons to the Main window toolbar to ease management of the wave files This example works in ModelSim SE only This file contains procedure
72. in the right pane can be viewed by scrolling For the second listing the item radix for paddr pdata saddr and sdata is now decimal ModelSim User s Manual List window UM 149 Finding items by name in the List window The Find dialog box allows you to search for text strings in the List window Select Edit gt Find List window to bring up the Find dialog box Enter a text string and Find it by searching Find in list x Right or Left through the List window display Find Find Next Specify Name to search Sees the real pathnames of the Field Direction Close items or Label to search their assigned names see Setting List window display properties UM 142 Checking Auto Wrap makes the search continue at the beginning of the window Note that you can change an item s label IV Auto Wrap Setting time markers in the List window Select Markers gt Add Marker List window to tag the selected list line with a marker The marker is indicated by a thin box surrounding the marked line The selected line uses the same indicator but its values are highlighted Delete markers by first selecting the marked line then selecting Markers gt Delete Marker Finding a marker FS list lel Ea File Edit Markers Prop Window eae a er TET top paddr top pdata top saddr toy Add Marker top stw y Delete Marker ftop sstb G topsrdy pooooooo0000001 000000
73. interface provides the window management frame only ModelSim handles all internal window features including menus buttons and scroll bars l ModelSim iof x File Edit Design View a Tompo cali Window Help workspace Library lt No lt No DesignLoaded gt tits Loaded gt transcript The menu bar at the top of the window provides access to a wide variety of simulation commands and ModelSim preferences The toolbar provides buttons for quick access to the many common commands The status bar at the bottom of the window gives you information about the data in the active ModelSim window The menu bar toolbar and status bar are described in detail below ModelSim User s Manual UM 124 7 Graphic Interface Workspace The workspace is available in software versions 5 5 and later It provides convenient access to projects compiled design units and simulation dataset structures It can be hidden or displayed by selecting the View gt Hide Show Workspace command The workspace can display four types of tabs as shown in the graphic below l ModelSim OF Xx File Edit eu view Project Run Saia Macro Options Window Help adder adder structural Ht vsim work adder E xorl xorgfonly Loading E modelsim55_102500 win32 std standard E xor2 xorg only Loading E modelsim55_102500 win32 ieee std_logic_ E and1 andafonly 1164 body 1 Loading work gates E ort orafonly Loading work adder structural
74. is a Tcl variable Instances of NAME denote paths that are determined by an environment variable except MTI_LIB_DIR which is determined by a Tcl variable _ N 3 6 Determines the path to the executable directory modeltech lt platform gt Sets MODEL_TECH to this path unless MODEL_TECH_OVERRIDE exists in which case MODEL_TECH is set to the same value as MODEL_TECH_OVERRIDE Finds the modelsim ini file by evaluating the following conditions use MODELSIM if it exists else use MGC_WD modelsim ini else use modelsim ini else use MODEL_TECH modelsim ini else use MODEL_TECH modelsim ini else use MGC_HOME ib modelsim ini else set path to modelsim ini even though the file doesn t exist Finds the location map file by evaluating the following conditions use MGC_LOCATION_MAP if it exists if this variable is set to no_map ModelSim skips initialization of the location map else use mgc_location_map if it exists else use HOME mgc mgc_location_map else use HOME mgc_location_map else use MGC_HOME etc mgc_location_map else use MGC_HOME shared etc mgc_location_map else use MODEL_TECH mgc_location_map else use MODEL_TECH mgc_location_map else use no map Reads various variables from the vsim section of the modelsim ini file See vsim simulator control variables UM 280 for more details Parses any command line arguments that were includ
75. lt library_directory gt switch for the vlog command CR 162 Extension Specifies the suffix of files in the library directory Multiple suffixes can be used Same as the libext lt suffix gt switch for the vlog command CR 162 Library File Specifies the Verilog source library file to search for undefined modules Same as the v lt library_file gt switch for the vlog command CR 162 Include Directory Specifies a directory for files included with the include filename compiler directive Same as the incdir lt directory gt switch for the vlog command CR 162 Macro Defines a macro to execute during compilation Same as the compiler directive define macro_name macro_text Also the same as the define lt macro_name gt lt macro_text gt switch for the vlog command CR 162 Simulating with the graphic interface UM 217 Simulating with the graphic interface You can use a project or the Load Design dialog box to simulate a compiled design For information on simulating in a project see Getting started with projects UM 18 To open the Load Design dialog select the Load Design button Main window or Design gt Load Design l ModelSim afar File Edit Design View eee Run Compare Macro Options Window Help ee O pemen g xj Loading project Library wor Loading project Modifying E modelsim55_se win32 test mpf ae adder run Over hl MP 2 1 4 1 Five tabs Design VHDL Verilog Lib
76. maps to M0DEL_TECH std_developerskit synopsys maps to MODEL_TECH synopsys verilog maps to 4O0DEL_TECH verilag work maps to mixed local directory ed e ed The Library Browser dialog box includes these options e Show Choose the mapping and library scope to view from the drop down list e Library Type list To view the contents of a library Select the library then click the View button This brings up the Library tab UM 34 in the Main window From there you can also delete design units from the library To create a new library mapping Click the Add button This brings up Create a New Library UM 33 dialog box that allows you to enter a new logical library name and the pathname to which it is to be mapped It is possible to enter the name of a non existent directory but the specified directory must exist as a ModelSim library before you can compile design units into it ModelSim will issue a warning message if you try to map to a non existent directory ModelSim User s Manual UM 38 3 Design libraries ModelSim User s Manual To edit an existing library mapping Select the desired mapping entry then click the Edit button This brings up a dialog box that allows you to modify the logical library name and the pathname to which it is mapped Selecting Delete removes an existing library mapping but it does not delete the library itself The library can be deleted with this vdel command CR 134 vdel
77. module having a time precision of 10ps from the timescale directive then the path delay receives a value of 20ps The SDF value of 16ps is rounded to 20ps Interconnect delays are rounded to the time precision of the module that contains the annotated MIPD ModelSim User s Manual UM 244 8 Standard Delay Format SDF Timing Annotation SDF for Mixed VHDL and Verilog Designs Annotation of a mixed VHDL and Verilog design is very flexible VHDL VITAL cells and Verilog cells can be annotated from the same SDF file This flexibility is available only by using the simulator s SDF command line options The Verilog sdf_annotate system task can annotate Verilog cells only See the vsim command CR 168 for more information on SDF command line options Interconnect delays ModelSim User s Manual An interconnect delay represents the delay from the output of one device to the input of another With Verilog designs ModelSim can model single interconnect delays or multisource interconnect delays See Arguments Verilog CR 174 under the vsim command for more information on the relevant command line switches Per VHDL VITAL 795 there is no convenient way to handle interconnect delays from multiple outputs to a single input Interconnect delay is modeled in the receiving device as a single delay from an input port to an internal node The node is explicitly declared The default is to use the value of the maximum encountered delay in the
78. of HDL items UM 170 Design hierarchy viewing in Structure window UM 172 Design library assigning a logical name UM 37 creating UM 33 for VHDL design units UM 45 mapping search rules UM 38 resource type UM 32 working type UM 32 Design units UM 32 adding Verilog units to a library CR 162 report of units simulated CR 192 viewing hierarchy UM 121 Directories mapping libraries CR 167 moving libraries UM 39 disablebp command CR 63 DLL files loading UM 89 do command CR 64 DO files macros error handling UM 270 executing at startup UM 275 UM 282 passing parameters to UM 269 Tcl source command UM 271 Do files macros CR 64 DOPATH environment variable UM 275 drivers command CR 65 dumplog64 command CR 66 E echo command CR 67 edit command CR 68 Editing in notepad windows UM 133 UM 293 in the Main window UM 133 UM 293 in the Source window UM 133 UM 293 Editor changing default UM 275 EDITOR environment variable UM 275 enablebp command CR 69 encryption securing pre compiled libraries UM 297 ENDFILE function UM 50 ENDLINE function UM 50 ModelSim User s Manual Entities selecting for simulation CR 177 entity simulator state variable UM 289 Environment displaying or changing pathname CR 70 environment command CR 70 Environment variables UM 275 accessed during startup UM 28 referencing from ModelSim command line UM 277 referencing with VHDL FILE variable UM 277 setting in Windows UM 276 specify transcript file location wit
79. of addern Loading entity addern Load Edit Refresh Create Library View Update Recompile Delete HHHHHHHHHHH Mi test_counter BIE xorg ModelSim gt wm title ModelSim ModelSim gt Project test lt No Design Loaded gt lt No Context gt A The context menu at the left includes the following commands Load Simulates the selected design unit and opens a structure tab in the workspace Related command line command is vsim CR 168 Edit Opens the selected design unit in the Source window Refresh Rebuilds the library image of the selected item s without using source code Related command line command is vcom CR 129 with the refresh argument Recompile Recompiles the selected design unit Related command line command is vcom CR 129 Delete Deletes the selected design unit Related command line command is vdel CR 134 Deleting a package configuration or entity will remove the design unit from the library If you delete an entity that has one or more architectures the entity and all its associated architectures will be deleted ModelSim User s Manual UM 36 3 Design libraries You can also delete an architecture without deleting its associated entity Expand the entity right click the desired architecture name and select Delete You are prompted for confirmation before any design unit is actually deleted The second context menu has the following options e Load Opens the
80. of the following VHDL block statement component instantiation constant generate statement generic package signal or variable Verilog function module instantiation named fork named begin net task or register variable Text conventions ModelSim User s Manual Text conventions used in this manual include italic text provides emphasis and sets off filenames path names and design unit names bold text indicates commands command options menu choices package and library logical names as well as variables and dialog box selection monospace type monospace type is used for program and command examples The right angle gt is used to connect menu choices when traversing menus as in File gt Save UPPER CASE denotes file types used by ModelSim e g DO WLF INI MPF PDF etc UM 15 2 Projects and system initialization Chapter contents Introduction sogo oa db amp amp ee oe e o amp UMG What are pajic Sog e oao s wo a w s p e UM I6 What are the benefits of proje aaa UM 16 How do projects differ in version5 5 22222 UM 17 Getting started with projects aaa a e UM 18 Step 1 Create a new project UM 19 Step 2 Add files to the project UM 21 Step 3 Compile the files UM 21 Step 4 Simulate a design UM 21 Other project operations UM 23 Customizing project settings UM 24 Cha
81. sets a Verilog register or net to the specified value variable is the register or net to be changed value is the new value for the register or net The value remains until there is a subsequent driver transaction or another deposit task for the same register or net This system task operates identically to the ModelSim force deposit command The following system tasks are extended to provide additional functionality for negative timing constraints and an alternate method of conditioning as does Verilog XL Srecovery reference event data_event removal_limit recovery_limit notifier tstamp_cond tcheck_cond delayed_reference delayed_data The recovery system task normally takes a recovery_limit as the third argument and an optional notifier as the fourth argument By specifying a limit for both the third and fourth arguments the recovery timing check is transformed into a combination removal and recovery timing check similar to the recrem timing check The only difference is that the removal_limit and recovery_limit are swapped Ssetuphold clk_event data_event setup_limit hold_limit notifier tstamp_cond tcheck_cond delayed_clk delayed_data The tstamp_cond argument conditions the data_event for the setup check and the clk_event for the hold check This alternate method of conditioning precludes specifying conditions in the clk_event and data_event arguments The tcheck_cond argument conditions the da
82. simulator internally represents time as a 64 bit integer in units equivalent to the smallest unit of simulation time also known as the simulation resolution limit The resolution limit defaults to the smallest time precision found among all of the timescale compiler directives in the design The time precision is the second number in the timescale directive For example 10 ps in the following directive timescale 1 ns 10 ps The time precision should not be unnecessarily small because it will limit the maximum simulation time limit and it will degrade performance in some cases If the design contains no timescale directives then the resolution limit defaults to the resolution value specified in the modelsim ini file default is 1 ps In any case you can override the default resolution limit by specifying the t option on the command line For example to explicitly choose 100 fs resolution vsim t 100fs top This forces 100 fs resolution even if the design has finer time precision As a result time values with finer precision are rounded to the nearest 100 fs Event order issues ModelSim User s Manual The Verilog language is defined such that the simulator is not required to execute simultaneous events in any particular order Unfortunately some models are inadvertently written to rely on a particular event order and these models may behave differently when ported to another Verilog simulator A model with even
83. tcl vsim pref tcl Loading project Modifying E modelsim55_se win32 example mpf ModelSim gt workspace zj lt No Context gt 4 lt No Design Loaded gt The name of the current project is shown at the bottom left corner of the Main window ModelSim User s Manual Getting started with projects UM 21 Step 2 Add files to the project Your right mouse button gives quick access to project commands When you right click in the workspace a context menu appears The menu that appears depends on where you click in the workspace jw Modelsim i i l0 x Compile Dut of Date Files Compile All Add file to Project Sort by Compile Order Select All Close Project Project Project test lt No Design Loaded gt lt No Context gt Aha 1 Right click in a blank area on the Project tab and select Add file to Project This opens the Add file to Project dialog You can also select Project gt Add file to Project from the menu bar Add file to Project Browse Add file as type Reference from current location default Copy to project directory Ok Cancel 2 Specify one or more files you want to add to the project The files used in this example are available in the examples directory that is installed along with ModelSim 3 For the files you re adding choose whether to reference them from their current location or copy them into the project directory
84. tempted to model a memory using signals Two common simulator problems are the likely result e You may get a memory allocation error message which typically means the simulator ran out of memory and failed to allocate more storage e Or you may get very long load elaboration or run times These problems are usually explained by the fact that signals consume a substantial amount of memory many dozens of bytes per bit all of which needs to be loaded or initialized before your simulation starts A simple alternative implementation provides some excellent performance benefits e storage required to model the memory can be reduced by 1 2 orders of magnitude e startup and run times are reduced e associated memory allocation errors are eliminated The trick is to model memory using variables instead of signals In the example below we illustrate three alternative architectures for entity memory Architecture style_87_bad uses a vhdl signal to store the ram data Architecture style_87 uses variables in the memory process and architecture style_93 uses variables in the architecture For large memories architecture style_87_bad runs many times longer than the other two and uses much more memory This style should be avoided Both architectures style_87 and style_93 work with equal efficiently You ll find some additional flexibility with the VHDL 1993 style however because the ram storage can be shared between mul
85. the cursor lt control u gt delete line lt control v gt paste from the clipboard lt control x gt cut the selection lt F8 gt search for the most recent command that matches the characters typed lt F9 gt run simulation lt F10 gt continue simulation lt Fll gt single step lt F12 gt step over The Main window allows insertions or pastes only after the prompt therefore you don t need to set the cursor when copying strings to the command line Right mouse button The right mouse button provides shortcut menus in the Main and Wave windows In the Source window the button gives you feedback on any HDL item under the cursor See Chapter 7 Graphic Interface for menu descriptions ModelSim User s Manual UM 295 C Tips and Techniques Appendix contents Running command line and batch mode simulations UM 296 Source code security and nodebug UM 296 Saving and viewing waveforms in batch mode UM 298 Setting up libraries for group use UM 298 Detecting infinite zero delay loops UM 299 Performance affected by scheduled events being cancelled UM 300 Modeling memory in VHDL UM 301 Setting up a List trigger with Expression Builder UM 305 This appendix contains various tips and techniques collected from several parts of the manual and from answers to questions received by tech support Your suggestions tips and techniques for this section would be ap
86. the waveform pane ModelSim User s Manual UM 202 7 Graphic Interface ModelSim User s Manual The Zoom menu options include Zoom Area with Mouse Button 1 Use mouse button 1 to create a zoom area Position the mouse cursor to the left side of the desired zoom interval press mouse button 1 and drag to the right Release when the box has expanded to the right side of the desired zoom interval Zoom In Zooms in by a factor of two increasing the resolution and decreasing the visible range horizontally Zoom Out Zooms out by a factor of two decreasing the resolution and increasing the visible range horizontally Zoom Full Redraws the display to show the entire simulation from time 0 to the current simulation time Zoom Last Restores the display to where it was before the last zoom operation Zoom Range Brings up a dialog box that allows you to enter the beginning and ending times for a range of time units to be displayed Zooming with toolbar buttons These zoom buttons are available on the toolbar Zoom in 2x Zoom area zoom in by a factor of two use the cursor to outline a from the current view k zoom area Zoom out 2x Zoom Full zoom out by a factor of zoom out to view the full two from current view range of the simulation from time 0 to the current time Zooming with the mouse To zoom with the mouse position the mouse cursor to the left side of the desired zoom interval press the middle mouse bu
87. through command history in Source window move cursor one line up down lt control gt lt left right arrow gt move cursor left right one word lt shift gt lt left right up down arrow gt extend selection of text lt control gt lt shift gt lt left right arrow gt extend selection of text by word lt up down arrow gt scroll through command history in Source window moves cursor one line up down lt control gt lt up down gt move cursor up down one paragraph lt alt gt activate or inactivate menu bar mode lt alt gt lt F4 gt close active window ModelSim User s Manual UM 294 B ModelSim Shortcuts Keystrokes Result lt backspace gt delete character to the left lt home gt move cursor to the beginning of the line lt end gt move cursor to the end of the line lt control gt lt home gt move cursor to the beginning of the text lt control gt lt end gt move cursor to the end of the text lt esc gt cancel lt control a gt select the entire content of the widget lt control c gt copy the selection lt control f gt find lt F3 gt find next lt control k gt delete from the cursor to the end of the line lt control s gt save lt control t gt reverse the order of the two characters to the right of
88. tree They can be used to reconstruct the RTL hierarchy in a gate level design and to locate virtual signals Thus virtual signals and virtual regions can be used in a gate level design to allow you to use the RTL test bench Virtual regions are created and attached using the virtual region command CR 153 User defined enumerated types can be defined in order to display signal bit sequences as meaningful alphanumeric names The virtual type is then used in a type conversion expression to convert a signal to values of the new type When the converted signal is displayed in any of the windows the value will be displayed as the enumeration string corresponding to the value of the original signal Virtual types are created using the virtual type command CR 159 Dataset WLF file and virtual commands UM 113 Dataset WLF file and virtual commands The table below provides a brief description of the actions associated with datasets WLF files and virtual commands For complete details about syntax arguments and usage refer to the ModelSim Command Reference Command name Action dataset alias CR 54 closes the specified dataset dataset list CR 58 lists all open datasets dataset open CR 59 opens a dataset dataset rename CR 60 assigns a new logical name to the specified dataset log CR 81 creates a WLF file for the current simulation nolog CR 87 suspends writing of data to the
89. with respect to clock while the SDF file may contain only a single setup check for both edges SDF Verilog SETUP data posedge clock 5 setup posedge data posedge clk 0 SETUP data posedge clock 5 setup negedge data posedge clk 0 In this case the cell accommodates more accurate data than can be supplied by the tool that created the SDF file and both timing checks correctly receive the same value Likewise the SDF file may contain more accurate data than the model can accommodate SDF Verilog SETUP posedge data posedge clock 4 setup data posedge clk 0 SETUP negedge data posedge clock 6 setup data posedge clk 0 In this case both SDF constructs are matched and the timing check receives the value from the last one encountered Timing check edge specifiers can also use explicit edge transitions instead of posedge and negedge However the SDF file is limited to posedge and negedge The explicit edge specifiers are 01 Ox 10 1x x0 and x1 The set of 01 Ox x1 is equivalent to posedge while the set of 10 1x x0 is equivalent to negedge A match occurs if any of the explicit edges in the specify port match any of the explicit edges implied by the SDF port For example SDF Verilog SETUP data posedge clock 5 setup data edge 01 Ox clk 0 Optional conditions SDF Timing check ports and path delays can have optional conditio
90. within a Verilog module or reference Verilog registers wires at any level of hierarchy from within a Verilog module when there is an interceding VHDL block This system task works only in ModelSim versions 5 5 and newer Syntax Sinit_signal_spy spy_object dest_object verbose Returns Nothing Arguments Name Description spy_object Required A full hierarchical path or relative path with reference to the calling block to a VHDL signal or Verilog register wire Use the path separator to which your simulation is set ie or A full hierarchical path must begin with a or The path must be contained within double quotes dest_object Required A full hierarchical path or relative path with reference to the calling block to a Verilog register or VHDL signal Use the path separator to which your simulation is set e or A full hierarchical path must begin with a or The path must be contained within double quotes verbose integer Optional Possible values are 0 or 1 Specifies whether you want a message reported in the Transcript stating that the spy_object s value is mirrored onto the dest_object Default is 0 no message Limitations e When mirroring the value of a VHDL signal onto a Verilog register the VHDL signal must be of type bit bit_vector std_logic or std_logic_vector e Mirroring slices or single bits of a vector is not supported If you do r
91. 0000100 nets register variables named events sry and module parameters sstrb sirdy Virtual items sadd 00000100 indicated by an orange diamond icon sdata 0000000000000100 virtual signals and virtual functions see Virtual signals UM 110 for more information The names of any VHDL composite types arrays and record types are shown in a hierarchical fashion Hierarchy also applies to Verilog nets and vector memories Verilog vector registers do not have hierarchy because they are not internally represented as arrays Hierarchy is indicated in typical ModelSim fashion with plus expandable minus expanded and blank single level boxes See Tree window hierarchical view UM 121 for more information ModelSim User s Manual UM 156 7 Graphic Interface The Signals window menu bar ModelSim User s Manual The following menu commands are available from the Signals window menu bar File menu Save As save the signals tree to a text file viewable with the ModelSim notepad CR 89 Environment allow the window contents to change based on the current environment or fix to a specific context or dataset Close close this copy of the Signals window Edit menu Copy copy the current selection in the Signals window Sort sort the signals tree in either ascending descending or declaration order Select All select all items in the Signals window Unselect All unselect all items in the
92. 01 oOoooo00000001 00000001 ZZZzzz 00000001 oo00000000000001 00000001 oooga 00000001 o000000000000001 00000001 onoga 00000001 oo00000000000001 00000001 Oooo 00000001 o000000000000001 00000001 Oooo 305 0 320 0 00000001 dd00000000000001 00000001 do00000000000001 0 00000001 O00000t 10 10 0 00000001 000000 Default dataset sim Choose a specific marked line to view by selecting Markers gt Goto The marker name on the Goto list corresponds to the simulation time of the selected line ModelSim User s Manual UM 150 7 Graphic Interface List window keyboard shortcuts Using the following keys when the mouse cursor is within the List window will cause the indicated actions Key Action lt arrow up gt scroll listing up selects and highlights the line above the currently selected line lt arrow down gt scroll listing down selects and highlights the line below the currently selected line lt arrow left gt scroll listing left lt arrow right gt scroll listing right lt page up gt scroll listing up by page lt page down gt scroll listing down by page lt tab gt searches forward down to the next transition on the selected signal lt shift tab gt searches backward up to the previous transition on the selected signal does not function on HP workstations lt control f gt opens the find dialog box finds the specified item label within t
93. 500 Using Parameters with DO files You can increase the flexibility of DO files using parameters Parameters specify values that are passed to the corresponding parameters 1 through 9 in the macro file For example do testfile design vhd 127 If the macro file testfile contains the line bp 1 2 this command would place a breakpoint in the source file named design vhd at line 127 There is no limit on the number of parameters that can be passed to macros but only nine values are visible at one time You can use the shift command CR 111 to see the other parameters ModelSim User s Manual UM 270 10 Tcl and macros Useful commands for handling breakpoints and errors If you are executing a macro when your simulation hits a breakpoint or causes a run time error ModelSim interrupts the macro and returns control to the command line The following commands may be useful for handling such events Any other legal command may be executed as well command result run CR 107 continue continue as if the breakpoint had not been executed completes the run CR 107 that was interrupted onbreak CR 92 specify a command to run when you hit a breakpoint within a macro onElabError CR 93 specify a command to run when an error is encountered during elaboration onerror CR 94 specify a command to run when an error is encountered within a macro status CR 113 get a traceback of nested macro calls when a macro
94. 7 Variable precedence UM 288 Simulator state variables ae UM 289 Referencing simulator state variables UM 289 Special considerations for now UM 290 B ModelSim Shortcuts UM 291 Wave window mouse and keyboard shortcuts 2 2 UM 291 List window keyboard shortcuts 2 a ee ee eee ee ee UM 292 Command shortcuts s os sa ee ee UM 293 Mouse and keyboard shortcuts in Main and Source windows UM 293 Right mouse button lt s lt s s sa sos eR eee eee ee ee a UM 294 C Tips and Techniques UM 295 Running command line and batch mode simulations UM 296 Source code security and nodebug UM 297 Saving and viewing waveforms in batch mode UM 298 Setting up libraries for group use UM 298 Detecting infinite zero delay loops UM 299 Performance affected by scheduled events being cancelled UM 300 Modeling memory in VHDL UM 301 ModelSim User s Manual UM 10 Table of Contents Setting up a List trigger with Expression Builder 2 2 UM 305 Index UM 307 ModelSim User s Manual UM 11 1 Introduction Chapter contents Standards supported aa a UM 12 Assumptions eee UM E12 Sectionsinthisdocument UM 12 Command reference a UM 13 Text conventions UM 14 What is an HDL item UM 14 This documentation was written for ModelSim version 5 5e fo
95. 7 Ifa word contains a dollar sign then Tcl performs variable substitution the dollar sign and the following characters are replaced in the word by the value of a variable Variable substitution may take any of the following forms name Name is the name of a scalar variable the name is terminated by any character that isn t a letter digit or underscore Sname index Name gives the name of an array variable and index gives the name of an element within that array Name must contain only letters digits and underscores Command substitutions variable substitutions and backslash substitutions are performed on the characters of index name Name is the name of a scalar variable It may contain any characters whatsoever except for close braces There may be any number of variable substitutions in a single word Variable substitution is not performed on words enclosed in braces 8 Ifa backslash appears within a word then backslash substitution occurs In all cases but those described below the backslash is dropped and the following character is treated as an ordinary character and included in the word This allows characters such as double quotes close brackets and dollar signs to be included in words without triggering special processing The following table lists the backslash sequences that are handled specially along with the value that replaces each sequence a Audible al
96. An SDF file contains delay and timing constraint data for cell instances in the design The annotator must locate the cell instances and the placeholders VHDL generics for the timing data Each type of SDF timing construct is mapped to the name of a generic as specified by the VITAL modeling specification The annotator locates the generic and updates it with the timing value from the SDF file It is an error if the annotator fails to find the cell instance or the named generic The following are examples of SDF constructs and their associated generic names SDF construct Matching VHDL generic name IOPATH a y 3 tpd_a_ IOPATH posedge clk q 1 2 tpd_clk_q_posedge INTERCONNECT ul y u2 a 5 tipd_a SETUP d posedge clk 5 tsetup_d_clk_noedge_posedge HOLD negedge d posedge clk 5 thold_d_clk_negedge_posedge SETUPHOLD d clk 5 5 tsetup_d_clk amp thold_d_clk WIDTH COND reset 1 b0 clk 5 tpw_clk_reset_eq_0 VHDL VITAL SDF UM 237 Resolving errors If the simulator finds the cell instance but not the generic then an error message is issued For example ERROR myasic sdf 18 Instance testbench dut ul does not have a generic named tpd_a_y In this case make sure that the design is using the appropriate VITAL library cells If it is then there is probably a mismatch between the SDF and the VITAL cells You need to find the cell instance and compare its generi
97. BJS environment variable setenv PLIOBJS pliappl so pliapp2 so pliappn so e As a pli option to the simulator multiple options are allowed pli pliappl so pli pliapp2 so pli pliappn so The various methods of specifying PLI applications can be used simultaneously The libraries are loaded in the order listed above Environment variable references can be used in the paths to the libraries in all cases ModelSim User s Manual UM 88 5 Verilog Simulation Registering VPI applications Each VPI application must register its system tasks and functions and its callbacks with the simulator To accomplish this one or more user created registration routines must be called at simulation startup Each registration routine should make one or more calls to vpi_register_systf to register user defined system tasks and functions and vpi_register_cb to register callbacks The registration routines must be placed in a table named vlog_startup_routines so that the simulator can find them The table must be terminated with a 0 entry Example PL T32 T32 T32 NT32 MyFuncCalltf PLI_BYTE8 user_data MyFuncCompiletf PLI_BYTE8 user_data MyFuncSizetf PLI_BYTE8 user_data MyEndOfCompCB p_cb_data cb_data_p NT32 MyStartOfSimCB p_cb_data cb_data_p void RegisterMySystfs void s_cb_data callback s_vpi_systf_data systf_data systf_data type vpiSysFunc systf_data sysfunctype
98. C AWINNT Profiles charley L The Write Postscript dialog box includes these options Printer e File name Enter a filename for the encapsulated Postscript eps file to be created or browse to a previously created eps file and use that filename Signal Selection e All signals Print all signals e Current View Print signals in the current view e Selected Print all selected signals ModelSim User s Manual Wave window UM 207 Time Range e Full Range Print all specified signals in the full simulation range e Current view Print the specified signals for the viewable time range e Custom Print the specified signals for a user designated From and To time Setup button See Printer Page Setup UM 209 Printing on Windows platforms Select File gt Print Wave window to print all or part of the waveform in the current Wave window or save the waveform as a printer file a Postscript file for Postscript printers Printing and writing preferences are controlled by the dialog box shown below LINKAGESHP LaserJet 5L x Printer e Name Choose the printer from the drop down menu Set printer properties with the Properties button e Status Indicates the availability of the selected printer ModelSim User s Manual UM 208 7 Graphic Interface ModelSim User s Manual Type Printer driver name for the selected printer The driver determines what type of file is output if Print to file is
99. CR 40 Batch mode simulations UM 296 stopping simulation CR 183 bd breakpoint delete command CR 41 bookmark add wave command CR 42 bookmark delete wave command CR 43 bookmark goto wave command CR 44 bookmark list wave command CR 45 bookmarks UM 203 bp breakpoint command CR 46 Break on assertion UM 227 on signal value CR 181 BreakOnAssertion ini file variable UM 280 Breakpoints continuing simulation after CR 107 deleting CR 41 UM 168 enabling and disabling UM 169 listing CR 46 setting CR 46 UM 168 signal breakpoints when statements UM 160 time based UM 160 Time based breakpoints in when statements CR 183 viewing in the Source window UM 163 Busses user defined UM 121 C case choice must be locally static CR 130 Case sensitivity VHDL vs Verilog CR 11 cd change directory command CR 49 Cell libraries UM 75 change command CR 50 CheckSynthesis ini file variable UM 278 Command reference UM 13 CommandHistory ini file variable UM 280 Command line mode UM 296 commands abort CR 31 add list CR 32 add wave CR 35 alias CR 39 batch_mode CR 40 bd breakpoint delete CR 41 bookmark add wave CR 42 bookmark delete wave CR 43 bookmark goto wave CR 44 ModelSim User s Manual Index bookmark list wave CR 45 bp breakpoint CR 46 cd change directory CR 49 change CR 50 configure CR 51 dataset alias CR 54 dataset clear CR 55 dataset close CR 56 dataset info CR 57 dataset list CR 58 dataset ope
100. Contents of and2 v module and2 y a b output y input a b and y a b endmodule Contents of or2 v module or2 y a b output y input a b OBY a ONF endmodule Compile the design in top down order assumes work library already exists o vlog top v Compiling module top Top level modules top vlog and2 v Compiling module and2 Top level modules and2 vlog or2 v Compiling module or2 Top level modules or2 Note that the compiler lists each module as a top level module although ultimately only top is a top level module If a module is not referenced by another module compiled in the same invocation of the compiler then it is listed as a top level module This is just an Compilation UM 63 informative message and can be ignored during incremental compilation The message is more useful when you compile an entire design in one invocation of the compiler and need to know the top level module names for the simulator For example vlog top v and2 v or2 v Compiling module top Compiling module and2 Compiling module or2 Top level modules top The most efficient method of incremental compilation is to manually compile only the modules that have changed This is not always convenient especially if your source files have compiler directive interdependencies such as macros In this case you may prefer to always compile your entire design in one invocation of the com
101. DL items you can view I variables The following HDL items for a VHDL and Verilog are viewable i within the Variables window cache verbose 1 VHDL items sdata_r 0000000000000100 constants generics and variables pdata_r zzzzzzzzzzzzzzzz saddr_r 00000100 Verilog items SINI sstrb_r register variables prdy_r The names of any VHDL composite types arrays and record types are shown in a hierarchical fashion Hierarchy also applies to Verilog vector memories Verilog vector registers do not have hierarchy because they are not internally represented as arrays Hierarchy is indicated in typical ModelSim fashion with plus expandable and minus expanded See Tree window hierarchical view UM 121 for more information AaGa a To change the value of a VHDL variable constant or generic or a Verilog register variable move the pointer to the desired name and click to highlight the selection Select Edit gt Change Variables window to bring up a dialog box that lets you specify a new value Note that Variable Name is a term that is used loosely in this case to signify VHDL constants and generics as well as VHDL and Verilog register variables You can enter any value that is valid for the variable An array value must be specified as a string without surrounding quotation marks To modify the values in a record you need to change each field separately Click on a process in the Process window to chan
102. Load Design dialog box See Simulating with the graphic interface UM 217 for details Related command line command is vsim CR 168 e Create Library Opens the Create a New Library dialog box See Creating a library UM 33 earlier in this chapter for details Related command line command is vlib CR 161 e View Provides various options for displaying design units e Update Reloads the library in case any of the design units were modified outside of the current session e g by a script or another user ModelSim User s Manual Working with design libraries UM 37 Assigning a logical name to a design library VHDL uses logical library names that can be mapped to ModelSim library directories By default ModelSim can find libraries in your current directory assuming they have the right name but for it to find libraries located elsewhere you need to map a logical library name to the pathname of the library You can use the GUI a command or a project to assign a logical name to a design library Library mappings with the GUI To associate a logical name with a library select Design gt Browse Libraries Main window This brings up a dialog box that allows you to view add edit and delete mappings as shown below Library Browser Iof Xx Show All Visible Libraries j j a E ieee maps to MODEL_TECH ieee mac_portable maps to 40DEL_TECH mgc_portable std maps to M4ODEL_TECH std std_developerskit
103. M 80 verilog ini file variable UM 278 Verilog PLI VPI UM 86 UM 101 ModelSim User s Manual Index 64 bit support in the PLI UM 100 compiling and linking PLI VPI applications UM 89 debugging PLI VPI code UM 100 PLI callback reason argument UM 93 PLI support for VHDL objects UM 96 registering PLI applications UM 86 registering VPI applications UM 88 specifying the PLI VPI file to load UM 90 Verilog Procedural Interface UM 86 Verilog XL differences in event order UM 70 Veriuser ini file variable UM 87 UM 282 version obtaining via Help menu UM 130 obtaining with vsim command CR 172 obtaining with vsim lt info gt commands CR 179 vgencomp command CR 136 VHDL delay file opening UM 286 dependency checking UM 45 field naming syntax CR 11 file opening delay UM 286 library clause UM 40 object support in PLI UM 96 simulating UM 46 source code viewing UM 163 standards UM 12 VITAL package UM 41 VHDL utilities UM 54 UM 55 get_resolution UM 54 to_real UM 56 to_time UM 57 VHDL493 ini file variable UM 279 view command CR 138 Viewing design hierarchy UM 121 library contents UM 34 waveforms CR 172 Viewing and saving waveforms UM 103 virtual count commands CR 139 virtual define command CR 140 virtual delete command CR 141 virtual describe command CR 142 virtual expand commands CR 143 virtual function command CR 144 virtual hide command CR 147 UM 111 virtual log command CR 148 virtual nohide command CR 150 virtual nolog com
104. Model Sim Xilinx User s Manual Version 5 5e Published 25 Sep 01 The world s most popular HDL simulator ModelSim User s Manual ModelSim is produced by Model Technology Incorporated Unauthorized copying duplication or other reproduction is prohibited without the written consent of Model Technology The information in this manual is subject to change without notice and does not represent a commitment on the part of Model Technology The program described in this manual is furnished under a license agreement and may not be used or copied except in accordance with the terms of the agreement The online documentation provided with this product may be printed by the end user The number of copies that may be printed is limited to the number of licenses purchased ModelSim is a registered trademark of Model Technology Incorporated Model Technology is a trademark of Mentor Graphics Corporation PostScript is a registered trademark of Adobe Systems Incorporated UNIX is a registered trademark of AT amp T in the USA and other countries FLEXIm is a trademark of Globetrotter Software Inc IBM AT and PC are registered trademarks AIX and RISC System 6000 are trademarks of International Business Machines Corporation Windows Microsoft and MS DOS are registered trademarks of Microsoft Corporation OSF Motif is a trademark of the Open Software Foundation Inc in the USA and other countries SPARC is a registered trademark and
105. R 181 for more details via a context menu in the Signal window When statements instruct ModelSim to perform actions when the specified conditions are met For example you can break on a signal value or at a specific simulator time see Time based breakpoints CR 183 When a breakpoint is hit a message appears in the transcript window about which signal caused the breakpoint To access the breakpoint commands select a signal and then click your right mouse button To set a breakpoint on a selected signal select Add Breakpoint from the context menu To remove a breakpoint from a selected signal select Remove Signal Breakpoint To remove all breakpoints in the current region select Remove All Signal Breakpoints To see a list of currently set breakpoints select Show Breakpoints ModelSim User s Manual Signals window UM 161 The Edit Breakpoint command opens the Edit When dialog box Edit When Condition HOE EE Opt Label top sdata echo Break on top sdata stop Command s The Edit When dialog includes the following options e Condition The condition s to be met for the specified command s to be executed Required See the when command CR 181 for more information on creating the condition statement Opt Label An optional text label for the when statement Command s The command s to be executed when the specified condition is met Any ModelSim or Tcl command or series of commands
106. SDF file Alternatively you can choose the minimum or latest value of the multiple delays with the vsim command CR 168 multisource_delay option multisource_delay min max latest Timing checks are performed on the interconnect delayed versions of input ports This may result in misleading timing constraint violations because the ports may satisfy the constraint while the delayed versions may not If the simulator seems to report incorrect violations be sure to account for the effect of interconnect delays Troubleshooting UM 245 Troubleshooting Specifying the wrong instance By far the most common mistake in SDF annotation is to specify the wrong instance to the simulator s SDF options The most common case is to leave off the instance altogether which is the same as selecting the top level design unit This is generally wrong because the instance paths in the SDF are relative to the ASIC or FPGA model which is usually instantiated under a top level testbench See Instance specification UM 234 for an example A common example for both VHDL and Verilog test benches is provided below For simplicity the test benches do nothing more than instantiate a model that has no ports VHDL testbench entity testbench is end architecture only of testbench is component myasic end component begin dut myasic end Verilog testbench module testbench myasic dut endmodule The name of the model is myasic and the ins
107. SPARCstation is a trademark of SPARC International Inc Sun Microsystems is a registered trademark and Sun SunOS and OpenWindows are trademarks of Sun Microsystems Inc All other trademarks and registered trademarks are the properties of their respective holders Copyright c 1990 2001 Model Technology Incorporated All rights reserved Confidential Online documentation may be printed by licensed customers of Model Technology Incorporated for internal business purposes only ModelSim support Support for ModelSim is available from your FPGA vendor See the About ModelSim dialog box accessed via the Help menu for contact information UM 3 Table of Contents 1 Introduction UM 11 Standards supported UM 12 Assumptions UM 12 Sections in this document UM 12 Command reference UM 13 What is an HDL item UM 14 Text conventions UM 14 2 Projects and system initialization UM 15 Introduction UM 16 How do projects differs in version 3 57 UM 17 Getting started with projects UM 18 Step 1 Create a new project UM 19 Step 2 Add files to the project UM 21 Step 3 Compile the files UM 22 Step 4 Simulate a design UM 23 Other project operations UM 23 Customizing project settings UM 24 Changing compile order UM 24 Grouping files UM 24 Setting compiler options UM 25 Accessing projects from the command line UM 26 System initialization UM 27 Files access
108. Signals window Expand Selected expand the hierarchy of the selected items Collapse Selected collapse the hierarchy of the selected items Expand All expand the hierarchy of all items that can be expanded Collapse All collapse the hierarchy of all expanded items Force apply stimulus to the specified Signal Name specify Value Kind Freeze Drive Deposit Delay and Cancel see also the force command CR 76 Noforce remove the effect of any active force command CR 76 on the selected HDL item see also the noforce command CR 86 Clock define clock signals by Signal Name Period Duty Cycle Offset and whether the first edge is rising or falling see Defining clock signals UM 162 Justify Values justify values to the left or right margins of the window pane Find find the specified text string within the Signals window choose the Name or Value field to search and the search direction down or up View menu Signals window UM 157 Wave List Log place the Selected Signals Signals in Region or Signals in Design in the Wave window UM 178 List window UM 139 or WLF file Filter Window menu choose the port and signal types to view Input Ports Output Ports InOut Ports and Internal Signals in the Signals window Initial Layout restore all windows to the size and placement of the initial full screen layout Cascade cascade all open windows Tile Horizontally
109. Structure Main window The discussion below applies to both the Structure window and the structure tabs in the Workspace The Structure window provides a hierarchical view of the structure of your design An entry is created by each HDL item within the design Your design structure can remain hidden if you wish see Source code security and nodebug UM 297 HDL items you can view truct The following HDL items for VHDL e ET z BRE and Verilog are represented by Eie Edit window hierarchy within Structure window z top toplonly proc VHDL items Ore D m memory indicated by a dark blue square icon component instantiation generate statements block statements and Mi Package std_logic_1164 packages I Package standard B Package std_logic_util Package vi_types cache cache Function hash indicated by a lighter blue circle Task update_mru icon module instantiations named forks named begins tasks and functions Verilog items Function pick_set Task sysread Task syswrite Virtual items Function get_hit indicated by an orange diamond E 30 cache_set only icon E 1 cache_set only virtual regions see Virtual Objects W 2 cache_set only User defined buses and more E 3 cache_set only UM 110 for more information You can expand and contract the display to view the hierarchical structure by clicking on the boxes that contain or Clicking expan
110. Synthesis Turns on limited synthesis rule compliance checking Edit the CheckSynthesis UM 278 variable in the modelsim ini file to set a permanent default Compiling with the graphic interface UM 215 e Vital Compliance Toggle Vital compliance checking Edit the NoVitalCheck UM 279 variable in the modelsim ini file to set a permanent default Optimize for StdLogic1164 Causes the compiler to perform special optimizations for speeding up simulation when the multi value logic package std_logic_1164 is used Unless you have modified the std_logic_1164 package this option should always be checked Edit the Optimize_1164 UM 279 variable in the modelsim ini file to set a permanent default Vital Toggle acceleration of the Vital packages Edit the NoVital UM 279 variable in the modelsim ini file to set a permanent default Verilog compiler options tab Compiler Options I Enable runtime hazard checks T Disable loading messages I Disable debugging data T Show source lines with errors I Convert identifiers to upper case Other Verilog Options Library Search Extension Library File Include Directory Macro OK Cancel Apply e Enable run time hazard checks Enables the run time hazard checking code Same as the hazards switch for the vlog command CR 162 Edit the Hazard UM 279 variable in the modelsim ini file to set a permanent default ModelSim User s Manual UM 216 7
111. Tcl CR 14 ved add command CR 119 ved checkpoint command CR 120 ved comment command CR 121 ved file command CR 122 VCD files UM 247 UM 317 adding internal signals CR 119 adding items to the file CR 119 converting to WLF files CR 128 creating CR 119 UM 249 dumping variable values CR 120 flushing the buffer contents CR 124 from VHDL source to VCD output UM 250 inserting comments CR 121 specifying maximum file size CR 125 specifying name of CR 123 specifying the file name CR 122 turn off VCD dumping CR 126 turn on VCD dumping CR 127 VCD system tasks UM 248 viewing files from another tool CR 128 ved files command CR 123 ved flush command CR 124 ved limit command CR 125 ved off command CR 126 ved on command CR 127 ved2wlf command CR 128 vcom command CR 129 vdel command CR 134 vdir command CR 135 Verilog ACC routines UM 97 cell libraries UM 75 compiler directives UM 84 compiling and linking PLI applications UM 89 compiling design units UM 61 compiling with XL uselib compiler directive UM 67 creating a design library UM 61 library usage UM 64 SDF annotation UM 238 sdf_annotate system task UM 238 simulating UM 69 delay modes UM 75 event order issues UM 70 XL compatible options UM 71 simulation hazard detection UM 71 simulation resolution limit UM 70 source code viewing UM 163 standards UM 12 system tasks UM 77 TF routines UM 98 XL compatible compiler options UM 65 XL compatible routines UM 100 XL compatible system tasks U
112. UM 12 UM 43 TEEE Std 1364 UM 12 UM 59 ieee_synopsis library UM 41 IgnoreError ini file variable UM 281 IgnoreFailure ini file variable UM 281 IgnoreNote ini file variable UM 281 IgnoreVitalErrors ini file variable UM 279 IgnoreWarning ini file variable UM 281 Implicit operator hiding with vcom explicit CR 133 Incremental compilation automatic UM 63 manual UM 63 with Verilog UM 62 index checking UM 45 Indexing signals memories and nets CR 11 init_signal_spy UM 55 init_usertfs function UM 87 initial dialog box UM 311 turning on off UM 274 Initialization sequence UM 29 Instantiation label UM 173 Interconnect delays CR 175 UM 72 UM 244 internal signals adding to a VCD file CR 119 Iteration_limit detecting infinite zero delay loops UM 299 IterationLimit ini file variable UM 281 K Keyboard shortcuts List window UM 150 UM 292 Main window UM 133 UM 293 Source window UM 293 Wave window UM 205 UM 291 L Libraries alternate IEFE libraries UM 41 creating design libraries CR 161 UM 33 design library types UM 32 design units UM 32 ieee_numeric UM 41 ieee_numeric library UM 41 ieee_synopsis UM 41 including precompiled modules UM 223 listing contents CR 135 lock file unlocking CR 131 CR 163 mapping from the command line UM 38 from the GUI UM 37 hierarchically UM 284 search rules UM 38 modelsim_lib UM 54 moving UM 39 naming UM 37 predefined UM 40 refreshing library images CR 132 CR 164 UM 41 resource
113. Verilog net or variable to change or for a specified time out period lt Done gt Indicates that the process has executed a VHDL wait statement fx process File Edit View Window lt Wait gt H ASSIGNHI13 lt Wait gt HASSIGNHI12 lt Wait gt HAL WAYSH144 lt Done gt IMPLICIT WIRE wen 3 lt Done gt IMPLICIT WIRE oen 3 lt Done gt IMPLICIT WIRE wen 2 lt Done gt IMPLICIT WIRE oen 2 lt Done gt IMPLICIT WIRE wen 1 without a time out or a sensitivity list The process will not restart during the current simulation run If you select a Ready process it will be executed next by the simulator When you click on a process in the Process window the following windows are updated Window updated Result Structure window UM 172 shows the region in which the process is located Variables window UM 175 shows the VHDL variables and Verilog register variables in the process Source window UM 163 shows the associated source code Dataflow window UM 135 shows the process the signals nets and registers the process reads and the signals nets and registers driven by the process Source window UM 163 ModelSim User s Manual shows the signals nets and registers declared in the region in which the process is located The Process window menu bar Process window UM 153 The following menu commands are available from the Process window menu bar F
114. WLF file for the specified signals searchlog CR 109 searches one or more of the currently open WLF files for a specified condition virtual function CR 144 creates a new signal that consists of logical operations on existing signals and simulation time virtual region CR 153 creates a new user defined design hierarchy region virtual signal CR 156 creates a new signal that consists of concatenations of signals and subelements virtual type CR 159 creates a new enumerated type vsim CR 168 wlf lt filename gt creates a WLF file for the simulation which can be reopened as a dataset ModelSim User s Manual UM 114 ModelSim User s Manual UM 115 7 Graphic Interface Chapter contents Window overview UM 116 Common window features UM 117 Main window UM 123 Dataflow window UM 135 List window UM 139 Process window UM 152 Signals window ee UM 155 Source window eee UM 163 Structure window UM 172 Variables window ee UM 175 Wave window eee ee UM 178 Compiling with the graphic interface UM 211 Simulating with the graphicinterface 3 UM 217 ModelSimtools eee UM 230 Graphic interface commands UM 232 ModelSim User s Manual UM 116 7 Graphic Interface Window overview ModelSim User s Manual The ModelSim simulation and debugging environment consists of nin
115. _path_delays option selects transport mode for path delays In transport mode narrow pulses are propagated through path delays Note that this option affects path delays only and not primitives Primitives always operate in inertial delay mode typdelays This option selects the typical value in min typ max expressions This is the default This option has no effect if the min typ max selection was determined at compile time Cell Libraries UM 75 Cell Libraries Model Technology passed the ASIC Council s Verilog test suite and achieved the Library Tested and Approved designation from Si2 Labs This test suite is designed to ensure Verilog timing accuracy and functionality and is the first significant hurdle to complete on the way to achieving full ASIC vendor support As a consequence many ASIC and FPGA vendors Verilog cell libraries are compatible with ModelSim Verilog The cell models generally contain Verilog specify blocks that describe the path delays and timing constraints for the cells See section 13 in the IEEE Std 1364 1995 for details on specify blocks and section 14 5 for details on timing constraints ModelSim Verilog fully implements specify blocks and timing constraints as defined in IEEE Std 1364 along with some Verilog XL compatible extensions SDF timing annotation Delay modes ModelSim Verilog supports timing annotation from Standard Delay Format SDF files See Chapter 8 Standard Delay Format SDF Timing
116. _spec gt delay selection Optional The lt mtm_spec gt delay selection is always used to select the delay scaling factor but if a lt scale_type gt is specified then it will determine the min typ max selection from the SDF file The allowed strings are from_min from_minimum from_typ from_typical from_max from_maximum and from_mtm Case is ignored and the default is from_mtm which means to use the lt mtm_spec gt value Verilog SDF UM 239 Examples Optional arguments can be omitted by using commas or by leaving them out if they are at the end of the argument list For example to specify only the SDF file and the instance it applies to Ssdf_annotate myasic sdf testbench ul To also specify maximum delay values Ssdf_annotate myasic sdf testbench ul maximum SDF to Verilog construct matching The annotator matches SDF constructs to corresponding Verilog constructs in the cells Usually the cells contain path delays and timing checks within specify blocks For each SDF construct the annotator locates the cell instance and updates each specify path delay or timing check that matches An SDF construct can have multiple matches in which case each matching specify statement is updated with the SDF timing value SDF constructs are matched to Verilog constructs as follows IOPATH is matched to specify path delays or primitives SDF Verilog IOPATH posedge clk q 3 4 posedge clk
117. a factor of two from the current view Zoom gt Zoom In keyboard i I or right mouse in wave pane gt Zoom In Zoom out 2x zoom out by a factor of two from current view Zoom gt Zoom Out keyboard o O or right mouse in wave pane gt Zoom Out Zoom area with mouse button 1 use the cursor to outline a zoom area Zoom gt Zoom Range keyboard r or R right mouse in wave pane gt Zoom Area Zoom Full zoom out to view the full range of the simulation from time 0 to the current time Zoom gt Zoom Full keyboard f or F right mouse in wave pane gt Zoom Full Fa aaa ee Interrupt Wave Drawing halts any waves currently being drawn in the Wave window none none ModelSim User s Manual UM 188 7 Graphic Interface Wave window toolbar buttons Button Menu equivalent Other options Restart reloads the design elements and resets the simulation time to zero with the option of keeping the current formatting breakpoints and WLF file Main menu Run gt Restart restart lt arguments gt see restart CR 104 Run run the current simulation for the default time length Main menu Run gt Run lt default_length gt see run CR 107 Continue Run continue the current simulation run Main menu Run gt Continue see run CR 107 Run All run the current simulation forever or until it hits a breakpoint or specified brea
118. able settings may be set from within the ModelSim GUI Options gt Edit Preferences Main window or by directly editing the preference file The default file for customized preferences is modelsim tcl When ModelSim starts it searches for a modelsim tcl file as follows e use MODELSIM_TCL UM 275 environment variable if it exists if MODELSIM_TCL is a list of files each file is loaded in the order that it appears in the list else e use modelsim tcl else e use HOME modelsim tcl if it exists If your preference file is not named modelsim tcl or if the file is not located in the directories mentioned above you must refer to it with the MODELSIM_TCL environment variable User defined variables Temporary user defined variables can be created with the Tcl set command Like simulator variables user defined variables are preceded by a dollar sign when referenced To create a variable with the set command set userl 7 You can use the variable in a command like echo userl Suserl More preferences Additional compiler and simulator preferences may be set in the modelsim ini file see Preference variables located in INI files UM 278 ModelSim User s Manual UM 288 A ModelSim Variables Variable precedence ModelSim User s Manual Note that some variables can be set in a tcl file or a ini file A variable set in a tcl file takes precedent over the same variable set in a ini file For example assume you
119. ackage UM 55 init_signal_spy The init_signal_spy utility mirrors the value of a VHDL signal or Verilog register wire called the spy_object onto an existing VHDL signal or Verilog register called the dest_object This allows you to reference signals registers or wires at any level of hierarchy from within a VHDL architecture e g a testbench This system task works only in ModelSim versions 5 5 and newer Syntax init_signal_spy spy_object dest_object verbose Returns Nothing Arguments Name Description spy_object Required A full hierarchical path or relative path with reference to the calling block to a VHDL signal or Verilog register wire Use the path separator to which your simulation is set ie or A full hierarchical path must begin with a or The path must be contained within double quotes dest_object Required A full hierarchical path or relative path with reference to the calling block to an existing VHDL signal or Verilog register Use the path separator to which your simulation is set i e or A full hierarchical path must begin with a or The path must be contained within double quotes verbose integer Optional Possible values are 0 or 1 Specifies whether you want a message reported in the Transcript stating that the spy_object s value is mirrored onto the dest_object Default is 0 no message Related functions None
120. add a variable The syntax for variables in the file is lt variable gt lt value gt Comments within the file are preceded with a semicolon gt Note The vmap command CR 167 automatically modifies library mappings in the current INI file ModelSim User s Manual UM 284 A ModelSim Variables Commonly used INI variables Several of the more commonly used modelsim ini variables are further explained below Environment variables You can use environment variables in your initialization files Use a dollar sign before the environment variable name Examples Library work HOME work_lib test_lib TESTNUM work vsim IgnoreNote IGNORE_ASSERTS IgnoreWarning IGNORE_ASSERTS IgnoreError IgnoreFailure Io 0 Tip There is one environment variable MODEL_TECH that you cannot and should not set MODEL_TECH is a special variable set by Model Technology software Its value is the name of the directory from which the VCOM compiler or VSIM simulator was invoked MODEL_TECH is used by the other Model Technology tools to find the libraries Hierarchical library mapping By adding an others clause to your modelsim ini file you can have a hierarchy of library mappings If the ModelSim tools don t find a mapping in the modelsim ini file then they will search just the library section of the initialization file specified by the others clause Examples Library asic_lib cae as
121. adding to a WLF file UM 159 adding to the Wave and List windows UM 159 alternative names in the List window label CR 33 alternative names in the Wave window label CR 36 applying stimulus to CR 76 UM 158 combining into a user defined bus UM 121 creating a signal log file CR 81 displaying drivers of CR 65 displaying environment of CR 70 displaying values in Signals window UM 155 examining values CR 71 finding CR 74 indexing arrays CR 11 pathnames in VSIM commands CR 10 referencing in the hierarchy UM 55 replacing values of with text CR 159 saving values as binary log file UM 159 selecting signal types to view UM 157 specifying force time CR 77 specifying radix of in List window CR 33 specifying radix of in Wave window CR 37 UM 315 specifying radix of signal to examine CR 71 viewing waveforms UM 178 Signals window UM 155 Simulating applying stimulus to signals and nets UM 158 command line mode UM 296 comparing simulations UM 103 saving simulations CR 81 CR 172 UM 103 UM 298 saving waveform as a Postscript file UM 206 setting default run length UM 227 setting iteration limit UM 227 setting time resolution UM 219 specifying design unit CR 168 specifying the time unit for delays CR 14 stepping through a simulation CR 114 stopping simulation in batch mode CR 183 Verilog UM 69 delay modes UM 75 event order issues UM 70 hazard detection UM 71 resolution limit UM 70 XL compatible simulator options UM 71 VHDL UM 46 viewing r
122. additional items to the right or the left of the original selection to select several items randomly Control click to add or subtract from the selected group to move the selected items re click on one of the selected items hold and drag it to the new location ModelSim User s Manual UM 146 7 Graphic Interface ModelSim User s Manual To format an item Select the item s label at the top of the List window or one of its values from the listing then select Prop gt Signal Props List window The resulting Modify Signal Properties dialog box allows you to set the item s label label width triggering and radix Modify Signal Properties list iof x Signal adder orl_out Labe 0 Radix Sybok Width M Characters Binary C Octal Decimal C Unsigned TATZE Hexadecimal Triggers line C ASCII Does not trigger line Default OK Cancel Apply The Modify Signal Properties dialog box includes these options e Signal Shows the full pathname of the selected signal Label Specifies the label that appears at the top of the List window column Radix Specifies the radix base in which the item value is expressed The default radix is symbolic which means that for an enumerated type the List window lists the actual values of the enumerated type of that item You can change the default radix for the current simulation using either Options gt Simulation Main win
123. al Distributed delay mode In distributed delay mode the specify path delays are ignored in favor of the distributed delays Select this delay mode with the delay_mode_distributed compiler option or the delay_mode_distributed compiler directive Path delay mode In path delay mode the distributed delays are set to zero in any module that contains a path delay Select this delay mode with the delay_mode_path compiler option or the delay_mode_path compiler directive Unit delay mode In unit delay mode the distributed delays are set to one the unit is the time_unit specified in the timescale directive and the specify path delays and timing constraints are ignored Select this delay mode with the delay_mode_unit compiler option or the delay_mode_unit compiler directive Zero delay mode In zero delay mode the distributed delays are set to zero and the specify path delays and timing constraints are ignored Select this delay mode with the delay_mode_zero compiler option or the delay_mode_zero compiler directive System Tasks System Tasks UM 77 The IEEE Std 1364 defines many system tasks as part of the Verilog language and ModelSim Verilog supports all of these along with several non standard Verilog XL system tasks The system tasks listed in this chapter are built into the simulator although some designs depend on user defined system tasks implemented with the Programming Language Interface PLI or Verilog Proce
124. al ModelSim includes an import wizard for referencing and using vendor FPGA libraries The wizard scans for and enforces dependencies in the libraries and determines the correct mappings and target directories A Important The FPGA libraries you import must be pre compiled Most FPGA vendors supply pre compiled libraries configured for use with ModelSim To import an FPGA library select Design gt Import Library Main window Import Library Wizard lolx The Import Library Wizard will step you through the tasks necessary to reference and use a library 4 library can be either an existing Model Technology library or an FPGA library that you received from an FPGA vendor If the library was received from an FPGA vendor it must be a precompiled library Please enter the location of the library to be imported below Import Library Pathname o Browse lt Previous Next gt Cancel Follow the instructions in the wizard to complete the import UM 43 4 VHDL Simulation Chapter contents Compiling VHDL designs UM 45 Creating a design library UM 45 Invoking the VHDL compiler UM 45 Dependency checking UM 45 Range and index checking UM 45 Simulating VHDL designs UM 46 Invoking the simulator from the Mada window UM 46 Using the TextIO package UM 47 Syntax for file declaration i UM 47 Using STD_INPUT and STD OUTPUT within ModelSim UM 48 TextIO impleme
125. ale units Gating is level sensitive rather than edge triggered Adding HDL items to the List window ModelSim User s Manual Before adding items to the List window you may want to set the window display properties see Setting List window display properties UM 142 You can add items to the List window in several ways Adding items with drag and drop You can drag and drop items into the List window from the Signals Source Process Variables Wave Dataflow or Structure window Select the items in the first window then drop them into the List window Depending on what you select all items or any portion of the design may be added Adding items from the Main window command line Invoke the add list CR 32 command to add one or more individual items separate the names with a space add list lt item_name gt lt item_name gt You can add all the items in the current region with this command add list Or add all the items in the design with add list r Adding items with a List window format file To use a List window format file you must first save a format file for the design you are simulating The saved format file can then be used as a DO file to recreate the List window formatting Follow these steps e Add HDL items to your List window e Edit and format the items to create the view you want see Editing and formatting HDL items in the List window UM 145 e Save the format to a file
126. ambiguity ModelSim prints the 3rd alternative For example ModelSim gt vsim t 10ps VSIM gt echo Snow 0 ps For the when command CR 181 special processing is performed on comparisons involving the now variable If you specify when now 100 the simulator will stop at time 100 regardless of the multiplier applied to the time unit B ModelSim Shortcuts UM 291 Appendix contents Wave window mouse and keyboard shortcuts UM 291 List window keyboard shortcuts UM 292 Command shortcuts UM 293 Command history shortcuts UM 293 Mouse and keyboard shortcuts in Main and Source windows UM 293 Right mouse button UM 294 This appendix is a collection of the keyboard and command shortcuts available in the ModelSim GUI Wave window mouse and keyboard shortcuts The following mouse actions and keystrokes can be used in the Wave window Mouse action Result lt control left button click on a scroll arrow gt scrolls window to very top or bottom vertical scroll or far left or right horizontal scroll Keystroke Action il or zoom in o O or zoom out for F zoom full mouse pointer must be over the the cursor or waveform panes lor L zoom last ror R zoom range lt arrow up gt scroll waveform display up by selecting the item above the currently selected item lt arrow down gt scroll waveform display down by selecting the item below the
127. ame that is assigned to the WLF file when it is reloaded A dataset prefix identifies each WLF file that is opened The current active simulation is prefixed by sim while any datasets are prefixed by the name of the WLF file For example two datasets are displayed in the Wave window below the current simulation is shown in the top pane and is indicated by the sim prefix a dataset from a previous simulation is shown in the bottom pane and is indicated by the gold prefix File Edit Cursor Zoom Compare Bookmark Format Window le 3H wt SHS sO RAK ex RIAR m 1H lade sim top clk sim top prw sim top pstrb sim top prdy gold top clk gold top prwy gold top pstrb gold top prdy 2820 ns 340 ns Dons 2619 ns to 2831 ns gold top paddr 00000001 0000100 Ai a gt Note The simulator time resolution see Resolution UM 282 must be the same for all datasets you re comparing including the current simulation Saving a simulation to a WLF file ModelSim User s Manual The results of each simulation run are automatically saved to a WLF file called vsim wif in the current directory If you run a new simulation in the same directory the vsim wif file is overwritten with the new results Therefore you should use the w1f lt filename gt argument to the vsim command CR 168 to specify a different name if you want to save the WLF file A
128. and backslash substitution are performed on the characters between the quotes as described below The double quotes are not retained as part of the word If the first character of a word is an open brace then the word is terminated by the matching close brace Braces nest within the word for each additional open brace there must be an additional close brace however if an open brace or close brace within the word is quoted with a backslash then it is not counted in locating the matching close brace No substitutions are performed on the characters between the braces except for backslash newline substitutions described below nor do semi colons newlines close brackets or white space receive any special interpretation The word will consist of exactly the characters between the outer braces not including the braces themselves If a word contains an open bracket then Tcl performs command substitution To do this it invokes the Tcl interpreter recursively to process the characters following the open bracket as a Tcl script The script may contain any number of commands and must be terminated by a close bracket The result of the script i e the result of its last command is substituted into the word in place of the brackets and all of the characters between them There may be any number of command substitutions in a single word Command substitution is not performed on words enclosed in braces Tcl command syntax UM 257
129. andle_condition routine The value returned by acc_decompile_exp is the string representation of the condition expression char tf_dumpfilename void This routine returns the name of the VCD file void tf_dumpflush void A call to this routine flushes the VCD file buffer same effect as calling dumpflush in the Verilog code int tf_getlongsimtime int aof_hightime This routine gets the current simulation time as a 64 bit integer The low order bits are returned by the routine while the high order bits are stored in the aof_hightime argument 64 bit support in the PLI PLI VPI tracing ModelSim User s Manual The PLI function acc_fetch_paramval cannot be used on 64 bit platforms to fetch a string value of a parameter Because of this the function acc_fetch_paramval_str has been added to the PLI for this use acc_fetch_paramval_str is declared in acc_user h It functions in a manner similar to acc_fetch_paramval except that it returns a char acc_fetch_paramval_str can be used on all platforms The foreign interface tracing feature is available for tracing PLI and VPI function calls Foreign interface tracing creates two kinds of traces a human readable log of what functions were called the value of the arguments and the results returned and a set of C language files that can be used to replay what the foreign interface code did The purpose of tracing files The purpose of the logfile is to aid you in debug
130. aracter to differentiate them from compiler command line arguments The R option is not a Verilog XL option but it is used by ModelSim Verilog to combine the compile and simulate phases together as you may be used to doing with Verilog XL It is not recommended that you regularly use this option because you will incur the unnecessary overhead of compiling your design for each simulation run Mainly it is provided to ease the transition to ModelSim Verilog Verilog XL uselib compiler directive The uselib compiler directive is an alternative source library management scheme to the v y and libext compiler options It has the advantage that a design may reference different modules having the same name You compile designs that contain uselib directive statements using the compile_uselibs vlog switch described below The syntax for the uselib directive is uselib lt library_reference gt where lt library_reference gt is dir lt library_directory gt file lt library_file gt libext lt file_extension gt lib lt library_name gt In Verilog XL the library references are equivalent to command line options as follows dir lt library_directory gt y lt library_directory gt file lt library_file gt v lt library_file gt libext lt file_extension gt libext lt file_extension gt For example the following directive uselib dir h vendorA libext v is equivalent to the following command line op
131. aracters from the selected lines Selected Find find the specified text string or regular expression within the source file there is an option to match case or search backwards Find Next find the next occurrence of a string specified with the Find command Replace find the specified text string or regular expression and replace it with the specified text string or regular expression Previous Coverage Miss Source window UM 165 when simulating with Code Coverage UM 251 finds the previous line of code that was not used in the simulation Next Coverage Miss when simulating with Code Coverage UM 251 finds the next line of code that was not used in the simulation Breakpoints add edit or delete file line and signal breakpoints see Setting file line breakpoints UM 168 read only Object menu toggle the read only status of the current source file Describe display information about the selected HDL item same as the describe command CR 62 the item name is shown in the title bar Examine display the current value of the selected HDL item same as the examine CR 71 command the item name is shown in the title bar Options menu Colorize Source colorize key words variables and comments Highlight Executable Lines highlight the line numbers of executable lines Middle Mouse Button Paste enable disable pasting by pressing the middle mouse button
132. ary is the working library In all other aspects it is the same as any other library Working with design libraries UM 33 Working with design libraries The implementation of a design library is not defined within standard VHDL or Verilog Within ModelSim design libraries are implemented as directories and can have any legal name allowed by the operating system with one exception extended identifiers are not supported for library names Creating a library When you create a project see Getting started with projects UM 18 ModelSim automatically creates a working design library If you don t create a project you need to create a working design library before you run the compiler This can be done from either the command line or from the ModelSim graphic interface From the ModelSim prompt or a DOS prompt use this vlib command CR 161 vlib lt directory_pathname gt To create a new library with the ModelSim graphic interface select Design gt Create a New Library Main window This brings up a dialog box that allows you to specify the library name and its logical mapping Create a New Library OF x Create anew library and a logical mapping to it a map to an existing library Library Name o Z fa X OK Cancel The Create a New Library dialog box includes these options Create a new library and a logical mapping to it Type the new library name into the Library Name f
133. ary where a design unit is stored after it is compiled as described earlier There is no limit to the number of libraries that can be referenced but only one library is modified during compilation Specifying the resource libraries UM 41 Alternate IEEE libraries supplied The installation directory may contain two or more versions of the IEEE library ieeepure Contains only IEEE approved std_logic_1164 packages accelerated for ModelSim ieee Contains precompiled Synopsys and IEFE arithmetic packages which have been accelerated by Model Technology including math_complex math_real numeric_bit numeric_std std_logic_1164 std_logic_misc std_logic_textio std_logic_arith std_logic_signed std_logic_unsigned vital_primitives vital_timing and vital_memory You can select which library to use by changing the mapping in the modelsim ini file The modelsim ini file in the installation directory defaults to the ieee library VITAL 2000 library ModelSim versions 5 5 and later include a separate VITAL 2000 library that contains an accelerated vital_memory package You ll need to add a use clause to your VHDL code to access the package For example LIBRARY vital2000 USE vital2000 vital_memory all Also when you compile use the vital2000 switch to vcom CR 129 Regenerating your design libraries Depending on your current ModelSim version you may need to regenerate your design libraries before running a simulation Chec
134. ate a dynamically loadable object for ModelSim Verilog In this case you must get the third party application vendor to supply the object files compiled as position independent code ModelSim User s Manual UM 96 5 Verilog Simulation Support for VHDL objects The PLI ACC routines also provide limited support for VHDL objects in an all VHDL design The following table lists the VHDL objects for which handles may be obtained and their type and fulltype constants Type Fulltype Description accArchitecture accArchitecture instantiation of an architecture accArchitecture accEntity VitalLevelO instantiation of an architecture whose entity is marked with the attribute VITAL_Level0 accArchitecture accArchVitalLevelO instantiation of an architecture which is marked with the attribute VITAL_LevelO accArchitecture accArchVitalLevel1 instantiation of an architecture which is marked with the attribute VITAL _Levell accArchitecture accForeignArch instantiation of an architecture which is marked with the attribute FOREIGN and which does not contain any VHDL statements or objects other than ports and generics accArchitecture accForeignArchMixed instantiation of an architecture which is marked with the attribute FOREIGN and which contains some VHDL statements or objects besides ports and generics accBlock accBlock block statement accForLoop accForLoop for loop
135. ave window to a selected printer options include All signals print all signals Current View print signals in current view for the time displayed Selected print all or current view signals for user designated time Wave window UM 183 Print Postscript save or print the waveform display as a Postscript file options include All Signals print all signals Current View print signals in current view for the time displayed Selected print all or current view signals for user designated time New Window split the pathname values and waveform window panes to provide Pane room for a new waveset Remove remove window split and active waveset Window Pane Refresh Display clear the Wave window empty the file cache and rebuild the window from scratch Close close this copy of the Wave window Edit menu Cut cut the selected item and waveform from the Wave window see Editing and formatting HDL items in the Wave window UM 192 Copy copy the selected item and waveform Paste paste the previously cut or copied item above the currently selected item Delete delete the selected item and its waveform Select All select or unselect all item names in the name pane Unselect All Combine combine the selected fields into a user defined bus Signal Breakpoints add edit and delete signal breakpoints see Setting signal breakpoints UM 160 Sort sort the top level
136. by selecting File gt Save Format List window List window UM 145 To use the format do file start with a blank List window and run the DO file in one of two ways e Invoke the do CR 64 command from the command line do lt my_list_format gt e Select File gt Load Format from the List window menu bar Select Edit gt Select All and Edit gt Delete to remove the items from the current List window or create a new blank List window by selecting View gt New gt List Main window You may find it useful to have two differently formatted windows open at the same time see Examining simulation results with the List window UM 148 gt Note List window format files are design specific use them only with the design you were simulating when they were created If you try to use the wrong format file ModelSim will advise you of the HDL items it expects to find Editing and formatting HDL items in the List window Once you have the HDL items you want in the List window you can edit and format the list to create the view you find most useful See also Adding HDL items to the List window UM 144 To edit an item Select the item s label at the top of the List window or one of its values from the listing Move copy or remove the item by selecting commands from the List window Edit menu UM 140 menu You can also click drag to move items within the window to select several contiguous items click drag to select
137. c names to those expected by the annotator Look in the VHDL source files provided by the cell library vendor If none of the generic names look like VITAL timing generic names then perhaps the VITAL library cells are not being used If the generic names do look like VITAL timing generic names but don t match the names expected by the annotator then there are several possibilities The vendor s tools are not conforming to the VITAL specification The SDF file was accidentally applied to the wrong instance In this case the simulator also issues other error messages indicating that cell instances in the SDF could not be located in the design The vendor s library and SDF were developed for the older VITAL 2 2b specification This version uses different name mapping rules In this case invoke vsim CR 168 with the vital2 2b option vsim vital2 2b sdfmax testbench ul myasic sdf testbench For more information on resolving errors see Troubleshooting UM 245 ModelSim User s Manual UM 238 8 Standard Delay Format SDF Timing Annotation Verilog SDF Verilog designs can be annotated using either the simulator command line options or the sdf_annotate system task also commonly used in other Verilog simulators The command line options annotate the design immediately after it is loaded but before any simulation events take place The sdf_annotate task annotates the design at the time it is called in the Verilog source c
138. cc_fetch_itfarg_int acc_fetch_tfarg_str acc_fetch_itfarg_str acc_fetch_timescale_info acc_fetch_type acc_fetch_type_str acc_fetch_value acc_free acc_handle_by_name acc_handle_calling_ mod_m acc_handle_condition acc_handle_conn acc_handle_hiconn acc_handle_interactive_scope acc_handle_loconn acc_handle_modpath acc_handle_ notifier acc_handle_object acc_handle_parent acc_handle_path acc_handle_pathin acc_handle_pathout acc_handle_port acc_handle_scope acc_handle_simulated_net acc_handle_tchk acc_handle_tchkarg1 acc_handle_tchkarg2 acc_handle_terminal acc_handle_tfarg acc_handle_itfarg acc_handle_tfinst acc_initialize acc_next acc_next_bit acc_next_cell acc_next_cell_load acc_next_child acc_next_driver acc_next_hiconn acc_next_input acc_next_load acc_next_loconn acc_next_modpath acc_next_net acc_next_output acc_next_parameter acc_next_port acc_next_portout ModelSim User s Manual UM 98 5 Verilog Simulation acc_next_primitive acc_next_scope acc_next_specparam acc_next_tchk acc_next_terminal acc_next_topmod acc_object_in_typelist acc_object_of_type acc_product_type acc_product_version acc_release_object acc_replace_delays acc_replace_pulsere acc_reset_buffer acc_set_interactive_scope acc_set_pulsere acc_set_sco
139. ce between value and units i e 10fs not 10 fs RunLength positive integer default simulation length in units specified 100 by the UserTimeUnit variable Startup do lt DO specifies the ModelSim startup macro see commented filename gt any the do command CR 64 out valid macro do file StdArithNoWarnings 0 1 if 1 warnings generated within the off 0 accelerated Synopsys std_arith packages are suppressed TranscriptFile any valid file for saving command transcript transcript filename environment variables may be included in the path name UnbufferedOutput 0 1 controls VHDL and Verilog files open for 0 write 0 Buffered 1 Unbuffered UserTimeUnit fs ps ns us ms specifies the default units to use for the ns sec or default lt timesteps gt lt time_units gt argument to the run command CR 107 NOTE the value of this variable must be set equal to or larger than the current simulator resolution specified by the Resolution variable shown above Veriuser one or more valid list of dynamically loadable objects for commented shared objects Verilog PLI VPI applications see Verilog out PLI VPI UM 86 WaveSignalName Width 0 positive controls the number of visible hierarchical 0 integer regions of a signal name shown in the Wave ModelSim User s Manual window UM 178 the default value of zero displays the full name a setting of one or above displays the corresponding level s of hierarchy
140. command CR 70 to change the active dataset ModelSim remembers a current context within each open dataset You can toggle between the current context of each dataset using the environment command CR 70 specifying the dataset without a path For example env foo sets the active dataset to foo and the current context to the context last specified for foo The context is then applied to any unlocked windows The current context of the current dataset usually referred to as just current context is used for finding objects specified without a path The Signals window can be locked to a specific context of a dataset Being locked to a dataset means that the window will update only when the content of that dataset changes If locked to both a dataset and a context e g test top foo the window will update only when that specific context changes You specify the dataset to which the window is locked by selecting File gt Environment Signals window Restricting the dataset prefix display The default for dataset prefix viewing is set with a variable in pref tcl PrefMain DisplayDatasetPrefix Setting the variable to 1 will display the prefix setting it to 0 will not It is set to 1 by default Either edit the pref tcl file directly or use the Options gt Edit Preferences Main window command to change the variable value Additionally you can restrict display of the dataset prefix if you use the environment nodataset comman
141. commands Multiple datasets can be opened when the simulator is invoked by specifying more than one vsim view lt filename gt option By default the dataset prefix will be the filename of the WLF file A different dataset name can also be specified as an optional qualifier to the vsim view switch on the command line using the following syntax view lt dataset gt lt filename gt For example vsim view foo vsim wlf ModelSim User s Manual WLF files datasets UM 109 Design regions and signal names can be fully specified over multiple WLF files by using the dataset name as a prefix in the path For example sim top alu out view top alu out golden top alu out Dataset prefixes are not required unless more than one dataset is open and you want to refer to something outside the default dataset When more than one dataset is open ModelSim will automatically prefix names in the Wave and List window with the dataset name You can change this default by selecting Edit gt Display Properties Wave window and Prop gt Display Props List window ModelSim designates one of the datasets to be the active dataset and refers all names without dataset prefixes to that dataset The active dataset is displayed in the context path at the bottom of the Main window When you select a design unit in a dataset s Structure tab that dataset becomes active automatically Alternatively you can use the Dataset Browser or the environment
142. configurations before an architecture that references them You can simulate a design containing units written with both the 1076 1987 and 1076 1993 versions of VHDL To do so you will need to compile units from each VHDL version separately The vcom CR 129 command compiles units written with version 1076 1987 by default use the 93 option with vcom CR 129 to compile units written with version 1076 1993 You can also change the default by modifying the modelsim ini file see Preference variables located in INI files UM 278 for more information Dependency checking Dependent design units must be reanalyzed when the design units they depend on are changed in the library vcom CR 129 determines whether or not the compilation results have changed For example if you keep an entity and its architectures in the same source file and you modify only an architecture and recompile the source file the entity compilation results will remain unchanged and you will not have to recompile design units that depend on the entity Range and index checking A range check verifies that a scalar value defined with a range subtype is always assigned a value within its range An index check verifies that whenever an array subscript expression is evaluated the subscript will be within the array s range Index checks are performed by default when you compile your design In versions 5 5 and later range checks are not performed by default You can sp
143. cros Tcl command syntax The following eleven rules define the syntax and semantics of the Tcl language Additional details on if command syntax UM 258 and set command syntax UM 259 follow 1 A Tcl script is a string containing one or more commands Semi colons and newlines are 2 6 ModelSim User s Manual command separators unless quoted as described below Close brackets are command terminators during command substitution see below unless quoted A command is evaluated in two steps First the Tcl interpreter breaks the command into words and performs substitutions as described below These substitutions are performed in the same way for all commands The first word is used to locate a command procedure to carry out the command then all of the words of the command are passed to the command procedure The command procedure is free to interpret each of its words in any way it likes such as an integer variable name list or Tcl script Different commands interpret their words differently Words of a command are separated by white space except for newlines which are command separators If the first character of a word is double quote then the word is terminated by the next double quote character If semi colons close brackets or white space characters including newlines appear between the quotes then they are treated as ordinary characters and included in the word Command substitution variable substitution
144. cttf miscellaneous reason callback function char tfname name of system task or function The following fields are ignored by ModelSim Verilog int forwref char tfveritool char tferrmessage int hash struct t_tfcell left_p struct t_tfcell right_p char namecell_p int warning_printed s_tfcell p_tfcell The various callback functions checktf sizetf calltf and misctf are described in detail in the IEEE Std 1364 The simulator calls these functions for various reasons All callback functions are optional but most applications contain at least the calltf function which is called when the system task or function is executed in the Verilog code The first argument to the callback functions is the value supplied in the data field many PLI applications don t use this field The type field defines the entry as either a system task USERTASK or a Verilog PLIVPI UM 87 system function that returns either a register USERFUNCTION or a real USERREALFUNCTION The tfname field is the system task or function name it must begin with The remaining fields are not used by ModelSim Verilog On loading of a PLI application the simulator first looks for an init_usertfs function and then a veriusertfs array If init_usertfs is found the simulator calls that function so that it can call mti_RegisterUserTF for each system task or function defined The mti_RegisterUserTF function is declared in veriuser h as f
145. currently selected item lt arrow left gt scroll waveform display left ModelSim User s Manual UM 292 B ModelSim Shortcuts Keystroke Action lt arrow right gt scroll waveform display right lt page up gt scroll waveform display up by a page lt page down gt scroll waveform display down by a page lt tab gt search forward right to the next transition on the selected signal finds the next edge lt shift tab gt search backward left to the previous transition on the selected signal finds the previous edge lt control f gt open the find dialog box searches within the specified field in the pathname pane for text strings List window keyboard shortcuts Using the following keys when the mouse cursor is within the List window will cause the indicated actions Key Action lt arrow up gt scroll listing up selects and highlights the line above the currently selected line lt arrow down gt scroll listing down selects and highlights the line below the currently selected line lt arrow left gt scroll listing left lt arrow right gt scroll listing right lt page up gt scroll listing up by page lt page down gt scroll listing down by page lt tab gt searches forward down to the next transition on the selected signal lt shift tab gt searches backward up to the previous transition on th
146. d List windows and accessed by the examine command CR 71 but cannot be set by the force command CR 76 Examples of virtual functions include the following e a function defined as the inverse of a given signal e a function defined as the exclusive OR of two signals e a function defined as a repetitive clock e a function defined as the rising edge of CLK delayed by 1 34 ns Virtual functions can also be used to convert signal types and map signal values The result type of a virtual signal can be any of the types supported in the GUI expression syntax integer real boolean std_logic std_logic_vector and arrays and records of these types Verilog types are converted to VHDL 9 state std_logic equivalents and Verilog net strengths are ignored ModelSim User s Manual UM 112 6 WLF files datasets and virtuals Virtual regions Virtual types ModelSim User s Manual Virtual functions can be created using the virtual function command CR 144 Virtual functions are also implicitly created by ModelSim when referencing bit selects or part selects of Verilog registers in the GUI or when expanding Verilog registers in the Signals Wave or List windows This is necessary because referencing Verilog register elements requires an intermediate step of shifting and masking of the Verilog vreg data structure User defined design hierarchy regions can be defined and attached to any existing design region or to the virtuals context
147. d SDF options Delay Selection sdfmin sdftyp sdfmax The drop down menu selects delay timing min typ or max to be used from the specified SDF file See also Specifying SDF files for simulation UM 234 The OK button places the specified SDF file and delay on the Region File list Cancel dismisses the dialog box without changes Disable SDF warnings sdfnowarn Select to disable warnings from the SDF reader Reduce SDF errors to warnings sdfnoerror Change SDF errors to warnings so the simulation can continue Multi Source Delay multisource_delay lt sdf_option gt Select max min or latest delay Controls how multiple PORT or INTERCONNECT constructs that terminate at the same port are handled By default the Module Input Port Delay MIPD is set to the max value encountered in the SDF file Alternatively you can choose the min or latest of the values ModelSim User s Manual UM 226 7 Graphic Interface Setting default simulation options Select Options gt Simulation Main window to bring up the Simulation Options dialog box shown below Options you can set for the current simulation include default radix default force type default run length iteration limit warning suppression break on assertion specifications and WLF file configuration OK accepts the changes made and closes the dialog box Apply makes the changes with the dialog box open so you can test your settings Cancel closes the dialog box
148. d by the MTI_USELIB_DIR environment variable see Environment variables UM 275 e A directory named mti_uselibs that is created in the current working directory gt Note In ModelSim versions prior to 5 5 the library files referenced by the uselib directive were not automatically compiled by ModelSim Verilog To maintain backwards compatibility this is still the default behavior when compile_uselibs is not used See Pre 5 5 release implementation of uselib directives for a description of the pre 5 5 implementation uselib is persistent As mentioned above the appearance of a uselib directive in the source code explicitly defines how instantiations that follow it are resolved This may result in unexpected consequences For example consider the following compile command vlog compile_uselibs dut v srtr v Assume that dut v contains a uselib directive Since srtr v is compiled after dut v the uselib directive is still in effect When srtr is loaded it is using the uselib directive from dut v to decide where to locate modules If this is not what you intend then you need to put an empty uselib at the end of dut v to close the previous uselib statement Simulation UM 69 Simulation The ModelSim simulator can load and simulate both Verilog and VHDL designs providing a uniform graphic interface and simulation control commands for debugging and analyzing your designs The graphic interface and simula
149. d delta visible on the left FS list T_jol x File Edit Markers Prop Window ns y top clk y top paddr top pdata top saddr aa delta ztop prw top stw gt top pstrb 4 top sstb 4 top prdy 4 top stdy 4 500 0 1 0 1 1 00000010 0000000000000010 0 0 1 00000010 22777 505 0 1 0 1 1 00000010 0000000000000010 0 1 1 00000010 00000 520 0 001 1 00000010 0000000000000010 0 1 1 00000010 000OOI 540 0 1 0 1 1 00000010 0000000000000010 0 1 1 00000010 00000 p 560 0 001 1 00000010 0000000000000010 0 1 1 00000010 00000 580 0 1 0 1 1 00000010 0000000000000010 0 1 1 00000010 00000 585 0 1 0 1 1 00000010 0000000000000010 0 1 0 00000010 00000 590 0 1 0 1 0 00000010 0000000000000010 0 1 0 00000010 000001 600 0 0 O 1 0 00000010 0000000000000010 0 1 0 00000010 00000 620 0 1 0 1 0 00000010 0000000000000010 0 1 0 00000010 00000 625 0 100 1 00000011 ZZZZZZ7777 227741 1 00000010 ZZZzzz i Default dataset sim a HDL items you can view One entry is created for each of the following VHDL and Verilog HDL items within the design e VHDL items signals and process variables e Verilog items nets and register variables e Virtual items Virtual signals and functions P Note Constants generics and parameters are not viewable in the List or Wave windows ModelSim User s Manual UM 140 7 Graphic Interface The List window menu bar The following menu commands are available from the List wind
150. d other simulator window characteristics see Preference variables located in Tcl files UM 287 for specific details on the modelsim tcl file ModelSim User s Manual UM 28 2 Projects and system initialization Environment variables accessed during startup The table below describes the environment variables that are read during startup They are listed in the order in which they are accessed For more information on environment variables see Environment variables UM 275 Environment variable Purpose MODEL_TECH set by ModelSim to the directory in which the binary executables reside e g modeltech lt platform gt MODEL_TECH_OVERRIDE provides an alternative directory for the binary executables MODEL_TECH is set to this path MODELSIM identifies path to the modelsim ini file MGC_WD identifies the Mentor Graphics working directory set by Mentor Graphics tools MGC_LOCATION_MAP identifies the path to the location map file set by ModelSim if not defined MODEL_TECH_TCL identifies the path to all Tcl libraries installed with ModelSim HOME identifies your login directory UNIX only MGC_HOME identifies the path to the MGC tool suite TCL_LIBRARY identifies the path to the Tcl library set by ModelSim to the same path as MODEL_TECH_TCL must point to libraries supplied by Model Technology TK_LIBRARY identifies the path to the Tk library set by ModelS
151. d to view a dataset To display the prefix use the environment command CR 70 with the dataset option you won t need to specify this option if the variable noted above is set to 1 The environment command line switches override the pref tcl variable ModelSim User s Manual UM 110 6 WLF files datasets and virtuals Virtual Objects User defined buses and more Virtual objects are signal like or region like objects created in the GUI that do not exist in the ModelSim simulation kernel Beginning with release 5 3 ModelSim supports the following kinds of virtual objects e Virtual signals UM 110 e Virtual functions UM 111 e Virtual regions UM 112 e Virtual types UM 112 Virtual objects are indicated by an orange diamond as illustrated by BUSI below waye default 4 Dj x File Edit Cursor Zoom Compare Bookmark Format Window SHS BB RA tr QQQAQH le si ww iw wi x fe it top clk 1 top prw 1 top pstrb 1 top prdy 0 top paddr 00001001 Ce 2s Ge Gee Gee ee es top pdata 0000000000001001 H H HHHH HHHX top BUS1 011 Yori Yor F 2 top srw 0 1 top sstrb 1 O top srdy 1 0 top stw RRR 1870 ns to 2725 ns Lf 2820 ns Ons Virtual signals Virtual signals are aliases for combinations or subelements of signals written to the WLF file by the simulation kernel They can be displayed in the Signals List and Wave windows accessed b
152. der a path delay of 10 along with a pulse_e 80 option The error limit is 80 of 10 and the rejection limit defaults to 80 of 10 This results in the propagation of pulses greater than or equal to 8 while all other pulses are filtered Note that you can force specify path delays to operate in transport mode by using the pulse_e 0 option t pulse_int_e lt percent gt This option is analogous to pulse_e except it applies to interconnect delays only t pulse_int_r lt percent gt This option is analogous to pulse_r except it applies to interconnect delays only t pulse_r lt percent gt This option controls how pulses are propagated through specify path delays where lt percent gt is a number between 0 and 100 that specifies the rejection limit as a percentage of the path delay A pulse less than the rejection limit is suppressed from propagating to ModelSim User s Manual UM 74 5 Verilog Simulation ModelSim User s Manual the output If the error limit is not specified see pulse_e UM 73 then it defaults to the rejection limit t pulse_e_style_ondetect This option selects the on detect style of propagating pulse errors see pulse_e lt percent gt A pulse error propagates to the output as an X and the on detect style is to schedule the X immediately as soon as it has been detected that a pulse error has occurred The on event style is the default for propagating pulse errors see tpulse_e_style_onevent
153. ding zero BodyN may also be omitted as long as else is omitted too The return value from the command is the result of the body script that was executed or an empty string if none of the expressions was non zero and there was no bodyN ModelSim User s Manual Tcl command syntax UM 259 set command syntax The Tcl set command reads and writes variables Note that in the syntax below the indicates an optional argument Syntax set varName value Description Returns the value of variable varName If value is specified then sets the value of varName to value creating a new variable if one doesn already exist and returns its value If varName contains an open parenthesis and ends with a close parenthesis then it refers to an array element the characters before the first open parenthesis are the name of the array and the characters between the parentheses are the index within the array Otherwise varName refers to a scalar variable Normally varName is unqualified does not include the names of any containing namespaces and the variable of that name in the current namespace is read or written If varName includes namespace qualifiers in the array name if it refers to an array element the variable in the specified namespace is read or written If no procedure is active then varName refers to a namespace variable global variable if the current namespace is the global namespace If a procedure is active then varName r
154. dow or the radix command CR 101 You can change the default radix permanently by editing the DefaultRadix UM 281 variable in the modelsim ini file For the other radixes binary octal decimal unsigned hexadecimal or ASCII the item value is converted to an appropriate representation in that radix In the system initialization file modelsim tcl you can specify the list translation rules for arrays of enumerated types for binary octal decimal unsigned decimal or hexadecimal item values in the design unit List window UM 147 e Width Allows you to specify the desired width of the column used to list the item value The default is an approximation of the width of the current value Trigger Triggers line Specifies that a change in the value of the selected item causes a new line to be displayed in the List window Trigger Does not trigger line Specifies that a change in the value of the selected item does not affect the List window The trigger specification affects the trigger property of the selected item See also Setting List window display properties UM 142 ModelSim User s Manual UM 148 7 Graphic Interface Examining simulation results with the List window Because you can use the Main window View menu UM 128 to create a second List window you can reformat another List window after the simulation run if you decide a different format would reveal the information you re after Compare the two illu
155. ds the hierarchy so the sub elements of that item can be seen Clicking contracts the hierarchy sim top 4 The first line of the Structure window indicates the top level design unit being simulated By default this is the only level of the hierarchy that is expanded upon opening the Structure window Structure window UM 173 Instance name components in the Structure window An instance name displayed in the Structure window consists of the following parts e instantiation label Indicates the label assigned to s s0 cache_set only the component or module instance in the instantiation we statement F eke architecture instantiation label entity or module entity or module Indicates the name of the entity or module that has been instantiated e architecture Indicates the name of the architecture associated with the entity not present for Verilog When you select a region in the Structure window it becomes the current region and is highlighted the Source window UM 163 and Signals window UM 155 change dynamically to reflect the information for that region This feature provides a useful method for finding the source code for a selected region because the system keeps track of the pathname where the source is located and displays it automatically without the need for you to provide the pathname Also when you select a region in the Structure window the Process window UM 152 is updated if In Region is select
156. dural Interface VPI If the simulator issues warnings regarding undefined system tasks then it is likely that these system tasks are defined by a PLI VPI application that must be loaded by the simulator IEEE Std 1364 system tasks The following system tasks are described in detail in the IEEE Std 1364 Timescale tasks printtimescale timeformat Probabilistic distribution functions dist_chi_square dist_erlang dist_exponential dist_normal dist_poisson dist_t dist_uniform random Simulator control tasks finish stop Conversion functions bitstoreal itor realtobits rtoi signed Sunsigned Simulation time functions realtime stime time Stochastic analysis tasks q_add q_exam q_full q_initialize q_remove Command line input test plusargs value plusargs Timing check tasks hold nochange period recovery setup setuphold skew width removal recrem ModelSim User s Manual UM 78 5 Verilog Simulation ModelSim User s Manual Display tasks display displayb displayh displayo monitor monitorb monitorh monitoro monitoroff monitoron strobe strobeb strobeh strobeo write writeb writeh writeo PLA modeling tasks async and array async nand array async or array async nor array async and plane async nand plane async or plane async nor plane sync and array sync nand array sync or arra
157. e libraries are loaded in the order listed above Environment variable references can be used in the paths to the libraries in all cases See also Appendix A ModelSim Variables for more information on the modelsim ini file Verilog PLI VP UM 91 PLI example The following example is a trivial but complete PLI application hello c include veriuser h static hello io_printf Hi there n s_tfcell veriusertfs usertask 0 0 0 hello 0 hello 0 last entry must be 0 hello v module hello initial hello endmodule Compile the PLI code for the Solaris operating system cc c I lt install_dir gt modeltech include hello c ld G o hello sl hello o le Compile the Verilog code vlib work x 5 vlog hello v Simulate the design vsim c pli hello sl hello Loading work hello Loading hello sl VSIM 1 gt run all Hi there VSIM 2 gt quit ModelSim User s Manual UM 92 5 Verilog Simulation VPI example The following example is a trivial but complete VPI application hello c include vpi_user h static hello vpi_printf Hello world n void RegisterMyTfs void s_vpi_systf_data systf_data systf_data type vpiSysTask systf_data sysfunctype vpiSysTask systf_data tfname Shello systf_data calltf hello systf_data compiletf 0 systf_data sizetf 0 systf_data user_data 0 vpi_register_systf amp systf_data
158. e lt time gt lt time gt add time divTime lt time gt lt time gt 64 bit integer divide mulTime lt time gt lt time gt 64 bit integer multiply subTime lt time gt lt time gt subtract time ModelSim User s Manual Tcl examples UM 265 Tcl examples Example 1 The following Tcl ModelSim example for UNIX shows how you can access system information and transfer it into VHDL variables or signals and Verilog nets or registers When a particular HDL source breakpoint occurs a Tcl function is called that gets the date and time and deposits it into a VHDL signal of type STRING If a particular environment variable DO_ECHO is set the function also echoes the new date and time to the transcript file by examining the VHDL variable gt Note In a Windows environment the Tcl exec command shown below will execute compiled files only not system commands in VHDL source signal datime string 1 to 28 28 spaces on VSIM command line or in macro proc set_date global env set do_the_echo set env DO_ECHO set s exec date force deposit datime s if do_the_echo echo New time is examine value datime bp src waveadd vhd 133 set_date continue sets the breakpoint to call set_date This is an example of using the Tcl while loop to copy a list from variable a to variable b reversing the order of the elements along the way set p set i expr llength a 1 while
159. e CR 166 vmap CR 167 vsim CR 168 VSIM Tcl commands UM 262 vsimDate CR 179 vsimId CR 179 vsimVersion CR 179 WaveActivateNextPane CR 189 WaveRestoreCursors CR 189 WaveRestoreZoom CR 189 when CR 181 where CR 185 wlf2log CR 186 write format CR 188 write list CR 190 write preferences CR 191 write report CR 192 write transcript CR 193 write tssi CR 194 write wave CR 196 Comment characters in VSIM commands CR 6 compare simulations UM 103 Compiler directives UM 84 IEEE Std 1364 2000 UM 84 XL compatible compiler directives UM 85 Compiling locating source errors UM 212 range checking in VHDL CR 132 UM 45 setting default options UM 213 setting options in projects UM 25 setting order in projects UM 24 Verilog CR 162 UM 61 incremental compilation UM 62 XL uselib compiler directive UM 67 XL compatible options UM 65 VHDL CR 129 UM 45 at a specified line number line lt number gt CR 130 selected design units just eapbc CR 130 standard package s CR 132 with the graphic interface UM 211 with VITAL packages UM 53 concatenation directives CR 17 of signals CR 17 CR 156 ConcurrentFileLimit ini file variable UM 280 configuration simulator state variable UM 289 Configurations simulating CR 168 configure command CR 51 Constants displaying values of CR 62 CR 71 constants used in case statements CR 130 context menus described UM 120 Library page UM 35 Signal window UM 160 Structure pages UM 106 UM 309 convert real to
160. e Edit Cursor Zoom Compare Bookmark Format Window oH aei RHA HX QQQQE EF LETENG iaie ie hw top clk top prw top pstrb top prdy 1 1 1 0 top paddr 00001001 mann a yy USCC in 2 a top pdata 0000000000001001 We sia as e ftop BUST E E 2 top srw 0 e E n E a HH a 011 omy yor 1 top sstrb 1870 ns to 2725 1 0 top srdy 1 top sry 0 ns E Other virtual items in the Wave window See Virtual Objects User defined buses and more UM 110 for information about other virtual items viewable in the Wave window Editing and formatting HDL items in the Wave window ModelSim User s Manual Once you have the HDL items you want in the Wave window you can edit and format the list in the pathname and values panes to create the view you find most useful See also Setting Wave window display properties UM 197 To edit an item Select the item s label in the pathname pane or its waveform in the waveform pane Move copy or remove the item by selecting commands from the Wave window Edit menu UM 183 You can also click drag to move items within the pathnames and values panes e to select several items control click to add or subtract from the selected group e to move the selected items re click and hold on one of the selected items then drag to the new location Wave window UM 193 To format an item Select the item s label i
161. e acc_handle_datapath routine We did not implement the acc_handle_datapath routine because the information it returns is more appropriate for a static timing analysis tool In version 5 5e the VPI is partially implemented as defined in the IEEE Std 1364 The list of currently supported functionality can be found in the following directory lt install_dir gt modeltech docs technotes Verilog_VPI note The IEEE Std 1364 is the reference that defines the usage of the PLI VPI routines This manual only describes details of using the PLI VPI with ModelSim Verilog Registering PLI applications ModelSim User s Manual Each PLI application must register its system tasks and functions with the simulator providing the name of each system task and function and the associated callback routines Since many PLI applications already interface to Verilog XL ModelSim Verilog PLI applications make use of the same mechanism to register information about each system task and function in an array of s_tfcell structures This structure is declared in the veriuser h include file as follows typedef int p_tffn typedef struct t_tfcell short type USERTASK USERFUNCTION or USERREALFUNCTION short data passed as data argument of callback function p_tffn checktf argument checking callback function p_tffn sizetf function return size callback function p_tffn calltf task or function call callback function p_tffin mis
162. e format CR 186 Quiet ini file variable VCOM UM 279 VLOG UM 280 quietly command CR 99 quit command CR 100 R R UM 67 Radix changing in Signals Variables Dataflow List and Wave windows CR 101 of signals being examined CR 71 of signals in Wave window CR 37 specifying in List window UM 146 specifying in Signals window UM 158 user defined character strings CR 159 radix command CR 101 range checking UM 45 disabling CR 131 enabling CR 132 RangeCheck ini file variable UM 282 real type converting to time UM 57 Reconstruct RTL level design busses UM 111 Records changing values of UM 175 Redirecting messages TranscriptFile UM 282 Refreshing library images CR 132 CR 164 UM 41 Register variables adding to the Wave and List windows UM 159 displaying values in Signals window UM 155 saving values as binary log file UM 159 viewing waveforms UM 178 ModelSim User s Manual report command CR 102 RequireConfigForAl DefaultBinding variable UM 279 Resolution UM 46 UM 54 specifying with t argument CR 171 Resolution ini file variable UM 282 resolution simulator state variable UM 289 Resource library UM 32 Restart UM 129 UM 131 UM 188 restart command CR 104 defaults UM 286 Restoring defaults UM 274 Results saving simulations UM 103 resume command CR 106 run command CR 107 RunLength ini file variable UM 282 S Saving and viewing waveforms UM 103 SDF errors and warnings UM 235 instance specification UM 234 interconnect
163. e selected signal does not function on HP workstations lt control f gt ModelSim User s Manual opens the find dialog box finds the specified item label within the list display Command shortcuts Command shortcuts UM 293 You may abbreviate command syntax but there s a catch the minimum characters required to execute a command are those that make it unique Remember as we add new commands some of the old shortcuts may not work Command history shortcuts The simulator command history may be reviewed or commands may be reused with these shortcuts at the ModelSim VSIM prompt Shortcut Description up and down arrows scrolls through the command history with the keyboard arrows click on prompt cursor left click once on a previous ModelSim or VSIM prompt in the transcript to copy the command typed at that prompt to the active history shows the last few commands up to 50 are kept Mouse and keyboard shortcuts in Main and Source win dows The following mouse actions and special keystrokes can be used to edit commands in the entry region of the Main window They can also be used in editing the file displayed in the Source window and all Notepad windows enter the notepad command within ModelSim to open the Notepad editor Keystrokes Result lt left right arrow gt move the cursor left right one character lt up down arrow gt scroll
164. e set for the current session only Transcript File set a transcript file to save for this session only Command History file for saving command history only no comments Save File set filename for Save Transcript and Save Transcript As Saved Lines limit the number of lines saved in the transcript default is 5000 Line Prefix specify the comment prefix for the transcript Update Rate specify the update frequency for the Main status bar ModelSim Prompt change the title of the ModelSim prompt VSIM Prompt change the title of the VSIM prompt Paused Prompt change the title of the Paused prompt lt path list gt a list of the most recent working directory changes Quit quit ModelSim ModelSim User s Manual Main window UM 127 Edit menu Copy copy the selected text Paste paste the previously cut or copied text to the left of the currently selected text Select All select all text in the Main window transcript Unselect All deselect all text in the Main window transcript Find search the transcript forward or backward for the specified text string Breakpoints open the Breakpoints dialog box see Setting file line breakpoints UM 168 for details Design menu Browse Libraries browse all libraries within the scope of the design Create a New create a new library or map a library to a new name Library Compile compile HDL source files into the current proj
165. e used to edit commands in the entry region of the Main window They can also be used in editing the file displayed in the Source window and all Notepad windows enter the notepad command within ModelSim to open the Notepad editor UM 133 for a list of mouse and keyboard editing options Checking HDL item values and descriptions There are two quick methods to determine the value and description of an HDL item displayed in the Source window e select an item then chose Object gt Examine or Object gt Description from the Source window menu e select an item with the right mouse button to see an examine pop up select now to examine the current simulation time in VHDL code You can also invoke the examine CR 71 and or describe CR 62 command on the command line or in a macro Finding and replacing in the Source window ModelSim User s Manual The Find dialog box allows you to find and replace text strings or regular expressions in the Source window Select Edit gt Find or Edit gt Replace to bring up the Find dialog box If you select Edit gt Find the Replace field is absent from the dialog Enter the value to search for in the Find in source Find field If you are doing a replace Find Find Next enter the appropriate value in the Replace I Case sensitive I Search backwards Close field Optionally specify whether the entries are case sensitive and whether to search backwards from the current cur
166. e variables such as environment variables must be set prior to simulation See Appendix A ModelSim Variables for a complete listing of ModelSim variables Compilation UM 61 Compilation Before you can simulate a Verilog design you must first create a library and compile the Verilog source code into that library This section provides detailed information on compiling Verilog designs For information on creating a design library see Chapter 3 Design libraries The ModelSim Verilog compiler vlog compiles Verilog source code into retargetable executable code meaning that the library format is compatible across all supported platforms and that you can simulate your design on any platform without having to recompile your design specifically for that platform As you compile your design the resulting object code for modules and UDPs is generated into a library By default the compiler places results into the work library You can specify an alternate library with the work option The following is a simple example of how to create a work library compile a design and simulate it Contents of top v module top initial display Hello world endmodule Create the work library o vlib work Compile the design vlog top v Compiling module top Top level modules top View the contents of the work library optional 2 vdir MODULE top Simulate the design vsim c top Loading work top VSIM 1
167. e windows A brief description of each window follows Main window UM 123 The initial window that appears upon startup All subsequent ModelSim windows are opened from the Main window This window contains the session transcript Dataflow window UM 135 Lets you trace signals and nets through your design by showing related processes List window UM 139 Shows the simulation values of selected VHDL signals and variables and Verilog nets and register variables in tabular format Process window UM 152 Displays a list of processes in the region currently selected in the Structure window Signals window UM 155 Shows the names and current values of VHDL signals and Verilog nets and register variables in the region currently selected in the Structure window Source window UM 163 Displays the HDL source code for the design Your source code can remain hidden if you wish see Source code security and nodebug UM 297 Structure window UM 172 Displays the hierarchy of structural elements such as VHDL component instances packages blocks generate statements and Verilog model instances named blocks tasks and functions In versions 5 5 and later this same information is displayed in the Main window workspace Variables window UM 175 Displays VHDL constants generics variables and Verilog register variables in the current process and their current values Wave window UM 178 Displays waveforms and current values f
168. ecify that range checks are performed by using the rangecheck argument to the vcom CR 129 command Or you can use the RangeCheck and NoIndexCheck variables in the modelsim ini to specify whether or not they are performed See Preference variables located in INI files UM 278 ModelSim User s Manual UM 46 4 VHDL Simulation Simulating VHDL designs After compiling the design units you can simulate your designs with vsim CR 168 This section discusses simulation from the Windows DOScommand line You can also use a project to simulate see Getting started with projects UM 18 or the Load Design dialog box see Simulating with the graphic interface UM 217 gt Note Simulation normally stops if a failure occurs however if a bounds check on a signal fails the simulator will continue running Invoking the simulator from the Main window ModelSim User s Manual For VHDL invoke vsim CR 168 with the name of the configuration or entity architecture pair Note that if you specify a configuration you may not specify an architecture This example invokes vsim CR 168 on the entity my_asic and the architecture structure vsim my_asic structure If a design unit name is not specified vsim CR 168 will present the Load Design dialog box from which you can choose a configuration or entity architecture pair See Simulating with the graphic interface UM 217 for more information Selecting the time resolution The s
169. ect s work library Load Design initiate simulation by specifying the top level design unit in the Design tab specify HDL specific simulator settings with the VHDL and Verilog tabs specify the library to search for design units instantiated from Verilog with the Libraries tab specify settings relating to the annotation of design timing with the SDF tab End Simulation end the simulation ModelSim User s Manual UM 128 7 Graphic Interface View menu All open all ModelSim windows Hide Show hide or show the workspace Workspace Layout Style provides five options Default restore the window layout to that used for versions 5 5 and later Classic restore the window layout to that used in versions prior to 5 5 Cascade Cascade all open windows Horizontal Tile all open windows horizontally Vertical Tile all open windows vertically Source open and or view the Source window UM 163 Structure open and or view the Structure window UM 172 Variables open and or view the Variables window UM 175 Signals open and or view the Signals window UM 155 List open and or view the List window UM 139 Process open and or view the Process window UM 152 Wave open and or view the Wave window UM 178 Dataflow open and or view the Dataflow window UM 135 Datasets open the Dataset Browser for selecting the current Dataset a You can specify a Layout Style to become the default for ModelSi
170. ected Signal Lists only the item s selected in the Signals window e Signals in Region Lists all items in the region that is selected in the Structure window e Signals in Design Lists all items in the design ModelSim User s Manual UM 160 7 Graphic Interface Adding items from the Main window command line Another way to add items to the Wave or List window or the WLF file is to enter the one of the following commands at the VSIM prompt choose either the add list CR 32 add wave CR 35 or log CR 81 command add list add wave log lt item_name gt lt item_name gt You can add all the items in the current region with this command add list add wave log Or add all the items in the design with add list add wave log r If the target window Wave or List is closed ModelSim opens it when you when you invoke the command Finding HDL items in the Signals window To find the specified text string within the Signals window choose the Name or Value field to search and the search direction Down or Up Find Find Next Field Direction Close Name Down C Value C Up You can also do a quick find from the keyboard When the Signals window is active each time you type a letter the signal selector highlight will move to the next signal whose name begins with that letter Setting signal breakpoints You can set signal breakpoints a k a when breakpoints see the when command C
171. ed during startip UM 27 Environment variables accessed during startup UM 28 Initialization sequence UM 29 3 Design libraries UM 31 Design library contents UM 32 Design library types UM 32 Working with design libraries UM 33 Managing library contents UM 34 Assigning a logical name to a design lib UM 37 Moving a library UM 39 Specifying the resource libraries UM 40 Predefined libraries UM 40 Alternate IEEE libraries nipoti UM 41 VITAL 2000 library UM 41 Regenerating your design braies UM 41 ModelSim User s Manual UM 4 Table of Contents Importing FPGA libraries 4 VHDL Simulation UM 43 Compiling VHDL designs Invoking the VHDL compiler Dependency checking Range and index checking Simulating VHDL designs Invoking the simulator from the Main window Using the TextIO package Syntax for file declaration Using STD_INPUT and STD OUTPUT aiki Modelim TextIO implementation issues Reading and writing hexadecimal ee Dangling pointers The ENDLINE function The ENDFILE function Using alternative input output files Providing stimulus Obtaining the VITAL specification and source code VITAL packages ModelSim VITAL compliance VITAL compliance checking Compiling and Simulating with accelerated VITAL packages Util package get_resolution init_signal_spyQ to_real to_time 5 Verilog Simulation UM 59 Compilation
172. ed in that window the Process window will in turn update the Variables window UM 175 The Structure window menu bar The following menu commands are available from the Structure window menu bar Some of the commands are also available from a context menu in a Structure tab of the Main window workspace File menu Save As save the structure tree to a text file viewable with the ModelSim notepad CR 89 Environment allow the window contents to change when the active dataset is changed or fix to a specific dataset Close close this copy of the Structure window Edit menu Copy copy the current selection in the Structure window Sort sort the structure tree in either ascending descending or declaration order Expand Selected expand the hierarchy of the selected item Collapse Selected collapse the hierarchy of the selected item ModelSim User s Manual UM 174 7 Graphic Interface Expand All expand the hierarchy of all items that can be expanded Collapse All collapse the hierarchy of all expanded items Find find the specified text string within the structure tree see Finding items in the Structure window UM 174 Window menu Initial Layout restore all windows to the size and placement of the initial full screen layout Cascade cascade all open windows Tile Horizontally tile all open windows horizontally Tile Vertically tile all open windows vertically
173. ed when you started ModelSim and reports any problems Defines the following environment variables use MODEL_TECH_TCL if it exists else ModelSim User s Manual UM 30 2 Projects and system initialization ModelSim User s Manual e set MODEL_TECH_TCL MODEL_TECH tcl e set TCL_LIBRARY MODEL_TECH_TCL tcl8 0 e set TK_LIBRARY MODEL_TECH_TCL Ak8 0 set TIX_LIBRARY MODEL_TECH_TCL tix4 1 e set ITCL_LIBRARY MODEL_TECH_TCL tcl3 0 e set ITK_LIBRARY MODEL_TECH_TCL itk3 0 e set VSIM_LIBRARY MODEL_TECH_TCL vsim 7 Initializes the simulator s Tcl interpreter 8 Checks for a valid license a license is not checked out unless specified by a modelsim ini setting or command line option The next four steps relate to initializing the graphical user interface 9 Sets Tcl variable MTI_LIB_DIR MODEL_TECH_TCL 10 Loads MTI_LIB_DIR pref tcl 11 Loads last working directory project init project history and printer defaults from the registry Windows 12 Finds the modelsim tcl file by evaluating the following conditions e use MODELSIM_TCL if it exists Gf MODELSIM_TCL is a list of files each file is loaded in the order that it appears in the list else e use modelsim tcl else e use HOME modelsim tcl if it exists That completes the initialization sequence Also note the following about the modelsim ini file When you change the working directory within ModelSim the tool reads the library vcom
174. eference a slice or bit of a vector the function will assume that you are referencing the entire vector ModelSim User s Manual System Tasks UM 83 Example module reg top_sigl initial begin Sinit_signal_spy top uut inst1l sigl top_sigl 1 end endmodule In this example the value of top uut inst1 sigi will be mirrored onto top_sigl ModelSim User s Manual UM 84 5 Verilog Simulation Compiler Directives ModelSim Verilog supports all of the compiler directives defined in the IEEE Std 1364 and some additional Verilog XL compiler directives for compatibility Many of the compiler directives such as timescale take effect at the point they are defined in the source code and stay in effect until the directive is redefined or until it is reset to its default by a resetall directive The effect of compiler directives spans source files so the order of source files on the compilation command line could be significant For example if you have a file that defines some common macros for the entire design then you might need to place it first in the list of files to be compiled The resetall directive affects only the following directives by resetting them back to their default settings this information is not provided in the IEEE Std 1364 celldefine default_decay_time define_nettype delay_mode_distributed delay_mode_path delay_mode_unit delay_mode_zero timescale unconnected_drive usel
175. efers to a parameter or local variable of the procedure unless the global command was invoked to declare varName to be global or unless a Tcl variable command was invoked to declare varName to be a namespace variable Command substitution Placing a command in square brackets will cause that command to be evaluated first and its results returned in place of the command An example is set a 25 set b 11 set c 3 echo the result is expr a b c will output the result is 12 This feature allows VHDL variables and signals and Verilog nets and registers to be accessed using examine lt radix gt name The name substitution is no longer supported Everywhere name could be used you now can use examine value lt radix gt name which allows the flexibility of specifying command options The radix specification is optional ModelSim User s Manual UM 260 10 Tcl and macros Command separator A semicolon character works as a separator for multiple commands on the same line It is not required at the end of a line in a command sequence Multiple line commands With Tcl multiple line commands can be used within macros and on the command line The command line prompt will change as in a C shell until the multiple line command is complete In the example below note the way the opening brace is at the end of the if and else lines This is important because otherwise the Tcl scanner won t know t
176. elSim User s Manual if rising_edge do_init for address in 0 to ram address end loop end if end process initialize end architecture style_93 architecture style_87 of memory begin memory process cs variable address begin natural if rising_edge cs then then nwords 1 loop data_in is address sulv_to_natural add_in if mwrite 1 then ram address data_in data_out lt ram address data_out lt ram address else end if end if end process end style_87 architecture bad_style_87 of memory is begin memory process cs variable address begin natural if rising_edge cs then 0 Modeling memory in VHDL UM 303 address sulv_to_natural add_in if mwrite 1 then ram address lt data_in data_out lt data_in else data_out lt ram address end if end if end process end bad_style_87 use std standard all library ieee use ieee std_logic_1164 all package conversions is function sulv_to_natural x std_ulogic_vector return natural function natural_to_sulv n bits natural return std_ulogic_vector end conversions package body conversions is function sulv_to_natural x std_ulogic_vector return natural is variable n natural 0 variable failure boolean false begin assert x high x low 1 lt 31 report Range of sulv_to_natural argument exceeds natural range severity error
177. er READLINE infile L1 Read and allocate buffer L2 Ll Copy pointers WRITELINE outfile L1 Deallocate buffer Good VHDL because L1 and L2 point to different buffers READLINE infile L1 Read and allocate buffer L2 new string Ll all Copy contents WRITELINE outfile L1 Deallocate buffer The ENDLINE function The ENDLINE function described in the IEEE Standard VHDL Language Reference Manual IEEE Std 1076 1987 contains invalid VHDL syntax and cannot be implemented in VHDL This is because access types must be passed as variables but functions only allow constant parameters Based on an ISAC VASG recommendation the ENDLINE function has been removed from the TextIO package The following test may be substituted for this function L NULL OR L LENGTH 0 The ENDFILE function ModelSim User s Manual In the VHDL Language Reference Manuals IEEE Std 1076 1987 and IEEE Std 1076 1993 the ENDFILE function is listed as function ENDFILE L in TEXT return BOOLEAN As you can see this function is commented out of the standard TextIO package This is because the ENDFILE function is implicitly declared so it can be used with files of any type not just files of type TEXT TextlO implementation issues UM 51 Using alternative input output files You can use the TextIO package to read and write to your own files To do this just declare an input or output file o
178. erefore the no_notifier option suppresses X propagation on timing violations no_path_edge This option causes ModelSim to ignore the input edge specified in a path delay The result is that all edges on the input are considered when selecting the output delay Verilog XL always ignores the input edges on path delays no_pulse_msg This option disables the warning message for specify path pulse errors A path pulse error occurs when a pulse propagated through a path delay falls between the pulse rejection limit and pulse error limit set with the pulse_r and pulse_e options A path pulse error results in a warning message and the pulse is propagated as an X The no_pulse_msg option disables the warning message but the X is still propagated Simulation UM 73 no_show_cancelled_e This option filters negative pulses on specify path delays so they don t show on the output This is the default behavior of Vsim You can drive an X for a negative pulse using show_cancelled_e no_tchk_msg This option disables error messages issued by timing check system tasks when timing check violations occur However notifier registers are still toggled and may result in the propagation of X s for timing check violations t nosdfwarn This option disables warning messages during SDF annotation tnotimingchecks This option completely disables all timing check system tasks nowarn lt mnemonic gt This option disables the class of warning messages s
179. erface The Main window menu bar The menu bar at the top of the Main window lets you access many ModelSim commands and features The menus are listed below with brief descriptions of each command s use l ModelSim File Edit Design View Project Run Compare Macro Options Window Help Se File menu New provides three options Folder create a new folder in the current directory Source create a VHDL Verilog or Other source file Project create a new project Open provides three options File open the selected hdl file Project open the selected mpf project file Dataset open the specified WLF file and assign it the specified dataset name Close provides three options Project close the currently open project file Dataset close the specified dataset Delete provides one option Project delete the selected mpf project file Change Directory change to a different working directory Save Transcript save the current contents of the transcript window to the file indicated with a Save Transcript As selection this selection is not initially available because the transcript is written to the transcript file by default see Saving the Main window transcript file UM 125 Save Transcript As save the current contents of the transcript window to a file Clear Transcript clear the Main window transcript display Options all options ar
180. ert bell 0x7 b Backspace 0x8 f Form feed Oxc n Newline Oxa r Carriage return Oxd t Tab 0x9 v Vertical tab Oxb lt newline gt whiteSpace A single space character replaces the backslash newline and all spaces and tabs after the newline This backslash sequence is unique in that it is replaced in a separate pre pass before the command is actually parsed This means that it will be replaced even when it occurs between braces and the resulting space will be treated as a word separator if it isn t in braces or quotes Backslash ModelSim User s Manual UM 258 10 Tcl and macros ooo The digits ooo one two or three of them give the octal value of the character xhh The hexadecimal digits hh give the hexadecimal value of the character Any number of digits may be present Backslash substitution is not performed on words enclosed in braces except for backslash newline as described above 9 Ifa hash character appears at a point where Tcl is expecting the first character of the first word of a command then the hash character and the characters that follow it up through the next newline are treated as a comment and ignored The comment character only has significance when it appears at the beginning of a command 10 Each character is processed exactly once by the Tcl interpreter as part of creating the words of a command For example if variable substitutio
181. ertion notes off 0 IgnoreWarning 0 1 if 1 ignore assertion warnings off 0 IterationLimit positive integer limit on simulation kernel iterations during 5000 one time delta License any single if set controls ModelSim license file search all lt license_option gt search license options include licenses nomgc excludes MGC licenses nomti excludes MTI licenses noqueue do not wait in license queue if no licenses are available plus only use PLUS license vlog only use VLOG license vhdl only use VHDL license viewsim accepts a simulation license rather than being queued for a viewer license see also the vsim command CR 168 lt license_option gt NoIndexCheck 0 1 if set to 1 run time index checks are 0 disabled ModelSim User s Manual UM 282 A ModelSim Variables Variable name Value range Purpose Default NumericStdNoWarnings 0 1 if 1 warnings generated within the off 0 accelerated numeric_std and numeric_bit packages are suppressed PathSeparator any single used for hierarchical path names must not character be the same character as DatasetSeparator RangeCheck 0 1 if set to 1 enables run time range checking 0 Resolution fs ps ns us ms simulator resolution this value must be less ps or sec with than or equal to the UserTimeUnit specified optional prefix of below NOTE if your delays are truncated 1 10 or 100 set the resolution smaller no spa
182. esults in List window UM 139 with the graphic interface UM 217 with VITAL packages UM 53 Simulations saving results UM 103 simulator resolution returning as a real UM 54 when comparing datasets UM 104 simulator time resolution vsim t CR 171 simulator version CR 172 CR 179 simultaneous events in Verilog changing order CR 162 sizetf callback function UM 94 so shared object file loading PLI VPI applications UM 89 software version UM 130 Sorting sorting HDL items in VSIM windows UM 120 Source code source code security UM 297 Source directory setting from source window UM 164 spaces in pathnames CR 9 Specify path delays CR 176 UM 74 Standards supported UM 12 Startup alternate to startup do vsim do CR 169 environment variables access during UM 28 ModelSim User s Manual UM 316 Index files accessed during UM 27 macro in the modelsim ini file UM 282 using a startup file UM 285 Startup ini file variable UM 282 Startup macros UM 285 Status bar Main window UM 133 status command CR 113 std ini file variable UM 278 std_developerskit ini file variable UM 278 std_logic_arith package UM 41 std_logic_signed package UM 41 std_logic_unsigned package UM 41 StdArithNoWarnings ini file variable UM 282 STDOUT environment variable UM 276 step command CR 114 Stimulus applying to signals and nets UM 158 stop command CR 115 Structure window UM 172 synopsys ini file variable UM 278 system calls VCD UM 248 Verilog UM 77 System com
183. even if the same value is written by both processes e A WRITE READ or READ WRITE hazard is flagged even if the write does not modify the variable s value e Glitches on nets caused by non guaranteed event ordering are not detected Verilog XL compatible simulator options See vsim CR 168 for a complete list of simulator options The options described here are equivalent to Verilog XL options Many of these are provided to ease the porting of a design to ModelSim Verilog talt_path_delays Specify path delays operate in inertial mode by default In inertial mode a pending output transition is cancelled when a new output transition is scheduled The result is that an output may have no more than one pending transition at a time and that pulses narrower ModelSim User s Manual UM 72 5 Verilog Simulation ModelSim User s Manual than the delay are filtered The delay is selected based on the transition from the cancelled pending value of the net to the new pending value The alt_path_delays option modifies the inertial mode such that a delay is based on a transition from the current output value rather than the cancelled pending value of the net This option has no effect in transport mode see tpuls lt percent gt and pulse_r lt percent gt 1 lt filename gt By default the simulation log is written to the file transcript The l option allows you to specify an alternate file maxdelays This option selects the ma
184. f 1 turns on VHDL 1993 vlog Verilog compiler control variables off 0 Variable name Value Purpose Default range Hazard 0 1 if 1 turns on Verilog hazard checking order off 0 dependent accessing of global vars ModelSim User s Manual UM 280 A ModelSim Variables Variable name Purpose Default Incremental if 1 turns on incremental compilation of modules off 0 NoDebug if 1 turns off inclusion of debugging info within design units off 0 Quiet if 1 turns off loading messages off 0 Show_Lint if 1 turns on lint style checking off 0 Show_source vsim simulator control variables if 1 shows source line containing error off 0 Variable name Value range Purpose Default AssertFile any valid alternative file for storing assertion transcript filename messages AssertionFormat see purpose sets the message to display after a break on S assertion message formats include R n Time S severity level T R report message Iteration T time of assertion D N n D delta l instance or region pathname if available print character BreakOnAssertion 0 4 defines severity of assertion that causes a 3 simulation break 0 note warning 2 error 3 failure 4 fatal CommandHistory any valid sets the name of a file in which to store the commented filename
185. f type TEXT The VHDL 87 declaration is file myinput TEXT is in pathname dat The VHDL 93 declaration is file myinput TEXT open read_mode iS pathname dat Then include the identifier for this file myinput in this example in the READLINE or WRITELINE procedure call Providing stimulus You can stimulate and test a design by reading vectors from a file using them to drive values onto signals and testing the results A VHDL test bench has been included with the ModelSim install files as an example Check for this file lt install_dir gt modeltech examples stimulus vhd ModelSim User s Manual UM 52 4 VHDL Simulation Obtaining the VITAL specification and source code VITAL ASIC Modeling Specification The IEEE 1076 4 VITAL ASIC Modeling Specification is available from the Institute of Electrical and Electronics Engineers Inc IEEE Customer Service 445 Hoes Lane Piscataway NJ 08855 1331 Tel 800 678 4333 908 562 5420 from outside the U S Fax 908 981 9667 home page http www ieee org VITAL source code The source code for VITAL packages is provided in the lt install_dir gt vhdl_src vital22b vital95 or vital2000 directories VITAL packages VITAL v3 0 accelerated packages are pre compiled into the ieee library in the installation directory gt Note By default ModelSim is optimized for VITAL v3 0 You can however revert to VITAL v2 2b by invoking vsim CR 168 with the
186. f_annotate system task UM 238 for more details Errors and warnings Errors issued by the SDF annotator while loading the design prevent the simulation from continuing whereas warnings do not Use the sdfnoerror option with vsim CR 168 to change SDF errors to warnings so that the simulation can continue Warning messages can be suppressed by using vsim with either the sdfnowarn or nosdfwarn options Another option is to use the SDF tab from the Load Design dialog box shown above Select Disable SDF warnings sdfnowarn or nosdfwarn to disable warnings or select Reduce SDF errors to warnings sdfnoerror to change errors to warnings See Troubleshooting UM 245 for more information on errors and warnings and how to avoid them ModelSim User s Manual UM 236 8 Standard Delay Format SDF Timing Annotation VHDL VITAL SDF VHDL SDF annotation works on VITAL cells only The IEEE 1076 4 VITAL ASIC Modeling Specification describes how cells must be written to support SDF annotation Once again the designer does not need to know the details of this specification because the library provider has already written the VITAL cells and tools that create compatible SDF files However the following summary may help you understand simulator error messages For additional VITAL specification information see Obtaining the VITAL specification and source code UM 52 SDF to VHDL generic matching ModelSim User s Manual
187. fication except within quotes when specifying a string value cific Values Override Instance specific Values G lt Name gt lt Value gt Select to override generics that received explicit values in generic maps The name and value are specified as above The use of this switch is indicated in the Override Instance column of the Generics list The OK button adds the generic to the Generics listing Cancel dismisses the dialog box without changes VITAL e Disable Timing Checks notimingchecks Disables timing checks generated by VITAL models e Use Vital 2 2b SDF Mapping vital2 2b Selects SDF mapping for VITAL 2 2b default is Vital95 e Disable Glitch Generation noglitch Disables VITAL glitch generation TEXTIO files e STD_INPUT std_input lt filename gt Specifies the file to use for the VHDL textio STD_INPUT file Use the Browse button to locate a file within your directories e STD_OUTPUT std_output lt filename gt Specifies the file to use for the VHDL textio STD_OUTPUT file Use the Browse button to locate a file within your directories ModelSim User s Manual UM 222 7 Graphic Interface Verilog settings tab 7 Load Design Ioj x Delay Selection Dela min m Pulse Options Other Options Disable pulse error and r Enable Hazard Checking I waming messages hazards no_pulse_msg Disable Timing Checks i Rejection Limit pulse_r ar Blocks Biers Erro
188. for i in x range loop n n 2 case x i is when 1 H gt n n 1 when 0 L gt null when others gt failure true end case end loop assert not failure report sulv_to_natural cannot convert indefinite std_ulogic_vector severity error if failure then return 0 else return n end if end sulv_to_natural function natural_to_sulv n bits natural return std_ulogic_vector is variable x std_ulogic_vector bits 1 downto 0 others gt 0 variable tempn natural n begin ModelSim User s Manual UM 304 C Tips and Techniques ModelSim User s Manual for iin x reverse_range loop if tempn mod 2 1 then xX i s 1 end if tempn tempn 2 end loop return x end natural_to_sulv end conversions Setting up a List trigger with Expression Builder UM 305 Setting up a List trigger with Expression Builder This example shows you how to set a List window trigger based on a gating expression created with the ModelSim Expression Builder If you want to look at a set of signal values ONLY during the simulation cycles during which an enable signal rises you would need to use the List window Trigger Gating feature The gating feature suppresses all display lines except those for which a specified gating function evaluates to true Select Prop gt Display Props List window to access the Triggers tab Modify Display Properties list
189. g XL uselib compiler directive UM 67 e Search libraries specified with L options in the order they appear on the command line e Search the work library e Search the library explicitly named in the special escaped identifier instance name It is important to recognize that the work library is not necessarily a library named work the work library refers to the library containing the module that instantiates the module or UDP that is currently being searched for This definition is useful if you have hierarchical modules organized into separate libraries and if sub module names overlap among the libraries In this situation you want the modules to search for their sub modules in the work library first This is accomplished by specifying L work first in the list of search libraries For example assume you have a top level module top that instantiates module modA from library libA and module modB from library libB Furthermore modA and modB both instantiate modules named cellA but the definition of cellA compiled into libA is different from that compiled into libB In this case it is insufficient to just specify L libA L libB as the search libraries because instantiations of cellA from modB resolve to the libA version of cellA The appropriate search library options are L work L libA L libB Compilation UM 65 Verilog XL compatible compiler options See vlog CR 162 for a complete list of compi
190. g and viewing in batch mode UM 298 viewing UM 178 WaveRestoreCursors command CR 189 WaveRestoreZoom command CR 189 WaveSignalNameWidth ini file variable UM 282 Welcome dialog turning on off UM 274 when command CR 181 when statement setting signal breakpoints UM 160 time based breakpoints CR 183 where command CR 185 Wildcard characters for pattern matching in simulator commands CR 13 Windows finding HDL item names UM 119 opening from command line CR 138 opening with the GUI UM 128 searching for HDL item values UM 119 Dataflow window tracing signals and nets UM 137 List window UM 139 adding HDL items UM 144 adding signals with a WLF file UM 159 examining simulation results UM 148 formatting HDL items UM 145 locating time markers UM 119 output file CR 190 saving the format of CR 188 saving to a file UM 150 setting display properties UM 142 setting triggers UM 143 UM 305 Main window UM 123 status bar UM 133 text editing UM 133 UM 293 time and delta display UM 133 toolbar UM 131 Process window UM 152 displaying active processes UM 152 specifying next process to be executed UM 152 viewing processing in the region UM 152 saving position and size UM 120 Signals window UM 155 VHDL and Verilog items viewed in UM 155 Source window setting tab stops UM 171 UM 319 text editing UM 133 UM 293 Structure window UM 172 HDL items viewed in UM 172 instance names UM 173 selecting items to view in Signals window UM 155 VHDL and Verilog
191. ge the Variables window ModelSim User s Manual UM 176 7 Graphic Interface The Variables window menu bar The following menu commands are available from the Variables window menu bar File menu Save As save the variables tree to a text file viewable with the ModelSim notepad CR 89 Environment Follow Process Selection update the window based on the selection in the Process window UM 152 Fix to Current Process maintain the current view do not update Close close this copy of the Variables window Edit menu Copy copy the selected items in the Variables window Sort sort the variables tree in either ascending descending or declaration order Select All select all items in the Variables window Unselect All deselect all items in the Variables window Expand Selected expand the hierarchy of the selected item Collapse Selected collapse the hierarchy of the selected item Expand All expand the hierarchy of all items that can be expanded Collapse All collapse the hierarchy of all expanded items Change change the value of the selected HDL item Justify Values justify values to the left or right margins of the window pane Find find the specified text string within the variables tree choose the Name or Value field to search and the search direction Down or Up View menu Wave List Log place the Selected
192. gedge reset posedge clk 0 RECREM negedge reset posedge clk 5 5 recrem negedge reset posedge clk 0 SKEW is matched to skew SDF Verilog SKEW posedge clk1 posedge clk2 5 skew posedge clk1 posedge clk2 0 WIDTH is matched to width SDF Verilog WIDTH posedge clk 5 width posedge clk 0 PERIOD is matched to period SDF Verilog PERIOD posedge clk 5 period posedge clk 0 NOCHANGE is matched to nochange SDF Verilog NOCHANGE negedge write addr 5 5 nochange negedge write addr 0 0 Optional edge specifications Timing check ports and path delay input ports can have optional edge specifications The annotator uses the following rules to match edges e A match occurs if the SDF port does not have an edge e A match occurs if the specify port does not have an edge e A match occurs if the SDF port edge is identical to the specify port edge e A match occurs if explicit edge transitions in the specify port edge overlap with the SDF port edge These rules allow SDF annotation to take place even if there is a difference between the number of edge specific constructs in the SDF file and the Verilog specify block For example the Verilog specify block may contain separate setup timing checks for a falling ModelSim User s Manual UM 242 8 Standard Delay Format SDF Timing Annotation and rising edge on data
193. ging PLI or VPI code The primary purpose of the replay facility is to send the replay file to MTI support for debugging co simulation problems or debugging PLI VPI problems for which it is impractical to send thePLI V PI code We still need you to send the VHDL Verilog part of the design to actually execute a replay but many problems can be resolved with the trace only Invoking a trace To invoke the trace call vsim CR 168 with the trace_foreign option Syntax vsim trace_foreign lt action gt tag lt name gt Verilog PLI VPI UM 101 Arguments lt action gt Specifies one of the following actions Action Result create log only writes a local file called mti_trace_ lt tag gt create replay only writes local files called mti_data_ lt tag gt c mti_init_ lt tag gt c mti_replay_ lt tag gt c and mti_top_ lt tag gt c create both log and replay tag lt name gt Used to give distinct file names for multiple traces Optional Examples vsim trace_foreign 1 mydesign Creates a logfile vsim trace_foreign 3 mydesign Creates both a logfile and a set of replay files vsim trace_foreign 1 tag 2 mydesign Creates a logfile with a tag of 2 The tracing operations will provide tracing during all user foreign code calls includingPLI VPI user tasks and functions calltf checktf sizetf and misctf routines and Verilog VCL callbacks ModelSim User s Manual UM 102
194. gs eliminate the need to remember a conceptual model of the design the compile order is maintained for you in the project remove the necessity to re establish compiler switches and settings at each session these are stored in the project metadata as are mappings to HDL source files allow users to share libraries without copying files to a local directory you can establish references to source files that are stored remotely or locally allow you to change individual parameters across multiple files in previous versions you could only set parameters one file at a time enable what if analysis you can copy a project manipulate the settings and rerun it to observe the new results e reload ini variable settings every time the project is opened in previous versions you had to quit ModelSim and restart the program to read in a new ini file Introduction UM 17 How do projects differ in version 5 5 Projects have improved a great deal from earlier versions Some of the key differences include e A new interface eliminates the need to write custom scripts e You don t have to copy files into a specific directory you can establish references to files in any location e You don t have to specify compiler switches the automatic defaults will work for many designs However if you do want to customize the settings you do it through a dialog box rather than by writing a script e All metadata compiler settings compile orde
195. h Libraries L Specifies the library to search for design units instantiated from Verilog Search Libraries First Lf Same as Search Libraries but these libraries are searched before uselib ModelSim User s Manual UM 224 7 Graphic Interface SDF settings tab Load Design olx Design VHDL Vetlog Libraries SDF r SDF Files Region Fil Add Delete Edit SDF Options Multi Source delay latest T Disable SDF wamings C min T Reduce SDF errors to warnings max Load Exit Cancel The SDF Standard Delay Format tab includes these options SDF Files The Add button opens a dialog box that allows you to specify the SDF files to load for the current simulation files are then added to the Region File list You may also select a file on the listing to Delete or Edit opens the dialog box below ModelSim User s Manual SDF options Simulating with the graphic interface UM 225 Specify an SDF File OF x SDF File my sdf Browse Apply to region counter Delay Selection typ OK Cancel From the Specify an SDF File dialog box you can set the following options SDF file lt region gt lt sdf_filename gt Specifies the SDF file to use for annotation Use the Browse button to locate a file within your directories Apply to region lt region gt lt sdf_filename gt Specifies the design region to use with the selecte
196. h TranscriptFile UM 282 specifying library locations in modelsim ini file UM 278 specifying UNIX editor CR 68 using in pathnames CR 10 variable substitution using Tcl UM 261 Error messages bad magic number UM 104 Errors during compilation locating UM 212 onerror command CR 94 Event order issues between simuators UM 70 event order changing in Verilog CR 162 examine command CR 71 exit command CR 73 Explicit ini file variable UM 279 Expression Builder UM 230 Expression_format CR 16 extended identifiers CR 15 syntax in commands CR 11 F f UM 65 file line breakpoints UM 168 find command CR 74 Finding a cursor in the Wave window UM 201 a marker in the List window UM 149 names and values UM 119 force command CR 76 defaults UM 285 format file Wave window UM 181 format list CR 188 format wave CR 188 G GenerateFormat ini file variable UM 28 1 Generics assigning or overriding values with g and G CR 169 examining generic values CR 71 get_resolution VHDL function UM 54 Graphic interface UM 115 GUI_expression_format CR 16 GUI expression builder UM 230 syntax CR 19 H Hazard ini file variable VLOG UM 279 Hazards event order issues UM 71 HDL item UM 14 help command CR 79 Hierarchy referencing signals in UM 55 viewing signal names without UM 197 history command CR 80 History shortcuts CR 7 UM 293 HOME environment variable UM 275 ieee ini file variable UM 278 IEEE libraries UM 41 IEEE Std 1076
197. h the binary executables reside YOU SHOULD NOT SET THIS VARIABLE MODEL_TECH_TCL used by ModelSim to find Tcl libraries for Tcl Tk 8 0 Tix and vsim may also be used to specify a startup DO file defaults to modeltech tcl may be set to an alternate path MGC_LOCATION_MAP used by ModelSim tools to find source files based on easily reallocated soft paths optional see http www model com resources pref_variables frameset htm UM 299 also see the Tcl variables SourceDir and SourceMap MODELSIM used by all ModelSim tools to find the modelsim ini file consists of a path including the file name optional An alternative use of this variable is to set it to the path of a project file lt Project_Root_Dir gt lt Project_Name gt mpf This allows you to use project settings with command line tools However if you do this the mpf file will replace modelsim ini as the initialization file for all ModelSim tools MODELSIM_TCL used by ModelSim to look for an optional graphical preference file can be a semi colon Windows separated list of file paths MTL TF_LIMIT limits the size of the VSOUT temp file generated by the ModelSim kernel the value of the variable is the size of k bytes TMPDIR below controls the location of this file STDOUT controls the name default 10 0 no limit MTI_USELIB_DIR specifies the directory into which object libraries are compiled when using the compile_usel
198. h ul ERROR myasic sdf Failed to find INSTANCE testbench u2 ERROR myasic sdf Failed to find INSTANCE testbench u3 ERROR myasic sdf Failed to find INSTANCE testbench u4 ERROR myasic sdf Failed to find INSTANCE testbench u5 WARNING myasic sdf This file is probably applied to the wrong instance WARNING myasic sdf Ignoring subsequent missing instances from this file After annotation is done the simulator issues a summary of how many instances were not found and possibly a suggestion for a qualifying instance WARNING myasic sdf Failed to find any of the 358 instances from this file WARNING myasic sdf Try instance testbench dut it contains all instance paths from this file The simulator recommends an instance only if the file was applied to the top level and a qualifying instance is found one level down Also see Resolving errors UM 237 for specific VHDL VITAL SDF troubleshooting ModelSim User s Manual UM 247 9 Value Change Dump VCD Files Chapter contents ModelSim VCD commands and VCD tasks UM 248 Creating a VCD file UM 249 Flow for four state VCD file UM 249 A VCD file from source to output UM 250 VHDL source code UM 250 VCD simulator commands UM 250 VCD output UM 251 This chapter explains Model Technology s Verilog VCD implementation for ModelSim The VCD file format is specified in the IEEE 1364 standard
199. hat there is more coming in the command and will try to execute what it has up to that point which won t be what you intend if exa sig_a 001122 echo Signal value matches do macro_l1 do else echo Signal value fails do macro_2 do_ Evaluation order An important thing to remember when using Tcl is that anything put in curly brackets is not evaluated immediately This is important for if then else procedures loops and so forth Tcl relational expression evaluation ModelSim User s Manual When you are comparing values the following hints may be useful e Tcl stores all values as strings and will convert certain strings to numeric values when appropriate If you want a literal to be treated as a numeric value don t quote it if exa var_1 345 The following will also work if exa var_1 345 e However if a literal cannot be represented as a number you must quote it or Tcl will give you an error For instance if exa var_2 0012 will give an error if exa var_2 001Z will work okay e Don t quote single characters in single quotes if exa var_3 X will give an error i x if exa var_3 will work okay Tcl command syntax UM 261 e For the equal operator you must use the C operator For not equal you must use the C operator Variable substitution When a lt var_name gt is encountered the Tcl parser will lo
200. have the following line in your modelsim ini file TranscriptFile transcript And assume you have the following line in your modelsim tcl file set PrefMain file In this case the setting in the modelsim tcl file will override that in the modelsim ini file and a transcript file will not be produced Simulator state variables Simulator state variables UM 289 Unlike other variables that must be explicitly set simulator state variables return a value relative to the current simulation Simulator state variables can be useful in commands especially when used within ModelSim DO files macros Variable Result argc returns the total number of parameters passed to the current macro architecture returns the name of the top level architecture currently being simulated for a configuration or Verilog module this variable returns an empty string configuration returns the name of the top level configuration currently being simulated returns an empty string if no configuration delta returns the number of the current simulator iteration entity returns the name of the top level VHDL entity or Verilog module currently being simulated library returns the library name for the current region MacroNestingLevel returns the current depth of macro call nesting n represents a macro parameter where n can be an integer in the range 1 9 returns the current simulation time expre
201. he SDF file are relative to the instance to which the SDF is applied Usually this instance is an ASIC or FPGA model instantiated under a testbench For example to annotate maximum timing values from the SDF file myasic sdf to an instance ul under a top level named testbench invoke the simulator as follows vsim sdfmax testbench ul myasic sdf testbench If the instance name is omitted then the SDF file is applied to the top level This is usually incorrect because in most cases the model is instantiated under a testbench or within a larger system level simulation In fact the design can have several models each having its own SDF file In this case specify an SDF file for each instance For example vsim sdfmax system ul asicl sdf sdfmax system u2 asic2 sdf system Specifying SDF files for simulation UM 235 SDF specification with the GUI As an alternative to the command line options you can specify SDF files in the Load Design dialog box under the SDF tab Load Design OL x Design VHDL Vetiog Libraries SDF SDF Files Region Fie SDF Options Multi Source delay latest I Disable SDF wamings C min I Reduce SDF errors to warnings C max Cancel You can access this dialog by invoking the simulator without any arguments or by selecting Design gt Load Design Main window For Verilog designs you can also specify SDF files by using the sdf_annotate system task See The sd
202. he VHDL 93 syntax for a file declaration is file identifier_list subtype_indication file_open_information You can specify a full or relative path as the file_logical_name for example VHDL 87 Normally if a file is declared within an architecture process or package the file is opened when you start the simulator and is closed when you exit from it If a file is declared in a subprogram the file is opened when the subprogram is called and closed when execution RETURNs from the subprogram Alternatively the opening of files can be delayed until the first read or write by setting the DelayFileOpen variable in the modelsim ini file Also the number of concurrently open files can be controlled by the ConcurrentFileLimit variable These variables help you manage a large number of files during simulation See Appendix A ModelSim Variables for more details ModelSim User s Manual UM 48 4 VHDL Simulation Using STD_INPUT and STD_OUTPUT within ModelSim The standard VHDL 87 TextIO package contains the following file declarations file input TEXT is in STD_INPUT file output TEXT is out STD_OUTPUT The standard VHDL 93 TextIO package contains these file declarations file input TEXT open read_mode is STD_INPUT file output TEXT open write_mode is STD_OUTPUT STD_INPUT is a file_logical_name that refers to characters that are entered interactively from the keyboard and STD_OUTPUT refers to text that is displa
203. he graphic below shows three Structure tabs one for the active simulation Sim and one each for two open datasets Test and Gold l ModelSim File Edit Design View Project Run Compare Macro Options Window Help Sg BR Hl myHeiea ae x top topfonly p proc c cache D m memory E Package std_logic_util W Package vl_types Package std_logic_1164 W Package standard El Project test gold top Ai If you have too many tabs to display in the available space you can scroll the tabs left or right by clicking and dragging them Each Structure tab has a context menu that you access by clicking the right mouse button ModelSim User s Manual WLF files datasets UM 107 ModelSim File Edit Design View Project Run Compare Macro Options Window Help eo SE FL myhia oP I livsiM 13 gt Save As D m memory Sot Ascending Package std_logic_util Expand Selected Descending E Package vl_types Collapse Selected Declaration Order E Package std_logic_1164 Expand All I Package standard Collapse All Find vv Project test gold top i The Structure tab context menu includes the following options Save As Writes the HDL item names in the Structure tab to a text file Sort Sorts the HDL items in the Structure tab by alphabetic ascending or descending or declaration order Expand Selected Shows the hierarchy of the selected HDL item Collapse Selected Hides the hierarch
204. he list display Saving List window data to a file Select File gt Write List format List window to save the List window data in one of these formats e tabular writes a text file that looks like the window listing ns delta a b cin sum cout 0 0 X X U X U 0 1 0 1 0 X U 2 0 0 1 0 X U e event writes a text file containing transitions during simulation eO 0 a X b X cin U sum X cout U O 1 a 0 b 1 fein 0 ModelSim User s Manual List window UM 151 TSSI writes a file in standard TSSI format see also the write tssi command CR 194 00000000000000010000000010 0 2 3 00000000000000010 010 4 100 00000001000000010000000010 You can also save List window output using the write list command CR 190 ModelSim User s Manual UM 152 7 Graphic Interface Process window The Process window displays a list of processes If View gt Active is selected then all processes scheduled to run during the current simulation cycle are displayed along with the pathname of the instance in which each process is located If View gt In Region is selected then only the processes in the currently selected region are displayed Each HDL item in the scrollbox is preceded by one of the following indicators lt Ready gt Indicates that the process is scheduled to be executed within the current delta time lt Wait gt Indicates that the process is waiting for a VHDL signal or
205. he zoom range Top Index The item that will display at the top of the wave window For instance if you specify 15 the Wave window will be scrolled down to show the 15th item in the window Save zoom range with bookmark When checked the zoom range will be saved in the bookmark Save scroll location with bookmark When checked the scroll location will be saved in the bookmark Once the bookmark is saved select it by name from the Bookmark menu and the Wave window will be zoomed and scrolled accordingly ModelSim User s Manual UM 204 7 Graphic Interface To edit or delete a bookmark select Bookmark gt Edit Bookmarks Wave window Bookmark Selection wayve OFX example Add Modify Delete Delete All Goto Bookmark Configuration Name example Zoom Range 0 ns 625 us Top Index 0 The Bookmark Selection dialog includes the following options Add bookmark add wave Add a new bookmark Modify Edit the selected bookmark Delete bookmark delete wave Delete the selected bookmark Delete All bookmark delete wave Delete all bookmarks Goto bookmark goto wave Zoom and scroll the Wave window using the selected bookmark ModelSim User s Manual Wave window mouse and keyboard shortcuts Wave window UM 205 The following mouse actions and keystrokes can be used in the Wave window Mouse action Result lt control left button click on a scroll arro
206. hen the compiler will search for a file with the suffix appended to an unresolved name You may specify only one libext option but it may contain multiple suffixes separated by The extensions are tried in the order they appear in the libext option t librescan This option changes how unresolved references are handled that are added while compiling a module or UDP from a source library By default the compiler attempts to resolve these references as it continues searching the source libraries If you specify the librescan option then the new unresolved references are deferred until after the current pass through the source libraries They are then resolved by searching the source libraries from the beginning in the order they are specified on the command line Compilation UM 67 tnolibcell By default all modules compiled from a source library are treated as though they contain a celldefine compiler directive This option disables this default The celldefine directive only affects the PLI Access routines acc_next_cell and acc_next_cell_load R lt simargs gt This option instructs the compiler to invoke the simulator after compiling the design The compiler automatically determines which top level modules are to be simulated The command line arguments following R are passed to the simulator not the compiler Place the R option at the end of the command line or terminate the simulator command line arguments with a single ch
207. iables UM 279 vsim simulator control variables UM 280 Library library path variables Variable name Value range Purpose ieee any valid path may include sets the path to the library containing IEEE and environment variables Synopsys arithmetic packages the default is modeltech iece std any valid path may include sets the path to the VHDL STD library the default environment variables is modeltech std std_developerskit any valid path may include sets the path to the libraries for MGC standard environment variables developer s kit the default is modeltech std_developerskit synopsys any valid path may include sets the path to the accelerated arithmetic environment variables packages the default is modeltech synopsys verilog any valid path may include sets the path to the library containing VHDL environment variables Verilog type mappings the default is modeltech verilog vcom VHDL compiler control variables Variable name Purpose Default CheckSynthesis if 1 turns on limited synthesis rule compliance off 0 checking checks only signals used read by a process ModelSim User s Manual Variable name Preference variables located in INI files Purpose UM 279 Default Explicit if 1 turns on resolving of ambiguous function overloading in favor of the explicit function declaration not the one automatically created by
208. ib ModelSim Verilog implicitly defines the following macro define MODEL_TECH IEEE Std 1364 compiler directives ModelSim User s Manual The following compiler directives are described in detail in the IEEE Std 1364 celldefine default_nettype define else endcelldefine endif ifdef ifndef include line nounconnected_drive resetall timescale unconnected_drive undef Compiler Directives UM 85 Verilog XL compatible compiler directives The following compiler directives are provided for compatibility with Verilog XL default_decay_time lt time gt This directive specifies the default decay time to be used in trireg net declarations that do not explicitly declare a decay time The decay time can be expressed as a real or integer number or as infinite to specify that the charge never decays delay_mode_distributed This directive disables path delays in favor of distributed delays See Delay modes UM 75 for details delay_mode_path This directive sets distributed delays to zero in favor of path delays See Delay modes UM 75 for details delay_mode_unit This directive sets path delays to zero and non zero distributed delays to one time unit See Delay modes UM 75 for details delay_mode_zero This directive sets path delays and distributed delays to zero See Delay modes UM 75 for details uselib This directive is an alternative to the v y and libext source lib
209. ibs argument to the vlog command CR 162 ModelSim User s Manual UM 276 A ModelSim Variables Variable Description PLIOBJS used by ModelSim to search for PLI object files for loading consists of a space separated list of file or path names optional STDOUT the VSOUT temp file generated by the simulator kernel is deleted when the simulator exits the file is not deleted if you specify a filename for VSOUT with STDOUT specifying a name and location use TMPDIR for the VSOUT file will also help you locate and delete the file in event of a crash an unnamed VSOUT file is not deleted after a crash either TMP specifies the path to a tempnam generated file VSOUT containing all stdout from the simulation kernel optional Creating environment variables in Windows In addition to the predefined variables shown above you can define your own environment variables This example shows a user defined library path variable that can be referenced by the vmap command to add library mapping to the modelsim ini file Using Windows 95 98 Me Open and edit the autoexec bat file by adding this line set MY_PATH temp work Restart Windows to initialize the new variable Using Windows NT 2000 Right click the My Computer icon and select Properties then select the Environment tab in Windows 2000 select the Advanced tab and then Environment Variables Add the new variable with this data Variable MY_PATH and Value temp
210. ic_lib work my_work others install_dir modeltech modelsim ini Tip Since the file referred to by the others clause may itself contain an others clause you can use this feature to chain a set of hierarchical INI files for library mappings Creating a transcript file A feature in the system initialization file allows you to keep a record of everything that occurs in the transcript error messages assertions commands command outputs etc To do this set the value for the TranscriptFile line in the modelsim ini file to the name of the file in which you would like to record the ModelSim history Save the command window contents to this file TranscriptFile trnscrpt ModelSim User s Manual Preference variables located in INI files UM 285 Using a startup file The system initialization file allows you to specify a command or a do file that is to be executed after the design is loaded For example VSIM Startup command Startup do mystartup do The line shown above instructs ModelSim to execute the commands in the macro file named mystartup do VSIM Startup command Startup run all The line shown above instructs VSIM to run until there are no events scheduled See the do command CR 64 for additional information on creating do files Turning off assertion messages You can turn off assertion messages from your VHDL code by setting a switch in the modelsim ini file This option was added because some uti
211. ield This creates a library sub directory in your current working directory initially mapped to itself Once created the mapped library is easily remapped to a different library Create a map to an existing library Type the new library name into the Library Name field then type into the Library Maps to field or Browse to select a library name for the mapping Library Name Type the new library name into this field ModelSim User s Manual UM 34 3 Design libraries e Library Maps to Type or Browse for a mapping for the specified library This field can be changed only when the Create a map to an existing library option is selected When you click OK ModelSim creates the specified library directory and writes a specially formatted file named _info into that directory The _info file must remain in the directory to distinguish it as a ModelSim library The new map entry is written to the modelsim ini file in the Library section See Library library path variables UM 278 for more information gt Note Remember that a design library is a special kind of directory the only way to create a library is to use the ModelSim GUI or the vlib command CR 161 Do not create libraries using DOS or Windows commands Managing library contents Library contents can be viewed deleted recompiled edited and so on using either the graphic interface or command line The Library tab in the Main window workspace provides access to desig
212. ild Compile to library work m File Properties Multiple files selected Ok Cancel The General tab includes these options Exclude File from Build Determines whether the file is excluded from the compile e Compile to library Specifies to which library you want to compile the file defaults to the working library ModelSim User s Manual UM 26 2 Projects and system initialization File Properties A variety of information about the selected file e g type size path Displays only if a single file is selected in the Project tab The definitions of the options on the VHDL and Verilog tabs can be found in the section Setting default compile options UM 213 When setting options on a group of files keep in mind the following e If two or more files have different settings for the same option the checkbox in the dialog will be grayed out If you change the option you cannot change it back to a multi state setting without cancelling out of the dialog Once you click OK ModelSim will set the option the same for all selected files e If you select a combination of VHDL and Verilog files the options you set on the VHDL and Verilog tabs apply only to those file types Accessing projects from the command line ModelSim User s Manual Generally projects are used only within the ModelSim graphical user interface However standalone tools will use the project file if they are in
213. ile and the remaining tasks require a filename argument to associate their actions with a specific file VCD commands VCD system tasks ved add CR 119 file lt filename gt fdumpvars ved checkpoint CR 120 lt filename gt fdumpall vcd files CR 123 lt filename gt a fdumpfile ved flush CR 124 lt ilename gt fdumpflush ved limit CR 125 lt filename gt fdumplimit ved off CR 126 lt filename gt fdumpoff ved on CR 127 lt filename gt fdumpon A Important Note that two commands ved file and ved files are available to specify a filename and state mapping for a VCD file Ved file allows for only one VCD file and exists for backwards compatibility with ModelSim versions prior to 5 5 Ved files allows for creation of multiple VCD files and is the preferred command to use in ModelSim versions 5 5 and later Creating a VCD file UM 249 Creating a VCD file ModelSim produces a four state VCD file with variable changes in 0 1 x and z with no strength information The output will also contain port driver changes unless filtered out with optional command line arguments The commands shown below are documented in detail in the ModelSim Command Reference Flow for four state VCD file First compile and load the design cd modeltech examples vlib work vlog counter v tcounter v vsim test_counter Next with the design loaded specify the
214. ile menu Save As save the process tree to a text file viewable with the ModelSim notepad CR 89 Environment Follow Context Selection update the window based on the selection in the Structure window UM 172 Fix to Current Context maintain the current view do not update Close close this copy of the Process window Edit menu Copy copy the selected process full name Sort sort the process list in either ascending descending or declaration order Select All select all processes in the Process window Unselect All deselect all processes in the Process window Find find the specified text string within the process list choose the Status ready wait or done the Process label or the path to search and the search direction down or up View menu Active display all the processes that are scheduled to run during the current simulation cycle In Region display any processes that exist in the region that is selected in the Structure window ModelSim User s Manual UM 154 7 Graphic Interface ModelSim User s Manual Window menu Initial Layout restore all windows to the size and placement of the initial full screen layout Cascade cascade all open windows Tile Horizontally tile all open windows horizontally Tile Vertically tile all open windows vertically Icon Children icon all but the Main windo
215. im to the same path as MODEL_TECH_TCL must point to libraries supplied by Model Technology TIX_LIBRARY identifies the path to the Tix library set by ModelSim to the same path as MODEL_TECH_TCL must point to libraries supplied by Model Technology ITCL_LIBRARY identifies the path to the incr Tcl library set by ModelSim to the same path as MODEL_TECH_TCL must point to libraries supplied by Model Technology ITK_LIBRARY identifies the path to the incr Tk library set by ModelSim to the same path as MODEL_TECH_TCL must point to libraries supplied by Model Technology VSIM_LIBRARY identifies the path to the Tcl files that are used by ModelSim set by ModelSim to the same path as MODEL_TECH_TCL must point to libraries supplied by Model Technology MTILIB_DIR identifies the path to all Tcl libraries installed with ModelSim MODELSIM_TCL ModelSim User s Manual identifies the path to the modelsim tcl file this environment variable can be a list of file pathnames separated by semicolons Windows System initialization UM 29 Initialization sequence The following list describes in detail ModelSim s initialization sequence The sequence includes a number of conditional structures the results of which are determined by the existence of certain files and the current settings of environment variables In the steps below names in uppercase denote environment variables except MTI_LIB_DIR which
216. imulation time resolution is 1 ps by default You can select a specific time resolution with the vsim CR 168 t option or from the Load Design dialog box Available resolutions are 1x 10x or 100x of fs ps ns us ms or sec For example to run in femtosecond resolution or 10fs resolution respectively vsim t fs topmod vsim t 10fs topmod Note that there is no space between the value and the units i e 10fs not 10 fs The default time resolution can also be changed by modifying the Resolution UM 282 variable in the modelsim ini file See Preference variables located in INI files UM 278 for more information on modifying the modelsim ini file You can view the current resolution by invoking the report command CR 102 with the simulator state option Using the TextlO package UM 47 Using the TextlO package To access the routines in TextIO include the following statement in your VHDL source code USE std textio all A simple example using the package TextIO is USE std textio all ENTITY simple_textio IS END ARCHITECTURE simple_behavior OF simple_textio IS BEGIN PROCESS VARIABLE i INTEGER 42 VARIABLE LLL LINE BEGIN WRITE LLL i WRITELINE OUTPUT LLL WAIT END PROCESS END simple_behavior Syntax for file declaration The VHDL 87 syntax for a file declaration is file identifier subtype_indication iS mode file_logical_name where file_logical_name must be a string expression T
217. indow will display the current process when you single step or when ModelSim hits a breakpoint ModelSim User s Manual UM 138 7 Graphic Interface Saving the Dataflow window as a Postscript file Select File gt Save Postscript Dataflow window to save the current Dataflow view as a Postscript file Configure the Postscript output with the following dialog box or use the Options gt Edit Preferences Main window command The dialog box has the following options Dataflow Save Postscript e Postscript File Write CY aaa specify the name of the file to save default is Postscript File dataflow ps Browse dataflow ps e Orientation Taian Minne Color Mode PEFS specify Landscape poao Color gesc horizontal or Portrait Landscape Normal vertical orientation Portrait EPS Color Mode specify Color 256 colors Gray gray scale white 0 00 00 0setrgbcolo or Monortriorocktonic Color Map hite 0 0 0 0 0 0 setrgbcolor color mode Postscript specify Normal Postscript or EPS Encapsulated Postscript file type Color Map specify the color mapping from current Dataflow window colors to Postscript colors ModelSim User s Manual List window UM 139 List window The List window displays the results of your simulation run in tabular format The window is divided into two adjustable panes which allow you to scroll horizontally through the listing on the right while keeping time an
218. ine by line ModelSim User s Manual Run gt Step Over step over see step CR 114 Main window UM 133 The Main window status bar Now 1 100 ns Delta 1 Env top m Fields at the bottom of the Main window provide the following information about the current simulation Field Description Now the current simulation time using the default resolution units see Simulating with the graphic interface UM 217 or a larger time unit if one can be used without a fractional remainder Delta the current simulation iteration number lt dataset name gt name of the current dataset item selected in the Structure window UM 172 Mouse and keyboard shortcuts The following mouse actions and special keystrokes can be used to edit commands in the entry region of the Main window They can also be used in editing the file displayed in the Source window and all Notepad windows enter the notepad command within ModelSim to open the Notepad editor Keystrokes Result lt left right arrow gt move the cursor left right one character lt up down arrow gt scroll through command history in Source window move cursor one line up down lt control gt lt left right arrow gt move cursor left right one word lt shift gt lt left right up down arrow gt extend selection of text lt control gt lt shift gt lt left right arrow gt exte
219. ironment variables may also be referenced from the ModelSim command line or in macros using the Tcl env array mechanism echo Senv ENV_VAR_NAME Removing temp files VSOUT The VSOUT temp file is the communication mechanism between the simulator kernel and the ModelSim GUL In normal circumstances the file is deleted when the simulator exits If ModelSim crashes however the temp file must be deleted manually Specifying the location of the temp file with TMPDIR above will help you locate and remove the file gt Note There is one environment variable MODEL_TECH that you cannot and should not set MODEL_TECH is a special variable set by Model Technology software Its value is the name of the directory from which the vcom compiler or vsim simulator was invoked MODEL_TECH is used by the other Model Technology tools to find the libraries ModelSim User s Manual UM 278 A ModelSim Variables Preference variables located in INI files ModelSim initialization IND files contain control variables that specify reference library paths and compiler and simulator settings See System initialization UM 27 for more details on how these variables are loaded The following tables list the variables by section and in order of their appearance within the INI file INI file sections Library library path variables UM 278 vcom VHDL compiler control variables UM 278 vlog Verilog compiler control var
220. is interrupted abort CR 31 terminate a macro once the macro has been interrupted or paused pause CR 95 cause the macro to be interrupted the macro can be resumed by entering a resume command CR 106 via the command line gt Note You can also set the OnErrorDefaultAction Tcl variable see Preference variables located in Tcl files UM 287 in the pref tcl file to dictate what action ModelSim takes when an error occurs Error action in DO files If a command in a macro returns an error ModelSim does the following 1 If an onerror CR 94 command has been set in the macro script ModelSim executes that command 2 If no onerror command has been specified in the script ModelSim checks the OnErrorDefaultAction Tcl variable If the variable is defined it will be invoked 3 If neither 1 or 2 is true the macro aborts ModelSim User s Manual Macros DO files UM 271 Using the Tcl source command with DO files See also Either the do command or Tcl source command can execute a DO file but they behave differently With the source command the DO file is executed exactly as if the commands in it were typed in by hand at the prompt Each time a breakpoint is hit the Source window is updated to show the breakpoint This behavior could be inconvenient with a large DO file containing many breakpoints When a do command is interrupted by an error or breakpoint it does not update any windows and keeps the DO file
221. ist Process Signals Source Structure or Variables window Select the items in the first window then drop them into the Wave window Depending on what you select all items or any portion of the design can be added Adding items from the Main window command line To add specific HDL items to the window enter separate the item names with a space add wave lt item_name gt lt item_name gt You can add all the items in the current region with this command add wave Or add all the items in the design with add wave r Adding items with a Wave window format file To use a Wave window format file you must first save a format file for the design you are simulating Follow these steps 1 Add the items you want in the Wave window with any method shown above 2 Edit and format the items see Editing and formatting HDL items in the Wave window UM 192 to create the view you want 3 Save the format to a file by selecting File gt Save Format Wave window To use the format file start with a blank Wave window and run the DO file in one of two ways e Invoke the do command CR 64 from the command line do lt my_wave_format gt e Select File gt Load Format Wave window ModelSim User s Manual UM 182 7 Graphic Interface Use Edit gt Select All and Edit gt Delete to remove the items from the current Wave window use the delete command CR 61 with the wave option or create a new blank Wave windo
222. it shouldn t save its data with calls to tf_write_save until it is called with reason_save reason_save For the execution of the checkpoint command This is when the PLI application must save its state with calls to tf_write_save reason_startofrestart For the start of execution of the restore command but before any of the simulation state has been restored This allows the PLI application to prepare for the restore but it shouldn t restore its state with calls to tf_read_restart until it is called with reason_restart The reason_startofrestart value is passed only for a restore command and not in the case that the simulator is invoked with restore reason_restart For the execution of the restore command This is when the PLI application must restore its state with calls to tf_read_restart reason_reset For the execution of the restart command This is when the PLI application should free its memory and reset its state We recommend that all PLI applications reset their internal state during a restart as the shared library containing the PLI code might not be reloaded See the keeploaded CR 170 and keeploadedrestart CR 170 vsim arguments for related information reason_endofreset For the completion of the restart command after the simulation state has been reset but before the design has been reloaded reason_interactive For the execution of the stop system task or any other time the simulation is interrupted and waiti
223. items in the name pane sort with full path name or viewed name use ascending or descending order Find find the specified item label within the pathname pane or the specified value within the value pane Justify Values justify values to the left or right margins of the window pane Display Properties set display properties for signal path length cursor snap distance row margin and dataset prefixes Signal Properties set label height color radix and format for the selected item use the Format menu selections below to quickly change individual properties ModelSim User s Manual UM 184 7 Graphic Interface Cursor menu Add Cursor add a cursor to the center of the waveform window Delete Cursor delete the selected cursor from the window Goto Zoom menu choose a cursor to go to from a list of current cursors Zoom lt selection gt Bookmark menu selection Full In Out Last Area with mouse button 1 or Range to change the waveform display range Add Bookmark add a new bookmark that saves a specific zoom and scroll range Edit Bookmarks edit an existing bookmark lt bookmark_name gt Format menu list of currently defined bookmarks Radix set the selected item s radix Format set the waveform format for the selected item Literal Logic Event Analog Color set the color for the selected item from a color palette
224. items viewed in UM 172 viewing design hierarchy UM 172 Variables window UM 175 displaying values UM 175 VHDL and Verilog items viewed in UM 175 Wave window UM 178 adding HDL items UM 181 adding signals with a WLF file UM 159 changing display range zoom UM 201 changing path elements CR 53 UM 282 cursor measurements UM 201 locating time cursors UM 119 saving format file UM 181 setting display properties UM 197 using time cursors UM 200 zoom options UM 202 zooming UM 201 WLF files adding items to UM 159 creating from VCD CR 128 limiting size CR 172 log command CR 81 overview UM 104 saving UM 104 specifying name CR 172 using in batch mode UM 298 wlf2log command CR 186 Work library UM 32 workspace UM 124 write format command CR 188 write list command CR 190 write preferences command CR 191 write report command CR 192 write transcript command CR 193 write tssi command CR 194 write wave command CR 196 X X propagation preventing CR 171 ModelSim User s Manual UM 320 Index Y y CR 164 UM 66 Z Zero delay loop detecting infinite UM 299 Zero delay oscillation UM 299 Zoom from Wave toolbar buttons UM 202 from Zoom menu UM 201 options UM 202 saving range with bookmarks UM 203 with the mouse UM 202 ModelSim User s Manual
225. k event Main menu Run gt Run All see run CR 107 also see Assertion settings tab UM 227 Break stop the current simulation run ModelSim User s Manual Using Dividers waye default Wave window UM 189 Dividing lines can be placed in the pathname and values window panes by selecting File gt New Divider Wave window Dividers serve as a visual aid to signal debugging allowing you to separate signals and waveforms for easier viewing Dividing lines can be assigned any name or no name at all The default name is New Divider In the illustration below two datasets have been separated with a Divider called Gold Notice that the waveforms in the waveform window pane have been separated by the divider as well File Edit Cursor Zoom Compare Bookmark Format Window oH tre RK FX QQQQH HH El le si 2 x fF F sim top pdata oooo000000000001 sim top srw sim top sstrb sim top srdy 0 1 sim top saddr 00000001 AAAA sinc tup sdata Doooosccanno000 magl ftom folle yuviw r gold top prw gold top pstrb 1 1 D PAE JE 2619 ns to 2831 ns 2820 ns 340 ns A After you have added a divider you can move it change its properties name and size or delete it To move a divider Click and drag the divider to the location you want To change a divider s name and size Click the divider with the right
226. k the installation README file to see if your libraries require an update You can regenerate your design libraries using the Refresh command from the Library tab context menu see Managing library contents UM 34 or by using the refresh argument to vcom CR 129 and vlog CR 162 From the command line you would use vcom with the refresh option to update VHDL design units in a library and vlog with the refresh option to update Verilog design units By default the work library is updated use work lt library gt to update a different library For example if you have a library named mylib that contains both VHDL and Verilog design units vcom work mylib refresh vlog work mylib refresh An important feature of refresh is that it rebuilds the library image without using source code This means that models delivered as compiled libraries without source code can be rebuilt for a specific release of ModelSim 4 6 and later only In general this works for moving forwards or backwards on a release Moving backwards on a release may not work if the models used compiler switches or directives Verilog only that do not exist in the older release gt Note You don t need to regenerate the std ieee vital22b and verilog libraries Also you cannot use the refresh option to update libraries that were built before the 4 6 release ModelSim User s Manual UM 42 3 Design libraries Importing FPGA libraries ModelSim User s Manu
227. late a design 1 To simulate one of the designs either double click the name or right click the name and select Load A new tab appears showing the structure of the current active simulation l ModelSim Torx File Edit Design View Project Run Compare Macro Options Window Help SR EFT AEREE oe E oo ples counter v Saas Model Technology ModelSim SE EE vlog 5 i E 5 Beta 4 Compiler 2001 01 Jan 18 2001 Compiling module counter Top level modules counter vsim work counter vsim work counter Function increment Loading work counter Faea iay i vsM Project test Now 0 ns Delta 0 sim counter Ahi At this point you are ready to run the simulation and analyze your results You often do this by adding signals to the Wave window and running the simulation for a given period of time See the ModelSim Tutorial for examples Other project operations In addition to the four actions just discussed the following are common project operations Open an existing project When you leave a ModelSim session ModelSim will remember the last opened project You can reopen it for your next session by clicking Open Project in the Welcome to ModelSim dialog You can also open an existing project by selecting File gt Open gt Project Main window Close a project Select File gt Close gt Project Main window This closes the Project tab but leaves the Library and Structure labeled Sim i
228. le Edit Design View Project Aun Compare Macro Options Window Help _ Compile x Reading E modelsim55_se win32 tcl vsim pi Libraiy wor al ModelSim gt wm title ModelSim SE EE The Compile HDL Source Files dialog box opens as shown below Compile HDL Source Files 21x Library work Look in a mixedHDL x c EEE a util vhd a proc Files of type HDL Files vhdl vhd v x Done Default Options Edit Source From the Compile HDL Source Files dialog box you can select source files to compile in any language combination e specify the target library for the compiled design units e select among the compiler options for either VHDL or Verilog ModelSim User s Manual UM 212 7 Graphic Interface Select the Default Options button to change the compiler options see Setting default compile options UM 213 for details The same Compiler Options dialog box can also be accessed by selecting Options gt Compile Main window or by selecting Compile Properties from the context menu in Project tab Select the Edit Source button to view or edit a source file via the Compile dialog box See Source window UM 163 for additional source file editing information Locating source errors during compilation If a compiler error occurs during compilation a red error message is printed in the Main transcript Double click on the error message to open the source file in an editable Source
229. lements 0 for Full Path Max Title Rows 5 Dataset Prefix C Show All Dataset Prefixes Show All Except sim C Show No Dataset Prefixes OK Cancel Apply The Window Properties tab includes these options Signal Names Sets the number of path elements to be shown in the List window For example 0 shows the full path 1 shows only the leaf element e Max Title Rows Sets the maximum number of rows in the name pane Dataset Prefix Show All Dataset Prefixes Displays the dataset prefix associated with each signal pathname Useful for displaying signals from multiple datasets Dataset Prefix Show All Except sim Displays all dataset prefixes except the one associated with the current simulation sim Useful for displaying signals from multiple datasets ModelSim User s Manual List window UM 143 e Dataset Prefix Show No Dataset Prefixes Turns off display of dataset prefixes Trigger settings tab The Triggers tab controls the triggering for the display of new lines in the List window You can specify whether an HDL item trigger or a strobe trigger is used to determine when the List window displays a new line If you choose Trigger on Signals then you can choose between collapsed or expanded delta displays You can also choose a combination of signal or strobe triggers To use gating Signals or Strobe or both must be selected E Modify Display Properties list a
230. ler options The options described here are equivalent to Verilog XL options Many of these are provided to ease the porting of a design to ModelSim Verilog t define lt macro_name gt lt macro_text gt This option allows you to define a macro from the command line that is equivalent to the following compiler directive define lt macro_name gt lt macro_text gt Multiple define options are allowed on the command line A command line macro overrides a macro of the same name defined with the define compiler directive t tincdirt lt directory gt This option specifies which directories to search for files included with include compiler directives By default the current directory is searched first and then the directories specified by the incdir options in the order they appear on the command line You may specify multiple incdir options as well as multiple directories separated by in a single incdir option delay_mode_distributed This option disables path delays in favor of distributed delays See Delay modes UM 75 for details delay_mode_path This option sets distributed delays to zero in favor of path delays See Delay modes UM 75 for details t delay_mode_unit This option sets path delays to zero and non zero distributed delays to one time unit See Delay modes UM 75 for details delay_mode_zero This option sets path delays and distributed delays to zero See Delay modes UM 75 for details f
231. lib lt library_name gt all Library mapping from the command line You can issue a command to set the mapping between a logical library name and a directory its form is vmap lt logical_name gt lt directory_pathname gt This command may be invoked from either a DOS prompt or from the command line within ModelSim When you use vmap CR 167 this way you are modifying the modelsim ini file You can also modify modelsim ini manually by adding a mapping line To do this edit the modelsim ini file using any text editor and add a line under the Library section heading using the syntax lt logical_name gt lt directory_pathname gt More than one logical name can be mapped to a single directory For example suppose the modelsim ini file in the current working directory contains following lines Library work usr rick design my_asic usr rick design This would allow you to use either the logical name work or my_asic in a library or use clause to refer to the same design library The vmap command CR 167 can also be used to display the mapping of a logical library name to a directory To do this enter the shortened form of the command vmap lt logical_name gt Library search rules The system searches for the mapping of a logical name in the following order e First the system looks for a modelsim ini file e If the system doesn t find a modelsim ini file or if the specified logical name does not exist in the
232. libraries UM 32 setting up for groups UM 298 std UM 40 verilog UM 64 VHDL library clause UM 40 working libraries UM 32 working with contents of UM 34 library simulator state variable UM 289 Licensing ModelSim User s Manual Index License variable in ini file UM 281 List window UM 139 adding items to CR 32 LM_LICENSE_FILE environment variable UM 275 Locating source errors during compilation UM 212 log command CR 81 Log file log command CR 81 nolog command CR 87 overview UM 103 QuickSim II format CR 186 redirecting with 1 CR 170 virtual log command CR 148 virtual nolog command CR 151 Ishift command CR 83 Isublist command CR 84 M MacroNestingLevel simulator state variable UM 289 Macros DO files creating from a saved transcript UM 125 depth of nesting simulator state variable UM 289 DO files macros UM 269 error handling UM 270 executing CR 64 executing at breakpoints CR 47 forcing signals nets or registers CR 76 parameter as a simulator state variable n UM 289 parameter total as a simulator state variable UM 289 passing parameters to CR 64 UM 269 relative directories CR 64 shifting parameter values CR 111 startup macros UM 285 Main window UM 123 Mapping libraries from the command line UM 38 hierarchically UM 284 math_complex package UM 41 math_real package UM 41 Memory modeling in VHDL UM 301 Menus Dataflow window UM 136 List window UM 140 Main window UM 126 Process window UM 153 Signals window UM 156
233. line breakpoints UM 168 for more information Remove Signal Removes the signal breakpoint from the selected signal Remove All Signals Removes all signal breakpoints Show All Shows a list of all signal breakpoints When a breakpoint is hit a message appears in the transcript window about which signal caused the breakpoint Breakpoints created by the when command CR 181 are not affected by the Remove All Signals menu pick nor are they reported via Show All Wave window UM 199 Finding items by name or value in the Wave window The Find dialog box allows you to search for text strings in the Wave window Select Edit gt Find Wave window to bring up the Find dialog box Choose either the Name _ or Value field to search Find in wave i and enter the value to Find i Find Next search for in the Find Field Close field Find the item by Name IV Auto Wrap Direction searching Down or Up through the Wave window display Auto Wrap continues the search at the top of the window C Value The find operation works only within the active pane ModelSim User s Manual UM 200 7 Graphic Interface Using time cursors in the Wave window waye default c g KO SF S gt eS KOX eS These Wave window n ee ae we Ou vw gt buttons give you quick Rs Bo g E a ey S access to cursor placement sr ae OD S D amp ES Vv V 7 and zooming Te ai af
234. lity packages print a huge number of warnings vsim IgnoreNote 1 IgnoreWarning 1 IgnoreError 1 IgnoreFailure 1 Messages may also be turned off with Tcl variables see Preference variables located in Tcl files UM 287 Turning off warnings from arithmetic packages You can disable warnings from the synopsys and numeric standard packages by adding the following lines to the vsim section of the modelsim ini file vsim NumericStdNoWarnings 1 StdArithNoWarnings 1 Warnings may also be turned off with Tcl variables see Preference variables located in Tcl files UM 287 Force command defaults The force command has freeze drive and deposit options When none of these is specified then freeze is assumed for unresolved signals and drive is assumed for resolved signals This is designed to provide compatibility with force files But if you prefer freeze as the default for both resolved and unresolved signals you can change the defaults in the modelsim ini file vsim Default Force Kind The choices are freeze drive or deposit DefaultForceKind freeze ModelSim User s Manual UM 286 A ModelSim Variables ModelSim User s Manual Restart command defaults The restart command has force nobreakpoint nolist nolog and nowave options You can set any of these as defaults by entering the following line in the modelsim ini file DefaultRestartOptions lt options gt where
235. llength S vsimPriv WaveWindows set dialog_prompt result defaultName set windowName GetValue Create Named Wave Window Debug puts Window name SwindowName n if SwindowName set windowName if SwindowName named_wave windowName else named_wave defaultName Creates a new wave window with the provided name defaults to Wave proc named_wave name Wave global vsimPriv view new wave set newWave lindex vsimPriv WaveWindows expr llength SvsimPriv WaveWindows 1 wm title newWave name Writes out format of all wave windows stores geometry and title info in windowSet do file Removes any extra files with the same fileroot Default file name is wave lt n gt starting from 1 proc save_wave fileroot wave global vsimPriv set n 1 set fileId open windowSet_ fileroot do w 755 foreach w SvsimPriv WaveWindows echo Saving wm title w set filename fileroot n do write format wave window w filename puts fileId wm title w wm title w puts fileId wm geometry w wm geometry w puts fileId mtiGrid_colconfig w grid name width mtiGrid_colcget w grid name width puts fileId mtiGrid_colconfig w grid value width mtiGrid_colcget w grid value width flush fileId incr n ModelSim User s Manual UM 268 10 Tcl and macros if catch glob fileroot n 9 do foreach f lsort glob fileroot n
236. locked This keeps the Source window from flashing scrolling and moving the arrow when a complex DO file is executed Typically an onbreak resume command is used to keep the macro running as it hits breakpoints Add an onbreak abort command to the DO file if you want to exit the macro and update the Source window See the do command CR 64 ModelSim User s Manual UM 272 ModelSim User s Manual UM 273 A ModelSim Variables Appendix contents Variable settings report UM 274 Personal preferences UM 274 Returning to the original ModelSim defaults UM 274 Environment variables UM 275 Preference variables located in INI files UM 278 Library library path variables UM 278 vcom VHDL compiler control variables UM 278 vlog Verilog compiler control variables UM 279 vsim simulator control variables UM 280 Setting variables in INI files UM 283 Commonly used INI variables UM 284 Commonly used INI variables UM 284 Preference variables located in Tcl files UM 287 Variable precedence UM 288 Simulator state variables UM 289 This appendix documents the following types of ModelSim variables e environment variables Variables referenced and set according to operating system conventions Environment variables prepare the ModelSim environment prior to simulation e ModelSim preference variables Variables used to control compiler or simulator functions and modify the appearance of the ModelSim GUI e simulator sta
237. lt filename gt This option reads more command line arguments from the specified text file Nesting of f options is allowed t mindelays This option selects minimum delays from the min typ max expressions If preferred you can defer delay selection until simulation time by specifying the same option to the simulator typdelays This option selects typical delays from the min typ max expressions If preferred you can defer delay selection until simulation time by specifying the same option to the simulator maxdelays This option selects maximum delays from the min typ max expressions If preferred you can defer delay selection until simulation time by specifying the same option to the simulator ModelSim User s Manual UM 66 5 Verilog Simulation ModelSim User s Manual nowarn lt mnemonic gt This option disables the class of warning messages specified by lt mnemonic gt This option only disables warning messages accompanied by a mnemonic enclosed in square brackets For example WARNING test v 2 TFMPC Too few port connections This warning message can be disabled with the nowarnTFMPC option AL This option treats all identifiers in the source code as all uppercase Options supporting source libraries The following options support source libraries in the same manner as Verilog XL Note that these libraries are source libraries and are very different from the libraries that the ModelSim compiler use
238. ltech modelsim ini to use the next time ModelSim is invoked without an existing project if you start a new project the new MPF file will use the settings in the new modelsim ini file Environment variables UM 275 Environment variables Before compiling or simulating several environment variables may be set to provide the functions described in the table below The variables are in the autoexec bat file on Windows 95 98 machines and set through the System control panel on NT machines The LM_LICENSE_FILE variable is required all others are optional ModelSim Environment Variables Variable Description DOPATH used by ModelSim to search for simulator command files do files consists of a colon separated semi colon for Windows list of paths to directories optional this variable can be overridden by the DOPATH tcl file variable EDITOR specifies the editor to invoke with the edit command CR 68 HOME used by ModelSim to look for an optional graphical preference file and optional location map file see Preference variables located in INI files UM 278 and http www model com resources pref_variables frameset htm UM 299 LM_LICENSE_FILE used by the ModelSim license file manager to find the location of the license file may be a colon separated semi colon for Windows set of paths including paths to other vendor license files REQUIRED MODEL_TECH set by all ModelSim tools to the directory in whic
239. m After choosing the Layout Style you want select Options gt Save Preferences and the layout style will be saved to the PrefMain layoutStyle preference variable Project menu Compile Order set the compile order of the files in the open Project see Changing compile order UM 24 for details Compile All compile all files in the open Project see Step 3 Compile the files UM 22 for details Add File to Project add file s to the open Project see Step 2 Add files to the project UM 21 for details Run menu Run lt default gt run simulation for one default run length change the run length with Options gt Simulation or use the Run Length text box on the toolbar ModelSim User s Manual Run All Main window UM 129 run simulation until you stop it Continue continue the simulation Run Next run to the next event time Step single step the simulator Step Over execute without single stepping through a subprogram call Restart Macro menu reload the design elements and reset the simulation time to zero only design elements that have changed are reloaded you specify whether to maintain the following after restart list and wave window environment breakpoints logged signals and virtual definitions see also the restart command CR 104 Execute Macro browse for and execute a DO file macro Options menu Compile set
240. m names with the Edit gt Find menu selection in these windows List Process Signals Source Structure Variables and Wave windows You can also Locate time markers in the List window with the Markers gt Goto menu selection Locate time cursors in the Wave window with the Cursor gt Goto menu selection ModelSim User s Manual UM 120 7 Graphic Interface Sorting HDL items Use the Edit gt Sort menu selection in the windows below to sort HDL items in ascending descending or declaration order Process Signals Structure Variables and Wave windows Names such as net_1 net_10 and net_2 will sort numerically in the Signals and Wave windows Saving window layout Context menus Menu tear off ModelSim User s Manual You can save the current positions and sizes of ModelSim windows as a default Follow these steps to save the layout as a default 1 Position and size the windows the way you want them to display 2 Select Options gt Save Preferences Main window and save the modelsim tcl file into the desired directory 3 Modify the Working Directory of your ModelSim shortcut to point at the directory or set the MODELSIM_TCL environment variable to point at the directory see Creating environment variables in Windows UM 276 for more details Context menus refer to menus that pop up in the middle of the interface by clicking the right mouse button The commands on the menu change depending on
241. m source to output UM 251 The VCD file created as a result of the preceding scenario would be called output vcd The following pages show how it would look VCD output Scomment File created using the following command ved files output vcd Sdate Fri Jan 12 09 07 17 2000 Send Sversion ModelSim EE PLUS 5 4 Send Stimescale ins Send Sscope module shifter_mod Send Svar wire clk Send Svar wire reset Send data_in end 8 Send Send Send Send Send Send Send Send Send Svar wire Svar wire Svar wire Svar wire Svar wire Svar wire Svar wire Svar wire Svar wire OrRrNWHBA UO 2AQQAQA QQ aA Svar wire Supscope end Senddefinitions end 0 Sdumpvars 0 i O o 0 0 amp OF 0 0 0 O 0 Send 100 1 150 0 200 TI Sdumpoff x x x x xX X r x x x x X ModelSim User s Manual UM 252 9 Value Change Dump VCD Files 1 a end T 350 1150 0 QO 400 L o 0 450 0 amp 0 0 500 0 0 0 550 0 0 0 600 1200 I Sdumpall 650 Lf 0 1 700 1 o 0 750 0 amp 0 Q 800 0 0 r 0 850 O 0 0 900 end amp 950 0 ModelSim User s Manual UM 253 10 Tcl and macros Chapter contents Tcl features within ModelSim UM 254 Tcl References UM 254 Tcl commands UM 255 Tcl command syntax UM 256 if command syntax UM 258
242. mand CR 151 Virtual objects UM 110 virtual functions UM 111 ModelSim User s Manual virtual regions UM 112 virtual signals UM 110 virtual types UM 112 virtual region command CR 153 UM 112 Virtual regions reconstruct the RTL Hierarchy in gate level design UM 112 virtual save command CR 154 UM 111 virtual show command CR 155 virtual signal command CR 156 UM 110 Virtual signals reconstruct RTL level design busses UM 111 reconstruct the original RTL hierarchy UM 111 virtual hide command UM 111 virtual type command CR 159 VITAL compiling and simulating with accelerated VITAL packages UM 53 obtaining the specification and source code UM 52 VITAL 2000 library UM 41 VITAL packages UM 52 vlib command CR 161 vlog command CR 162 vmake command CR 166 vmap command CR 167 VPI registering applications UM 88 VPI PLI UM 86 compiling and linking applications UM 89 VSIM build date and version CR 179 vsim command CR 168 W Warnings disabling individual compiler warnings CR 131 disabling specific warning messages CR 164 CR 175 turning off warnings from arithmetic packages UM 285 wave adding CR 35 Wave format file UM 181 Wave log format WLF file CR 172 UM 103 of binary signal values CR 81 Wave window UM 178 toggling Waveform popup on off UM 179 UM 198 WaveActivateNextPane command CR 189 Waveform logfile log command CR 81 overview UM 103 Waveform popup UM 179 UM 198 Waveforms UM 103 saving and viewing CR 81 UM 104 savin
243. mands UM 261 System initialization UM 27 system tasks VCD UM 248 Verilog UM 77 T tab stops in the Source window UM 171 tb command CR 116 Tcl UM 253 UM 264 command separator UM 260 command substitution UM 259 command syntax UM 256 evaluation order UM 260 Man Pages in Help menu UM 130 preference variables UM 287 relational expression evaluation UM 260 variable substitution UM 261 VSIM Tcl commands UM 262 Text and command syntax UM 14 Text editing UM 133 UM 293 TextIO package alternative I O files UM 51 containing hexadecimal numbers UM 50 ModelSim User s Manual dangling pointers UM 50 ENDFILE function UM 50 ENDLINE function UM 50 file declaration UM 47 implementation issues UM 49 providing stimulus UM 51 standard input UM 48 standard output UM 48 WRITE procedure UM 49 WRITE_STRING procedure UM 49 TF routines UM 98 TFMPC disabling warning CR 175 Time simulation time units CR 14 time resolution as a simulator state variable UM 289 Time resolution in Verilog UM 70 setting with vsim command CR 171 UM 46 setting in the GUI UM 219 time type converting to real UM 56 Time based breakpoints UM 160 timescale directive warning disabling CR 175 Timing annotation UM 233 handling negative timing constraints UM 80 to_real VHDL function UM 56 to_time VHDL function UM 57 toggling Waveform popup on off UM 179 UM 198 Toolbar Main window UM 131 Wave window UM 186 Tracing HDL items with the Dataflow window UM 137 transcript
244. manent default ModelSim User s Manual UM 228 7 Graphic Interface e Ignore Assertions For Selects the assertion type to ignore for the current simulation Multiple selections are possible Edit the IgnoreFailure IgnoreError IgnoreWarning and IgnoreNote UM 281 variables in the modelsim ini file to set permanent defaults When an assertion type is ignored no message will be printed nor will the simulation halt even if break on assertion is set for that type gt Note Assertions that appear within an instantiation or configuration port map clause conversion function will not stop the simulation regardless of the severity level of the assertion WLF settings tab M Simulation Options Iof x E wre WLF File Size Limit WLF File Time Limit No Size Limit No Time Limit Size Limit fo WLF Attributes C Time Limit 0 ns gt Design Hierarchy V Compress WLF data Save regions containing logged signals I Delete WLF file on exit C Save all regions in design OK Cancel Apply The WLF Files tab includes these options e WLF File Size Limit Limits the WLF file by size as closely as possible to the specified number of megabytes If both size and time limits are specified the most restrictive is used Setting it to 0 results in no limit Edit the WLFSizeLimit UM 283 variable in the modelsim ini file to set a permanent default WLF File Time Limit Limit
245. modelsim ini file the system searches the current working directory for a subdirectory that matches the logical name An error is generated by the compiler if you specify a logical name that does not resolve to an existing directory See also See Commands CR 25 for more information about the library management commands Graphic Interface UM 115 for more information about the graphical user interface and Projects and system initialization UM 15 for more information about the modelsim ini file Working with design libraries UM 39 Moving a library Individual design units in a design library cannot be moved An entire design library can be moved however by using standard operating system commands for moving a directory ModelSim User s Manual UM 40 3 Design libraries Specifying the resource libraries VHDL resource libraries Within a VHDL source file you can use the VHDL library clause to specify logical names of one or more resource libraries to be referenced in the subsequent design unit The scope of a library clause includes the text region that starts immediately after the library clause and extends to the end of the declarative region of the associated design unit Jt does not extend to the next design unit in the file Note that the library clause is not used to specify the working library into which the design unit is placed after compilation the veom command CR 129 adds compiled design units to the cu
246. modules compiled with nodebug can only instantiate design units or modules that are also compiled nodebug ModelSim User s Manual UM 298 C Tips and Techniques Saving and viewing waveforms in batch mode You can run vsim as a batch job but view the resulting waveforms later 1 When you invoke vsim the first time use the wlf option to rename the wave log format WLF file and redirect stdin to invoke the batch mode The command should look like this vsim wlf wavesavl wlf counter lt command do Within your command do file use the log command CR 81 to save the waveforms you want to look at later run the simulation and quit When vsim runs in batch mode it does not write to the screen and can be run in the background 2 When you return to work the next day after running several batch jobs you can start up vsim in its viewing mode with this command and the appropriate w f files vsim view wavesavl wlf Now you will be able to use the Waveform and List windows normally Setting up libraries for group use ModelSim User s Manual By adding an others clause to your modelsim ini file you can have a hierarchy of library mappings If the ModelSim tools don t find a mapping in the modelsim ini file then they will search the library section of the initialization file specified by the others clause For example library asic_lib cae asic_lib work my_work others usr modeltech modelsim ini
247. mouse button and select Divider Properties from the pop up menu To delete a divider Select the divider and either press the lt Delete gt key on your keyboard or select Delete from the pop up menu ModelSim User s Manual UM 190 7 Graphic Interface Splitting Wave window panes The pathnames values and waveforms window panes of the Wave window display can be split to accommodate signals from one or more datasets Selecting File gt New Window Pane Wave window creates a space below the selected waveset and makes the new window pane the selected pane The selected wave window pane is indicated by a white bar along the left margin of the pane In the illustration below the Wave window is split showing the current active simulation with the prefix sim and a second view mode dataset with the prefix gold For more information on viewing multiple simulations see Chapter 6 WLF files datasets and virtuals wave default E 3 5 x File Edit Cursor Zoom Compare Bookmark Format Window oH tM RA eX QQQQh lesi 3H sim top clk sim top prw sim top pstrb sim top prdy w ak fe F gold top clk gold top prw gold top pstrb gold top prdy gold top paddr 00000001 2820 ns 340 ns ENNE JE R10 ne ta DAAH ne BEE Ak ModelSim User s Manual Wave window UM 191 Combining items in the Wave window You can combine signals in the Wave window i
248. mpatible routines 2 2 2 ee eee ee UM 100 64 bit support in the PLI 2 2 2 2 2 2 2 UM 100 PLIVPI facing s oo e oo a eo ote Se ee A Be we ete Se 4 UM 6 WLF files datasets and virtuals UM 103 WLF files datasets UM 104 Saving a simulation to a WLF ie z UM 104 Opening datasets UM 105 Viewing dataset structure UM 106 Managing datasets UM 108 Using datasets with ModelSim M UM 108 Restricting the dataset prefix display UM 109 Virtual Objects User defined buses and more UM 110 Virtual signals UM 110 Virtual functions UM 111 Virtual regions UM 112 Virtual types UM 112 Dataset WLF file and virtual commands UM 113 7 Graphic Interface UM 115 Window overview UM 116 Common window features UM 117 Quick access toolbars UM 118 Drag and Drop UM 118 Command history UM 118 Automatic window updating UM 119 Finding names and locating cursors UM 119 Sorting HDL items UM 120 Saving window layout UM 120 Context menus UM 120 ModelSim User s Manual UM 6 Table of Contents Menu tear off Combining signals into a user dated bis Tree window hierarchical view Main window Workspace Transcript The Main window menu bat The Main window toolbar The Main window status bar Mouse and keyboard shortcuts Dataflow window Link to active cursor in Wave vindos Dataflow window menu bar Tracing HDL items with the Dataflow wie Saving the Da
249. n CR 59 dataset rename CR 60 delete CR 61 describe CR 62 disablebp CR 63 do CR 64 drivers CR 65 dumplog64 CR 66 echo CR 67 edit CR 68 enablebp CR 69 environment CR 70 examine CR 71 exit CR 73 find CR 74 force CR 76 graphic interface commands UM 232 help CR 79 history CR 80 log CR 81 Ishift CR 83 Isublist CR 84 modelsim CR 85 noforce CR 86 nolog CR 87 notation conventions CR 6 notepad CR 89 noview CR 90 nowhen CR 91 onbreak CR 92 onElabError CR 93 onerror CR 94 pause CR 95 pwd CR 98 quietly CR 99 quit CR 100 radix CR 101 report CR 102 restart CR 104 resume CR 106 run CR 107 ModelSim User s Manual searchlog CR 109 shift CR 111 show CR 112 status CR 113 step CR 114 stop CR 115 system UM 261 tb traceback CR 116 transcript CR 117 TreeUpdate CR 189 tssi2mti CR 118 variables referenced in CR 14 vcd add CR 119 ved checkpoint CR 120 ved comment CR 121 ved file CR 122 ved files CR 123 ved flush CR 124 ved limit CR 125 ved off CR 126 ved on CR 127 vcom CR 129 vdel CR 134 vdir CR 135 vgencomp CR 136 view CR 138 virtual count CR 139 virtual define CR 140 virtual delete CR 141 virtual describe CR 142 virtual expand CR 143 virtual function CR 144 virtual hide CR 147 virtual log CR 148 virtual nohide CR 150 virtual nolog CR 151 virtual region CR 153 virtual save CR 154 virtual show CR 155 virtual signal CR 156 virtual type CR 159 vlib CR 161 vlog CR 162 vmak
250. n occurs then no further substitutions are performed on the value of the variable the value is inserted into the word verbatim If command substitution occurs then the nested command is processed entirely by the recursive call to the Tcl interpreter no substitutions are performed before making the recursive call and no additional substitutions are performed on the result of the nested script 11 Substitutions do not affect the word boundaries of a command For example during variable substitution the entire value of the variable becomes part of a single word even if the variable s value contains spaces if command syntax The Tcl if command executes scripts conditionally Note that in the syntax below the indicates an optional argument Syntax if expri then bodyl elseif expr2 then body2 elseif else bodyN Description The if command evaluates expr as an expression The value of the expression must be a boolean a numeric value where 0 is false and anything else is true or a string value such as true or yes for true and false or no for false if it is true then body is executed by passing it to the Tcl interpreter Otherwise expr2 is evaluated as an expression and if it is true then body2 is executed and so on If none of the expressions evaluates to true then bodyN is executed The then and else arguments are optional noise words to make the command easier to read There may be any number of elseif clauses inclu
251. n the graphic above tabs open in the workspace Delete a project Select File gt Delete gt Project Main window ModelSim User s Manual UM 24 2 Projects and system initialization Customizing project settings Though the default project settings will work for many designs it is easy to customize the settings if needed Changing compile order Grouping files ModelSim User s Manual When you compile all files in a project ModelSim by default compiles the files in the order in which they were added to the project You have two alternatives for changing the default compile order 1 select and compile each file individually 2 specify a custom compile order To specify a custom compile order follow these steps 1 Right click in an empty area of the Project tab and select Sort by Compile Order 2 Drag the files into the correct order Note that you can select multiple files and drag them simultaneously gt Note Files can be displayed in the Project tab in alphabetical or compile order using the Sort by Alphabetical Order or Sort by Compile Order commands on the context menu Keep in mind that the order you see in the Project tab is not necessarily the order in which the files will be compiled You can group two or more files in the Project tab You might do this for organizational purposes or to send the files to the compiler at the same time For example you might have one file with a bunch of Verilog define sta
252. n the pathname pane or its waveform in the waveform pane then select Edit gt Signal Properties Wave window The resulting Wave Signal Properties dialog box has three tabs View Format and Compare e Signal Properties The View tab includes these options Display Name Specifies a new name in the pathname pane for the selected signal Radix Specifies the Radix of the selected signal s Setting this to default causes the signal s radix to change whenever the default is modified using the radix command CR 101 Item values are not translated if you select Symbolic Wave Color Specifies the waveform color Select a new color from the color palette or enter an X Windows color name Name Color Specifies the signal name s color Select a new color from the color palette or enter an X Windows color name ModelSim User s Manual UM 194 7 Graphic Interface Wave Signal Properties The Format tab includes these options e Format Literal Displays the waveform as a box containing the item value if the value fits the space available This is the only format that can be used to list a record Format Logic Displays values as U X 0 1 Z W L H or e Format Event Marks each transition during the simulation run ModelSim User s Manual Wave window UM 195 Format Analog Step Interpolated Backstep All signals in the following illustration are the same top clk signal Sta
253. n time at the bottom When you have more than one cursor each time box appears in a separate track at the bottom of the display ModelSim also adds a delta measurement showing the time difference between two adjacent cursor positions If you click in the waveform display the cursor closest to the mouse position is selected and then moved to the mouse position Another way to position multiple cursors is to use the mouse in the time box tracks at the bottom of the display Clicking anywhere in a track selects that cursor and brings it to the mouse position The cursors are designed to snap to the closest wave edge to the left on the waveform that the mouse pointer is positioned over You can control the snap distance via the Edit gt Display Properties menu selection You can position a cursor without snapping by dragging in the area below the waveforms You can also move cursors to the next transition of a signal with these toolbar buttons Find Previous Find Next Transition Transition locate the next signal locate the previous signal value change for the value change for the selected signal selected signal Zooming changing the waveform display range Zooming lets you change the simulation range in the waveform pane You can zoom with either the context menu toolbar buttons mouse keyboard or commands Using the Zoom menu You can use the Wave window menu bar or call up the context menu by clicking the right mouse button in
254. n units configurations modules packages entities and architectures in a library Note the icons identify whether a unit is an entity E a module M and so forth ModelSim File Edit Design View Project Run Macro Options Window Help Pill Es ModelSim gt E org IC test_adder_behavioral IC test_adder_structural 1 test_counter E testhench Library zj lt No Design Loaded gt Ai The Library tab includes these options e Library Select the library you wish to view from the drop down list Related command line command is vdir CR 135 ModelSim User s Manual Working with design libraries UM 35 e DesignUnit Description list Select a plus box to view the associated architecture or select a minus box to hide the architecture The Library tab also has two context menus that you access with your right mouse button One menu is accessed by right clicking a design unit name the second is accessed by right clicking a blank area in the Library tab The graphic below shows the two menus METE OL x File Edit Design View Project Run Compare Macro Options Window Help Loading package gates Compiling architecture structural of adder Loading entity adder Loading entity xorg Loading entity andg Loading entity org Compiling entity addern Compiling architecture structural of addern Loading entity adder Compiling architecture behavioral
255. n window They can also be used in editing the file displayed in the Source window and all Notepad windows enter the notepad command within ModelSim to open the Notepad editor UM 133 for details Saving the Main window transcript file Variable settings determine the filename used for saving the Main window transcript If either PrefMain file in modelsim tcl or TranscriptFile in modelsim ini file is set then the transcript output is logged to the specified file By default the TranscriptFile variable in modelsim ini is set to transcript If either variable is set the transcript contents are always saved and no explicit saving is necessary If you would like to save an additional copy of the transcript with a different filename you can use the File gt Save Transcript As or File gt Save Transcript menu items The initial save must be made with the Save Transcript As selection which stores the filename in the Tcl variable PrefMain saveFile Subsequent saves can be made with the Save Transcript selection Since no automatic saves are performed for this file it is written only when you invoke a Save command The file is written to the specified directory and records the contents of the transcript at the time of the save Using the saved transcript as a macro DO file Saved transcript files can be used as macros DO files See the do command CR 64 for more information UM 125 ModelSim User s Manual UM 126 7 Graphic Int
256. nd selection of text by word lt up down arrow gt scroll through command history in Source window moves cursor one line up down lt control gt lt up down gt move cursor up down one paragraph lt alt gt activate or inactivate menu bar mode lt alt gt lt F4 gt close active window lt backspace gt delete character to the left lt home gt move cursor to the beginning of the line lt end gt move cursor to the end of the line ModelSim User s Manual UM 134 7 Graphic Interface ModelSim User s Manual Keystrokes Result lt control gt lt home gt move cursor to the beginning of the text lt control gt lt end gt move cursor to the end of the text lt esc gt cancel lt control a gt select the entire content of the widget lt control c gt copy the selection lt control f gt find lt F3 gt find next lt control k gt delete from the cursor to the end of the line lt control s gt save lt control t gt reverse the order of the two characters to the right of the cursor lt control u gt delete line lt control v gt paste from the clipboard lt control x gt cut the selection lt F8 gt search for the most recent command that matches the characters typed lt F9 gt run simulation lt F10 gt
257. ng for user input reason_Sscope For the execution of the environment command or selecting a scope in the structure window Also for the call to acc_set_interactive_scope if the callback_flag argument is non zero reason_paramvc For the change of value on the system task or function argument ModelSim User s Manual UM 94 5 Verilog Simulation reason_synch For the end of time step event scheduled by tf_synchronize reason_rosynch For the end of time step event scheduled by tf_rosynchronize reason_reactivate For the simulation event scheduled by tf_setdelay reason_paramdrc Not supported in ModelSim Verilog reason_force Not supported in ModelSim Verilog reason_release Not supported in ModelSim Verilog reason_disable Not supported in ModelSim Verilog The sizetf callback function A user defined system function specifies the width of its return value with the sizetf callback function and the simulator calls this function while loading the design The following details on the sizetf callback function are not found in the IEEE Std 1364 e If you omit the sizetf function then a return width of 32 is assumed e The sizetf function should return 0 if the system function return value is of Verilog type real e The sizetf function should return 32 if the system function return value is of Verilog type integer PLI object handles Many of the object handles returned by the PLI ACC routines are pointe
258. nging compile order Boe ee me o Ge UME Setting compiler options 2 a UM 25 Accessing projects from the commandline UM 26 System initialization eo owe Oe we ee amp oe po a UM 27 Files accessed during siiip eaaa a a UM 27 Environment variables accessed diag vere oo ele UM 28 Initialization sequence a a UM 29 This chapter discusses ModelSim projects Projects simplify the process of compiling and simulating a design and are a great tool for getting started with ModelSim This chapter also includes a section on Model Sim initialization ModelSim User s Manual UM 16 2 Projects and system initialization Introduction What are projects Projects are collection entities for HDL designs under specification or test At a minimum projects have a root directory a work library and metadata which are stored in a mpf file located in a project s root directory The metadata include compiler switch settings compile order and file mappings Projects may also consist of HDL source files or references to source files other files such as READMEs or other project documentation local libraries references to global libraries What are the benefits of projects ModelSim User s Manual Projects offer benefits to both new and advanced users Projects simplify interaction with ModelSim you don t need to understand the intricacies of compiler switches and library mappin
259. notated if the output port is omitted If the module contains no path delays then all primitives that drive the specified output port are annotated or all primitives that drive any output port if the output port is omitted SETUP is matched to setup and setuphold SDF Verilog SETUP d posedge clk 5 setup d posedge clk 0 SETUP d posedge clk 5 setuphold posedge clk d 0 0 HOLD is matched to hold and setuphold SDF Verilog HOLD d posedge clk 5 hold posedge clk d 0 HOLD d posedge clk 5 setuphold posedge clk d 0 0 SETUPHOLD is matched to setup hold and setuphold SDF Verilog SETUPHOLD d posedge clk 5 5 setup d posedge clk 0 SETUPHOLD d posedge clk 5 5 hold posedge clk d 0 SETUPHOLD d posedge clk 5 5 setuphold posedge clk d 0 0 RECOVERY is matched to recovery SDF Verilog RECOVERY negedge reset posedge clk 5 recovery negedge reset posedge clk 0 REMOVAL is matched to removal SDF Verilog REMOVAL negedge reset posedge clk 5 removal negedge reset posedge clk 0 ModelSim User s Manual Verilog SDF UM 241 RECRENM is matched to recovery removal and recrem SDF Verilog RECREM negedge reset posedge clk 5 5 recovery negedge reset posedge clk 0 RECREM negedge reset posedge clk 5 5 removal ne
260. ns The annotator uses the following rules to match conditions A match occurs if the SDF does not have a condition e A match occurs for a timing check if the SDF port condition is semantically equivalent to the specify port condition e A match occurs for a path delay if the SDF condition is lexically identical to the specify condition Timing check conditions are limited to very simple conditions therefore the annotator can match the expressions based on semantics For example Verilog SETUP data COND reset 1 posedge clock 5 setup data posedge clk amp amp amp reset 0 0 ModelSim User s Manual Verilog SDF UM 243 The conditions are semantically equivalent and a match occurs In contrast path delay conditions may be complicated and semantically equivalent conditions may not match For example SDF Verilog COND r1 Il r2 OPATH clk q 5 if r1 Il r2 clk gt q 5 matches COND r1 Il r2 COPATH clk q 5 if r2 Il r1 clk gt q 5 does not match The annotator does not match the second condition above because the order of rl and r2 are reversed Rounded timing values The SDF TIMESCALE construct specifies time units of values in the SDF file The annotator rounds timing values from the SDF file to the time precision of the module that is annotated For example if the SDF TIMESCALE is Ins and a value of 016 is annotated to a path delay in a
261. ns and Verilog modules and UDPs user defined primitives The design units are classified as follows Primary design units Consist of entities package declarations configuration declarations modules and UDPs Primary design units within a given library must have unique names Secondary design units Consist of architecture bodies and package bodies Secondary design units are associated with a primary design unit Architectures by the same name can exist if they are associated with different entities Design unit information The information stored for each design unit in a design library is e retargetable executable code e debugging information e dependency information Design library types ModelSim User s Manual There are two kinds of design libraries working libraries and resource libraries A working library is the library into which a design unit is placed after compilation A resource library contains design units that can be referenced within the design unit being compiled Only one library can be the working library in contrast any number of libraries including the working library itself can be resource libraries during a compilation The library named work has special attributes within ModelSim it is predefined in the compiler and need not be declared explicitly i e library work It is also the library name used by the compiler as the default destination of compiled design units In other words the work libr
262. nsistency throughout all operating system environments 8 Standard Delay Format SDF Timing Annotation UM 233 This chapter discusses ModelSim s implementation of SDF Standard Delay Format timing annotation Included are sections on VITAL SDF and Verilog SDF plus troubleshooting 9 Value Change Dump VCD Files UM 247 This chapter explains Model Technology s Verilog VCD implementation for ModelSim The VCD usage is extended to include VHDL designs 10 Tcl and macros UM 253 This chapter provides an overview of Tcl tool command language as used with ModelSim A ModelSim Variables UM 273 This appendix describes environment system and preference variables used in ModelSim B ModelSim Shortcuts UM 291 This appendix describes ModelSim keyboard and mouse shortcuts C Tips and Techniques UM 295 This appendix contains an extended collection of ModelSim usage examples taken from our manuals and tech support solutions Command reference The complete command reference for all ModelSim commands is located in the ModelSim Command Reference Command Reference cross reference page numbers are prefixed with CR e g Commands CR 25 ModelSim User s Manual UM 14 1 Introduction What is an HDL item Because ModelSim works with both VHDL and Verilog HDL refers to either VHDL or Verilog when a specific language reference is not needed Depending on the context HDL item can refer to any
263. ntation issues UM 49 Writing strings and aggregates UM 49 Reading and writing hexadecimal saianibers UM 50 Dangling pointers UM 50 The ENDLINE function UM 50 The ENDFILE function UM 50 Using alternative input output files UM 51 Providing stimulus UM 51 Obtaining the VITAL specification and source code UM 52 VITAL packages UM 52 ModelSim VITAL compliance UM 52 VITAL compliance checking UM 52 Compiling and Simulating with decelented VITAL packas UM 53 Compiling and Simulating with accelerated VITAL packages UM 53 Util package UM 54 get_resolution UM 54 init_signal_spy UM 55 to_real UM 56 to_time UM 57 This chapter provides an overview of compilation and simulation for VHDL designs within the ModelSim environment using the TextIO package with ModelSim ModelSim s implementation of the VITAL VHDL Initiative Towards ASIC Libraries specification for ASIC modeling and documentation on ModelSim s special built in utilities package The TextIO package is defined within the VHDL Language Reference Manuals IEEE Std 1076 1987 and IEEE Std 1076 1993 it allows human readable text input from a declared source within a VHDL file during simulation ModelSim User s Manual UM 44 4 VHDL Simulation Compiling and simulating with the GUI Many of the examples in this chapter are shown from the command line For compiling and simulating within a project or the ModelSim GUI see e Get
264. nto busses A bus is a collection of signals concatenated in a specific order to create a new virtual signal with a specific value To create a bus select one or more signals in the Wave window and then choose Edit gt Combine EF Combine Selected Signals Name EUSI Combine Into Order of Indexes Bus C Ascending C Group Descending I Remove selected signals after combining OK Cancel The Combine Selected Signals dialog box includes these options e Combine Into Only the Bus option is valid at this time Groups are not currently implemented Order of Indexes Specifies in which order the selected signals are indexed in the bus If set to Ascending the first signal selected in the Wave window will be assigned an index of 0 If set to Descending the first signal selected will be assigned the highest index number Remove selected signals after combining Specifies whether you want to remove the selected signals from the Wave window once the bus is created In the illustration below three signals have been combined to form a new bus called BUS 1 Note that the component signals are listed in the order in which they were selected in the Wave window Also note that the bus value is made up of the values of its component signals arranged in a specific order Virtual objects are indicated by an orange diamond ModelSim User s Manual UM 192 7 Graphic Interface wave default 10 x Fil
265. nu bar File menu New edit a new VHDL Verilog or Other source file Open select a source file to open Use Source specify an alternative file to use for the current source file this alternative source mapping exists for the current simulation only Source Directory add to a list of directories the SourceDir variable in modelsim tcl to search for source files Properties list a variety of information about the source file for example file type file size file modification date Save save the current source file Save As save the current source file with a different name Compile compile HDL source files Close close this copy of the Source window Edit menu To edit a source file make sure the Read Only option in the Source Options dialog box is not selected use the Edit gt read only Source menu selection lt editing option gt basic editing options include Undo Cut Copy Paste Select All and Unselect All see The following mouse actions and special keystrokes can be used to edit commands in the entry region of the Main window They can also be used in editing the file displayed in the Source window and all Notepad windows enter the notepad command within ModelSim to open the Notepad editor UM 133 Comment Selected turns the selected lines into comments by inserting the correct language comment character at the beginning of each line Uncomment removes comment ch
266. obust scripting language for macros Tcl References ModelSim User s Manual Two books about Tcl are Tcl and the Tk Toolkit by John K Ousterhout published by Addison Wesley Publishing Company Inc and Practical Programming in Tcl and Tk by Brent Welch published by Prentice Hall You can also consult the following online references e Select Help gt Tcl Man Pages Main window e The Model Technology web site lists a variety of Tcl resources www model com resources tcltk asp Tcl commands Tcl commands UM 255 For complete information on Tcl commands select Help gt Tcl Man Pages Main window Also see Preference variables located in Tcl files UM 287 for information on Tcl variables ModelSim command names that conflict with Tcl commands have been renamed or have been replaced by Tcl commands See the list below Previous ModelSim command Command changed to or replaced by continue run CR 107 with the continue option format list wave write format CR 188 with either list or wave specified if replaced by the Tcl if command see if command syntax UM 258 for more information list add list CR 32 nolist nowave delete CR 61 with either list or wave specified set replaced by the Tcl set command see set command syntax UM 259 for more information vsource CR 180 add wave CR 35 ModelSim User s Manual UM 256 10 Tcl and ma
267. ode This provides more flexibility than the command line options The sdf_annotate system task ModelSim User s Manual The syntax for sdf_annotate is Syntax Ssdf_annotate lt sdffile gt lt instance gt lt config_file gt lt log_file gt lt mtm_spec gt lt scale_factor gt lt scale_type gt Arguments lt sdffile gt String that specifies the SDF file Required lt instance gt Hierarchical name of the instance to be annotated Optional Defaults to the instance where the sdf_annotate call is made lt config_file gt String that specifies the configuration file Optional Currently not supported this argument is ignored lt log_file gt String that specifies the logfile Optional Currently not supported this argument is ignored lt mtm_spec gt String that specifies the delay selection Optional The allowed strings are minimum typical maximum and tool_control Case is ignored and the default is tool_control The tool_control argument means to use the delay specified on the command line by mindelays typdelays or maxdelays defaults to typdelays lt scale factors String that specifies delay scaling factors Optional The format is lt min_mult gt lt typ_mult gt lt max_mult gt Each multiplier is a real number that is used to scale the corresponding delay in the SDF file lt scale_type gt String that overrides the lt mtm
268. og Although ModelSim is an excellent tool to use while learning HDL concepts and practices this document is not written to support that goal Finally we make the assumption that you have worked the appropriate lessons in the ModelSim Tutorial and are therefore familiar with the basic functionality of ModelSim The ModelSim Tutorial is available from the ModelSim Help menu this document In addition to this introduction you will find the following major sections in this document 2 Projects and system initialization UM 15 This chapter provides a definition of a ModelSim project and discusses the use of a new file extension for project files 3 Design libraries UM 31 To simulate an HDL design using ModelSim you need to know how to create compile maintain and delete design libraries as described in this chapter 4 VHDL Simulation UM 43 This chapter is an overview of compilation and simulation for VHDL within the ModelSim environment 5 Verilog Simulation UM 59 This chapter is an overview of compilation and simulation for Verilog within the ModelSim environment Command reference UM 13 6 WLF files datasets and virtuals UM 103 This chapter describes datasets and virtuals both methods for viewing and organizing simulation data in ModelSim 7 Graphic Interface UM 115 This chapter describes the graphic interface available while operating ModelSim ModelSim s graphic interface is designed to provide co
269. ok for variables that have been defined either by ModelSim or by you and substitute the value of the variable gt Note Tcl is case sensitive for variable names To access environment variables use the construct Senv lt var_name gt echo My user name is Senv USER Environment variables can also be set using the env array set env SHELL bin csh See Simulator state variables UM 289 for more information about ModelSim defined variables System commands To pass commands to the DOS window use the Tcl exec command echo The date is exec date ModelSim User s Manual UM 262 10 Tcl and macros List processing In Tcl a list is a set of strings in curly braces separated by spaces Several Tcl commands are available for creating lists indexing into lists appending to lists getting the length of lists and shifting lists These commands are Command syntax Description lappend var_name vall val appends vall val2 etc to list var_name lindex list_name index returns the index th element of list_name the first element is 0 linsert list_name index val1 val2 inserts vall val2 etc just before the index th element of list_name list vall val2 returns a Tcl list consisting of val1 val2 etc llength list_name returns the number of elements in list_name Irange list_name first last returns a sublist of list_name from index first to index last first or last may be end
270. ollows void mti_RegisterUserTF p_tfcell usertf The storage for each usertf entry passed to the simulator must persist throughout the simulation because the simulator de references the usertf pointer to call the callback functions It is recommended that you define your entries in an array with the last entry set to 0 If the array is named veriusertfs as is the case for linking to Verilog XL then you don t have to provide an init_usertfs function and the simulator will automatically register the entries directly from the array the last entry must be 0 For example s_tfcell veriusertfs usertask 0 0 0 abc_calltf 0 Sabc usertask 0 0 0 xyz_calltf 0 Sxyz 0 last entry must be 0 Alternatively you can add an init_usertfs function to explicitly register each entry from the array void init_usertfs p_tfcell usertf veriusertfs while usertf gt type mti_RegisterUserTF usertftt It is an error if a PLI shared library does not contain a veriusertfs array or an init_usertfs function Since PLI applications are dynamically loaded by the simulator you must specify which applications to load each application must be a dynamically loadable library see Compiling and linking PLI VPI applications UM 89 The PLI applications are specified as follows e As a list in the Veriuser entry in the modelsim ini file Veriuser pliappl so pliapp2 so pliappn so e As a list in the PLIO
271. ons top sdata see Virtual Objects User defined buses and more UM 110 for more information Comparison items indicated by a yellow triangle comparison region and comparison signals see Chapter 10 Waveform Comparison for more information gt Note Constants generics and parameters are not viewable in the List or Wave windows The data in the item values pane is very similar to the Signals window except that the values change dynamically whenever a cursor in the waveform pane is moved At the bottom of the waveform pane you can see a time line tick marks and a readout of each cursor s position As you click and drag to move a cursor the time value at the cursor location is updated at the bottom of the cursor Wave window UM 181 You can resize the window panes by clicking on the bar between them and dragging the bar to a new location Waveform and signal name formatting are easily changed via the Format menu UM 184 You can reuse any formatting changes you make by saving a Wave window format file see Adding items with a Wave window format file UM 181 Adding HDL items in the Wave window Before adding items to the Wave window you may want to set the window display properties see Setting Wave window display properties UM 197 You can add items to the Wave window in several ways Adding items from the Signals window with drag and drop You can drag and drop items into the Wave window from the L
272. or the VHDL signals and variables and Verilog nets and register variables you have selected Current and past simulations can be compared side by side in one Wave window Common window features Common window features UM 117 ModelSim s graphic interface provides many features that add to its usability features common to many of the windows are described below Feature Feature applies to these windows Quick access toolbars UM 118 Main Source and Wave windows Drag and Drop UM 118 Wave windows Dataflow List Signals Source Structure Variables and Command history UM 118 Main window command line Automatic window updating UM 119 Dataflow Process Signals and Structure windows Finding names and locating cursors UM 119 various windows Sorting HDL items UM 120 windows Process Signals Source Structure Variables and Wave Menu tear off UM 120 all windows Combining signals into a user defined bus UM 121 List and Wave windows Tree window hierarchical view UM 121 Cut Copy Paste Delete into any entry box by clicking the right mouse button in the entry box Standard cut copy paste shortcut keystrokes X 4C 4V will work in all entry boxes When the focus changes to an entry box the contents of that box are selected highlighted This allows you to replace the current contents of the entry box with new contents with a simple pa
273. ort lt init_function gt app obj lt install_dir gt modeltech win32 mtipli lib out app exe For the Verilog PLI the lt init_function gt should be init_usertfs Alternatively if there is no init_usertfs function the lt init_function gt specified on the command line should be veriusertfs For the Verilog VPI the lt init_function gt should be vlog_startup_routines These requirements ensure that the appropriate symbol is exported and thus ModelSim can find the symbol when it dynamically loads the DLL The PLI and VPI have been tested with DLLs built using Microsoft Visual C C compiler version 4 1 or greater The gcc compiler cannot be used to compile PLI VPI applications under Windows This is because gcc does not support the Microsoft lib dll format ModelSim User s Manual UM 90 5 Verilog Simulation ModelSim User s Manual Specifying the PLI VPI file to load The PLI applications are specified as follows e As a list in the Veriuser entry in the modelsim ini file Veriuser pliappl so pliapp2 so pliappn so e As a list in the PLIOBJS environment variable setenv PLIOBJUS pliappl so pliapp2 so pliappn so e As a pli option to the simulator multiple options are allowed pli pliappl so pli pliapp2 so pli pliappn so gt Note On Windows platforms the file names shown above should end with dll rather than so The various methods of specifying PLI applications can be used simultaneously Th
274. ou can define display properties of the Wave window by selecting Edit gt Display Properties Wave window To save these settings permanently select Options gt Save Preferences Main window 5 Wave Window Properties 5 x Display Signal Path r Snap Distance jo elements fi 0 pixels Use 0 for full path Row Margin 4 pixels Pan Child Row Margin Left Right 2 pixels Waveform Popup IV Waveform Popup Enabled Dataset Prefix Display C Always Show Dataset Prefixes Show Dataset Prefixes if 2 or more OK Cancel The Wave Window Properties dialog box includes the following options e Display Signal Path Sets the display to show anything from the full pathname of each signal e g sim top clk to only its leaf element e g sim clk A non zero number indicates the number of path elements to be displayed The default is Full Path You can change this permanently by editing the SignalNameWidth Tcl variable See Preference variables located in Tcl files UM 287 for details Justify Value Specifies whether the signal values will be justified to the left margin or the right margin in the values window pane Snap Distance Specifies the distance the cursor needs to be placed from an item edge to jump to that edge a 0 specification turns off the snap e Row Margin Specifies the distance in pixels between top level signals ModelSim User s
275. ow menu bar File menu Write List format save the listing as a text file in one of three formats tabular events or TSSI Load Format run a List window format DO file previously saved with Save Format Save Format save the current List window display and signal preferences to a DO macro file running the DO file will reformat the List window to match the display as it appeared when the DO file was created Close Edit menu close this copy of the List window Cut cut the selected item field from the listing see Editing and formatting HDL items in the List window UM 145 Copy copy the selected item field Paste paste the previously cut or copied item to the left of the currently selected item Delete delete the selected item field Combine combine the selected fields into a user defined bus keep copies of the original items rather than moving them see Combining signals into a user defined bus UM 121 Select All select all signals in the List window Unselect All deselect all signals in the List window Find find the specified item label within the List window Markers menu Add Marker add a time marker at the currently selected line Delete Marker delete the selected marker from the listing Goto choose the time marker to go to from a list of current markers ModelSim User s Manual List window UM
276. pe acc_set_value acc_vcl_add acc_vcl_ delete acc_version gt Note acc_fetch_paramval cannot be used on 64 bit platforms to fetch a string value of a parameter Because of this the function acc_fetch_paramval_str has been added to the PLI for this use acc_fetch_paramval_str is declared in acc_user h It functions in a manner similar to acc_fetch_paramval except that it returns a char acc_fetch_paramval_str can be used on all platforms IEEE Std 1364 TF routines ModelSim Verilog supports the following TF routines described in detail in the IEEE Std 1364 io_mcdprintf io_printf mc_scan_plusargs tf_add_long tf_asynchoff tf_iasynchoff tf_asynchon tf_iasynchon tf_clearalldelays tf_iclearalldelays tf_compare_long tf_copypvc_flag tf_icopypvc_flag tf_divide_long tf_dofinish tf_dostop tf_error tf_evaluatep tf_ievaluatep tf_exprinfo tf_iexprinfo tf_getcstringp tf_igetcstringp tf_getinstance tf_getlongp tf_igetlongp tf_getlongtime tf_igetlongtime tf_getnextlongtime tf_getp tf_igetp tf_getpchange tf_igetpchange tf_getrealp tf_igetrealp tf_getrealtime tf_igetrealtime tf_gettime tf_igettime tf_gettimeprecision tf_igettimeprecision tf_gettimeunit tf_igettimeunit ModelSim User s Manual tf_getworkarea tf_igetworkarea tf_long_to_real tf_longtime_
277. pecified by lt mnemonic gt This option only disables warning messages accompanied by a mnemonic enclosed in square brackets For example WARNING test v 2 TFMPC Too few port connections This warning message can be disabled with the nowarnTFMPC option ntc_warn This option enables warning messages from the negative timing constraint algorithm This algorithm attempts to find a set of delays for the timing check delayed net arguments such that all negative limits can be converted to non negative limits with respect to the delayed nets If there is no solution for this set of limits then the algorithm sets one of the negative limits to zero and recalculates the delays This process is repeated until a solution is found A warning message is issued for each negative limit set to zero By default these warnings are disabled t pulse_e lt percent gt This option controls how pulses are propagated through specify path delays where lt percent gt is a number between 0 and 100 that specifies the error limit as a percentage of the path delay A pulse greater than or equal to the error limit propagates to the output in transport mode transport mode allows multiple pending transitions on an output A pulse less than the error limit and greater than or equal to the rejection limit see pulse_r lt percent gt propagates to the output as an X If the rejection limit is not specified then it defaults to the error limit For example consi
278. piler If you specify the incr option the compiler will automatically determine which modules have changed and generate code only for those modules This is not as efficient as manual incremental compilation because the compiler must scan all of the source code to determine which modules must be compiled The following is an example of how to compile a design with automatic incremental compilation vlog incr top v and2 v or2 v Compiling module top Compiling module and2 Compiling module or2 Top level modules top Now suppose that you modify the functionality of the or2 module vlog incr top v and2 v or2 v Skipping module top Skipping module and2 Compiling module or2 Top level modules top The compiler informs you that it skipped the modules top and and2 and compiled or2 g Automatic incremental compilation is intelligent about when to compile a module For example changing a comment in your source code does not result in a recompile however changing the compiler command line options results in a recompile of all modules gt Note Changes to your source code that do not change functionality but that do affect source code line numbers such as adding a comment line will cause all affected modules to be recompiled This happens because debug information must be kept current so that ModelSim can trace back to the correct areas of the source code ModelSim User s Manual UM 64 5 Verilog
279. points see Setting signal breakpoints UM 160 and the when command CR 181 Source window UM 169 You can enable and disable existing breakpoints by checking or unchecking the box next to the breakpoint s name To add a new file line breakpoint select Add BP or Edit Selected for an existing file line breakpoint Add Edit Breakpoint File Name o Line Condition Instance i itstsi lt s lt lt lt i lt a aa Command s OK Cancel The Add Edit Breakpoint dialog box includes the following options File Name The file name in which you want to set the breakpoint Required The button next to this field allows you to browse to select a file Line The line number on which you want to set the breakpoint Required Condition The condition s that determine whether the breakpoint is hit See the bp command CR 46 for more information on creating the condition statement Instance Specify a region in which the breakpoint should be set If left blank the breakpoint affects every instance in the design Command s One or more commands that you want executed at the breakpoint ModelSim User s Manual UM 170 7 Graphic Interface Editing the source file in the Source window Several toolbar buttons shown above mouse actions and special keystrokes can be used to edit the source file in the Source window See The following mouse actions and special keystrokes can b
280. ppress Warnings Selecting From Synopsys Packages suppresses warnings generated within the accelerated Synopsys std_arith packages Edit the StdArithNoWarnings UM 282 variable in the modelsim ini file to set a permanent default Selecting From IEEE Numeric Std Packages suppresses warnings generated within the accelerated numeric_std and numeric_bit packages Edit the NumericStdNoWarnings UM 282 variable in the modelsim ini file to set a permanent default Default Run Sets the default run length for the current simulation Edit the RunLength UM 282 variable in the modelsim ini file to set a permanent default Iteration Limit Sets a limit on the number of deltas within the same simulation time unit to prevent infinite looping Edit the IterationLimit UM 281 variable in the modelsim ini file to set a permanent iteration limit default Default Force Type Selects the default force type for the current simulation Edit the DefaultForceKind UM 280 variable in the modelsim ini file to set a permanent default Assertion settings tab MELET Options ioj x DDED assets E m Break on Assertion 7 Ignore Assertions For Fatal T Failure Failure T Eror C Eror T Waring C Waring T Note C Note OK Cancel Apply The Assertions tab includes these options e Break on Assertion Selects the assertion severity that will stop simulation Edit the BreakOnAssertion UM 280 variable in the modelsim ini file to set a per
281. preciated ModelSim User s Manual UM 296 C Tips and Techniques Running command line and batch mode simulations ModelSim User s Manual The typical method of running ModelSim is interactive you push buttons and or pull down menus in a series of windows in the GUI graphic user interface But there are really three specific modes of ModelSim operation GUI command line and batch Here are their characteristics GUI mode This is the usual interactive mode it has graphical windows push buttons menus and a command line in the text window This is the default mode Command line mode running vsim exe This an operational mode that has only an interactive command line no interactive windows are opened To run vsim in this manner invoke it with the c option as the first argument from the DOS prompt in Windows 95 98 2000 NT The resulting transcript file is created in such a way that the transcript can be re executed without change if you desire Everything except the explicit commands you enter will begin with a leading comment character Batch mode running vsim exe Batch mode is an operational mode that provides neither an interactive command line nor interactive windows In a Windows environment vsim is run from a Windows 95 98 2000 NT DOS prompt and standard input and output are re directed to and from files An example is C modeltech gt vsim ent arch lt infile gt outfile where infile contains force
282. r file mappings are stored in the project mpf file A Important Due to the significant changes projects created in versions prior to 5 5 cannot be converted automatically If you created a project in an earlier version you will need to recreate it in version 5 5 With the new interface even the most complex project should take less than 15 minutes to recreate Follow the instructions in the ensuing pages to recreate your project ModelSim User s Manual UM 18 2 Projects and system initialization Getting started with projects ModelSim User s Manual This section describes the four basic steps to working with a project For a discussion of more advanced project features see Customizing project settings UM 24 Step 1 Create a new project UM 19 This creates a mpf file and a working library Step 2 Add files to the project UM 21 Projects can reference or include HDL source files and any other files you want to associate with the project You can copy files into the project directory or simply create mappings to files in other locations Step 3 Compile the files UM 22 This checks syntax and semantics and creates the pseudo machine code ModelSim uses for simulation Step 4 Simulate a design UM 23 This specifies the design unit you want to simulate and opens a structure tab in the workspace Getting started with projects UM 19 Step 1 Create a new project 1 Select Create a Project from the
283. r Limit pulse_e notimingchecks User Defined Arguments lt plusarg gt Cancel The Verilog tab includes these options e Delay Selection mindelays typdelays maxdelays Use the drop down menu to select timing for min typ max expressions Pulse Options e Disable pulse error and warning messages no_pulse_msg Disables path pulse error warning messages e Rejection Limit pulse_r lt percent gt Sets the module path pulse rejection limit as a percentage of the path delay e Error Limit pulse_e lt percent gt Sets the module path pulse error limit as a percentage of the path delay ModelSim User s Manual Simulating with the graphic interface UM 223 Other Options Enable Hazard Checking hazards Enables hazard checking in Verilog modules e Disable Timing Checks in Specify Blocks notimingchecks Disables the timing check system tasks setup hold in specify blocks e User Defined Arguments lt plusarg gt Arguments are preceded with making them accessible through the Verilog PLI routine mc_scan_plusargs The values specified in this field must have a preceding them or ModelSim may incorrectly parse them Libraries settings tab l Load Design Desi VHDL Veriog oic SDF Search Libraries L Search Libraries First Lf Load Exit Save Cancel The Libraries tab includes these options e Searc
284. r Microsoft Windows 95 98 Me NT 2000 If the ModelSim software you are using is a later release check the README file that accompanied the software Any supplemental information will be there ModelSim User s Manual UM 12 1 Introduction Standards supported ModelSim VHDL supports both the IEEE 1076 1987 and 1076 1993 VHDL the 1164 1993 Standard Multivalue Logic System for VHDL Interoperability and the 1076 2 1996 Standard VHDL Mathematical Packages standards Any design developed with ModelSim will be compatible with any other VHDL system that is compliant with either IEEE Standard 1076 1987 or 1076 1993 ModelSim Verilog is based on IEEE Std 1364 1995 and a partial implementation of 1364 2001 Standard Hardware Description Language Based on the Verilog Hardware Description Language The Open Verilog International Verilog LRM version 2 0 is also applicable to a large extent Both PLI Programming Language Interface and VCD Value Change Dump are supported for ModelSim PE and SE users In addition all products support SDF 1 0 through 3 0 VITAL 2 2b VITAL 95 IEEE 1076 4 1995 and VITAL 2000 Assumptions Sections in ModelSim User s Manual We assume that you are familiar with the use of your operating system If you are not familiar with Microsoft Windows we recommend that you work through the tutorials provided with MS Windows before using ModelSim We also assume that you have a working knowledge of VHDL and Veril
285. raries and SDF allow you to select various simulation options You can switch between tabs to modify settings then begin simulation by selecting the Load button If you select Cancel all selections remain unchanged and you are returned to the Main window the Exit button only active before simulation closes ModelSim The Save Settings button allows you to save the preferences on all tabs to a DO macro file Compile before you simulate To begin simulation you must have compiled design units located in a design library see Creating a design library UM 45 gt Note Many of the dialog box options discussed in this section include parenthetical elements that correspond to vsim CR 168 command options For example Simulator Resolution time lt multiplier gt lt time_unit gt ModelSim User s Manual UM 218 7 Graphic Interface Design selection tab Load Design Desan VHDL Vaiiog Lives SOF Library work M counter M test_counter Simulate Simulator Resolution add default P gt Note The Exit button closes the Load Design dialog box and quits ModelSim The Design tab includes these options e Library Specifies a library to view Make certain your selection is a valid ModelSim library the library must be created by ModelSim and it s directory must include a _info file e Design Unit This hierarchical list allows you to select one top level entity or configuration to be
286. rary compiler options See Verilog XL uselib compiler directive UM 67 for details The following Verilog XL compiler directives are silently ignored by ModelSim Verilog Many of these directives are irrelevant to ModelSim Verilog but may appear in code being ported from Verilog XL accelerate autoexpand_vectornets disable_portfaults enable_portfaults endprotect expand_vectornets noaccelerate noexpand_vectornets noremove_gatenames noremove_netnames nosuppress_faults protect remove_gatenames remove_netnames suppress_faults The following Verilog XL compiler directives produce warning messages in ModelSim Verilog These are not implemented in ModelSim Verilog and any code containing these directives may behave differently in ModelSim Verilog than in Verilog XL default_trireg_strength signed unsigned ModelSim User s Manual UM 86 5 Verilog Simulation Verilog PLI VPI The Verilog PLI Programming Language Interface and VPI Verilog Procedural Interface both provide a mechanism for defining system tasks and functions that communicate with the simulator through a C procedural interface There are many third party applications available that interface to Verilog simulators through the PLI see Third party PLI applications UM 95 In addition you may write your own PLI VPI applications ModelSim Verilog implements the PLI as defined in the IEEE Std 1364 with the exception of th
287. reset 0 force clk 0 0 1 50 rep 100 run 10000 Source code security and nodebug UM 297 Source code security and nodebug The nodebug option on both vcom CR 129 and vlog CR 162 hides internal model data This allows a model supplier to provide pre compiled libraries without providing source code and without revealing internal model variables and structure gt Note ModelSim s nodebug compiler option provides protection for proprietary model information The Verilog protect compiler directive provides similar protection but uses a Cadence encryption algorithm that is unavailable to Model Technology If a design unit is compiled with nodebug the Source window will not display the design unit s source code the Structure window will not display the internal structure the Signals window will not display internal signals it still displays ports the Process window will not display internal processes and the Variables window will not display internal variables In addition none of the hidden objects may be accessed through the Dataflow window or with ModelSim commands Even with the data hiding of nodebug there remains some visibility into models compiled with nodebug The names of all design units comprising your model are visible in the library and you may invoke vsim CR 168 directly on any of these design units and see the ports For this reason it is important to compile all design units with nodebug Design units or
288. rmation about view the readme file pertaining to ModelSim s online Help documentation Documentation open and read ModelSim documentation in PDF or HTML format PDF files can be read with a free Adobe Acrobat reader available on the ModelSim installation CD or from www adobe com Tcl Help open the Tcl command reference man pages in Windows help format Tcl Syntax open Tcl syntax details in HTML format Tcl Man Pages open the Tcl Tk 8 0 manual in HTML format Technotes select a technical note to view from the drop down list ModelSim User s Manual Main window UM 131 The Main window toolbar Buttons on the Main window toolbar give you quick access to these ModelSim commands and functions l ModelSim File Edit Design View Project Run Compare Macro Options Window Help EEI ane RK xO S lt Q A amp s Ss ss S amp ae S r amp we S E PY Main window toolbar buttons Button Menu equivalent Command equivalents Compile Design gt Compile also vcom lt arguments gt or ds open the Compile HDL Source Options gt Compile vlog lt arguments gt Files dialog box to select files for opens the Compile compilation Options dialog box see vcom CR 129 or vlog CR 162 Load Design Design gt Load Design vsim lt arguments gt 5 open the Load Design dialog box to initiate simulation see vsim CR 168 Copy Edit gt Copy see Mouse and keyboard copy the selected text within the shortcuts UM 133
289. ros UM 253 Tcl features within ModelSim UM 254 Tcl References UM 254 Tcl commands UM 255 Tcl command syntax UM 256 if command syntax UM 258 set command syntax UM 259 Command substitution UM 259 Command separator UM 260 Multiple line commands UM 260 Evaluation order ere UM 260 Tcl relational expression evaluation UM 260 Variable substitution UM 261 System commands UM 261 List processing UM 262 ModelSim Tcl commands UM 262 ModelSim Tcl time commands UM 263 Conversions UM 263 Relations UM 263 Arithmetic UM 264 Tclexamples UM 265 Example 2 UM 266 Macros DO files UM 269 ModelSim User s Manual UM 9 Using Parameters with DO files 2 2 a ee 2 UM 269 A ModelSim Variables UM 273 Variable settings report UM 274 Personal preferences UM 274 Returning to the original ModelSim defaults UM 274 Environment variables eRe eR a UM 275 Creating environment variables in Windows UM 276 Referencing environment variables within ModelSim UM 277 Removing temp files VSOUT UM 277 Preference variables located in INI files UM 278 Library library path variables UM 278 vcom VHDL compiler control variables UM 278 vlog Verilog compiler control variables UM 279 vsim simulator control variables UM 280 Setting variables in INI files UM 283 Commonly used INI variables UM 284 Preference variables located in Tcl files UM 287 User defined variables UM 287 More preferences UM 28
290. rrent working library By default this is the library named work To change the current working library you can use vcom work and specify the name of the desired target library Predefined libraries ModelSim User s Manual Certain resource libraries are predefined in standard VHDL The library named std contains the packages standard and textio which should not be modified The contents of these packages and other aspects of the predefined language environment are documented in the IEEE Standard VHDL Language Reference Manual Std 1076 1987 and ANSI IEEE Std 1076 1993 See also Using the TextIO package UM 47 A VHDL use clause can be used to select specific declarations in a library or package that are to be visible within a design unit during compilation A use clause references the compiled version of the package not the source By default every design unit is assumed to contain the following declarations LIBRARY std work USE std standard all To specify that all declarations in a library or package can be referenced you can add the suffix all to the library package name For example the use clause above specifies that all declarations in the package standard in the design library named std are to be visible to the VHDL design file in which the use clause is placed Other libraries or packages are not visible unless they are explicitly specified using a library or use clause Another predefined library is work the libr
291. rs to objects that naturally exist in the simulation data structures and the handles to these objects are valid throughout the simulation even after the acc_close routine is called However some of the objects are created on demand and the handles to these objects become invalid after acc_close is called The following object types are created on demand in ModelSim Verilog accOperator acc_handle_condition accWirePath acc_handle_path accTerminal acc_handle_terminal acc_next_cell_load acc_next_driver and acc_next_load accPathTerminal acc_next_input and acc_next_output accTchkTerminal acc_handle_tchkargl and acc_handle_tchkarg2 accPartSelect acc_handle_conn acc_handle_pathin and acc_handle_pathout accRegBit acc_handle_by_name acc_handle_tfarg and acc_handle_itfarg If your PLI application uses these types of objects then it is important to call acc_close to free the memory allocated for these objects when the application is done using them If your PLI application places value change callbacks on accRegBit or accTerminal objects do not call acc_close while these callbacks are in effect ModelSim User s Manual Verilog PLIVPI UM 95 Third party PLI applications Many third party PLI applications come with instructions on using them with ModelSim Verilog Even without the instructions it is still likely that you can get it to work with ModelSim Verilog as long as the application uses standard PLI routine
292. rting with analog step the top clk signal has been relabeled to illustrate each different wave format wave default SE File Edit Cursor Zoom Compare Bookmark Format Window SHa tae RK Lyi QAQQ Q top clk analog step analog interpolated analog backstep literal logic event Ons to 306 ns Analog Step Displays a waveform in step style Analog Interpolated Displays the waveform in interpolated style Analog Backstep Displays the waveform in backstep style Often used for power calculations Offset and Scale Allows you to adjust the scale of the item as it is seen on the display Offset is the number of pixels offset from zero The scale factor reduces if less than 1 or increases if greater than 1 the number of pixels displayed Only the following types are supported in Analog format VHDL types All vectors std logic vectors bit vectors and vectors derived from these types Scalar integers Scalar reals Scalar time Verilog types All vectors Scalar real Scalar integers ModelSim User s Manual UM 196 7 Graphic Interface e Height Allows you to specify the height in pixels of the waveform Signal Properties The Compare tab includes the same options as those in the Add Signal Options dialog box see Adding Signals Regions and or Clocks UM 267 ModelSim User s Manual Wave window UM 197 Setting Wave window display properties Y
293. rtup_routines table will be defined As aresult when PLI and VPI applications exist in the same application object file they must be registered in the same manner VPI registration functions that would normally be listed in a vlog_startup_routines table can be called from an init_usertfs function instead Compiling and linking PLI VPI applications ModelSim Verilog uses operating system calls to dynamically load PLI and VPI applications when the simulator loads a design Therefore the applications must be compiled and linked for dynamic loading on a specific operating system The PLI VPI routines are declared in the include files located in the ModelSim lt install_dir gt modeltech include directory The acc_user h file declares the ACC routines the veriuser h file declares the TF routines and the vpi_user h file declares the VPI routines The following instructions assume that the PLI or VPI application is in a single source file For multiple source files compile each file as specified in the instructions and link all of the resulting object files together with the specified link instructions Windows 95 98 2000 NT Me platforms Under Windows ModelSim loads a 32 bit dynamically linked library for each PLI VPI application The following compile and link steps are used to create the necessary dll file and other supporting files using the Microsoft Visual C C compiler cl c I lt install_dir gt modeltech include app c link dll exp
294. s The following guidelines are for preparing a Verilog XL PLI application to work with ModelSim Verilog Generally a Verilog XL PLI application comes with a collection of object files and a veriuser c file The veriuser c file contains the registration information as described above in Registering PLI applications To prepare the application for ModelSim Verilog you must compile the veriuser c file and link it to the object files to create a dynamically loadable object see Compiling and linking PLI VPI applications UM 89 For example if you have a veriuser c file and a library archive libapp a file that contains the application s object files then the following commands should be used to create a dynamically loadable object for the Solaris operating system cc c I lt install_dir gt modeltech include veriuser c ld G o app sl veriuser o libapp a That s all there is to it The PLI application is ready to be run with ModelSim Verilog All that s left is to specify the resulting object file to the simulator for loading using the Veriuser modesim ini file entry the pli simulator option or the PLIOBJS environment variable see Registering PLI applications UM 86 gt Note On the HP700 platform the object files must be compiled as position independent code by using the z compiler option Since the object files supplied for Verilog XL may be compiled for static linking you may not be able to use the object files to cre
295. s pref_variables frameset htm ModelSim User s Manual UM 300 C Tips and Techniques Performance affected by scheduled events being cancelled Performance will suffer if events are scheduled far into the future but then cancelled before they take effect This situation will act like a memory leak and slow down simulation In VHDL this situation can occur several ways The most common are waits with time out clauses and projected wave forms in signal assignments The following code shows a wait with a time out Signals synch bit lt 0 p process begin wait for 10 ms until synch 1 end process synch lt not synch after 10 ns At time 0 p makes an event for time 10ms When synch goes to 1 at 10 ns the event at 10 ms is marked as cancelled but not deleted and a new event is scheduled at 10ms 10ns The cancelled events are not reclaimed until time 10ms is reached and the cancelled event is processed As a result there will be 500000 10ms 20ns cancelled but undeleted events Once 10ms is reached memory will no longer increase because we will be reclaiming events as fast as we add them For projected wave forms the following would behave the same way signals synch bit 0 p process synch begin output lt 0 1 after 10ms end process synch lt not synch after 10 ns ModelSim User s Manual Modeling memory in VHDL UM 301 Modeling memory in VHDL As a VHDL user you might be
296. s the WLF file by size as closely as possible to the specified amount of time If both time and size limits are specified the most restrictive is used Setting it to 0 results in no limit Edit the WLFTimeLimit UM 283 variable in the modelsim ini file to set a permanent default ModelSim User s Manual Simulating with the graphic interface UM 229 e Compress WLF data Compresses WLF files to reduce their size You would typically only disable compression for troubleshooting purposes Edit the WLFCompress UM 283 variable in the modelsim ini file to set a permanent default Delete WLF file on exit Specifies whether the WLF file should be deleted when the simulation ends Edit the WLFDeleteOnQuit UM 283 variable in the modelsim ini file to set a permanent default e Design Hierarchy Specifies whether to save all design hierarchy in the WLF file or only regions containing logged signals Edit the WLFSaveAllRegions UM 283 variable in the modelsim ini file to set a permanent default ModelSim User s Manual UM 230 7 Graphic Interface ModelSim tools e The GUI Expression Builder UM 230 Edit gt Search gt Search for Expression gt Builder List or Wave window Helps you build logical expressions for use in Wave and List window searches and several simulator commands For expression format syntax see GUI_expression_format CR 16 The GUI Expression Builder ModelSim User s Manual The GUI Expression Builder is a
297. s to manage multiple wave files Source this file from the command line or as a startup script source lt path gt wave_mgr tcl add_wave_buttons Add wave management buttons to the main toolbar new save and load new_wave Dialog box creates a new wave window with the user provided name mnamed_wave lt name gt Creates a new wave window with the specified title save_wave lt file root gt Saves name window location and contents for all open wave windows Creates lt file root gt lt n gt do file for each window where lt n gt is 1 to the number of windows Default file root is wave Also creates windowSet do file that contains title and geometry info load_wave lt file root gt Opens and loads wave windows for all files matching lt file root gt lt n gt do where lt n gt are the numbers from 1 9 Default lt file root gt is wave Also runs windowSet do file if it exists Tcl examples UM 267 Add wave management buttons to the main toolbar proc add_wave_buttons _add_menu main controls right SystemMenu SystemWindowFrame Load Waves load_wave _add_menu main controls right SystemMenu SystemWindowFrame Save Waves save_wave _add_menu main controls right SystemMenu SystemWindowFrame New Wave new_wave Simple Dialog requests name of new wave window Defaults to Wave lt n gt proc new_wave global dialog_prompt vsimPriv set defaultName Wave
298. s to store compilation results You may find it convenient to use these options if you are porting a design to ModelSim or if you are familiar with these options and prefer to use them Source libraries are searched after the source files on the command line are compiled If there are any unresolved references to modules or UDPs then the compiler searches the source libraries to satisfy them The modules compiled from source libraries may in turn have additional unresolved references that cause the source libraries to be searched again This process is repeated until all references are resolved or until no new unresolved references are found Source libraries are searched in the order they appear on the command line v lt filename gt This option specifies a source library file containing module and UDP definitions Modules and UDPs within the file are compiled only if they match previously unresolved references Multiple v options are allowed y lt directory gt This option specifies a source library directory containing module and UDP definitions Files within this directory are compiled only if the file names match the names of previously unresolved references Multiple y options are allowed libext lt suffix gt This option works in conjunction with the y option It specifies file extensions for the files in a source library directory By default the compiler searches for files without extensions If you specify the libext option t
299. selected Where The printer port for the selected printer Comment The printer comment from the printer properties dialog box Print to file Make this selection to print the waveform to a file instead of a printer The printer driver determines what type of file is created Postscript printers create a Postscript ps file non Postscript printers create a prn or printer control language file To create an encapsulated Postscript file eps use the File gt Print Postscript menu selection Signal Selection e All signals Print all signals e Current View Print signals in current view e Selected Print all selected signals Time Range e Full Range Print all specified signals in the full simulation range e Current view Print the specified signals for the viewable time range e Custom Print the specified signals for a user designated From and To time Setup button See Printer Page Setup UM 209 Wave window UM 209 Printer Page Setup Clicking the Setup button in the Write Postscript or Print dialog box allows you to define the following options this is the same dialog that opens via File gt Page setup Page Setup Paper Margins Paper size Top fos fu tt u aail g Bottom 0 5 Width bs Let fos Height 11 0 Right fos f e 4j SEL m Label width Cursors Grid Color Color Auto Adjust Off C Off C Grayscale C Fixed width j5 inches C On On
300. set command syntax UM 259 Command substitution UM 260 Command separator UM 260 Multiple line commands UM 260 Evaluation order s i UM 260 Tcl relational expression evaluation UM 260 Variable substitution UM 261 System commands UM 261 List processing UM 262 ModelSim Tcl commands UM 262 ModelSim Tcl time commands UM 263 Tcl examples UM 265 Macros DO files UM 269 This chapter provides an overview of Tcl tool command language as used with ModelSim Macros in ModelSim are simply Tcl scripts that contain ModelSim and optionally Tcl commands Tcl is a scripting language for controlling and extending ModelSim Within ModelSim you can develop implementations from Tcl scripts without the use of C code Because Tcl is interpreted development is rapid you can generate and execute Tcl scripts on the fly without stopping to recompile or restart ModelSim In addition if ModelSim does not provide the command you need you can use Tcl to create your own commands ModelSim User s Manual UM 254 10 Tcl and macros Tcl features within ModelSim Using Tcl with ModelSim gives you these features e command history like that in C shells full expression evaluation and support for all C language operators a full range of math and trig functions support of lists and arrays regular expression pattern matching procedures the ability to define your own commands command substitution that is commands may be nested r
301. sor location Check the Regular expression checkbox if you are using regular expressions T Regular expression Source window UM 171 Setting tab stops in the Source window You can set tab stops in the Source window by selecting the Main window Options gt Edit Preferences command Follow these steps 1 Select the By Names tab 2 Select Source in the first column and then select the tabs item in the second column 3 Press the Change Value button 4 In the dialog that appears enter a single number n which sets a tab stop every n characters where a character width is the width of the 8 character or Enter a list of screen distances for the tab stops For instance 21 49 77 105 133 161 189 217 245 273 301 329 357 385 413 441 469 The number 21 or 21p means 21 pixels the number 3c means three centimeters the number 1i means one inch A Important Do not use quotes or braces in the list i e 21 49 or 21 49 This will cause the GUI to hang You can also set tab stops using the PrefSource tabs Tcl preference variable ModelSim User s Manual UM 172 7 Graphic Interface Structure window ModelSim User s Manual gt Note In ModelSim versions 5 5 and later the information contained in the Structure window is shown in the structure tabs of the Main window Workspace UM 124 The Structure window will not display by default You can display the Structure window at any time by selecting View gt
302. splay all values for the next say 10 ns after the rising edge of enable then set the On Duration value to 10 ns Otherwise leave it at zero and select Apply again When everything is correct click OK to close the Modify Display Properties dialog box When you save the List window configuration the list gating parameters will be saved as well and can be set up again by reading in that macro You can take a look at the macro to see how the gating can be set up using macro commands Index UM 307 CR Command Reference UM User s Manual Symbols delay_mode_distributed UM 65 delay_mode_path UM 65 delay_mode_unit UM 65 delay_mode_zero UM 65 incdir UM 65 libext UM 66 librescan UM 66 maxdelays UM 65 mindelays UM 65 nolibcell UM 67 nowarn UM 66 typdelays UM 65 So shared object file loading PLI VPI applications UM 89 define UM 65 delayed CR 21 A abort command CR 31 Absolute time CR 14 ACC routines UM 97 Accelerated packages UM 41 add list command CR 32 add wave command CR 35 alias command CR 39 architecture simulator state variable UM 289 argc simulator state variable UM 289 Arrays indexes CR 11 slices CR 11 AssertFile ini file variable UM 280 AssertionFormat ini file variable UM 280 Assertions selecting severity that stops simulation UM 227 B Bad magic number error message UM 104 balloon dialog toggling on off UM 198 Base radix specifying in List window UM 146 batch_mode command
303. ssed in the current time resolution e g 1000 ns returns the current simulation time as an absolute number of time steps e g 1000 resolution returns the current simulation time resolution Referencing simulator state variables Variable values may be referenced in simulator commands by preceding the variable name with a sign For example to use the now and resolution variables in an echo command type echo The time is now resolution Depending on the current simulator state this command could result in The time is 12390 10ps If you do not want the dollar sign to denote a simulator variable precede it with a For example now will not be interpreted as the current simulator time ModelSim User s Manual UM 290 A ModelSim Variables Special considerations for now ModelSim User s Manual The now variable is set within ModelSim by a procedure that converts the current simulator time to user time units as specified in the t argument to vsim command CR 168 When no multiplier is specified with the time unit e g 1ps the procedure formats now without a time unit For example ModelSim gt vsim t lps VSIM gt echo Snow 0 However when a multiplier is specified e g 10ps it s difficult to know how it should behave for a given simulation time For example if the current simulation time is 500ps and resolution is 10ps should now be 50 or 500 or 500ps To remove any
304. statement accForeign accShadow foreign scope created by mti_CreateRegion accGenerate accGenerate generate statement accPackage accPackage package declaration accSignal accSignal signal declaration The type and fulltype constants for VHDL objects are defined in the acc_vhdl h include file All of these objects except signals are scope objects that define levels of hierarchy in the Structure window Currently the PLI ACC interface has no provision for obtaining handles to generics types constants variables attributes subprograms and processes ModelSim User s Manual IEEE Std 1364 ACC routines Verilog PLIVPI UM 97 ModelSim Verilog supports the following ACC routines described in detail in the IEEE Std 1364 acc_append_delays acc_append_pulsere acc_close acc_collect acc_compare_handles acc_configure acc_count acc_fetch_arge acc_fetch_argv acc_fetch_attribute acc_fetch_attribute_int acc_fetch_attribute_str acc_fetch_defname acc_fetch_delay_mode acc_fetch_delays acc_fetch_direction acc_fetch_edge acc_fetch_ fullname acc_fetch_fulltype acc_fetch_index acc_fetch_location acc_fetch_name acc_fetch_paramtype acc_fetch_paramval acc_fetch_polarity acc_fetch_precision acc_fetch_pulsere acc_fetch_range acc_fetch_size acc_fetch_tfarg acc_fetch_itfarg acc_fetch_tfarg_int a
305. ste command without having to delete the old value Structure Signals Variables and Wave windows Cut Copy Paste Delete Select All Dialog boxes will appear on top of their parent window instead of the upper left corner of the screen The Main window includes context menus that are accessed by clicking the right mouse button The middle mouse button will allow you to paste the following into the transcript window text currently selected in the transcript window a current primary X Windows selection can be from another application or contents of the clipboard Find Breakpoint s Transcript window context menu gt Note Selecting text in the transcript window makes it the current primary X Windows selection This way you can copy transcript window selections to other X Windows windows xterm emacs etc ModelSim User s Manual UM 118 7 Graphic Interface e The Edit gt Paste operation in the transcript window will ONLY paste from the clipboard e All menus highlight their accelerator keys Quick access toolbars TTT sob File Edit Cursor Zoom Compare Bookmark Format Window oH 28 RK tyi AIAR iE ELEVEN iaie le 9 i Buttons on the Main Source and Wave windows provide access to commonly used commands and functions See The Main window toolbar UM 131 The Source window toolbar UM 166 and The Wave window toolbar UM 186 Drag and Drop
306. step analog interpolated analog backstep literal logic and event formats Each signal can be formatted individually The default format is logic If you rest your mouse pointer on a signal in the waveform pane a popup displays with information about the signal You can toggle this popup on and off in the Wave Window Properties dialog see Setting Wave window display properties UM 197 O00 oOgo0000 on000001 00000010 oooonoTy Li ee oe ee SS a ee aoe el es sim top paddr 695 ns oooo00011 cursors Waveform popup ModelSim User s Manual UM 180 7 Graphic Interface Cursor panes There are two cursor panes The left pane shows the current simulation time and the value for each cursor The top most value is the current simulation time The selected cursor s value is highlighted You can select a cursor by selecting its value in the left pane The right pane shows the absolute time value for each cursor and relative time between cursors Up to 20 cursors can be displayed two cursor panes HDL items you can view ModelSim User s Manual VHDL items indicated by a dark blue square ftop clk signals and process variables top pry top pstrb Verilog items top prdy indicated by a light blue circle top paddr nets register variables and named top pdata events ftop srw top sstrb Virtual items ftop srdy indicated by an orange diamond top saddr virtual signals buses and functi
307. strations File Edit Markers Prop Window The divider bar separates time and 2 gaap top paddr y a a top sadd gt delta from values delta top prw top stw y signal values are top pstb 4 top sstb 5 P top prd top std listed in symbolic val di Ti dela Td ieee ai 500 0 1 01 1 00000010 0000000000000010 O O 1 00000010 Z nowiine 505 0 1 0 1 1 00000010 0000000000000010 0 1 1 00000010 Of 520 0 001 1 00000010 0000000000000010 0 1 1 00000010 Of 540 0 1 0 1 1 00000010 0000000000000010 0 1 1 00000010 OF 560 0 0011 00000010 0000000000000010 O 1 1 00000010 OC 580 0 1 011 00000010 0000000000000010 0 1 1 00000010 oF 585 0 1 011 00000010 ooooo00000000010 O 1 0 00000010 oF 590 0 1 0 1 0 00000010 0000000000000010 O 1 0 00000010 OC 600 0 0 01 0 00000010 oooooooo00000010 O 1 0 00000010 OC PS list EE File Edit Markers Prop Window ns eae ee top sdata op prw 4 op siw 4 Signal values are ftop pstb top sstb 4 listed in decimal top prdy top stdy format top paddr top saddr 500 0 UW e SAMI MO ee Z 505 0 Wa 2 a 2 2 520 0 anaa e eaa 4 2 540 0 Um 2 sA 2 2 560 0 Hi yy 2 2 I A 2 580 0 Ula Aq E 2 585 0 U Waa e 2010 2 2 Aon 0 SAnS a eee 2 In the first List window the HDL items are formatted as symbolic and use an item change to trigger a line the field width was changed to accommodate the default label width The window divider maintains the time and delta in the left pane signals
308. t an item in the Structure window UM 172 or use the File gt Open command Source window to add a file to the window Your source code can remain hidden if you wish see Source code security and nodebug UM 297 The window is divided into two panes the left hand pane contains line numbers and the right hand pane contains the source file The pathname of the source file is indicated in the header of the Source window As shown in the picture below you may also see the following in the left hand pane e Green line numbers denote executable lines e Blue arrow denotes a process that you have selected in the Process window UM 152 e Red circles denote file line breakpoints hollow circles denote breakpoints that are currently disabled fi source counter yhd lel FS File Edit Object Options Window oH BAA OO end increment begin ctr process clk reset begin if reset l then if reset event then count lt others gt 0O after tpd_reset_to_ count end if elsif clk event and clk 1 then count lt increment count after tpd_ clk to_count end if end process If you hold your mouse pointer over an HDL item in the right hand pane a pop up will show you the full pathname of the item and its current value ModelSim User s Manual UM 164 7 Graphic Interface The Source window menu bar ModelSim User s Manual The following menu commands are available from the Source window me
309. t help you find the event order dependencies but it allows you to ignore them Keep in mind that this option does not account for all event order discrepancies and that using this option may degrade performance hazards This option detects event order hazards involving simultaneous reading and writing of the same register in concurrently executing processes vsim CR 168 detects the following kinds of hazards WRITE WRITE Two processes writing to the same variable at the same time READ WRITE One process reading a variable at the same time it is being written to by another process ModelSim calls this a READ WRITE hazard if it executed the read first WRITE READ Same as a READ WRITE hazard except that ModelSim executed the write first vsim CR 168 issues an error message when it detects a hazard The message pinpoints the variable and the two processes involved You can have the simulator break on the statement where the hazard is detected by setting the break on assertion level to error To enable hazard detection you must invoke vlog CR 162 with the hazards option when you compile your source code and you must also invoke vsim with the hazards option when you simulate Limitations of hazard detection e Reads and writes involving bit and part selects of vectors are not considered for hazard detection The overhead of tracking the overlap between the bit and part selects is too high e A WRITE WRITE hazard is flagged
310. t order dependencies is ambiguous and should be corrected For example the following code is ambiguous module top reg r initial r 0 initial r 1 initial 10 Sdisplay r endmodule The value displayed for r depends on the order that the simulator executes the initial constructs that assign to r Conceptually the initial constructs run concurrently and the simulator is allowed to execute them in any order ModelSim Verilog executes the initial constructs in the order they appear in the module and the value displayed for r is 1 Verilog XL produces the same result but a simulator that displays 0 is not incorrect because the code is ambiguous Since many models have been developed on Verilog XL ModelSim Verilog duplicates Verilog XL event ordering as much as possible to ease the porting of those models to ModelSim Verilog However ModelSim Verilog does not match Verilog XL event ordering in all cases and if a model ported to ModelSim Verilog does not behave as expected then you should suspect that there are event order dependencies Simulation UM 71 Tracking down event order dependencies is a tedious task so ModelSim Verilog aids you with a couple of compiler options compat This option turns off optimizations that result in different event ordering than Verilog XL ModelSim Verilog generally duplicates Verilog XL event ordering but there are cases where it is inefficient to do so Using this option does no
311. t switch for the vcom command CR 129 Edit the Quiet UM 279 variable in the modelsim ini file to set a permanent default Show source lines with errors Causes the compiler to display the relevant lines of code in the transcript Same as the source switch for the vcom command CR 129 Edit the Show_source UM 279 variable in the modelsim ini file to set a permanent default Flag Warnings on Unbound Component Flags any component instantiation in the VHDL source code that has no matching entity in a library that is referenced in the source code either directly or indirectly Edit the Show_Warning1 UM 279 variable in the modelsim ini file to set a permanent default Process without a WAIT statement Flags any process that does not contain a wait statement or a sensitivity list Edit the Show_Warning2 UM 279 variable in the modelsim ini file to set a permanent default Null Range Flags any null range such as 0 down to 4 Edit the Show_Warning3 UM 279 variable in the modelsim ini file to set a permanent default No space in time literal e g 5ns Flags any time literal that is missing a space between the number and the time unit Edit the Show_Warning4 UM 279 variable in the modelsim ini file to set a permanent default Multiple drivers on unresolved signals Flags any unresolved signals that have multiple drivers Edit the Show_Warning5 UM 279 variable in the modelsim ini file to set a permanent default Check for
312. ta_event for the hold check and the clk_event for the setup check This alternate method of conditioning precludes specifying conditions in the clk_event and data_event arguments The delayed_clk argument is a net that is continuously assigned the value of the net specified in the clk_event The delay is non zero if the setup_limit is negative zero otherwise The delayed_data argument is a net that is continuously assigned the value of the net specified in the data_event The delay is non zero if the hold_limit is negative zero otherwise The delayed_clk and delayed_data arguments are provided to ease the modeling of devices that may have negative timing constraints The model s logic should reference the delayed_clk and delayed_data nets in place of the normal clk and data nets This ensures that the correct data is latched in the presence of negative constraints The simulator automatically calculates the delays for delayed_clk and delayed_data such that the correct data is latched as long as a timing constraint has not been violated System Tasks UM 81 The following system tasks are Verilog XL system tasks that are not implemented in ModelSim Verilog but have equivalent simulator commands Sinput filename This system task reads commands from the specified filename The equivalent simulator command is do lt filename gt Slist hierarchical_name This system task lists the source code for the specified scope The equivalent f
313. taflow window as a Postscript file List window HDL items you can view The List window menu bar i Setting List window display properties Adding HDL items to the List window Editing and formatting HDL items in the List wios r Examining simulation results with the List window Finding items by name in the List window Setting time markers in the List window List window keyboard shortcuts Saving List window data to a file Process window The Process window menu Signals window The Signals window menu bes Selecting HDL item types to view Forcing signal and net values Adding HDL items to the Wave and Lies nanos ora WLF file Finding HDL items in the Signals window Setting signal breakpoints Defining clock signals Source window The Source window menu sbat The Source window toolbar Setting file line breakpoints Editing the source file in the Source window Checking HDL item values and descriptions Finding and replacing in the Source window Setting tab stops in the Source window Structure window The Structure window menu ibat Finding items in the Structure window Variables window ModelSim User s Manual segogqgqcgqcgcsg qosgogcggcggcgcgcsc 4 JM 120 JM 121 JM 121 aed lt jmi N es M 124 M 125 M 126 M 131 M 133 M 133 JM 135 JM 135 JM 136 JM 137 JM 138 JM 139 M 139 M 140 M 142 M 144 M 145 M 148 M 149 M 149 M 150 M 150 M 152
314. tance label is dut For either testbench an appropriate simulator invocation might be vsim sdfmax testbench dut myasic sdf testbench Optionally you can leave off the name of the top level vsim sdfmax dut myasic sdf testbench The important thing is to select the instance for which the SDF is intended If the model is deep within the design hierarchy an easy way to find the instance name is to first invoke the simulator without SDF options open the structure window navigate to the model instance select it and enter the environment command CR 70 This command displays the instance name that should be used in the SDF command line option ModelSim User s Manual UM 246 8 Standard Delay Format SDF Timing Annotation Mistaking a component or module name for an instance label Another common error is to specify the component or module name rather than the instance label For example the following invocation is wrong for the above testbenches vsim sdfmax testbench myasic myasic sdf testbench This results in the following error message ERROR myasic sdf The design does not have an instance named testbench myasic Forgetting to specify the instance If you leave off the instance altogether then the simulator issues a message for each instance path in the SDF that is not found in the design For example vsim sdfmax myasic sdf testbench Results in ERROR myasic sdf Failed to find INSTANCE testbenc
315. te variables Variables that provide feedback on the state of the current simulation ModelSim User s Manual UM 274 A ModelSim Variables Variable settings report The report command CR 102 returns a list of current settings for either the simulator state or simulator control variables Use the following commands at either the ModelSim or VSIM prompt report simulator state report simulator control Personal preferences There are several preferences stored by ModelSim on a personal basis independent of modelsim ini or modelsim tcl files These preferences are stored in the Windows Registry under HKEY_CURRENT_USER Software Model Technology Incorporated ModelSim cwd History of the last five working directories pwd This history appears in the Main window File menu e phst Project History pinit Project Initialization state one of Welcome OpenLast NoWelcome This determines whether the Welcome To ModelSim dialog box appears when you invoke the tool printersetup All setup parameters related to Printing i e current printer etc The HKEY_CURRENT_USER key is unique for each user Login on Windows NT Returning to the original ModelSim defaults ModelSim User s Manual If you would like to return ModelSim s interface to its original state simply rename or delete the existing modelsim tcl and modelsim ini files ModelSim will use pref tcl for GUI preferences and make a copy of lt install_dir gt mode
316. tements and a second file that is a Verilog module You would want to compile these two files at the same time To group files follow these steps 1 Right click in an empty area of the Project tab and select Sort by Compile Order 2 Select the files you want to group 3 Right click one of the selected files and select Group Customizing project settings UM 25 Setting compiler options The VHDL and Verilog compilers vcom and vlog respectively have numerous options that affect how a design is compiled and subsequently simulated Outside of a project you can set the defaults for all future simulations using the Options gt Compile Main window command Inside of a project you can set these options on individual files or a group of files To set the compiler options in a project select the file s in the Project tab right click on the file names and select Properties The resulting dialog varies depending on the number and type of files you have selected If you select a single VHDL or Verilog file you ll see the General tab and the VHDL or Verilog tab respectively On the General tab you ll see file properties such as Type Path and Size If you select multiple files the file properties on the General tab are not listed Finally if you select both a VHDL file and a Verilog file you ll see all three tabs but no file information on the General tab Project Compiler Settings m Project Properties J Exclude File from Bu
317. the compiler for each type declaration on 1 IgnoreVitalErrors if 1 ignores VITAL compliance checking errors off 0 NoCaseStaticError if 1 changes case statement static errors to warnings off 0 NoDebug if 1 turns off inclusion of debugging info within design units off 0 NoOthersStaticError if 1 disables errors caused by aggregates that are not locally static off 0 NoVital if 1 turns off acceleration of the VITAL packages off 0 NoVitalCheck if 1 turns off VITAL compliance checking off 0 Optimize_1164 if 0 turns off optimization for IEEE std_logic_1164 package on 1 Quiet if 1 turns off loading messages off 0 RequireConfigForAlIDefault Binding if 1 instructs the compiler not to generate a default binding during compilation off 0 Show_source if 1 shows source line containing error off 0 Show_VitalChecks Warnings if 0 turns off VITAL compliance check warnings on 1 Show_Warning 1 if 0 turns off unbound component warnings on 1 Show_Warning2 if 0 turns off process without a wait statement warnings on 1 Show_Warning3 if 0 turns off null range warnings on 1 Show_Warning4 if 0 turns off no space in time literal warnings on 1 Show_WarningS if 0 turns off multiple drivers on unresolved signal warnings on 1 VHDL93 0 1 i
318. time UM 57 convert time to real UM 56 cursors link to Dataflow window UM 135 Wave window UM 200 Customizing via preference variables UM 287 D dataset alias command CR 54 Dataset Browser UM 108 dataset clear command CR 55 dataset close command CR 56 dataset info command CR 57 dataset list command CR 58 dataset open command CR 59 dataset rename command CR 60 datasets UM 103 managing UM 108 restrict dataset prefix display UM 109 simulator time resolution UM 104 specifying with the environment command CR 70 DatasetSeparator ini file variable UM 280 Declarations hiding implicit with explicit declarations CR 133 Default compile options UM 213 Default editor changing UM 275 DefaultForceKind ini file variable UM 280 DefaultRadix ini file variable UM 281 DefaultRestartOptions variable UM 281 UM 286 Defaults restoring UM 274 window arrangement UM 120 Delay detecting infinite zero delay loops UM 299 interconnect CR 171 CR 175 UM 72 modes for Verilog models UM 75 SDF files UM 233 specifying stimulus delay UM 159 DelayFileOpen ini file variable UM 281 delete command CR 61 deleting library contents UM 34 Delta collapse deltas in the List window UM 143 hide deltas in the List window CR 52 UM 143 referencing simulator iteration as a simulator state variable UM 289 Delta cycles UM 299 ModelSim User s Manual UM 310 Index delta simulator state variable UM 289 Dependent design units UM 45 describe command CR 62 Descriptions
319. ting started with projects UM 18 e Compiling with the graphic interface UM 211 e Simulating with the graphic interface UM 217 ModelSim variables ModelSim User s Manual Several variables are available to control simulation provide simulator state feedback or modify the appearance of the ModelSim GUI To take effect some variables such as environment variables must be set prior to simulation See Appendix A ModelSim Variables for a complete listing of ModelSim variables Compiling VHDL designs UM 45 Compiling VHDL designs Creating a design library Before you can compile your design you must create a library in which to store the compilation results Use vlib CR 161 to create a new library For example vlib work This creates a library named work By default compilation results are stored in the work library gt Note The work library is actually a subdirectory named work This subdirectory contains a special file named _info Do not create libraries using MS Windows or DOS commands always use the vlib command CR 161 See Design libraries UM 31 for additional information on working with libraries Invoking the VHDL compiler ModelSim compiles one or more VHDL design units with a single invocation of vcom CR 129 the VHDL compiler The design units are compiled in the order that they appear on the command line For VHDL the order of compilation is important you must compile any entities or
320. tions y h vendorA libext v Since the uselib directives are embedded in the Verilog source code there is more flexibility in defining the source libraries for the instantiations in the design The appearance of a uselib directive in the source code explicitly defines how instantiations that follow it are resolved completely overriding any previous uselib directives For example the following code fragment shows how two different modules that have the same name can be instantiated within the same design uselib dir h vendorA file v NAND2 ul nl n2 n3 ModelSim User s Manual UM 68 5 Verilog Simulation ModelSim User s Manual uselib dir h vendorB file v NAND2 u2 n4 n5 n6 This allows the NAND2 module to have different definitions in the vendorA and vendorB libraries compile_uselibs argument In ModelSim versions 5 5 and later use the compile_uselibs argument to vlog CR 162 to reference uselib directives The argument finds the source files referenced in the directive compiles them into automatically created object libraries and updates the modelsim ini file with the logical mappings to the libraries When using compile_uselibs ModelSim determines into what directory to compile the object libraries by choosing in order from the following three values e The directory name specified by the compile_uselibs argument For example compile_uselibs mydir e The directory specifie
321. tiple processes For example a second process is shown that initializes the memory you could add other processes to create a multi ported memory To implement this model you will need functions that convert vectors to integers To use it you will probably need to convert integers to vectors Example functions are provided below in package conversions use std standard all library ieee use ieee std_logic_1164 all use work conversions all entity memory is generic add_bits integer 12 data_bits integer 32 port add_in in std_ulogic_vector add_bits 1 downto 0 data_in in std_ulogic_vector data_bits 1 downto 0 data_out out std_ulogic_vector data_bits 1 downto 0 cs mwrite in std_ulogic do_init in std_ulogic subtype word is std_ulogic_vector data_bits 1 downto 0 constant nwords integer 2 add_bits type ram_type is array 0 to nwords 1 of word end architecture style_93 of memory is ModelSim User s Manual UM 302 C Tips and Techniques shared variable ram ram_type begin memory process cs variable address natural begin if rising_edge cs then address sulv_to_natural add_in if mwrite 1 then ram address data_in data_out lt ram address else data_out lt ram address end if end if end process memory illustrates a second process using the shared variable initialize process do_init variable address begin natural Mod
322. to_time Util package UM 57 Example If the simulator resolution is set to ps and you enter the following function realval to_real 12 99 ns then the value returned to realval would be 12990 0 If you wanted the returned value to be in units of nanoseconds ns instead you would use the get_resolution UM 54 function to recalculate the value realval le 9 to_real 12 99 ns get_resolution If you wanted the returned value to be in units of femtoseconds fs you would enter the function this way realval le 15 to_real 12 99 ns get_resolution to_time converts a real value into a time value with respect to the current simulator resolution The precision of the converted value is determined by the simulator resolution For example if you were converting 5 9 to a time and the simulator resolution was ps then the time value would be 6 ps Syntax timeval to_time realval Returns Name Description timeval time The real value represented as a physical type time with respect to the simulator resolution Arguments Name Description realval The value of the type real Related functions get_resolution UM 54 to_real UM 56 Example If the simulator resolution is set to ps and you enter the following function timeval to_time 72 49 then the value returned to timeval would be 72 ps ModelSim User s Manual UM 58 ModelSim User s Manual
323. tor commands are described elsewhere in this manual while this section focuses specifically on Verilog simulation Invoking the simulator A Verilog design is ready for simulation after it has been compiled into one or more libraries The simulator may then be invoked with the names of the top level modules many designs contain only one top level module For example if your top level modules are testbench and globals then invoke the simulator as follows vsim testbench globals If a top level module name is not specified ModelSim will present the Load Design dialog box from which you can choose one or more top level modules See Simulating with the graphic interface UM 217 for more information After the simulator loads the top level modules it iteratively loads the instantiated modules and UDPs in the design hierarchy linking the design together by connecting the ports and resolving hierarchical references By default all modules and UDPs are loaded from the library named work On successful loading of the design the simulation time is set to zero and you must enter a run command to begin simulation Commonly you enter run all to run until there are no more simulation events or until finish is executed in the Verilog code You can also run for specific time periods e g run 100 ns Enter the quit command to exit the simulator ModelSim User s Manual UM 70 5 Verilog Simulation Simulation resolution limit The
324. tostr Verilog PLIVPI UM 99 tf_message tf_mipname tf_imipname tf_movepvc_flag tf_imovepvc_flag tf_multiply_long tf_nodeinfo tf_inodeinfo tf_nump tf_inump tf_propagatep tf_ipropagatep tf_putlongp tf_iputlongp tf_putp tf_iputp tf_putrealp tf_iputrealp tf_read_restart tf_real_to_long tf_rosynchronize tf_irosynchronize tf_scale_longdelay tf_scale_realdelay tf_setdelay tf_isetdelay tf_setlongdelay tf_isetlongdelay tf_setrealdelay tf_isetrealdelay tf_setworkarea tf_isetworkarea tf_sizep tf_isizep tf_spname tf_ispname tf_strdelputp tf_istrdelputp tf_strgetp tf_istrgetp tf_strgettime tf_strlongdelputp tf_istrlongdelputp tf_strrealdelputp tf_istrrealdelputp tf_subtract_long tf_synchronize tf_isynchronize tf_testpvc_flag tf_itestpvc_flag tf_text tf_typep tf_itypep tf_unscale_longdelay tf_unscale_realdelay tf_warning tf_write_save ModelSim User s Manual UM 100 5 Verilog Simulation Verilog XL compatible routines The following PLI routines are not defined in IEEE Std 1364 but ModelSim Verilog provides them for compatibility with Verilog XL char acc_decompile_exp handle condition This routine provides similar functionality to the Verilog XL acc_decompile_expr routine The condition argument must be a handle obtained from the acc_h
325. tton three button mouse or lt Ctrl gt left mouse button two button mouse and while continuing to press drag to the right and then release at the right side of the desired zoom interval Zooming keyboard shortcuts See Wave window mouse and keyboard shortcuts UM 205 for a complete list of Wave window keyboard shortcuts Wave window UM 203 Saving zoom range and scroll position with bookmarks Bookmarks allow you to save a particular zoom range and scroll position This lets you return easily to a specific view later You save the bookmark with a name and then access the named bookmark from the Bookmark menu Bookmarks are saved in the Wave format file see Adding items with a Wave window format file UM 181 and are restored when the format file is read There is no limit to the number of bookmarks you can save Bookmarks can also be created and managed from the command line See bookmark add wave command CR 42 for details To add a bookmark select Bookmark gt Add Bookmark Wave window Bookmark Properties wave iof x Bookmark Label example Zoom jo ns to 625 us Top Index E IV save zoom range with bookmark V save scroll location with bookmark OK Cancel The Bookmark Properties dialog includes the following options Bookmark Label A text label to assign to the bookmark The label will identify the bookmark on the Bookmark menu Zoom A starting value and ending value that define t
326. ugging Same as the nodebug switch for the vecom command CR 129 See Source code security and nodebug UM 297 for more details Edit the NoDebug UM 279 variable in the modelsim ini file to set a permanent default ModelSim User s Manual UM 214 7 Graphic Interface ModelSim User s Manual Use explicit declarations only Used to ignore an error in packages supplied by some other EDA vendors directs the compiler to resolve ambiguous function overloading in favor of the explicit function definition Same as the explicit switch for the vcom command CR 129 Edit the Explicit UM 279 variable in the modelsim ini file to set a permanent default Although it is not intuitively obvious the operator is overloaded in the std_logic_1164 package All enumeration data types in VHDL get an implicit definition for the operator So while there is no explicit operator there is an implicit one This implicit declaration can be hidden by an explicit declaration of in the same package LRM Section 10 3 However if another version of the operator is declared in a different package than that containing the enumeration declaration and both operators become visible through use clauses neither can be used without explicit naming for example ARITHMETIC left right This option allows the explicit operator to hide the implicit one Disable loading messages Disables loading messages in the Main window Same as the quie
327. unctionality is provided by selecting a module in the graphic interface Structure window The corresponding source code is displayed in the source window Sreset This system task resets the simulation back to its time 0 state The equivalent simulator command is restart Srestart filename This system task sets the simulation to the state specified by filename saved in a previous call to save The equivalent simulator command is restore lt filename gt Ssave filename This system task saves the current simulation state to the file specified by filename The equivalent simulator command is checkpoint lt filename gt Sscope hierarchical_name This system task sets the interactive scope to the scope specified by hierarchical_name The equivalent simulator command is environment lt pathname gt Sshowscopes This system task displays a list of scopes defined in the current interactive scope The equivalent simulator command is show Sshowvars This system task displays a list of registers and nets defined in the current interactive scope The equivalent simulator command is show ModelSim User s Manual UM 82 5 Verilog Simulation init_signal_spy The init_signal_spy system task mirrors the value of a VHDL signal or Verilog register wire called the spy_object onto an existing Verilog register or VHDL signal called the dest_object This system task allows you to reference VHDL signals at any level of hierarchy from
328. voked in the project s root directory If invoked outside the project directory the MODELSIM environment variable can be set with the path to the project file lt Project_Root_Dir gt lt Project_Name gt mpf You can also use the project command CR 96 from the command line to perform common operations on new projects The command is to be used outside of a simulation session System initialization System initialization UM 27 ModelSim goes through numerous steps as it initializes the system during startup It accesses various files and environment variables to determine library mappings configure the GUI check licensing and so forth Files accessed during startup The table below describes the files that are read during startup They are listed in the order in which they are accessed File Purpose modelsim ini contains initial tool settings see Preference variables located in INI files UM 278 for specific details on the modelsim ini file location map file used by ModelSim tools to find source files based on easily reallocated soft paths default file name is mgc_location_map pref tcl contains defaults for fonts colors prompts window positions and other simulator window characteristics see Preference variables located in Tcl files UM 287 for specific details on the pref tcl file modelsim tcl contains user customized settings for fonts colors prompts window positions an
329. w Icon All icon all windows Deicon All deicon all windows lt window_name gt list of the currently open windows select a window name to switch to or show that window if it is hidden when the source window is available the source file name is also indicated open additional windows from the View menu UM 128 in the Main window Signals window UM 155 Signals window The Signals window is divided into two window panes The left pane shows the names of HDL items in the current region which is selected in the Structure window The right pane shows the values of the associated HDL items at the end of the current run The data in this pane is similar to that shown in the Wave window UM 178 except that the values do not change dynamically with movement of the selected Wave window cursor You can double click a signal and it will highlight that signal in the Source window opening a Source window if one is not open already Horizontal scroll bars for each window pane allow scrolling to the right or left in each pane individually The vertical scroll bar will scroll both panes together The HDL items can be sorted in ascending descending or declaration order HDL items you can view ey signals sim 0 x File Edit View Window One entry is created for each of the following VHDL and Verilog items within the design ek pr VHDL items pstrb signals prdy 0 paddr 00000100 Verilog items pdata 000000000
330. w gt scrolls window to very top or Keystroke bottom vertical scroll or far left or right horizontal scroll Action il or zoom in oOo zoom out for F zoom full mouse pointer must be over the the cursor or waveform panes lor L zoom last ror R zoom range lt arrow up gt scroll waveform display up by selecting the item above the currently selected item lt arrow down gt scroll waveform display down by selecting the item below the currently selected item lt arrow left gt scroll waveform display left lt arrow right gt scroll waveform display right lt page up gt scroll waveform display up by a page lt page down gt scroll waveform display down by a page lt tab gt search forward right to the next transition on the selected signal finds the next edge lt shift tab gt search backward left to the previous transition on the selected signal finds the previous edge lt control f gt open the find dialog box searches within the specified field in the pathname pane for text strings ModelSim User s Manual UM 206 7 Graphic Interface Saving waveforms Saving a eps file Select File gt Print Postscript Wave window to save the waveform as a eps filewrite wave command CR 196 Printing and writing preferences are controlled by the dialog box shown below Write Postscript fi a ooo
331. w with View gt New gt Wave Main window gt Note Wave window format files are design specific use them only with the design you were simulating when they were created The Wave window menu bar waye default File Edit Cursor Zoom Compare Bookmark Format Window she B RK eT QQQQE Lere mi Hate le f a The following menu commands and button options are available from the Wave window menu bar If you see a dotted line at the top of a drop down menu you can select it to create a separate menu window Many of these commands are also available via a context menu by clicking your right mouse button within the wave window itself File menu Open Dataset open a dataset New Divider insert a divider at the current location New Group setup a new group element a container for other items that can be moved cut and pasted like other objects NOT CURRENTLY IMPLEMENTED Save Format save the current Wave window display and signal preferences toa DO macro file running the DO file will reformat the Wave window to match the display as it appeared when the DO file was created Load Format run a Wave window format DO file previously saved with Save Format Page Setup setup page for printing options include paper size margins label width cursors color scaling and orientation Print ModelSim User s Manual send the contents of the W
332. where in the interface you click In other words the menus change based on the context of their use All window menus can be torn off to create a separate menu window To tear off click on the menu then select the dotted line button at the top of the menu Common window features UM 121 Combining signals into a user defined bus You can collect items of the same type in the List window UM 139 or Wave window UM 178 and combine them into a bus Use the Edit gt Combine menu command in either window Tree window hierarchical view ModelSim provides a hierarchical or tree view of some aspects of your design in the Main window Structure tabs and the Structure Signals Variables and Wave windows HDL items you can view structure ofj xi Depending on which window you are z 7 rae File Edit Window viewing one entry is created for each of the following VHDL and Verilog E top toplonly HDL items within the design p proc VHDL items m memory indicated by a dark blue square icon signals variables component instantiations generate statements Bi Package std_logic_1164 block statements and packages Package standard Package std_logic_util E Package vi_types l cache cache Verilog items Function hash indicated by a lighter blue circle icon Task update_mru parameters registers nets module instantiations named forks named begins tasks and functions Function pick_set Task sysread
333. wo virtual signals The definitions of virtuals can be saved to a macro file using the virtual save command CR 154 By default when quitting ModelSim will append any newly created virtuals that have not been saved to the virtuals do file in the local directory If you have virtual signals displayed in the Wave or List window when you save the Wave or List format you will need to execute the virtuals do file or some other equivalent to restore the virtual signal definitions before you re load the Wave or List format during a later run There is one exception implicit virtuals are automatically saved with the Wave or List format Implicit and explicit virtuals An implicit virtual is a virtual signal that was automatically created by ModelSim without your knowledge and without you providing a name for it An example would be if you expand a bus in the Wave window then drag one bit out of the bus to display it separately That action creates a one bit virtual signal whose definition is stored in a special location and is not visible in the Signals window or to the normal virtual commands All other virtual signals are considered explicit virtuals Virtual functions Virtual functions behave in the GUI like signals but are not aliases of combinations or elements of signals logged by the kernel They consist of logical operations on logged signals and can be dependent on simulation time They can be displayed in the Signals Wave an
334. work Click Set and Apply to initialize the variable you don t need to restart NT Library mapping with environment variables Once the MY_PATH variable is set you can use it with the vmap command CR 167 to add library mappings to the current modelsim ini file If you re using the vmap command from DOS prompt type vmap MY_VITAL MY_PATH If you re using vmap from ModelSim VSIM prompt type vmap MY_VITAL SMY_PATH If you used DOS vmap this line will be added to the modelsim ini MY_VITAL c temp work If vmap is used from the ModelSim VSIM prompt the modelsim ini file will be modified with this line MY_VITAL MY_PATH ModelSim User s Manual Environment variables UM 277 You can easily add additional hierarchy to the path For example vmap MORE_VITAL MY_PATH more_path and_more_path vmap MORE_VITAL SMY_PATH more_path and_more_path The character in the examples above is Tcl syntax that precedes a variable The character is an escape character that keeps the variable from being evaluated during the execution of vmap Referencing environment variables within ModelSim There are two ways to reference environment variables within ModelSim Environment variables are allowed in a FILE variable being opened in VHDL For example entity test is end use std textio all architecture only of test is begin process FILE in_file text is in SENV_VAR_NAME begin wait end process end Env
335. ximum value in min typ max expressions The default is the typical value This option has no effect if the min typ max selection was determined at compile time t mindelays This option selects the minimum value in min typ max expressions The default is the typical value This option has no effect if the min typ max selection was determined at compile time t multisource_int_delays This option enables multisource interconnect delays with transport delay behavior and pulse handling ModelSim uses a unique delay value for each driver to driven module interconnect path specified in the SDF file Pulse handling is configured using the pulse_int_e and pulse_int_r switches described below no_cancelled_e_msg This option disables negative pulse warning messages By default Vsim issues a warning and then filters negative pulses on specify path delays You can drive an X for a negative pulse using show_cancelled_e no_neg_tchk This option disables negative timing check limits by setting them to zero By default negative timing check limits are enabled This is just the opposite of Verilog XL where negative timing check limits are disabled by default and they are enabled with the neg_tchk option no_notifier This option disables the toggling of the notifier register argument of the timing check system tasks By default the notifier is toggled when there is a timing check violation and the notifier usually causes a UDP to propagate an X Th
336. y sync nor array sync and plane sync nand plane sync or plane sync nor plane Value change dump VCD file tasks dumpall dumpfile dumpflush dumplimit dumpoff dumpon dumpvars File I O tasks fclose fdisplay fdisplayb fdisplayh fdisplayo ferror fflush fgetc fgets fmonitor fmonitorb fmonitorh fmonitoro fopen fread fscanf fseek fstrobe fstrobeb fstrobeh fstrobeo ftell fwrite fwriteb System Tasks UM 79 fwriteh fwriteo readmemb readmemh rewind sdf_annotate sformat sscanf swrite swriteb swriteh swriteo ungetc gt Note readmemb and readmemh match the behavior of Verilog XL rather than IEEE Std 1364 Specifically it loads data into memory starting with the lowest address For example whether you make the declaration memory 127 0 Or memory 0 127 ModelSim will load data starting at address 0 and work upwards to address 127 ModelSim User s Manual UM 80 5 Verilog Simulation Verilog XL compatible system tasks ModelSim User s Manual The following system tasks are provided for compatibility with Verilog XL Although they are not part of the IEEE standard they are described in an annex of the IEEE Std 1364 Scountdrivers Sgetpattern Ssreadmemb Ssreadmemh The following system tasks are also provided for compatibility with Verilog XL they are not described in the IEEE Std 1364 Sdeposit variable value This system task
337. y of the selected HDL item Expand All Shows the hierarchy of all HDL items in the list Collapse All Hides the hierarchy of all HDL items in the list Find Opens the Find dialog See Finding items in the Structure window UM 174 for details ModelSim User s Manual UM 108 6 WLF files datasets and virtuals Managing datasets When you have one or more datasets open you can manage them using the Dataset Browser To open the browser select View gt Datasets Main window Dataset Browser Dataset Contest Mode fcache sysread View E modelsimS4b_se exal control Simulation No signals logged View Open Dataset Close Dataset Make Active Rename Dataset Doe The Dataset Browser dialog box includes the following options Open Dataset Opens the View Dataset dialog box see Opening datasets UM 105 so you can open additional datasets Close Dataset Closes the selected dataset This will also remove the dataset s Structure tab in the Main window workspace Make Active Makes the selected dataset active You can also effect this change by double clicking the dataset name Active dataset means that if you type a region path as part of a command and omit the dataset prefix the active dataset will be assumed It is equivalent to typing env lt dataset gt at the VSIM prompt Rename Dataset Allows you to assign a new logical name for the selected dataset Using datasets with ModelSim
338. y the examine command and set using the force command Virtual signals can be created via a menu in the Wave and List windows Edit gt Combine or with the virtual signal command CR 156 Virtual signals can also be dragged and dropped from the Signals window to the Wave and List windows Virtual signals are automatically attached to the design region in the hierarchy that corresponds to the nearest common ancestor of all the elements of the virtual signal The virtual signal command has an install lt region gt option to specify where the virtual signal should be installed This can be used to install the virtual signal in a user defined region in ModelSim User s Manual Virtual Objects User defined buses and more UM 111 order to reconstruct the original RTL hierarchy when simulating and driving a post synthesis gate level implementation A virtual signal can be used to reconstruct RTL level design buses that were broken down during synthesis The virtual hide command CR 147 can be used to hide the display of the broken down bits if you don t want them cluttering up the Signals window If the virtual signal has elements from more than one WLF file it will be automatically installed in the virtual region virtuals Signals Virtual signals are not hierarchical if two virtual signals are concatenated to become a third virtual signal the resulting virtual signal will be a concatenation of all the subelements of the first t
339. yed on the screen In ModelSim reading from the STD_INPUT file allows you to enter text into the current buffer from a prompt in the Main window The last line written to the STD_OUTPUT file appears at the prompt ModelSim User s Manual TextlO implementation issues UM 49 TextlO implementation issues Writing strings and aggregates A common error in VHDL source code occurs when a call to a WRITE procedure does not specify whether the argument is of type STRING or BIT_VECTOR For example the VHDL procedure WRITE L hello will cause the following error ERROR Subprogram WRITE is ambiguous In the TextIO package the WRITE procedure is overloaded for the types STRING and BIT_VECTOR These lines are reproduced here procedure WRITE L inout LINE VALUE in BIT_VECTOR JUSTIFIED in SIDE RIGHT FIELD in WIDTH 0 procedure WRITE L inout LINE VALUE in STRING JUSTIFIED in SIDE RIGHT FIELD in WIDTH 0 The error occurs because the argument hello could be interpreted as a string or a bit vector but the compiler is not allowed to determine the argument type until it knows which function is being called The following procedure call also generates an error WRITE L 010101 This call is even more ambiguous because the compiler could not determine even if allowed to whether the argument 010101 should be interpreted as a string or a bit vector There are two possible solutions to this problem e

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ModelSim User's Manual - Institut für Informatik