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Model 64621A State Analysis Control Board Service Manual

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1. a zl 5 Da o m 2 12225 OO Fe d E x m elu c zt 49 lt 2 Q 2r gt gt 1 ED Ds ca 18 T3 T2 Ti 64621 66501 2 Q E G lt 5 HE 5 Bo PDC a 4 ae STATE CONTROL BOARD z q 7008 REV A 5 lt o SIF Boa ona Olen OT II LME e M E c BEBE cLock Pop k LTE 10 1 FS1 FS FS2 LSE u4 us u7 u n sa 8 Lj L on Al mu 010 11 12 STROBES TEST i e UM T5 qp R27 E R FF rar EERE EF EE F g R28 PREIRO R oes HMCLK CONTROL ANALYSIS cm lal 1 i c RN INTERFACE PROBE STROBE U16 u17 9018 vi9 l uzo U21 022 U23 1 924 TP11 R31 LINES CONTROLLER 5 Ege me HQWRITE HWQ i dt 14 Q1 U31 U32 U33 TP13 U35 U27 TEST 11 5 1 9 aoe eae E ez 1 us pas Qus U41 Gre U46 abusa ur Ies f d d d e i U36 u40 de hee 5 OBES para C32 C33 C34 Oeno cas SI 5 e n cc M CR3 C28 U56 amp C29 pera 3 a a a z e de es u70 u72 u73 aa 5 9 8 G Ola
2. 5 T4 T2 TI 64621 66501 Mp2 R2 9 STATE CONTROL BOARD R3 J z REV A MP3 c roo CLOCK POD 10 1 FS1 FS FS2 04 E Ore ee 1 010 cn 12 C68 VI I 1 J 8 528 suole 3 R20 EE U15 912 U13 Rio o R21 eci bg 1 1 7 a2 E 2 2 gt R27 TESTE co R30 016 Ui7 U18 u19 920 021 G 922 U23 1 924 8 a 2 a T 5 5 5 U29 amp uso 1 y i dl c 031 027 14 Q1 U32 U33 U34 _ Tee U35 R33 cs XJ 0 20 025 gt mo u ad U48 049 USI 8 N v e a a H U53 54 955 U43 U44 U45 U47 u50 952 9 936 938 040 042 C30 31 C32 C33 C34 cas C3e 37 R34 38 gu f CR3 C28 use 3 29 uai x z z U74 u70 u72 U73 U67 U68 U69 U58 059 U60 u61 u62 u63 064 065 966 Loy z 1 975 076 40 41 C42 C43 C44 T J xu 9 o r F Rnss Fr f F qd e F fe fe uso u91 092 g 9 078 u79 uso ust us2 U83 u85 u87 uss 994 L J bat Sd L L SA CLOCK Te C48 C49 Losa 27
3. s t N T3 1 T3 2 T3 3 73 M T3 5 73 6 T3 7 73 10 13 11 73 12 73 13 73 14 73 15 73 16 73 18 73 20 TOTLZ U 73 21 1796 3781 8989 50 9 93 5 C6HO 6HFO 8F6A 641C 1F56 F82U HUSA 9520 AOCT AC8P 0567 894H 1796 3781 8989 50P9 93A5 C6HO 1 6HFO 641C FUOC F82U UHAU 9520 high AC8P PP9C 894H 1796 3781 CONNECTIONS ST SP Start TP19 Qual Stop TP19 Clock U99 pin 3 Ground GND TP Qual U100 pin 7 n I 0 86 FU0C high FU0C ThP2 low 8F6A 1F56 HUSA AOCT 8F6A 1F56 HU5A AOCT H9C2 5APh 885 H244 2 9501 3133 POAU FF68 FF68 P48H 8A99 7920 470F 3U9H 8965 80H9 CPFF FF68 00F4 ECL ECL ECL ECL ECL ECL ECL ECL SAC 4 7 Model 64621A Performance Verification Board 64621 66503 Test 6 Loop VH 894H QUAL PFA4 MODE EDGES THRESHOLDS CONNECTIONS Normal Clock Positive Data High ST SP Start TP19 Start Positive Data Low Qual Stop TP19 QUAL Stop Negative Clock TIL Clock U99 pin 3 High ST SP QL TIL Ground GND TP Qual 0100 pin 7 levels TIL except where noted 0 86 13 P82F U 90 6 U 92 10 0F8U U 86 14 hori U 90 7 6HFO U 92 11 3U98 U 86 15 U
4. 4 30 4 75 TEST 9 STROBE GENERATOR CALIBRATION 4 31 4 77 TEST 10 THRESHOLD CIRCUIT CALIBRATION 4 31 4 79 TEST 11 PREPROCESSOR INTRFC STIMULUS LOOP H 4 31 4 84 TEST 12 REAR PANEL PORT STIMULUS LOOP 4 31 Model 64621A Table of Contents Section Adjustments INTRODUCTION rv ee oes Mc oe euer RE SU Be deese dre 5 1 SAFETY REQUIREMENTS pm Siete EQUIPMENT REQUIRED VN Rae s RA AE DENS LE 5 T TEST EQUIPMENT Peck atv due exe eo Ea Sadi PP 5 8 ACCESSORIES e ona SU secu d e era aie 91 5 1 5 1 5 3 n m 5 9 PROCEDURE ane varese 5 11 STROBE GENERATOR ADJUSTMENTS TEST O 5 12 THRESHOLD ADJUSTMENTS TEST 10 Section VI Replaceable parts 1 INTRODUCTION Se aS RES TOC erre 3 ABBREVIATIONS CORRE CR u ME 6 1 5 REPLACEABLE PARTS LIST deal uq aas e a d Suwa T ORDERING INFORMATION PLN de d ses 6 1 10 SPARE PARTS KIT VERAM PERDE 6 12 DIRECT MAIL ORDER SYSTEM 6 2 Oey
5. Pila ii 4 20 Figure 4 15 Clock IC Shift 1 4 21 Figure 4 16 VA n Aa dO Seok o t TERES 4 23 Figure 8 17 State LUPE She iure viste 4 25 Figure 4 18 Trace Memory Tm ARE dario Emme veh reda ede 12 4 27 Figure 4 19 Other Counter Tests E vies 4 29 Figure 4 20 Intermodule Sicha de Macatee E avast 2 5 30 Signature 1 gna Vua ce Ro Section V Adjustments Figure 5 1 Adjustment Locations Muse IRR ete e 5 5 Section Replaceable Parts Table 6 1 Reference Designators and taxes 6 3 Figure 6 1 Probe Cable Breakdown E 6 4 Table 6 2 Replaceable Parts 115 6 5 Table 6 3 List of Manufacturers Codes GC p NERA Ea s pati Desc L0 Model 64621A List of Figures and Tables Section Vil Manual Backdating Table 7 1 Manual le ar Rede Bee E 7 1 Section VIII Service Figure 8 1 State Analyzer Subsystem Block 8 5 Figure 8 2 State Analysis Control Board Block Diagram 8 9 Figure 8 3 Clock Term Generator
6. ALR46 0098 5612 A1R47 0698 6612 ALR48 0757 0394 A1R49 0757 0394 81850 0757 0438 ISTOR 2k ISTOR 2K ISTOR 51 5 RESISTOR 51 125 RESISTOR 5 11 17 2 F TC 0 100 28480 0698 5612 04 100 20480 0598 6612 u F 0 100 24546 4 1 8 0 5181 W TO 0 100 24546 4 1 8 10 5181 SW TC 0 100 24546 C4 1 8 T0 5111 F AIRS1 4698 6012 ALRS2 0698 3455 AIRSS 0678 6612 ALRS4 0257 0394 AIRSS 0757 0394 RESISTOR 1 125W F 0 100 29480 0698 6642 RESISTOR 261K 1X 125W TC 0 100 24546 C4 1 8 T0 2613 F RESISTOR 1 125W 0 100 28480 0598 6612 RESISTOR 51 1 1 1254 F TC 0 100 24546 C4 1 8 T0 S1R1 F RESISTOR 51 1 1 125W F 0 100 24546 C4 1 8 T0 S1R1 F gt ALRSS 0757 0394 1 57 0752 0394 RESISTOR 51 1 17 125 F TC 0 100 24546 4 1 8 0 5181 RESISTOR 51 1 1 1254 F 0 100 24546 4 1 8 70 5181 F co 1 2 0360 0535 ALTPS 0360 0555 ALTPS 0560 0535 11 9 0360 0535 1 10 0360 0535 TERMINAL TEST POINT PCR 00000 ORDER K CRIPTION TERMINAL TEST POINT PCR 00000 ORDER CRIPTION TERMINAL TEST POINT PCR 00000 ORDER SCRIPTION TERMINAL TEST POINT PCB 00000 ORDER URIPTION TERMINAL TEST POINT PCR 00000 ORDER SCRIPTION 1 11 0360 0535 ALTP12 0360 0535 A1TP14 0360 0535 GND 0360 0535 GND 0360 0535 GND 0360 0535 RiTP18 0360 0535 1 19 0360 0535 TERMINAL TEST POINT PCR 00000 ORDER TERM
7. 2497 Jkt Antara Bldg 12th Floor Jl Medan Merdeka Selatan 17 JAKARTA PUSAT Tel 21 340417 341445 Telex 46748 BERSAL IA A C E M BERCA Indonesia P T Jalan Kutai 24 SURABAYA Tel 67118 Telex 31146 BERSAL SB Cable BERSAL SURABAYA IRAQ Hewlett Packard Trading S A Service Operation Mansoor City 9B 3 7 BAGHDAD Tel 551 49 73 Telex 212 455 HEPAIRAQ IK IRELAND Hewlett Packard Ireland Ltd 82 83 Lower Leeson Street DUBLIN 2 Tel 0001 608800 Telex 30439 A C CM E M P Cardiac Services Ltd Kilmore Road Artane DUBLIN 5 Tel 01 351820 Telex 30439 M SALES amp SUPPORT OFFICES Arranged alphabetically by country ISRAEL Eldan Electronic Instrument Ltd 1270 JERUSALEM 91000 16 Ohaliav St JERUSALEM 94467 Tel 533 221 553 242 Telex 25231 AB PAKRD IL Computation and Measurement Systems CMS Ltd 11 Masad Street 67060 TEL AVIV Tel 388 388 Telex 33569 Motil IL C CM E P ITALY Hewlett Packard Italiana S p A Traversa 99 Via Giulio Petroni 19 70124 BARI Tel 080 41 07 44 CM Hewlett Packard Italiana S p A Via Emilia 51 0011 BOLOGNA Anzola Dell Emilia Tel 051 731061 Telex 511630 Hewlett Packard Italiana 5 Via Principe Nicola 43G C 95126 CATANIA Tel 095 37 10 87 Telex 970291 C Hewlett Packard Italiana S p A Via G Di Vittorio 9 1 20063 CERNUSCO SUL NAVIGLIO
8. C30 31 C32 C33 C34 cas C3e 37 R34 38 i CR3 C28 U55R Di C29 ust g z O P F U74 072 973 U67 U68 U69 U58 59 960 u61 u62 u63 964 065 966 L Losi Lod L 1 975 076 cao 41 42 C43 C44 5 n J I 9 e R3 e 7 F qd e e e e e e m 091 092 U93 9 078 980 ust us2 083 uss U87 U88 094 J LJ MERI SA CLOCK a C49 7 cas 4 rao 47 48 3 R38 R39 Ut c a REA fe g up d d e e F I e u97 098 9100 U101 0102 9103 0104 9105 9106 9107 0108 0109 9110 42 R43 Ra4 53 C54 TP15 U112 C51 52 css R4 cse R47 C57 R48 0130 45 GND u128 8497 g g s g D F 71 q qg a U115 0116 u17 vidi 0124 0125 0127 U118 9119 0120 0121 0122 0126 Tp18 0129 17 LJ c67 R54 C64 c58 cei RB1 J L Rss U Rss cse R50 62 TP19 6 Rse C6 TP16 R57 C6 60 SA START STOP 35 53 59 69 79 8385 i gt Pt 5 5 83 64621A STATE CONTROL Component Locator SAC 8 52 P O 1 STATE ANALYSIS CONTROL BOARD 64621 66503 TRACE STATE TIME COUNTER 4 NC 2 6 24 1 5
9. U 38 10 HO2H ECL U 42 15 78AA ECL U 58 5 A59P ECL U 38 11 762F U 42 16 F61U ECL 58 6 PHAC ECL U 38 13 Ch27 ECL U 42 17 6546 ECL U 58 7 082C ECL U 38 14 03P7 ECL U 42 18 99F7 ECL U 58 9 9946 ECL U 42 19 357P ECL U 42 21 082C ECL U 42 23 SAC 4 33 Model 64621A Performance Verification Board 64621 66503 MODE EDGES Normal Clock sas Start Stop levels are 8PC9 058 5 59 1 85 li2c2 U5C3 PFH9 4871 5 082C 9946 8PC9 048 25HU U5C3 1 85 6302 508 082 9946 99FT 357P 5A59 1 85 4202 600000000000 UEWNRPOONKDNU G A A ON U5C3 PFH9 6302 508P PHAC 082C 9946 c qa qa c lt qa c ON ON GN OX GX ON PPPPPP P 1 1 1 1 O NO NU TN P U 61 1 SAC 4 34 Positive Positive Negative THRESHOLDS Data High Data Low Clock TIL ST SP QL TIL Test 1 Loop VH 8U24 CONNECTIONS ST SP Start TP19 Qual Stop TP19 Clock U99 pin 3 Ground GND TP TTL except where noted ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL 99FT 35TP 25HU U5C3 PFH9 5 FFU9 T 9UOH 0 5459 1 25HU 1 9UO
10. aa gt Q D 2 gt 2 O 8 8 Cand 8 3 DATA 5 5 83 64621A STATE CONTROL a 5 Oo o m S 12225 OG EE c IM m uiu 2 gt lt DE DE E gt ca 15 73 T2 Ti 64621 66501 z DIOL Z z PDC E G lt ego tc D 6 a EE T STATE CONTROL BOARD g R 5 lt MPA ole SITA II LME Si ee a sis ki s LTE 10 U FS1 FS FS2 LSE u4 us Us u7 u e e 8 LJ 41 Tog d 4 U10 11 12 8 nce e ag po 8 58 3 ic 73 E PREPROCESSOR CLOCK STROBES r3 ali eater ipu us H 152 REC F U28 5829 INTERFACE PROBE HMCLK STROBE CONTROL ANALYSIS R u16 ui7 juts 1 u20 u21 H u2 U23 U24 5 U26 ZRS BUS INTERFACE GENERATOR LINES CONTROLLE 5 885 HQWRITE HWQ Q1 U31 U32 U33 934 TP13 U35 U27 L Rsa TEST 11 TEST 1 9 T O7 amp Je oe 1 18 3 0
11. U125 1 1 U101 13 4022 U106 h PCCF U125 2 28H4 U101 14 55659 U125 3 PCCF U101 15 422A U118 2 664F 0118 3 664F U127 6 28H4 U102 1 PACS U102 2 9147 SAC 4 h2 Board 64621 66503 MODE EDGES Normal Clock Positive Start Positive Stop Negative THRESHOLDS Data High Data Low Clock TTL ST SP QL TTL levels are TIL except where noted Ww OA 1 ON CANA cu 1 PH Co di MIO wi wl Oro Ul TOTLZ U 16 1 TOTLZ U 19 3 U 19 6 U 19 7 C330 low 3113 60FU 3401 high low 0000 6550 993H 87AF 3178 0000 6550 81F1 low 0000 6550 87AF QUEL 9064 high 9064 0000 993 0160 6550 0160 0000 19 0160 0160 0000 6550 0000 6550 3809 996 996 ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL 9 20 2 0 20 5 0 45 12 TOTLZ U 45 13 U 45 15 TOTLZ U 66 4 U 66 13 U 66 2 U 66 3 U 66 14 U 66 15 TOTLZ U 69 U 69 U 69 U 69 N 6852 993 0000 6550 6852 0000 6531 3809 0160 996 3809 0000 0160 6550 830A 0049 5380 3797 C234 762C P7U2 3809 9054 FCCP 717H 3U21 8U36 A483 60FU high high high U16U 6510 high Model 64621A P
12. T In BUS INTERFACE GENERATOR LINES CONTROLLER HQWRITE HWQ Cia Qi U31 Y 032 034 x TP13 wil Md zr E E n c20 Re TEST 11 TEST 1 9 T ue u RN ci Salieri aig gen E i i 2 EE gt 7 5 U43 U44 u45 Te U36 U38 040 u42 fool dp STROBES C30 31 C32 C33 C34 Oeno _c35 i Nod 5 C28 use 3 29 Us 31 z 7 7 3 9 2 E n PN dE NU mac E x n gt n 5 a 058 059 060 U61 U62 063 064 065 066 Uer is B we cha se LJ a lt a TRACE TRACE ES STATE TIME puo COUNT STATUS a e can x Si LE E COUNTER MEMORY re 1 i H TEST 5 7 TEST 6 m vs 090 U91 092 u93 1 8 U78 079 U80 081 082 083 084 085 087 088 T U94 L J LIL cm Sui haa Wines E 45 ru as E R40 um 0113 Er u97 098 9100 U101 9103 0104 9106 n i RI gia Duo n L co csi AMT css R46 5 R47 CS7 R48 0130 lt S O n hec GND RIT CONTROL 9 4 BRE Eee TRITO Cs7 58 ad _ RSI ET _ R54 64 ADDRESS p eo on Sn Ee rep oe cso SA START STOP N MEN LEE i ai i P1 5 5 83 o I 64621A STATE CONTROL gt 5 a MAINFRAME INTERFACE TEST 1 Block Diagram Component Locator SAC 8 44 Model 64621A Service P O 1 STA
13. n 7 5 U 39 U4 042 9 n I c 8 S I c22 q c23 8 U C24 _ 8 amp gt 5 gt t amp EES 8 u ed 8 6c t O G 8 5 S 25 te 5 Bi a wo i sel s I 27 26 1 c CONTROL LDBO 7 GENERATOR 11 E STROBES ll file C30 31 C32 C33 C34 35 29 U57 amp p g zu x lt z z s a a a u70 u72 U73 Q lt use uso U61 u62 u63 U64 U65 U66 pd ust ors Ne TRACE TRACE z STATE TIME o COUNT STATUS m i aaa COUNTER MEMORY ve q F Ra6 F g TEST 5 7 TEST 6 rq rq a pu F 4 U78 u79 uso U81 us2 us3 usa uss use u87 uss id da HE i BNC 994 CONTROL m J LJ IL uss n c47 48 C49 ri 45 E J 46 cse ms THAO S uni Uds p O g F1 eq R n rud s g e A o 096 U97 0100 U101 0102 9103 0104 0106 0107 o E 3 Ra 7 ess a ee ee i L m z m AMT css O R46 C56 R47 5 R48 0130 E o R45
14. Figure 5 1 Adjustment Locations SAC 5 5 Model 64621A Adjustments NOTES SAC 5 6 Model 64621A Replaceable Parts SECTION VI REPLACEABLE PARTS 6 1 INTRODUCTION 6 2 This section contains information for ordering parts Table 6 1 lists ab breviations used in the parts list and throughout the manual Table 6 2 lists all replaceable parts in reference designator order Table 6 3 contains the names and addresses that correspond to the manufacturers five digit code numbers 6 3 ABBREVIATIONS 6 4 Table 6 1 lists abbreviations used in the parts list the schematics and throughout the manual In some cases two forms of the abbreviation are used one all in capital letters and one partial or no capitals This occurs because the ab breviations in the parts list are always capitals However in the schematics and other parts of the manual other abbreviation forms are used with both lowercase and uppercase letters 6 5 REPLACEABLE PARTS LIST 6 6 Table 6 2 is the list of replaceable parts and is organized as follows a Chassis mounted parts in alphanumerical order by reference designation b Electrical assemblies and their components in alphanumerical order by reference designation c Miscellaneous parts The information given for each part consists of the following a The Hewlett Packard part number and the check digit b The total quantity Qty in the instrument The description of the part d A five dig
15. 1 01254 2104471 2106471 SAC 6 7 Model 64621A Reference Designation 41U77 1078 41079 1080 1081 21082 11183 21084 81185 1U86 41087 21088 41089 7090 1091 1092 1093 7094 1095 21095 211097 21098 81099 10100 1U101 270102 810103 A1U104 810105 210105 210107 420108 210109 2410110 10111 A1U112 810113 A1115 410116 210117 410118 210119 10120 1012 ALU A1U123 4111124 A1U12 410126 2410127 lu128 A1U129 A1U130 ALXU26 1 2 amp 1xU29 A1XU47 ALXUSO ALXUSS 1XU70 1 071 ALXU72 A1XU73 A1XU90 A1XU91 1 092 A1XU93 amp 1XU112 AIXUL17 A1XU126 ALXULE7 SAC 6 8 Replaceable Parts HP Part Number 1820 1052 1920 1788 1820 1788 1820 1831 1820 1788 1820 1788 1820 1052 1820 1052 1820 1173 1820 1997 1816 1 308 19816 1308 1816 1308 1920 1052 1810 0273 19820 1197 1820 1282 1820 1282 1820 1197 1820 1216 1820 1216 1820 1216 0 1282 0 1430 1820 1281 1820 1 ERE 20 1052 2 20 1052 1810 0273 1484 5009 181 0 0273 1820 1423 1820 2102 1820 1997 1820 2075 1820 2024 1820 11955 1920 12 208 1810 0298 1820 1173 1810 0273 1200 0654 1200 0654 1200 0639 1200 0796 1200 0796 1200 0607 1200 0607 1200 0639 1200 0612 1200 0612 1200 0612 1200 0612 1200 0612 1200 0612 1200 0612 1200 0612 1200 0654 1200 0607 1200 0607 1200 0638 Table 6 2 Replaceable Parts
16. Box 2342 NL 5600 CH EINDHOVEN Tel 040 326911 Telex 51484 hepae nl A C E M P NEW ZEALAND Hewlett Packard N Z Ltd 5 Owens Road P O Box 26 189 Epsom AUCKLAND Tel 687 159 Cable HEWPAK Auckland C CM E P Hewlett Packard N Z Ltd 4 12 Cruickshank Street Kilbirnie WELLINGTON 3 Box 9443 Courtenay Place WELLINGTON 3 Tel 877 199 Cable HEWPACK Wellington C CM E P Northrop Instruments amp Systems Ltd 369 Khyber Pass Road Box 8602 AUCKLAND Tel 794 091 Telex 60605 Northrop Instruments amp Systems Ltd 110 Mandeville St Box 8388 CHRISTCHURCH Tel 488 873 Telex 4203 AM Northrop Instruments amp Systems Ltd Sturdee House 85 87 Ghuznee Street P O Box 2406 WELLINGTON Tel 850 091 Telex NZ 3380 NIGERIA Elmeco Nigeria Ltd 46 Calcutta Crescent Apapa Box 244and LAGOS NORTHERN IRELAND See United Kingdom NORWAY Hewlett Packard Norge A S Folke Bernadottes vei 50 Box 3558 N 5033 FYLLINGSDALEN Bergen Tel 0047 5 16 55 40 Telex 76621 hpnas n Hewlett Packard Norge A S Osterndalen 16 18 P O Box 34 N 1345 OSTERAS Tel 0047 2 17 11 80 Telex 76621 hpnas n A C CM E M P OMAN Khimjil Ramdas Box 19 MUSCAT SULTANATE OF OMAN Tel 745601 Telex 5289 BROKER MB MUSCAT Suhail amp Saud Bahwan 169 MUSCAT SULTANATE OMAN Tel 734201 Telex 5274 BAHWAN MB
17. 1250 1032 Figure 4 7 Data Probe Test Connector SAC h 11 Model 64621A Performance Verification 4 16 TEST 5 BNC PORT OUTPUTS Specifications Stimulus Port 1 Pulse Width Trigger Events 50 nS 20 nS Sequencer Events 50 nS 20 nS Delay From Clock Trigger Events 225 nS 25 ns Sequencer Events 200 nS 25 nS Halt Port 2 Delay From Clock Measurement Complete 225 nS 25 nS Trace Point 225 nS 25 ns Description Input clock measure delay to BNCs using an Oscilloscope Equipment Pulse 8013 11 HP1722B or 1783 SAC 4 12 Model 64621A Performance Verification PULSE STATE ANALYZER GEN OSCILLOSCOPE STATE CONTROL BOARD i 500 OUT A B 10 1 PROBE 500 WES CLOCK PROBE TEST CONNECTOR SEE FIGURE 4 4 Figure 4 8 BNC Port Output Test Configuration Procedure for Stimulus BNC Port 1 a adjust Pulse Generator for 100 KHz 10 uS square wave with amplitude from 0 V to 2 8 V Clock Threshold is automatically set for TTL 1 4 V b Press meas system only if more than one measurement system is installed c Press state x d Press assert bnc port 1 on all triggers e Press execute repetitively f Press trace specification g Set Oscilloscope to measure td and tw as shown in Figure 4 9 SAC h 13 Model 64621A Performance Verification 2 8
18. Milano Tel 02 4459041 Telex 334632 A C CM E M P Hewlett Packard Italiana 5 Via C Colombo 49 20090 TREZZANO SUL NAVIGLIO Milano Tel 02 4459041 Telex 322116 Hewlett Packard Italiana S p A Via Nuova San Rocco a Capodimonte 62 A 80131 NAPOLI Tel 081 7413544 Telex 710698 Hewlett Packard Italiana S p A Viale G Modugno 33 16156 GENOVA PEGLI Tel 010 68 37 07 Telex 215238 Hewlett Packard Italiana S p A Via Pelizzo 15 35128 PADOVA Tel 049 664888 Telex 430315 Hewlett Packard Italiana S p A Viale C Pavese 340 00144 ROMA EUR Tel 06 54831 Telex 610514 A C E M P Hewlett Packard Italiana S p A Via di Casellina 57 C 1 50018 SCANDICCI FIRENZE Tel 055 753863 Hewlett Packard Italiana S p A Corso Svizzera 185 110144 TORINO Tel 011 74 4044 Telex 221079 IVORY COAST S LT E L Societe Ivoirienne de Telecommunications Bd Giscard d Estaing Carrefour Marcory Zone 4 A Boite postale 2580 ABIDJAN 01 Tel 353600 Telex 43175 E SITI Immeuble General Av du General de Gaulle 01 BP 161 ABIDJAN O1 Tel 321227 CP JAPAN Yokogawa Hewlett Packard Ltd 152 1 Onna ATSUGI Kanagawa 243 Tel 0462 25 0031 C CME Yokogawa Hewlett Packard Ltd Meiji Seimei Bidg 6F 3 1 Hon Chiba Cho CHIBA 280 Tel 472 25 7701 CE Yokogawa Hewlett Packard Ltd Yasuda
19. NC WRAP LATCH NTRIG LDVTTL 2 LCLA TRACE COUNT STATUS MEMORIES 2 WRITE 3 READ EN 6 6 WRITE READ L gt WAITE 4 EN 17 d WRITE E G2 WRITE READ 63 READ LTCSMS3 al EN N a 2 1 4 3 19 S 604 sss 1582 ss a 3 VS 607 CD0 7 se 9 LTCSMS3 LD80 7 84 8 R3 2K R9 2K 42 5 us 14 LBCLR 5 5 Model 64621A Service ICs ON THIS SCHEMATIC DES U8 U66 67 68 86 U70 73 90 93 U87 88 U96 U98 103 U104 105 1820 0269 1820 1052 1820 1997 1816 1308 1820 1428 1820 1197 1820 1282 1820 1430 HP PART NO MFG PART NO 7403 10125 1415374 9315422 7415158 741500 7415109 74415161 PARTS ON THIS SCHEMATIC POWER SUPPLY CONFIGURATION 5 22 28 8 U70 73 90 93 14 7 0896 8 066 5 16 U87 88 98 5 20 10 U67 68 86 Figure 8 17 Trace Count Status Memory SAC 8 55 Model 64621A Service TO FROM IMB CLOCK PROBE SEB TO FROM OTHER PREPROCESSOR BOARDS P E a 2 2 gt Q o 2 gt 2 O o
20. cs4 15 0112 m m z m 52 css 1 R46 56 R47 57 R48 0130 la a pos Te CONTROL O e fe 71 e SMS luna und uo 0128 0129 0127 1129 TP17 L J c67 64 ADDRESS pon Ga e IM VERE ce e up 3 e NEN 1 13 53 59 69 79 8385 P1 i i 06 5 5 83 64621 STATE CONTROL tr z O A a MAINFRAME INTERFACE TEST 1 Block Diagram Component Locator SAC 8 48 P O 1 STATE ANALYSIS CONTROL BOAAD 64621 66503 none SEQUENCE OCCURRENCE COUNTERS MEMORIES 5 PSOCINC anon fr ii ON 49 S ips bol Lul TT 3 i V7 V lt UPPER 4 MEMORY LEAST MEMORY MEMORY MEMORY ECL SIGNIFICANT 4 ECL ECL 4 ECL COUNTER COUNTER COUNTER RAM 16X4 RAM 16X4 RAM 16X4 RAM 16X4 0 0 1 1 2 2 3 3 1C WRITE 1EN READ LSEQD3 12 AD AS 50 3 LSEGDO LSEGD4 LSEGD2 LSEQD3 LSEQDA LSEQD6 LSEQD7 Brae cu u a jo 1 3 25 1 pt 4 M 1325 es EEA E POWER SUPPLY CONFIGURATION 5 amend 52 3 U63 64 ma OA gt U63 U63 Eres L U63 gt U63 U64 i 5 U64 DE U64 5 064 i 5 5 R36 p 5 a E 3 a 2 LDBO LSOCLD ae i _ O 3 33 LSOCE Model 64621A Service
21. ee e l Lis et race TRACE F1 TATE TIME Z COUNT STATUS urs urs Lal lo cas 0e Coal COUNTER MEMORY ee ae ER nts L TEST 5 7 TEST 6 i uso 091 092 F BNC 078 u79 uso ust us2 us3 usa uss u87 uss T CONTROL ka L 2 45 oS Rage Baba rao 47 C48 49 un T uiis s ET qd g z g al d a a LES u97 U100 0102 9103 0104 0106 0107 k N s J L ae RR cs4 TPIS 0112 amp 5 m 51 52 C55 S R46 56 R47 C57 Ras 0190 ND CONTROL ar S O 9 a em ee tis 0115 0116 U117 U124 0127 dr Db LETTER ae TP17 C67 ADDRESS MN Le RENE LE opt gg 1 13 35 53 59 69 79 8385 i P1 08 5 5 83 P 64621A STATE CONTROL tr z o MAINFRAME INTERFACE TEST 1 Block Diagram Component Locator SAC 8 56 P O A1 STATE ANALYSIS CONTROL BOARD 64621 66503 MAINFRAME WRITE INTERFACE LWTHS2 78 1 14 5 4 N H 6 LOAD 9K 5 ADDRESS LATCHES 1080 5 wo n Nu m 1 1 LWATSTB TTL ECL wo LWOCMU 8 4 LWOCML gt 4 L LWSEGMU gg LWSEGML 59 3 CONTROL REGISTER 2 D FF PBRSTB 702 5 7 9 m Q ro U420 LSTATE 6 1
22. fete x Ilo m ou Su Du gt 1 lt Nju O 2r amp 2r H gt gt 1 gt ss Wami Os T5 74 T2 T 64621 66501 Q rjc lt 416 200 amp or 51 De 0r Ds are STATE CONTROL BOARD lt 3 ur mju Olina Mju om LME 7008 O zlelels REV lt 0 o gt j an a O 3a lero OJI IT Im F CLOCK POD ji LTE 10 U FS1 FS FS2 LSE 04 Us us u7 us I e 5 4 me LL n U10 11 12 STROBES Test sj UTR sue ti a PREPROCESSOR CLOCK Om epee r F gies INTERFACE PROBE HMCLK STROBE NE Pare eee 016 Ui7 U19 d 020 021 022 U23 m 924 5 hi IB BUS E N zga i INTERFAC GENERATOR HQWRITE HWQ U31 J 032 3 U33 j U34 i 13 vit ULT E TEST 11 TEST 1 9 26 E E 2 2 e Tap 8 L 8 T 5 u44 u45 u47 u50 vel T 5 ed U40 042 21 STROBES A C30 C31 C32 C33 C34 5 SR ow N e N 9 N C28 use 3 C29 usy eo 1 m i 1 i P a m m 2 a u70 Uri u72 U73 5 8 D COUNT STATUS i ie Sains Ou MERO COUNTER MEMORY Pi e e 1 TEST 5 7 TEST 6 ir r BNC 081 082 083 084 085 087 088 CONTROL ae edt SA CLOCK po T C47 C48 49 Ec 2 O n37 46 R3s Ra9 R40 Uit U113 0
23. 9 H410 TA 6297 29Hh AU30 583 C6U5 ECL ECL ECL ECL ECL ECL ECL ECL sac 4 41 Model 64621A Performance Verification Board 64621 66503 Test 4 Loop D VH AU30 MODE EDGES THRESHOLDS CONNECTIONS Normal Clock Positive Data High ST SP Start TP19 Start Positive Data Low Qual Stop TP19 Stop Negative Clock TIL Clock U99 pin 3 ST SP QL TIL Ground GND TP levels except where noted U 98 10 2277 U102 3 F89F U118 11 0000 U 98 12 9339 0102 6F58 TOTLZ 98693 U 98 13 664F 0102 5 28H4 U 98 14 664F U102 6 HF93 0121 1 87P 4 0102 7 29H4 U121 2 6291 U100 1 PACS U102 9 9339 U121 3 Hh10 U100 2 9147 U121 h U100 3 F89F U104 1 29H4 U121 5 0 9 1100 h 87P4 U104 2 AU30 U121 6 5U93 U100 5 87P4 TOTLZ 531 U121 7 U100 7 25 2 0104 11 19PU U121 8 6093 U100 9 1852 0104 12 83H3 0121 9 8401 0100 10 high 0104 13 0 71 0121 11 8401 1100 11 high 0104 14 OTHO U121 12 6093 0100 12 CAI 0104 15 P17F 0121 13 70CH 0121 14 5093 U101 1 5 U105 1 29H4 U121 15 0 9 0101 2 9147 U105 2 AU30 0121 16 FP49 U101 3 F89F 0105 10 P17F 0121 17 H410 U101 h 6F58 0105 11 33 6 0121 18 6297 0101 5 28H4 0105 12 6 0121 19 0000 0101 6 7343 1105 13 20 0101 7 H488 1105 14 6509 0122 1 25 2 0101 9 UC61 0105 15 5 0122 h C6U5 0101 10 918 0122 16 H410 0101 11 5388 U106 2 F368 U101 12 6 U106 3
24. A s gt 2 2 w gt o a 5 9 xE m 2 olze Ole ORE 4 1 lt oiu zu e e gt c3 T5 T4 T3 T2 64621 66501 MP2 2 Tic c oa 7 er Zoo c DE ZIO OG PDC 4 R2 9 STATE CONTROL BOARD a d HJI we mlu lt LME BETS MES a O o nn N Ojo Alcoa OT II LTE 1 FS1 FS FS2 va us ve u7 25 d eng UE js 58 sie CO A TEST 8 HTR G ETE a o z ll 22 fee EN ra PREPROCESSOR CLOCK STROBES ieee EINE INTERFACE PROBE HMCLK STROBE CONTROL ANALYSIS u16 vr vis violi uo luz uzs in i fuz amp mE 2 i 2 T In BUS INTERFACE GENERATOR LINES CONTROLLER HQWRITE HWQ cia Q1 U31 Y U32 U33 j U34 TP13 ed m 5 E be n ne E TP12 sos c TEST 11 TEST 1 9 T Bu MEET REA w ww and m i 2 n F 5 043 044 045 050 052 oe 9
25. ECL U 40 9 H772 U 58 3 low ECL U 61 3 low ECL U 40 10 FFO8 ECL U 58 4 ECL U 61 4 Hh10 ECL U 40 11 7933 ECL U 58 5 5093 ECL 0 61 5 6297 ECL U 40 13 741A ECL U 58 6 ECL 0 61 6 H31H U 40 14 ECL U 58 A2UF ECL 0 61 A2UF ECL U 40 15 4FUF ECL U 58 9 TF78 ECL 0 61 9 8 ECL U 40 16 0837 ECL U 58 10 PC61 ECL U 61 10 PC61 ECL U 10 17 3500 ECL U 58 11 6U93 ECL 0 61 11 9 U 40 18 6093 U 58 12 8401 U 61 12 0 9 ECL U 40 19 8401 ECL U 58 13 58 9 ECL U 61 13 4022 U 40 21 ECL 58 14 HT7UO ECL U 61 14 2A78 ECL 40 23 3HA7 ECL U 58 15 6261 ECL U 61 15 113C ECL 0 2 2 PC61 ECL 59 1 55 ECL U 62 5 5388 U 42 4 8 ECL U 59 2 4685 ECL U 62 7 PF6C U 42 6 6297 ECL U 59 3 low ECL U 62 10 58 9 2 7 Hh1O ECL 59 4 ECL U 62 11 1022 U 2 8 5388 ECL 59 5 5093 ECL U 42 9 H772 ECL U 59 6 H31H ECL U 62 1 PF6C ECL U 42 10 FFO8 ECL 59 7 A2UF ECL U 62 2 5388 ECL U 42 11 7933 ECL U 59 9 8 ECL U 62 14 4022 ECL U 42 13 741A ECL U 59 10 PC61 ECL U 62 15 58C9 ECL U 42 14 ECL U 59 11 6093 ECL U 42 15 4FUF ECL U 59 12 8401 ECL 0 63 5 6297 U 42 16 0837 ECL 0 59 13 1022 ECL U 63 7 Hh10 U 42 17 3500 ECL U 59 14 82 0 ECL U 63 10 0 9 U 42 18 ECL U 59 15 FP66 ECL U 63 11 9 0 42 19 0 9 ECL U 42 21 A2UF ECL U 60 1 2 9 ECL U 63 1 Hh10 ECL U 42 23 H31H ECL U 60 2 HP6A ECL U 63 2 6297 ECL 0 60 3
26. Pte Ltd 08 00 Inchcape House 450 2 Alexandra Road Alexandra P O Box 58 SINGAPORE 9115 Tel 4731788 Telex 34209 HPSGSO RS Cable HEWPACK Singapore A C E M P Dynamar International Ltd Unit 05 11 Block 6 Kolam Ayer Industrial Estate SINGAPORE 1334 Tel 747 6188 Telex 26283 RS CM SOUTH AFRICA Hewlett Packard So Africa Pty Ltd P O Box 120 Howard Place CAPE PROVINCE 7450 Pine Park Center Forest Drive Pine lands CAPE PROVINCE 7405 Tel 021 53 7954 Telex 57 20006 A C CM E M P Hewlett Packard So Africa Pty Ltd 2nd Floor Juniper House 92 Overport Drive DURBAN 4067 Tel 031 28 4178 Telex 6 22954 Hewlett Packard So Africa Pty Ltd 6 Linton Arcade 511 Cape Road Linton Grange PORT ELIZABETH 6001 Tel 041 301201 Telex 24 2916 SALES amp SUPPORT OFFICES Arranged alphabetically by country SOUTH AFRICA Cont d Hewlett Packard So Africa Pty Ltd Fountain Center Kalkden Str Monument Park Ext 2 PRETORIA 0105 Tel 012 45 57258 Telex 3 21063 CE Hewlett Packard So Africa Pty Ltd Private Bag Wendywood SANDTON 2144 Tel 802 5111 802 5125 Telex 4 20877 SA Cable HEWPACK Johannesburg A C CM E M P SPAIN Hewlett Packard Espafiola S A Calle Entenza 321 08029 BARCELONA Tel 3 322 24 51 321 73 54 Telex 52603 hpbee ACEMP Hewlett Packard Espafiola S A Calle San Vicente S N Edificio Albia II 7B 48001 BILBAO Tel 4 423 83 06
27. g aq DI qd g DI a a lo 098 u99 9100 9101 0102 0103 0104 0106 0107 0108 U110 N ora n e 2 toe e em css T 846 56 R47 5 gcc lt e Q R45 0128 849 J 7 Q 3 s s CONTROL 2 a Di ta O du AREIS TP17 67 ADDRESS ssi eo ew cH D on dem C60 SA START STOP 1 13 35 53 59 69 79 8385 i P1 j 08 5 5 83 P I 64621A STATE CONTROL 5 5 a MAINFRAME INTERFACE TEST 1 Block Diagram Component Locator SAC 8 54 0 1 STATE ANALYSIS CONTROL BOARD 64621 66503 MUX TRACE COUNT STATUS MEMORY 15 TRACE COUNT 3 READ ADDRESS i pi REGISTER D FF 1N en 7o PRSTE fat be V 86 LAB4 18 19 LABS 17 LABS 14 5 Y b v 5 v 88 5 0 vj LABA4 41 8 es LRMACR 9 TRACE MEMORY ADDRESS SELECTOR WRITE READ TRACE MEMORY ADDRESS COUNTER READ REGISTER PMACRS 7 2 s U66B NMACRS 6 nJ ECL 2 N TTL 9 O 6 5 P O 1 U66 2 WRITE 3 READ N e TRACE POINT R46 2K REGISTER 14 5 43 HOWRITE 10N TRACE COUNT STATUS MEMORY ADDRESS COUNTER LTCSMS0 3 4 LTCSMSO posters 20 ii TRACE POINT LATCH 155027 LTRCP
28. 1826 0544 1810 0298 1810 0298 1810 0298 810 0298 1810 0298 1816 1462 1810 0298 1816 1462 1910 0298 1816 1462 1810 0298 1816 1462 1920 0806 1820 0802 1820 1400 1810 0219 1820 0809 1810 0219 1810 0219 1820 0809 1810 0219 1820 1173 1820 2024 1826 0856 1826 0856 1810 0273 1810 0302 1816 1338 1816 1338 1816 1338 1816 1338 1820 1173 1820 1173 1820 1173 1820 1052 1820 1052 1820 1997 1820 1997 1820 1997 1816 1308 1816 1308 1816 1308 1816 1308 1820 1052 1810 0273 1810 0273 siena bill dd OD CQ on M ILES et et oa oonan 10 SIATE ANALYZER CONTRULILE NETWORK 10 P470 0 OHM X NETWORK 10 SrP240 0 OHM X MISC EC 14 TNP GATE ECL AND QUAD 2 INP IC GATE ECL NOR QUAD 2 INMP IC ECL 14 TNP GA TTL QUAD 2 IND NETWORK RES 10 5IP240 0 Chm NETWORK RESG 10 S81P10 0K OM NETWORK REG 19eSTP10 9K GHM NETUORK RES 0 51P47 0 OHM X 4 NETWORK REG 10 8IP240 0 CHM X IC GATE TTL AND QUAD 2 INP NETWO RK RESG 10 81P470 0 Qum X GATE DR QUAD 2 INP IC CNTR ECL BIN SYNCHRO POS EDG TC ENIR ECL BIN SYNCHRO POS FDGE GATE ECL NOR QUAD 2 INP IC GATE NOR QUAD 2 INP 28480 00121 91121 07263 14715 04713 07243 01295 01121 03321 01121 01121 91121 01295 03121 04713 TRIG 07243 TRIG 072635 04713 04713 LOH ECL D TYPF POS EOGE TRIG DUAL 04713 LCH ECL De TYPE POS CDGE TRIG DUAL 04212 FF ECL D M S DUAL I
29. 301 644 5800 Telex 710 862 1943 A C CM E M Hewlett Packard Co 2 Choke Cherry Road ROCKVILLE MD 20850 Tel 301 948 6370 A C CM E M Massachusetts Hewlett Packard Co 1775 Minuteman Road ANDOVER MA 01810 Tel 617 682 1500 A C CM E M P Hewlett Packard Co 32 Hartwell Avenue LEXINGTON MA 02173 Tel 617 861 8960 CE Michigan Hewlett Packard Co 4326 Cascade Road S E GRAND RAPIDS MI 49506 Tel 616 957 1970 CM Hewlett Packard Co 39550 Orchard Hill Place Drive NOVI MI 48020 Tel 313 349 9200 Hewlett Packard Co 1771 W Big Beaver Road TROY 48084 Tel 313 643 6474 C Minnesota Hewlett Packard Co 2025 W Larpenteur Ave ST PAUL MN 55113 Tel 612 644 1100 A C CM E M Missouri Hewlett Packard Co 1001 E 1015 Terrace Suite 120 KANSAS CITY MO 64131 3368 Tel 816 941 0411 A C CM E M a Hewlett Packard Co 13001 Hollenberg Drive BRIDGETON MO 63044 Tel 314 344 5100 A C E M Nebraska Hewlett Packard 10824 Old Mill Rd Suite 3 OMAHA NE 68154 Tel 402 334 1813 New Jersey Hewlett Packard Co 120 W Century Road PARAMUS NJ 07653 Tel 201 265 5000 A C CM E M Hewlett Packard Co 20 New England Av West PISCATAWAY NJ 08854 Tel 201 562 6100 A C CM E New Mexico Hewlett Packard Co 7801 Jefferson N E ALBUQUERQUE 87109 Tel 505 292 1330 New York Hewlett Packard Co 5 Computer Drive South ALBANY N
30. 999 NL 1183 AMSTELVEEN The Netherlands Tel 20 437771 Telex 18 919 hpner SOUTH EAST EUROPE Hewlett Packard S A World Trade Center 110 Avenue Louis Casai 1215 Cointrin GENEVA Switzerland Tel 022 98 96 51 Telex 27225 hpser MEDITERRANEAN AND MIDDLE EAST Hewlett Packard S A Mediterranean and Middle East Operations Atrina Centre 32 Kifissias Ave Paradissos Amarousion ATHENS Greece Tel 682 88 11 Telex 21 6588 HPAT GR Cable HEWPACKSA Athens UNITED KINGDOM Hewlett Packard Ltd Nine Mile Ride Easthampstead WOKINGHAM Berkshire IRGII 3LL Tel 0344 773100 Telex 848805 EASTERN USA Hewlett Packard Co 4 Choke Cherry Road ROCKVILLE MD 20850 Tel 301 258 2000 MIDWESTERN USA Hewlett Packard Co 5201 Tollview Drive ROLLING MEADOWS IL 60008 Tel 312 255 9800 SOUTHERN USA Hewlett Packard Co 2000 South Park Place P O Box 105005 ATLANTA GA 30348 Tel 404 955 1500 WESTERN USA Hewlett Packard Co 3939 Lankershim Blvd P O Box 3919 LOS ANGELES CA 91604 Tel 213 506 3700 OTHER INTERNATIONAL AREAS Hewlett Packard Co Intercontinental Headquarters 3495 Deer Creek Road PALO ALTO CA 94304 Tel 415 857 1501 Telex 034 8300 Cable HEWPACK ANGOLA Telectra Angola LDA Empresa Tecnica de Equipamentos Rua Conselheiro Julio de Vilhema 16 Caixa Postal 6487 LUANDA Tel 35515 35516 Telex 3134 ARGENTINA Hewlett Packard Argentina S A Montaneses
31. CHAN B CLK so il 225nS 25nS 5 1 4V CHAN A Figure 4 10 BNC Port 2 Waveform j Verify that Port 2 output for Measurement Complete has a time delay td of 225 nS 25 nS k Press halt 1 Press assert bnc_port_2 on trace point m Press execute repetitively n Press trace specification o Using Oscilloscope set up of previous measurement measure time delay td p Verify that Port 2 output for Trace Point has a time delay td of 225 nS 25 nS SAC 4 15 Model 64621A Performance Verification 4 17 TROUBLESHOOTING 4 18 General Comments If the operation verification failed troubleshoot the first test that failed then re run operational verification The automatic tests listed in Figure 4 11 are interdependent 50 that all tests preceeding a given test must pass for the given test to pass 10 MHz State Test Board in Slot 2 Pass Tested 1 Failed 0 Test Slot 2 State Control and Clock Tested Failed Automatic Tests 1 Mainframe interface and stimulus 1 0 2 Control IC shift register 1 0 3 Clock IC shift register 1 0 4 Sequencer 1 0 5 State count 1 0 6 Trace memory 1 0 7 Other counter tests 1 0 8 Intermodule Rus 1 0 Manual Tests 9 Strobe generator calibration 0 10 Threshold circuit calibration 0 11 interface data hus stimulus 0 12 Rear panel PORT stimulus 0 Figure 4 11 Automatic Tests 4 19 Tests 9 and 10 are used in Chapter V Adjustment
32. Converters DACs The Strobe Generator is also exercised 4 27 How the Slow Clock Dectector is reset then a Performance Verification Strobe PPVSTB is written to the Strobe Generator This triggers the Slow Clock Detector monostable and its status is read at the Analysis Status Buffer 4 28 Results Strobe Request passes if the monostable is read high Release data bus is a read of the mainframe data bus when nothing is addressed Failure indi cates that a card in the cardcage is causing problems on the data bus The stimulus portion of this test is write only therefore no results are given for it 10 MHz State Test Board in Slot 2 Pass Tested 1 Failed 0 Slot 2 State Control and Clock Test 1 ainframe interface and stimulus Strobe Request Pass Release data bus 0000000000000000 Figure 4 12 Mainframe Interface 4 29 Stimulus A staircase ramp is produced by the DACs TP11 amp TP12 during this test See Figure 4 13 The DACs are also stimulated by test 10 The Sequencer is exercised in a write only mode during this test in order to break its feedback loops This test loads the Sequence Transition Memories and the Sequence Occurrence Counter Memories then stimulates the Sequencer by operating the Sequence State Latch Counter in the count mode HLD asserted Loopback occurs when the State Latch Counter latch the next state from their parallel inputs HLD is not asserted 4 2 V Ve 42 Figure 4
33. G x 1 8 LPPBEN PREPROCESSOR DATA BUFFER 8 LRSTB m PREPROCESSOR ADDRESS BUFFER LL e ST ENI 19 P O U53 5 gt 2 v 18 Lo b 1 8 G 082 7 086 3 gt 087 2 7 8 On BE CLOCK THRESHOLD DIGITAL TO ANALOG CONVERTERS R26 51 1 DB3 6 V 3 0 iL B dir WW ee ne rro Hu d EHE R27 4 75K B Hime COMP 637 27 415 Ni rvaer 3 R33 5 44K 45 V D A CONV 1 DBO 9 m los R23 SR li 500 0 2 101 cC M CDM M ET uc Er dE B s i eK PREPROCESSOR CONTROL 6 La HENSTIM 9 U129 alto o Qu 2 Eun pt al 8 99 5 PHALT 5 8 lt 4 d e TP18 PREPROCESSOR SA CLOCK CLOCK TERM GENERATOR u25 PCT 9 90 29 26 28 HUM HCDO 1 9 e TP11 VTHSH2 V 33 X KEYBOARD ENTRY 6NDSEN HMCLK 2 ICs ON THIS SCHEMATIC REF DES HP PART MFG PART NO INB4 5011 INB4 5011 1820 2075 7415245 1826 0271 SN72741P 1820 2024 7415244 1826 0856 6080 1820 1197 741500 1820 1173 10124 PARTS THIS SCHEMATIC C12 36 37 CR1 2 J3 R19 34 48 49 54 57 TP11 12 U10 11 25 30 35 53 55 99 128 129 wi POWER SUPPLY CONF
34. GND u128 149 d O gt CONTROL 0115 0116 U117 U124 0127 U118 0119 0120 0122 18 P17 c67 R54 C64 C58 61 _ p59 R53 5 59 R50 62 TP19 C63 rse C65 c60 START STOP 69 RS1 ADDRESS R57 66 8 C 8 2 3 5 5 83 64621 STATE CONTROL N N 4 MAINFRAME INTERFACE TEST 1 Block Diagram Component Locator SAC 8 58 P O 1 STATE ANALYSIS CONTROL BOARD 64621 66503 MAINFRAME READ INTERFACE D CPU READ DECODER 6 8 LADEN _ a ER 1 LABS 2 Ja LABiO 3 8 LABB 10 2 POSTB 2 NDSTB 7 55 CD0 7 2 1 50805 2 1550 7 TRACE DATA READ REGISTER D v e rs q o y 15 LDB2 12 1083 d 9 084 d 6 LDB5 ovis SEQUENCE READ REGISTER ANALYSIS STATUS BUFFER TRACE COUNT STATUS MEMORY SELECTOR Model 64621A Service ICs ON THIS SCHEMATIC REF DES HP PART NO MFG PART NO 1820 1052 10125 1820 1997 7415374 1820 1216 1415138 1820 1281 1415139 1820 1282 1418109 1820 2024 7415244 LRMACR LRTPRG PARTS ON THIS SCHEMATIC R37 40 47 U65 66 69 89 100 106 107 122 POWER SUPPLY CONFIGURATION 5 U69 89 122 49 U100 106 107 5 9 8 16566 16 Figure 8 19 Mainfram
35. Hewlett Packard Co Kawaiahao Plaza Suite 190 567 South King Street HONOLULU HI 96813 Tel 808 526 1555 Idaho Hewlett Packard Co 11309 Chinden Blvd BOISE ID 83707 Tel 208 323 2700 Illinois Hewlett Packard Co 304 Eldorado Road P O Box 1607 BLOOMINGTON IL 61701 Tel 809 662 9411 CM Hewlett Packard Co 525 W Monroe 1308 CHICAGO IL 60606 Tel 312 930 0010 C Hewlett Packard Co 1200 East Diehl Road NAPERVILLE IL 60566 Tel 312 357 8800 C Hewlett Packard Co 5201 Tollview Drive ROLLING MEADOWS IL 60008 Tel 312 255 9800 Telex 910 687 1066 A C CM E M Indiana Hewlett Packard Co 11911 Meridian St CARMEL IN 46032 Tel 317 844 4100 A C CM E M Hewlett Packard Co 3702 Rupp Drive WAYNE IN 46815 Tel 219 482 4283 CE lowa Hewlett Packard Co 4070 22nd Av SW CEDAR RAPIDS IA 52404 Tel 319 390 4250 Hewlett Packard Co 4201 Corporate Dr WEST DES MOINES IA 50265 Tel 515 224 1435 Kansas Hewlett Packard Co 7804 East Funston Road 203 WICHITA KS 67207 Tel 316 684 8491 Kentucky Hewlett Packard Co 10300 Linn Station Road 100 LOUISVILLE KY 40223 Tel 502 426 0100 Louisiana Hewlett Packard Co 160 James Drive East ST ROSE LA 70087 P O Box 1449 KENNER LA 70063 Tel 504 467 4100 Maryland Hewlett Packard Co 3701 Koppers Street BALTIMORE MD 21227 Tel
36. LOVEN is developed in the Sequencer Low Overview Reset developed in the Sequencer and used only in the 20 Channel Data Acquisition Board LOVRST is used to reset the Overview Counter Low Power On Preset when low during Mainframe power up or during A C power line disturbances LPOP resets various latches counters and registers to a known state When LPOP returns to a high state the Mainframe begins executing software Low Preprocessor Buffer Enable when low LPPBEN enables the Preprocessor Data and Address Buffers to allow information to be transferred to from the Preprocessor Low Preprocessor Strobe developed in the Mainframe Interface Circuits LPPSTB develops HTCLK LTCLK LPPSTB transfers data to from the State Analyzer and the Preprocessor Low Register Clock a clock developed from the CPU s Address Bus and LWRT LRC is used to latch information from the CPU s Data Bus into Control Registers U120 and U123 generating various control signals for the State Analyzer Control Board Low Read Enable developed in the Mainframe Interface Address Decoder When low LRDEN enables the CPU Read Decoder The CPU Read Decoder in turn selects one of five registers or buffers to place information from the Control Board onto the CPU Data Bus Mnemonic LRMACR LRSQRG LRSTB LRSTS LRSTSS LRTDR LRTPRG LRUN LSCE LSCLK LSE LSEL Model 64621A Service Table 8 1 Mnemonics Cont d Descri
37. LTE LTP LTRCP LWOCML LWOCMU LWRAP LWRT LWRTB LWRTSTB select the Trace Counter Status Memories Low Trigger Enable LTE is one of the bidirectional signals that make up the Intermodule Bus IMB When LTE is low the Trigger Recognition func tion is enabled in the State Analyzer LTE is wire ORed with other modules Low Trace Point LTP is normally high The transition from high to low indicates that the State Analyzer has found the Trigger Event requested by the user Low Trace Point LTRCP is normally high The transition from high to low indicates that the State Analyzer has found the Trigger Event requested by the user LTRCP is returned to the CPU through the Analysis Status Buffer Low Write Occurrence Memory Lower when low the CPU can load information into the Lower Sequence Occurrence Memories LSEQDO 7 Low Write Occurrence Memory Upper when low the CPU can load information into the Upper Sequence Occurrence Memories LSEQDO 7 Low Wrap a status signal returned to the CPU at the CPU s request When low LWRAP indicates that the Trace Counter Status Memories are full of information Low Write one of the control lines from the Mainframe When low the CPU is writing to the addressed device i e the State Analyzer Control Board Low Write Buffered one of the control lines from the Mainframe with ad ditional buffering When low the CPU is writing to the addressed device i
38. U 80 MO E C0 e P aac 1 PRR 1 1 C c lt cC c c q btu PRR 1 1 1 PR OO w CO CO Co WWW Co 1 1 TO fO N ro ro N N N 1 WPOVQAUIE WROONKS GOGG 82P0 1628 OF 48 3357 8390 498 AU30 8390 OH42 4 98 3357 UN6F OH42 U15C Uh6F HP A A2H9 F7P6 2708 1628 4 98 U15C 3357 8ccc 19UP 113C 2A78 1628 9 UFUF 0837 9hFH UFUF 0837 Model 64621A Performance Verification Test 4 Loop D VH AU30 CONNECTIONS ST SP Start TP19 Qual Stop TP19 Clock U99 pin 3 Ground GND TP ECL U 84 4 ECL U 84 5 U 84 12 ECL U 84 13 ECL ECL U 84 3 ECL U 84 7 ECL U 84 11 ECL U 84 15 ECL U 85 5 ECL U 85 7 ECL U 85 10 ECL U 85 11 ECL ECL U 85 1 ECL U 85 h U 85 12 ECL U 85 13 ECL ECL U 89 1 ECL U 89 2 ECL U 89 3 ECL U 89 4 ECL U 89 5 ECL U 89 6 U 89 7 ECL U 89 8 ECL U 89 9 ECL U 89 11 ECL U 89 12 ECL U 89 13 ECL U 89 14 ECL U 89 15 ECL U 89 16 U 89 17 U 89 18 U 89 19 U 98 1 U 98 5 ECL TOTLZ ECL U 98 7 ECL ECL 3500 H772 FF08 7933 3500 H772 FF08 7933 Hh88 hh8rF C918 UC61 hh8F 7cc8 1628 5451 1852 8401 7933 FF08 6U93 70CH H772 3500 5U93 PCCF 0 9 0837 UF LE
39. rricesa nesoURcE TRIGGER TRIGGER RESOURCE TERM 0 7 HCQ HPLS LSFLG SEQUENCE PATTERNS LBSP 0 2 LSOCE WRITE SEQUENCE SEQUENCE LSE QUAL HwQ OCCURRENCE CARRY 1 STATE TSS0 7 TRANSITION GATING HBQWRT BUS SEQUENCE STATE BSS 0 3 COUNTER 28 _voc NTR 5 2V 3 VEE TTL 25 24 92 VEE 14 GND 31 GND LOVEN LOVRST POST TO 20 TRACEPOINT CHANNEL COUNTER MEASUREMENT COMPLETE ANALYZER ENABLE N LRUN L TTL ANALYZE ANALYZER ANALYZER ENABLE ENABLE HHOWHT LME IMB DRIVE HWRT PSOCINC 4 IMB IMB LTE HTR LSE PIPELINE REGISTER NOT PART OF ANALYSIS CONTROLLER LDB0 TTL PWAC TTL LLD TTL 7 Figure 8 9 Analysis Controller Block Diagram SAC 8 23 Model 64621A Service 8 116 STATE TIME COUNTER 8 117 Description 8 118 The State Time Counter is a custom designed 20 bit Gray Code counter with prescale The prescaler allows it to count up to 750 000 000 000 states in the count states mode and 8 hours at a 25 MHz rate in the count time mode Externally the Counter is ECL except for three TIL inputs Internally it is emitter functional logic EFL Chip delay from clock edge to counter outputs is approximately 25 nS without prescale With prescale chip delay can exceed 100 nS There are 5 prescale factors 1 divide by 1 2 divide by 8 3 divide by 2 e10 h divide by 2 e17 and 5 divide by 2 e2h 8 119 Where Used 8 120 The counter is used on both the 64621A Control Board and
40. 04012 SAO PAULO SP Tel 011 572 6537 Telex 24720 HPBR BR M Datatronix Electronica Ltda Av Pacaembu 746 C11 PAULO SP Tel 118 260111 CM CAMEROON Beriac B P 23 DOUALA Tel 420153 Telex 5351 CP CANADA Alberta Hewlett Packard Canada Ltd 3030 3rd Avenue N E CALGARY Alberta T2A 617 Tel 403 235 3100 A C CM E M P Hewlett Packard Canada Ltd 11120 178th Street EDMONTON Alberta T5S 1 2 Tel 403 486 6666 A C CM E M P SALES amp SUPPORT OFFICES Arranged alphabetically by country CANADA Cont d British Columbia Hewlett Packard Canada Ltd 10691 Shellbridge Way RICHMOND British Columbia V6X 2W7 Tel 604 270 2277 Telex 610 922 5059 A C CM E M P Hewlett Packard Canada Ltd 121 3350 Douglas Street VICTORIA British Columbia V8Z 311 Tel 604 381 6616 Manitoba Hewlett Packard Canada Ltd 1825 Inkster Blvd WINNIPEG Manitoba R2X 1R3 Tel 204 694 2777 A C CM E M P New Brunswick Hewlett Packard Canada Ltd 814 Main Street MONCTON New Brunswick E1C 1 6 Tel 506 855 2841 5 Hewlett Packard Canada Ltd Suite 111 900 Windmill Road DARTMOUTH Nova Scotia B3B 1P7 Tel 902 469 7820 C CM E M P Ontario Hewlett Packard Canada Ltd 3325 N Service Rd Unit 3 BURLINGTON Ontario L7N 3G2 Tel 416 335 8644 Hewlett Packard Canada Ltd 496 Days Road KINGSTON Ontario K7M 5R4 Tel 613 38
41. 13 Stimulus SAC 4 18 Model 6h621A Performance Verification 4 30 Loop A Signature Path for Strobe Request U121 U122 U117 U65 Loop A signature Path for Release Data Bus U121 U122 Loop A Signature Path for Strobe Generator U24 U52 U8 1 101 Loop A Signature Path for DACs 055 U5h 1102 U121 Loop A Signature Path for Sequencer U16 U80 Occurrence Counter Occurrence Count Memories Transition Memories Sequence State Latch Counter Mainframe Interface sac 4 19 Model 64621A Performance Verification 4 31 TEST 2 CONTROL IC SHIFT REGISTER LOOP B 4 32 Purpose to verify that the shift register within the Analysis Controller U1 can be loaded correctly 4 33 How Serial Data is loaded into Ul through pin 20 Pin 18 is the enable and pin 19 is the clock Pin 17 NMC outputs the same data 59 clock cycles later 4 34 Results Register data passes if the shift register overflowed correctly The data is read by the Analysis Status Buffer as the signal NMC memory complete Shift control refers to the testing of the signal LLD 10 MHz State Test Board in Slot 2 Pass Tested 1 Failed 0 Slot 2 State Control and Clock 2 Test 2 Control shift register Register data All 076 Pass 611 i s Pass Patterns Pass Shift control Pass NOTE This tests only the shift register Figure 4 14 Control IC Shift Register 4 35 Loop Signature Path U121 0122 U1 U103 0102 SAC 4 20 Model 6462
42. 16 BIT LEVEL SELECT REGISTER 26 CPU DATA 15 BUFFER Figure 8 3 Clock Term Generator Block Diagram SAC 8 11 Model 64621A Service 8 58 STROBE GENERATOR 8 59 The Strobe Generator develops seven major strobes from HMCLK or PPVSTB and PBSTBRQ see Figure 8 4 1 HSRS 2 HTIMS 3 HOVS 4 HPLS 5 HWRT 6 LMV 7 LDV HMCLK is used to drive the Strobe Generator in the Analyzer s run mode PPVSTB and PBSTBRQ are used in the Performance Verification mode 8 60 Strobe Uses 8 61 HSRS is used to clock the IMB State Recognition Register in the Analysis Control Chip P NBSRS clocks data into the State Recognition Latch Counters on the Data Acquisition Boards 8 62 HTIMS is used to transfer information to the outputs of the Trace State Time Counter 8 63 HOVS is used to develop LBOVEN and PBOVRST LBOVEN and PBOVRST are used the 20 Channel Data Acquisition Board only LBOVEN allows the Overview section to look for its trigger events PBOVRST is used to reset the Overview State Time Counter 8 64 HPLS is used to latch information into the Pipeline Registers on the Control Board and the Data Acquisition Boards 8 65 HWRT is used to time write commands to Trace and Overview Memories These write commands store data in the Memories 8 66 LMV develops P NMACRS P NMACRS is used to latch information from the Trace Count Status Memory Address Counter into the Trace Memory Address Counter Read Register 8 67 LDV is used to
43. 2140 50 1428 BUENOS AIRES Tel 783 4886 4836 4730 Cable HEWPACKARG A C CM E P Biotron S A C l e l Av Paso Colon 221 Piso 9 1399 BUENOS AIRES CM Laboratorio Rodriguez Corswant S R L Misiones 1156 1876 Bernal Oeste BUENOS AIRES Tel 252 3958 252 4991 A Argentina Esanco S R L Avasco 2328 1416 BUENOS AIRES Tel 541 58 1981 541 59 2767 A AUSTRALIA Adelaide South Australia Office Hewlett Packard Australia Ltd 153 Greenhill Road PARKSIDE S A 5063 Tel 272 5911 Telex 82536 Cable HEWPARD Adelaide A C CM E M P Brisbane Queensland Office Hewlett Packard Australia Ltd 10 Payne Road THE GAP Queensland 4061 Tel 30 4133 Telex 42133 Cable HEWPARD Brisbane A C CM E M P Canberra Australia Capital Territory Office Hewlett Packard Australia Ltd 121 Wollongong Street FYSHWICK A C T 2609 Tel 80 4244 Telex 62650 Cable HEWPARD Canberra C CM E P Melbourne Victoria Office Hewlett Packard Australia Ltd 31 41 Joseph Street BLACKBURN Victoria 3130 Tel 895 2895 Telex 31 024 Cable HEWPARD Melbourne A C CM E M P Perth Western Australia Office Hewlett Packard Australia Ltd 261 Stirling Highway CLAREMONT W A 6010 Tel 383 2188 Telex 93859 Cable HEWPARD Perth A C CM E M P Sydney New South Wales Office Hewlett Packard Australia Ltd 17 23 Talavera Road P O Box 308 NORTH RYDE N S W 2113 Tel 888 4444 Telex 21561 Cable HEWPARD Sydney
44. 4 F8CT TOTLZ 200 U123 12 126F U 97 5 9524 U116 8 0000 0123 13 64P2 TOTLZ 400 TOTLZ 400 0123 14 C6F4 U 97 7 0000 U116 9 high TOTLZ 200 0126 5 52F8 U 97 9 0000 U123 1 high 0126 7 F7PF TOTLZ 1 U123 2 low 0126 11 SAC 4 53 Model 64621A Performance Verification NOTES SAC 4 54 Model 64621A Adjustments SECTION V ADJUSTMENTS 5 1 INTRODUCTION 5 2 This section describes adjustments and checks required to return the instrument to peak operating capability after repairs have been made 5 3 The Strobe Generator Adjustment procedure is Test 9 of the Performance Verification and the Threshold Adjustments procedure is Test 10 5 4 SAFETY REQUIREMENTS 5 5 Although this instrument has been designed in accordance with international safety standards general safety precautions must be observed during all phases of operation service and repair of the instrument Failure to comply with precau tions listed in the Safety Summary at the front of this manual or with specific warnings given throughout the manual could result in serious injury or death or damage to equipment Service adjustments should be performed only by qualified ser vice personnel 5 6 EQUIPMENT REQUIRED 5 7 TEST EQUIPMENT 1 41 2 Digit Multimeter accurate to 1 mV Hewlett Packard Model 3466A or equivalent 2 Dual Channel 100 MHz bandwidth Oscilloscope with delta time measurement capabilities accurate to 0 5 ns Hewlett P
45. 4 inches thick around all sides of the instrument to provide firm cushioning and prevent move ment inside container 4 Seal shipping container securely e Mark shipping container FRAGILE to ensure careful handling f In any correspondence refer to instrument by model number and complete repair number SAC 2 5 Model 64621A Installation NOTES SAC 2 6 Model 64621A Operation SECTION III OPERATION 3 1 INTRODUCTION 3 2 The operation of the Model 6h621A is a function of the system software Complete operation from the keyboard of the system is beyond the scope of the Service Manual Please refer to the Operator s Manuals for the procedure SAC 3 1 Model 64621A Operation NOTES SAC 3 2 Model 64621A Performance Verification SECTION IV PERFORMANCE VERIFICATION 4 1 INTRODUCTION 4 2 This section describes the Performance Verification opt_test for Model 64621A State Analysis Control Board This Section consists of three parts 1 Operation Verification 2 Performance Verification and 3 Troubleshooting 4 3 The Operation Verification tests are all automatic and require no test equip ment or dissassembly of the Mainframe The Operation Verification provides a 90 assurance that the Model 64621A meets all specifications 4 4 The Performance Verification tests require test equipment and disassembly of the Mainframe The Performance Verification tests involve manual testing and verification of sp
46. 5 P O 013 13 55 s 47 6 e 2 Oua 12 045 TRACE STATE TIME COUNTER M aa J 6 nie 33 S yer it 10 0129 basen 35 LTRACE HOWRITE 25 bPSET HTIMS 26 LPLATCH ESTATE 8 ON state 8 HLOAD 5 47 HCE 7 Loe Oz E LSFLGB 5 ou LSFLGB HCGB HOTFB 54 7 ECL TTL CNT49 13 ECL TTL ECL TTL 15 ECL TTL CNTO 19 55 7 ICs ON THIS SCHEMATIC REF DES PART NO MFG PART U20 1820 0802 10102 U45 1820 1400 10104 U74 77 94 108 109 110 1820 1052 10125 U127 1920 1208 141532 1820 1173 10124 PARTS THIS SCHEMATIC POWER SUPPLY CONFIGURATION 8 9 120 45 8 U74 77 94 16 108 110 129 N 14 t uz Model 64621A Service Figure 8 16 Trace State Time Counter SAC 8 53 Model 64621A Service TO FROM CLOCK PROBE PREPROCESSOR Z S IMB TO FROM OTHER o m 0 gt gt Q o c e gt gt 2 a ui 5 alo Da O o r m 2 12295 rele
47. 8 8 ST yor 5 2 HCG 4 LSF TTL NMC TTL NTR PORT LATCHES ANALYSIS CONTROLLER LABI 8 1 as R PHALT OF s enm Ed Model 64621A Service ICs ON THIS SCHEMATIC REF DES HP PART MFG PART ul INB4 5010 INB4 5010 1820 1400 10104 1820 0802 10102 1820 1201 741508 1820 1831 10103 1820 1788 10016 1820 1282 7415109 1820 1210 141551 1820 1195 1415175 1820 0780 8831 PARTS THIS SCHEMATIC C15 CR3 J1 2 01 R1 35 42 43 45 TP3 5 7 8 10 U1 7 12 13 14 15 16 18 31 41 97 116 123 126 POWER SUPPLY CONFIGURATION U5 6 16 18 14 5 7 0116 Figure 8 15 Analysis Controller SAC 8 51 lt lt PREPROCESSOR INTERFACE LDBO 7 BUS TEST 11 LAB0 3 ADD TO FROM CLOCK PROBE CONTROL m 79 O m o o l o I Y d gt j CLOCK PROBE HMCLK INTERFACE LDBO 11 STROBE GENERATOR TEST 1 9 STROBES o O Al ul z Oz o nieg O 5 oju Es 2r gt gt SIS S E E 2 CINE OE o a Ola Alco OF TI 26 5 oo mjw Jio STROBES CONTROL ANALYSIS LINES CONTROLLER CONTROL BNC CONTROL DATA T T o lt gt o 2 2 o gt o HQWRITE H
48. 8 T0 3481 F 1622 RESISTOR 4 22K 1 at TC 0 100 24546 C4 1 8 TU0 4 21 F AIREZ 2 TSTOR TRMR 500 SIDE ADI 17 02111 4 22501 ALR24 2100 3123 R STOR TRMR 500 2 SIDE ADI 17 02111 432501 AIR25 2100 3123 RESTSTOR TRMR 500 SIDE ADI 17 02111 ABP SOL ALR2S ALR27 ALR28 AIRE 81850 0757 0283 RESISTOR 51 1 1 0 100 24546 4 1 8 0 5101 RESISTOR 4 75K 1 F TC 0 100 24546 4 1 8 70 4751 RESISTOR 4 75K 1 4 0 100 24546 4 1 8 70 4781 RESISTOR 2 17 100 24546 C4 1 8 T0 2001 F RESISTOR 2K 1 125 0 100 24546 4 1 8 0 2001 0 5 6 6 AIRS1 9678 6612 AIRI 0757 0394 A1R33 0757 0438 ALRS4 0757 0438 AIRSS 0752 0394 RESISTOR 2K 4 12 5W F 0 100 28480 0598 6612 RESISTOR 51 1 1 125W 0 100 24546 CA 1 8 TO S1R1 F ISTOR 5 11 1X 129W F T 100 24546 CA 1 8 T0 S111 F RESISTOR 5 11 1X 125W TC 0 100 24546 4 1 8 TO 5111 F RESISTOR 1 1 1 125W F TC 0 100 24546 C4 1 B T0 51R1 F sui A1R36 0095 6612 A1R37 0598 6612 ALRIS 998 6642 1939 0698 6612 A1R40 9998 6612 RESISTOR 2K 4 125W RESISTOR K 125W 1X 1254 SAX X 28480 0698 6612 28480 0698 6612 28480 0698 6612 28480 0698 6612 28480 0098 6612 1641 0698 6612 ALR42 0757 0726 1 43 0678 6612 ALR44 0598 6612 ALR4AS 0678 6612 Ad 28480 0698 6612 24546 C5 1 4 TO 8S11R F 28480 0698 6612 280480 0598 6612 100 28480 0678 6612 STOR 2K STOR 3TSTOR 2K
49. 90 9 H9C2 U 92 12 PUC6 0 86 16 1AP8 U 90 10 0F8U U 92 13 0405 U 86 17 90 11 5AP4 U 92 14 U87C U 86 18 6FlC U 90 12 PUC6 U 92 15 UAFH U 86 19 2789 U 90 13 884A 0 92 16 FFFP 0 90 14 U87C U 92 18 05 U 87 1 894H U 90 15 H244 U 92 20 894H TOTLZ OFLO U 90 16 FFFP TOTLZ 1796 U 87 2 7153 U 90 18 63PH U 92 21 3781 U 87 3 2789 U 90 20 89hH U 87 APFh TOTLZ 1796 U 93 1 8989 U 87 5 COUF U 90 21 3781 U 93 2 50P9 U 87 6 1AP8 U 93 3 93A5 U 87 7 93A5 U 91 1 8989 U 93 4 U 87 9 50P9 U 91 2 50 9 U 93 5 C6H0 U 87 10 9 U 91 3 93A5 U 93 6 U 87 11 9163 U 91 4 APFh U 93 7 6 U 87 12 8989 U 91 5 6 0 U 93 9 10214 87 13 00 U 91 6 U 93 10 0F8U U 87 14 H219 U 91 7 6HFO U 93 11 160 U 91 9 0405 U 93 12 PUC6 U 88 1 894H U 91 10 0F8U 0 93 13 UOFP TOTLZ OFLO U 91 11 UAFH U 93 14 U87C U 88 2 7233 U 91 12 PUC6 0 93 15 934P U 88 3 CPFF U 91 13 8 6 U 93 16 FFFP U 88 4 3781 U 91 14 U87C 0 93 18 U 88 5 OUHO U 91 15 1 56 U 93 20 894H U 88 6 3U9H 0 91 16 FFFP 2 1796 U 88 T 0 91 18 018 U 93 21 3781 U 88 9 U 91 20 894H U 88 10 70 TOTLZ 1796 U 94 14 4214 0 88 11 F989 U 91 21 3781 U 94 5 160 0 88 12 6 0 94 12 UOFP U 88 13 P48H 0 92 1 8989 U 94 13 934P U 88 14 4P69 U 92 2 50P9 92 3 93 5 U 94 3 4214 ECL U 90 1 8989 U 92 h APFY U 94 7 16U4 ECL U 90 2 50P9 U 92 5 C6H0 U 94 11 UOFP ECL U 90 3 9345 U 92 6 U 94 15 934P
50. A C E M Hewlett Packard Espafiola S A Crta de la Corufia Km 16 400 Las Rozas E MADRID Tel 1 637 00 11 Telex 23515 HPE Hewlett Packard Espa ola S A Avda 5 Francisco Javier S N Planta 10 Edificio Sevilla 2 41005 SEVILLA Tel 54 64 44 54 Telex 72933 A C M P Hewlett Packard Espa ola S A Isabel La Catolica 8 46004 VALENCIA Tel 0034 6 351 59 44 CP SWEDEN Hewlett Packard Sverige AB Ostra Tullgatan 3 5 21128 MALMO Tel 040 70270 Telex 854 17886 via Sp nga office CP Hewlett Packard Sverige AB Skalholtsgatan 9 Kista Box 19 S 16393 SPANGA Tel 08 750 2000 Telex 854 17886 Telefax 08 7527781 A C CM E M P Hewlett Packard Sverige AB Fr tallsgatan 30 5 42132 VASTRA FROLUNDA Gothen burg Tel 031 49 09 50 Telex 854 17886 via Spanga office A C CM E M P SUDAN Mediterranean Engineering amp Trading Co Ltd P O Box 1025 KHARTOUM Tel 41184 Telex 24052 CP SWITZERLAND Hewlett Packard Schweiz AG Clarastrasse 12 CH 4058 BASEL Tel 61 33 59 20 A Hewlett Packard Schweiz AG 7 rue du Bois du Lan Case postale 365 CH 1217 MEYRIN 1 Tel 0041 22 83 11 11 Telex 27333 HPAG CH C CM Hewlett Packard Schweiz AG Allmend 2 CH 8967 WIDEN Tel 0041 57 31 21 11 Telex 53933 hpag ch Cable HPAG CH A C CM E M P SYRIA General Electronic Inc Nuri Basha Ahnaf Kays Street Box 5781 DAMASCUS Tel 33 24
51. ADJUSTMENTS TEST 10 a Place the State Analysis Control Board on an extender board The IMB and SEB Bus Cables do not need to be connected b If it is not already disconnected disconnect the Clock Probe Cable from J3 Connect the ground lead of the DMM to the GND TP near U70 See Figure 5 1 Using a jumper wire connect 11 and TP12 together e Connect the positive lead of the DMM to Testpoint 11 f Select opt test press RETURN The display will indicate the option modules present and the card slot number they are located in g Press slot number RETURN Slot number is a number from 1 to 9 equal to the location of the State Analysis Control Board h Press run slot number test 1 0 RETURN CRT should now dis play Test 10 Threshold Circuit Calibration i Each time the RETURN key is pressed the D A Converter will be set to a new value Press RETURN until Reference h 267 V Negative Limit is displayed SAC 5 3 Model 64621A Adjustments j Adjust FS R24 to 4 267 1 mV See Figure 5 1 k Remove the jumper from TP11 and TP12 Positive lead of the DMM remains on 11 1 Continue pressing RETURN until Reference 433 mV ECL 1 3 V is displayed Adjust FS2 R25 to 433 mV See Figure 5 1 Each time RETURN is pressed the D A Converter will be set to a different value Press RETURN six times and verify that the value measured on the DMM is within 3
52. Clock Term Generator U25 returned to the Mainframe Used in Performance Verification to indicate that the Term Generator can respond to the various combinations of clocks and qualifiers input from the Clock Probe or Preprocessor High Clock 0 7 differential LCLKO 7 clock signals or qualifier bits from the user s equipment The eight bits are defined to be clocks or qualifiers by keyboard entry HCLKO 7 may come from either the Clock Probe or the Preprocessor High Count Qualify when high HCQ enables the Trace State Time Counter to increment HCQ develops HCQB The status of HCQ is stored in the Trace Count Status Memory When a high is stored for HCQ the software will add the value one to the stored value in the Trace Count Status Memory High Count Qualify Buffered a flag returned to the CPU When high HCQB indicates that the Trace State Time Counter may have been counting when the user s information was stored High Count Test used when testing the Trace State Time Counter When high HCTST divides the Counter into two ten bit counters HCTST is con trolled by the CPU High Data Valid derived from the Strobe Generator When high HDVLD has latched CDO 7 into the Trace Data Read Register When LRTDR is low the latched information is presented to the CPU over the Data Bus HDVLD is also returned to the CPU through the Analysis Status Buffer indicating that information has been latched into the Trace Data Read Regist
53. Counter U112 on the Control Board and the Counter U23 in the Overview State Time Counter on the 20 channel board 8 12 The Block Diagram is also divided into six sections shown by the red lines These six secitons represent time There are six time periods 1 Clock Qualification 2 Input Data Sampled 3 Decode Trigger Terms and Bucket Generation 4 Pipeline Registers 5 Data Storage Count Enable Determination and 6 Store Data and Output SAC 8 1 Model 64621A Service 8 13 DESCRIPTION 8 14 Time Period 1 8 15 Clock Qualification consists of all the circuitry for setting up the threshold levels for the clock The Data Threshold block sets up the threshold levels for the 20 channels of data addition to the clock threshold circuitry the Control Board portion of this section contains the interfaces to the general purpose preprocessor the interface to the Inter Module Bus IMB and the Clock Term Generator The Clock Term Generator is loaded by the CPU when the clock is specified in the format specification When that specification is satisfied the Clock Term Generator sends out a 15ns pulse to the Strobe Generator which initiates a timing sequence in the rest of the state analyzer 8 16 Time Period 2 8 17 The key to the State Analysis System is the Strobe Generator It provides all the timing signals for the system to insure the proper sequence of events 8 18 The Strobe Generator in Time Period 2 is where th
54. D amp us pum U41 A 6 Uae U49 usi 8 S 1 8 M ri 5 043 044 045 U47 050 052 7 VSS ds gt u36 u40 STROBES 1 C30 C31 C32 C33 C34 end 5 ape pre N e M 9 M CR3 C28 U56 29 ice 1 1 1 1 1 a 067 u68 m U70 971 072 073 Ure cel un mom A d i m o d TRACE TRACE L L STATE TIME COUNT STATUS urs urs Dom oa COUNTER MEMORY r ER E r TEST 5 7 TEST 6 i m i xm Us igs 091 092 U93 F BNC g ure u79 uso ust us2 us3 usa 085 u87 uss CONTROL _ ES u95 ML 47 C48 49 pr 2 45 E J 46 Ras R40 vm u113 g O g F1 8 71 qd F d a 096 U97 9100 U101 0102 9103 0104 U106 U107 bnt rn R42 I deli ree El e ns cs RA 53 54 A m Una 51 C52 55 46 56 4 5 lt 9 gem l rJ Jg e CONTROL 9115 0116 0117 0124 0127 2 x TP17 E am 667 ADDRESS SRI a Sn Ms MELLE CENE TP16 R57 C66 o O a N i N 4 MAINFRAME INTERFACE TEST 1 Block Diagram Component Locator SAC 8 16 Model 64621A Service P O A1 STATE ANALYSIS CONTROL BOARD 64621 66503 SEQUENCER 5
55. E Imtac LLC Box 8676 MUTRAH SULTANATE OF OMAN Tel 601695 Telex 5741 Tawoos On PAKISTAN Mushko amp Company Ltd House No 16 Street No 16 Sector F 6 3 ISLAMABAD Tel 824545 Cable FEMUS Islamabad Mushko amp Company Ltd Oosman Chambers Abdullah Haroon Road KARACHI 0302 Tel 524131 524132 Telex 2894 MUSKO PK Cable COOPERATOR Karachi A E M P PANAMA Electronico Balboa S A Calle Samuel Lewis Ed Alfa Apartado 4929 PANAMA 5 Tel 64 2700 Telex 3483 ELECTRON PG A CM E M P PERU Cla Electro M dica S A Los Flamencos 145 Ofc 301 2 San Isidro Casilla 1030 LIMA 1 Tel 41 4325 41 3705 Telex Pub Booth 25306 PEC PISIDR CM E M P SAMS Arenida Republica de Panama 3534 San Isidro LIMA Tel 419928 417108 Telex 20450 PE LIBERTAD ACP PHILIPPINES The Online Advanced Systems Corp 2nd Floor Electra House 115 117 Esteban Street Legaspi Village Makati P O Box 1510 Metro MANILA Tel 815 38 10 up to 16 Telex 63274 ONLINE PN A C E M P PORTUGAL Mundinter Intercambio Mundial de Com rcio S A R L Av Antonio Augusto Aguiar 138 Apartado 2761 LISBON Tel 19 53 21 31 53 21 37 Telex 16691 munter p M Soquimica Av da Liberdade 220 2 1298 LISBOA Codex Tel 56 21 82 Telex 13316 SABASA A Telectra Empresa T cnica de Equipmentos El ctricos S A R L Rua Rodrigo da Fonseca 103 P O Box 2531 LISBON 1 Tel 19 68 60 7
56. ECL U 90 4 APFh U 92 7 6HFO U 90 5 C6HO U 92 9 UOFP Board 64621 66503 MODE EDGES Normal Clock Positive Start Positive Stop THRESHOLDS Data High Data Low Clock TTL ST SP QL TTL Model 64621A Performance Verification Test 6 Loop F VH 894H QUAL VH PFA4 levels are TTL except where noted U 96 8 TOTLZ U 96 9 U 96 10 TOTLZ U 98 U 98 U 98 U100 U100 U100 U100 U100 U100 U100 U100 N Ov 1 ppp 1 p o 894H OFLO AF2A 0000 OFLO 5006 336 AF2A 80H9 8965 7920 489A 489A high 6CF6 high 027 416P 190 80 9 8965 7920 OHCU F1H7 8A99 5UU6 HATA 894H 1796 F6H1 5UU 5UU 89H 1796 H219 91C3 COUF 1153 9518 1105 1 1105 2 0105 10 0105 11 0105 12 0105 13 1105 15 0105 15 U106 9 0106 10 0106 11 0106 12 0106 13 10106 11 0107 2 0107 3 0107 4 0107 6 0107 10 0107 12 0107 13 0107 11 U108 4 0108 5 0108 12 0108 13 U108 3 0108 7 U108 11 U108 15 U109 4 1109 5 0109 12 10109 13 0110 0110 5 510706 894H 9518 UP69 F989 OUHO 7233 F6H1 63PH PP9C 05C7 018F 8H76 665A C AH C AH FF68 665A 8H76 FF68 CHOP CHOP 0A05 UAFH 8F6A 1F56 0A05 UAFH 8F6A 1F56 HUSA AOCT 4214 16U4 UOFP 3U98 CONNECTIONS ST SP Start TP19 Qual Stop TP19 Cloc
57. ECL TO TTL QUAD 2 INP IC TTL LS D TYPE POS EDGE TRIG FF TTL LS D TYPE PQS FD IC FF TTL LS D TYPE POS EDCE TRIG IC TTL L 1024 1K STAT RAM 75 5 IC TTL L 1024 1K STAT RAM 7 5 IC TTL L 1024 1K STAT RAM TTL L 1024 1K STAT RAM TC XLIR ECL ECL TO TTL QUAD 2 1 NETUORK RES 10 SIP470 0 OHM X 9 NETWCORK RES 10 SIP470 0 OHM X 9 SN 04713 04713 04713 01121 084713 01121 01121 04713 01121 04713 01295 34335 34335 01121 01121 07263 07263 27203 07263 04713 04713 04713 04713 04713 PRISIN 01295 TRIG PRL TN 01295 PR L IN 01295 07263 07243 3 01121 See introduction to this section for ordering information NU4 5010 2104471 2104241 F 1061 MC10104P MCL 0702 F10014PC SN7403N 21042741 21004105 2104103 2005470 2108241 SN74LSUGN 2104471 2 0132 FIACIADE 110401000 MC101029P MCI9102P 01301 0101 01 MOLC ASIP MC10104P iNBA 5018 SN7ALSPASN 2106103 SN72741P SN72741P BC 4021 2106241 2104241 23106241 2105241 2104241 MEMI04 22H 210A241 MUMIUAPDPOH 2104241 MEMIOA4APOH 2106241 MEMIDAZIH 0109P MO10100P 0104 2988221 MC1011S5P 208B221 PARKERI MC10115P PARR MC10124L 94741 52448 AMAOBNAPO AMGIBOAPC 2104471 808 470 10145 10145 10145 10145 MC10124L MC101241 MC10124L MO101251 MC101 251 SN7418374N SN74LS374N SN741 S374N 93LA22PC 931 422PC 93L422PC 9 422
58. Enable and IMB Receive and Drive 8 104 The 58 bit shift register selects which of these sub blocks or inputs will actively be used to produce an output Finally the Sequencer plays a major role in controlling the State Analysis Subsystem and is referenced in the Block Diagram even though it is not physically part of the Analysis Controller 8 105 Resource Allocation On the Acquisition Boards trace data addresses the Resource Pattern Trigger Memories and the Memories output an 8 bit pattern wire ORed accross all boards which forms the Resource Pattern input LBRPO 7 for the Analysis Controller Inside the Analysis Controller these eight signals are allo cated to various functions with the following limitations the sum of the resources cannot exceed eight trigger and store can use up to eight resources count can use up to four resources LBRP2 3 6 7 overview count can use up to four resources LBRPO 1 4 5 four resources can be ranges provided a 20 channel board is present a not condition requires two resources The 58 bit shift register uses 30 bits to specify which terms will be used by which function The following table shows an example for resource allocation STATE RECOGNITION RESOURCES trigger on ADDRESS 4000H and STATUS Mem_read 1 or ADDRESS 4000H and DATA lt gt 0 2 3 or ADDRESS range OH thru OFFH store on ADDRESS range 4000H thru 4135H 5 ADDRESS 0F000H 6 count on ADDRESS 6000H 7 o
59. NO POSTAGE PACKARD NECESSARI IF MAILED IN THE UNITED STATES BUSINESS REPLY CARD FIRST CLASS PERMIT NO 1303 COLORADO SPRINGS COLORADO POSTAGE WILL BE PAID 8Y ADDRESSEE HEWLETT PACKARD LOGIC PRODUCT SUPPORT DEPT Attn Technical Publications Manager Centennial Annex D2 P O Box 617 Colorado Springs Colorado 80901 0617 FOLD HERE Your cooperation in completing and returning this form wil be greatly appreciated Thank you READER COMMENT SHEET Service Manual Model 64621A State Analysis Control Board 64621 90903 June 1983 Your comments are important to us Please answer this questionaire and return it to us Circle the number that best describes your answer in questions 1 through 7 Thank you 1 The information in this book is complete Doesn t cover enough 12 3 4 5 Covers everything what more do you need 2 The information in this book is accurate Too many errors 1 2 3 4 5 Exactly right 3 The information in this book is easy to find can t find things need 1 2 3 4 5 can find info quickly 4 The Index and Table of Contents are useful Helpful 1 2 3 4 5 Missing or inadequate 5 What about the how to procedures and examples No help 12 3 4 5 Very helpful Too many now 1 2 3 4 5 I d like more 6 What about the writing style Confusing 1 2 3 4 5 Clear 7 What about organization of the book Poor order 1 2 3 4 5 Good order 8 What about the size of the book too big small 12 3 4 5 R
60. NPN ST PD 350MW FT 300MHZ 04713 245904 GIRI 0757 0394 i RESISTOR 51 1 1 125M F TC 04 100 24546 CA 1 8 TYO SIR T F ALRe 0698 6612 STOR 2K 1 1254 F 0 100 28480 0698 6612 AIRS 0698 6612 STOR 2K 17 1254 0 100 28480 Uov8 60612 164 2100 3123 ESISTOR TRMR 500 10 C SIDE ADI 02111 S01 AIRS 2100 3123 SISTOR TRMR 500 10 C STOE ADJI TRN 02111 43PS01 ALTRO 2100 3123 AIR 2100 3123 ALRS 2100 3123 AIRY 0698 6612 ALR10 0098 6612 RESTSTOR TRMR 500 STDESADI 17 02111 450501 RESTSTOR TRMR 500 STUE ADJ 17 TRN 02111 01 RESISTOR TRMR 500 A SIDE ADJ 17 TRN 02111 ARP SOL 2515 PK 4 125W F 28480 0078 6612 1 1254 F 0 100 28480 0698 6612 proso AIRII 752 0394 A1R12 394 A1R13 0598 3447 ARIA 0757 0346 AIRIS 0757 0346 STOR 51 1 1 1254 F TC 94 24546 C4 1 8 TO SIR t F ISTOR 51 1 1 24546 UG lt 511 F ISTOR 422 1 24546 4 1 8 0 4228 F SISTOR 10 1 1254 24546 C4 1 8 T 10RO F RESISTOR 10 1 125W F 4 100 24546 C4 1 8 TO0 10R9 F uubos AIRIS 0757 0346 1617 A1R18 AIRY ALR2O 0698 3154 RESTSTOR 10 1 12 24546 4 1 8 0 10 0 RE TOR 348 1 120 0 100 24546 CA 1 8 T0 3APR RESISTOR 10 1 125 F T 100 24546 4 1 8 0 1090 RESISTOR 261K 1 125W F 0 100 24546 C4 1 8 T0 2613 F RESISTOR 4 22K 1 125 TC 0 100 24746 4 1 8 0 4201 b ro A1R21 0628 3152 RESISTOR 3 40K 1 12 F TCz0 100 24546 CA 1
61. Negative Clock TTL Clock U99 pin 3 ST SP QL TIL Ground GND TP levels are TIL except where noted U119 2 1UPP 0120 18 508P U122 11 high 0119 3 1UPP U120 19 low U122 12 357P U119 4 chr8 U122 13 high U119 5 ChF8 U122 1h 99F7 0119 6 A192 0121 1 7755 0122 15 low U119 7 A192 0121 2 508P U122 16 6302 0119 8 95623 U121 3 6302 0122 17 high U119 9 9523 0121 4 9927 U122 18 508P U119 11 0000 U121 5 357P 0122 19 8877 0119 12 8877 0121 6 A59P 0119 13 8877 0121 7 4871 0119 18 8124 0121 8 8 9 U123 1 high TOTLZ OFLO 0121 9 048 0123 2 low 0119 15 8 24 0121 11 048 U123 3 high 0119 16 U871 0121 12 8 9 0123 4 5401 0119 17 U871 U121 13 4871 U123 5 57U4 0119 18 high 0121 14 A59P U123 6 low U119 19 high 0121 15 357P 0123 7 high 0121 16 99F7 U123 9 high U121 17 6302 U123 11 high 0120 2 high 0121 18 508 0123 12 C3HA U120 3 048C 0121 19 0000 0123 13 9361 U120 4 8 9 U123 14 high 120 5 low 0120 6 low 0122 1 8877 0120 7 4871 0122 2 high U125 h 0000 U120 8 5 U122 3 048C U120 11 high U122 4 high 1120 13 357P 0122 5 8 9 U127 4 0000 U120 1h 99F7 U122 6 low TOTLZ 70347 U120 16 high U122 7 4871 U127 5 U871 U120 17 6302 U122 8 U127 6 1871 0122 9 A59P SAC 4 36 Model 64621A Performance Verification Board 64621 66503 Test 2 Loop B VH 0418 MODE EDGES THRESHOLDS CONNECTIONS Normal Clock Positive Data High ST SP Start TP19 Start Pos
62. OVERVIEW 108 15 OVERVIEW EVENT LATCH a ht HOV LTRACE cr ee mani EVENT A 03 OVERVIEW MEMORY 1 3 gt PIPELINE TO OVERVIEW OVERVIEW MEMORY 4096 X 4 OEN MEMORY REGISTER OV E RV EW STATE TIME MEMORY LOMCO 11 ADDRESS HOMA 0 11 HBOWRT PINC COUNTER ADDRESS SELECTOR HBOWRT COUNTER TRACE TIME OV STATE SEL WR Po 25MHz PBOVRST L25MHz x HOVEQ avka y LOMCO 11 MEMORY PBPLS COUNTER zu LATCH BUS OEN TO OVERVIEW STATE TIME FM CPU INTFC COUNTER 4 TRACE POD DATA MEMORY DATA ACQUISITION STATE TRA DATA RECOGNITION er 88 0 R D TRAGE POD DATA RESOURCE MEMORY 800 7 1007 THRESHOLD COUNTERS PATTERN T 2 g POD DATA ADDRESS 256x20 CLOCK TRIGGER Tie 5 ADDRESS SELECTOR VIHSH MEMORY TRACE COUNTER SYNDO 19 SYNDO 19 POD DATA SYNPDO 19 THRESHOLD PIPELINE GNDSEN D A REGISTER 7 CONVERTER 1801 SEQUENCE P NBDSTB P NBSRS TRIGGER LBSPO 3 18807 5 MEMORY FROM FROM 5 ADDITION
63. Read Register Figure 4 16 reports this as Memory Address Trace Point is tested by clearing U98 then setting it by having the Analysis Controller issue an NTRIG Trigger The result LTRCP is read by the Analysis Status Buffer 4 46 Sequence Addressing in Figure 4 16 is a test of the address lines of the Transition Memories RAM U36 and the Analysis Controller are loaded so that a walk ing ones address pattern causes U36 to output Sequence Store Qualify LSSQ This causes the Analysis Controller to enable HQWRT provided other Analysis Controller inputs are good Also HBOTF can cause failures in HSTR signal HQWRT increments the MAC Now that the Transition Memories and the MAC and LTRCP are known to work additional functions of the Analysis Controller can be tested The Analysis Controller inputs tested are HSTR Sequencer Trigger LSTE Sequencer Trigger Enable LSSE Sequencer Store Enable and LSME Sequencer Master Enable The results are obtained from the NTRIG and HQWRITE outputs of the Analysis Controller 4 47 Results all results of this test are read at of three places the Sequence Read Register the Trace MAC Read Register or LTRCP at the Analysis Status Buffer SAC 4 22 Model 64621A Performance Verification 10 MHz State Test Board in Slot 2 Pass Tested 1 Failed 0 Slot 2 State Control and Clock Test 4 Sequencer 54321 98768543210 State Register Count 00000000 Load 00000000 Occur Counter Bits T
64. STORE STATES ELAPSED TIME TRIGGER TRACEPOINT IMB RESOURCE PATTERNS SEQUENCER INTERMODULE BUS IMB tr T 55 lt z Zw lt STROBE GENERATOR Figure 8 8 Analysis Controller Summary 8 99 Modes 8 100 The Analysis Controller has two primary modes run mode and load mode con trolled by LRUN and LLD The load mode is used to program a 58 bit shift register inside the Analysis Controller The parallel outputs of the register initialize and determine which of the various inputs will control the Analysis Controller during a trace execution The 58 bits are grouped as follows Storage Function 3 bits Trigger Function 6 bits Master Enable Function 4 bits Resource Pattern Allocation 30 bits Initialize Poststore 10 bits Initialize Sequencer Enables 5 bits The run mode is used while executing a trace 8 101 Two secondary modes are used during performance verification run_load mode with both LRUN and LLD low and not run_not load mode with both LRUN and LLD high Run_load mode allows the Analysis Controller to run but excludes external clocks Not run not load mode is used while testing the Sequencer 8 102 Block Diagram SAC 8 19 Model 64621A Service 8 103 The Block Diagram shows a time progression from the arrival of resource patterns to output of control signals including write control First there is Resource Allocation then Resource Gating then Write Qualification Additional major sub blocks include Analyzer
65. Seimei Hiroshima Bldg 6 11 Hon dori Naka ku HIROSHIMA 730 Tel 82 241 0611 Yokogawa Hewlett Packard Ltd Towa Building 2 3 Kaigan dori 2 Chome Chuo ku KOBE 650 Tel 078 392 4791 CE Yokogawa Hewlett Packard Ltd Kumagaya Asahi 82 Bldg 3 4 Tsukuba KUMAGAYA Saitama 360 Tel 0485 24 6563 CCME Yokogawa Hewlett Packard Ltd Asahi Shinbun Daiichi Seimei Bldg 4 7 Hanabata cho KUMAMOTO 860 Tel 096 354 7311 Yokogawa Hewlett Packard Ltd Shin Kyoto Center Bldg 614 Higashi Shiokoji cho Karasuma Nishiiru Shiokoji dori Shimogyo ku KYOTO 600 Tel 075 343 0921 CE Yokogawa Hewlett Packard Ltd Mito Mitsui Bldg 4 73 Sanno maru 1 Chome MITO Ibaraki 310 Tel 0292 25 7470 C CME Yokogawa Hewlett Packard Ltd Meiji Seimei Kokubun Bldg 7 8 Kokubun 1 Chome Sendai MIYAGI 980 Tel 0222 25 1011 Yokogawa Hewlett Packard Ltd Nagoya Kokusai Center Building 47 1 Nagono 1 Chome Nakamura ku NAGOYA 450 Tel 052 571 5171 C CM E M Yokogawa Hewlett Packard Ltd Saikyoren Building 1 2 Dote machi OHMIYA Saitama 330 Tel 0486 45 8031 Yokogawa Hewlett Packard Ltd Chuo Bldg 4 20 Nishinakajima 5 Chome Yodogawa ku OSAKA 532 Tel 06 304 6021 Telex YHPOSA 523 3624 A C CM E M P Yokogawa Hewlett Packard Ltd 27 15 Yabe 1 Chome SAGAMIHARA Kanagawa 229 Tel 0427 59 1311 Yokogawa Hewlett Packard Ltd Daiichi Seimei Bldg 7 1 Nishi Shinjuku 2 C
66. Strobe Generator The D A Converters provide threshold levels for the Clock Probe The threshold levels are set by the operator through the keyboard 8 38 PREPROCESSOR INTERFACE BUS The Preprocessor Interface Bus provides the communications path from the Mainframe to the General Purpose Probes and the General Purpose Preprocessor The clock for the State Analyzer is provided by the Preprocessor when it is being used instead of the Clock Probe 8 39 STROBE GENERATOR The Strobe Generator converts the output of the Clock Term Generator U25 into the various strobes needed throughout the State Analyzer including the Acquisition Boards The amounts of delay for each strobe and the pulse widths are adjustable The Strobe Generator can also be activated by the Mainframe Interface for Performance Verification using signals PPVSTB or PBSRQ 8 40 SEQUENCER The Sequencer is a group of counters memories and gates that allow the State Analyzer to find events in various sequences and occurrences SAC 8 6 Model 64621A Service The Sequencer is programmed by the Mainframe for each Trace to be performed Variables are entered from the keyboard 8 41 ANALYSIS CONTROLLER The Analysis Controller Ul is the heart of the State Analyzer The Analysis Controller recognizes events occurring on the Acquisition Boards and in general provides the handshaking between the Acquisition Boards and the Control Board
67. The Analysis controller is programmed by the Mainframe CPU The Analysis Controller controls the Intermodule Bus IMB 8 42 BNC CONTROL The BNC Control circuit drives signals of correct polarity to the Mainframe s Rearpanel The polarity is selected by software 8 43 TRACE STATE TIME COUNTER The Trace State Time Counter U112 is a 20 bit floating point gray code counter The State Time Counter accumulates the time between two stored states or the number of states between two stored states The State Time Counter is referenced to a 25 MHz crystal when measuring time and to the qualified count states as input in the trace specification when counting states The 25 MHz crystal is located in the Mainframe 8 44 TRACE COUNT STATUS MEMORY The Trace Count Status Memory stores the values output from the Trace State Time Counter for each measurement The Trace Count Status Memory can store values for each of the 256 locations in the Trace Pod Data Memory on the Acquisition Boards The values are read from the memories over the Mainframe s Data Bus and for matted by the CPU for display on the CRT The Trace Count Status Memory stores sequence states and flags associated with each counter value 8 45 MAINFRAME INTERFACE The Mainframe Interface consists of various latches and buffers wire ORed for interfacing the State Analyzer s circuits to the Mainframe SAC 8 7 Model 64621A Servic
68. U 1 40 SAH6 ECL U 66 13 894H 0 68 16 10 U 68 17 COUF 5 3 0000 U 66 2 FF68 ECL U 68 18 7753 TOTLZ OFLO U 66 3 1525 ECL U 68 19 FF34 U 5 6 0000 ECL U 66 6 FF68 ECL U 5 7 ECL U 66 4525 ECL U 69 1 127 U 5 10 0000 ECL U 66 15 894H ECL U 69 2 8007 U 5 11 F23A ECL TOTLZ OFLO U 69 3 AC8P U 5 12 894H ECL U 69 4 9520 TOTLZ OFLO U 67 1 416P U 69 5 1108 U 5 13 894H ECL U 67 2 8007 U 69 6 F789 U 5 14 0000 ECL U 67 UP69 U 69 7 F82U TOTLZ OFLO U 67 h F989 U 69 8 641c U 5 15 894H ECL U 67 5 1108 U 69 9 8PU8 U 67 6 F789 U 69 11 4525 U 16 9 894H ECL U 67 7 000 U 69 12 101 QUAL U 16 12 0000 ECL U 67 8 7233 U 69 13 FFFP TOTLZ OFLO U 67 9 8PU8 U 69 14 U87C SAC 4 46 Board 64621 66503 MODE EDGES Normal Clock Positive Start Positive Stop THRESHOLDS Data High Data Low Clock TTL ST SP QL TTL Model 64621A Performance Verification Test 6 Loop F 894H QUAL PFA4 levels are TIL except where noted 6412 10 PUC6 OF8U FF34 8989 50P9 93A5 C6HO 6HFO AAF2 641C 9501 F82U 3733 9520 POAU AC8P 63PH 894H 1796 3781 8989 50 9 9345 C6H0 6HFO HU5A 641C AOCT F82U 4214 9520 16U4 AC8P 018F 894H TOTLZ U 71 21 72 72 T2 72 72 72 72 72 72 10 72 11 72 12 72 13 72 14 72 15 72 16 72 18 72 20 72 21 FWD P
69. W1 CLOCK CABLE W2 DATA CABLE gt CONNECTORS NOT SEPARATELY REPLACEABLE ORDER CABLE ASSEMBLY Figure 6 1 Probe Cable Breakdown SAC 6 4 Model 64621A Replaceable Parts Table 6 2 Replaceable Parts List Reference Description Mfr Part Number Designation 646218 3 STATE ANALYSIS CONTROL 28480 1 64621 66503 10MHZ STATE ANALYSIS CONTROL BOARD 20490 64621 66503 AlC1 0160 2085 7 01UF B0 29 109V0C CUR 28480 0169 205 AlC2 0160 2055 CAPACITOR FXD 010 8020 100UDC CFR 206480 0160 2055 AICS 0160 2085 CAPACTTOR FXO 91UF 80 207 100UDC CER 28480 9160 2055 A1C4 016 j CAPACITOR FXD 01UF 80 20 100UDC CER 2 0160 20 A1CS 0160 3793 E CAPACITOR FXD 680PF 1 100U0C MICA 2846 9160 3793 A1C6 0140 0149 CAPACITOR FXD 470PF SX 300UDC MICA LIE DM1SFA71J0300WV1CR A107 0140 0149 h CAPACITOR FXD 470PF 300v0C MICA 22136 15 47170350059 1 1C8 0160 3067 CAPACITOR FXD 200PF 5 300UDC MICA 2948 0160 3067 A1C9 0160 3793 CAPACITOR FXD 680PF 1 100UDC MICA 0160 3793 1 10 0140 0149 CAPACTTOR FXD 470PF 300UDC MICA 2136 DM15F471J0300WW1CR 1 11 9 1010 480 202 100V0C CER 7848 9160 2055 A1C12 2 CAPACITOR FXD 1UF 80 20 S0VDO CER 20400 E A1C13 b CAPACITOR FXO 01UF 80 20 100VDC CER 20480 61C14 TOR FXD Q1UF 80 100UDC CER 204980 0160 207 1 15 2055 CAPACITOR FXD 01UF 480 20 1909066 CER 28480 0160 2055 1 1
70. Zone Industrielle de Courtaboeuf Avenue des Tropiques 91947 Les Ulis Cedex ORSAY Tel 6 907 78 25 Telex 600048F A C CM E M P Hewlett Packard France Paris Porte Maillot 15 boulevard de L Amiral Bruix 75782 PARIS Cedex 16 Tel 1 502 12 20 Telex 613663F Hewlett Packard France 124 Boulevard Tourasse 64000 PAU Tel 59 80 38 02 Hewlett Packard France 2 All e de la Bourgonnette 35100 RENNES Tel 99 51 42 44 Telex 740912F C CM E M P Hewlett Packard France 98 avenue de Bretagne 76100 ROUEN Tel 35 63 57 66 Telex 770035F Hewlett Packard France 4 rue Thomas Mann Boite Postale 56 67033 STRASBOURG Cedex Tel 88 28 56 46 Telex 890141F C E M P Hewlett Packard France La P ripole III 20 chemin du Pigeonnier de la C pi re F 31083 TOULOUSE Cedex Tel 61 40 11 12 Telex 531639F Hewlett Packard France 9 rue Baudin 26000 VALENCE Tel 75 42 76 16 Hewlett Packard France Carolor ZAC de Bois Briand 57640 VIGY Metz Tel 8 771 20 22 Hewlett Packard France Parc d activit des Pr s 1 rue Papin 59658 VILLENEUVE D ASCQ Cedex Tel 20 47 78 78 Telex 160124F GABON Sho Gabon Box 89 LIBREVILLE Tel 721 484 Telex 5230 GERMAN FEDERAL REPUBLIC Hewlett Packard GmbH Gesch ftsstelle Keithstrasse 2 4 D 1000 BERLIN 30 Tel 030 21 99 04 0 Telex 018 3405 hpbin d A C E M P Hewlett Packard GmbH V
71. all the data so that the front end can bring in new data and the rest of the analyzer can process the current data The latching is done by the Positive Pipeline Strobe PPLS which occurs 95ns after the Strobe Generator is started This allows the state boards to work on 2 different sets of input data at the same time The timing for PPLS is critical SAC 8 2 Model 64621A Service 8 24 Time Period 5 8 25 The Data Storage Count Enable Determination continues the resource allocation and gating that was started in time period 4 All this is done on the control board in the Analysis Controller These control signals are output by the Analysis Controller gating functions HOVCQ High Overview Count Qualify HOVCQ when high enables the overview counter in the 20 channel Data Acquisition Board It is derived from the internal Overview Count Signal or LSOCE Low Sequence Overview Count Enable from the Sequencer HCQ High Count Qualify When high HCQ enables the Trace State Timing Counter allowing it to increment It is derived by the internal Trace Count signal or the LSCE Low Sequence Counter Enable signal from the Sequencer LSFLG Low Store Flag This active low signal indicates to the Trace Count Status Memory that storage is enabled LSFLG is enabled by the internal storage signal or LSE Low Storage Enable from the IMB Inter Module Bus if active or either of the signals from the Sequencer LSSE Q Low Sequen
72. and low level channel 2 and low level channel T f Press execute g Verify on trace list that time count rel column is 16 uS 20 uS or 224 us h Repeat for rising edge of channel 1 through 7 Set all other clock channels to low level SAC 4 3 Model 64621A Performance Verification 2 8V 0v A 20nS Figure 4 3 Clock Width Falling Edge Waveform i Setup Pulse Generator for the waveform in Figure 4 3 j Press clock is falling edge channel 0 and high level channel 1 and high level channel 2 and high level channel T k Press execute l Verify on trace list that time count rel column is 16 uS 20 uS or 2 05 Repeat for falling edge of channel 1 through channel 7 Set all other clock channels to high level SAC 4 4 Model 64621A Performance Verification BNC SIGNAL BNC GND Jumper wire on RS232 connector Signal on pins 16 17 18 19 20 21 22 and 23 Signal ground pin 15 PIN PIN 16 15 REMAINING PINS OMITTED FOR CLARITY Connecting BNC to RS232 connector DBM 25P TRW CING M ie ARTE TU UE SUMAN RG due deh tes 1251 0063 BNG CONNECTION T akun i V DOR a 1250 1032 Figure 4 4 Clock Probe Test Connector SAC 4 5 Model 64621A Performance Verification 4 15 TEST 4 DATA SETUP amp HOLD TIME amp QUAL CLOCK RATE Specifications Data Setup Time 30 nS
73. cas5 cae rao 47 C48 49 c50 4i R38 R39 U111 Uis Fass 01 7 F g J 198 U97 098 9100 U101 0102 9103 0104 0106 0109 bi 41 R42 843 Ra4 53 C54 TP15 U112 C51 52 css R4 56 R47 C57 R48 U130 RI GND 849 0124 0125 4127 0117 0123 5 u18 U119 U120 U121 0122 U126 17 C67 ke c61 Rs2 d R53 ART RS C59 R50 C 2 TP19 6 Rss C6 TP16 R57 C66 6 SA START STOP 35 53 59 69 79 8385 H RI 5 5 83 64621A STATE CONTROL Component Locator SAC 8 50 INTERMODULE BUS IMB SYNCHRONOUS EXPANSION BUS SEB E ee eg UL Circ ee drei cetacei j i KY y ad Gd Gl cib TY T eee REL A AA onwuoao n RIT PEE P O A1 STATE ANALYSIS CONTROL BOARD 64621 66503 ANALYSIS CONTROLLER LBSP0 3 41 3 8 74 NINCSS 14 ECL 6 0850 5 P O U7 ACT TERM o a MAINFRAME PORT DRIVER SEQUENCER LINES 11 PORTS 60 8 ET som m s 8 13 NC 3 uc PSTIM 4 LRUN B PLCLK TTL 5 SERDATA LLOAD TTL RESOURCE PATTERNS
74. e the State Analyzer Control Board Low Write Strobe CPU controlled When low LWRTSTB enables the Mainframe Interface Write Decoders when the CPU wants to do a write cycle on the Control Board SAC 8 35 Model 64621A Service Mnemonic LWSEQML LWSEQMU LWTHS1 52 NBDSTB NBSRS NDSTB NIHALT NINCSS NISTIM NMACRS SAC 8 36 Table 8 1 Mnemonics Cont d Description Low Write Sequence Memory Lower when low the CPU can load information into the Lower Sequence Transition Memories LSEQDO 7 LWSEQML is developed in the Write Decoders Low Write Sequence Memory Upper when low the CPU can load information into the Upper Sequence Transition Memories LSEQDO 7 LWSEQMU is developed in the Write Decoders Low Write Threshold 1 when LWTHS1 goes from a high to a low information from the CPU is latched into the Digital to Analog Converter The output current is proportional to the binary value latched Full Scale Current X Binary Value Latched 256 Output Current Low Write Threshold 2 when LWTHS2 goes from a high to a low information from the CPU is latched into the Digital to Analog Converter The output current is proportional to the binary value latched Full Scale Current X Binary Value Latched 256 Output Current Negative Bus Data Strobe a differential signal PBDSTB developed in the Strobe Generator Used to latch the outputs of the Trace Pod Data Memories in
75. high HOVCQ al lows the Overview Counter on the 20 Channel Data Acquisition Board to in crement HOVCQ is derived from the Analysis Controller or HLD High Overview Strobe generated in the Strobe Generator Develops LBOVEN and PBOVRST These two signals are used on the 20 Channel Data Acquisition Board only High Pipeline Strobe developed in the Strobe Generator HPLS is used by the Control Board and both Data Acquisition Boards for latching information into the Pipeline Reqisters at the correct time in the Analyzer s timing cycle PBPLS High Qualified Write when high HQWRITE is used to write to the Trace Counter Status Memories and to internally reset the Trace State Time Counter HQWRITE going low increments the Trace Count Status Memory Address Counter HQWRITE is derived from HWRT and enabled by HWQ High State Recognition Strobe developed in the Strobe Generator HSRS is used to clock the State Recognition Register in the Analysis Control chip The purpose of the register is to store information received on the Intermodule Bus IMB HSRS also clocks LRUN High Sequence Trigger when high indicates that a Sequence Trigger has been found High Transfer Clock differential clock LTCLK used the Preprocessor When goes from a low state to a high state data is transferred to from the State Analyzer and the Preprocessor High Time Strobe developed in the Strobe Generator Used in the Trace
76. in the Register is transferred to the CPU Data Bus when LRMACR goes low Port 1 a signal from the Card Cage to the Rear Panel Connector PORT 1 In the case of the State Analyzer Control Board PORT1 is used for Positive Stimulus see PSTIM Port 2 a signal from the Card Cage to the Rear Panel Connector PORT 2 In the case of the State Analyzer Control Board PORT2 is used for Positive Halt see PHALT Positive Pipeline Strobe same as NINCSS but inverted When PPLS goes from a low to a high state the Sequence Pipeline Latch Counter is incre mented one state when in the count mode Positive Performance Verification Strobe PPVSTB is developed in the Write Decoders from the CPU PPVSTB when going from a low state to a high state begins a strobe generator cycle PPVSTB is used only during Performance Verification PPVSTB is wire ORed with HMCLK and PBSTBRQ Positive Sequence Occurrence Counter Increment developed from NOCSTB When PSCINC goes from a low to a high the Sequence Occurrence Counters Mnemonic PSQRGS PSTIM PWAC PWCLK PWLOAD PWRUN 550 7 VIHSH1 2 Model 64621A Service Table 8 1 Mnemonics Cont d Description will be incremented one state when in the count mode PSOCINC may also be driven by HBOWRT they are wire ORed PSOCINC never drives HBOWRT Positive Sequence Register Strobe a differential signal NSQRGS developed in the Strobe Generator PSQRGS is used to latch informa
77. indicate the point in time that the Trace Memory outputs are stable P NBSRS HSRS HTIMS HPLS HWRT LMV PPVSTB HMCLK PBSTBRQ Figure 8 4 Strobe Generator Block Diagram SAC 8 12 Model 64621A Service 8 68 How A Strobe is Generated 8 69 Figure 8 4 is a simple block diagram of the Strobe Generator and Figure 8 5 shows the timing relationship of the seven major strobe signals The time periods indicated are approximate values and should not be used for calibration purposes 8 70 Six of the seven stages work very much the same Therefore only the first stage will be discussed The seventh stage is built using OR gates 8 71 At time zero U23 pin 11 goes from a low to a high the same in the run mode or Performance Verification mode Because U23 pin 10 is connected to a high level U23 pin 15 goes high when the positive edge on pin 11 occurs At the same time U23 pin 14 begins to go low Pin 14 cannot go low instantly due to the charge in C10 and the currents in R18 R8 and the 240 ohms in U9 The amount of time it takes pin 14 to reach a low state is determined by these components 8 72 The hysteresis of U50 pin 13 is set to 1 55 V by U50 pin 9 two 220 ohm resistors in U51 and one 240 ohm resistor in U35 As U50 pin 13 U23 pin 14 goes negative the hysteresis level being crossed U50 pin 15 goes positive changing the hysteresis level This action is fed back to U50 pin 12 and enhances U50 pin 13 going negative c
78. inputs and outputs Signals having a common relationship will have a common number i e C7 and 7D C7 controls D Dependency notation 2 3 5 6 1 C7 is read as when 2 and 3 and 5 and 6 are true the input will cause the counter to increment by one count or the input C7 will control the loading of the input value 7D into the D flip flops The following types of dependencies are defined AND G OR V and Negate N denote Boolean relationship between inputs and outputs in any combination Interconnection Z indicates connections inside the symbol Control C identifies a timing input or a clock input of a sequential element and indicates which inputs are controlled by it Set S and Reset R specify the internal logic states outputs of an RS bistable element when the R or S input stands at its internal 1 state Enable EN identifies an enable input and indicates which inputs and outputs are controlled by it which outputs can be in their high impedance state Mode M identifies an input that selects the mode of operation of an element and indicates the inputs and outputs depending on that mode Address A identifies the address inputs Transmission X identifies bi directional inputs and outputs that are connected together when the transmission input is true DEPENDENCY NOTATION SYMBOLS Address selects inputs outputs indicates binary range Negate complements state Control permits action Reset Input
79. is a Strobe Generator output LSTATE should oscillate If all other tests pass replace the Counter U112 and rerun the test 10 MHz State Test Board in Slot 2 Pass Tested 1 Failed Slot 2 State Control and Clock Test 7 Other counter tests Prescale 1 Pass 2 Pass 3 Pass Time enable Pass Time reset Pass Prescale 4 Pass Figure 4 19 Other Counter Tests SAC 4 29 Model 64621A Performance Verification 4 71 TEST 8 INTERMODULE BUS 4 72 This test has two parts internal test using loopback in the Analysis Controller and external test which requires that another system be connected via the Intermodule Bus IMB 4 73 Assuming all cables connections and configurations are correct and working properly failure of this test indicates that the Analysis Controller of one of the systems is failing If no external system is connected the test will still indi cate pass provided the internal test passes 4 74 The State Analysis PV software provides the test IMB softkey for IMB testing It selects the board that is to be the Intermodule Bus Driver 10 MHz State Test Board Slot 3 Pass Tested 1 Failed 0 Slot 3 State Control and Clock Test 8 Intermodule Bus Internal tests Master Enable Pass Trigger Enable Pass Storage Enable Pass Tests with IMB test Receive board IMR test ME TE SE TR 1 Error Drive Porti pulses DCik Port2 Por t1 ME TE SE TR IMB test board limitations 1 N
80. loaded with a true state at the address supplied by the incoming data and the sequence state 8 56 The sequence pattern is applied to the Sequence State Latch this register is used as a counter only to load memories before a trace after modification by the DME Gate The DME disjoint minterm event is formed by inverting LBSP3 and ORing the result with LBSP2 This allows the operator to specify one term which has the form ADDRESS lt gt 5 In other words the operator can specify one not equal to term Only LBSPO 2 are left as inputs to the Sequence State Latch 8 87 BSSO 3 supplies four more inputs to the Sequence State Latch 550 3 is out put by the Sequence Transition Memories and forms the major feedback path for the Sequencer The fourth input to the Latch is low Occurrence Carry LOCCRY LOCCRY is output by the Occurrence Counter when it has found a term the required number of times 8 88 At Positive Pipeline Strobe PPLS these inputs are latched and applied to the Transition Memories forming a new sequence state named Trace Sequence State T3S0 T TSSO 7 is stored in Trace Memory and can be used by the operator to debug code During performance verification the CPU can read TSSO 7 from trace memory to verify proper functioning of the Sequencer SAC 8 16 Model 64621A Service 8 89 The Sequence Transition Memories use 550 as address lines and outputs 16 control signals These signals include BSSO 3 us
81. low ECL U 63 14 FPh9 ECL 43 3 PCCF ECL U 60 h Hh10 ECL U 63 15 0 9 ECL U 43 5 0000 ECL U 60 5 6297 ECL TOTLZ 67701 U 60 6 ECL U 64 5 5093 U 43 6 0000 ECL 0 60 7 A2UF ECL U 64 7 TOCH TOTLZ 67701 0 60 9 8 ECL U 64 10 8401 U 43 448F U 60 10 PC61 U 64 11 6093 U 60 11 9 ECL U 52 7 15FH U 60 12 0 9 ECL U 64 1 70CH ECL U 60 13 58C9 ECL U 64 2 5093 ECL U 52 1 15 ECL U 60 14 2708 ECL U 64 14 6U93 ECL U 52 3 CAUH ECL U 60 15 6 ECL U 64 15 8401 ECL Board 64621 66503 MODE EDGES Normal Clock Positive Start Positive Negative Stop THRESHOLDS Data High Data Low Clock TIL HH ST SP QL TTL levels are TIL except where noted U 65 5 PCCF U 65 6 U 65 PCCF U 66 h PCCF U 66 5 PCCF U 66 12 AU30 CA14 8401 33C6 6093 70CH FC20 6509 5093 U 68 11 PCCF 68 12 0 9 68 13 19PU 68 14 83H3 68 15 9 68 16 H410 6 6 6 U 68 U 68 U 68 U 68 U 68 U 68 on ON EWM P 8 17 0C71 8 18 8 19 6297 78 h 60 78 5 U15C 78 6 0F48 78 7038 8800 78 10 6261 78 11 HTUO 78 13 1628 q c c lt c lt lt s 1 79 4 8390 T9 5 U15C 79 6 oHh2 4685 19 9 55 79 10 66 1 ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL U 79 11 U 79 13 U 80 U 80 U 80 U 80 U 80
82. of Operation at the bit level Therefore the follow ing discussion is at the concept level of various functions 8 5 The following five areas of the State Analyzer are discussed in detail 1 Clock Term Generator 2 Strobe Generator 3 Sequencer 4 Analysis Controller and 5 State Time Counter 8 6 The Clock Term Generator Analysis Controller and the State Time Counter are custom integrated circuits manufactured by Hewlett Packard How the ICs work is presented to help you understand how the State Analyzer works rather than a black box approach 8 7 The Strobe Generator is discussed because it must be repaired using convention al methods instead of Signature Analysis 8 8 The Sequencer is discussed because it is not apparent from the schematics how it works due to feedback loops 8 9 STATE ANALYZER SUBSYSTEM BLOCK DIAGRAM 8 10 The State Analysis Subsystem Block Diagram Figure 8 1 is designed to give an overview of the State Analysis System The block diagram is divided into two sec tions the Control Board and the Data Acquisition Board The Data Acquisition Board is also divided into two sections the Overview block which is only on the 20 chan nel board and the rest of the blocks which are on both the 20 channel and 40 chan nel boards 8 11 The shaded blocks on the Control Board are all parts of the Analysis Controller U1 a hybrid chip Other hybrids are the Clock Term Generator U25 the Trace State Time
83. oxide substrate mounting mylar nano 10 9 normally closed neon nickel plate mechanical part plug transistor resistor thermistor switch transformer terminal board test point normally open nominal negative positive zero zero temperature coefficient negative positive 5 SCR not recommended for SE field replacement SECT not separately SEMICON replaceable 1 SIL order by description SL oval head SPG oxide SPL SST SR peak STL printed circuit picofarads 10 12 TA farads TD phosphor bronze phillips peak inverse voltage positive negative positive part of polystyrene porcelain positions potentiometer peak to peak point peak working voltage rectifier radio frequency round head or right hand integrated circuit vacuum tube neon bulb photocell etc voltage regulator cable socket crystal tuned cavity network rack mount only root mean square reverse working voltage slow blow screw selenium sectionts semiconductor silicon silver slide spring special stainless steel split ring steel tantalum time delay toggle thread titanium tolerance trimmer traveling wave tube micro 10 6 variable dc working volts 7 with watts working inverse voltage wirewound without SAC 6 3 Model 64621A Replaceable Parts MP5 LABEL MP3 TOP
84. the 6h623A 20 Channel Acquisition Board 8 121 On the Control Board the Counter is used during trace 256 states and is used during Overview on the 20 Channel Board Pin 35 controls the Trace Overview modes On the Control Board pin 35 is tied low the Trace mode On the 20 Channel Board pin 35 is tied high for the Overview mode 8 122 LSTATE pin 8 makes the decision to count either qualified states or time intervals When LSTATE is low states between stored qualified states will be counted When LSTATE is high time between stored qualified states will be counted 8 123 Function 8 124 Modes The counter has two modes the load mode and the normal mode The load mode is used during Performance Verification It forces the Counter to act like two ten bit counters without prescale which qreatly improves loading and test ing efficiency The normal mode is described in the Block Diagram description 8 125 Block diagram The Block Diagram shows inputs on the left and outputs on the right The three major sections are counter control 20 bit counter and the output latch 8 126 Counter Control The counter control section controls the count reset and latch functions The counter s versatility is shown by the triple 2 to 4 selector one selector for each function Using the count function as an example if pin 8 is a logic high and pin 35 is a logic high then overview on time is selected which is input 3 to all functions of the s
85. the Analysis Controller and is returned to the CPU through the Analysis Status Buffer Low Sequence Counter Enable a Sequencer output used by the Analysis Controller to determine when the Trace State Time Counter should be enabled Low Slow Clock when low LSCLK indicates that it has been at least 100 mS since the last HMCLK The status of LSCLK is returned to the CPU through the Analysis Status Buffer over the CPU Data Bus Low Storage Enable LSE is one of the bidirectional signals that make up the Intermodule Bus IMB When LSE is low the Storage Qualify function is enabled in the State Analyzer and will store information when another module tells it to LSE is wire ORed with other modules Low Select a signal originating in the Mainframe When low LSEL allows the State Analyzer Identification Code to be returned over the CPU s Data Bus This allows the CPU to identify if there is a State Analyzer Control Board installed in the Mainframe and if so which slot of the Card Cage it SAC 8 33 Model 64621A Service Mnemonic LSEQDO 7 LSFLG LSFLGB LSME LSOCE LSOCEN LSOCLD LSSE LSSQ LSTATE LSTB SAC 8 34 Table 8 1 Mnemonics Cont d Description is installed in LSEL is also used to enable the State Analyzer Control Board Low Sequence Data 0 7 the data path the CPU uses to load information into the Sequence Transition and Sequence Occurrence Memories prior to a measurement 100 7
86. 0 20 100VDC CER 20480 0160 2055 A1C39 0150 2055 80 20 190VDC CER 28480 0160 2955 41040 0160 2055 CAPACTTOR FXD 01UF 80 20 100UDC CER 28480 0160 2055 amp 1C41 0160 2055 CAPACTTOR FXD QIUF 80 20 100VDC CER 28480 9160 2055 1 42 0160 2055 CAPACITOR FXD Q1UF 80 20 10090 CF 20480 0160 205 A1C43 0160 2055 7 01UF 80 20 100VDC CE 0480 0160 2055 1C44 0160 2055 CAPACITOR FXD 01UF 80 207 100UDC CF 20480 01460 2055 AIC4S 0160 2055 CAPACTTOR FXD 1UF 80 20 100VDC C 28480 0160 2055 1 46 0160 2055 CAPACTTOR FXD 01UF 80 20 100UDC C 20480 0160 2055 A1C47 0160 2055 CAPACITOR FXD 01UF 80 20 10090 C 28480 0160 20 A1C48 0160 2055 CAPACITOR FXD 010 80 20 100VDC C 289480 0160 2055 A1C49 0160 2055 CAPACITOR 01UF 0 20 100VDC 28480 0160 2085 1050 0160 2055 CAPACITOR FXD Q01UF 80 20 100VDC 204900 0160 2055 CAPA amp CTITOR FXD 01UF 80 20 100900 CE 2B4B0 9160 2055 CAPACITOR FXD 01UF 80 20 100UDC CER 0160 205 CAPACITUR FXD 01UF 80 20 100VDC 0160 208 CAPACITOR FXD O1UF 80 20 100VDC C 0160 2055 CAPACITOR FXD 01UF 80 20 100VDC 0160 2055 AICS1 0160 2055 1 52 0160 2055 A1CS3 0150 2055 A1C54 0160 2055 1 55 0100 2055 92939 1 56 0100 2055 A1C57 0160 2055 A1C58 0180 1746 AICS 0180 1746 A1C60 0180 1746 CAPACITOR FXD 01UF 80 20 100UDC C 20490 0160 2055 CAPACITDR FXD 01UF 80 20 100VDC CE 01
87. 01 346 8370 A C M Hewlett Packard Co 220 Great Circle Road Suite 116 NASHVILLE TN 37228 Tel 615 255 1271 Texas Hewlett Packard Co 1826 P Kramer Lane AUSTIN TX 78758 Tel 512 835 6771 Hewlett Packard Co 5700 Cromo Dr EL PASO TX 79912 Tel 915 833 4400 Hewlett Packard 3952 Sandshell Drive FORT WORTH TX 76137 Tel 817 232 9500 C Hewlett Packard Co 10535 Harwin Drive HOUSTON TX 77036 Tel 713 776 6400 A C E M P Hewlett Packard Co 511 E John W Carpenter Fwy Royal Tech Center 100 IRVING TX 75062 Tel 214 556 1950 CE Hewlett Packard Co 109 E Toronto Suite 100 McALLEN TX 78503 Tel 512 630 3030 Hewlett Packard Co 930 E Campbell Rd RICHARDSON TX 75081 Tel 214 231 6101 A C CM E M P Hewlett Packard Co 1020 Central Parkway South SAN ANTONIO TX 78216 Tel 512 494 9336 A C E M P Utah Hewlett Packard Co 3530 W 2100 South SALT LAKE CITY UT 84119 Tel 801 974 1700 Virginia Hewlett Packard Co 4305 Cox Road GLEN ALLEN VA 23060 Tel 804 747 7750 Hewlett Packard Tanglewood West Bldg Suite 240 3959 Electric Road ROANOKE VA 24018 Tel 703 774 3444 CEP Washington Hewlett Packard Co 15815 S E 37th Street BELLEVUE WA 98006 Tel 206 643 4000 Hewlett Packard 708 North Argonne Road SPOKANE WA 99212 2793 Tel 509 922
88. 0160 2055 9 CAPACITOR FXD 01UF 80 20 100VDC CER 28480 0160 2055 Change 1 1 QTY from 50 to 49 Page SAC 6 5 Table 6 2 Replaceable Parts List Delete A1TP19 0360 0535 0 TERMINAL TEST POINT PCB 00000 ORDER BY DESCRIPTION Change 1 2 QTY from 13 to 12 Page SAC 6 6 Table 6 2 Replaceable Parts List Delete A1U14 1820 1201 6 1 IC GATE TTL AND QUAD 2 INP 01295 1820 1201 Section VIII Delete TP19 from the eight component locators facing the schematics Service Sheet 5 Remove U1hC Disconnect pin 17 from U14C pins 9 and 10 Disconnect U14C pin 8 from J2 pin 43 Show pin 43 as NC Disconnect J2 pins 42 and 44 from ground Show them as NC Service Sheet 7 Show U98A pins 2 3 and 4 as no connection NC Disconnect U73 pin 9 from U73 pin 17 5V Connect U73 pin 9 to U73 pin 11 LSFLGB Service Sheet 8 Delete C68 from the list of 5 Volt bypass caps 01UF Delete TP19 SA START STOP test point from 1 pin 69 SAC 7 2 Model 64621A Service SECTION VIII SERVICE 8 1 INTRODUCTION 8 2 This section contains information for troubleshooting and repairing the Model 64621A State Analysis Control Board 8 3 The block diagram schematic component location figure and other service in formation are provided on fold out service sheets to help you in servicing the Model 64621A 8 4 Because the State Analysis Control is software dependent it becomes very dif ficult to discuss the Theory
89. 09 13 POUH 0112 27 0000 ECL SAC 4 45 Model 64621A Performance Verification Board 64621 66503 Test 6 Loop F 894 QUAL PFA4 MODE EDGES THRESHOLDS CONNECTIONS Normal Clock Positive Data High ST SP Start 19 Start Positive Data Low Qual Stop TP19 QUAL Stop Negative Clock TTL Clock U99 pin 3 High ST SP QL TIL Ground GND TP Sb Qual U100 pin 7 levels are TTL except where noted U 1 4 low U 16 13 0000 ECL U 67 11 894H U 1 17 2362 TOTLZ OFLO TOTLZ OFLO U 1 18 CAHC U 67 12 1U1A QUAL U 1 19 6192 U 19 2 FF68 ECL U 67 13 219 U 1 20 FF34 U 19 3 4525 ECL U 67 14 9163 U 1 34 34F8 U 19 4 4525 ECL U 67 15 6412 U 1 35 A336 U 19 5 4525 U 67 16 10 U 19 6 FF68 ECL U 67 17 COUF U 1 2 3174 U 19 FF68 ECL U 67 18 7753 U 1 3 0000 ECL U 61 19 FF34 TOTLZ OLFO U 20 2 77 ECL U 1 4 F23A ECL U 20 5 F23A ECL U 68 1 190C U 1 7 4314 ECL U 68 2 8007 U 1 8 FUOC ECL U 45 12 0000 ECL U 68 3 4P69 U 1 9 HChi ECL U 45 13 1 77 ECL U 68 4 F989 U 1 12 ECL U 45 15 0000 ECL 0 68 5 1108 U 1 16 0000 ECL TOTLZ OFLO 0 68 6 F789 U 1 21 74P2 ECL U 68 7 OUHO U 1 30 19F2 ECL U 65 13 0000 U 68 8 7233 U 1 33 0000 ECL TOTLZ OFLO U 68 9 8 08 TOTLZ OFLO U 68 11 4525 U 1 36 5AH6 ECL U 66 4 4525 U 68 12 1U1A QUAL U 1 37 5AH6 ECL U 66 5 4525 U 68 13 219 U 1 38 5AH6 ECL U 66 12 38054 U 68 14 91C3 U 1 39 3396 ECL TOTLZ 1796 U 68 15 6412
90. 106471 SN74ULS04N SN 4L GOIN SN741 S123N GN741 S373N 34741 SIZIN SN74LSA74N 5 741652 9 741 5175 SN7403N SN741 802N 058821 4741 58 32 2104241 MC101241 2104471 1200 0654 1200 0639 1200 0796 1200 0796 1200 0607 200 0607 1200 0639 1200 0612 1200 06 1200 0612 1200 0612 1200 061 1200 0612 1200 0612 1200 0612 1200 0654 1200 0607 206 0607 1200 0638 Reference Designation HP Part Number 2200 0147 2200 0151 64620 67601 64620 67602 7121 2158 64620 61602 64620 61605 64620 61620 Model 64621A Replaceable Parts Table 6 2 Replaceable Parts List Cont d Description SCREW MACH 4 40 S IN LG PAN HD POZT SCREW MACH 4 40 75 IN LG PAN HD POZT HOOD CONNECTOR AS BLY TOP HOOD CONNECTOR ASSEMBLY CROTTOM LABLE CLOCK PRORE CABLE CLOCK ASSEMBLY NOTE IF THE CABLE IS DAMAGED THE ENTIRE Wi CABLE CI OCK ASSY MUST REPLACED CABLE DATA ASSEMBLY DEPENDS ON THE NUMBER OF ACQUISITION BOARDS BEING USED IN THE SYSTEM SEE THE ACQUIGITION MANUALS CABLE SYNCHRONOUS EXPANSION BUS SER CABLE INTERMODULE BUS IME 28490 28480 28480 28480 See introduction to this section for ordering information Mfr Part Number GRDER BY DESCRIPTION ORDER BY DESCRIPTION 64620 67601 64620 67602 7121 2158 64620 61602 64620 61605 64620 61620 SAC 6 9 Model 64621A Replaceable Parts 80167 4013 00000 11236 19701 SAC 6 10 Table 6 3 List of
91. 1A Performance Verification 4 36 TEST 3 CLOCK IC SHIFT REGISTER LOOP C 4 37 Purpose to verify that the Clock Term Generator U25 be loaded correctly 4 38 How Serial Data is loaded into U25 pins 13 and 15 Pin 14 is the clock Pins 26 and 28 output the same data several clock cycles later and the results are read at the Status Buffer 4 39 Results Register input bits passes if the shift register overflowed correct ly The bits are read as HCDO and HCD1 at the Analysis Status Buffer External Clocks is an indirect test which shows that U25 is not activating the Strobe Generator 10 MHz State Test Roard in Slot 2 Pass Tested 1 Failed 0 Slot 2 State Control and Clock Test 3 Clock IC shift register Register input bits 10 All 0 8 00 1 Error ALL 176 00 Patterns 00 External Clocks Pass Figure 4 15 Clock IC Shift Register 4 40 Loop C Signature Path U121 U122 U25 U102 sac 4 21 Model 64621A Performance Verification 4 41 TEST 4 SEQUENCER LOOP D 4 42 Purpose to verify operation of the Sequencer NOTE This test contains two feedback loops U16 3 to U17 pin 11 LOCCRY and U42 outputs to U18 parallel inputs Signature Analysis of feedback loops might fail to isolate the failed com ponent In that case use Test 1 which stimulates the Sequencer without allowing loopback Also all locations of the Sequence Transition Memories are not tested If a Transition Memory failu
92. 2 Telex 12598 CME C P C S I Rua de Costa Cabral 575 4200 PORTO Tel 499174 495173 Telex 26054 CP PUERTO RICO Hewlett Packard Puerto Rico 101 Mu oz Rivera Av Esu Calle Ochoa HATO REY Puerto Rico 00918 Tel 809 754 7800 A C CM M E P QATAR Computer Arabia P O Box 2750 DOHA Tel 428555 Telex 4806 CHPARB Nasser Trading amp Contracting 1563 DOHA Tel 422170 Telex 4439 NASSER DH M SAUDI ARABIA Modern Electronics Establishment Hewlett Packard Division P O Box 281 Thouqbah AL KHOBAR 31952 Tel 895 1760 895 1764 Telex 671 106 HPMEEK SJ Cable ELECTA AL KHOBAR Modern Electronics Establishment Hewlett Packard Division Box 1228 JEDDAH Tel 644 96 28 Telex 4027 12 FARNAS SJ Cable ELECTA JEDDAH A C CM E M P Modern Electronics Establishment Hewlett Packard Division 22015 RIYADH 11495 Tel 476 3030 Telex 202049 MEERYD SJ A C CM E M P Abdul Ghani El Ajou Corp P O Box 78 RIYADH Tel 40 41 717 Telex 200 931 EL AJOU SCOTLAND See United Kingdom SENEGAL Societe Hussein Ayad amp Cie 76 Avenue Georges Pompidou 305 DAKAR Tel 32339 Cable AYAD Dakar E Moneger Distribution S A 1 Rue Parent 148 DAKAR Tel 215 671 Telex 587 Systeme Service Conseil SSC 14 Avenue du Parachois DAKAR ETOILE Tel 219976 Telex 577 CP SINGAPORE Hewlett Packard Singapore Sales
93. 2 1 State Subsystem With 20 Channel 2 3 Figure 2 2 State Subsystem No 20 Channel e 22 Section Ill Operation Section IV Performance Verification Figure 4 1 Clock Width Test eee 4 3 Figure 4 2 Clock Width Rising Edge Waveform SSR he ere Tee d d s Roe 4 3 Figure 4 3 Clock Width Falling Edge 424 Figure 4 4 Clock Probe Test Connector iii sar ORA Figure 4 5 Setup and Hold Time Test 4 7 Figure 4 6 Setup and Hold Time 2 1 9 Figure 1 7 Data Probe Test 4 11 Figure 4 8 BNC Port Output Test 4 13 Figure 4 9 BNC Port 1 Waveform 9425444 hak Sons 4 14 Figure 4 10 BNC Port 2 Waveform au eae a es ta cater E 4 15 Figure 4 11 Automatic Teste ere rer 4 16 Table 4 1 Troubleshooting 4 17 Figure 4 12 Mainframe lN 18 Figure 4 13 Stimulus mo Dc MEE 4 18 Figure 4 14 Control IC Shift
94. 2 C851 ECL U121 3 92 U 52 4 80 ECL SAC 4 38 Model 64621A Performance Verification Board 64621 66503 Test 4 Loop D VH AU30 MODE EDGES THRESHOLDS CONNECTIONS Normal Clock Positive Data High ST SP Start TP19 Start Positive Data Low Qual Stop TP19 Stop Negative Clock TIL Clock U99 pin 3 ST SP QL TTL Ground GND TP levels are TTL except where noted U 1 18 CAUH U 6 11 low ECL U 20 3 PCCF ECL U 1 19 OU6H U 6 14 high ECL U 20 6 448F ECL U 1 20 6297 U 20 0000 ECL U 1 34 2277 U 16 2 92 ECL TOTLZ 67701 U 1 35 AU30 U 16 3 F6UC ECL TOTLZ 283 U 16 5 low ECL U 36 2 3U78 ECL U 16 6 A60A ECL U 36 4 AU88 ECL U 1 1 U613 ECL U 16 T UH44 ECL U 36 6 5093 U 1 2 492F ECL 0 36 7 ECL U 1 3 0000 ECL U 17 2 9 ECL U 36 8 PF6C ECL TOTLZ 67701 U 17 3 ECL U 36 9 H772 ECL U 1 4 TUCh ECL U 17 4 8505 ECL U 36 10 FFO8 ECL U 1 5 8067 ECL U17 5 15FH ECL U 36 11 7933 ECL U 1 6 FHhA ECL U 17 6 CAUH ECL U 36 13 741A ECL U 1 7 AU88 ECL U 17 7 low ECL U 36 14 94FH ECL U 1 8 1U4CU ECL U 17 9 low ECL U 36 15 4FYF ECL U 1 9 026 ECL U 17 10 high ECL U 36 16 0837 ECL U 1 10 1164 ECL U 17 11 F6UC ECL U 36 17 3500 ECL U 1 11 126C ECL U 17 12 7 8 U 36 18 6093 ECL U 1 12 026 ECL U 17 13 5451 ECL U 36 19 8401 ECL U 1 16 0000 ECL U 17 14 0837 ECL U 36 21 492F ECL TOTLZ 67701 U 17 15 ECL U 36 23 high ECL 0 1 21 TF F EC
95. 20 Channel Acquisition Boards with General Purpose Probes Unqualified Clock Rate 25 MHz max Qualified Clock Rate 10 MHz max Time Count Accuracy 0 1 or 40 ns whichever is greater Pulse Widths Setup and Hold Times all polarities Clock Pulse Width 20 ns min Clock Qualifier Setup Time time qualifier must be present prior to active edge of clock 20 ns max Clock Qualifier Hold Time time qualifier must remain present and stable after active edge of clock 0 ns Data Setup Time time data must be present prior to active edge of clock 30 ns max Data Hold Time time data must remain present and stable after active edge of clock 0 ns BNC Port Outputs Mainframe Rearpanel programmable polarity Stimulus Port 1 TTL pulse output into 50 Ohms Occurs at each recognized event Trigger Events Pulse Width 50 ns 20 ns Delay from clock 225 ns 25 ns Sequencer Events Pulse Width 50 ns 20 ns SAC 1 1 Model 64621A General Information Table 1 1 Specifications Cont d Delay from clock 200 ns 25 ns Halt Port 2 TTL level output into 50 Ohms False at execute true at event recognition or halt Measurement Complete Delay from clock 225 ns 25 ns Trace Point Delay from clock 225 ns 25 ns Table 1 2 Supplemental Characteristics Memory Size Width expandable to 120 channels in combinations of 20 and or 40 channel ac quisition boards max 3 ACQ boards Depth Trace S
96. 23 PSOCINC PSOCINC ECL TTL ICs ON THIS SCHEMATIC REF DES HP PART NO MFG PART U6 19 1820 0802 U17 18 1820 1718 LOWER SEQUENCE TRANSITION UPPER SEQUENCE MEMORY TRANSITION MEMORY ECL AM 256 4 U36 38 40 42 1816 1462 U52 85 1820 1173 1sso 13 U65 83 84 1820 1052 PARTS THIS SCHEMATIC b TSS6 10 b TSS7 44 SEQUENCE STATE LATCHES COUNTER WRITE WRITE EN READ J EN READ POWER SUPPLY iA TA 2 550 estoni CONFIGURATION Lseab2 18 34 5 scava 19 HA 9 256 4 U6 17 19 5 41 LBSP0 3 2 8 Lc WRITE WRITE1 4 EN READ EN READ 1 5 2 15 0014 6 2 LSOCLD U36 38 40 42 LWSEGML 140 14 soos 2 Tap 245 seans 48 345 Lstop 19 Ha 389 2 B 4 LSEGD0 7 Figure 8 13 Sequencer SAC 8 47 Model 64621A Service TO FROM IMB CLOCK PROBE SEB TO FROM OTHER PREPROCESSOR BOARDS asss DECR san gt Q o c o d 2 gt 2 ui 5 Oo Da O o lI
97. 3 7 high U 26 9 73 8 U 97 low U123 9 high U 26 11 73c8 U 97 9 low U 26 12 7379 U 97 11 low U127 1 0000 U 26 13 7319 TOTLZ 24 U 26 14 7329 U 99 4 low U127 2 0000 U 26 15 7331 U 99 5 high TOTLZ 26 U 26 16 733H U 99 6 high U127 3 0000 U 26 17 733C U 99 8 high TOTLZ 24 U 26 18 7338 U 99 9 low 0127 8 0000 U 26 19 0000 U 99 10 low TOTLZ 24 TOTLZ 24 U127 9 0000 U116 6 high TOTLZ 24 U 53 2 U116 8 low U 53 3 8HhA U116 9 high U129 1 high ECL 53 5 659P U129 2 0000 ECL U 53 7 3FU9 U118 2 A285 TOTLZ 24 U 53 9 A285 U118 5 3FU9 U129 3 low ECL U 53 11 A285 U118 6 659P U129 h 7339 ECL U 53 13 3FU9 U118 11 0000 TOTLZ 24 53 15 659P TOTLZ 2 0129 5 high U 53 17 8HhA U129 6 high ECL U 53 18 73F7 0119 16 73F7 0129 13 low ECL U129 1h high ECL SAC h 52 Model 64621A Performance Verification Board 64621 66503 Test 12 Loop VH 9524 MODE EDGES THRESHOLDS CONNECTIONS Normal Clock Positive Data High ST SP Start 19 Start Positive Data Low Qual Stop TP19 Fess Stop Negative Clock TIL Clock U99 3 ST SP QL TIL Ground GND TP levels are TIL except where noted U 1 3 9524 ECL U 97 11 8741 U123 3 high U 1 4 high ECL U 97 12 F8C7 U123 4 AFFP U 1 17 8741 U 97 14 0505 U123 5 26 U 1 35 9524 U123 6 C6F4 TOTLZ 400 U116 1 9524 U123 7 23P0 TOTLZ 400 U123 9 12 U 97 2 0505 U116 6 9524 0123 11 C6FN U 97
98. 3 mV of the value displayed for all six DAC levels If the voltages are not correct there is most likely a problem in the DAC and must be correc ted using the Performance Verification o Connect the positive lead of the DMM to TP12 p Continue pressing RETURN until Reference 433 mV ECL 1 3 V is displayed q Adjust FS1 R23 to 433 mV See Figure 5 1 r Each time RETURN is pressed the D A Converter will be set to a different value Press RETURN six times and verify that the value measured on the DMM is within 33 mV of the value displayed for all six DAC levels If the voltages are not correct there is most likely a problem in the DAC and must be correc ted using the Performance Verification s Press end RETURN end to exit the State Analysis Control Performance Verification SAC 5 4 TEST POINTS 1 NBSRS 2 PBSRS 3 PBPLS 4 HBOWRT 5 HBQWRT 6 LMACS 7 PBOVRST 8 LBOVEN 9 LDV 10 HOVS 11 UTHSH2 12 UTHSH1 13 NO NAME 14 SA CLOCK 15 LSCLK 16 LRUN 17 LMS 18 LPPSTB 19 LMAP2 49 Model 64621A Adjustments T5 T4 T3 T2 Tt R4 R5 R6 R7 R8 CLOCK POD STATE CONTROL BOARD REV A 64621 66501 J3 GND 17 16 1 GND 251 FS FS2 Qlelw NJAJAN 85 64621 STATE CONTROL 5 5 83 ADJUSTMENT LOCATIONS
99. 4 2088 Hewlett Packard Canada Ltd 552 Newbold Street LONDON Ontario N6E 255 Tel 519 686 9181 A C CM E M P Hewlett Packard Canada Ltd 6877 Goreway Drive MISSISSAUGA Ontario L4V 1M8 Tel 416 678 9430 A C CM E M P Hewlett Packard Canada Ltd 2670 Queensview Dr OTTAWA Ontario K2B 8K1 Tel 613 820 6483 A C CM E M P Hewlett Packard Canada Ltd The Oaks Plaza Unit 9 2140 Regent Street SUDBURY Ontario P3E 558 Tel 705 522 0202 Hewlett Packard Canada Ltd 3790 Victoria Park Ave WILLOWDALE Ontario M2H 3H7 Tel 416 499 2550 Quebec Hewlett Packard Canada Ltd 17500 Trans Canada Highway South Service Road KIRKLAND Quebec H9J 2X8 Tel 514 697 4232 A C CM E M P Hewlett Packard Canada Ltd 1150 rue Claire Fontaine QUEBEC CITY Quebec G1R 5G4 Tel 418 648 0726 C Hewlett Packard Canada Ltd 130 Robin Crescent SASKATOON Saskatchewan S7L 6M7 Tel 306 242 3702 C CHILE ASC Ltda Austria 2041 SANTIAGO Tel 223 5946 223 6148 Telex 340192 ASC CK CP sical Ltda Av Italia 634 Santiago Casilla 16475 SANTIAGO 9 Tel 222 0222 Telex 440283 JCYCL CZ CM E M Metrolab S A Monjitas 454 of 206 SANTIAGO Tel 395752 398296 Telex 340866 METLAB CK A Olympia Chile Ltda Av Rodrigo de Araya 1045 Casilla 256 V SANTIAGO 21 Tel 225 5044 Telex 340892 OLYMP Cable Olympiachile Santiagochile CHINA People s Republic of
100. 4 8 Model 64621A Performance Verification p 2 8V OV 3 0 5 HOLDTIME 2 8V OV 30nS SETUP TIME 100nS dl 100nS 2 Figure 4 6 Setup and Hold Time Waveforms sac 4 9 Model 64621A Performance Verification SAC 4 10 s Press execute Verify 11111 for data probe under test Change Pulse Generator 2 to waveform Press execute Verify 00000 for data probe under test Change Pulse Generator 1 to waveform D Press format_specification Press clock is falling edge channel 0 Press execute Verify 00000H for data probe under test Change Pulse Generator 2 to waveform B Press execute Verify 11111 for data probe under test Press clock_is both_edges channel 0 Press execute Verify alternating 00000 and 11111H for data probe under test and time count rel column is 08 uS or 12 uS Model 64621A Performance Verification SOLDERED JUMPER GND BNC SIGNAL Back view looking at solder cups Jumper wire on RS232 solder connector Signal on pins 2 6 8 12 15 24 Signal ground on pin 25 PIN 24 PIN 25 REMAINING PINS OMITTED FOR CLARITY Side view connecting BNC to RS232 connector 5 ro e e e xar IT RIS RR D bana 1251 0063 BNG connector ze eade PUR Hadr de e PA EN EO aei obe VQ peste rl ad lor ur eet
101. 409 hpas dk CE DOMINICAN REPUBLIC Microprog S A Juan Tom s Mej a y Cotes No 60 Arroyo Hondo SANTO DOMINGO Tel 565 6268 Telex 4510 ARENTA DR RCA P ECUADOR CYEDE Cia Ltda Avenida Eloy Alfaro 1749 y Belgica Casilla 6423 CCI QUITO Tel 450 975 243 052 Telex 22548 CYEDE ED Medtronics Valladolid 524 Madrid P O 9171 QUITO Tel 223 8951 Telex 2298 ECKAME ED A Hospitalar S A Robles 625 Casilla 3590 QUITO Tel 545 250 545 122 Telex 2485 HOSPTL ED Cable HOSPITALAR Quito M Ecuador Overseas Agencies C A Calle 9 de Octubre 818 Box 1296 Guayaquil QUITO Tel 306022 Telex 3361 PBCGYE ED M EGYPT Sakrco Enterprises 70 Mossadak Str Dokki Giza CAIRO Tel 706440 Telex 93146 International Engineering Associates 24 Hussein Hegazi Street Kasr el Ain CAIRO Tel 23829 21641 Telex 93830 IEA UN Cable INTEGASSO S S C Medical 40 Gezerat El Arab Street Mohandessin CAIRO Tel 803844 805998 810263 Telex 20503 SSC UN EL SALVADOR IPESA de El Salvador S A 29 Avenida Norte 1223 SAN SALVADOR Tel 26 6858 26 6868 Telex 20539 IPESA SAL A C CM E P ETHIOPIA Seric Ethiopia Box 2764 ADDIS ABABA Tel 185114 Telex 21150 CP FINLAND Hewlett Packard Oy Piispankalliontie 17 02200 ESPOO Tel 00358 0 88721 Telex 121563 HEWPA SF A C CM E M P FRANCE Hewlett Packard France 2 1 Mercure Rue Berthelot 13763 Le
102. 59 61 63 65 67 PI R36 38 39 43 44 50 51 TP17 18 U37 41 62 75 76 96 98 99 101 103 106 115 117 121 124 125 127 POWER SUPPLY CONFIGURATION 5 3 52 81 ue2 5 U96 99 115 16 124 125 127 5 106 107 U98 101 103 5 0118 121 Figure 8 18 Mainframe Write Interface SAC 8 57 Model 64621A Service TO FROM CLOCK PROBE PREPROCESSOR IMB TO FROM OTHER ia eae o m U gt gt Q o e a gt gt 2 a 5 094 o9 3 Q e TIE 2 2920 reg 9 ch e 5 o Ba 259 elac 2609 lt d LU am Iola 6 o m 05086 One Ok r 10 CR1 R18 CR2 C13 R19 PREPROCESSOR INTERFACE BUS TEST 11 CLOCK BE HMCLK STROBE CONTROL ANALYSIS LINES CONTROLLER 2 83 HQWRITE HWQ g U29 0 LH kd J2 49 PDC ca T5 T4 T3 T2 TI 64621 66501 MP2 R2 9 STATE CONTROL BOARD i print oe CLOCK POD MPI g g e D LTE 10 1 FS1 FS FS2 LSE u4 us 06 us E 93 5 va 010 11 12 TEST 8 HTR cw us b as ee e Ra 015 R10 fe 852 STROBES Roc Dac b dir UND res lita g F g 6 g 828 H Tar T 8 29
103. 6 0160 2055 CAPACTTOR FXD 0107 80 20 100UDC CER 28480 0160 AICI 0150 3793 CAP TIR FXD 680PF 4 12 109VDC MICA 28480 0160 3 A1C18 0160 2055 TQR FXD 01UF 80 20 100900 CER 28480 0150 2 A1C19 0160 2055 DAP TUR FXO 01UF 80 20 190 CER 20480 01060 20 A1C20 0160 2055 TOR FXD 01UF 80 20 100VDO CER 29480 0160 2 1 21 0160 2055 DUE 480 20 1904906 CER 78480 amp 1 22 0160 2055 80 20 100UDC CER 28480 102 9150 2055 3 gt ITOR FXO 01UF 80 297 109VDC CFR 20480 A1C24 0160 2055 TOR FXD OLUF 80 20 100UDC CER 29480 1025 9160 2085 CAPACITOR FXD 01UF 80 P9 180406 CER PRARO A1C26 2160 2055 CAPACTTOR FXD 1UF 80 207 100UDC CER 204980 1027 f 2055 CAPACITOR FXD 91UF B 100UDC CER 28480 1C28 205 CAPACITOR FXD Q1UF POX 100VDO CER 28480 1 29 1 Si 55 CAPACITOR 010 3 190VDC CER 28480 1 30 0150 2055 CAPACTTOR FXD O1UF 80 20 100UDC CER 20480 A1C31 9160 2095 7 CAPACITOR FXD O1UF 80 29 100UDC CER 28480 0160 2055 A1C32 016 055 CAPACTTOR FXD 010 80 20 100UDC CER 29480 0160 2055 A1C33 91460 2085 CAPA amp CIT R FXD 01UF 80207 100VDC CER 28480 0160 2055 A1C34 0160 2055 CAPACITOR FXD 01UF 80 20 100UDC CER 28480 0160 2055 A1C35 0160 2055 CAPACITOR FXD 01UF 80207 100UDC CER 28480 0160 2055 1 36 0100 0178 CAPACTTOR FXD 27PF 5 300VDC MICA 20480 0160 0178 1 57 0160 0178 3 CAPACITOR FXD 5 300VDC MICA 28480 0160 0178 1 38 0160 2055 CAPACITOR FXD O1UF 8
104. 60 2055 CAPACITOR FXD 15UF 10 20VDC TA 289 150D156X9020B2 CAPACITOR FXD 151 10 20V0C TA 56289 1500156 90221 2 CAPACITOR FXD 15UF 10 20VDC TA 56289 1500156 9020 2 1 61 0140 0149 CAPACITOR FXD 470PF 5 300UDC MICA 72136 15 4713030 0WV1CR A1C62 0160 3508 CAPACITOR FXD 1UF B0 20 50VDC CER 28480 0160 3508 A1C63 0160 2055 CAPACITOR FXD 01UF 90 20 100VDC CER 28480 0160 2055 A1C64 0180 1746 CAPACITOR FXD 15UF 10X 20VDC 56289 1500156 9029 2 1 65 0180 1746 CAPACITOR FXD 15UF 10 20VDC TA 5289 150D156X9020B2 ALC66 0180 1746 CAPACITOR FXD 15UF 10 20VDC 56289 1500156 90201 2 A1C67 0160 2055 CAPACITOR FXD 01UF 80 20 100UDC CER 28480 0160 2055 A1C68 0160 2055 CAPACITOR FXD 01UF 80 20 100VDC CER 28480 0160 2055 See introduction to this section for ordering information SAC 6 5 Model 64621A Replaceable Parts Table 6 2 Replaceable Parts List Cont d Reference HP Part Designation Number Description Mfr Part Number AICRI 1901 0050 3 DIODE SWITCHING BOY 200MA ZNS 20480 1901 0050 ALCR2 1901 0050 SWITCHING 80V 200MA 2 5 2480 1901 0050 ALCRS 1901 0050 1 SWITCHING BOV 200MA ONS 20480 1901 0050 ALIS 1251 7005 CONNECTOR SO PIN M POST TYPE 28400 1251 7005 AMP 1 64621 85001 EXTRACTOR BOARD 28480 64621 85001 ALMP2 64621 85002 EXTRACTOR P C BOARD 28400 64621 85002 amp 1MP3 1480 0116 1 PIN GRY 062 TN DIA 25 TN LG STL 28480 1480 0116 ALQI 1854 0215 TRANSISTOR
105. 7000 West Virginia Hewlett Packard Co 501 56th CHARLESTON WV 25304 Tel 304 925 0492 Wisconsin Hewlett Packard Co 275 N Corporate Dr BROOKFIELD WI 53005 Tel 414 784 8800 A C E M URUGUAY Pablo Ferrando S A C e Avenida Italia 2877 Casilla de Correo 370 MONTEVIDEO Tel 80 2586 Telex 802586 A CM E M Olympia de Uruguay S A Maquines de Oficina Avda del Libertador 1997 Casilla de Correos 6644 MONTEVIDEO Tel 91 1809 98 3807 Telex 6342 OROU UY P VENEZUELA Hewlett Packard de Venezuela C A 3A Transversal Los Ruices Norte Edificio Segre 2 amp 3 Apartado 50933 CARACAS 1071 Tel 239 4133 Telex 251046 HEWPACK A C CM E M P Hewlett Packard de Venezuela C A Centro Civdad Comercial Tamanaco Nivel C 2 Nueva Etapa Local 53H05 Chuao CARACAS Tel 928291 Albis Venezolana S R L Av Las Marias Ota Alix El Pedregal Apartado 81025 CARACAS 1080A Tel 747984 742146 Telex 24009 ALBIS VC A Tecnologica Medica del Caribe C A Multicentro Empresarial del Este Ave Libertador Edif Libertador Nucleo Oficina 51 52 CARACAS Tel 339867 333780 M Hewlett Packard de Venezuela C A Residencias Tia Betty Local 1 Avenida 3 y con calfe 75 MARACAIBO Estado Zulia Apartado 2646 Tel 061 7580 1 75805 75806 80304 Telex 62464 HPMAR Hewlett Packard de Venezuela Urb Lomas de Este Torre Trebol Piso 11 VALENCIA Estado
106. 82 C CM E M P UNITED STATES Alabama Hewlett Packard Co 700 Century Park South Suite 128 BIRMINGHAM AL 35226 Tel 205 822 6802 A C M P Hewlett Packard Co 420 Wynn Drive HUNTSVILLE AL 35805 Tel 205 830 2000 C CM E M Alaska Hewlett Packard Co 3601 C St Suite 1416 ANCHORAGE AK 99503 Tel 907 563 8855 CE Arizona Hewlett Packard Co 8080 Pointe Parkway West PHOENIX AZ 85044 Tel 602 273 8000 A C CM E M P Hewlett Packard Co 3400 East Britannia Dr Bldg C Suite 124 TUCSON AZ 85706 Tel 602 573 7400 CEM California Hewlett Packard Co 99 South Hill Dr BRISBANE CA 94005 Tel 415 330 2500 C Hewlett Packard Co 5060 E Clinton Avenue Suite 102 FRESNO CA 93727 Tel 209 252 9652 CM Hewlett Packard Co 1421 S Manhattan Av FULLERTON CA 92631 Tel 714 999 6700 C CM E M Hewlett Packard Co 7408 Hollister Ave A GOLETA CA 93117 Tel 805 685 6100 GE Hewlett Packard Co 5400 W Rosecrans Blvd LAWNDALE CA 90260 Tel 213 643 7500 Telex 910 325 6608 CM Hewlett Packard Co 2525 Grand Avenue Long Beach CA 90815 Tel 213 498 1111 C Hewlett Packard Co 3155 Porter Drive PALO ALTO CA 94304 Tel 415 857 8000 CE Hewlett Packard Co 4244 So Market Court Suite A SACRAMENTO CA 95834 Tel 916 929 7222 A CEM Hewlett Packard Co 9606 Aero Drive SAN DIEGO CA 92123 Tel 619 279 3200 Hewlett Packard 5725 W
107. 87 Telex 411 215 Cable ELECTROBOR DAMASCUS E Middle East Electronics 2308 Abu Rumaneh DAMASCUS Tel 33 45 92 Telex 411771 M TAIWAN Hewlett Packard Taiwan Kaohsiung Office 11 F 456 Chung Hsiao 1st Road KAOHSIUNG Tel 07 2412318 CE Hewlett Packard Taiwan 8th Floor Hewlett Packard Building 337 Fu Hsing North Road TAIPEI Tel 02 712 0404 Telex 24439 HEWPACK Cable HEWPACK Taipei A C CM E M P Ing Lih Trading Co 3rd Floor 7 Jen Ai Road Sec 2 TAIPEI 100 Tel 02 3948191 Cable INGLIH Taipei A THAILAND Unimesa Co Ltd 30 Patpong Ave Suriwong BANGKOK 5 Tel 235 5727 Telex 84439 Simonco TH Cable UNIMESA Bangkok A C E M Bangkok Business Equipment Ltd 5 5 6 Dejo Road BANGKOK Tel 234 8670 234 8671 Telex 87699 BEQUIPT TH Cable BUSIQUIPT Bangkok TOGO Societe Africaine De Promotion Immeuble 22 Rue d Atakpame B P 4150 LOME Tel 21 62 88 Telex 5304 TRINIDAD amp TOBAGO Caribbean Telecoms Ltd Corner McAllister Street amp Eastern Main Road Laventille P O Box 732 PORT OF SPAIN Tel 624 4213 Telex 22561 CARTEL WG Cable CARTEL PORT OF SPAIN CM E M P Computer and Controls Ltd P O Box 51 66 Independence Square PORT OF SPAIN Tel 62 279 85 Telex 3000 POSTLX WG ACCT 10090 AGENCY 1264 Feral Assoc 8 Fitzgerald Lane PORT OF SPAIN Tel 62 36864 62 39255 Telex 22432 FERALCO Cable FERA
108. 9 5 C Rir NU 50 76 15 BUF 162 LASTB 18 1080 Flo 16 LDB2 3 V 3 4 3 V V 3 4 IT 3 V V 3 4 oF IT be V V 3 4 oF IT v 4 94 LDB4 V 3 4 I be V V 3 4 i I P2 V V 3 4 n IT Da V V 3 4 Ij Elm u LDB6 Sa am 2E 4 108 11 5 i LPOP 5 C3 26 29 35 38 C13 14 20 22 25 C4 2 4 16 18 19 24 67 6 11 40 44 46 49 52 56 63 68 28 34 51 67 30 32 39 45 50 57 z 01UF 01UF 01UF 5 C58 5 56 TP19 SA START STOP a a a lt 5 ajajajajajajajaja a duna Pea to sns A S Po SERA DIN ERR a ne kuta z 122222222 9 _ ane or Los 69 aun oo oo o annnno 5 5 PORT2 s onoo MO 79 80 85 86 13 14 3 4 3 4 66 9 10 1 1 37 38 39 Lu TO FROM MAINFRAME 1080 7 4 Model 64621A Service ICs ON THIS SCHEMATIC REF DES HP PART NO MFG PART NO U62 1820 1173 096 99 1820 1197 098 103 1820 1282 U101 102 1820 1216 U106 1820 1281 U115 1820 1199 0117 1820 1423 U118 119 1820 2102 U120 1820 1997 U121 1820 2075 U124 1820 0269 U125 1820 1144 U127 1820 1208 10124 141500 7415109 7415138 7415139 741504 7415123 1415373 1415374 7415245 7403 741502 741532 PARTS ON THIS SCHEMATIC C1 4 11 13 14 16 18 30 32 34 35 38
109. 9 15 high ECL TOTLZ 1 8 2 UF8C U 22 10 0000 U 8 3 73AU TOTLZ 1 U 8 4 734U 20 9 8024 ECL U 22 11 0000 ECL U 8 5 T3AU U 20 10 0000 TOTLZ 1 U 8 6 UF8C TOTLZ 1 U 22 13 0000 ECL U 20 11 0000 ECL TOTLZ 1 TOTLZ 1 U 22 14 8U24 ECL 16 3 18F3 U 20 12 8U24 ECL U 22 15 0000 ECL U 16 6 0965 ECL TOTLZ 1 U 16 7 PhF ECL U 20 13 0000 ECL TOTLZ 1 U 23 2 0000 ECL 20 14 8024 ECL U 23 3 8U24 ECL U17 2 03 ECL U 20 15 0000 ECL U 23 4 0000 ECL U 17 3 Ch27 TOTLZ 1 17 4 1492 ECL U 23 6 0000 ECL U 17 5 high U 21 2 0000 TOTLZ 1 17 6 low ECL U 21 3 8U24 ECL U 23 7 high ECL U 17 7 low ECL U 21 4 0000 ECL TOTLZ 1 U 17 9 low ECL TOTLZ 1 U 23 10 high ECL U 17 10 high ECL U 21 6 0000 ECL U 23 11 73AU ECL U 17 11 18F3 ECL TOTLZ 1 23 13 0000 ECL 17 12 22 ECL U 21 7 0000 ECL U 23 14 8U24 ECL 17 13 PP34 ECL TOTLZ 1 TOTLZ 1 U 17 14 F61U ECL U 23 15 0000 ECL U 17 15 78AA ECL SAC 4 32 Model 64621A Performance Verification Board 64621 66503 Test 1 Loop A VH 8U24 MODE EDGES THRESHOLDS CONNECTIONS Normal Clock Positive Data High ST SP Start TP19 Start Positive Data Low Qual Stop TP19 Stop Negative Clock TIL Clock U99 pin 3 ST SP QL TIL Ground GND TP levels are TIL except where noted 8 15 78AA ECL U 52 5 T3AU 8 16 F61U ECL U 52 T high U 52 10 U 24 2 73AU ECL U 24 h T3A
110. 936 938 040 042 STROBES 30 31 C32 C33 C34 Oeno _c35 og 5 C28 U568 3 29 z z 7 n gt n 5 a 058 059 060 U61 U62 063 064 065 066 Uer is B we cha se LJ a lt a JO r STATE TIME puo COUNT STATUS pM go SU En nod ec COT 2 COUNTER MEMORY 1 Pope td TEST 5 7 TEST 6 ues vs 090 U91 092 u93 1 8 U78 079 U80 081 082 083 084 085 087 088 T U94 L J E aes LIL cm Sui haa Wines E 45 ee as ass E R40 um 0113 Er U97 U98 9100 U101 9103 0104 0106 E Re C53 n 0112 gt C51 52 css R4 5 R47 C57 R48 0130 lt S O n ROS GND uza RIT CONTROL 9 4 TPI7 C67 58 24 _ R51 ET R54 64 ADDRESS es T 12 mp es 60 SA START STOP NEM i ai P1 5 5 83 o I 64621A STATE CONTROL gt 5 d MAINFRAME INTERFACE TEST 1 Block Diagram Component Locator SAC 8 42 TO FROM CLOCK PROBE PREPROCESSOR qq aut 64621 66503 CLOCK PROBE PREPROCESSOR J3 P O A1 STATE ANALYSIS CONTROL BOARD INTERFACE M E 4 8 LABO 3 LWATB gt V 2 aja ajoja e ola lt 5 EJ a
111. A C CM E M P AUSTRIA Hewlett Packard Ges m b h Verkauisb ro Graz Grottenhofstrasse 94 A 8052 GRAZ Tel 0316 291 56 60 Telex 32375 CE Hewlett Packard Ges m b h Lieblgasse 1 P O Box 72 A 1222 VIENNA Tel 0222 2500 0 Telex 134425 HEPA A A C CM E M P BAHRAIN Green Salon P O Box 557 MANAMA Tel 255503 255950 Telex 8441 Wael Pharmacy Box 648 Tel 256123 Telex 8550 WAEL BN Zayani Computer Systems 218 Shaik Mubarak Building Government Avenue Box 5918 MANAMA Tel 276278 Telex 9015 BELGIUM Hewlett Packard Belgium S A N V Bivd de la Woluwe 100 Woluwedal B 1200 BRUSSELS Tel 02 762 32 00 Telex 23 494 paloben bru A C CM E M P BERMUDA Applied Computer Technologies Atlantic House Building Par La Ville Road Hamilton 5 Tel 295 1616 P BRAZIL Hewlett Packard do Brasil l e C Ltda Alameda Rio Negro 750 Alphaville 06400 BARUERI SP Tel 011 421 1311 Telex 011 33872 HPBR BR Cable HEWPACK Sao Paulo A C CM E M P Hewlett Packard do Brasil Le C Ltda Praia de Botafago 228 6 Andar conj 614 Edificio Argentina Ala A 22250 RIO DE JANEIRO Tel 02 552 6422 Telex 21905 HPBR BR Cable HEWPACK Rio de Janeiro Convex Van Den Rua Jose Bonifacio 458 Todos Os Santos CEP 20771 RIO DE JANEIRO RJ Tel 591 0197 Telex 33487 EGLB BR A ANAMED 1 C E Ltda Rua Bage 103
112. AC can be read through the Tracepoint Register and the Trace MAC Read Register 461 Write Loop The main loop loop F of this test takes signatures when the RAMs are being read and while the RAM addresses are being selected from the CPU via U86 and a high on the select line of the Trace Count Status Memoery Address selector The write loop loop G allows the RAM addresses to be tested when the Memory Address Counter is selected 4 62 Previous tests have verified the functioning of the MAC and its associated Trace MAC Read Register Test 5 used the Address Selector and location 00 Hex of the memory Therefore the most likely failures detected by this test are the remaining memory locations particularly U70 U73 and U90 which were not tested in Test 5 4 63 Other circuitry tested for the first time include U67 Tracepoint Register U98 Wrap bit and Post Trace Point Counter function of 101 4 64 Results all testing results are read at the Analysis Status Buffer U122 and the CPU Data Buffer U121 10 MHz State Test Board in Slot 2 Pass Tested 1 Failed 0 Slot 2 State Control and Clock Test 6 Trace memory 1 Error Address Bit Memory Channel 76543210 10987554 21098765432109876543210 Address Counter 00000000 Trace Point Req 00000000 Trace Point Wrap 00 Store seq state 00000000 mostly 1 4 00000000000000000000000000000000 mostly 076 0000000000000000000000000000000 Addrass Test 00000000 00000000000000000000000000000000 Inde
113. AL z ADDITIONAL ADDITIONAL aco Bos V ACQ 805 ACO BDS o 1 um UEN 1 Fs T EAD CLOCK TERM GENERATOR VU ag HBOWRT HBOWRT REGISTER PELS CK HCLKO P STROBE oe EDGE GENERATOR RESOURCE ALLOCATION TRA DETECT SS AND GATING TRACE STATE TIME COUNTER TRACE COUNT STATUS MEMORY m STROBE READ maa P NBSRS 4 OVERVIEW COUNT QUAL OVERVIEW COUNT OVERVIEW RESISTER TRACE COUNT QUAL 1550 7 CLK OEN li DENEN RESOURCE GATING mas SEQUENCER dee Li n TO OTHER RECOGNITION Q STORAGE TERM 0 7 SIORAGE cae CO COUNT STATUS P NDSTB LRTDR LEVEL SELCT mm av ace LCLKL7 AND EDGE GANG TRIGGER TERM 0 7 TRACE UAL PINC MEMORY FROM TRACE Mind GATING pea COUNT STATUS MENE 8 ADDRESS 1080 7 EDGE DET Gaal ene MEMORY ADDRESS COUNTER CPU 125MHz ADDRESS SELECTOR REGISTER DATA TO OTHER 3 LBSPO 2 LOVEN 3 0 TIME COUNTER CLK DEN BUS EDGE DET LOVRST D CLK SEL Eu HQWRITE H HQWRITE PMACRS IRMACR gt CPU RESHO LOCCRY see SEQUENCE 2 155 1550 THRESHOLD 8550 3 4 OCCURRENCE sequence LATCH TRANSITION LSME gt OCCURRENCE COUNTER 1507 MEMORIES 2 V LSTE HSTR fesses 05 POINT VTHSHI COUNTER gt RESO MEMORIES COUNTER TRIGGER REGISTER THRESHOLD GATING HQWRITE GNDSEN D A CLK OEN CONVERTER 2 PSOCINC 4 VIHSH2 2 _ LSOCLD LSOCEN LTRCP LRTPRG THRESHOLD 8550 3 D A TO TRACE STATE TIME COUNTER CONVERTER E LWRAP ANALYSIS TO TRACE MEMORIES AND COUNTER SI
114. AT Tel 2445111 Telex 22247 MATIN KT Cable MATIN KUWAIT W J Computer Services Box 5897 SAFAT Tel 2462640 Telex 30336 TOWELL KT LEBANON Computer Information Systems S A L Chammas Building P O Box 11 6274 Dora BEIRUT Tel 89 40 73 Telex 42309 LIBERIA Unichemicals Inc Box 4509 MONROVIA Tel 224282 Telex 4509 E MADAGASCAR Technique et Precision 12 rue de Nice P O Box 1227 101 ANTANANARIVO Tel 22090 Telex 22255 LUXEMBOURG Hewlett Packard Belgium S A N V Blvd de la Woluwe 100 Woluwedal B 1200 BRUSSELS Tel 02 762 32 00 Telex 23 494 paloben bru A C CM E M P MALAYSIA Hewlett Packard Sales Malaysia Sdn Bhd 9th Floor Chung Khiaw Bank Building 46 Jalan Raja Laut KUALA LUMPUR Tel 03 986555 Telex 31011 HPSM MA A C E M P Protel Engineering 1917 Lot 6624 Section 64 23 4 Pending Road Kuching SARAWAK Tel 36299 Telex 70904 PROMAL MA Cable PROTELENG MALTA Philip Toledo Ltd Birkirkara P O Box 11 Notabile Rd MRIEHEL Tel 447 47 455 66 Telex 1649 MAURITIUS Blanche Birger Co Ltd 18 Jules Koenig Street PORT LOUIS Tel 20828 Telex 4296 MEXICO Hewlett Packard de Mexico S A Francisco J Allan 30 Colonia Nueva Los Angeles 27140 COAHUILA Torreon Tel 37220 Hewlett Packard de Mexico S A Monti Morelos 299 Fraccionamiento Loma Bo
115. ATUS HQWRITE M sl BUFFER _ _ ANALYZER ENABLE POST TRACE CROFT HWRT HDVLD 10807 LRUN COUNTER COMPLETE Hooy PREPROCESSOR ANALYZER CLK om LIWRT ENABLE HBOWRT 1103 BUS GATING PSOCINC NTRIG HAET NSEQEV NTRIG IMB DRIVE PORTL 2 IMB RECEIVE UIN DD NSEQEV LSE PORT ORTI REAR HIR LATCHES STATE LTE HIR LSE IMB LTE HIR PIPELINE LSME LRUN PPIB RECOGNITION LTE HTR REGISTER REGISTER CLK CONTROL BOARD PWRUN CPU LME LTE HTR LSE PDC Figure 8 1 State Analyzer Subsystem Block Diagram SAC 8 5 Model 64621A Service 8 34 CONTROL BOARD BLOCK DIAGRAM 8 35 The Model 64621A State Analysis Control Board consists of the following nine basic functional groups Clock Probe Interface Preprocessor Interface Bus Strobe Generator Sequencer Analysis Controller BNC Control Trace State Time Counter Trace Count Status Memory Mainframe Interface 8 36 CONTROL BOARD BLOCK DIAGRAM THEORY 8 37 CLOCK PROBE INTERFACE The Clock Probe Interface consists of the Clock Term Generator chip U25 and the D A Converters U54 and U55 The Clock Term Generator allows eight different clocks to be input to the State Analyzer The eight clocks may be used in various qualification patterns The Clock Term Generator outputs a master clock to the
116. AUS eec OUR D SE cone 2 5 Section Ill Operation 351 INTRODUCTION 5 999 ev Ure RR EA RE RUE V Re UE E 3 1 Section IV Performance Verification 4 1 INTRODUCTION REAGITO RA IT RANA 4 1 4 7 OPERATION VERIFICATION 4 1 4 8 PERFORMANCE VERIFICATION 4 1 WET MANUAL TESTS i236 o ese 4 2 4 12 TEST 1 INPUT THRESHOLD and MINIMUM SWING 4 2 4 13 TEST 2 INPUT THRESHOLD RANGE 4 2 4 14 TEST 3 MIN CLOCK WIDTH amp QUAL SETUP amp HOLD TIME 4 2 4 15 TEST 4 DATA SETUP amp HOLD TIME amp QUAL CLOCK RATE 4 6 4 16 TEST 5 BNC PORT OUTPUTS 4 12 li 1T TROUBLESHOOTING 4 2022 ERI wate NE A OS 4 16 4 25 TEST 1 MAINFRAME INTRFC and STIMULUS LOOP 4 18 4 31 TEST 2 CONTROL SHIFT REGISTER LOOP B 4 20 4 36 TEST 3 CLOCK IC SHIFT REGISTER LOOP 4 21 4 41 TEST SEQUENCER LOOP D 4 22 4 50 TEST 5 STATE COUNT LOOP E 4 25 4 58 TEST 6 TRACE MEMORY LOOPS 4 27 4 67 TEST 7 OTHER COUNTER TESTS 4 29 hsTi TEST 8 INTERMODULE BUS
117. Block Diagram iv es 8 11 Figure 8 4 Strobe Generator Block 8 12 Figure 8 5 Strobe Timing 1 1 1 8 14 Figure 8 6 Sequencer ia aaa 8 15 Figure 8 7 Sequencer Block 8 18 Figure 8 8 Analysis Controller Summary Spa TES acs 4a 8519 Figure 8 9 Analysis Controller Block La guru ae e a ala 8 23 Figure 8 10 State Time Counter Block Diagram E 8 26 Table 8 1 1 5255555 5 2 54 eA Ea 8 27 Table 8 2 Schematic Diagram Qa ga persa zia Table 8 3 Logic 1 Reg 8 41 Figure 8 11 Probe Preprocessor 8 43 Figure 8 12 Strobe Generatori iui senti ERIS RR UE NU RR RS RICE a 8 45 Figure 8 13 Sequencer vaya Mrs RC ME EE ek yup eae BUT Figure 8 14 Sequence Occurrence 8 49 Figure 8 15 Analysis 11 2 8 51 Figure 8 16 Trace State Time RR 2 8 53 Figure 8 17 Trace Count St
118. Boards The State Data Acquisition Boards may be the 40 Channel State Data Acquisition Board the 20 Channel State Data Acquisition Board or a combination of the two Acquisition Boards State Analyzer will have the necessary number of Data and Clock Probes for the Acquisition Boards used Models 64635A and 64636A 1 16 Up to three Acquisition Boards may be combined to form a State Analyzer with as many as 120 channels 1 17 Logic Analyzers within one Mainframe may be connected together using the Inter Module Bus IMB One possible use of the IMB is to allow a State Analyzer to trigger a Timing Analyzer or another State Analyzer SAC 1 4 Model 64621A Installation SECTION Il INSTALLATION 2 1 INTRODUCTION 2 2 This section contains information for installing and removing the Model 64621A Included are initial inspection procedures preparation for use and instructions for repacking the instrument for shipment 2 3 INITIAL INSPECTION 2 4 Inspect the shipping container for damage If the shipping container or cushioning material is damaged it should be kept until contents of the shipment have been checked for completeness and the instrument has been checked mechanically and electrically Procedures for checking electrical performance are given in Section IV If the contents are not complete if there is mechanical damage or defect or if the instrument does not pass the Performance Tests notify the nearest Hewlett P
119. C GATE ECL QUAD 2 INP 10 CLUCK GENERATOR MISC TTL 15 NETWORK RES 10 S1P10 0K OHM IC 8 DIP P PKG OP AMP GP PKG V REF B DIP C NETWORK RES 10 STP240 0 OHM NETWORK RES 10 STP240 0 Chim NETWORK RES 10 G81P240 0 DHM NETWORK RES 10 GIP240 0 NETW RK RES 10 STP240 0 OHM 04713 04713 20400 01295 01121 31295 01295 04713 01321 91121 01121 01121 01121 ECL Z10K 1024 1K STAT RAM t0 NS 50167 NETWORK RES 10 S51P240 0 OHM X ECL 19K 1024 1K STAT RAM NETWORK RES 10 51P240 0 OHM X IC EELZIOK 1024 1K STAT RAM NETWORK RES 10 S P240 0 OHM X 81121 50167 03121 59167 01121 IC ECL 19K 1024 1K STAT RAM 10 5 50167 OR NOR DUAL 4 2A TE NOR QUAD 2 NP GATE ECL AND QUAD 2 INP NETWORK RES 51IP 20 0 OHM X 4 NETWURK RES B8 G1P220 0 NETWORK RES 8 S1P220 0 OHM TC REYR ECL LINE RCVR QUAD 2 INP NETWORK RES 8 5 220 0 OHM X 4 RCUR ECL LINE RCUR QUAD INP 4 4 IC XLIR ECL TT TO ECL QUAD 2 DRUR TTL LS LINE DRUR CONV 8 BR D A 20 DIP P PKG IC CONV 8 B D A 20 DIP P PKG NETWORK RES 10 51P470 0 OHM X 9 NETWORK RES 8 S1P47 0 OHM X 4 ECL 10K 64 RIT STAT 6 5 Ic 2 64 STAT 6 NS IC 64 BIT STAT RAM 6 5 Ic oh 64 H T STAT RAM 6 8 TC TTL TO ECL QUAD 2 R TTL TO ECL QUAD 2 INP IC XL TTL TO ECL QUAD 2 INP IC ECL TO TTL QUAD 2 INP
120. Carabobo Apartado 3347 Tel 041 222992 223024 CP YUGOSLAVIA Do Hermes General Zdanova 4 YU 11000 BEOGRAD Tel 340 327 342 641 Telex 11433 ACEP Hermes Titova 50 YU 61000 LJUBLJANA Tel 324 856 324 858 Telex 31583 CEMP Elektrotehna Titova 51 YU 61000 LJUBLJANA CM ZAIRE Computer amp Industrial Engineering 25 Avenue de la Justice B P 12797 KINSHASA Gombe Tel 32063 Telex 21552 CP ZAMBIA R J Tilbury Zambia Ltd P O Box 32792 LUSAKA Tel 215590 Telex 40128 E ZIMBABWE Field Technical Sales Private Limited 45 Kelvin Road North P O Box 3458 HARARE Tel 705 231 Telex 4 122 RH Manual Part Number 64621 90903 Printed in U S A JUNE 1983 HEWLETT Replaces 64621 90901 March 1982 PACKARD
121. China Hewlett Packard Ltd 47 F China Resources Bldg 26 Harbour Road HONG KONG Tel 5 8330833 Telex 76793 HPA HX Cable HP ASIA LTD China Hewlett Packard Ltd P O Box 9610 Beijing 4th Floor 2nd Watch Factory Main Bldg Shuang Yu Shu Bei San Huan Rd Hai Dian District Tel 28 0567 Telex 22601 CTSHP CN Cable 1920 Beijing A C CM E M P COLOMBIA Instrumentaci n H A Langebaek amp Kier S A Carrera 4A No 52A 26 Apartado Aereo 6287 BOGOTA 1 D E Tel 212 1466 Telex 44400 INST CO Cable AARIS Bogota Nefromedicas Ltda Calle 123 No 9B 31 Apartado Aereo 100 958 BOGOTA D E 10 Tel 213 5267 213 1615 Telex 43415 HEGAS CO A Compumundo Avenida 15 107 80 BOGOTA D E Tel 214 4458 Telex 45466 MARICO Carvajal S A Calle 29 Norte No 6A 40 Apartado Aereo 46 CALI Tel 368 1111 Telex 55650 CEP CONGO Seric Congo B P 2105 BRAZZAVILLE Tel 815034 Telex 5262 COSTA RICA Cientifica Costarricense S A Avenida 2 Calle 5 San Pedro de Montes de Oca Apartado 10159 SAN JOSE Tel 24 38 20 24 08 19 Telex 2367 GALGUR CR CYPRUS Telerexa Ltd Box 4809 14C Stassinos Avenue NICOSIA Tel 62698 Telex 2894 LEVIDO CY DENMARK Hewlett Packard A S Datavej 52 DK 3460 BIRKEROD Tel 02 81 66 40 Telex 37409 hpas dk A C CM E M P Hewlett Packard A S Rolighedsvej 32 DK 8240 RISSKOV Aarhus Tel 06 17 60 00 Telex 37
122. Enable permits action Set Input AND permits action OR permits action Mode selects action Interconnection Transmission LS 04 08 83 2 gt Dynamic 1 Exclusive OR L Hysteresis Interrogation Internal Connection Borrow Generate Borrow Input Borrow Output Borrow Propagate Carry Generate Carry Input Adder OR Passive Pull Down internal resistor Passive Pull Up internal resistor Postponed Shift Left or up Arithmetic Logic Unit Comparator Divide By Equal To Binary Coded Decimal Binary Buffer Counter Decimal Astable 10012 Delay Used for factoring terms using algebraic techniques Information not defined Logic symbol not defined due to complexity LABELS Carry Output Carry Propagate Content Data Input Extension input or output Function MATH FUNCTIONS CHIP FUNCTIONS DIR Directional DMUX Demultiplexer FF Flip Flop MUX Multiplexer OCT Octal DELAY and MULTIVIBRATORS Uni Nonretriggerable Monostable NV Ju J Input K Input Operand Transition Count Up Count Down Greater Than Less Than Look Ahead Carry Generator Multiplier Subtractor Random Access Memory Line Receiver Read Only Memory Segment Shift Register Nonvolatile State of initial power up Retriggerable Monostable LS 04 08 83 3 SAC 8 41 Model 64621A Service TO FROM IMB CLOCK PROBE SEB TO FROM OTHER PREPROCESSOR BOARD
123. F8 U103 2 802 0 81 9 1C85 U100 3 192 TOTLZ OFLO U 81 10 h2C2 ECL U100 h 8877 U103 3 8 24 U 81 11 1685 U100 5 7755 U103 h 6579 U 81 12 low ECL U100 7 8877 U103 6 high U 81 13 080P ECL U100 9 high U103 7 low U100 10 high U100 11 high U 82 4 15662 ECL U100 12 high U106 2 8877 U 82 5 PPHP ECL U106 3 8 24 U 82 6 5HA1 ECL TOTLZ OFLO U 82 7 PFH9 ECL 0101 1 10 0106 4 8021 U 82 9 1563 0101 2 ChF8 TOTLZ 4641 U 82 10 9 ECL 0101 3 A192 U106 5 8U24 U 82 11 10563 0101 4 0753 TOTLZ OLFO U 82 12 low ECL U101 5 0871 U106 6 8877 U 82 13 080P ECL U101 6 1407 U106 7 0753 0101 7 U101 9 6110 85 5 0101 10 872 U115 8 U871 U 85 10 872A 0101 11 FFU9 0115 9 7755 U 85 11 6110 0101 12 U115 12 1407 0101 13 25HU 0115 13 9C23 U101 14 5A59 U 85 4 22F4 ECL 0101 15 73AU 85 12 080P ECL U117 2 0000 U 85 13 PP34 TOTLZ 1 U102 1 1UPP 0117 3 09 0102 2 CUF8 0117 13 U 89 1 high U102 3 A192 U102 h 0753 U102 5 U871 U118 2 8U2h U 96 11 7755 0102 6 9C23 U118 3 8U24 U 96 12 0871 0102 7 THO9 TOTLZ OFLO U 96 13 high 0102 9 high U118 11 0000 0102 10 6C7U TOTLZ 70347 SAC 4 35 Model 64621A Performance Verification Board 64621 66503 Test 1 Loop A VH 8U24 MODE EDGES THRESHOLDS CONNECTIONS Normal Clock Positive Data High ST SP Start TP19 Start Positive Data Low Qual Stop TP19 aeons Stop
124. H 2 FFU9 4 25HU 5 5A59 508P 6302 35TP 99FT 1 6302 2 508 4 99F7 5 357P 5 4871 048c 8PC9 1 34871 2 5 3 8PC9 5 o48c 0000 TOTLZ 1 ECL U 67 1 high ECL ECL ECL U 68 1 high ECL U 69 1 high U 78 4 0965 ECL U 78 5 PPHP ECL U 78 6 PHF6 ECL U 78 h2c2 ECL ECL U 78 9 1685 ECL ECL U 78 10 4ec2 ECL U 78 11 1 85 ECL ECL U 78 12 low ECL U 78 13 080P ECL U 79 3 8024 U 79 4 PUF6 ECL U 79 5 PPHP U 79 6 hcc2 ECL U 79 9 ECL ECL U 79 9 U5C3 ECL U 79 10 PFH9 ECL ECL U 79 11 U5C3 ECL U 79 12 low ECL U 79 13 080P U 80 2 PhF6 ECL U 80 3 PhF U 80 4 PUF6 ECL U 80 5 5 1 ECL U 80 6 PhF6 ECL ECL U 80 7 UCC2 ECL U 80 10 PhF6 ECL ECL U 80 11 4cc2 ECL ECL U 80 12 4CC2 ECL U 80 13 5HA1 ECL Model 64621A Performance Verification Board 64621 66503 Test 1 Loop 8U24 MODE EDGES THRESHOLDS CONNECTIONS Normal Clock Positive Data High ST SP Start TP19 Start Positive Data Low Qual Stop TP19 Stop Negative Clock TTL Clock U99 pin 3 atea ST SP QL TTL Ground GND TP levels except where noted U 80 14 P24A ECL 0 99 11 7755 0102 11 8 24 U 80 15 ECL U 99 12 8124 0102 12 high TOTLZ 70347 U102 13 high U 99 13 0871 U102 14 9153 U 81 4 PhF ECL 0102 15 2FF1 U 81 5 PPHP ECL U 81 6 high ECL U100 1 1UPP U 81 7 4262 ECL U100 2 Ch
125. HP 64000 Logic Development System Model 64621A State Analysis Control Board UJ Prat CERTIFICATION Hewlett Packard Company certifies that this product met its published specifications at the time of shipment from the factory Hewlett Packard further certifies that its calibration measurements are traceable to the United States National Bureau of Standards to the extent allowed by the Bureau s calibration facility and to the calibra tion facilities of other International Standards Organization members WARRANTY This Hewlett Packard system product is warranted against defects in materials and workmanship for a period of 90 days from date of installation During the warranty period HP will at its option either repair or replace products which prove to be defective Warranty service of this product will be performed at Buyer s facility at no charge within HP service travel areas Outside HP service travel areas warranty service will be performed at Buyer s facility only upon HP s prior agreement and Buyer shall pay HP s round trip travel expenses In all other cases products must be returned to a service facility designated by HP For products returned to HP for warranty service Buyer shall prepay shipping charges to HP and HP shall pay shipping charges to return the product to Buyer However Buyer shall pay all ship ping charges duties and taxes for products returned to HP from another country HP warrants that its softw
126. IGURATION 20 14 57 026 53 5 us 9 25 T9 5 Vcc 5 _ 251173132 Model 64621A Service Figure 8 11 Probe Preprocessor Interface SAC 8 43 Model 64621A Service TO FROM IMB CLOCK PROBE SEB TO FROM OTHER PREPROCESSOR BOARD A s gt 2 2 w gt o a 5 9 xE m 2 olze Ole ORE 4 1 lt oiu zu e e gt T5 T4 T3 T2 64621 66501 MP2 2 Tic c oa 7 er Zoo c DE ZIO OG PDC 4 R2 9 STATE CONTROL BOARD d ur imua Oln a mlu lt LME i pisn A TOCK BOD MES lt O gt il o nn N Ojo Alcoa OT II LTE i Mi 1 FS1 FS FS2 Us U6 m Ul 25 B LSE 3 5 Us i 010 Cn ore TEST 8 HTR Sasu Ge a rar lle 2 F R28 PREPROCESSOR CLOCK STROBES o Um m iE INTERFACE PROBE HMCLK STROBE CONTROL ANALYSIS U16 Ui7 U18 vis 1 u20 021 G U2 U23 1 U24 8 THN BSL 2 2
127. INAL TEST POINT PCE 00000 ORDER TERMINAL TEST POINT 00000 ORDER CRIPTION TERMINAL TEST POINT PCB 00000 ORDER RIPTION TERMINAL TEST POINT 00000 QRDER CRIPTION TERMINAL TEST POINT PCR 00000 ORDER BY DESCRIPTION TERMINAL TEST POINT PCB 00000 GRDER DESCRIPTION TERMINAL TEST POINT 00000 URDER DESCRIPTION See introduction to this section for ordering information SAC 6 6 Model 64621A Replaceable Parts Table 6 2 Replaceable Parts List Cont d HP Part Number Reference Description Mfr Part Number Designation 101 0103 ALU4 ALUS 1U6 A1U7 ALUB 109 1U10 1U11 1U12 611013 ALUL4 ALUS 1016 02017 AIIB 241019 1 20 021 A1022 01123 1024 1029 81026 ALU27 1028 1029 1030 ALUS1 A1U32 ALUSS ALUS 1035 136 61137 610138 1059 91440 ALU41 ALU42 ALU4S 81044 3045 1046 21047 21048 1049 1090 ALUS AlUS2 ALUSS 1054 ALUSS A1US6 21057 41058 1059 21060 1061 41062 1063 81064 ALU6S A1U66 A1U67 A1U68 1U69 611070 1071 41072 1073 41074 A1U75 41076 1964 5010 1810 0273 1810 0298 1820 2359 1820 1400 1820 0802 1820 5 1820 1810 0298 1810 0280 1810 0280 1810 0302 1810 0298 1820 1201 1810 027 1820 1831 1820 1788 1820 1760 1820 0802 1820 0802 1820 1944 1820 1944 1820 0817 1820 1400 1464 5018 1820 2075 1810 0280 1826 0271 1826 0271
128. L TTL L GATE TTL DRVR TTL GATE TTL S D TYPE POS EDGE TRIG NAND QUAD 2 INP LG NOR QUAD 2 INP LINE DRVR RUAD LS OR QUAD 2 INP NETWORK RES 10 SIP240 0 OHM X 9 IC XLTR E NETWORK TTL TO ECL QUAD 2 INP 55 10 51 470 0 OHM X 9 40 CONT DIP DIP 40 CONT DIP DIP 20 CONT DIP DIP NT DIP DIP SONT DIP DIPS CONT DIP DIP ONT DIP DIP CONT DIP DIP DIP DIP 5L DIP_DIP S DIP DIP DIP DIP DIP DIP DIP DIP DIP DIP DIP DIP 14 CONT DIP DIP 04713 07263 07263 04713 07263 07263 04713 04713 04713 03295 07263 07263 07263 04713 21121 01295 01295 01295 01295 01295 1295 01295 012985 01295 91295 01295 91295 04713 04713 04713 01121 29490 91121 01295 01295 01295 n1295 0129 31295 01295 01295 91295 01295 01295 27014 01295 81121 04713 21121 28480 20490 28480 2848 8 CRAB 28480 28480 See introduction to this section for ordering information Mfr Part Number 101251 F1C016DC F100160C MC103031 F100160C Fi1 0Q016DC WG 10121 MC1012 C191 24 SN741 8374N SN74LS1238N SN74LS5158N SN74LS374N 93 422PC 93 422PC 93LA22PC 93L422PC 1 01291 2106471 SN7ALSOON SN 4LS107AN 4741 5109 47 41 508 SN 41 513 8 74L5138N 7416138 1 510 9 SN74L81616N 241 6161 9 741 5139 47 41 5109 MC101 610125 WC 01251 2106471 INE4 S009 2
129. L 0 1 30 3078 U 18 2 H772 ECL U 38 2 2020 ECL U 1 33 0000 ECL U 18 3 3500 U 38 4 ECL TOTLZ 67701 U 18 4 AU30 ECL U 38 6 6297 ECL U 1 36 FP73 ECL TOTLZ 0 U 38 T H410 ECL U 1 37 12 ECL U 18 5 15 ECL U 38 8 PF6C ECL U 1 38 2020 ECL U 18 6 8505 ECL U 38 9 H772 ECL U 1 39 69P1 ECL U 18 7 PC61 ECL U 38 10 FFO8 ECL U 1 40 3078 ECL U 18 9 7F78 ECL U 38 11 7933 ECL U 18 10 A2UF ECL U 38 13 741A ECL U 5 2 0000 ECL U 18 11 H31H ECL U 38 14 9hFH ECL TOTLZ 66382 U 18 12 7 8 ECL U 38 15 ECL U 5 3 0000 ECL 18 13 5451 ECL U 38 16 0837 ECL TOTLZ 66382 U 18 14 7933 ECL U 38 17 3500 ECL U 5 4 0000 ECL U 18 15 FFO8 ECL U 38 18 FPh9 ECL U 5 5 026 ECL U 38 19 0 9 ECL U 5 6 0000 ECL 0 19 9 8505 ECL U 38 21 12 5 7 HO26 0 19 12 CAUH ECL U 38 23 3078 U 5 10 0000 ECL U 19 15 69 1 ECL U 5 11 U 40 2 U15C ECL U 5 14 0000 ECL U 40 4 3357 ECL TOTLZ 531 U 40 6 5093 ECL SAC 4 39 Model 64621A Performance Verification Board 64621 66503 Test 4 Loop D AU30 MODE EDGES THRESHOLDS CONNECTIONS Normal Clock Positive Data High ST SP Start TP19 Start Positive Data Low Qual Stop TP19 lt P sie Stop Negative Clock TIL Clock U99 pin 3 ST SP QL TIL Ground GND TP levels are TIL except where noted U 0 7 70CH ECL U 58 1 8800 ECL U 61 1 19UP ECL U 40 8 5388 ECL U 58 2 7038 ECL U 61 2 8
130. LCO M TUNISIA Precision Electronique S A R L 31 Avenue de la Liberte TUNIS Tel 893937 Telex 13238 Tunisie Electronique S A R L 94 Av Jugurtha Mutuelleville 1002 TUNIS BELVEDERE Tel 280144 Telex 13238 CEP Corema S A 23 bis Rue de Marseille TUNIS Tel 253 821 Telex 14812 CABAM TN M TURKEY E M A Mediha Eldem Sokak No 41 6 Yenisehir ANKARA Tel 319175 Telex 46912 KTX TR Cable EMATRADE ANKARA M Teknim Company Ltd Iran Caddesi No 7 Kavaklidere ANKARA Tel 275800 Telex 42155 TKNM TR E CM Saniva Bilgisayar Sistemleri A S Buyukdere Caddesi 103 6 Gayrettene ISTANBUL Tel 1727030 Telex 26345 SANI TR CP Best Inc Esentepe Gazeteciler Sitesi Keskin Kalemy Sokak 6 3 Gayrettepe ISTANBUL Tel 1721328 Telex 42490 A UNITED ARAB EMIRATES Emitac Ltd P O Box 1641 SHARJAH Tel 591181 Telex 68136 EMITAC EM Cable EMITAC SHARJAH E C M P A Emitac Ltd P O Box 2711 ABU DHABI Tel 8204 19 20 Cable EMITACH ABUDHABI Emitac Ltd Box 8391 DUBAI Tel 377591 Emitac Ltd P O Box 473 RAS AL KHAIMAH Tel 28133 21270 UNITED KINGDOM GREAT BRITAIN Hewlett Packard Ltd Trafalgar House Navigation Road ALTRINCHAM Cheshire WA14 1NU Tel 061 928 6422 Telex 668068 ACEMP Hewlett Packard Ltd Miller House The Ring BRACKNELL Berks RG12 1XN Tel 0344 424898 Telex 848733 E Hewlett Packard Ltd Elstree House Elstree Wa
131. LDBO 7 and LSEQDO 7 Low Store Flag an Analysis Controller output LSFLG is used as a flag in the Trace Counter Status Memories When low LSFLG indicates when storage is enabled Low Store Flag Buffered LSFLGB is the same as LSFLG except translated from an ECL level to a TTL level When low LSFLG indicates when storage is enabled Low Sequence Master Enable an Analysis Controller input When low LSME enables the LRUN portion of the Analysis Controller LSME is an output of the Sequence Transition Memory Low Sequence Overview Count Enable an Analysis Controller input When low LSOCE enables LBRPO 7 to generate HOVCQ LSOCE is an output of the Sequence Transition Memory Low Sequence Occurrence Counter Enable when low LSOCEN allows the Sequence Occurrence Counters to count up The command to enable is stored in the Sequencer by the CPU LDBO 7 LSEQDO 7 LSOCEN is an output of the Sequence Transition Memory Low Sequence Occurrence Counter Load when low LSOCLD allows the value stored in the Sequence Occurrence Memories to be loaded into the Sequence Occurrence Counters The command to load the Counters is stored in the Sequencer by the CPU LDBO 7 LSEQDO 7 LSOCLD is an output of the Sequence Transition Memory Low Sequence Store Enable an Analysis Controller input When low LSSE enables LBRO 7 to generate LSFLG LSSE also enables HWQ LSSE is and out put of the Sequence Transition Memory Low Sequence
132. LSEGD0 7 01 3 MOST SIGNIFICANT COUNTER ECL ECL U16 5 3 LOCCRY 40 3 ICs ON THIS SCHEMATIC REF DES HP PART NO MFG PART NO U16 80 1820 1831 U58 61 1816 1338 U63 64 1820 1173 U78 79 81 82 1820 1788 PARTS ON THIS SCHEMATIC Figure 8 14 Sequence Occurrence Counter Memory SAC 8 19 TO FROM CLOCK PROBE SEB PREPROCESSOR __ IMB TO FROM OTHER a ia 2 2 gt Q 2 2 W gt 2 O o a wi 5 4 lo _ Da I m 9 212205 2 OO FE x IM m luu elu gt lt DE e gt gt aor gt 33 9 oc gior Soo cor So oo PDC 5 5 o Qo oa ol 2 II UTE LSE TEST 8 HTR PREPROCESSOR CLOCK STROBES PROBE HMCLK STROBE INTERFACE BUS TEST 11 E e e e a m m lt l CONTROL ANALYSIS LINES CONTROLLER GENERATOR STROBES LLL C a gt p Rea HQWRITE HWQ CONTROL STATE TIME 7 COUNTER TEST 5 7 TRACE MEMORY TEST 6 BNC CONTROL CONTROL LDBO 7 N N 4 MAINFRAME INTERFACE TEST 1 Block Diagram COUNT STATUS Model 64621A Service
133. Las Positas Blvd Pleasanton CA 94566 Tel 415 460 0282 Hewlett Packard Co 3003 Scott Boulevard SANTA CLARA CA 95054 Tel 408 988 7000 Telex 910 338 0586 A C CM E Hewlett Packard Co 2150 W Hillcrest Dr THOUSAND OAKS CA 91320 805 373 7000 C CME Colorado Hewlett Packard Co 2945 Center Green Court South Suite A BOULDER CO 80301 Tel 303 938 3005 ACE Hewlett Packard Co 24 Inverness Place East ENGLEWOOD CO 80112 Tel 303 649 5000 A C CM EM Connecticut Hewlett Packard Co 500 Sylvan Av BRIDGEPORT CT 06606 Tel 203 371 6454 CE Hewlett Packard Co 47 Barnes Industrial Road South WALLINGFORD CT 06492 Tel 203 265 7801 A C CM E M Florida Hewlett Packard Co 2901 N W 62nd Street FORT LAUDERDALE FL 33309 Tel 305 973 2600 C E M P Hewlett Packard Co 6800 South Point Parkway Suite 301 JACKSONVILLE FL 32216 Tel 904 398 0663 Hewlett Packard Co 6177 Lake Ellenor Drive ORLANDO FL 32809 Tel 305 859 2900 Hewlett Packard 4700 Bayou Blvd Building 5 PENSACOLA FL 32503 Tel 904 476 8422 A C M Hewlett Packard Co 5550 W Idlewild 150 TAMPA FL 33614 Tel 813 884 3282 Georgia Hewlett Packard Co 2000 South Park Place ATLANTA GA 30339 Tel 404 955 1500 Telex 810 766 4890 A C CM E M P Hewlett Packard Co 3607 Parkway Lane Suite 300 NORCROSS GA 30092 Tel 404 448 1894 CEP Hawaii
134. List Cont d ECL ECL Description ECL TO TTL QUAD 7 BIN SYNCHRO POS SL REN SYNCHRO POK TTL t gt MUXR DAT OR QUAD 2 INP BIN SYNCHRO P OG EDGE TRTG BIN SYNCHRO POG EDGE TRIC ECL TO TTL QUAD 2 INP ECL TO TTL QUAD 2 TTL TO ECL QUAD INP 8 D TYPE POS EDGE TRIG PRI IN A SEL TTL LS 2 T0 1 LINE QUAD 2 MUXR DATA SEL TTL 0 171 QUAD gt EE TTE L 8 DeTYPE gt TT L 1024 1K TIL L 1024 IK STAT gt TTL 1 1024 1K STAT IC TTL L 1024 1K STAT IC XLTR ECL NETWORK RES 10 IC GATE TTL IC FF TTL gt FF TTL L gt TTL C DCDR TTI gt DEDR gt DCDR TTL POR SELLE CE 2 CNTR OTO TTL QUAD 470 0 OHM LS NAND QUAD 2 J K BAR PG J K BAR POS NAND QUAD 2 INP 2 70 8 1 INE 3 INP 3 TO B L INE 3 INP SE TRIG 1 L LS 3 TO 8 L NE BAR PO LS 2 CNTR TTL LS BIN SYNCHRO Pf TRIG IC TTL FF TTL IC XLIR IC XLTR ECL LS 2 TO A LINU DUAL 2 XNP S BAR PUSG EDGE TRIG eTOeTTL QUAD INP TO TTL QUAD 2 INP E TO TTL QUAD 2 INP NETWORK RES 10 SIP470 0 OHM 9 iC CUUNT NETWORK RE TQ INV TTL IC GATE IC MV TTL LS TC LCH gt LOH TTL TI oh BIT GRAY CURE 10 51 420 0 DHM X 9 LS 1 INP AND INY DUAL 2 INP 3 MONOSTEL RETRTG DUAL OCTL POS EDGE C DRVR TTL LS LINE DRYR DET
135. MACR goes low Mnemonic NOCSTB NSEQEV NSQRGS NTRIG PBDSTB PBOVRST PBPLS PBRSTB PBSRS Model 64621A Service Table 8 1 Mnemonics Cont d Description Negative Measurement Complete an output from the Analysis Controller When low NMC indicates to the CPU that the information requested by the user has been stored in the Trace Memories NMC also latches LMC into the Port Latch Negative Occurrence Counter Strobe NOCSTB is developed from the CPU s Address Bus and other control lines from the CPU NOCSTB is used to develop PSOCINC NOCSTB is used only during performance verification Negative Sequence Event when going from a high state to a low state NSEQEV indicates that either a Sequence Event has been found or the Sequence Occurrence Counters have been incremented NSEQEV can develop PSTIM a State Analyzer output Negative Sequence Register Strobe a differential signal PSQRGS developed in the Strobe Generator NSQRGS is used to latch information from the Sequence State Latch Counters into the Sequence Read Register The information in the Register is placed on the CPU Data Bus when LRSQRG goes low Negative Trigger an Analysis Controller output NTRIG goes from a high state to a low state each time the Trigger Event specified by the user oc curs NTRIG latches LTP into the Port Latch and LTRCP into the Trace Point Latch Positive Bus Data Strobe a differential signal NBDSTB deve
136. MENT 2 25 This instrument may be stored or shipped in environments within the following limits 10 Deg C to 75 Deg C bd Ce Rog deni 5 80 ALTITUOE 9255529 ak oe EIN ES 15000 50000 ft instrument should also be protected from temperature extremes which cause condensation within the instrument 2 26 PACKING 2 27 Tagging for Service If the instrument is to be shipped to a Hewlett Packard Sales Service Office for service or repair attach a tag showing owner with ad dress complete instrument repair number and a description of the service required 2 28 Original Packing Containers and materials identical to those used in factory packing are available through Hewlett Packard Offices Mark the container FRAGILE to ensure careful handling In any correspondence refer to the instrument by model number and complete repair number 2 29 Other Packing The following general instructions should be used for repacking with commercially available materials a Wrap instrument in heavy plastic or paper If shipping to Hewlett Packard Office or Service Center attach a tag indicating type of service required return address model number and complete repair number b Use a strong shipping container A double wall carton made of 350 pound test material is adequate Use a layer of shock absorbing material 70 to 100 mm 3 to
137. MORIES PSOCINC BUS SEQUENCE STATE BUS SEQUENCE STATE STATE SEQUENCE RECOGNITION PATTERN SEQUENCE DATA FROM PROBE SYNDO 19 TRIGGER TATE COUNTER MEMORY yee SEITE SEQUENCE TRANSITION LBSPO 3 COUNTER SEQUENCE MEMORIES CLK SEQUENCE STATE PATTERN CLK P N BSRS SEQUENCE PATTERNS FROM OTHER ACQ BOARDS HPLS Figure 8 7 Sequencer Block Diagram sac 8 18 LOAD ENABLE 550 3 LSOCLD LSOCEN LOVEN LOVRST LSOCE LSCE LSME LSSE LSTE LSSQ HSTR TSSO 7 TO OVERVIEW ENABLE ANALYSIS CONTROLLER FUNCTIONS CONTROL ANALYSIS CONTROLLER FUNCTIONS TO TRACE MEMORY Model 64621A Service 8 95 ANALYSIS CONTROLLER 8 96 Description 8 97 The Analysis Controller Ul is a custom designed IC which controls the master enable count store and trigger functions of the State Analysis Subsystem Figure 8 8 is a summary of the Analysis Controller 8 98 The Analysis Controller decodes inputs from the Resource Patterns the Sequencer and the Inter Module Bus IMB and outputs control signals to all cards in the State Analysis Subsystem and to other Analysis Subsystems over the IMB The Analysis Controller must be programmed loaded before each execution Electrically the inputs and outputs are at ECL levels with the exception of the following TTL signals NTR NMC LLOAD SERDATA PLCLK and LRUN Internally the part is emitter functional logic EFL similar in design to ECL LOAD RESOURCE GATING COUNT STATES TIME EVENTS
138. Manufacturers Codes Manufacturer Name FUJITSU LTD HITACHT ANY SATISFACTORY SUPPLIER N BRADLEY CO XAS INSTR INC SEMICOND CMPNT DIV SPECTROL ELECTRONICS CORP MOTOROLA SEMICONDUCTOR PRODUCTS FAIRCHILD MICONDUCTOR DIV BERNE INC MEPCO ZELECTRA CORP EMCON DIV ITW CORNING GLASS WORKS BRADFORD EK CORP SEMICON amp MC DIV SEMICONDUCTOR CORP RNING GLASS WORKS WILMINGTON LETT PACKARD CO CORPORATE RCA CORP SOLID STATE DIV ADVANCED MICRO DEVICES INC STETTNE USH INC CTRIC co MOTIVE CORP TRW INC PHILADELPHIA DIV Address TOKYO TOKYO MILWAUKEE DALLAS CITY OF IND MOUNTAIN VIEW BERNE MINERAL WELLS SAN DIEGO BRADF ORD SLATERSVILI E SANTA CLARA WILMINGTON PALO ALTO SOMERVILLE SUNNY VALE CAZENOVIA NORTH ADAMS FLORENCE PHILADELPHIA See introduction to this section for ordering information 52204 75222 91745 85008 94042 46711 76057 92129 16701 07 6 1 28401 94304 94096 150 01247 06226 19108 Model 64621A Manual Backdating SECTION VII MANUAL BACKDATING 7 1 INTRODUCTION 7 2 This section contains information required to backdate or update this manual for a specific repair number prefix 7 3 MANUAL CHANGES 7 4 This manual applies directly to the instrument having the repair number prefix shown on the manual title page If the repair prefix is not the same as the one on the title page find your repair number prefix in Table 7 1 and make
139. P19 Qual Stop TP19 Clock U66 pin 13 Ground GND TP Model 64621A Performance Verification Test 6 Loop G VH 62A5 030C 11 H896 13 HAHA 5HC6 564A Cocca 1 pp ou C830 7391 13 21 H173 34PU tot P Po PP FA68 2 11 2UUA 2 13 C830 2 14 FH56 1391 92 18 62 5 TOTLZ 768 5525275 NO SO NO NO NO NO NO NO NO NO lt lt lt lt lt c C lt c q n 87P8 4010 7702 0818 H473 8 8 62H4 1444 U 93 11 A2HC U 93 13 FA68 U 93 15 U 93 18 6245 TOTLZ 768 U 93 20 736C U 93 21 995U w 1 ON NV FWD P sac 4 51 Model 64621A Performance Verification Board 64621 66503 Test 11 Loop H 7339 MODE EDGES THRESHOLDS CONNECTIONS Normal CLOCK Positive Data High ST SP Start TP19 START Positive Data Low Qual Stop TP19 STOP Negative Clock Clock U99 pin 3 ST SP QL TIL Ground GND TP NOTE Remove the clock pod connector from J3 levels except where noted U 1 17 low U 65 3 high ECL U120 h 733 U 1 35 high U 65 4 high U120 5 low U120 6 low U 26 1 OOUP U 96 4 73F7 U120 7 733H U 26 2 7338 U 96 5 OOUP U120 11 high U 26 3 7333 U 96 6 7339 U 26 4 733H TOTLZ 24 U123 1 high 26 5 7331 U123 2 low U 26 6 7329 U 97 2 3FU9 U123 3 high U 26 7 7319 U 97 h high U123 6 low 26 8 7379 U 97 5 high U12
140. Point Counter counts the number of states to be stored after trace point then sets the Measurement Complete NMC Latch which disables the Write Qualify Gating forces HWQ to go low The 58 bit shift register uses 10 bits Initialize Poststore to initialize the two latches and the PostTrace Point Counter NOTE Writing to the Overview Event Memory is not controlled by the Write Qualification function Overview writing is controlled directly by the Sequencer and Analyzer Enable 8 109 produces a pulse each time the trigger event occurs and can be used to trigger external test equipment NMC can be routed to external test equipment and also serve as an overflow for the 58 bit shift register The overflow function is used during performance verification to test the loading of the Analysis Controller Data is input on bit 0 of the data bus LDBO and clocked by Positive Write Analysis Controller PWAC Low Load LLD must be low to clock in data 8 110 Analyzer Enable This is the master enable for the entire State Analyzer Master Enable LME can be set low by Run LRUN which is a keyboard command to begin execution or it can be received from the IMB When LME is strobed by State Recognition Strobe HSRS it latches Analyzer Enable 1 HAE1 When 1 is strobed by Pipeline Strobe HPLS it produces Positive Pipeline Strobe PPLS which is used to strobe the Sequencer the Data Pipeline Registers and Analyzer Enable 2 HAE2
141. RE WARNINGS Warnings such as the example below precede potentially dangerous procedures throughout this manual Instructions contained in the warnings must be followed Dangerous voltages capable of causing death are present in this instrument Use extreme caution when handling testing and adjusting Model 64621A Table of Contents Table of Contents Paragraph Page Section General Information 1 1 INTRODUCTION 1 1 1 4 SPECIFICATIONS 1 1 1 6 INSTRUMENTS COVERED BY THIS MANUAL 1 3 1 11 RECOMMENDED TEST EQUIPMENT 1 4 1 13 DESCRIPTION 2 2245 HERR er reg oie de wwii 1 4 Section Il Installation 2 1 INTRODUCTION 4e ana 2 1 2 3 INITIAL INSPECTION ha e RI RR en re tegen a 2 1 2 5 PREPARATION FOR USB il on on VU W in 2 1 2 7 INSTALLATION INSTRUCTIONS 2 1 2 8 MAINFRAME CONFIGURATION 2 1 2 13 CARDCAGE SLOT IDENTIFICATION 2 1 2 19 SYNCHRONOUS EXPANSION BUS SEB 2 2 2 21 INTER MODULE BUS IMB 2 2 2 23 STORAGE AND SHIPMENT 2 5 9 04 ENVIRONMENT qe She EE VE 2 5 2 96 PACKING Lowe hw ee e date ede s
142. Resource Gating from the Sequencer are similar to the inputs from the IMB Receiver It is the 58 bit shift register which determines which circuitry will actively control the State Analyzer during a particular run The Sequencer can perform a master enable function by setting Sequence Master Enable LSME low The Sequencer alone controls Overview Enable LOVEN and Overview Reset LOVRST SAC 8 21 Model 64621A Service 8 114 Timing of Analysis Controller 8 115 The Strobe Generator controls timing of the Analysis Controller by use of State Recognition Strobe HSRS Pipeline Strobe HPLS and Write Strobe HWRT HSRS HPLS nS 95 nS 135 nS 180 nS __ 21 HWRT _ 0 Prior to Resource Allocation the Resource Patterns Analyzer Enable and IMB are clocked by HSRS After Resource Allocation HPLS clocks the Sequencer and all other inputs so that Resource Gating is valid Finally HWRT clocks out write signals and HWRT going low clocks the IMB Drive Internal delays are in the several nanosecond range due to the EFL logic design SAC 8 22 RESOURCE ALLOCATION Model 64621A Service WRITE ALLOCATION QUAL TERM 2 3 6 7 OVERVIEW COUNT OVERVIEW COUNT RESOURCE RESOURCE GATING QUALIFICATION u QUAL HOCQ TRACE COUNT uil TRACE COUNT RESOURCE STORAGE 5 STORAGE RESOURCE TRIGGER 1
143. Section Vil Manual Backdating 7 1 INTRODUCTION RISO RIEN SSA 1 7 3 MANUAL CHANGES idea S ROUES QE TE Section VIII Service 8 1 INTRODUCTION 8 9 STATE ANALYZER SUBSYSTEM BLOCK DIAGRAM o du os S bem Uns MX 8 13 DESCRIPTION rr is gt 8 34 CONTROL BOARD BLOCK DIAGRAM TREE 8 8 36 CONTROL BOARD BLOCK DIAGRAM THEORY roe eade 8 8 46 DETAILED CIRCUIT THEORY 8 1 8 47 CLOCK TERM GENERATOR 8 1 8 58 STROBE GENERATOR 8 1 8 76 SEQUENCER EDEN 8 15 8 95 ANALYSIS CONTROLLER 8 19 8 116 STATE TIME COUNTER do oon ra bur no 8 130 MNEMONICS err eer Sn 270 Model 64621A List of Figures and Tables List of Figures and Tables Figure or Table Page Section General Information Figure 1 1 Model 64621A State Analysis Control 1 0 Table 1 1 Specifications ORA e CR 6 eee bel Table 1 2 Supplemental Charactenistiesi Table 1 3 Recommended Test Equipment STATA ET S Section Il Installation Figure
144. State Test Board in Slot 2 Pass bested 1 Failed 0 Slot 2 State Control and Clock Test 5 State count 987 6543210987 6545F10 Reset to 0 00000000000000000000 1 Error Count enable Pass 10 10 count Pass 20 bit count Pass Output test 0 s 00000000000000000000 175 00000000000000000000 Figure 4 17 State Count SAC 4 25 Model 64621A Performance Verification 4 56 Figure 4 17 Interpretation Reset to 0 00000000000000000000 twenty output bits of U112 read from memory 19 b16 U93 15 12 072 11 b8 092 bh 071 bO 091 Count enable Pass test of HCOUNTQUAL 10 10 count Pass two ten bit counter mode selected by HCTST 20 bit count Pass 20 bit counter mode Output test 076 00000000000000000000 175 00000000000000000000 same outputs as Reset to 0 above 4 57 Loop Signature Path U69 U87 088 U104 0105 0106 memory RAM s translators U112 U1 U120 U100 U102 SAC 4 26 Model 64621A Performance Verification 4 58 TEST 6 TRACE MEMORY LOOPS F amp G 4 59 Purpose test Trace Counter Status Memory Tracepoint Register Wrap bit and Post Trace Point Counter which is a circuit internal to the Analysis Controller 4 60 How The Memory is 32 bits wide 20 bits are Counter data 8 bits are Sequence State data and the remaining 4 bits are for flags In addition to the RAMs the Memory contains an Address Counter MAC and an Address Selector M
145. State Time Counter PLATCH When HTIMS goes from a low to a high the in formation inside the Trace State Time Counter is latched into its output latches High Trigger HTR is one of the bidirectional signals that make up the Intermodule Bus IMB HTR is used to indicate to other modules connected to the IMB that a trigger event has been found Being bidirectional the State Analyzer can tell other modules that it has found a trigger or ob serve that another module has found a trigger event HTR is wire ORed with other modules High Write Qualify generated by the Analysis Controller HWQ is used to enable HBQWRT and stops the Trace State Time Counter when the output of the Counter is being stored in the Trace Counter Status Memories SAC 8 29 Model 64621A Service Mnemonic HWRT L25MHZ LAO 13 0 13 LBCLR LBMACS LBOVEN LBRPO 7 LBSPO 3 LCLKO 7 LCLR LDO 12 SAC 8 30 Table 8 1 Mnemonics Cont d Description High Write developed in the Strobe Generator HWRT is used to transfer storage commands from the inputs to the outputs of the Analysis Controller at the correct time in the data acquisition cycle and to provide timing for other write signals Low 25 Megahertz a high accuracy crystal controlled clock originating in the Mainframe L25MHZ is used to clock the Trace State Time Counter when in the time mode for measuring time between states Low Address 0 13 a 16 bit addres
146. Store Qualify an Analysis Controller input When low LSSQ qualifies LBRPO 7 When qualified LBRPO 7 generates LSFLG LSSQ also qualifies HWQ LSSQ is an output of the Sequence Transition Memory Low State LSTATE controls the two modes of the Trace State Time Counter When LSTATE is low the Counter counts the number of states be tween two stored states PINC is used to increment the counter in the state mode When LSTATE is high the Counter counts time using L25MHZ as a reference Low Strobe a signal orginating in the Mainframe When low and the CPU is in the write mode LWRT low LSTB indicates the Data Bus has valid Mnemonic LSTE LSTM LTCLK Model 64621A Service Table 8 1 Mnemonics Cont d Description information on it When low and in the read mode LSTB indicates that the CPU is not driving the Data Bus and the device addressed may now drive it Low Sequence Trigger Enable a Sequencer output used by the Analysis Controller When LSTE is low the Analysis Controller enables NTRIG Low Start Memory a signal originating in the Mainframe When low LSTM indicates that the information on the CPU s Address Bus is valid Low Transfer Clock differential clock HTCLK used the Preprocessor When LTCLK goes from a high state to a low state data is transferred between the State Analyzer and the Preprocessor LTCSMS0 3 Low Trace Count Status Memory Select 0 3 LTCSMS is used to enable chip
147. TE ANALYSIS CONTROL BOARD HOVS 5 64621 66503 STROBE GENERATOR 5 PBSRS Ea 5 u 6 HSAS Di S 5 M PMACRS 2 9 o H 3 TTL ECL 2 i 3 25 ICs ON THIS SCHEMATIC 5 12 DES HP PART MFG PART 13 25 101 121 526 3 ECL 2 ui 5 3 ione O 3 U5 24 45 1820 1400 10104 R36 2K TTL ECL 3 amp U6 19 20 44 1820 0802 10102 gt 5 MM lt U8 1820 0269 7403 o 1 PSORGS OE U16 1820 1831 10103 i OL U21 22 1820 1944 10130 U23 1820 0817 10131 73 25 U43 1820 0806 10109 047 50 1820 0809 10115 052 85 1820 1173 10124 150808 5 g 065 1820 1052 10125 0117 1820 1423 7415123 PARTS ON THIS SCHEMATIC C5 10 17 31 33 62 R4 5 7 18 36 52 TP1 2 6 9 13 15 4 13 LSCLK G 9 U2 4 6 8 9 12 13 16 19 24 31 35 43 52 57 65 85 117 3 25 11 249 lio o Lsv ly P 0 U34 e TP15 ECL seit 5 n d 100MS ves ls POWER SUPPLY gt tur La eevee CONFIGURATION Or 5 5 052 65 85 id uo o af RR 3 0 USI 9 NC D ow M 13 7 08 ow R18 zi 10 e 2 a C10 Ti U46 m 470 LT ECL 047 Figure 8 12 Strobe Generator SAC 8 45 Model 64621A Service TO FROM IMB CLOCK PROBE SEB TO FROM OTHER PREPROCESSOR BOARDS Cesa LG
148. U ECL U 3 U 3 U 24 5 high ECL U 38 17 6546 ECL 10 high U 38 18 99F7 ECL U 38 19 357P U 25 13 508P U 38 21 4778 ECL U 52 1 high ECL U 25 15 6302 U 38 23 15 ECL 52 2 73AU U 52 3 low ECL U 52 4 high ECL 26 19 8U24 U 40 2 PPHP ECL U 52 12 ECL TOTLZ 0 U 40 4 5 1 U 52 15 high ECL U 40 6 5 ECL U 40 7 4871 U 36 2 4778 ECL U 40 8 FFU9 ECL U 54 2 048C U 36 4 PH15 ECL U 40 9 62FC ECL U 54 3 8 9 U 36 6 A59P ECL U 40 10 HO2H ECL U 54 4 1871 U 36 7 4871 U 40 11 762F ECL U 54 5 A59P U 36 8 9UOH ECL U 40 13 Ch27 ECL U 54 6 357P U 36 9 62FC ECL U 40 14 03P7 ECL U 54 7 99FT U 36 10 HO2H ECL U 40 15 784A U 54 8 6302 U 36 11 762F ECL U 40 16 F61U ECL U 54 9 508P U 36 13 Ch27 ECL U 40 17 6546 U 54 12 2FF1 U 36 14 03P7 ECL U 40 18 P14U ECL U 36 15 78AA ECL U 40 19 O48C ECL U 36 16 165A ECL U 40 21 8HF9 ECL U 55 2 048 U 36 17 65 6 ECL U 40 23 UH9h ECL U 55 3 8PC9 U 36 18 8PC9 55 4 4871 U 36 19 O48C ECL U 55 5 A59P U 36 21 900 ECL U 42 2 TFCH ECL U 55 6 357P U 36 23 PCHO ECL U 42 4 9946 ECL U 55 7 99 U 42 6 508P ECL U 55 8 6302 U 42 7 6302 ECL U 55 9 508P U 38 2 4778 ECL U 42 8 FFU9 ECL U 55 12 9153 U 38 4 PH15 ECL U 42 9 62FC ECL U 38 6 508P ECL U 42 10 HO2H ECL U 38 7 6302 ECL U 42 11 762F ECL U 58 1 1 85 U 38 8 9UOH ECL U 42 13 Ch27 ECL U 58 2 41262 ECL U 38 9 62FC ECL U 42 14 03P7 ECL 58 4 4871
149. U121 3 10 0121 16 6412 0122 16 10 0121 4 6412 0121 17 A10C 0122 18 FF34 U121 5 1U1A QUAL U121 18 FF34 U121 6 8PU8 U121 19 0000 U125 1 FF68 U121 7 F789 TOTLZ OFLO U125 2 0121 8 1108 0125 3 1525 0121 9 8007 U122 1 6 6 U122 2 HATA SAC 4 50 Board 64621 66503 MODE EDGES Normal Clock Positive Start Positive So FS Se Stop THRESHOLDS Data High Data Low Clock TIL ST SP QL TIL levels are TIL except where noted 87P8 4010 7702 0818 H473 8 8 70 62Hh TO 52C6 70 11 8h8U 70 13 966c 70 15 C1l9U 70 18 564A 70 20 736C 70 21 9950 10 70 TO TO 70 10 WON ON rS P 71 9 H62P 71 11 23 71 13 1444 71 15 A2HC 71 18 34PU 72 9 21 72 11 H173 72 13 H62P 72 15 23 72 18 6245 TOTLZ 768 3 9 low 3 11 3254 3 12 0 19 3 13 61P7 3 15 high 73 18 62 5 TOTLZ 768 U 87 1 0000 TOTLZ OFLO U 87 2 6ACH U 87 3 62A5 TOTLZ 640 U 87 4 0818 87 5 15 7 U 87 6 62A5 2 320 U 87 7 7702 U 87 9 oko U 87 10 62A5 TOTLZ 160 U 87 11 22P5 U 87 12 87P8 U 87 13 62A5 TOTLZ 80 U 97 14 PS4H U 88 1 0000 TOTLZ 0FLO 88 2 UCUA U 88 3 6245 TOTLZ 40 88 h 9950 U 88 5 c H6 U 88 6 6245 TOTLZ 20 U 88 7 H473 U 88 9 8 84 0 88 10 6245 TOTLZ 10 U 88 11 21 U 88 12 62H4 U 88 13 6245 TOTLZ 5 U 88 14 0071 CONNECTIONS ST SP Start T
150. V SCOPE CHAN B 225 5 25nS ov td SCOPE CHAN A 50 5 20nS Figure 4 9 BNC Port I Waveform h Verify that Port 1 output for Trigger Events has a time delay td of 2 1 i j 25 nS 25 nS a pulse width tw of 50 nS 20 nS measured at TIL evels 1 4 V threshold Press halt Press sequence term number 1 find any state enable Press sequence term number 2 find state disable Press assert bnc port 1 on sequence enable and disable Press trigger on nothing Press execute repetitively Press trace specification Using the Pulse Generator set up of previous measurement measure td and tw with the Oscilloscope 4 2 Verify that Port 1 output for Sequence Events has time delay td of 00 nS 25 nS and a pulse width tw of 50 nS 20 nS measured at TTL levels 1 i V threshold Procedure for Hilt BNC Port 2 SAC 4 14 a Move channel A of the Oscilloscope to Port 2 Adjust Pulse Generator for square wave of 50 Hz with amplitude from 0 to 2 8 V Clock Threshold is automatically set for TTL 1 4 V Press halt Press trigger any state Press trigger position is end of trace Model 64621A Performance Verification f Press assert bnc port 2 on measurement complete E Press execute repetitively h Press trace specification i Set Oscilloscope to measure td Turn Intensity up to see channel A 2 8V SCOPE
151. WQ STATE TIME COUNTER TEST 5 7 CONTROL LAB4 11 x LDB0 7 o N S O IMB TO FROM OTHER yor BOARDS 5 PDC LME LTE LSE TEST 8 HTR COUNT STATUS MEMORY TEST 6 MAINFRAME INTERFACE TEST 1 Block Diagram Model 64621A Service 49 15 T4 T2 T1 64621 66501 m q R2 9 STATE CONTROL BOARD g rR3 k REVA _ ulli CLOCK POD 10 U 11 FS1 FS FS2 ua Us U8 u7 ea 5 9 Vini id 010 11 12 i 1 1 5 8 dip p R20 C68 Ui 012 U13 R9 o o 9 8 5 R21 v ee mo 1 P j I R22 11 o n 2 R27 me t 2 al th p f 898 e 1 i R30 U16 Ui7 U18 vis 11 u20 021 G 922 u23 1 924 8 0 T 5 5 5 u29 lt T D I ail c14 u31 032 U33 U34 TP13 U35 U27 BL R33 c20 lp CELL eee sedo TA 2 i U48 949 051 8 E 8 9 U53 Us4 55 I 9 U43 U44 045 U47 uso 52 9 936 938 040 042 L
152. When HAE2 is strobed by Write HWRT it produces High Bus Overview Write Strobe HBOWRT and Positive Sequence Occurence Counter Increment PSOCINC HBOWRT is used to write to the Overview Event Memories on the 20 Channel Acquisition Board 8 111 Another source of master enable is the Sequencer When the Sequencer finds all of the required states in the order specified it can drive Sequence Master Enable LSME low LSME then enables the trigger and store functions in the Analysis Controller LSME can also be programmed to drive LME on the IMB The 58 bit shift register uses 4 bits to specify whether or not the IMB or Sequencer will control Master Enable 8 112 IMB Receive and Drive Master Enable Trigger and Store functions can be received by the Analysis Controller from the IMB the Analysis Controller can transmit drive Delayed Clock PDC as well as Master Enable LME Trigger HTR Trigger Enable LTE and Store Enable LSE When the Analysis Controller is receiving IMB signals the signals are latched with the State Recognition Strobe HSRS and applied to the Resource Gating after Pipeline Strobe HPLS When the Analysis Controller is driving the IMB they are strobed out by Write HWRT The 58 bit shift register is responsible for determining which IMB signals are active 8 113 Sequencer The Sequencer is an integral part of the Control Board and should be considered an extension of the Analysis Controller The inputs to the
153. Y 12205 Tel 518 458 1550 Hewlett Packard Co 9600 Main Street CLARENCE NY 14031 Tel 716 759 8621 CE Hewlett Packard Co 200 Cross Keys Office Park FAIRPORT NY 14450 Tel 716 223 9950 A C CM E M Hewlett Packard Co 7641 Henry Clay Blvd LIVERPOOL NY 13088 Tel 315 451 1820 A C CM E M Hewlett Packard Co No 1 Pennsylvania Plaza 55th Floor 34th Street amp 8th Avenue MANHATTAN NY 10119 Tel 212 971 0800 CM Hewlett Packard Co 15 Myers Corner Rd Hollowbrook Park Suite 20 WAPPINGER FALLS NY 12590 CME Hewlett Packard Co 250 Westchester Avenue WHITE PLAINS NY 10604 Tel 914 684 6100 C CM E Hewlett Packard Co 3 Crossways Park West WOODBURY NY 11797 Tel 516 682 7800 A C CM E M 2 SALES amp SUPPORT OFFICES Arranged alphabetically by country UNITED STATES Cont d North Carolina Hewlett Packard Co 305 Gregson Dr CARY NC 27511 Tel 919 467 6600 C CM E M P Hewlett Packard Co 9600 H Southern Pine Blvd CHARLOTTE NC 28210 Tel 704 527 8780 c Hewlett Packard Co 5605 Roanne Way GREENSBORO NC 27420 Tel 919 852 1800 A C CM E M P Ohio Hewlett Packard Co 2717 S Arlington Road AKRON OH 44312 Tel 216 644 2270 CE Hewlett Packard Co 23200 Chagrin Blvd 100 BEACHWOOD OH 44122 Tel 216 292 4677 CP Hewlett Packard Co 9920 Carver Road CINCINNATI OH 45242 Tel 513 891 9870 CM Hewlett Packard Co 16500 Sprague R
154. Z 6510 U 94 7 6872 ECL U 87 13 low U 92 5 high 0 94 11 028 U 87 14 low U 92 6 high U 94 15 8173 U 92 high U 88 1 U16U U 92 9 66P4 U100 1 67UC U 88 2 low U 92 10 A483 U100 2 56U3 U 88 3 low U 92 11 U4UP 0100 3 0 1 0 88 4 high U 92 12 8 36 0100 h 67F1 U 88 5 low U 92 13 1075 0100 5 67F1 U 88 6 low 92 14 FCCP U100 10 830A U 88 high U 92 15 1662 U 88 9 high U 92 16 905 0102 1 67UC U 88 10 low U 92 18 U35F 0102 2 5603 0 88 11 low U 92 20 10160 U102 3 0 1 U 88 12 high TOTLZ 19 0102 h 5038 U 88 13 low U 92 21 high U102 5 96AP U 88 14 low 0102 6 62 0 93 1 high 0102 7 1023 U 91 1 high U 93 2 high 0102 11 U 91 2 high U 93 3 high U 91 3 high U 93 4 U16U 0104 1 1023 0 91 4 U16U TOTLZ 6510 0104 2 1160 TOTLZ 6510 U 93 5 high TOTLZ 19 U 91 5 high U 93 6 high 0104 11 low U 91 6 high U 93 7 high U104 12 low U 91 7 high U 93 9 796A 0105 13 5 U 91 9 5 U 93 10 A483 0104 14 0 91 10 A483 U 93 11 6872 U104 15 low U 93 12 8036 SAC 4 44 Model 64621A Performance Verification Board 64621 66503 Test 5 Loop E VH U16U MODE EDGES THRESHOLDS CONNECTIONS Normal Clock Positive Data High ST SP Start TP19 Start Positive Data Low Qual Stop TP19 Sa Stop Negative Clock TIL Clock U99 pin 3 ST SP QL Ground GND TP levels are TTL except where noted U105 1 1023 0109 3 6536 TOTL
155. Z 6531 U105 2 1161 U109 7 9115 ECL U112 32 81F1 ECL U105 10 low U109 11 6960 ECL 0112 36 1075 ECL U105 11 low 0109 15 POUH ECL U112 37 16C2 ECL U105 12 low U112 38 7020 ECL U105 13 low 0110 4 66P4 U112 39 7190 ECL U105 14 low U110 5 U4UP U112 40 hFAU ECL 0110 12 1075 0106 9 THC8 0110 13 1662 0120 11 0106 10 POUS 0120 16 0106 11 U35F U110 3 66P4 1120 17 3021 0106 12 U110 7 U4UP ECL 0120 18 60FU 0106 13 0110 11 1075 ECL 0120 19 low 0106 14 8PP4 0110 15 1662 ECL 0121 1 67F1 0107 2 6085 1112 8 low U121 2 60FU U107 3 6085 0112 9 0121 3 3021 0107 4 F996 U121 4 717H 0107 6 8PPY U112 2 CPC6 ECL U121 5 0107 10 9HUH 0112 3 796 U121 6 P7U2 0107 12 F996 U112 4 6872 ECL U121 7 3797 0107 13 79H2 U112 5 028 ECL U121 8 0107 14 T9H2 0112 6 8173 U121 9 0049 U112 14 354P ECL 0121 11 0049 U108 4 354P 0112 15 99U4 ECL 0121 12 U108 5 990 0112 16 2HP6 0121 13 3797 0108 12 2 6 0112 17 1 31 0121 14 P7U2 0108 13 1 31 1112 18 6536 0121 15 0112 19 9115 0121 16 717H U108 3 354P ECL U112 20 6960 ECL 0121 17 3021 U108 T 9900 ECL 0112 21 POUH ECL 0121 18 60FU U108 11 2HP6 ECL U112 22 66P4 ECL U121 19 0000 U108 15 1 31 0112 23 UMUP ECL TOTLZ 34488 U112 25 0000 ECL U109 h 6536 TOTLZ 19 U125 1 F996 U109 5 9015 0112 26 0000 0125 2 96AP 0109 12 6960 TOTLZ 6550 U125 3 3809 01
156. a failure occurred refer to the paragraph on Troubleshooting in Section IV of this manual This manual covers only the tests for the Control Board 4 11 MANUAL TESTS 4 12 TEST 1 INPUT THRESHOLD and MINIMUM SWING Refer to the Model 64635A and 64636A Service Manuals for the procedure 4 13 TEST 2 INPUT THRESHOLD RANGE Refer to the Model 64635A and 64636A Service Manuals for the procedure 4 14 TEST 3 MIN CLOCK WIDTH amp QUAL SETUP amp HOLD TIME Specifications Clock Width 20 nS at threshold level Qualifier Setup Time 20 nS Qualifier Hold Time 0 nS Description This Test verifies that the clock input circuitry functions properly with an input signal having a minimum clock width Equipment Pulse HP8013B HP1722B HP1743A SAC 4 2 Model 64621A Performance Verification PULSE STATE ANALYZER GENERATOR CLOCK PROBE TEST CONNECTOR SEE FIGURE 4 4 Figure 4 1 Clock Width Test Configuration e 200ns _ 2 8V ov cal le 20nS Figure 4 2 Clock Width Rising Fdge Waveform Procedure Need Control Board and at least one Acquisition Board with General Purpose Probes a Setup Pulse Generator for waveform in Figure 4 2 b Press meas sys only if more than one measurement system is installed c Press state x d Press format specification e Press clock is rising edge channel 0 and low level channel 1
157. ackard Model 1743A with probes 5 8 ACCESSORIES 1 Hewlett Packard Model 64000 series Mainframe with extender board and SEB Extender Cable 5 9 PROCEDURE 5 10 This procedure assumes that all other modules of this system are working prop erly and are calibrated and meet or exceed their respective specifications NOTE Installation and removal of P C Boards must be done with the AC Power for the Mainframe turned off 5 11 STROBE GENERATOR ADJUSTMENTS TEST 9 a Place the State Analysis Control Board on an extender board The SEB Bus Cable must be connected to the Acquisition Boards Use the extreme ends of the cable to avoid reflections Select opt test press RETURN The display will indicate the option modules present and the card slot number in which they are located SAC 5 1 Model 64621A Adjustments c Press slot number RETURN Slot number is a number from 0 to 9 equal to the location of the State Analysis Control Board d Press run slot number test 9 repeat RETURN CRT should now display Test 9 Strobe Generator Calibration NOTE All of the following Strobe Generator measurements must be made within 0 5 ns of the indicated value All transitions are measured at the 50 level ECL Level e Connect channel A of the scope to TP2 State Recognition Strobe and trig ger on channel A Connect channel B to TP3 Pipeline Strobe Using adjust ment T1 R8 adjust
158. ackard Office If the shipping container is damaged or if the cushioning material shows signs of stress notify the carrier as well as the Hewlett Packard Office Keep the shipping materials for carrier s inspection The HP office will arrange for repair or replacement at HP option without waiting for claim settlement 2 5 PREPARATION FOR USE 2 6 There are no specific preparation for use procedures except the actual instal lation of the boards in the Mainframe cardcage 2 7 INSTALLATION INSTRUCTIONS 2 8 MAINFRAME CONFIGURATION 2 9 Depending on the number of channels required the State Analysis Subsystem will use two or more card slots of the Mainframe cardcage 2 10 Due to the way the Mainframe CPU identifies the boards installed in the cardcage the State Control Board 64621A should be installed in the lowest num bered card slot available 2 11 The 64622A 40 Channel State Data Acquisition Boards if any must be in stalled in the next higher numbered card slots See Figures 2 1 and 2 2 2 12 The 64623A 20 Channel State Data Acquisition Board if any is installed in the next higher numbered slot See Figures 2 1 and 2 2 2 13 CARDCAGE SLOT IDENTIFICATION 2 14 When the CPU finds a State Analysis Control Board in the cardcage the CPU then expects to find either a 20 Channel Acquisition Board or a 40 Channel Acquisition Board in the next higher numbered slot 2 15 The concept of the Control Board being in a lower
159. al To keep this manual as current as possible Hewlett Packard recommends that you periodically request the latest Manual Changes supplement The supplement for this manual is identified with the manual print date and part number both of which appear on the manual title page Complimentary copies of the supplement are available from Hewlett Packard 1 10 For information concerning a repair number prefix that is not listed on the title page or in the Manual Changes supplement contact your nearest Hewlett Packard Office SAC 1 3 Model 64621A General Information 1 11 RECOMMENDED TEST EQUIPMENT 1 12 Equipment required to maintain the Model 64621A is listed in Table 1 3 Other equipment may be substituted if it meets or exceeds the critical specifica tions listed in the table Table 1 3 Recommended Test Equipment 4 1 2 Digit Multimeter accurate to 1 mV Hewlett Packard Model 3466A equivalent Hewlett Packard Model 5005A Signature Multimeter Dual Channel 100 MHz Oscilloscope with delta time measurement accurate to 0 5 ns Hewlett Packard Model 1743A with probes or equivalent 1 13 DESCRIPTION 1 14 The State Analyzer is used to monitor information flow in the data domain The information may be a software program the actions of a hardware state machine or random logic signals 1 15 The State Analyzer consists of one Model 64621A State Analysis Control Board and from one to three State Data Acquisition
160. are and firmware designated by HP for use with an instrument will ex ecute its programming instructions when properly installed on that instrument HP does not war rant that the operation of the instrument or software or firmware will be uninterrupted or error free LIMITATION OF WARRANTY The foregoing warranty shall not apply to defects resulting from improper or inadequate main tenance by Buyer Buyer supplied software or interfacing unauthorized modification or misuse operation outside of the environment specifications for the product or improper site preparation or maintenance NO OTHER WARRANTY IS EXPRESSED OR IMPLIED HP SPECIFICALLY DISCLAIMS THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE EXCLUSIVE REMEDIES THE REMEDIES PROVIDED HEREIN ARE BUYER S SOLE AND EXCLUSIVE REMEDIES HP SHALL NOT BE LIABLE FOR ANY DIRECT INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES WHETHER BASED ON CONTRACT TORT OR ANY OTHER LEGAL THEORY ASSISTANCE Product maintenance agreements and other customer assistance agreements are available for Hewlett Packard products For any assistance contact your nearest Hewlett Packard Sales and Service Office ISSUE A SERVICE MANUAL CHANGES MANUAL IDENTIFICATION Model Number 64621A Date Printed June 1983 Part Number 64621 90903 This supplement contains important information for correcting manual errors and for adapting the manual to instruments contain
161. ation of outlines together with one or more qualifying symbols and the representation of input and output lines INPUTS OUTPUTS Some have a common Control Block with an array of elements CHIP CONTROL FUNCTION BLOCK CTR DIV 16 COMMON si z OUTPUT DEPENDENCY NOTATION COMMON CONTROL INPUTS I 2 3 5 6 1 C7 ARRAY gt 2 4 5 6 1 C7 LEAST ELEMENTS SIGNIFICANT ELEMENT kiki eee MOST SIGNIFICANT ELEMENT INPUTS 3 OUTPUTS CONTROL BLOCK All inputs and dependency notation affect the array elements directly Common outputs are located in the control block Control blocks may be above or below the array elements ARRAY ELEMENTS All array elements are controlled by the control block as a function of the dependency notation Any array element is independent ofall other array elements Unless indicated the least significant element is always closest to the control block The array elements are arranged by binary weight The weights are indicated by powers of 2 shown in D US 04 08 83 d Outputs of array elements are located in the corresponding array element with the least significant bit closest to the control block CHIP FUNCTION The labels for chip functions are defined i e CTR counter MUX multiplexer DEPENDENCY NOTATION Dependency notation is always read from left to right relative to the symbol s orientation Dependency notation indicates the relationship between inputs outputs or
162. ations Manager Centennial Annex D2 P O Box 617 Colorado Springs Colorado 80901 0617 FOLD HERE Your cooperation in completing and returning this form will be greatly appreciated Thank you READER COMMENT SHEET Service Manual Model 64621A State Analysis Control Board 64621 90903 June 1983 Your comments are important to us Please answer this questionaire and return it to us Circle the number that best describes your answer in questions 1 through 7 Thank you 1 The information in this book is complete Doesn t cover enough 1 2 3 4 5 Covers everything what more do you need 2 The information in this book is accurate Too many errors 1 2 3 4 5 Exactly right 3 The information in this book is easy to find can t find things need 1 2 3 4 5 I can find info quickly 4 The Index and Table of Contents are useful Helpful 1 2 3 4 5 Missing or inadequate 5 What about the how to procedures and examples No help 12 3 4 5 Very helpful Too many now 1 2 3 4 5 I d like more 6 What about the writing style Confusing 1 2 3 4 5 Clear 7 What about organization of the book Poor order 1 2 3 4 5 Good order 8 What about the size of the book too big small 1 2 3 4 5 Right size Comments Particular pages with errors Name optional Job title Company Address Note If mailed outside U S A place card in envelope Use address shown on other side of this card 0103 HEWLETT
163. ative to the symbol s orientation with inputs on the left side of the symbol and Common control inputs are located in the control block and control the inputs outputs to the array elements outputs on the right side of the symbol the symbol may be reversed if the dependency notation is a single term N Analog Signal according to the dependency notation t 2 Inversion Shift Right or down amp AND O Negation Solidus allows an input or output to have All dependency notation is read from left to right relative to the symbol s orientation more than one function Inputs to the array elements are located with the corresponding array element with the least significant element closest to the control block Bit Grouping Nonlogic Input Output An external state is the state of an input or output outside the logic symbol Three State OUTPUTS Outputs are located on the right side of the symbol and are effected by their dependency notation gt Buffer Open Circuit external resistor An internal state is the state of an input or output inside the logic symbol All internal states are True High SYMBOL CONSTRUCTION Causes notation and symbols to effect inputs outputs an AND relationship and to occur in the order read from left to right ircuit ext resist Common control outputs are located in the control block Compare 9 Open external resistor Some symbols consist of an outline or combin
164. atus 8 55 Figure 8 18 Mainframe Write 8 5 7 Figure 8 19 Mainframe Read 8 59 vi Model 64621A General Information gt I 12 Figure 1 1 Model 64621A State Analysis Control Board SAC 1 0 Model 64621A General Information SECTION 1 GENERAL INFORMATION 1 1 INTRODUCTION 1 2 This Service Manual contains information required to install test and service the Hewlett Packard Model 64621A State Analysis Control Board SAC Operating in structions are provided in a separate Operating Manual supplied with the instrument It should be kept with the instrument for use by the operator 1 3 Shown on the title page is a microfiche part number This number can be used to order 4x6 inch microfilm transparencies of the manual Each microfiche contains up to 96 photoduplicates of the manual pages 1 4 SPECIFICATIONS 1 5 Instrument specifications are listed in table 1 1 These specifications are the performance standards or limits against which the instrument is tested Table 1 2 lists supplemental characteristics Supplemental characteristics are not specifications but are typical characteristics included as additional information for the user Table 1 1 Specifications Includes Models 64621A Control Board 64622A 40 Channel Acquisition and 64623A
165. ausing U50 pin 15 to change to a high state very quickly 8 73 The output of stage one U50 pin 15 is fed to the next stage providing U23 pin 6 with a positive going clock The same action as in stage one now begins in stage two This effect ripples through the remaining stages 8 74 The output of U50 pin 15 is also sent back to the reset input of U23B pin 13 When U50 pin 15 goes high U23B is reset causing U23 pin 15 to go low This action defines the pulse width of HSRS 8 75 At the same time U23 pin 14 is going high at the rate defined by the RC net work When U50 13 reaches the positive hysteresis U50 pin 15 goes low reset mode U23 pin 13 is now removed and stage one is ready to begin the cycle again SAC 8 13 Model 64621A Service TIME IN NANOSECONDS o 25 50 75 100 125 HSRS 023 15 45 20 HTIMS 050 14 dk HOVS 4 235 022 15 4 n 89 HPLS U22 2 47 HWRT 921 15 ae LMV e a 921 2 LDV Ua Ig 8 SAC 8 14 75 100 125 150 175 48 150 175 200 200 Figure 8 5 Strobe Timing Relationship 225 225 250 275 275 300 300 Model 64621A Service 8 76 SEQUENCER 8 77 Description 8 78 The Sequencer consists of memories counters and latches Its purpose is to enable various functions of the State Analy
166. ce Store Enable Qualify NTRIG Negative Trigger This signal goes from a high to a low each time a user specified trigger event occurs It is used to latch signals into the trace point latch internal to the Analysis Controller and into the BNC Port latch It is derived from the in ternal Trigger Signal or LSTE HSRS Low Sequence Trigger Enable High State Recognition Strobe signals from the Sequencer or either LTE HTR Low Trigger Enable High Trigger from the IMB LTE Low Trigger Enable This active low bidirectional signal is the IMB signal that is sent to the other modules when a trigger is recognized by the control board It is derived from the same signals NTRIG output is derived from 8 26 The Trace State Time Counter in Time Period 5 is used whenever that function is turned on in the trace specification It is another of the hybrid chips designed for this instrument Its function is to count the number of states between two states or periods of time between two states When LSTATE Low State is low the counter counts the number of states between two stored states The counter is in cremented by PINC Positive Increment which is developed from HWQ High Write Qualify and HWRT High Write HWQ is generated by the Analysis Controller and is used to disable the counter when the output of the Counter is being stored in the Trace Count Status Memory HWRT is developed in the Strobe Generator each time a qualified clock is det
167. del 64621A Service Table 8 2 Schematic Diagram Notes ETCHED CIRCUIT BOARD WIRE COLORS ARE GIVEN BY NUMBERS IN PARENTHESES USING THE RESISTOR COLOR CODE FRONT PANEL MARKING 925 15 WHT RED GRN 0 BLACK 5 GREEN 1 BROWN 6 BLUE 2 RED 7 VIOLET REAR PANEL MARKING 3 ORANGE 8 4 YELLOW 9 WHITE MANUAL CONTROL OPTIMUM VALUE SELECTED AT FACTORY TYPICAL VALUE SHOWN PART MAY HAVE BEEN OMITTED SCREWDRIVER ADJUSTMENT UNLESS OTHERWISE INDICATED ELECTRICAL TEST POINT RESISTANCE IN OHMS TP WITH NUMBER CAPACITANCE IN PICOFARADS INDUCTANCE IN MICROHENRIES NUMBERED WAVEFORM NUMBER CORRESPONDS TO MICROPROCESSOR ELECTRICAL TEST POINT NO PART OF NO CONNECTION LETTERED TEST POINT CLOCKWISE END OF VARIABLE NO MEASUREMENT AID RESISTOR PROVIDED you og od COMMON CONNECTIONS ALL LIKE DESIGNATED POINTS ARE CONNECTED NUMBER ON WHITE BACKGROUND OFF PAGE CONNECTION LARGE NUMBER ADJACENT SERVICE SHEET NUMBER FOR OFF PAGE CONNECTION CIRCLED LETTER OFF PAGE CONNECTION BETWEEN PAGES OF SAME SERVICE SHEET INDICATES SINGLE SIGNAL LINE NUMBER OF LINES ON A BUS 42 STD 20 09 81 SAC 8 40 Model 64621A Service Table 8 3 Logic Symbology Table 8 3 Logic Symbology Cont d Table 8 3 Logic Symbology Cont d GENERAL INPUTS Inputs are located on the left side of the symbol and are affected by their dependency notation OTHER SYMBOLS All signals flow from left to right rel
168. e Through the use of read and write decoders the Mainframe can select various groups of circuitry on the Control Board and write to program or read from verify interrogate them over the Mainframe s Data Bus SAC 8 8 Model 64621A Service TO FROM IMB CLOCK PROBE SEB TO FROM OTHER aa PREPROCESSOR TO FROM ACQUISITION BOARDS COME WE a 5 elo o o9 2 12920 re 9 5 S fo Sui we ou gt 2 cc ISISE zoo a Or ziooo PDC 0 9 E DE 2105 mua cla cm LME lt JO gt o O J cca VIT TI LTE LSE TEST 8 HTR STROBES PREPROCESSOR CLOCK INTERFACE PROBE HMCLK STROBE CONTROL ANALYSIS BUS LINES CONTROLLER INTERFACE GENERATOR HQWRITE HWQ TEST 1 9 STROBES TEST 11 LDBO 7 LABO 3 LDBO 7 TRACE STATE TIME COUNTER TEST 5 7 TRACE COUNT STATUS MEMORY TEST 6 BNC CONTROL CONTROL LDBO 7 LDBO 7 CONTROL DATA L25MHz CONTROL MAINFRAME INTERFACE TEST 1 Figure 8 2 State Analysis Control Board Block Diagram sac 8 9 Model 64621A Service 8 46 DETAILED CIRCUIT THEORY 8 47 CLOCK TERM GENERATOR 8 48 The Clock Term Generator U25 is a custom designed clock decoder It con verts eight clock channel inputs into a single master clock 8 49 Each clock input can be programmed by loading two internal shift regi
169. e Read Interface SAC 8 59 SALES amp SUPPORT OFFICES Arranged alphabetically by country Product Line Sales Support Key Key Product Line Analytical CM Components Computer Systems Electronic Instruments amp Measurement Systems Medical Products Personal Computation Products Sales only for specific product line Support only for specific product line IMPORTANT These symbols designate general product line capability They do not insure sales or support availability for all products within a line at all locations Contact your local sales office for information regarding locations where HP support is available for specific products HEADQUARTERS OFFICES If there is no sales office listed for your area contact one of these headquarters offices NORTH CENTRAL AFRICA Hewlett Packard S A 7 rue du Bois du Lan CH 1217 MEYRIN 1 Switzerland Tel 022 83 12 12 Telex 27835 hmea Cable HEWPACKSA Geneve ASIA Hewlett Packard Asia Ltd 47 F 26 Harbour Rd Wanchai HONG KONG G P O Box 863 Hong Kong Tel 5 8330833 Telex 76793 HPA HX Cable HPASIAL TD CANADA Hewlett Packard Canada Ltd 6877 Goreway Drive MISSISSAUGA Ontario L4V 1M8 Tel 416 678 9430 Telex 610 492 4246 EASTERN EUROPE Hewlett Packard Ges m b h Lieblgasse 1 72 A 1222 VIENNA Austria Tel 222 2500 0 Telex 1 3 4425 HEPA A NORTHERN EUROPE Hewlett Packard S A Uilenstede 475
170. e contact electrical outlet or used with a three contact to two contact adapter with the grounding wire green firmly connected to an electrical ground safety ground at the power outlet The power jack and mating plug of the power cable meet International Electrotechnical Commission IEC safety standards DO NOT OPERATE IN AN EXPLOSIVE ATMOSPHERE Do not operate the instrument in the presence of flammable gases or fumes Operation of any electrical instrument in such an environment constitutes a definite safety hazard KEEP AWAY FROM LIVE CIRCUITS Operating personnel must not remove instrument covers Component replacement and internal ad justments must be made by qualified maintenance personnel Do not replace components with the power cable connected Under certain conditions dangerous voltages may exist even with the power cable removed To avoid injuries always disconnect power and discharge circuits before touching them DO NOT SERVICE OR ADJUST ALONE Do not attempt internal service or adjustment unless another perscn capable of rendering first aid and resuscitation is present DO NOT SUBSTITUTE PARTS OR MODIFY INSTRUMENT Because of the danger of introducing additional hazards do not install substitute parts or perform any unauthorized modification of the instrument Return the instrument to a Hewlett Packard Sales and Service Office for service and repair to ensure that safety features are maintained DANGEROUS PROCEDU
171. e input data is latched into the acquisition cards The signals from the Strobe Generator P NBSRS Positive Negative Bus State Recognition Strobe are sent across the SEB Synchronous Expansion Bus to strobe in the data on the acquisition cards The PBSRS signal is also used in the Overview State Time Counter only on the 20 channel acquisition board to increment the overview counter every time a valid clock term is encountered 8 19 Time Period 3 8 20 The Resource Pattern Sequence Pattern and Event Generation is where the State Analyzer s resources are allocated and the Sequencer patterns determined The Acquisition Board detects specified combinations of trigger storage and count in formation and sends that information on LBRPO 7 Low Bus Resource Pattern over the SEB to the Resource Allocation portion of the Analysis Controller This section of the Analysis Controller determines from the data on the LBRO 7 lines how to allo cate the set number of resources available to the state analyzer among the trigger storage and count specifications 8 21 The Resource Pattern Sequence Pattern and Event Generation block also deter mines when the Data Acquisition boards have found the sequence state s requested by the user If no sequence events were specified then the Low Bus Sequence Pattern 0 3 LBSP 0 3 lines would always be high 8 22 Time Period 4 8 23 Time Period 4 Pipeline Registers is where the State Analyzer latches
172. e is used to indicate the edge that the signal becomes true on No indication of the voltage levels is given i e TIL ECL MOS This information is given on the schematic using the newer type of Logic Symbology Table 8 1 Mnemonics Mnemonic Description BSSO 3 Bus Sequence State 0 3 a feed back path within the Sequencer that enables it to change from one state to the next A state may require that an event occur only once or it may require the event to occur many times before changing to the next state CDO 7 Counter Data 0 7 outputs of the Trace Counter Status Memories The in formation stored in the Memories represents the time between two stored states or the number of states between two stored states A value for each measurement is stored and returned to the CPU 0 7 LDBO 7 over the CPU s Data Bus for formatting and display on the CRT The sequence state for each measurement is also returned to the CPU by CDO 7 CNTO 19 Count 0 19 outputs of the Trace State Time Counter CNTO 19 represents the time between two stored states or the number of states between two stored states The value CNTO 19 for each measurement is stored in the Trace Count Status Memory GNDSEN Ground Sense the return path from the Clock Probe for the Clock Threshold Digital to Analog Converters HBOTF High Bus Overview Trigger Flag from the ACQ Board When high indicates that the 20 Channel Acquisition Board has seen a qualified trigger
173. ecifications Therefore the Performance Verification Tests should be run only by a qualified service person 4 5 The Performance Verification tests are divided into two parts 1 automated tests and 2 manual tests The automated test must all pass before performing the manual tests NOTE Before running the following tests insure the boards are in stalled as indicated in Section II of this manual Both Operation Tests and Performance Tests must be run to insure that the Model 64621A meets all specifications after repair 4 6 The Troubleshooting portion of this Section describes the tests shows the dis plays for the tests decodes the displays and tells how to use the tests with Signature Analysis for troubleshooting 4 7 OPERATION VERIFICATION a Press opt test RETURN b Enter SLOT of State Control Board RETURN Press run all boards RETURN d The status line near the bottom should read STATUS 10MHz Verification PASSED e Run the continuity tests as outlined in Section IV of the Model 64635A General Purpose Data Probe and the Model 64636A General Purpose Clock Probe Service Manuals 4 8 PERFORMANCE VERIFICATION 4 9 Automated Tests a Press opt test RETURN b Enter SLOT of State Control Board RETURN SAC 4 1 Model 64621A Performance Verification Press run all boards RETURN 4 10 The status line near the bottom of the display should read Status 10MHz Verification Passed If
174. ected 8 27 When LSTATE is high the Counter counts the time between two states The L25 MHz Low 25 Megahertz signal is used to clock the Counter in this mode SAC 8 3 Model 64621A Service 8 28 Time Period 6 8 29 Time Period 6 is the Store Data and Output block This is the last stage before the captured data and count information is sent to CPU for display There are three separate operations that occur in this block 8 30 The first is on the 64623A the 20 channel acquisition board where the Overview events are stored in the Overview memory The CPU unloads Overview Memory using LRDL Low Read Data Latch for the Overview Event Data Latch and LRDOV Low Read Overview for the Overview Memory Address Counter Latch 8 31 The second operation that occurs in this block is on both the 64622A 40 chan nel acquisition board and the 64623A 20 channel acquisition board The 20 chan nels of data on each half of the board are latched into the Trace Pod Data Memory by HBQWRT High Bus Qualified Write HBQWRT synchronizes the data storage with the Trace Counter Status Memory on the control board The data is read from the Trace Pod Data Latch onto the CPU Data Bus by LRDL Low Read Data Latch which is developed on the acquisition board from CPU control signals 8 32 The third operation takes place on the control board The Trace Count Status Memory section of the Control Board stores the 8 outputs of the Sequence State Latch Co
175. ed to change from one sequence state to the next as well as function enables for count trigger store and master enable functions a trigger signal HSTR and a store signal LSSQ The Memories also output Low Overview Enable LOVEN and Low Overview Reset LOVRST which con trol Overview on the 20 Channel Board The Memories output two control signals to the Sequence Occurrence Counter Low Sequence Occurrence Counter Load LSOCLD and Low Sequence Occurrence Counter Enable LSOCEN 8 90 Function Enables The Sequencer will enable an Analyzer function only when all specified sequence terms have been found The enabling signals serve as inputs to the Analysis Controller except for LOVEN and are as follows LSOCE Low Sequence Overview Count Enable LSCE Low Sequence Count Enable LSSE Low Sequence Store Enable LSTE Low Sequence Trigger Enable LOVEN Low Overview Enable LSME Low Sequence Master Enable The Sequencer can disable the above functions by driving any of them high 8 91 Sequence Occurrence Counter Memories This part of the Sequencer controls the Occurrence or the number of times a sequence state must be found before the Sequencer moves on to the next specified state 8 92 An Example Suppose a state must occur 10 times before the Sequencer looks for the next state Before the trace started the Transition memories were loaded so that when the term prior to the 10 times term was found the Transition Memories output Low S
176. elector This means that the control section will count using 25 MHz as input PINC is used to count states it will reset when PSET goes high and it will latch the count when PLATCH goes high The count pulse must be enabled by a high counter enable HCE in order to reach the prescale circuitry The prescaler will pass pulses directly to the 20 bit counter until the count ex ceeds 611 000 Then the 3 bit exponent will cause the prescaler to divide by 8 before allowing a count pulse As the count increases the prescaler will divide by 2 10 2 e17 and finally 2 e2h 8 127 PSET Positive Set PSET is an edge sensitive input which resets the counter to a known state The counter is locked in that state until the reset function is clocked by 25 MHz The half way AND gate does not allow PSET to reset the counter until it has counted to at least half way through the divide by 1 range SAC 8 24 Model 64621A Service 8 128 20 Bit Counter The counter provides a 20 bit output consisting of 3 bit ex ponent and a 17 bit mantissa It operates either as a time counter or as a state counter The time count mode provides a minimum resolution of 40 nS with a minimum 3 digit accuracy from 100 nS to 30 kS 8 hours The state count mode provides single state resolution to 611 670 states and prescaled counts up to 750 000 000 000 states Because it counts in Gray Code only one bit changes for each new state the outputs appear to change without a patt
177. equence Occurrence Counter Load LSOCLD At that time 550 3 will cause the Occurrence Memories to output terminal count 65535 minus 10 or 65525 LSOCLD will load the Occurrence Counter with 65526 The next time the sequence pat tern goes true the Transition Memories will output Low Sequence Occurrence Counter Enable enabling the Occurrence Counter The Occurrence Counter will be incremented by Positive Sequence Occurrence Counter Increment PSOCINC due to HWRT strobe This will continue until the Counter reaches terminal count Then the Counter out puts Low Occurrence Carry LOCCRY which will be latched into the Sequence State Latch and will change the sequence state 8 93 Sequencer Troubleshooting 8 94 Performance verification on the Control Board tests the Sequencer using Test 4 loop includes the feedback paths of LOCCRY and BSSO 3 If signature analysis shows that multiple signatures are bad it is due to the propogation of a bad signature around the loop Test 1 has been provided to break the feedback It is a stimulus test for the Sequencer which writes to all locations of the Transition Memories and the Occurrence Memories and tests the Occurrence Counter but does not latch the next sequence state into the Sequence State Latch SAC 8 17 Model 64621A Service LSOCLD SEQUENCE LSOCEN OCCURRENCE SEQUENCE COUNTER OCCURRENCE TERMINAL COUNT COUNTER TC ME
178. er High Enable Halt when high HENHLT allows PHALT to be sent to the Preprocessor HENHLT is CPU controlled High Enable Stimulus when high HENSTIM allows PSTIM to be sent to the Preprocessor HENSTIM is CPU controlled High Invert when high inverts the two signals going to PORT1 and PORT2 The inversion may be selected by a keyboard command High Load when high HLD switches the Sequence State Latches Counter to the count mode The outputs of the Counter are used to address the Sequence Transition Memories while loading information from the CPU LDBO T LSEQDO 7 HLD and LLD are asserted at the same time High Master Clock when going from a low to a high HMCLK indicates that the eight clock inputs have satisfied the requirements that have been programmed into the Clock Term Generator by the CPU and has started the Strobe Generator Cycle HMCLK is wire ORed with PPVSTB and PBSTBRQ Mnemonic HOTFB HOVCQ HOVS HPLS HQWRITE HSRS HSTR HTCLK HTIMS HWQ Model 64621A Service Table 8 1 Mnemonics Cont d Description High Overview Trigger Flag Buffered from the ACQ Board When high in dicates that the 20 Channel Acquisition Board has seen a qualified trigger event A trigger event is a single occurrence of an event decoded from in put data or from the Overview State Time Counter HOTFB comes from the 20 Channel ACQ Board only High Overview Count Qualify HOVCQ becomes HBOVCQ When
179. erformance Verification CONNECTIONS Test 5 Loop E VH U16U ST SP Start TP19 Qual Stop TP19 Clock U99 pin 3 Ground GND TP ECL ECL ECL ECL ECL ECL ECL ECL ECL d c c c c c c c c c c c N T high high 6536 762C 9U15 C234 6960 5380 POUH 9UTP U16U 6510 high high high high U16U high high high 7020 762C 7190 C234 UF AU 5380 CPC6 U35F 0160 19 high 7020 7190 4FAU CPC6 7020 7190 4FAU 6 ECL ECL ECL ECL SAC 4 43 Model 64621A Performance Verification Board 64621 66503 Test 5 Loop E VH U16U MODE EDGES THRESHOLDS CONNECTIONS Normal Clock Positive Data High ST SP Start TP19 Start Positive Data Low Qual Stop TP19 SSeS Stop Negative Clock TIL Clock U99 pin 3 ST SP QL TIL Ground GND TP levels are TIL except where noted U 85 7 F996 U 91 11 990 0 93 13 028 0 91 12 8 36 0 93 14 FCCP U 85 1 F996 ECL 91 13 2 6 U 93 15 8173 U 91 14 FCCP 0 93 16 9055 U 87 1 0160 U 91 15 1H31 U 93 18 POUS TOTLZ 6550 U 91 16 9054 U 93 20 U16U U 87 2 F9PC U 91 18 9U7P TOTLZ 19 U 87 3 low 91 20 1160 U 93 21 high U 87 4 10160 TOTLZ 19 U 87 5 5CF3 0 91 21 high U 94 4 796A U 87 6 low U 94 5 6872 U 87 7 high 0 92 1 high 0 94 12 028 0 87 9 high U 92 2 high U 94 13 8173 0 87 10 low 92 3 high U 87 11 low U 92 3 U16U U 94 3 796A ECL U 87 12 high TOTL
180. ern The counter out puts are reset after each storage event an exception is gt halfway restriction in time count which produces a relative count 8 129 Output Latch The Output Latch is controlled by a gate and an output enable When PLATCH goes high the counter outputs are latched The exception is PSET When PSET is low and trace state is selected the latch is transparent when PSET goes high the counter outputs are latched Low output enable LOE enables the output drivers The counter outputs will be low when LOE is high or when the counter is reset latched and LOE goes low SAC 8 25 Model 64621A Service PIN 32 HCE ECL 8 HTIME LSTATE TTL 35 HOV LTRACE ECL 27 ECL 33 34 25 MHz ECL 25 PSET ECL 26 PLATCH ECL 9 HLOAD TTL 7 LOE TTL 5V d Vcc 3 25V z VEE 3 25V VEE 29 GND GND Figure 8 10 State Time Counter Block Diagram SAC 8 26 gt 3 ENABLE TEN TEN R gt HALF E ee MN VEM ae 20 BIT GRAY CODE COUNTER EXP RACE STATE RACE TIME MANTISSA 20 CNTO 19 ECL Model 64621A Service 8 130 MNEMONICS 8 131 The signals in this product have been assigned mnemonics that indicate the true state and the function of the signal line In general the first character in dicates the true state H for high 1 for low If the signal is used with an edge sensitive device P for positive and N for negativ
181. ertriebszentrun S dwest Schickardstrasse 2 D 7030 BOBLINGEN Tel 07031 645 0 Telex 7265 743 hep A C CM E M P Hewlett Packard GmbH Vertriebszentrum West Berliner Strasse Ill D 4030 RATINGEN 3 Tel 02102 494 0 Telex 589 070 hprad A C E M P Hewlett Packard GmbH Gesch ftsstelle Schleefstr 28a D 4600 DORTMUND 41 Tel 0231 45001 Telex 822858 hepdad ACE Hewlett Packard GmbH Vertriebszentrum Mitte Hewlett Packard Strasse D 6380 BAD HOMBURG Tel 06172 400 0 Telex 410 844 hpbhg Hewlett Packard GmbH Vertriebszentrum Nord Kapstadtring 5 D 2000 HAMBURG 60 Tel 040 63804 1 Telex 021 63 032 hphh d A C E M P Hewlett Packard GmbH Gesch ftsstelle Heidering 37 39 D 3000 HANNOVER 61 Tel 0511 5706 0 Telex 092 3259 A C CM E M P Hewlett Packard GmbH Gesch ftsstelle Rosslauer Weg 2 4 D 6800 MANNHEIM Tel 0621 70 05 0 Telex 0462105 ACE Hewlett Packard GmbH Gesch ftsstelle Messerschmittstrasse 7 D 7910 NEU ULM Tel 0731 70 73 0 Telex 0712816 HP ULM D Hewlett Packard GmbH Gesch ftsstelle Emmericher Strasse 13 D 8500 N RNBERG 10 Tel 0911 5205 0 Telex 0623 860 hpnbg C CM E M P Hewlett Packard GmbH Vertriebszentrum S d Eschenstrasse 5 D 8028 TAUFKIRCHEN Tel 089 61 20 7 0 Telex 0524985 A C CM E M P Hewlett Packard GmbH Gesch ftsstelle Ermlisallee 7517 WALDBRONN 2 Tel 07243 602 0 Telex 782 838 hepk ACE GREAT BRITAIN See United Ki
182. event A trigger event is a single occurrence of an event decoded from input data or from the Overview State Time Counter HBOTF comes from the 20 Channel ACQ Board only HBOVCQ High Bus Overview Count Qualify sent only to the 20 Channel Data Acquisition Board When high HBOVCQ allows the Overview Counter to incre ment HBOVCQ may be driven by the Analysis Controller or HOVCQ HBOWRT High Bus Overview Write sent to the 20 Channel Acquisition Board only When high HBOWRT enables write circuits on the 20 Channel ACQ Board for writing to the Overview Event Memories HBOWRT is also used to increment the Overview Trace State Time Counter and can drive PSOCINC due to a wire OR connection see PSOCINC When enabled on the 20 Channel Data Acquisition Board HBOWRT allows the Overview Event Memories to be written to and increments the Overview Memory Address Counters HBQWRT High Bus Qualified Write when high HBQWRT synchronizes the Trace Pod Data Memories in the Acquisition Boards with the Trace Counter Status SAC 8 27 Model 64621A Service Mnemonic 0 1 HCLKO 7 HCQ HCQB HCTST HDVLD HENHLT HENSTIM HINV HLD HMCLK SAC 8 28 Table 8 1 Mnemonics Cont d Description Memories in the Control Board When low HBQWRT increments the Trace Pod Data Memory Address Counters in the Data Acquisition Boards HBQWRT is enabled by HWQ and is derived from HWRT High Clock Data 0 1 outputs from the
183. gh Master Clock HMCLK A high output by the Edge Detect Register to any flip flop will prevent that detector from toggling All filp flop outputs are ORed to produce HMCLK Therefore all possible combinations of channels and edges are allowed The only restriction is that HMCLK pulses must be at least 100 nS apart 8 56 HMCLK drives Pulse Width Output PWO which is connected externally to Pulse Width Input PWI After a delay PWI resets the edge detector responsible for the master clock This results in a pulse width of 15 nS maximum for HMCLK 8 57 The Edge Detect Shift Register and Level Detect Shift Register can be made to overflow during performance verification These registers output High Clock Data 0 and 1 HCDO 1 SAC 8 10 Model 64621A Service CLOCK TERM GENERATOR FROM EDGE SELECT REGISTER 1 OF 8 CLOCK INPUTS FROM 5 CLOCK PROBE POSITIVE OR EDGE PREPROCESSOR 6 DETECTOR PWI ECL 35 WIRED TOGETHER EXTERNALLY LEVEL SELECTOR 2 36 FROM LEVEL SELECT FROM EDGE SELECT REGISTER REGISTER 12 5 TYPICAL V NEGATIVE t3 EDGE HMCLK ECL 39 srROBE DETECTOR 25 11 FROM OTHER 12 7 OTHER 31 LEVEL 32 SELECTORS 9 10 33 34 TO D INPUTS 14 OTHER TO RESET INPUTS 14 OTHER EDGE DETECTORS EDGE DETECTORS FROM D CPU DATA 13 BUFFER 16 BIT EDGE SELECT REGISTER V_g FROM ja PWCLK TTL ie WRITE DECODER ANALYSIS STATUS BUFFER HCD1 TTL FROM
184. ght bits are defined to be clocks or qualifiers by keyboard entry LCLKO 7 may come from either the Clock Probe or the Preprocessor Low Clear used to clear various counters and registers on the Control Board Derived from the CPU Address Bus and other Mainframe control lines LCLR is also used on the 20 and 40 Channel Data Acquisition Boards LBCLR to clear various counters and registers Low Data 0 12 a 16 bit bidirectional bus used to transfer data to and from the CPU When LSTB is low the data on the bus is valid Only bits 0 12 are used in this model Mnemonic LDB0 7 LDV LDVTTL LIAO 3 LID LIDB LIDO T LIWRT LLD LMACS LMAP2 LMC LME Model 64621A Service Table 8 1 Mnemonics Cont d Description Low Data Buffered 0 7 same as LDO 7 with additional buffering LDBO 7 is distributed throughout the State Analyzer Control Board Low Data Valid developed by the Strobe Generator When low LDV indi cates that the Trace Memory outputs are stable and the CPU may read them Low Data Valid TTL LDVTTL is used to clock the Trace Point Register LDVTTL is derived from LDV in the Strobe Generator Low Interface Address 0 3 signals used for reading and writing informa tion in the Preprocessor LIA0 3 are derived from the CPU s Address Bus Low Identification a signal originating in the Mainframe When low the CPU is requesting that the Board Identification be sent from the State A
185. hen LME is low the State Analyzer is al lowed to operate in a normal mode without waiting for other modules If the State Analyzer is operating in the Measurement Enable Mode and LME is high it may not drive or receive any IMB functions LME is wire ORed with other modules SAC 8 31 Model 64621A Service Mnemonic LMS LMSYN LMV LOCCRY LOVEN LOVRST LPOP LPPBEN LPPSTB LRC LRDEN SAC 8 32 Table 8 1 Mnemonics Cont d Description Low Memory Select developed from LSEL and LSTM When low LMS latches the CPU Address Bus LAO 13 LWRT and LID into the Address Latches At the same time LMS enables the CPU Data Buffer bidirectional If LRSTB is low the CPU can send information to the Control Board over the CPU Data 100 12 If LRSTB is high the CPU can read information from the Control Board Low Memory Synchronize a signal sent to the CPU When low the CPU is forced to wait until the Control Board can complete a read or write operation Low Memory Valid developed by the Strobe Generator When low LMV generates PMACRS and NMACRS if PBRSTB has occurred Low Occurrence Carry when low LOCCRY indicates that the Sequence Occurrence Counters have reached terminal count Low Overview Enable LOVEN is sent only to the 20 Channel Data Acquisition Board When low LOVEN allows the Overview section to look for its Trigger Events LOVEN is strobed to the 20 Channel Board with HOVS
186. home Shinjuku ku TOKYO 160 Tel 03 348 4611 CE Yokogawa Hewlett Packard Ltd 29 21 Takaido Higashi 3 Chome Suginami ku TOKYO 168 Tel 03 331 6111 Telex 232 2024 YHPTOK A C CM E M P Yokogawa Hokushin Electric Corp 9 32 Nokacho 2 Chome 2 Chome Musashino shi TOKYO 180 Tel 0422 54 1111 Telex 02822 421 YEW MTK J A Yokogawa Hewlett Packard Ltd Meiji Seimei Utsunomiya Odori Building 1 5 Odori 2 Chome UTSUNOMIYA Tochigi 320 Tel 0286 33 1153 Yokogawa Hewlett Packard Ltd Yasuda Seimei Yokohama Nishiguchi Bidg 30 4 Tsuruya cho 3 Chome YOKOHAMA 221 Tel 045 312 1252 CE JORDAN Scientific and Medical Supplies Co Box 1387 AMMAN Tel 24907 39907 Telex 21456 SABCO JO ADCOM Ltd Inc Kenya 30070 NAIROBI Tel 331955 Telex 22639 Samsung Hewlett Packard Co Ltd Dongbang Yeoeuido Building 12 16th Floors 36 1 Yeoeuido dong Yongdeungpo ku SEOUL Tel 784 2666 784 4666 Telex 25166 SAMSAN K A C CM E M P Young In Scientific Co Ltd Youngwha Building 547 Shinsa Dong Kangnam ku SEOUL 135 Tel 5467771 Telex K23457 GINSCO A KUWAIT Al Khaldiya Trading amp Contracting P O Box 830 SAFAT Tel 424910 411726 Telex 22481 AREEG KT Cable VISCOUNT Gulf Computing Systems Box 25125 SAFAT Tel 435969 Telex 23648 Photo amp Cine Equipment P O Box 270 SAF
187. ic ordering information are available through your local HP office Addresses and phone numbers are located at the back of this manual SAC 6 2 Model 64621A Replaceable Parts Table 6 1 Reference Designators and Abbreviations assembly motor battery capacitor coupler diode delay line device signaling lamp misc electronic part amperes automatic frequency control amplifier beat frequency oscillator beryllium copper binder head bandpass brass backward wave oscillator counter clockwise ceramic Cabinet mount only coeficient common K composition complete LH connector LIN cadmium plate LK WASH cathode ray tube LOG clockwise LPF deposited carbon M drive MEG MET FLM electrolytic MET OX encapsulated MFR external MHZ MINAT farads MOM flat head MOS fillister head MTG fixed MY giga 109 N germanium glass NE ground ed REFERENCE DESIGNATORS fuse filter integrated circuit jack relay inductor loud speaker meter microphone ABBREVIATIONS henries N O hardware NOM hexagonal NPO mercury hour s hertz intermediate freq impregnated incandescent includets insulationted internal kilo 1000 left hand linear taper lock washer logarithmic taper low pass filter milli 10 3 meg 106 metal film metallic oxide manufacturer mega hertz miniature momentary metal
188. ications Depth 3 choices 15 terms with restarts no windows 7 terms with restarts one window 3 terms without restarts two windows Occurrence 1 to 65535 times Enable Disable separately Immediately Eventually qualification 8 82 The depth is due to the feedback signals Bus Sequence State 550 3 Four signals allow only sixteen permutations and one cannot be used A window uses a signal and it cannot be used by the terms The Sequence Occurrence Counter is a sixteen bit counter 8 83 Sequencer Block Diagram 8 84 The major components of the Sequencer are the Sequence Pattern Trigger Memory the Sequence State Latch Counter the Sequence Transistion Memories the Sequence Occurrence Counter Memories and the Sequence Occurrence Counter All of these com ponents are located on the Control Board except the Trigger Memories which lo cated on the Data Acquisition Boards All the Memories must be loaded with informa tion from the Mainframe before a trace begins 8 85 During a trace synchronous data e g SYNDO 19 on a 20 Channel Acquisition Board from the State Recognition Latch Counter provides part of an address to the Sequence Pattern Trigger Memory The remainder of the address is provided by Bus Sequence State 550 3 the last sequence state The Trigger Memories output a se quence pattern LBSPO 3 All Trigger Memories are wire and will drive a se quence pattern signal true low if all the Memories were
189. ight size Comments Particular pages with errors Name optional __ Job title Company Address Note If mailed outside U S A place card in envelope Use address shown on other side of this card HEWLETT CA PACKARD SERVICE MANUAL MODEL 64621A STATE ANALYSIS CONTROL BOARD REPAIR NUMBERS This manual applies to 64621A State Analysis Control Boards with a repair number prefix of 2311A For fur ther information on repair numbers refer to Instruments Covered by This Manual in Section I and Section VII for Backdating to earlier Models COPYRIGHT HEWLETT PACKARD COMPANY 1982 1983 LOGIC SYSTEMS DIVISION COLORADO SPRINGS COLORADO U S A ALL RIGHTS RESERVED Manual Part No 64621 90903 PRINTED June 1983 SAFETY SUMMARY The following general safety precautions must be observed during phases of operation service and repair of this instrument Failure to comply with these precautions or with specific warnings elsewhere in this manual violates safety standards of design manufacture and intended use of the instrument Hewlett Packard Company assumes no liability for the customer s failure to comply with these requirements GROUND THE INSTRUMENT To minimize shock hazard the instrument chassis and cabinet must be connected to an electrical ground The instrument is equipped with a three conductor ac power cable The power cable must either be plugged into an approved thre
190. ing improvements made after the printing of the manual To use this supplement Make all ERRATA corrections Make all appropriate serial number related changes indicated in the tables below Serial Prefix or Number Make Manual Changes Serial Prefix or Number Make Manual Changes S kK A NEW ITEM Model 64621A is now supported by the Bluestripe program which means you should no longer perform component level troubleshooting on the board whose number is listed here The Bluestripe pipeline contains replacement boards for 64000 options made by Hewlett Packard replacement boards for this instrument are available at the factory The part number for the replacement board is 64621 69503 NOTE Manual change supplements are revised as often as necessary to keep manuals as current and accurate as possible Hewlett Packard recommends that you periodically request the latest edition of this supplement When requesting copies quote the manual identification information from your supplement or the model number and print date from the title page of the manual Date 7 March 1984 HEWLETT Page lof 1 ISSUE A 2 PACKARD Printed in U S A 3H3H 0103 HEWLETT NO POSTAGE PACKARD NECESSARY IF MAILED THE UNITED STATES BUSINESS REPLY CARD FIRST CLASS PERMIT NO 1303 COLORADO SPRINGS COLORADO POSTAGE WILL BE PAID BY ADDRESSEE HEWLETT PACKARD LOGIC PRODUCT SUPPORT DEPT Attn Technical Public
191. iption Positive Bus Strobe Request a signal coming from the Data Acquisition Boards during Performance Verification only PBSTBRQ when going from a low to a high state begins a strobe generator cycle PBSTBRQ is wire ORed with PPVSTB and HMCLK Positive Delayed Clock an IMB signal driven by the State Analyzer PDC is a delayed version of HMCLK When enabled PDC may be used by other Modules using the IMB Positive Data Strobe a differential signal NDSTB developed in the Strobe Generator PDSTB and NDSTB are used to develop HDVLD see HDVLD Positive Halt PHALT goes from a low to a high state when Trace Point or Measurement Complete occurs if enabled by the user PHALT is used in the Preprocessor if enabled and becomes PORT2 Positive Interface Halt a differential signal NIHALT sent to the Preprocessor that can be used to halt the user s system PIHALT is derived from PHALT when enabled by HENHLT Positive Interface Stimulus a differential signal NISTIM sent to the Preprocessor PISTIM is developed from PSTIM when enabled by HENSTIM PISTIM goes from a low to a high state when a Trigger Event or Sequence Event occurs if enabled by the user Positive Memory Address Counter Register Strobe a differential signal NMACRS developed in the Strobe Generator PMACRS is used to latch infor mation from the Trace Count Status Memory Address Counter into the Trace Memory Address Counter Read Register The information
192. ise noted SAC h 16 Model 64621A Performance Verification 4 22 The Synchronous Expansion Bus SEB connects the State Control board to State Acquisition boards The SEB is not tested here it is tested by the automatic tests for the State Acquisition boards Also the overview functions for the Analysis Controller chip are not tested here 4 23 Configuration For the purpose of running P V during fault isolation the State Analysis Subsystem can be run in a minimum configuration The minimum con figuration for the various boards is shown in the following table Table 4 1 Troubleshooting Configurations Board Under Test Need 64621A 64622A 64623A 64621A YES YES YES 64622A NO YES YES 64623A NO NO YES Clock Probe NO NO NO Data Probe N A NO NO SEB NO YES YES IMB NO NO NO Other Boards NO NO NO 4 24 After repairing individual boards the system must be configured to a standard configuration per Section II and pass the 11 boards test This will uncover system interaction problems or failures if they exist Note that the IMB test using a Timing 64600S Subsystem will pass only if the Timing Subsystem is completely in stalled and correctly cinfigured SAC 4 17 Model 64621A Performance Verification 4 25 TEST 1 MAINFRAME INTRFC and STIMULUS LOOP A 4 26 Purpose the purpose is two fold to verify that the mainframe can control the State Control board and to stimulate the Sequencer and the Clock Threshold D A
193. it code that indicates the manufacturer e The manufacturers part number The total quantity for each part is given only once at the first appearance of the part number in the list 6 7 ORDERING INFORMATION 6 8 To order a part listed in the replaceable parts table quote the Hewlett Packard part number and check digit indicate the quantity required and ad dress the order to the nearest Hewlett Packard office 6 9 To order a part that is not listed in the replaceable parts table include the instrument model number instrument repair number the description and function of SAC 6 1 Model 64621A Replaceable Parts the part and the number of parts required Address the order to the nearest Hewlett Packard office 6 10 SPARE PARTS KIT 6 11 A spare parts kit is not available at this time 6 12 DIRECT MAIL ORDER SYSTEM 6 13 Within the USA Hewlett Packard can supply parts through a direct mail order system Advantages of using the system are as follows a Direct ordering and shipment from the HP Parts Center in Mountain View California b No Maximum or minimum on any mail order there is a minimum order amount for parts ordered through a local HP office when the orders require billing and invoicing c Prepaid transportation there is a small handling charge for each order d No invoices to provide these advantages a check or money order must accom pany each order 6 14 Mail order forms and specif
194. itive Data Low Qual Stop TP19 Stop Negative Clock TIL Clock U99 pin 3 ST SP QL Ground GND TP levels are except where noted U 1 17 99CA 0102 10 6 U121 1 AH41 U 1 18 A22H U102 12 F513 U121 2 3831 U 1 19 F513 U121 4 ACHH U 1 20 3831 0121 16 0103 2 2 0121 18 3831 U103 3 2H4F U121 19 0000 U102 1 820F 0103 0102 2 6 0103 7 A22H U102 3 F513 0122 1 0102 h A959 U122 6 99CA U102 5 A959 U118 2 2HUF 0122 19 U102 6 0418 U118 3 2H4F TOTLZ 6027 U118 11 0000 TOTLZ 982 SAC 4 37 Model 64621A Performance Verification Board 64621 66503 Test 3 Loop VH C811 MODE EDGES THRESHOLDS CONNECTIONS Normal Clock Positive Data High ST SP Start TP19 Start Positive Data Low Qual Stop TP19 Stop Negative Clock Clock U99 pin 3 ha ST SP QL TIL Ground GND TP levels are TIL except where noted U 25 13 993U U 52 12 C851 U121 8 6 9 U 25 14 6 99 U 52 15 80 ECL U121 9 1861 U 25 15 92 U121 11 1861 25 16 0F97 0121 12 6HH9 U 25 26 0 97 U102 1 09 2 0121 17 92 U 25 28 A384 U102 2 0121 18 9930 U102 3 6HH9 U121 19 0000 U102 4 CC76 TOTLZ 213 U 25 9 high ECL U102 5 6 U102 6 C851 0102 13 6 99 U122 1 0367 52 5 C851 0122 3 1861 U 52 10 C80P U122 5 6HH9 0121 1 0367 U122 15 A384 U121 2 993U U122 17 OF97 U 52
195. k U99 pin 3 Ground GND TP Qual U100 pin 7 ECL ECL ECL ECL U110 12 0110 13 0110 3 0110 7 0110 11 0110 15 0112 0112 MO 0112 U112 U112 U112 U112 U112 1h U112 15 U112 16 U112 17 U112 18 U112 19 U112 20 U112 21 U112 22 U112 23 U112 25 TOTLZ U112 26 TOTLZ U112 27 TOTLZ U112 32 U112 36 U112 37 U112 38 U112 39 0112 10 EW U118 2 1118 3 U118 4 U118 5 0 05 UAFH UOFP 3098 0405 UAFH low high AOCT 42154 160 UOFP 934P 0 05 UAFH 8F6A 1F56 HU5A AOCT 42154 1610 UOFP 3U98 0000 1796 0000 1796 0000 1796 ThP2 0A05 UAFH 8F6A 1F56 HUSA C6AH C6AH CHOP CHOP ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL SAC 4 49 Model 64621A Performance Verification Board 64621 66503 Test 6 Loop 894H QUAL PFA4 MODE EDGES THRESHOLDS CONNECTIONS Normal Clock Positive Data High ST SP Start 19 Start Positive Data Low Qual Stop TP19 QUAL Stop Negative Clock Clock U99 pin 3 High ST SP QL TTL Ground GND TP Qual 0100 pin 7 levels TIL except where noted 0118 11 0000 0121 11 8007 U122 h AF2A TOTLZ OFLO U121 12 1108 U122 6 2362 U121 13 F789 U122 9 8 08 U121 1 489A U121 14 8 08 U122 11 4525 U121 2 FF34 0121 15 1U1A QUAL U122 14 6412
196. loped in the Strobe Generator Used to latch the outputs of the Trace Pod Data Memories into the Trace Pod Data Latch on the Data Acquisition Boards Positive Bus Overview Reset developed from HOVS PBOVRST is used only on the 20 Channel Data Acquisition Board When PBOVRST goes from a low state to a high state the 20 Bit Overview Counter is reset Positive Bus Pipeline Strobe same as HPLS except buffered Used in the 20 and 10 Channel Data Acquisition Boards for latching information into Pipeline Registers at the correct time in the Analyzer s timing cycle Positive Bus Read Strobe a CPU generated signal When PBRSTB goes from a low state to a high state P N DSTB P N MACRS and P N SQRGS are enabled in the Strobe Generator These strobes are used to latch internal informa tion into various data registers memories as it moves from the input of the State Analyzer to the its outputs and then to the CPU Positive Bus State Recognition Strobe a differential strobe NBSRS developed in the Stroke Generator and sent to the Data Acquisition Boards At the beginning of a data acquisition cycle PBSRS goes from a low state to a high state PBSRS is used to latch user information into the State Recognition Latches Counters SAC 8 37 Model 64621A Service Mnemonic PBSTBRQ PDC PDSTB PHALT PIHALT PISTIM PMACRS 1 2 PPLS PPVSTB PSOCINC SAC 8 38 Table 8 1 Mnemonics Cont d Descr
197. m 2 ol2 25 EO lt 5 o cjui g Su O SF 19 dr s 49 2 2 MP2 gt 5 u 5 ar 5 29 PDC n1 m 02 Ds di S 9 TP STATE CONTROL BOARD 7 8 R8 x R amp 586 o o m a OL Da OLII i ARI ee 10 FS1 H LSE ua Us ur J e 9 N n 09 5 8 HTR BU METEO ME m E STROBES 015 ae gt RIO me HM bol F1 ME A PREPROCESSOR CLOCK EE Jest 77 z ES I STR INTERFACE PROBE HMCLK STROBE CONTROL ANALYSIS EE BUS INTERFACE GENERATOR LINES CONTROLLER 8 5 i T m k Uso HQWRITE HWQ Qi U31 U32 U33 U34 i a Um TEST 11 TEST 1 9 lt 24 Hi UST i 939 046 U48 U49 USI pe 8 g 1 d d 1 H U40 042 L E STROBES A C30 C31 C32 C33 34 Oeno 5 22 bou N e N 9 N C28 uss DI 29 USTR 2 p FP I U74 a m m m us m m 070 971 972 973 5 8 8 G 7 2 LI L STATE TIME Z COUNT STATUS urs er cca Ee c39 u77 COUNTER MEMORY s ef 5 5 7 6 m i FA BNC uso U82 u83 uss uss U87 uss ve i a CONTROL 095 ci tra 41 2 D mE R4o C47 C48 49 Una 5 098 u99 9100 9101 0102 9104 0105 0106 0107 0108 U110 cb TRB
198. maximum Data Hold Time 0 nS Description Since the data inputs are sampled with selected transitions of the clock they must remain stable at the time of the clock to ensure that the desired input state is sampled Data setup and hold time specifications define the time period that data inputs must remain stable Data setup time is the time prior to the clock that data inputs must begin to be stable data hold time is the time after the clock when data inputs are no longer required to remain stable This test is to verify that the correct state is sampled when data inputs with minimum setup and hold time requirements are presented to the State Analyzer Equipment SAC 4 6 Pulse Generators 2 2 8013 Oscilloscope 2 1 22 or 1753 STATE ANALYZER STATE CONTROL BOARD Model 64621A Performance Verification PULSE PULSE GEN 1 GEN 2 OSCILLOSCOPE TRIG TRIG IN QUT OUT OUT CLOCK PROBE TEST CONNECTOR SEE FIGURE 4 4 10 1 PROBE DATA PROBE TEST CONNECTOR SEE FIGURE 4 7 19 GND Figure 4 5 Setup and Hold Time Test Configuration SAC 4 7 Model 64621A Performance Verification Procedure a Press meas sys only if more than one measurement system is installed b Press state x c Press format specification d Adjust Pulse Generators 1 and 2 for waveforms A and B respectively as in Figure h 6 SAC
199. nalyzer Control Board to the CPU over the Data Bus on data bits 8 and 12 Low Identification Buffered a signal originating in the Mainframe and buffered on the State Analyzer Control Board See LID Low Interface Data 0 7 a bidirectional data bus between the Preprocessor and the Control Board LIDO 7 are derived from the CPU s bidirectional Data Bus Low Interface Write one of the control lines from the Control Board to the Preprocessor When low the Control Board is writing to the addressed device i e the Preprocessor LIWRT is the same as LWRT except buffered two times LWRTB Low Load when low LLD allows the internal registers of the Analysis Controller to be loaded with serial data LBDO from the CPU LLD and HLD are asserted at the same time Low Memory Address Counter Select developed in the Strobe Generator When low LMACS allows the Trace Count Status Memory Address Counters on the Control Board to address the Trace Counter Status Memories When high the CPU can address the Memories over the CPU Address Bus Low Map 2 a signal developed by the CPU LMAP2 is used as the Start Stop Pulse in Signature Analysis and appears only on the extender card Low Measurement Complete when low LMC indicates that the State Analyzer has stored all the information requested by the user in the Trace Memories Low Measurement Enable LME is one of the bidirectional signals that make up the Intermodule Bus IMB W
200. ngdom GREECE Hewlett Packard A E 178 Kifissias Avenue 6th Floor Halandri ATHENS Greece Tel 6471543 6471673 6472971 Telex 221 286 HPHLGR A C CM E M P Kostas Karaynnis S A 8 Omirou Street ATHENS 133 Tel 32 30 303 32 37 371 Telex 215962 RKAR GR A C CM E Intelect Div 209 Mesogion 11525 ATHENS Tel 6474481 2 Telex 216286 Haril Company 38 Mihalakopoulou ATHENS 612 Tel 7236071 Telex 218767 Hellamco P O Box 87528 18507 PIRAEUS Tel 4827049 Telex 241441 A GUATEMALA IPESA Avenida Reforma 3 48 Zona 9 GUATEMALA CITY Tel 316627 314786 Telex 3055765 IPESA GU A C CM E M P HONG KONG Hewlett Packard Hong Kong Ltd G P O Box 795 5th Floor Sun Hung Kai Centre 30 Harbour Road HONG KONG Tel 5 8323211 Telex 66678 HEWPA HX Cable HEWPACK Hong Kong ECP CET Ltd 10th Floor Hua Asia Bldg 64 66 Gloulester Road HONG KONG Tel 5 200922 Telex 85148 CET HX CM Schmidt amp Co Hong Kong Ltd 18th Floor Great Eagle Centre 23 Harbour Road HONG KONG Tel 5 8330222 Telex 74766 SCHMC HX AM ICELAND Hewlett Packard Iceland Hoefdabakka 9 110 Reykjavik Tel 1 67 1000 A C CM E M P INDIA Computer products are sold through Blue Star Ltd All computer repairs and maintenance service is done through Computer Maintenance Corp Blue Star Ltd Sabri Complex 2nd Floor 24 Residency Rd BANGALORE 560 025 Tel 55660 57888 1 Tele
201. nita 45060 GUADALAJARA Jalisco Tel 316630 314600 Telex 0684 186 ECOME MEXICO Cont d Microcomputadoras Hewlett Packard S A Monti Pelvoux 115 LOS LOMAS Mexico D F Tel 520 9127 Hewlett Packard Mexicana S A de C V Av Periferico Sur No 6501 Tepepan Xochimilco 16020 MEXICO D F Tel 6 76 46 00 Telex 17 74 507 HEWPACK MEX A C CM E M P Hewlett Packard De Mexico Polanco Avenida Ejercito Nacional 579 2day3er piso Colonia Granada 11560 MEXICO D F Tel 254 4433 Hewlett Packard De Mexico S A de C V Czda del Valle 409 Ote 4th Piso Colonia del Valle Municipio de Garza Garcia 66220 MONTERREY Nuevo Le n Tel 78 42 41 Telex 038 410 MOROCCO Etablissement Hubert Dolbeau amp Fils 81 rue Karatchi B P 11133 CASABLANCA Tel 3041 82 3068 38 Telex 23051 22822 E Gerep 2 rue Agadir Boite Postale 156 CASABLANCA 01 Tel 272093 272095 Telex 23 739 Sema Maroc Dept Seric 6 rue Lapebie CASABLANCA Tel 260980 Telex 21641 CP NETHERLANDS Hewlett Packard Nederland B V Startbaan 16 1187 XR AMSTELVEEN P O Box 667 NL1180 AR AMSTELVEEN Tel 020 547 6911 Telex 13 216 HEPA NL A C CM E M P Hewlett Packard Nederland B V Bongerd 2 NL 2906VK CAPELLE A D WSSEL P O Box 41 NL 2900AA CAPELLE A D WSSEL Tel 10 51 64 44 Telex 21261 HEPAC NL CE Hewlett Packard Nederland B V Pastoor Petersstraat 134 136 NL 5612 LV EINDHOVEN
202. numbered slot and Acquisition Boards in the higher slots is due to the system assigning labels Pod 1 Pod 2 etc to the 20 bit groups of information stored in the Acquisition board s SAC 2 1 Model 64621A Installation memory This is important when connecting the Pods to the User s System and in Preprocessor applications the software assumes that the information on Pod 1 is the Addresses from the User s System 2 16 When connecting the Pod Cables to the State Analysis Boards the Pods should be labeled as indicated in Figures 2 1 or 2 2 i e Pod 1 to Pod 1 etc 2 17 Up to three Acquisition Boards may be installed with one Control Board forming one State Analysis Subsystem 2 18 The State Analysis Subsystem configuration must not interfere with the Emulation Subsystem if any in the highest numbered card slots some Mainframes may not have room for both a State Analysis Subsystem and an Emulation Subsystem 2 19 SYNCHRONOUS EXPANSION BUS SEB 2 20 The State Control and Acquisition Boards must be grouped together to allow the Synchronous Expansion Bus SEB cable W3 to connect the Control Board to the Acquisition Boards J2 See Figures 2 1 and 2 2 2 21 INTER MODULE BUS IMB 2 22 Some systems may contain more than one State Analysis Subsystem or a combina tion of a State Analyzer and another type of Analysis Subsystem If this is the case the second State Subsystem is installed in the same manner as
203. oad CLEVELAND OH 44130 Tel 216 243 7300 A C CM E M Hewlett Packard Co 9080 Springboro Pike MIAMISBURG OH 45342 Tel 513 433 2223 A C CM E M Hewlett Packard Co One Maritime Plaza 5th Floor 720 Water Street TOLEDO OH 43604 Tel 419 242 2200 C Hewlett Packard Co 675 Brooksedge Blvd WESTERVILLE OH 43081 Tel 614 891 3344 C CME Oklahoma Hewlett Packard Co 3525 N W 56th St Suite C 100 OKLAHOMA CITY OK 73112 Tel 405 946 9499 Hewlett Packard Co 3840 103rd E Ave 100 TULSA OK 74146 Tel 918 665 3300 SEPT 1985 Hewlett Packard 9255 S W Pioneer Court WILSONVILLE OR 97070 Tel 503 682 8000 Pennsylvania Hewlett Packard Co 50 Dorchester Rd HARRISBURG PA 17112 Tel 717 657 5900 Hewlett Packard Co 111 Zeta Drive PITTSBURGH PA 15238 Tel 412 782 0400 Hewlett Packard Co 2750 Monroe Boulevard VALLEY FORGE PA 19482 Tel 215 666 9000 A C CM E M South Carolina Hewlett Packard Co Brookside Park Suite 122 1 Harbison Way COLUMBIA SC 29210 Tel 803 732 0400 C M Hewlett Packard Co 555 N Pleasantburg Dr Suite 107 GREENVILLE SC 29607 Tel 803 232 8002 C Tennessee Hewlett Packard Co One Energy Centr 200 Pellissippi Pkwy KNOXVILLE TN 37932 Tel 615 966 4747 A C M Hewlett Packard Co 3070 Directors Row Directors Square MEMPHIS TN 38131 Tel 9
204. ot tested Drive HE TE SE TR Receive Porti nulses DCLIk Ponrt2 Pon tl ME TE SE TRO Figure 4 20 Intermodule Bus SAC h 30 Model 64621A Performance Verification 4 75 TEST 9 STROBE GENERATOR CALIBRATION 4 76 This test is a stimulus to the Control Board only It is used in Section V for calibration of the Strobe Generator See Section V 4 77 TEST 10 THRESHOLD CIRCUIT CALIBRATION 4 78 This test is a stimulus to the Control Board only It is used in Section V for calibration of the Threshold Circuit See Section V 4 79 TEST 11 PREPROCESSOR INTRFC STIMULUS LOOP H 4 80 Purpose to verify that the Control Board can write to the Preprocessor No data is read from the Preprocessor 4 81 How When LMS is activated the address and data information on the CPU bus is loaded into U26 and U53 and read at the outputs of U26 and U53 At the same time the control signals are read at the outputs of U129 4 82 Results All results of this test are read at the Address Latch U118 or the CPU Data Buffer U121 483 Loop H Signature Paths 026 0118 0127 053 01 0123 065 0116 096 0119 0127 1120 099 1129 4 84 TEST 12 REAR PANEL PORT STIMULUS LOOP 1 485 Purpose to verify that the control board writes to PORT1 and PORT2 on the rear panel of the Mainframe 486 How there are two sections to this test 1 The PHALT signal is activated and sent to BNC2 when the control signal PWRUN goes high Thi
205. ption Low Read Memory Address Counter Register when low LRMAC enables the Trace Memory Address Counter Read Register allowing the value of the Trace Count Status Memory Address Counters to be read over the CPU s Data Bus Low Read Sequence Register when low LRSQRG enables the Sequence Read Register allowing the value of the Sequence State Latch Counters 580 to be read over the CPU s Data Bus Low Read Strobe developed in the Mainframe Interface from LWRTB and LIDB LSTB and LSEL When low LRSTB allows information to be placed on the CPU Data Bus Low Read Status when low LRSTS enables the Analysis Status Buffer al lowing the states of eight different signals to be read over the CPU s Data Bus Low Reset Sequence State Counter when low LRSTSS resets the Sequence State Counter to zero The Counters cannot begin counting until LRSTSS returns to a high state LRSTSS is developed from the CPU s Address Bus and other control lines from the CPU Low Read Trace Data Register when low LRTDR enables the Trace Data Read Register allowing the contents of the Trace Counter Status Memories CD0 7 to be read over the CPU s Data Bus Low Read Trace Point Register when low LRTPRG enables the Trace Point Register allowing the value of the Trace Count Status Memory Address Counters to be read over the CPU s Data Bus Low Run master enable for the Control Board generated by the CPU When low LRUN enables
206. r STATUS IO 8 8 106 The table shows 4 resources used by trigger 2 by store and 2 by count Because of the DATA lt gt 0 the second specification line for trigger required 2 resources Internally this is done by DME disjoint minterm event gating which requires one resource to find DATA 0 and a second resource to invert it Pipeline Strobe HPLS latches the count store and trigger resources and they are applied to Resource Gating 8 107 Resource Gating The count storage and trigger resources are gated with the Sequencer IMB and Analyzer Enable and output as Overview Count Qualify HOCQ Store Flag LSFLG and Trigger NTR The 58 bit shift register uses 18 bits Storage Function Trigger Function Analyzer Enable Function Initialize Sequencer enables to specify which inputs to Resource Gating will be looked at The default state for these bits cause the Analysis Controller to count everything store al ways and trigger on anything 8 108 Write Qualification Write Qualify Gating determines which trace data will be written into the Trace Pod Data Memories Low Strobe Enable LSE is directly produced by Storage Qualify Gating and can be modified by the Trace Point Latch and the Measurement Complete Latch The Trace Point Latch is set by the first trigger NTR then it enables the Post Trace Point Counter to count each time data is SAC 8 20 Model 64621A Service stored in the Trace Memories The Post Trace
207. re Path for Sequence Addressing and Functions U1 036 U38 sac 4 24 Model 64621A Performance Verification 4 50 TEST 5 STATE COUNT LOOP 4 51 Purpose verify operation of the Trace State Time Counter U112 in the state count mode 4 52 How The Counter temporarily stores data in location 00 Hex of the Trace Count Status Memory That location is read at the Trace Data Read Register 4 53 One difficulity with this test is that it requires the Trace Count Status Memory to work before it is tested Test 6 In particular the address used to write data to the RAMs is not sampled in Test 5 because RAM outputs are sampled at read time If Test 5 fails and only RAM outputs are bad test the Trace Count Status Memory Address Selector and the Memory Address Counter using signature analysis or run Test 6 and take signatures in both the main loop and the write loop 4 54 The Counter uses the following controls HQWRT which resets the Counter PINC which increments the count states LSTATE which puts the Counter in the count states mode HCTST which selects between a 20 bit mode and two 10 bit modes HCQ which en ables the Counter and 25MHz which is used internally by the Counter 4 55 Results all results for this test are read by the Trace Data Read Register That register receives data from the memory bank selected by the signals LTCSMSO 3 Low Trace Count Status Memory Select U70 U73 and U90 are not used by this test 10 MHz
208. re is suspected use Test 1 because it exercises all memory locations 4 43 With the Sequence State Latch Counter in the count load mode Transition Memories and the Occurrence Memories are loaded The Analysis Controller and the Sequence State Latch Counter are then put into the run mode and strobes are generated via PPVSTB The events that follow are complex and only an overview is given here The Sequence State Latch Counter is clocked by PPLS pipeline strobe which is enabled by the Analysis Controller at U5 The Sequence State is the output of the Sequence State Latch Counter and is read as TSSO 7 Trace Sequence State by the Sequence Read Register 4 44 Next the Sequence Occurrence Counter and Counter Memories are tested Counter is clocked by PSOCINC PSOCINC in the run mode is enabled by the Analysis Controller at U5 The only output of the Occurrence Counter is Occurrence Carry LOCCRY it is latched by the Pipeline Latch Counter and read as TSS4 using the Sequence Read Register RAM address in Figure 4 16 refers to the output of U42 it is also latched by the Pipeline Latch Counter and then read 555 by the Sequence Read Register 4 45 Now the plot thickens The Trace Count Status Memory Address Counter MAC and Trace Point bit LTRCP are needed to test the outputs of memories U36 and U38 which are processed by the Analysis Controller The MAC is cleared incremented by HQWRITE and read by the Trace MAC
209. rmat specification Use of symbols in Trace specification Trace list uses symbols to present symbolic display Each label may have its own or use another symbol map Probing Versatility General Purpose Probes Models 64635A and 64636A General Purpose Preprocessor with dedicated interfaces See Model 64650A General Purpose Preprocessor Manual 1 6 INSTRUMENTS COVERED BY THIS MANUAL 1 7 Attached to the instrument or printed on the printed circuit board is the repair number The repair number is in the form 000040000 It is in two parts the first four digits and the letter are the repair prefix and the last five are the suffix The prefix is the same for all identical instruments The suffix however is assigned sequentially and is different for each instrument The contents of this manual apply to instruments with the repair number prefix es listed under REPAIR NUMBERS on the title page 1 8 An instrument manufactured after the printing of this manual may have a repair number prefix that is not listed on the title page This unlisted repair number prefix indicates that the instrument is different from those described in this manual The manual for this newer instrument is accompanied by a Manual Changes supplement This supplement contains change information that explains how to adapt the manual for the newer instrument 1 9 In addition to change information the supplement contains information for cor recting errors in the manu
210. rue 0000000000000000 False 0000000000000000 RAM Address 0000 Memory Address 00000000 Trace Point Pass Sequence Addressing Pass Functions 0000 CHSTR LSTE LSSE LSME Figure 4 16 Sequencer 4 48 Figure 4 16 Interpretation State Register Count 00000000 eight bit Sequence State output by U17 and U18 when clocked by NINCSS Load 00000000 eight bit Sequence State latched by U17 and 018 when HLD is not asserted Occur Counter Bits True 0000000000000000 No Carry Load False 0000000000000000 sixteen bits loaded from U58 U61 into U78 U79 U81 U82 then unloaded through each pin 4 and gated by U80 and 016 to become LOCCRY RAM Address 0000 four bit input to 058 061 on lines A0 A3 Memory Address 00000000 Trace Point Pass outputs of U104 and U105 read at U68 Trace Point is the output of 098 read at U122 Sequence Addressing Pass bits 0 of U36 tested by output at pin 4 LSSQ Functions 0000 HSTR LSTE LSSE LSME 01 input pins 2 37 36 38 tested at Ul output pins 4 35 appears on failure of c arry bit on U78 pin 4 only 4 49 Loop D Signature Path for State Register 0121 U89 083 U84 U17 018 185 U52 0101 SAC 4 23 Model 64621A Performance Verification Loop D Signature Path for Occurrence Counter U16 U78 U82 058 061 Uh2 U62 U6h U17 018 Note go to Test 1 for test without loopback Loop D Signature Path for Memory Address U121 0122 U68 U98 010 0105 U5 Ul Loop D Signatu
211. s NOTE There are many TTL ECL and Translators in this product A bad TIL level can be mistaken for a good ECL level Please pay close attention to the levels when troubleshooting using the schematics Also a bad TTL input level can cause the entire TTL chip to output bad information 4 20 Each automatic test is now described and a signature analysis path provided Each SA path works its way from the test output back towards the inputs To run a particular test press opt_test then RETURN Press SLOT of the State Control board then RETURN Finally press run SLOT test test of first failing test repeat then RETURN Examples of valid commands while operating the State Analysis Performance verification are as follows run 1 test 3 repeat RETURN This runs test 3 repeatedly on the board in slot 1 and allows signatures to be taken b display 2 test 9 RETURN This displays the results of test 9 for the board in slot 2 It does not cause test 9 to run Various other commands are prompted by the softkeys e g stop stops the test in progress list file name writes the display to the designated file end causes the program to leave State Analysis PV and go to option test PV 4 21 When a bit pattern is given e g data 00000100 the 1 indicates that bit 2 has failed In all cases a 0 indicates pass and a 1 indicates failure the msb is to the extreme left all patterns start with bit O unless otherw
212. s Milles Cedex AIX EN PROVENCE Tel 42 59 41 02 Telex 410770F A C E M P Hewlett Packard France 64 rue Marchand Saillant 61000 ALENCON Tel 33 29 04 42 Hewlett Packard France 28 rue de la Republique Boite Postale 503 25026 BESANCON Cedex Tel 81 83 16 22 Telex 361157 Hewlett Packard France Chemin des Mouilles Boite Postale 162 69130 ECULLY Cedex Lyon Tel 78 833 81 25 Telex 310617F Hewlett Packard France Parc d activit s du Bois Briard 2 avenue du Lac 91040 EVRY Cedex Tel 6 077 96 60 Telex 692315F E Hewlett Packard France 5 avenue Raymond Chanas 38320 EYBENS Grenoble Tel 76 62 57 98 Telex 980124 HP GRENOB EYBE Hewlett Packard France Rue Fernand Forest 7 Kergaradec 29239 GOUESNOU Tel 98 41 87 90 Hewlett Packard France Centre d affaires Paris Nord Batiment Amp re Rue de la Commune de Paris Boite Postale 300 93153 LE BLANC MESNIL Tel 1 865 44 52 Telex 211032F Hewlett Packard France Parc d activit s Cadera Quartier Jean Mermoz Avenue du Pr sident JF Kennedy F 33700 M RIGNAC Bordeaux Tel 56 34 00 84 Telex 550105F CEM Hewlett Packard France Immueble Les 3 B Nouveau chemin de la Garde ZAC du Bois Briand 44085 NANTES Cedex Tel 40 50 32 22 Telex 711085F crt Hewlett Packard France 125 rue du Faubourg Bannier 45000 ORLEANS Tel 38 68 01 63 FRANCE Cont d Hewlett Packard France
213. s bus generated by the CPU and used to address various devices in the system Only bits 0 13 are used in this model Low Address Buffered 0 13 same LA0 13 with additional buffering LAB0 13 may also be latched from the Address Bus Low Bus Clear same as LCLR except buffered LBCLR is sent to the 20 and 40 Channel Data Acquisition Boards to clear various counters and registers Low Bus Memory Address Counter Select developed in the Strobe Generator Used in the 20 and 40 Channel Data Acquisition Boards When low LBMACS al lows the Memory Address Counters on the ACQ Boards to address the Trace Pod Data Memories When high the CPU can address the Memories over the CPU Address Bus Low Bus Overview Enable developed from HOVS LBOVEN is used only on the 20 Channel Data Acquisition Board When low LBOVEN allows the Overview section to look for its trigger events and enables overview storage Low Bus Resource Pattern 0 7 eight signals coming from the Data Acquisition Boards When low indicates to the Analysis Controller that combinations of Trigger Storage and Count information have been detected Low Bus Sequence Pattern 0 3 four signals coming from the Data Acquisition Boards When low they indicate to the Sequencer that the Data Acquisition Boards have found the Sequence State s requested by the user Low Clock 0 7 differential 7 clock signals or qualifier bits from the user s equipment The ei
214. s latches LAB1 Low Address Bus 1 into the Port Latches U97 2 The PSTIM signal is activated and sent to PORT1 when NTRIG Negative Trigger from Ul goes low This occurrs each time the trigger event is encountered 4 87 Loop I Signature Path Ul U97 U123 U116 1126 SAC 4 31 Model 64621A Performance Verification Board 64621 66503 Test 1 Loop A 8U24 MODE EDGES THRESHOLDS CONNECTIONS Normal Clock Positive Data High ST SP Start TP19 Start Positive Data Low Qual Stop TP19 Stop Negative Clock Clock U99 pin 3 Ae ST SP QL TTL Ground GND TP levels are TTL except where noted U 1 7 15 0 18 2 62FC ECL U 21 10 0000 0 1 30 15 U 18 3 6546 ECL TOTLZ 1 U 1 36 15 U 18 5 high ECL U 21 11 0000 ECL U 1 37 4778 ECL U 18 6 1492 TOTLZ 1 U 1 38 4778 ECL 18 7 TFCH U 21 13 0000 U 1 39 high 18 9 9946 ECL TOTLZ 1 U 1 40 4778 U 18 10 082C 21 14 802 ECL U 18 11 ECL TOTLZ 1 U 18 12 22F4 ECL U 21 15 0000 ECL U 6 3 7260 ECL 18 13 PP34 U 6 6 UH9h ECL U 18 14 762F ECL U 6 0000 ECL U 18 15 HO2H ECL U 22 2 0000 ECL TOTLZ 1 U 22 3 8U24 ECL U 6 9 8 9 ECL U 22 4 0000 ECL U 6 12 0000 ECL U 19 9 1492 ECL TOTLZ 1 U 6 13 8HF9 ECL U 19 11 080P ECL U 22 6 0000 ECL U 19 12 low ECL TOTLZ 1 U 19 14 PCHO ECL U 22 7 0000 ECL U 8 1 UF8C U 1
215. sters The shift register outputs set up the channel to be edge sensitive or level sensi tive but not both at once The level sensitive inputs are called clock qualifiers and are wire ANDed internally Any combination of inputs can be made edge sensi tive and any input can trigger on a positive edge a negative edge or both edges 8 50 The eight clock channel inputs are differential at approximately ECL levels and the master clock output HMCLK is ECL The two shift registers and their clock are TTL levels 8 51 Clock Term Generator Timing 8 52 Inputs used as clock qualifiers have a set up time of 20 nS and hold time of 0 nS Inputs used as clocks must have a pulse width of 20 nS minimum Due to system restrictions the master clock rate is 10 MHz maximum Propagation delay is ap proximately 8 nS from clock input to master clock output 8 53 Clock Term Generator Block Diagram 8 54 Prior to execution of a trace the Edge Detect Register and Level Select Register are loaded from lines DBO and DB1 using Positive Write Clock PWCLK Two bits per clock channel control the channel s Level Select Gate The channel can be made don t care by programming both bits high The outputs of all eight Level Select Gates are ANDed so that all qualifiers must be true before the data input to the Edge Detect filp flops go true 8 55 Two more programmable bits per clock channel are needed to control which clock edge if any will produce a Hi
216. the changes to the manual that are listed for that repair number prefix When making changes list ed in table 7 1 make the change with the highest number first Example if backdating changes 1 2 and 3 are required for your repair number do change 3 first then change 2 and finally change 1 7 5 If the repair number of your instrument is not listed either on the title page or in table 7 1 refer to an enclosed MANUAL CHANGES sheet for updating information Also if a MANUAL CHANGES sheet is supplied make all indicated ERRATA corrections Table 7 1 Manual Changes PREFIX MAKE CHANGES 2144A 1 and 2 2246A 2 CHANGE 1 Section VI Page SAC 6 4 Table 6 2 Replaceable Parts List Change Al part number from 64621 66502 to 64621 66501 Check digit from 6 to 5 Page SAC 6 5 Table 6 2 Replaceable Parts List Change A1R2 R3 R9 R10 R29 31 R36 41 R43 47 R51 R53 part numbers from 0698 6612 to 0757 0283 20 places Check digit from 1 to 6 20 places Tolerance from 0 1 to 1 20 places Mfr Code from 28480 to 24546 Mfr Part Number from 0698 6612 to Ch 1 8 TO 2001 F Delete last line 1 18 0365 0535 0 Terminal Test Point PCB 00000 Order by Description Change 1 2 QTY from 12 to 11 SAC T 1 Model 64621A Manual Backdating CHANGE 2 Section VI Page SAC 6 4 Table 6 2 Replaceable Parts List Change Al to read Al 64621 66502 6 1 10MHZ STATE ANALYSIS CONTROL BOARD 28480 64621 66502 Delete A1C68
217. the first one If the second Analyzer is not a State Analyzer refer to that Analyzer s Service Manual for installation information The Inter Module Bus IMB Cable W4 is in stalled accross the top of the boards J1 See Figures 2 1 and 2 2 SAC 2 2 Model 64621A Installation CARD CAGE SLOT IMB SEB NUMBER CABLE CABLE W4 W3 N 3 J1 64623A IMB 20 CH ACQ DATA CABLE W2 POD 1 J3 N 2 64622A 40 CH ACQ DATA CABLE W2 DATA CABLE W2 MAXIMUM POD 2 POD 3 FOUR J3 A J4 B BOARDS N 1 64622A 40 CH ACQ DATA CABLE W2 DATA CABLE W2 POD 4 POD 5 J3 A 4 64621A CONTROL CLOCK CABLE W1 CLOCK POD J3 TOP OR FRONT OF CARDCAGE FOR PREPROCESSORS POD 1 ADDRESS POD 2 DATA POD 5 DATA Figure 2 1 State Subsystem With 20 Channel Acquisition SAC 2 3 Model 64621A Installation CARD CAGE SLOT CABLE CABLE WA W3 N 3 J1 J2 64622A IMB SEB 40 CH ACQ DATA CABLE W2 DATA CABLE W2 POD 1 POD 2 J3XA J4 B N 2 64622A 40 CH ACQ DATA CABLE W2 DATA CABLE W2 POD 3 POD 4 MAXIMUM J3XA J4 B FOUR BOARDS N 64622A 40 CH ACQ DATA CABLE W2 DATA CABLE W2 POD 5 POD 6 J3XA J4 B N 64621A CONTROL CLOCK CABLE W1 CLOCK POD TOP OR FRONT OF CARDCAGE J3 FOR PREPROCESSORS POD 1 ADDRESS POD 2 DATA POD 6 DATA Figure 2 2 State Subsystem No 20 Channel Acquisition SAC 2 4 Model 64621A Installation 2 23 STORAGE AND SHIPMENT 2 24 ENVIRON
218. the rising edge of channel B as indicated in the follow ing diagram CH A TP2 A 95 5 el CH TP3 k f Connect channel A to TP3 Pipeline Strobe and trigger on channel A Connect channel B to TP10 Overview Strobe Using adjustment T2 R7 adjust the falling edge of channel B as indicated in the following diagram CH A TP3 n 18s U CH TP10 e g Connect channel B to TP5 Qualified Write Strobe Channel A remains on TP3 and is the trigger for the scope Using adjustment T3 R6 adjust the rising edge of channel B as indicated in the following diagram ST LULU as 5 IL GENE SAC 5 2 Model 64621A Adjustments h Connect channel A and B to TP5 Qualified Write Strobe Trigger on channel A Using adjustment Th R5 adjust the pulse width as indicated in the 1 lowing diagram CH A amp B TPS ci Se NEM D 48ns n i Connect channel B to TP9 data Valid Strobe Channel A remains on TP5 and is also the trigger Using adjustment T5 R4 adjust the falling edge of channel B as indicated in the following diagram CH A 5 s 05 TP9 j Pressing stop end RETURN end will end the Strobe Generator Calibration Performance Verification k This completes the Strobe Generator Calibration 5 12 THRESHOLD
219. tion from the Sequence Pipeline Latch Counters into the Sequence Read Register The information in the Register is placed on the CPU Data Bus when LRSQRG goes low Positive Stimulus PSTIM goes from a low to a high state when a Trigger Event or a Sequence Event occurs if enabled by the user PSTIM is used in the Preprocessor if enabled and also becomes PORT1 Positive Write Analysis Controller a CPU controlled signal developed in the Write Decoders When the Analysis Controller is in the load mode LLD low PWAC writes LDBO into the Controller Positive Write Clock a CPU controlled signal developed in the Write Decoders PWCLK writes LDBO and LDBl into the Clock Term Generator Positive Write Load a CPU controlled signal developed in the Write Decoders When going from a low state to a high state PWLOAD latches LABO into the Load Latch asserting or negating HLD and LLD Positive Write Run a CPU controlled signal developed in the Write Decoders When going from a low state to a high state PWRUN latches LABO into the Run Latch producing LRUN and latches LAB1 into the Port Latches negating LTP and LMC Trace Sequence State 0 7 outputs of the Sequence State Latch Counters used in either the load mode or the run mode 550 7 represent the present sequence state Voltage Threshold 1 2 a voltage that is programmable by the user and sent to the Clock Probe as a reference voltage for the Comparators SAC 8 39 Mo
220. to the Trace Pod Data Latch on the Data Acquisition Boards Negative Bus State Recognition Strobe a differential strobe PBSRS developed in the Strobe Generator and sent to the Data Acquisition Boards At the beginning of a data acquisition cycle NBSRS goes from a high state to a low state NBSRS is used to latch user information into the State Recognition Latches Counters Negative Data Strobe a differential signal PDSTB developed in the Strobe Generator NDSTB and PDSTB are used to develop HDVLD see HDVLD Negative Interface Halt a differential signal PIHALT sent to the Preprocessor that can be used to halt the user s system Negative Increment Sequence State when NINCSS goes from a high to a low state the Sequence State Latch Counter will be incremented one state when in the count mode NINCSS is developed by the CPU and is wire ORed with PPLS Negative Interface Stimulus a differential signal PISTIM sent to the Preprocessor NISTIM is developed from PSTIM when enabled by HENSTIM NISTIM goes from a high to a low state when a Trigger Event or Sequence Event occurs if enabled by the user Negative Memory Address Counter Register Strobe a differential signal PMACRS developed in the Strobe Generator NMACRS is used to latch infor mation from the Trace Count Status Memory Address Counters into the Trace Memory Address Counter Read Register The information in the Register is placed on the CPU Data Bus when LR
221. torage 256 locations Overview Model 64623A only 4096 locations Sequence Multiple function control with windows and qualifiers occurrence and restart Clocks 8 ORed clocks and or qualifiers Interactive Read of Trace Data up to 4 75 MHz qualified clock rate Run Status Waiting for trigger Trace in process Overview in process Slow clock Measurement complete Overview Functions Model 64623A only Sequencer Windowed Controlled 3 Modes State Data Time Count start to stop 8 0 hrs max time within 40 ns or 0 1 Event Count start to stop count by one from 0 to 611 670 max count 750 10e 9 3 Displays Overview Histogram Overview List Overview Graph IMB Functions interconnection with other modules Master Enable drive receive Storage Enable drive receive Trigger Enable drive receive Trigger drive receive Delay Clock drive only SAC 1 2 Model 64621A General Information Table 1 2 Supplemental Characteristics Cont d 20 Bit Ranging Model 64623A only Applicable to trace or overview functions Four trace ranges or up to 15 overview ranges Range on a contiguous subset of the 20 bits right justified Trace Count Measurement Windowing of time or state count Stored State to Stored State Time Count 8 0 hrs max time within 40 ns or 0 1 Event Count count by one from 0 to 611 670 max count 750 X 10e 9 Symbol Entry and Output Definition of symbol maps in fo
222. unter TSS0 7 the 20 outputs of the Trace State Time Counter CNTO 19 and three control signals High Overview Trigger Flag Buffered HCQB High Count Qualify Buffered and LSFLGB Low Store Flag Buffered The CPU needs these con trol signals to interpret the data from the state system 8 33 The final section is the five registers that hold the information to be read onto the CPU Data Bus These five registers are enabled by control signals developed in the CPU Read Decoder on the Control Board from the CPU Address Bus sig nals The five signals are LRSQRG Low Read Sequence Register This active low signal allows the output of the Sequence State Latch Counters TSS 0 7 to be read onto the CPU Data Bus LRTDR Low Read Trace Data Register When low LRTDR enables the Trace Point Register allowing the value of the Trace Count Status Memory to be read by the CPU LRTPRG Low Read Trace Point Register This active low signal allows the Trace Point address to be read over the CPU Data Bus The Trace Point address was latched by LTRCP when the trace point was found LRSTS Low Read Status When low LRSTS enables the Analysis Status Buffer to allow eight different signals to be read by the CPU SAC 8 4 DATA PROBE CLOCK PROBE Model 64621A Service OVERVIEW STATE TIME COUNTER um 2 LEV 03 HOLDING REGISTER OVERVIEW i EVENT LOVE 0 3 DATA HCE HTIME LSTATE
223. x 0845 430 Cable BLUESTAR AC CME Blue Star Ltd Band Box House Prabhadevi BOMBAY 400 025 Tel 4933101 4933222 Telex 011 71051 Cable BLUESTAR Blue Star Ltd Sahas 414 2 Vir Savarkar Marg Prabhadevi BOMBAY 400 025 Tel 422 6155 422 6556 Telex 011 71193 BSSS IN Cable FROSTBLUE A C CM E M Blue Star Ltd Kalyan 19 Vishwas Colony Alkapuri BORODA 390 005 Tel 65235 65236 Cable BLUE STAR A Blue Star Ltd 7 Hare Street CALCUTTA 700 001 Tel 230131 230132 Telex 021 7655 Cable BLUESTAR Blue Star Ltd 133 Kodambakkam High Road MADRAS 600 034 Tel 472056 470238 Telex 041 379 Cable BLUESTAR AM Blue Star Ltd 13 Community Center New Friends Colony NEW DELHI 110 065 Tel 633773 634473 Telex 031 61120 Cable BLUEFROST AC CMEM UJ Blue Star Ltd 15 16 C Wellesley Rd PUNE 411011 Tel 22775 Cable BLUE STAR A Blue Star Ltd 2 2 47 1108 Bolarum Rd SECUNDERABAD 500 003 Tel 72057 72058 Telex 0155645 Cable BLUEFROST AE Blue Star Ltd T C 7 603 Poornima Maruthunkuzhi TRIVANDRUM 695 013 Tel 65799 65820 Telex 0884 259 Cable BLUESTAR E Computer Maintenance Corporation Ltd 115 Sarojini Devi Road SECUNDERABAD 500 003 Tel 310 184 345 774 Telex 031 2960 ct INDONESIA BERCA Indonesia P T P O Box 496 Jkt Abdul 62 JAKARTA Tel 21 373009 Telex 46748 BERSAL IA Cable BERSAL JAKARTA BERCA Indonesia
224. x Counter Pase Figure 4 18 Trace Memory SAC 4 27 Model 64621A Performance Verification 4 65 Figure 4 18 Interpretation Address Counter 00000000 outputs of U10h and U105 read at U68 Trace Point Reg 00000000 U67 Trace Point Wrap 00 U98 pin 7 and U103 pin 9 respectively Store seq state 00000000 mostly 1 s 000000000000000000000000000000 mostly 0 s 000000000000000000000000000000 32 bit memory read at U69 Bit pattern 531 b28 1 71 b27 b2h 191 b23 b20 072 b19 b16 192 b15 b12 073 11 b8 U93 bh UTO b3 bO U90 Address Test 00000000 000000000000000000000000000000 indirect test of RAM address bits A0 A7 Index Counter Pass strobe inputs to Ul cause counter to overflow at Ul pin 17 The Index Counter is shown as the Post Trace Point Counter on the Block Diagram 4 66 Loop F Signature Path U121 U122 U67 U69 U98 U103 U105 U86 U88 Loop signature Path for Trace Count Status Memory U112 11 SAC 4 28 Model 64621A Performance Verification 4 67 TEST 7 OTHER COUNTER TESTS 4 68 Purpose verify operation of prescale function and count time mode of Trace State Time Counter 4 69 How The Counter is incremented by the 25 MHz clock and the count is stored in the Trace Count Status Memory location 00 Hex 4 70 Results Signature Analyis is impractical because the interval is greater than 9 seconds The only untested signals are HTIMS and LSTATE HTIMS
225. y BOREHAMWOOD Herts WD6 1SG Tel 01 207 5000 Telex 8952716 Hewlett Packard Ltd Oakfield House Oakfield Grove Clifton BRISTOL Avon BS8 2BN Tel 0272 736806 Telex 444302 CEP Hewlett Packard Ltd Bridewell House 9 Bridewell Place LONDON EC4V 6BS Tel 01 583 6565 Telex 298163 CP Hewlett Packard Ltd Pontefract Road NORMANTON West Yorkshire WF6 1RN Tel 0924 895566 Telex 557355 CP Hewlett Packard Ltd The Quadrangle 106 118 Station Road REDHILL Surrey RH1 1PS Tel 0737 68655 Telex 947234 CEP Hewlett Packard Ltd Avon House 435 Stratford Road Shirley SOLIHULL West Midlands B90 4BL Tel 021 745 8800 Telex 339105 CEP Hewlett Packard Ltd West End House 41 High Street West End SOUTHAMPTON Hampshire 503 300 0703 476767 Telex 477138 CP Hewlett Packard Ltd Harmon House No 1 George Street UXBRIDGE Middlesex UX8 1YH Tel 895 720 20 Telex 893134 5 C CM E M P Hewlett Packard Ltd King Street Lane Winnersh WOKINGHAM Berkshire RG11 Tel 0734 784774 Telex 847178 ACEMP IRELAND NORTHERN IRELAND Hewlett Packard Ireland Ltd Carrickfergus Industrial Centre 75 Belfast Road Carrickfergus BELFAST BT38 8PH Tel 09603 67333 Telex 747626 CE SCOTLAND Hewlett Packard Ltd 8 Woodside Place GLASGOW G3 7QF Tel 041 332 6232 Telex 779615 CE Hewlett Packard Ltd SOUTH QUEENSFERRY West Lothian EH30 9TG Tel 031 331 1188 Telex 726
226. zer Subsystem when a series of states or events have occurred in the system under test The Sequencer hardware contains feedback circuitry which combines the sequence state with incoming data to form the next sequence state The Sequencer is a good example of a synchronous state machine 8 79 Functions 8 80 The Sequencer can enable and disable all functions of the State Analysis Subsystem See Figure 8 6 It can also cause the State Analyzer to trigger store and drive the IMB master enable It must be loaded before execution of a trace or overview To operate the Sequencer the operator must specify a series of terms and or windows The terms usually represent states e g an address or a data value and the windows are an enable disable pair of terms Then the operator specifies the order in which these terms must occur how many times each must occur occurrence and whether the next term must occur immediately or eventually The operator must specify which sequence term will enable a function and which term will disable a function The operator may also specify which terms will restart the sequencer Further details are available in the operator s manual LOAD COUNT ENABLE DISABLE OVERVIEW FUNCTION COUNT FUNCTION STORE FUNCTION TRIGGER FUNCTION OVERVIEW FUNCTION MASTER ENABLE FUNCTION Figure 8 6 Sequencer Functions SAC 8 15 Model 64621A Service 8 81 Sequencer Specif

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