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1. Technical Reference Local PCI Devices User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board The following table shows the on board PCI devices and their location within the PCI configuration space These devices consist of the Ethernet controllers and several devices within the i915GM chip set O Fea JE O gcc Fee CH Fea OC Fee EC JE O JE gt NM LA de 5 6 27 26 26 26 26 29 29 29 29 29 30 30 30 31 31 31 31 0x8086 0x8086 0x8086 0x8086 0x8086 0x8086 0x8086 0x8086 0x8086 0x8086 0x8086 0x8086 0x8086 0x8086 0x8086 0x8086 0x8086 0x8086 0x8086 0x8086 0x8086 0x8086 0x8086 Ox10B5 0x2590 0x2592 0x2792 0x2668 0x2660 0x2662 0x2664 0x2666 0x2658 0x2659 0x265A Ox265B 0x265C Ox244E Ox266E 0x266D 0x2640 0x266F 0x2651 0x266A 0x108B 2 0x109A 0x108B 2 0x109A 0x108B 2 0x109A 0x8111 Host Bridge Internal Graphics Device Int Graphics Config Regs Intel High Definition Audio PCI Express Port 1 PCI Express Port 2 PCI Express Port 3 PCI Express Port 4 USB UHCI Controller 1 USB UHCI Controller 2 USB UHCI Controller 3 USB UHCI Controller 4 USB 2 0 EHCI Controller PCI to PCI Bridge AC 97 Audio Controller AC 97 Modem Controller LPC Bridge IDE Controller SATA Controller SMB Controller Ethernet Controller NC1 Ethernet Controller NC2 Ethernet Controller NC3 PCIE to PCI Bridge This bus number can vary depending on the PCI
2. M CPU Board OldNV d Sf O I 199 yf O I 199 JMP COM2 f O l 4294 CIDAES pd EKF ekf com SATA GPIO LED LED OEKF e CDFRIO e ekf com EKF 22 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board Strapping Headers ISPCON EC y J LRST J RTC J SPK JSWAP JSATA J1 J2 J3 J4 J5 MJ 1 2 4 P CU Pe P EXPB P IDET P IDEB Pal P SA P SATA SODIMM1 SODIMM2 LED Indicators LEDO 4 3 CD3 JIVE On Board Elements PLD programming connector not stuffed Jumper to reset BIOS CMOS RAM values Jumper to reset Board Jumper to reset RTC core of ICH6 not stuffed Speaker connector Hot Swap Micro Switch Connector SATA switch CPCI J3 J5 not stuffed Connectors amp Sockets CompactPCI Bus 32 bit 33MHz PXI Trigger CompactPCI Rear IJO PMC mezzanine module connectors 32 bit PCI rear I O option UART COM port TTL level pin header provided for an optional EKF CU series PHY module Expansion interface connector for optional mezzanine companion boards such as CCA LAMBADA or CCB BOSSANOVA available either from top T or bottom B of the CD3 JIVE board Ultra ATA 100 IDE port either for C10 CFA mezzanine module with CompactFlash Card or 1 8 Inch ATA hard disk or optional mezzanine companion boards such as CCA LAMBADA or CCB BOSSANOVA available either from top T or bottom B of the CD3 JIVE board CPU debug port
3. NC 5V COM TXD COM RXD GND GND NC USB OC2 NC NC NC 5V GND 3 3V 3 3V NC NC 5V 5V NC NC GND GND GND GND KEY AREA VGA_RED VGA_GREEN VGA BLUE VGA VSYNC GND GND GND DDC DAT 5V GND GND GND 5V GND NC GND 5V NC GND NC IDE CS1 IDE CS3 NC NC NC NC IDE DACK IDE IRQ14 IDE A01 IDE AOO GND NC GND NC IDE OW IDE IOR NC NC NC GND IDE D14 IDE DOO IDE D15 NC NC NC NC IDE DO3 IDE D12 IDE D02 IDE D13 NC NC AC SDINO AC SDIN1 IDE DO9 IDE DO5 IDE D10 IDE DO4 AC BITCLK GND AC SYNC AC SDOUT IDE RST IDE DO7 IDE DOS Signals orange italic Deviant usage on CD2 CDY Coloured green these signals may be in use for PXI trigger This pin is pulled up with 2 4kO to 4 3V Stuffing option SIO GPIO25 614 USB P24 USB P2 USB PT USB P1 USB OC1 COM DTR Be NC USB ES NC USB P4 NC USB P4 NG GND VGA_HSYNC DDE Sel GND NC IDE CBLID NC IDE ACT NC IDE A02 NC IDE IORDY NC IDE DREQ NC IDE DOT AC SDIN2 IDE D11 AC_RST IDE D06 ekf com 22 21 20 19 18 17 16 15 14 SS Ks o N W N U Bb HN WB N WO LC EKF SATAOTN NC SATAITN GND GND PMC5 PMC10 EON PMC15 PMC20 PMC25 PMC30 PMC35 PMCAO PMC45 PMC50 PMC55 PMC60 ToN SATAOTP GND SATAITP GND PMC PMCO PMC1 1 oN PMC16 PMC21 PMC26 PMC31 PMC36 PMC41 PMC46 PMC51 PMC56 PMCo1 SE CompactPCI J5 GND ve GND GND PMC2 PMC PMC12 P3 oN PMC1
4. PMC Mezzanine MJ2 67 PMC Mezzanine MJ4 68 Appendix e 69 Mechanical Drawings a a AER 790239 00790479 3924 97 7838 994799993 4E RR RS 69 d ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board About this Manual This manual describes the technical aspects of the CD3 JIVE required for installation and system integration It is intended for the experienced user only Edition History n Contents Changes User Manual CD3 JIVE english initial edition Text 4197 File 2006 06 19 cd3 uge wpd 2 Review jj 28 August 2006 3 Added additional Information jb 2007 02 02 Added photos CD3 JIVE CDT RIO C14 SATA 4 Added 12V connectivity to table of expansion interface connector PEXP jb 2007 06 05 pin 40 and to the table in section Hardware Monitor LM87 Removed some typos 5 Added additional Information jb 2007 07 19 Changed block diagram Added photos CD3 JIVE C14 SATA with PMC 6 Added information regarding Ethernet Jumbo Frame support to table jj 7 February Feature Summary 2008 7 Added chapter serial COM port connector jj 6 March 2008 8 Modified images C10 CFA amp C30 PATA mezzanine modules added images jj 24 November C24 GBE 3 Ethernet front panel jack option 2008 9 Added Power requirements for type 6 vi 2009 02 20 10 Corrected section Replacement of the Battery jj 8 September 2010 EKF 4 ekf co
5. 27 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board Serial ATA Interface SATA The CD3 JIVE provides four serial ATA SATA ports each capable of transferring 150MB s Integrated within the ICH6 the SATA controller features different modes to support also legacy operating systems The four SATA channels are routed to the CompactPCI J3 connector thus they are accessible via the rear I O transition module CDT RIO Two serial ATA ports could be switched alternately to an onboard connector suitable for mounting C14 SATA The other two SATA channels could be switched between CompactPCI J3 an CompactPCI J5 A LED named HD located in the front panel signals disk activity status of the SATA and IDE devices Available for download from Intel s web site are drivers for popular operating systems e g Windows 2000 Windows XP and Linux Enhanced IDE Interface The EIDE interface handles the exchange of information between the processor and legacy mass storage peripheral devices like hard disks ATA CompactFlash cards and CD ROM drives The interface supports gt Up to two parallel ATA devices gt PIO Mode 3 4 Ultra ATA 33 Ultra ATA 66 Ultra ATA 100 The IDE interface is routed to the on board connectors P IDET and P IDEB T top side B bottom side of the board P IDE is used to interface to the CompactFlash Card adapter C10 CFA or to the expansion board CCA LAMBADA Use the C10 CFA adapter to attach a
6. C10 E10 B9 D9 AS C8 ES B7 D 6 Co Ep B5 D5 A4 C4 E4 B3 D3 A2 C2 E2 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board Appendix Mechanical Drawings The following drawing shows the positions of mounting holes and expansion connectors on the CD3 JIVE 160 00 143 435 81 715 A 1 72 585 10 865 La M 3 556 gt 233 350 227 838 Hn HEN GN 222 95 183 35 146 35 128 35 124 35 94 50 HHIH TT LIU UI Zr poe T 3 556 EKF 69 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board boards EKF Elektronik GmbH Philipp Reis Str 4 59065 Hamm Germany systems solutions Phone 49 0 2381 6890 0 Fax 49 0 2381 6890 90 Internet www ekf com E Mail info ekf com
7. PMC22 PMC27 PMC32 PMC37 PMC42 PMC47 PMC52 PMC57 PMC62 ar ej SIV Be SATAORN GND SATATRN GND PMC3 PMC8 PMC13 5V PMC18 PMC23 PMC28 PMC33 PMC38 PMC43 PMC48 PMC53 PMC58 PMC63 5V PMC signals derived from PMC mezzanine connector J4 Signals can be switched between J3 J5 2 Default SATA Activity LED in Front Panel of CD3 JIVE User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board GND PMC4 PMC9 PMC14 5V PMC19 PMC24 PMC29 PMC34 PMC39 PMC44 PMC49 PMC54 PMC59 PMC64 5V SATAORP NC ACTLED SATA1RP ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board P CU Serial Interface Connectors If the on board RS 232 transceiver ADM211E is either not stuffed or disabled by removing the jumper JMP COM alternatively external PHY modules can be attached to the CD3 JIVE by means of a flat ribbon cable The CD3 JIVE may be equipped with the header P CU suitable for the EKF CU7 CU8 series of PHY modules The CU7 RS485 Is an isolated fieldbus interface available either for party line configuration or full duplex point to point CU7 RS485 CU8 RS232 P CU 2 00mm Pin Header 2 x 5 1 5V 0 5A 2 DSR 1 2 5 RI 3 4 RXD E TXD 5 6 DTR N 10 RTS 7 CTIS 2 00mm Shrouded DCD 9 10 GND Pin Header JMP COM removed Transceiver disabled set Bri Transceiver enabled Remove JMP COM to disable the on board transceiver when usin
8. These include also the Ultra Low Voltage ULV Celeron M and the Low Voltage LV Pentium M processors as listed below The processors are housed in a Micro FC BGA package for direct soldering to the PCB i e the CPU chip cannot be removed or changed by the user The processors supported by the CD3 JIVE are running at FSB clock speeds of 400MHz and 533MHz The internal Pentium M processor speed is achieved by multiplying the host bus frequency by a variable value The multiplier is chosen by currently required performance and the actual core temperature This technology is called Enhanced Intel SoeedStep Power is applied across the CompactPCI connectors J1 3 3V 5V The processor core voltage is generated by a switched voltage regulator sourced from the 5V plane The processor signals Its required core voltage by 6 dedicated pins according to Intels IMVP IV voltage regulator specification ULV Celeron M 373 1 0 1 0 400 0 5 5 0 100 06D8h C 0 SL8LW LV Pentium M 738 0 6 1 4 400 2 10 0 100 06D6h B 1 SL7P9 06D8h G20 SL89N Pentium M 745 0 6 1 8 400 2 21 0 100 06D6h B 0 SL7Q6 06D8h CO SL8U8 Pentium M 760 0 8 2 0 533 2 27 0 100 06D8h SCH SL869 1 2 This processor does not support SpeedStep technology thus it runs at a fixed core speed Following the Intel Embedded Roadmap this processor is recommended for long time availability EKF 25 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board
9. lt SYSTEM User Guide CD3 JIVE e CompactPCI E 6U Advanced Pentium M CPU Board Document No 4197 e Edition 10 2010 09 User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board Contents EE tnis Manual RER EELER EE HH 4 It lO TI FIS EE 4 Related DOCUMENTS aos s Vyss saa resides ren dada da bn da d din dila din ne nl a k e i 5 Nos 0 5 ligde IMarkS anan aana ai aa ii an ai in Wi a D here Wa Ta Wi ag E E AA Dm mm mn 5 Legal Disclaimer Liability Exclusion kk KK KK KK KI KIRI K K K K KI KII RI KII KI KII KK 5 REG uuu ai an Mb a oe iga ai ee ee ss s WES 6 pall SIANG 4444446644 b ober steecteecteeoteesteesteteteeoteuseeas 6 Short Description CD3 JIVE e 9 Block Diagram CD3 JIVE KK KK KK KI KK KK KK 16 Top View Component Assembly CD3 JIVE Ak kK KK KK ee 18 CDT RIO Rear I O Transition Module_ eee 19 Short Description ee 19 Block Diagram CDT RIO 4k kk kK KK KEK KI KIRI KI K K KIRI KI KIRI KIRI KIRI KII KIRI KIRI KI KIR k 21 Assembly Drawing CDT RIO 21 CD3 JIVE On Board Elements K KI K KIRI KI KI KI KI KI KI KI KI KK 23 Strapping Heades gt A 3 dl ah ll k Jl TORT ak dil b dl ad eget oped dos 23 CONNES K amp K DOCK S a d la 3 42 d di d di4 dk saq di bd di ex ase 23 ME pj e szil C lt 2 au akc he bc m
10. ADS P 12 AD42 11 Are 10 AD49 9 ADD 8 AD56 7 AD59 6 AD63 5 C BE5 4 V I O 3 CLK4 2 CLK2 1 CLK1 This pin is pulled up with 1kQ to V I O Other pull up resistor values e g 2 7kQ for V I O 3 3V are available on request GA3 gt GND GND GND BRSVP2B18 GND PKI TRIGO BRSVP2B16 GND AD34 GND AD41 GND AD48 GND AD55 GND AD62 GND 64EN BRSVP254 GND CLK3 GND This pin is pulled up with 10kQ to 5V This pin is not connected This pin is pulled up with 10kQ to 3 3V EKF GA2 RSV RSV RSV BRSVP2C18 PRST DEG FAL PND V I O AD40 V I O AD47 V I O AD54 V I O ADHI V I O C BE7 GNT3Z SYSEN REQ1 50 GA1 RSV GND RSV GND REQ6 GND REQS GND DUA GND AD44 GND ADS D GND AD58 GND C BE4 GND REQ4 GNT2 GNT1 GAO RSV RSV RSV PKI TRIG6 gt BRSVP2E18 GNT6O PXI_TRIG7 gt BRSVP2E16 GNT5 ADHI AD36 AD39 AD43 AD46 ADO AD53 ADI AD60 PAR64 C BE6 GNT4 REQ3 REQ2 pin positions printed italic coloured brown reserved by specification and not connected Coloured green these signals may be in use for GPIO on J4 ekf com CompactPCI J3 19 18 17 16 15 14 13 12 10 EKF GND LPa DA LPa DB LPb DA LPb DB GND NC NC NC NC GND NC SATA TX3 gt NC GND N
11. CompactFlash ATA style silicon disk whenever a hard disk is not suitable for your system or as an additional mass storage device The CCA LAMBADA expansion board is capable to carry an on board 1 8 or 2 5 hard disk drive When using the 1 8 option the concurrent operation of a CompactFlash device Is possible A LED named HD located in the front panel signals the disk activity status of both the IDE and SATA devices The IDE controller is integrated into the ICH6 Ultra ATA IDE drivers can be downloaded from the Intel web site EKF 28 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board Graphics Subsystem The graphics subsystem is part of the Intel 1915GM Graphics Memory Controller Hub GMCH and supports dual screen operation The CD3 JIVE therefore is provided with a DVI I DVI 1 and in addition a DVI D DVI 2 graphics connector DVI I is both a digital and analog interface DVI D is only a digital interface Recent digital input flat panel displays are widely available with this connector style For classic monitors adapters or adapter cables can be used for converting from DVI I to the 15 pin HD D SUB connector A special display transmitter chip is used to convert Intel s proprietary PCI express based SDVO interface to the differential DVI signals The Sil1362 Silicon Image transmitter uses PanelLink Digital technology to support displays ranging from VGA to UXGA resolutions 25 165Mpps in a s
12. JIVE Advanced CompactPCI 6U Pentium M CPU Board Block Diagram CD3 JIVE EKF Block Diagram Alternative CPU Pentium M CD3 JIVE e Pentium M 745 1 8GHz 760 Bes e LV Pentium M 738 1 4GHz e Celeron M 370 1 5GHz 2 0GHz Sheet 1 2 ULV Celeron M 373 1 0GHz FSB 533MHz O Dual SDVO O DDR2 533 N lt 1GB 2GB gt E lo ES C 2 O UN VGA N USB U a GPIO er o AC 97 ol GPIO SIO weem U DVI ES PS 2 COM JA lt wv x FWH G E A E BIOS ER 802 U DN N ON Au U 40 el NANGEN oo GG PCI UJ AC 97 W J1 TA gu J2 CB 5 Gro F o MA O E USB ke PCle Een E CIOTA 1 CompactFlash ATA 2 a LLI OI O O EKF o lt b c ekf com 5 l UL 16 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board Block Diagram CD3 JIVE E H LU Rev 1 lt a i Sheet 2 2 EKF PCle to PCI GE ekf com Bridge PICMG 2 16 pci JN Pce L 82 GE 1 1 J SATA or SIO SATA 0 1 T E SATA SW2 E Mi SATA sW1 SATA Front Panel I O Option Dual 2 5 Inch HD C14 SATA Dual 2 5 HD Module PMC Mezzanine PMC Module and or 2 5 Inch SATA Hard Disk Module C14 SATA Mounts on Top of the PMC Local Po
13. Thermal Considerations In order to avoid malfunctioning of the CD3 JIVE take care of appropriate cooling of the processor and system e g by a cooling fan suitable to the maximum power consumption of the CPU chip actually in use Please note that the processors temperature is steadily measured by a special controller LM87 attached to the onboard SMBus System Management Bus A second temperature sensor internal to the LM87 allows for acquisition of the boards surface temperature Beside this the LM87 also monitors most of the supply voltages A suitable software to display both the temperatures as well as the supply voltages is MBM Motherboard Monitor which can be downloaded from the web After installation both temperatures and voltages can be observed permanently from the Windows taskbar The CD3 JIVE is equipped with a passive heatsink Its height takes into account the 4HP limitation in mounting space of a CPCI board In addition a forced vertical airflow through the system enclosure e g bottom mount fan unit is strongly recommended gt 15m h or 200LFM around the CPU slot As an exception the CD3 2 JIVE ULV Celeron M 1GHz can be operated with natural convection only Be sure to thoroughly discuss your actual cooling needs with EKF Generally the faster the CPU speed the higher its power consumption For higher ambient temperatures consider increasing the forced airflow to 400 or 600LFM The table showing the supported pr
14. UART COM port TTL level connector provided for an optional MEN SA type PHY mezzanine module Serial ATA mezzanine module connector provided for the C14 SATA dual hard disk option 200 pin DDR2 memory module SDRAM PC2 3200 4200 DDR400 533 sockets User programmable LEDs option 23 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board CD3 JIVE Front Panel Elements EKF GBE 1 GBE 2 USB1 2 DVI 1 VGA DVI 2 COM PMC GP HD HS ETH3 Reset PWR RES 1000Base TX 100Base TX 10Base T RJ 45 receptacles with integrated indicator LEDs activity amp speed Universal Serial Bus 2 0 self powered root hub type A receptacle DVI I integrated digital amp analog receptacle suitable for DVI digital flat panel displays and or analog monitors Option VGA D Sub connector DVI D digital only receptacle suitable for DVI digital flat panel displays Option CU SA type mezzanine module or COM port connector PMC mezzanine module front panel connector s General Purpose LED LED indicating any activity on IDE or SATA ports Hot swap LED Blue Activity LED rear panel or PICMG 2 16 backplane GBE port Reset push button switch with integrated indicator LED power good 24 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board Microprocessor The CD3 JIVE is designed for use with Pentium M and Celeron M processors manufactured in 90nm technology Dothan
15. enumeration schema implemented in BIOS S The CD3 JIVE is available with a 82573E 0x108B or 82573L 0x109A Ethernet controller EKF ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board Local SMB Devices The CD3 JIVE contains a few devices that are reachable via the System Management Bus SMBus These are the clock generation chip the SPD EEPROMs on the SO DIMM memory modules a general purpose serial EEPROM and a supply voltage and CPU temperature controlling device in particular Other devices could be connected to the SMB via the CompactPCI signals IPMB SCL J1 B17 and IPMB SDA J1 C17 0x58 Hardware Monitor CPU Temperature Sensor LM87 OxAO SPD of SODIMM1 OxA2 SPD of SODIMM2 OxAE General Purpose EEPROM OxD2 Main Clock Generation CK 410M Hardware Monitor LM87 Located on the SMBus the CD3 JIVE offers a hardware monitor of type LM87 NSC This device is capable to observe board and CPU temperatures as well as several supply voltages generated on the board with a resolution of 8 bit The following table shows the mapping of the voltage inputs of the LM87 to the corresponding supply voltages of the CD3 JIVE AIN1 CPU Core Voltage 9 8 0x28 AIN2 1 05V 9 8 Ox29 VCCP1 PESV AN 0x21 VCCP2 D2 REN 14 1 0x25 TA OVD 2 FADN 13 0x20 ION ON 42 0x22 ov FSV 26 0x23 12V 12V 62 5 0x24 Revision 1 or higher Beside the continuous measuring of temperatures and voltages the LM87 may compare the
16. panel is available with additional connectors Utilization of the CDT RIO transition module adds a level of I O functionality that is not available with the CD3 JIVE CPU board alone Further on swapping the CPU card is simplified by means of rear WO which is important for efficient system maintenance MTTR For technical details please refer to the CDT RIO Technical Information Manual available at www ekf com c ccpu cd3 cdt tie pdf EKF ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board CD3 JIVE with CDT RIO EKF 20 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board Block Diagram CDT RIO _P PMC Y y P AUDIO P SA2 9 we PMC optional 2 mg Rearl O mezzanine es back panel o adapter N ac EKF J5 ekf com NT THENG m amp gt so BENA E USB4 am USB a U U Fa HD Audio Y Ge USB P CU n gt COM TD COM RS 232 Q E E o VGA P SA1 Q CC Gplo n JMP COM m VGA le 2 aW P GPIO 5V lt FE P POW So o E SE CH x N P PS2 GETH ae Block Diagram _ GETH Y A SE 10 100 1000Mbps SPO SP1 SP2 SP3A Ethernet d Ji e SATA T T T o LY LY a CC Serial ATA J 3 6U 4HP Assembly Drawing CDT RIO EKF z21 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium
17. power consumption The Intel chipset is based on PCI Express technology and has a powerful integrated graphics accelerator The CD3 JIVE is provided with two independent front panel DVI video connectors for simultaneous attachment of two flat panel displays It both video ports are active in single channel mode they can have different display timing and data Alternatively the DVI ports can be combined for a dual screen configuration supporting higher resolutions and refresh rates The CD3 JIVE is equipped with three independent Gigabit Ethernet controllers including PICMG 2 16 support and eight USB 2 0 ports for high soeed communication An on board socket accommodates either a CompactFlash ATA card or an 1 8 inch hard disk module A PMC mezzanine module connector may be used for individual system expansion As an option the CD3 JIVE is available in addition with a dual 2 5 inch SATA hard disk add on module which mounts on top of the PMC slot Furthermore a rear I O transition module is available for the CD3 JIVE Four Serial ATA channels are routed across the J3 J5 CPCI connectors besides two Gigabit Ethernet ports four USB channels and a variety of other useful signals Benefits of the CD3 JIVE PCI Express Chipset Dual Screen Graphics Controller 3 x Gigabit Ethernet Controllers 4 x SATA I F 8 x USB 2 0 Channels PMC Mezzanine Module Slot Y YV YV V YV wW W VW Y Y Y YW RoHS compliant EKF Pent
18. 00Mbit s when lit green and 10Mbit s when off The lower green LED indicates LINK established when continuously on and data transfer activity when blinking If the lower green LED is permanently off no LINK is established Available as an option a 3 GE F P jack can be assembled together with a 8HP front panel C24 GBE Mezzanine Module EKF 5 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board FR e CD3 JIVE with 3rd Gigabit Ethernet Front Panel Jack Option EKF 52 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board COM Port Connector As an option the CD3 JIVE can be equipped with a COM port connector serial interface RS 232 The serial port connector is exclusive to the secondary video output connector DVI D due to limited space in the front panel The serial port interface is provided by the on board SIO Super I O chip As RS 232 line drivers receivers an ADM211E was chosen featuring 230kbps guaranteed data rate In order to enable the ADM211E the jumper J COM must be set or a 0 Ohm shunt resistor position must be filled in parallel to J COM as an alternative The serial connector COM should not be used concurrently with neither P CU on board header for attachment of CU series PHY modules nor P SA SA modules in order to avoid interference between signals trom different sources Hence if either P CU or P SA is engaged please remove ju
19. 386 Draft 2 4a pg 48 PCI protocol capable card pin positions printed italic coloured brown reserved by specification and not connected IT r ITA Notes IDSEL is assigned to AD16 2 This pin position is normally a PMC reserved pin on CD2 it may be used to connect to the SERIRQ signal This pin position is pulled to 3 3V via separate 3 3 KO resistor This pin position is pulled to GND via separate 1 0 KO resistor EKF 67 ekf com EKF User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board B15 D15 A14 C1 4 E14 B13 D13 A11 C11 E11 B10 D10 A9 C9 ES BS D8 A C7 E7 BO D6 A5 C5 E5 B4 D4 A3 C3 E3 B2 D2 com Ll RO CO 13 15 19 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 5f 59 61 63 PMC Mezzanine MJ4 I O 01 JO 03 JO 05 JO 07 I O 09 O 11 I O 13 VO 15 VO 17 VONG I O 21 O 23 V O 25 WO 27 VO 29 I O 31 JO 33 JO 35 WO 37 I O 39 I O 41 JO 43 WO 45 WO 47 JO 49 I O 51 JO 53 I O 55 WO 57 JO 59 I O 61 I O 63 68 I O 02 JO 04 I O 06 I O 08 VO 10 I O 12 VO 14 VO 16 0 18 JO 20 IJO 22 VO 24 JO 26 JO 28 I O 30 I O 32 JO 34 I O 36 VO 38 JO 40 JO 42 I O 44 JO 46 JO 48 I O 50 JO 52 WO 54 JO 56 JO 58 I O 60 JO 62 I O 64 O N 10 2 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 C15 E15 B14 D14 A13 C13 E13 B11 D11 A10
20. AD2 22 AD7 GND 3 3V AD6 AD5 21 3 3V AD9 AD8 M66EN C BEO 20 AD12 GND V I O AD11 AD10 19 3 3V AD15 AD14 GND AD13 18 SERRA GND 3 3V PAR C BE1 17 3 3V IPMB SCL IPMB SDA GND PERR 16 DEVSEL GND V I O STOP LOCK 15 3 3V FRAME IRDY BDSEL 9 TRDY 14 13 KEN NREA 12 11 AD18 AD17 AD16 GND C BE2 10 AD21 GND 3 3V AD20 AD19 9 C BE3 AD23 GND AD22 8 AD26 GND V I O AD25 AD24 7 AD30 AD29 AD28 GND AD27 6 REQ GND 3 3V CLK AD31 5 BRSVP1A5 BRSVP1B5 RST GND GNT 4 IPMB PWR GND V I O INTP INTS 3 INTA INTB INTC 5V INTD 2 5 5V 5 5 5 1 5V 12V 12V 5V n W N NA NGA NGA O pin positions printed italic coloured brown reserved by specification and not connected This pin is pulled up with 1kQ to V I O Other pull up resistor values e g 2 7kO for V I O 3 3V are available on request This pin is not used on CD3 JIVE but pulled up with 1kQ to V I O Other pull up resistor valus on request This pin is fixed to GND on CD3 JIVE to force 33MHz operation since 66MHz operation is not supported This pin is pulled up with 2 4k to J1 pin A4 This pin is not connected This is a short pin providing the last connection on hot board insertion EKF 58 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board CompactPCI J2 22 GA4 21 CLK6 20 CLK5 19 GND 18 BRSVP2A18 17 BRSVP2A17 16 PKI TRIG1 BRSVP2A16 15 BRSVP2A15 14 AD35 V 13
21. C SATA TX2 NC GND NC SATA KI NC GND NC SATA TXO NC NC SAW AC ET GND LPa DA LPa DB LPb DA LPb DB GND NC NC NC NC GND NC SATA TX3 NC GND NC SATA TX2 gt NC GND NC SATA TX1 NC GND NC SATA TXO NC GND NC GND GND GND GND GND GND NC NC NC NC GND NC GND NC SC NC GND NC 5V NC GND NC TSY NC GND NG GND NC GND LPa DC LPa DD LPb DC LPb DD GND NC NC NC NC GND NC SATA RX3 NC GND NC SATA RX2 NC GND NC SATA RX1 NC GND NC SATA RXO NC GND NC J3 is optional concurrent to PICMG 2 16 backplane Signals orange italic Deviant usage on CD2 CDY Signals can be switched between J3 J5 Default SATA Activity LED in Front Panel of CD3 JIVE Signals can be switched between J3 P SATA 60 User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board GND LPa DC LPa DD LPb DC LPb DD GND NC NC NC NC GND NC SATA RX34 NC GND NC SATA RX24 NC GND NC SATA RX14 NC GND NC SATA _RXO NC GND NC ekf com EKF 25 24 23 22 21 20 User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board CompactPCI J4 MS DATA SIO_GPIO20 SIO GPIO24 KB DATA MS CLK SIO GPIO21 Nee KB CLK GND SIO GPIO22 SIO GPIO26 GND COM2 RIZ SIO GPIO23 SIO GPIO27 5V COM RTS COM DSR COM CTS COM DCD
22. CI bus to allow the system hot swapping This signal is routed to the GPI3 of the ICH6 on the CD3 JIVE A System Management Interrupt SMI can be requested if ENUM changes by Insertion or removal of a board Blue Hot Swap LED The CD3 JIVE is equipped with a blue LED a LED marked as HS is placed in the front panel near the lower board handle that indicates when board extraction is permitted A micro switch in one of the front panel ejectors signals when a board extraction event takes place This micro switch is connected via the 3 pin header JSWAP EKF 32 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board Power Supply Status DEG FAL Power supply failures may be detected before the system crashes down by monitoring the signals DEG or FAL These active low lines are additions of the CompactPCI specification and may be driven by the power supply DEG signals the degrading of the supply voltages FAL there possible failure On the CD3 JIVE the signal FALZ is routed to the GPI4 and DEG to the GPI5 of the ICH6 PXI Trigger Signals As a stuffing option resistor network the CD3 JIVE supports four of the eight trigger signals of the PXI standard across the connector J2 as defined by National Instruments The trigger signals are provided by the local SIO Super I O chip IT8761E GPIO20 21 are routed to TRIGO 1 and GPIO26 27 are used to control TRIG6 7 These signals may alternatively be used as GPIO li
23. E Line Expansion Interface SMI Line USB Port 6 Overcurrent Detect Line USB Port 7 Overcurrent Detect Line CompactPCI Bus Grant Line 6 CompactPCl Bus Grant Line 5 General Purpose LED Control via PLD Ethernet Switch Front Rear LOW Ethernet Port 1 via Rear I O HIGH Ethernet Port 1 via Front I O Local Option Reg Interface within PLD Local Option Reg Interface within PLD Connect SERIRQ to CompactPCI Line INTS LOW SERIRQ disconnected from INTS HIGH SERIRQ connected to INTS Connect CPCI IPMB to local SMBus LOW IPMB disconnected from SMBus HIGH IPMB connected to SMBus Enable CompactPCI Clock Buffer Not used on CD3 fixed to GND ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board CD3 JIVE GPIO Usage ICH6 GPIO GPIO 27 GPIO 28 JO GPI 29 31 GPIO 32 O GPIO 33 O GPIO 34 O GPI 40 GPI 41 GPO 48 O GPO 49 OD GPIO Usage FWH EEN 3 3V 3 3V 3 3V 3 3V 5V 3 3V EEN 1 05V VGA SWITCH EJECT LED BOARD CFG NC1 EN NC2 EN NC3 EN CPCI REQ4 LPC_DRQEXP CPCI GNT4 CPU PWRGD VGA Switching Line LOW VGA via Rear I O HIGH VGA via Front WO CPCI Hot Swap Ejector Board Configuration Jumpers Enable Ethernet Controller NC1 Enable Ethernet Controller NC2 Enable Ethernet Controller NC3 CompactPCI Bus Request Line 4 Expansion Interface LPC DMA Request Line CompactPCI Bus Grant Line 4 CPU Power Good Line CD3 JIVE GPIO Usage FWH GPIO GPI O GPI 1 G
24. O 47 Video Monitor Connector DVI 1 DVI I A8 Video Monitor Connector DVI 2 DVI D 49 Video Monitor Connector VGA 50 USB Connectors 50 Ethernet Connectors 51 COM Port Connector 53 Internal Connectors 54 Expansion Interface Header P EXP 54 ATA IDE Header PIDE 55 Speaker Header J SPK 56 Hot Swap Micro Switch Pin Row JSWAP 56 PLD Programming Header ISPCON 56 Processor Debug Header P ITP 57 Compara J sae aaa eure cree mmmmmpmmpphe r r eee Ree ees 58 COMA sud 3 RARE RSRERSRS ES RR ea nnnmm 59 CO G JS Sv an aa Gee ete eee mm kb maa 60 CompaciCilA amp 2 kR K be kg n K m kan K w h 61 e raa Cl Jos et eee eee nee eee mm pe s 62 P CU Serial Interface Connectors 63 P SA Serial Interface Connectors 64 P SATA 65 PMC Mezzanine MJ 66
25. PI 2 GPI 3 GPI 4 EKF 3 3V 3 3V 3 3V 3 3V FWH ID IDE CLBID WDOGRST LSB PCB REV MSB PCB REV FWH Identity Fixed to GND indicates FWH 1 IDE 80pol Cable Detection Line Last Hardware Reset caused by watchdog GPI4 GPI3 Rev 0 0 0 0 1 1 1 0 2 1 1 ES ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board GPIO Usage SIO CD3 JIVE GPIO Usage SIO GPIO Erz Heran iwan E zaman GPIO 13 GPIO 14 GPIO 15 GPIO 16 GPIO 17 GPIO 20 GPIO 21 er lO 22 GPIO 23 GPIO 24 GPIO 25 GPIO 26 GPIO 27 I O I O I O I O I O I O I O I O I O I O 5V 5V 8mA 5V 8mA 5V 24mA 5V 24mA 5V 8mA 5V 8mA 5V 24mA 5V 24mA 5V 24mA 5V 24mA 5V 24mA 5V 24mA CPCI 64EN7 SATA SWITCH TRSHDN SIO GPIO16 SIO GPIO17 PXI TRIGO PXI TRIGI SIO GPIO22 SIO GPIO23 SIO GPIO24 SIO GPIO25 PXI_TRIG6 PXI_TRIG7 CompactPCI 64 Bit Backplane Serial ATA Switch LOW C14 SATA HIGH CDT RIO COM Onboard Enable Disable LOW Disable HIGH Enable GPIO on Expansion Interface P EXP Pin 29 GPIO on Expansion Interface P EXP Pin 30 PXI Trigger O on CompactPCI J2 Pin B16 PXI Trigger 1 on CompactPCI J2 Pin A16 GPIO J4 b23 GPIO J4 b22 GPIO J4 c25 Serial ATA Switch2 LOW CompactPCl J5 HIGH CompactPCl J3 Stuffing option GPIO JA c24 PXI Trigger 6 on CompactPCl J2 Pin E18 PXI Trigger 7 on CompactPCI J2 Pin E16 These GPIO
26. SO DIMM socket DDR2 533 PC2 SDRAM 2 x 1GB maximum dual channel symmetric mode supported 2 x DVI single or dual screen video output up to 2048x1536 mode support graphics controller with dual independent display pipes for different display timing and data on both outputs in single display mode or dual screen mode for higher resolutions and refresh rates gt The lower DVI I connector is suitable for both digital DVI and analog VGA displays for attachment of VGA style monitors adapters and adapter cables are available gt The upper DVI D connector is suitable for displays with DVI input only gt Front panel option D Sub female HD15 VGA connector available replaces DVI I connector gt Rear I O option Analog video across J4 P4 suitable for CDT RIO rear I O transition module VGA connector All ports over current protected data transfer rate of up to 480Mbps conforming to USB2 0 gt 2 x USB front panel connectors gt 4 x USB rear I O ports across J4 P4 gt Suitable CDT RIO rear WO transition module provides 3 x USB back panel connectors 1 x USB on board connector gt 2 x USB ports available with proprietary expansion interface option CCA LAMBADA CCB BOSSANOVA mezzanine companion board Triple 10 100 1000Mbps Gigabit Ethernet GbE controller One GbE Port software switchable BIOS between front panel and rear WO Up to 2 x GbE accessible via RJ45 jacks from the front panel 3 x GbE via front panel option b
27. acility C10 2 CFA Quad channel Serial ATA I F gt On board SATA mezzanine storage module option C14 SATA 1 or 2 hard disk drives 2 5 inch mass storage module mounts on top of the PMC slot space gt Up to 4 x SATA channels available for J3 P3 rear I O option SATA 0 1 can be routed either to the J3 or J5 rear I O connector by means of a software controlled signal switch and SATA 2 3 channels can be switched between J3 for rear I O or P SATA for on board usage together with the C14 SATA mezzanine module gt Suitable rear WO transition module CDT RIO provides 3 x on board SATA connectors and optionally 1 x eSATA connector back panel External SATA ICH6 integrated 32 bit PCI bridge 133MBps CPCI master Board hot insertion extraction without adversely effecting a running system Basic Hot Swap implementation according to CompactPCI Hot Swap Specification PICMG 2 1 In order to use the CD3 JIVE as a peripheral slot board special board versions are required available on request gt 4 x Serial ATA 2 x if on board SATA storage module option is selected gt 2 x GB Ethernet 1 port shared with front panel connector selectable by BIOS gt 4 x USB gt VGA Analog Video gt PS 2 Keyboard Mouse gt COM1 TTL Level not available together with front panel connector option RS 232 RS 485 gt GPIO TTL Level gt AC 97 Audio gt Suitable rear I O transition module CDT RIO available gt Phoenix BIOS with EKF embedded sy
28. an continue to operate even though the power switch is in its off state Caution Electrostatic discharge ESD can damage components Perform the procedures described in this chapter only at an ESD workstation If such a station is not available you can provide some ESD protection by wearing an antistatic wrist strap and attaching it to a metal part of the system chassis or board front panel Store the board only in Its original ESD protected packaging Retain the Original packaging antistatic bag and antistatic box in case of returning the board to EKF for rapair EKF 35 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board Installing the Board Warning This procedure should be done only by qualified technical personnel Disconnect the system from its power source before doing the procedures described here Failure to disconnect power or telecommunication links before you open the system or perform any procedures can result in personal injury or equipment damage Typically you will perform the following steps e Switch off the system remove the AC power cord e Attach your antistatic wrist strap to a metallic part of the system A e Remove the board packaging be sure to touch the board only at the front panel e Identify the related CompactPCI slot peripheral slot for YO boards system slot for CPU boards with the system slot typically most right or most left to the backplane e Insert ca
29. and the processors runs at full speed again A similar feature is embedded within the Graphics and Memory Controller GMCH 1915GM An on die temperature sensor is used to protect the GMCH from exceeding its maximum junction temperature T 105 C by reducing the memory bandwidth J max These features are controllable by BIOS menu entries By default the BIOS of the CD3 JIVE enables mode TM2 which is the most efficient Main Memory The CD3 JIVE is equipped with two sockets for installing 200 pin SO DIMM modules module height 1 25 inch Supported are unbuffered DDR2 SO DIMMs V 1 8V without ECC featuring on die EKF 26 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board termination ODT according the PC2 3200 or PC2 4200 specification Minimum memory size is 128MB maximum memory size is 2GB Due to the video requirements of the 1915GM chipset a minimum of 2x256MB of memory is recommended for the operating systems Windows NT 4 0 Windows 2000 or Windows XP some of the system memory Is dedicated to the graphics controller The contents of the SPD EEPROM on the SO DIMMs is used by the BIOS at POST Power on Self Test to program the memory controller within the chipset The 1915GM chipset supports symmetric and asymmetric memory organization The maximum memory performance can be obtained by using the symmetric mode To achieve this mode two SO DIMMs of equal capacity must be installed in th
30. d for an on board SATA hard disk mezzanine module C14 SATA on the CD3 JIVE or are externally available across J3 SATA channels 2 3 are also controlled by the BIOS select either to be used externally on CompactPCl J3 or CompactPCl J5 The COM 1 port does not include the physical transceiver TTL level only This transceiver is located on the rear I O module CDT RIO instead If COM1 is already in use on the CD3 JIVE by means of a PHY attached to P CU or P SA the transceiver on the CDT RIO must be inhibited by removing the CDT J COM jumper Rear I O is restricted to the J3 J5 connectors except PXI across J2 hence the CD3 JIVE CPU card by default is suitable for any common 32 64 bit CompactPCI J1 J2 backplane EKF 34 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board Installing and Replacing Components Before You Begin Warnings The procedures in this chapter assume familiarity with the general terminology associated with industrial electronics and with safety practices and regulatory compliance required for using and moditying electronic equipment Disconnect the system from its power source and from any telecommunication links networks or modems before performing any of the procedures described in this chapter Failure to disconnect power or telecommunication links before you open the system or perform any procedures can result in personal injury or equipment damage Some parts of the system c
31. e CompactFlash adapter module please request for a special solution which allows to use both the CF slot and the 1 8 inch drive simultaneously ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board C14 SATA Dual Serial ATA Hard Disk Mezzanine Module In addition the CD3 JIVE can be optionally ordered with a 2 5 inch SATA hard disk mezzanine module C14 SATA single or dual drive This storage module option would normally occupy the mounting space which was originally reserved for the PMC module 4HP solution but the PMC mezzanine module can also be placed underneath the C14 SATA module 8HP solution and therefore the storage solution C14 SATA can be used in parallel with one PMC Module If the CD3 JIVE is equipped with the C14 SATA storage module the number of SATA channels for rear I O usage is limited to 2 The 2 5 inch hard disk module is an economical solution because its using the CD3 JIVE on board SATA controller There are several PMC based solutions available the DE2 TIGER a SATA IDE controller PMC card with an integrated 1 8 inch drive DB1 FALCON a Five Port USB 2 0 host controller for more available solutions please contact EKF DE2 TIGER PMC Module with on Board 1 8 Inch Hard Disk EKF ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board CD3 JIVE 8HP Solution w PMC Module C14 SATA CCA LAMBADA EKF 15 ekf com User Guide CD3
32. e be oe GG He SG Ge PPP 23 CD3 JIVE Front Panel Elements EERE nde KI KI Rt e KIR 24 MICO OC gg PA gp A rr oa aa 2 MM 2 2 oomxxmDDMMDx xnmnmmn 25 Term GConsld l3l OlS csc gt x yx sx 555555555555 pa 55 pe Sees Phos QA yess pa u Wy 26 Malt BAGIO EENHEETEN 26 EAN SUBS SIC a a a s olo osa z ebe 1929 9 8392 3 9299399 d e Z obe Z eee Z ebe 2238 ERES 27 Serial ATA Interface SATA 28 Enhanced IDE Interface es 28 Graphics Subsystem KI KI KI KK KI K KI KI KI KI KI KI KI KI KI KI KI KK KK K 29 Peale 6 a ak EE KN KEN ss 30 Universal Serial Bus USB 30 LPC Super l O Interface 30 Rece UNGO 44444480408 EA Kh 1k a bk a A A d hk h 468 dk xb KI a eet GI di d da dira 31 Firmware Hub Flash BIOS 31 Mezzanine Mera EE ala sw yu su Vu blr dla dy lk dn dik del da dr dn dir dily did dla din dw d le d 32 PG Power Good LED 32 AD Hard DEKA EBD s an a nan n nn n ans EUR RUE sp 36 a 304 aw p MA M6 Enea eee eee 32 GP General Purpose LED 32 FOU swap Detection css ss sa AE e S S agi ot ete S eset et Se ot S S spp S ees oe apup Sees 32 Power Supply Status DEG FALZ 33 PXI Trigger Signals 2 naunan aaaea 33 CRO SION A KHE a pS 33 Rear iere apro s
33. e memory sockets In asymmetric mode different memory modules may be used with the drawback of less bandwidth A special case of asymmetric mode is to populate only one memory module i e one socket may be left empty LAN Subsystem The Ethernet LAN subsystem is composed of three Intel 82573 Gigabit Ethernet controllers that provide also legacy 10Base T and 100Base TX connectivity Two Ethernet ports are fed to two RJ45 jacks located in the front panel one is configurable as an alternative to backplane packet switching according PICMG Spec 2 16 or CDT RIO rear panel I O The third Ethernet controller is solely available for backplane packet switching or rear panel I O Each port includes the following features One PCI Express lane per Ethernet controller 250MB s 1000Base Tx Gigabit Ethernet 100Base TX Fast Ethernet and 10Base T capability Half or full duplex operation IEEE 802 3 Auto Negotiation for the fastest available connection Jumperless configuration complete software configurable Two bicoloured LEDs integrated into the dedicated RJ 45 connectors to signal the LAN link the LAN connection speed and activity status Y vv YV Y W Each NIC Networking Interface Controller is connected by a single PCI Express lane to the chipset ICH6 Their MAC addresses unique hardware numbers are stored in dedicated EEPROMSs The Intel Ethernet software and drivers for the 82573 is available from Intel s website for download EKF
34. etore You Begin By default the CD3 JIVE comes fully equipped and tested with two DDR2 SD RAM memory modules So normally there should be no need to Install the memory modules The CD3 JIVE requires at least one PC2 3200 4200 400 533MHz DDR2 SDRAM SO DIMM module for better performance two SO DIMMs of equal capacity are recommended Further it is highly recommended that Serial Presence Detect SPD SO DIMMs be used since this allows the chipset to accurately configure the memory settings for optimum performance A replacement memory module must match the 200 pin SO DIMM form factor known trom Notebook PCs DDR2 V 1 8V PC2 3200 PC2 4200 400 533MHz on die termination ODT unbuffered non ECC style Suitable modules are available up to 1GB The 1915GM supports modules of up to a maximum of 14 address lines AO A13 Memory modules organized by more than14 address lines are not suitable Replacement of the Battery When your system is turned off a battery maintains the voltage to run the time of day clock and to keep the values in the CMOS RAM The battery should last during the lifetime of the CD3 JIVE For replacement the old battery must be desoldered and the new one soldered It is recommended that you send back the board to EKF for battery replacement Warning Danger of explosion if the battery is incorrectly replaced Replace only with the same or equivalent type Do not expose a battery to Tire EKF 39 ekf com
35. exclusively for direct attachment of a dynamic speaker device When connecting to the input of a sound card most likely a short circuit situation will occur between the 5V pin of the JSPK connector and the GND pin of the audio card input which could cause permanent damage to the CD3 JIVE and the audio board despite the PolySwitch resettable fuse A workaround to this would be to place a 1k resistor across pin 1 and pin 2 of the JSPK connector and strapping a single wire cable from JSPK pin 2 to the audio input Hot Swap Micro Switch Pin Row JSWAP PLD Programming Header ISPCON ISPCON RH K K K s K K K ekf com 1 3 3V 2 SernalOut 3 Serial In 4 ispGAL Enable 5 NC 6 Mode 7 GND 8 Clock Note The ISPCON is not stuffed Its footprint is situated at the bottom side of the board EKF 56 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board Processor Debug Header P ITP EKF P ITP 1 2 2 20 21 D 23 24 25 26 2 28 Note The Debug Header is situated at the bottom side of the board 57 TDI TMS TRST NC Tek NC TDO BCLKN BCLKP GND FBO RST BPM5 GND BPM4 GND BPM3 GND BPM2 GND BPM1 GND BPMO DBA DBR VTAP ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board CompactPCI J1 25 5V REQ64 ENUM 3 3V 5V 24 AD 5V V I O AD0 ACK64 23 3 3V AD4 AD3 5V
36. g P CU EKF 63 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board P SA Serial Interface Connectors Another header P SA may be provided on the CD3 JIVE which complies with the MEN SA series of PHY modules No more than one transceiver may be in use either P CU P SA or the on board transceiver P SA2 2 54mm Socket 2 x 5 5V 0 5A 2 1 GND 58 RXD 4 3 TXD E RTS 6 5 DIR n CTS 8 7 DSR 10 2 54mm Socket RIZ 10 DCD JMP_COM Remove JMP COM to disable the on board transceiver when using P SA EKF 64 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board P SATA The CD3 JIVE can be optionally ordered with a 2 5 inch SATA hard disk mezzanine module C1 4 SATA single or dual drive These signals can be switched between CompactPCl J3 and P SATA P SATA 2 00mm Socket 2 x 13 GND I 2 GND SATA2TP 3 4 5V SEA SATA2TN 5 6 5V GND GND SATA2RN 3 10 5V SATA2RP 11 12 5V GND 13 14 GND SATA3TP 15 16 3 3V SATA3TN 17 18 3 3V GND 19 20 GND 26 SATA3RN 21 22 3 3V SATA3RP 23 24 3 3V GND 25 26 GND EKF 65 ekf com EKF User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board O N UT UJ 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 pin positions printed italic coloured brown reserved by specification and not connected 2 This pin position is pulled to 3 3V via
37. ingle link interface The GMCH supports several video resolutions and refresh rates A partial list is contained in the table below Please note that flat panel displays should be operated with their maximum resolution at 60Hz refresh rate 640x480 Av GAG ANA ANA ANA 800x600 VA Viv oh ANA VNS 1024x768 Va A ANG P Viv ANA 1280x1024 Ziya V A Va rU Viv VA 1600x1200 WA LE Z v Y 2048x1536 Vay gy 4 VV This video mode is suitable for popular flat panel displays As an alternative option to the DVI 1 receptacle the CD3 JIVE can be equipped with an ordinary HD D Sub 15 lead connector VGA style This connector is suitable for analog signals only so the PanelLink transmitter is not stuffed with this option Nevertheless also flat panel displays can be attached to the D Sub connector but with minor reduced image quality Independent from the video connector actually in use DVI or VGA the VESA DDC 2B standard is supported This is a two wire serial bus clock data which is controlled by the GMCH and allows to read out important parameters e g the maximum allowable resolution from the attached monitor In addition DDC Power 5V Is delivered to either connector A resettable fuse is stuffed to protect the board from an external short circuit condition 0 754 Graphics drivers for the i915GM can be downloaded from the Intel web site EKF 29 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU B
38. ium M 2GHz FSB 533MHz CompactPCI CPU 6U 4HP 2 x 1GB DDR2 Memory Dual Channel Mode Capable On Board CompactFlash Card or 1 8 Inch Hard Disk Mezzanine Module Option on Board Dual 2 5 Inch SATA Hard Disk Mezzanine Module Mezzanine Expansion Board and Rear I O Transition Module Options ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board CD3 JIVE with C14 SATA EKF 10 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board CD3 JIVE with on Board CompactFlasch Module amp DB1 FALCON PMC Module CD3 JIVE with PMC Mezzanine Module DB1 FALCON amp 1 8 Inch Hard Disk Drive ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board CD3 JIVE w PMC Module C14 SATA 4HP Front Panel CD3 JIVE w PMC Module 8 C14 SATA 8HP Front Panel EKF ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board wd The CD3 JIVE comes with a CompactFlash adapter module which is suitable to hold a silicon memory CF card or Microdrive hard disk If the CD3 JIVE is accompanied by a mezzanine expansion module such as the CCA LAMBADA or CCB BOSSANOVA the position of the CompactFlash adapter module changes to the mezzanine card Ki EKF CompactFlash Adapter Module for CD3 JIVE 1 8 Inch on board Hard Disk Module for CD3 JIVE 4 Optionally an on board 1 8 inch hard disk module is available When ordered it replaces th
39. l Elements CDT RIO Back Panel Elements EKF do not scale draft only ekf com LAA gt N N E OPTION OS E rs xdi T G LE e S A T A E A e C T T CDT RIO Mezzanine EKF ekf com ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board Video Monitor Connector DVI 1 DVI I 17 TXO 9 TX1 TX 18 pi 10 TKI 4 2 TX2 F El o 19 GND 11 GND 3 GND EE 20 12 4 E E E m m 21 13 5 Nung 22 GND 4 poe PON v DE Sa E E NH 2 23 TXC 15 GND 7 DDC SDA 2 E El x mm 24 TXC 16 DVI HP 8 VSYNC c3 BLUE c1 RED gt C6 GND C5 GND c4 HSYNC 2 GREEN 2 D 5V protoected by a PolySwitch Fuse 0 75A 2 This signal may be switched either to the front connector or to the rear I O adapter CDT RIO For attachment of an ordinary analog RGB monitor to the DVI I receptacle there are both adapters and also adapter cables available trom DVI I to the HD SUB15 connector Attachment of digital monitors flat panel displays should be done by means of a DVI to DVI cable single link style cable is sufficient EKF 48 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board Video Monitor Connector DVI 2 DVI D DVI 2 DVI D x 17 TXO 9 TX1 1 TX2 18 To 1 TXIT 2 DO WW 19 GND 11 GND 3 GND E 20 D 4 mu EN 13 5 an 22 GND 14 DDC POW 6 DDC SCL s 23 TXC 15 GND 7 DDC SDA
40. m User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board Related Documents gt For information about the CCA LAMBADA refer to the CCA Technical Information Manual available at http www ekf com c ccpu cca cca_ tie pdt gt For information about the CCB BOSSANOVA refer to the CCB Technical Information Manual available at http Awww ekf com c ccpu ccb ccb_tie pdt gt For information regarding the CDT RIO rear WO transition module please read the CDT Technical Information Manual available at http www ekf com c ccpu cd3 cdt tie pdf gt For ordering information refer to document CD3 JIVE Product Information available at http www ekt com c ccpu cd3 cd3_pie pdt CompactPCI CompactPCI Specification PICMG 2 0 R3 0 Oct 1 1999 www picmg org PCI Express PCI Express Base Specification Revision 1 0a April 15 2003 www pclsig com Ethernet IEEE Std 802 3 2000 Edition standards ieee org USB Universal Serial Bus Specification www usb org Serial ATA Serial ATA Revision 2 5 www serialata org CompactFlash CF and CompactFlash Specification Revision 2 0 www compacttlash org PMC Common Mezzanine Card Family P1386 2 4a amp P1386 1 2 4 www leee 0rg Nomenclature Signal names used herein with an attached designate active low lines Trade Marks Some terms used herein are property of their respective owners e g gt Intel Pentium Celeron Pentium M Core Duo Intel gt CompactPCI PICMG gt PCI Exp
41. mper J COM which forces the ADM211E into its shutdown mode COM RS 232 EIA TIA 232 Male D Sub 9 e 261 02 009 23 1 DCD DSR 6 2 RXD RTS 7 7 3 TXD CTS 8 4 DTR RI 9 5 GND Stuffing of connectors and other components described on this page are highly custom specific Please discuss your actual needs with EKF sales ekf de before ordering EKF 53 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board Internal Connectors Expansion Interface Header P EXP GND 1 2 3 3V PCI CLK 3 4 PCI_RST gt LPC ADO 5 6 LPC AD1 LPC AD2 7 8 LPC AD3 LPC FRM 9 10 LPC DRQ GND 11 12 3 3V S SERIRO 13 14 EXP PMEZ EXP SMI 15 16 SIO CLK14 FWH IDO 17 18 FWH INIT ICH RCINZ 19 20 ICH A20GATE GND 21 22 5V x USB EXP P2 23 24 USB EXP P1 USB EXP P2 25 26 USB EXP P1 USB EXP OC 27 28 H DBRESET SIO GPIO16 29 30 SIO GPIO17 GND 31 32 5V 40 AC97 SDOUT 33 34 AC97 SDINO 1227 8 T TT Ta AC97 RST 35 36 AC97 SYNC AC97 BITCLK 37 38 AC97 SDIN1 SPEAKER 39 40 12V VCCRTC This pin is connected to VCCRTC alternatively it connects to 12V via a 0 Ohm jumper The expansion interface header is available on both sides of the board top and bottom in order to provide attachment of the CCA LAMBADA either to the left or to the right side of the CD3 JIVE WARNING Neither the 3 3V pin nor the 5V pin nor the 12V pin are protected against a short circuit situation This connector therefo
42. nents could explode A and cause personal injury EKF 37 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board EMC Recommendations C In order to comply with the CE regulations for EMC it is mandatory to observe the following rules The chassis or rack includino other boards in use must comply entirely with CE Close all board slots not in use with a blind front panel Front panels must be fastened by built In screws Cover any unused front panel mounted connector with a shielding cap External communications cable assemblies must be shielded shield connected only at one end of the cable Use ferrite beads for cabling wherever appropriate Some connectors may require additional isolating parts Reccomended Accessories Blind CPCI Front EKF Elektronik Widths currently available Panels 1HP 5 08mm with handle 4HP 8HP without handle 2HP 4HP 8HP 10HP 12 HP Ferrit Bead Filters ARP Datacom Ordering No 63115 Dietzenbach 102 820 cable diameter 6 5mm 102 821 cable diameter 10 0mm 102 822 cable diameter 13 0mm Metal Shielding Conec Polytronic Ordering No Caps 59557 Lippstadt CDFA 09 165 X 13129 X DB9 CDSFA 15 165 X 12979 X DB15 CDSFA 25 165 X 12989 X DB25 EKF 38 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board Installing or Replacing the Memory Modules Note If you decide to replace the memory observe the precautions in B
43. nes in a non PXI environment GPIO Signals As an alternative the IT8761E GPIO20 21 and GPIO26 27 are also available from the rear WO connector J4 stuffing option by means of a resistor network In addition the IT8761E GPIO22 GPIO24 are permanently wired to J4 GPIO25 is default used for switching SATA signals between CompactPCI J3 and CompactPCI J5 As a stuffing option GPIO25 could be wired to J4 In addition to the GPIO lines listed above available for rear I O on J2 and or J4 the expansion connector P EXP provides another two GPIO lines available for user specific application The 5V TTL signals sio gpio16 17 are controlled by the on board SIO IT8761E with an internal 50kQ PU resistor and capable of sinking 24mA each EKF 33 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board Rear I O Options Optionally the CD3 JIVE can be used for rear I O with respect to the following functions 2 x Gigabit Ethernet J3 4 x SATA up to 4 x SATA 1 x eSATA J3 Analog video VGA J4 4 x USB J4 PS 2 keyboard amp mouse J4 COM1 TTL level J4 GPIO J4 PMC mezzanine module rear I O J5 Y V YV V Y YV Y y The analog graphics and the Gigabit Ethernet port 1 lines are routed to signal multiplexers on the CD3 JIVE These analog signal switches controlled by the BIOS select either the front panel or the rear I O connection This is also true for the SATA channels 0 1 which can either be use
44. oard Real Time Clock The CD3 JIVE has a time of day clock and 100 year calendar integrated into the ICH6 A battery on the board keeps the clock current when the computer is turned off The CD3 uses a BR2032 lithium battery soldered in the board giving an autonomy of more than 3 years Under normal conditions replacement should be superfluous during lifetime of the board Universal Serial Bus USB The CD3 JIVE is provided with eight USB ports all of them are USB 2 0 capable Two USB interfaces are routed to front panel connectors two ports are feed to the expansion board interface connectors P EXP and four ports are optionally available for rear WO across the J4 P4 CompactPCI connector The front panel USB connectors can source up to 0 5A 5V each over current protected by two electronic switches Protection for the USB ports on the expansion interface and on the rear I O connector is located on the CCA LAMBADA and the CDT RIO respective The USB controllers are integrated into the ICH6 LPC Super l O Interface In a modern system legacy ports as PS 2 keyboard mouse COM1 2 and LPT have been replaced by USB and Ethernet connectivity The 1 4MB floppy disk drive has been swapped against CD RW drives attached to a SATA connector or USB memory sticks Hence the CD3 JIVE is virtually provided with all necessary I O ports However for compatibility purposes the CD3 JIVE is additionally equipped with a simple Super I O chip for optional
45. oard has no power JRIC NA 1 RICRST 2 GND EKF 240 1 02 ekf com Jumper OFF No RTC reset performed Jumper ON RTC reset performed This setting is the factory default EKF 45 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board Connectors Caution Some of the internal connectors provide operating voltage 3 3V and 5V to devices inside the system chassis such as internal peripherals Not all of these connectors are overcurrent protected Do not use these internal connectors for powering devices external to the computer chassis A fault in the load presented by the external devices could cause damage to the board the interconnecting cable and the external devices themselves EKF 46 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board Front Panel CD3 JIVE Back Panel CDT RIO CD3 JIVE A II AN AY D V D C D V O USB G ITI UJ CD mm UG gt Em EKF CD3 JIVE A mz z mNNIZ OFT SE EH G U Emm u G rm u o gt gt a CD3 JVE A m Z ENNS OS OU mm mm UC gt gt ma CD3 JIVE DVI 8 VGA CD3 JIVE DVI amp COM ae CJ m G Iamo gt gt gt Oo O anl O O HOD CDT RIO Standard EKF ekf com CD3 JIVE Front Pane
46. ocessors above give also the maximum power consumption TDP Thermal Design Power of a particular processor Fortunately the power consumption is by far lower when executing typical Windows or Linux tasks The heat dissipation increases when e g rendering software like the Acrobat Distiller is executed The Pentium M processors support Intel s Enhanced SpeedStep technology This enables dynamic switching between multiple core voltages and frequencies depending on core temperature and currently required performance The processors are able to reduce their core speed and core voltage in up to 8 steps down to 600MHz This leads to an obvious reduction of power consumption max 7 5W 0600MHZ resulting in less heating This mode of lowering the processor core temperature is called TM2 TM Thermal Monitor Note that TM2 is not supported by Celeron M processors Another way to reduce power consumption is to modulate the processor clock This mode TM1 is supported also by the Celeron M processors and is achieved by actuating the Stop Clock input of the CPU A throttling of 5096 e g means a duty cycle of 5096 on the stop clock input However while saving considerable power consumption the data throughput of the processor is also reduced The processor works at full speed until the core temperature reaches a critical value Then the processor is throttled by 5096 As soon as the high temperature situation disappears the throttling will be disabled
47. pa KG 1 DVI HP 8 C3 c1 c6 GND c5 GND c4 C2 Y 5V protoected by a PolySwitch Fuse 0 754 EKF 49 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board Video Monitor Connector VGA As an option the CD3 JIVE can be equipped with a legacy VGA connector High Density D Sub 15 position female connector The VGA connector replaces the DVI 1 DVI I receptacle and the digital video interface therefore is not available with this option VGA Option 1 RED 2 GREEN 3 BLUE 2 4 NC 5 GND 6 GND 7 GND 8 GND 4 9 DDC POW 10 GND 11 NC 17 DOC SDA 13 HSYNC 14 VSYNC 15 DDE SEL 5V protoected by a PolySwitch Fuse 0 75A 2 This signal may be switched either to the front connector or to the rear I O adapter CDT RIO USB Connectors USB Ports 1 2 POW 2 USB DATA NEG 3 USB DATA POS Y 5V protected by an Electronic Fuse 0 5A 4 GND EKF 50 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board Ethernet Connectors G ETH1 2 RJ45 2 2 4 9 10 2 055 8 This signal may be switched either to the front connector or to the rear I O adapter CDT RIO NC1 MDXO0 NC1 MDXO NC1 MDX14 NC1 MDX2 NC1 MDX2 NC1 MDX1 NC1 MDX3 NC1 MDX3 NC2_MDXO NC2_MDXO NC2_MDX1 NC2_MDX2 NC2_MDX2 NC2 MDX1 NC2 MDX3 NC2 MDX3 The upper green yellow dual LED signals 1Gbit s when lit yellow 1
48. rd carefully be sure not to damage components mounted on the bottom side of the board by scratching neighboured front panels e A card with onboard connectors requires attachment of associated cabling now Lock the ejector lever fix screws at the front panel top bottom Retain original packaging in case of return EKF 36 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board Removing the Board Warning This procedure should be done only by qualified technical personnel Disconnect the system from its power source before doing the procedures described here Failure to disconnect power or telecommunication links before you open the system or perform any procedures can result in personal injury or equipment damage Typically you will perform the following steps Warning Switch off the system remove the AC power cord Attach your antistatic wrist strap to a metallic part of the system A Identify the board be sure to touch the board only at the front panel unfasten both front panel screws top bottom unlock the ejector lever Remove any onboard cabling assembly Activate the ejector lever Remove the card carefully be sure not to damage components mounted on the bottom side of the board by scratching neighboured front panels Store board in the original packaging do not touch any components hold the board at the front panel only Do not expose the card to fire Battery cells and other compo
49. re should be used only for attachment of an expansion board like CCA LAMBADA The maximum current flowing across these pins should be limited to 2A per power rail EKF 54 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board ATA IDE Header P IDE IDE RSTZ 1 2 GND IDE D07 3 4 IDE DO8 IDE DOG 5 6 IDE D09 IDE DOS 7 8 IDE D10 IDE D04 EET IDE D11 IDE DO3 GREG IDE D12 IDE D02 B i IDE D13 IDE DO GRO IDE D14 S IDE DOO 17 18 IDE D15 GND ig 28 3 3V n IDE DREO 20 22 3 3V IDE_IOW 28 24 GND IDE_IOR 25 GND IDE IORDY ay 38 5V IDE DACK 29 45V IDE IRQ INT 15 a 22 GND ag IDE A1 SE WEN IDE CBLID 1 27mm IDE AO 35 36 IDE A2 pose IDE CS1 z IDE CS3 IDE ACT sol G GND Like the expansion interface header the IDE connector is also available on both sides of the board WARNING Neither the 3 3V pin nor the 5V pin are protected against a short circuit situation This connector therefore should be used only for attachment of the C10 CFA adapter or an expansion board like CCA LAMBADA The maximum current flowing across these pins should be limited to 2A per power rail EKF 55 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board Speaker Header J SPK JSPK PS X 1 5V 2 Speaker EKF 240 1 02 ekf com WARNING The 5V pin is protected against a short circuit situation by a 0 1A PolySwitch The JSPK connector should be used
50. rear I O of PS 2 keyboard mouse and COM TTL level only across the J4 P4 CPCI connector COM1 is also available as front panel connector option if the DVI 2 video connector would not be needed requires a SA type PHY module attached to P SA The Super I O controller resides on the local LPC bus LPC Low Pin Count interface standard which is a serialized ISA bus replacement As an alternative EKF offers the CCA LAMBADA or CCB BOSSANOVA mezzanine expansion modules to the CD3 JIVE featuring all classic Super I O functionality The CCA LAMBADA is a 3U Eurocard with a 4HP single width front panel Access to the connectors PS 2 mouse keyboard COM USB and audio in out is given directly from the front panel The CCA LAMBADA connects to the CD3 JIVE across the connector P EXPT or P EXPB hence the CCA LAMBADA can be attached either to the top or to the bottom of the CD3 JIVE EKF 30 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board Reset Watchdog The CD3 JIVE is provided with two supervisor circuits to monitor the supply voltages 1 8V 3 3V 5V and to generate a clean power on reset signal The reset manual push button is situated at the front panel The button is indent mounted behind the front and requires a tool e g pen to be pressed preventing from being inadvertently activated The push button reset signal is routed across a PLD programmable logic device and could be inhibited on customers req
51. ress PCI SIG gt Windows 2000 Windows XP Microsoft gt EKF ekf system EKF EKF does not claim this list to be complete Legal Disclaimer Liability Exclusion This manual has been edited as carefully as possible We apologize for any potential mistake Information provided herein is designated exclusively to the proficient user system integrator engineer EKF can accept no responsibility for any damage caused by the use of this manual EKF 5 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board CD3 JIVE Features Feature Summary Feature Summary CD3 JIVE Double size CompactPCI style Eurocard 160x233mm front panel width 4HP 20 3mm Form Factor Processor Chipset Memory Video USB Ethernet Serial Port COM Mezzanine Facility PMC Module or SATA Storage Module EKF Designed for Intel Pentium M Micro FC BGA 479 processors 90nm Dothan maximum junction temperature 100 C gt CD3 2 1 0GHz ULV Celeron M Dothan 373 400MHz FSB 512KB L2 cache 5W gt CD3 3 1 4GHz LV Pentium M Dothan 738 400MHz FSB 2MB L2 cache 10W gt CD3 6 2 0GHz Pentium M Dothan 760 533MHz FSB 2MB L2 cache 27W Intel 1915 chipset Alviso consisting of gt 82915GM Graphics Memory Controller Hub GMCH with Intel Graphics Media Accelerator GMA 900 gt 82801FB I O Controller Hub ICH6 gt 82802 Compatible Firmware Hub FWH Dual 200 pin
52. s have pullup resistors of approx 50kQ within the SIO EKF AA ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board Configuration Jumpers Reset Jumper BIOS CMOS RAM Values J GP The jumper J GP is used to bring the contents of the battery backed CMOS RAM to a default state The BIOS uses the CMOS to store configuration values e g the actual boot devices Using this jumper is only necessary if It is not possible to enter the setup of the BIOS To reset the CMOS RAM mount a jumper on J GP and perform a system reset As long as the jumper is stuffed the BIOS will use the default CMOS values after any system reset To get normal operation again the jumper has to be removed JGP AS 1 GPl6 2 GND EKF 240 1 02 ekf com Jumper OFF No CMOS reset performed Jumper ON CMOS reset performed This setting is the factory default Reset Jumper ICH6 RTC Core J RTC The jumper J RTC is used to reset the battery backed core of the ICH6 This effects some registers within the ICH6 RTC core that are important before the CPU starts its work after a system reset Note that J RTC will neither perform the clearing of the CMOS RAM values nor resets the real time clock To reset the RTC core the board must be removed from the system rack Short circuit the pins of J RTC for about 1 sec After that reinstall the board to the system and switch on the power It is important to accomplish the RTC reset while the b
53. se values against programmable upper and lower boundaries As soon as a measurement violates the allowed value the LM87 may request an interrupt via the GPI 11 of the ICH6 EKF 41 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board GPIO Usage GPIO Usage ICH6 GPI 0 GPI 1 GPI 2 GPI 3 GPI 4 GPI 5 GPI 6 GPI 7 GPI 8 GPI 9 GPI 10 GPI 11 GPI 12 GPI 13 GPI 14 GPI 15 GPO 16 GPO 17 GPO 18 om O RM O GPO 19 GPO 20 GPO 21 GPO 23 O GPIO 24 O GPIO 25 O GPI 26 EKF 5V 5V 5V 5V 5V 5V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V BESA 5 3 3V 3 3V 3 3V 3 3V 3 3V EEN 3 3V 3 3V 3 3V 3 3V 3 3V CPCI_REQ6 CPCI_REQ5 CPCI INTP CPCI ENUM CPCI FALZ CPCI DEG GP JUMP CPCI SYSENZ N A USB OCA USB OC5 HM INTZ EXP PMEZ EXP SMIZ USB OC6 USB OC7 CPCI GNT6 CPCI GNT5 GP LED ETH Switch PLD SCL PLD SDA CPCI INTS EN CPCI SMB EN CPCI CLK EN N A my CompactPCl Bus Request Line 6 CompactPCI Bus Request Line 5 CompactPCI Interrupt Request Line INTP CompactPCl System Enumeration Line ENUM CompactPCI Power Failure Line FAL CompactPCl Power Degeneration Line DEG BIOS CMOS Values Reset Jumper J GP CompactPCl System Slot Enable Line SYSEN Not used on CD3 fixed to GND USB Port 4 Overcurrent Detect Line USB Port 5 Overcurrent Detect Line Hardware Monitor LM87 Interrupt Line Expansion Interface PM
54. separate 3 3 KO resistor Me is fixed to 3 3V on CD3 JIVE PMC Mezzanine MJ1 GND INTB INTD GND CLK GND REQ ve AD28 AD25 GND AD22 AD19 Oe FRAME GND DEVSEL GND Reserved PAR VI O AD12 ADO9 GND AD06 AD04 VI O gt ADO2 ADOO GND 12V INTA INTC 5V Reserved 3 3V GND GNT FSV AD31 AD27 GND C BE3 AD21 5V AD17 GND IRDY F 5V LOCK Reserved GND AD15 AD11 5V C BEO ADO5 GND ADO3 ADO 5V REQ64 Notes This pin position is showing the actual interrupt assignment on the CD3 JIVE local PCI bus 66 O N 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board PMC Mezzanine MJ2 1 12V 2 3 4 5 GND 6 7 GND Reserved 8 9 SERIRQ Reserved 10 11 BUSMODE2 3 3V 12 13 RST BUSMODE3 14 5 3 3V BUSMODE4 16 17 PME GND 18 19 AD30 AD29 20 21 GND AD26 22 23 AD24 3 3V 24 25 IDSEL AD23 26 2 3 3V AD20 28 29 AD18 GND 30 31 AD16 C BE2 32 33 GND Reserved 34 35 TRDY 3 3V 36 37 GND STOP 38 39 PERR GND 40 41 3 3V SERR 42 43 C BE1 GND 44 45 AD14 AD13 46 47 M66EN AD10 48 49 AD08 3 3V 50 51 AD07 Reserved 52 53 JE ESSI Reserved 54 55 Reserved GND 56 57 Reserved Reserved 58 59 GND Reserved 60 61 ACK644 3 3V 62 63 GND Reserved 64 BUSMODE 4 2 signals coded according to P1
55. stems enhancements gt 8Mbit Flash memory gt Updates available from website ekf com gt Intel graphics drivers gt Intel networking drivers 5 D VWIAO TW 5V 0 25V 0 15V Board MaxPower WinXP Idle MaxPower WinXP Idle CD3 2 JIVE tbd tbd tbd tbd CD3 3 JIVE tbd tbd tbd tbd CD3 6 JIVE 2 A 2 3A 5 5A 1 6A gt Operating temperature 0 C 70C CPU dependent gt Storage temperature 40 C 85 C max gradient 5 C min gt Humidity 5 95 RH non condensing gt Altitude 300m 3000m gt Shock 15g 0 33ms 6g 6ms gt Vibration 1g 5 2000Hz gt EN55022 EN55024 EN60950 1 UL60950 1 IEC60950 1 gt 2002 95 EC RoHS 7 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board Feature Summary CD3 JIVE MTBF tbd Performance Rating Board Processor CPU MEM Score Measured with CD3 2 JIVE 1 0GHz ULV Celeron M Dothan 373 tbd PCMark2002 under Windows XP 1GB DDR2 533 CD3 6 JIVE 2 0GHz Pentium M Dothan 760 tbd CD3 3 JIVE 1 4GHz LV Pentium M Dothan 738 tbd Subject to technical changes EKF 8 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board Short Description CD3 JIVE Scalable from the ULV Celeron M processor up to the 2 0GHz Pentium M and provided with 2GB dual channel capable DDR2 RAM the CD3 JIVE is a versatile 6U 4HP double size Eurocard CompactPCI CPU board designed especially for systems which require high performance at low
56. t any time Firmware Hub Flash BIOS The BIOS is stored in an 82802 8Mbit Firmware Hub there are second sources in use with deviant part numbers The firmware hub contains a nonvolatile memory core based on flash technology allowing the BIOS to be upgraded The FWH can be reprogrammed if suitable by a DOS based tool This program and the latest CD3 JIVE BIOS are available from the EKF website Read carefully the enclosed instructions If the programming procedure fails e g caused by a power interruption the CD3 JIVE may no more be operable In this case you would have to send in the board because the BIOS is directly soldered to the PCB and cannot be changed by the user EKF 31 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board Mezzanine Interfaces The PMC mezzanine card socket enables on board expansion of the CD3 JIVE The PMC slot on the CD3 supports a 32 bit 66MHz PCI interface with VI O 3 3V The modules rear UO is wired to the CompactPCI connector J5 Alternatively I O can be obtained via the front panel connector of the module if any As an option the CD3 JIVE is also available with a dual 2 5 inch SATA hard disk add on module C14 SATA which occupies the PMC slot PG Power Good LED The CD3 JIVE offers a software programmable LED located in the reset push button After system reset this LED defaults to signal the board healthy respective power good state This LED changes its f
57. uest An alternative way to generate a system reset is to activate the signal PRST located on CompactPCI connector J2 pin C17 Pulling this signal to GND will have the same effect as to push the handle s red push button The healthy state of the CD3 JIVE is signalled by the LED PG Power Good located in the front panel As soon as this LED begins to shine all power voltages are within their specifications and the reset signal has been deasserted An important reliability feature is the watchdog function which is programmable by software The behaviour of the watchdog is defined within the PLD which activates deactivates the watchdog and controls its time out period The time out delay is adjustable in the steps 2 10 50 and 255 seconds After alerting the WD and programming the time out value the related software e g application program must trigger the watchdog periodically All watchdog related functions are made available by calling service requests within the BIOS The watchdog is in a passive state after a system reset There is no need to trigger It at boot time The watchdog is activated on the first trigger request If the duration between two trigger requests exceeds the programmed period the watchdog times out and a system reset will be generated The watchdog remains in the active state until the next system reset There is no way to disable it once it had been put on alert whereas It is possible to reprogram its time out value a
58. unction by calling an appropriate BIOS request and Is then controlled by software only The PG LED remains in the programmable state until the next system reset occurs HD Hard Disk Activity LED The CD3 JIVE offers a LED marked as HD placed within the front panel This LED signals activity on any device attached to the SATA or the IDE ports GP General Purpose LED A second programmable LED can be also observed trom the front panel The status of the GP LED is controlled by the GPO18 output of the ICH6 Setting this pin to 1 will switch on the LED As of current the GP LED is not dedicated to any particular hardware or firmware function this may change in the future Hot Swap Detection The CD3 JIVE uses a LTC1646 hot swap power controller The main task of this device is a controlled switching of the board power supplies On board insertion the various power planes on the board 3 3V 5V 12V are ramped up slowly to avoid too large voltage drops within the system When all voltages have reached their nominal values the controller asserts the CompactPCI signal HEALTHY connector J1 pin B4 Electronic circuit breakers protect 3 3V and 5V against overcurrent fault conditions As soon as the current on these supplies exceed a value of 11A the power of all supplies including 12V are switched off and the fault is flagged to the system by deasserting the HEALTHY signal The CompactPCl specification added the signal ENUM to the P
59. wer O EKF 17 Basic Hot Swap Controller PICMG 2 1 SATA 0 1 HMC Rear IYO CPCI Power 46 CompactPCI UJ CompactPCI Ul ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board Top View Component Assembly CD3 JIVE A EE EKF ekf com Red Outline PMC Mezzanine Module Option Yellow Outline Dual SATA Hard Disk Drive Uu uj uu EN esa LOOMI IC E LRST wamaqa EXP EE e 1 m lo C E5 EKF CD3 JIVE ekf com EKF 18 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board CDT RIO Rear I O Transition Module Short Description Available as a rear I O expansion board to the CD3 JIVE CPU card the CDT RIO is provided with several I O port connectors to be used either in addition to the CD3 JIVE front panel connectors or alternatively Being mainly a passive rear I O transition module groups of signals from the CD3 JIVE CPU board are passed across the CompactPCI J3 5 P3 5 connector to the CDT RIO Some of the data lines are available locally on the CDT board for system internal wiring only while other connectors such as VGA Video and Gigabit Ethernet are mounted into the back panel for external use USB and SATA eSATA channels are provided both on board and externally Typically the CDT RIO Is equipped with a 4 HP rear panel 20 3mm width As a custom specific option an 8 HP
60. y means of special mezzanine PCB C24 GBE replaces 277 DVI Up to 2 x GbE rear I O according to PICMG 2 16 across J3 Up to 2 x GbE rear I O alternatively accessible via RJ45 jacks from the CDT RIO back panel Jumbo Frame support up to 9KB Y Y Y Y Y Y y Available as an option D Sub 9 pin replaces DVI D connector RS 232E or RS 485 selectable Optional usage of both gt 1 Slot for a PMC module I O from the front panel and rear WO across J5 dedicated PCle to PCI bridge gt On board Serial ATA dual 2 5 inch hard disk module C14 SATA mounts on top of the PMC module space 6 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board Proprietary Expansion Interface Parallel ATA IDE Serial ATA CompactPCI Hot Swap Funktion Rear I O J3 P3 J5 P5 BIOS Drivers All Major OS Typical Power Requirements Thermal Conditions Environmental Conditions EC Regulations EKF Feature Summary CD3 JIVE gt On board LPC USB AC97 Super l O USB and audio expansion interface connector gt Suitable CCA LAMBADA 3U companion board available Single channel IDE I F 2 devices gt Ultra ATA 100 connector handover to CCA LAMBADA CCB BOSSANOVA mezzanine expansion board with optional on board 2 5 inch IDE hard disk drive or external device gt CompactFlash socket for a CFA ATA memory card or Microdrive C10 1 CFA gt Option 1 8 inch on board hard disk module replaces CompactFlash f
61. yau as a h a h KUN AL di Meee eee Gi di u R a NE o de dil dir k ee 34 Installing and Replacing Components 35 Before YOU BEGIN i kk kk kk kk KK KK KI KK KK K K KI KI KK KI KI KK KI KI KK KI KI KI KI KI KI KI KI KI KI KIRI KI KI KK K 35 Installing the Board 36 Removing the Board 1 0 0 37 EMC RecommendationsS KK KI KIR KI KI PE RUE UR E 38 2 ekf com User Guide CD3 JIVE Advanced CompactPCI 6U Pentium M CPU Board Installing or Replacing the Memory Modules 39 Replacement of the Battery 0 39 Technical Reference K V eee eee eee ra 40 Local PCI Devices 40 Local SMB Devices 41 Hardware Monitor LM87 41 az D 42 EIS Ee Jaza EEN 42 GPIO Usage PWH e Ae a kk a Ze a kad A e bu ot dian d fh Qanta auch det Q disa d del 43 GRO USOS s pees agan s TEES 44 Configuration JumperS x vas kk kk kk KK KK KK RU KI KI KI K K FEES KI KI KIIR KI KI RIK KIRI KIRI K KK Ag E 45 Reset Jumper BIOS CMOS RAM Values J GP A5 Reset Jumper ICH6 RTC Core U RTC 45 se ia EE E EE E EE E EE EE eee eee oe r Fp i 46 Front Panel CD3 JIVE Back Panel CDT RI

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