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DPV 11 serial synchronous interface user guide

1. A A mm lt lt lt lt 205 405 Ur BIT BEQ BIS BIT BEQ BIS BIT BEQ BIS MOV BR END CLEAR R4 FOR RETURN CODES D RDBF RS R3 ADDRESS OF RECEIVER CSR SEL 2 0505 R3 205 MC DSR R4 15 THE DATA SET READY NO YES SET INDICATOR IN R4 4 we ue IS THE PHONE RINGING NO YES SET INDICATOR IN R4 DSRING R3 49 MC RNG gt w uo x DSCARY R3 15 THERE CARRIER PRESENT 685 NO POST COMPLETE MC CAR R4 5 YES SET INDICATOR IN R4 4 SP RETURN RESULTS IN SAVED R4 CTLCMP POST CONTROL FUNCTION COMPLETE TITLE DPV BYTE ORIENTED DPV 11 DEVICE DRIVER MODULE IDENT X00 COPYRIGHT C 1980 BY DIGITAL EQUIPMENT CORPORATICN MAYNARD MASS EXAMPLE OF AN APPLICATION RSX 11M BYTE ORIENTED DPV 11 DEVICE DRIVER lt o Se MCALL SINTSX SINTXT INHIBS ENABLS MCALL CCBDFS TM
2. 3 19 Receive Data oic rati osse Pots 3 19 Transmit ote 3 20 INTERRUPT VECTORS ca ADR EUER 3 21 iii APPENDIX A APPENDIX B APPENDIX C APPENDIX D GLOSSARY Figure No PY ON Un D RU n CONTENTS Cont Page DIAGNOSTIC SUPERVISOR SUMMARY INTRODUCTION uu cain diti toten 1 VERSIONS OF THE DIAGNOSTIC SUPERVISOR 1 LOADING AND RUNNING A SUPERVISOR DIAGNOSTIC 1 SUPERVISOR COMMANLDS RO ne SA hes A 3 Command SS WIE CS edad I ln te 4 Control Escape Characters Supported cei eee eee in ecd epe bas A 4 5 USYNRT DESCRIPTION IC DESCRIPTIONS GENERA Losa ibid DERE 1 DC003 INTERRUPT CHIP din etd UE C 1 DC004 PROTOCOL CHIP C 3 DCODS BUS TRANSCEIVER CHIP eet bitrate tot Desde C 3 261532 QUAD DIFFERENTIAL LINE 222 C 6 8640 UNIBUS nc elt ts C 6 882 TL IAIN A E rec C 6 9636A DUAL LINE DRIVER o C 6 9638 DUAL DIFFERENTIAL LINE eR C 6 PROGRAMMING EXAMPLES ILLUSTRATIONS Title Page DPV Ty Ste Mic caste tantra Ska ha ubus
3. _ e TISPAD CLRB MOV MOV BR D FLAG D TCNT R5 R5 TXABRT R4 TISEXT ESET THE DEVICE FLAG BYTE EXT STATE SEND SECOND PAD ET TXABRT TO SEND A PAD e eo mo e LIT o z lt _ 0 TISCLR TISRTS R5 NEXT STATE DROP REQUEST TO SEND D 7 TISCEX MOV TXABRT R4 SETUP TO SEND ANOTHER ABORT CHAR BIC R4 DISABLE THE TRANSMITTER BR TISEXT CURRENT STATE DROP REQUEST TO SEND EXIT TISRTS BIT DC HDX D DCHR D TCNT RS HALF DUPLEX CHANNEL BEQ TISDON NO LEAVE RTS ACTIVE BIC DSRTS 5 R4 DROP REQUEST TO SEND LINE BR TISDON POST TRANSMIT COMPLETE CURRENT STATE TRANSMITTER DATA UNDERRUN TISLAT MOV amp TISDON R5 NEXT STATE RE TRANSMIT MOVB DD ABT D FLAG D TSPA RS THIS FRAME WAS ABORTED INC D TURN D TSPA R5 COUNT THE ERROR EVENTS BR TISCLX SEND PAD DISABLE TRANSMITTER CURRENT STATE IDLE FLAGS BETWEEN FRAMES TISFLG MOV TXSTRM R4 CLEAR TXENDM IDLE FLAGS MOVB DD ACT D FLAG D TCNT RS TRANSMITTER IS ACTIVE M 550 ca POMA CURRENT STATE POST COMPLETE OR RE TRANSMIT CEN NU Se Se dl ros uides TISDON ADD D TPRI D TCNT R5S ADJUST LINE TABLE POINTER BIC TXITEN
4. 1 2 Electrical SPECI CAtiOMs aid 1 3 Performance Parameters imita 1 3 DEVIS CONFIGURATIONS vis RSS RS ii la 1 3 STANDARDS OVERVIEW 1 3 INSTALLATION INTRODUCTION Sen ne E 2 1 UNPACKING AND 2 1 PRE INSTALLATION REQUIREMENT S 2 1 INSTALLATION Sua e Gt leno 2 6 Verification of Hardware Operation 2 7 Connection to External Equipment Link Testing 2 8 TEST ONNECTORS ei tus tuu ei audiat eise tidie ers 2 8 REGISTER DESCRIPTIONS AND PROGRAMMING INFORMATION INTRODUCTION 256 ecce eii 3 1 DPV11 REGISTERS AND DEVICE ADDRESSES 3 1 REGISTER BIT 55 2 2 24 2 2 1 3 2 Receive Control and Status Register 3 2 Receive Data and Status Register 3 2 Parameter Control Sync Address Register PCSAR 3 2 Parameter Control and Character Length Register PCSCR 3 2 Transmit Data and Status Register TDSR 3 2 DATA TRANSFERS
5. VEC RQSTB BDINL INITOL BINIT L BIAKOL BIAKI L RQSTA H ROSTB H ENA ST H ENB ST H Table C 1 DC003 Pin Signal Descriptions Description Interrupt Vector Gating Signal This signal gates the appropri ate vector address onto the bus and forms the bus signal BRPLY L Not used in the DPV11 Vector Request B Signal When asserted this signal indicates RQST B service vector address is required When negated it indicates RQST A service vector address is required VECTOR H is the gating signal for the entire vector address VEC RQST B H is normally bit 2 of the address Bus Data In THE BDIN signal always precedes a BIAK sig nal Initialize Out This is the buffered BINIT L signal used in the device interface for general initialization Bus Initialize When asserted this signal brings all drive lines to their negated state except INITO L Bus Interrupt Acknowledge This signal is the daisy chained signal that is passed by all devices not requesting interrupt ser vice see BIAKI L Once passed by a device it must remain passed until a new BAIKI L is generated Bus Interrupt Acknowledge This signal 15 the processor s re sponse to BIRQ L true This signal is daisy chained such that the first requesting device blocks the signal propagation while nonrequesting devices pass the signal on as BIAKO L to the next device in the chain The leading edge of BIAKI L causes BIRQ L to be unass
6. DISABLE TXDONE INTERRUPTS MOV SP R4 RESTORE R4 FOR PRIORITY DROP SINTSX SINTSV W O R4 SAVED POPS R5 MOV R3 SP SAVE AN ADDITIONAL REGISTER MOV R5 R4 ACTIVE CCB ADDRESS TO R4 CLR R5 THIS CCB IS NO LONGER ACTIVE BITB DD ABT D FLAG D TCBQ R5 WAS THE FRAME ABORTED BNE TRSTRT YES SETUP RE TRANSMISSION TST D KCCB D TCBQ R5 TRANSMIT KILL IN PROGRESS BNE CKILLT YES RETURN CCB S TO THE DLC CLR R3 SET COMPLETION STATUS SUCCESS CALL SDDXMP POST TRANSMIT COMPLETE TO THE DLC MOV R5 R4 FIRST CCB ON SECONDARY CHAIN BEQ TREXIT NONE THERE TRANSMITTER IDLE MOV R4 R5 REMOVE CCB FROM SECONDARY CHAIN CURRENT STATE START UP FRAME TRANSMISSION jim DI oe E O Sr A ee ess TRSTRT CLR R4 CLEAR CCB LINKAGE WORD D 8 MOV TST ADD BISB BICB MOV CLR MOV DF 55 MOV MOV MOV MOVB 1 MOV ENDC ADD TSTB BPL MOV BR a 47 MOV BIS BIS MOV 405 BIS TREXIT MOV ASYRET 2 2 CURRENT CKILLT MOV CKTTiMC BIC MOV CLR 26 MOV MOV CLR CALL MOV RA R5 SETUP AS THE ACTIVE CCB se R5 SKIP BACK OVER D TPRI C FLG1 R4 7 POINT TO THE CCB BUFFER FLAGS RA D FLAG D TPRI R5 i SAVE FLAGS FOR LEVEL 7 USE DD ABT D FLAG D TPRI RS MAKE SURE ABORT FLAG IS OFF SET TRANSMIT BYTE COUNT INITIALIZE D T
7. Receive Data Ready RDATRY Receive Status Ready RSTARY Data Set Change DAT SET CH The signal DAT SET CH only causes an interrupt if bit 5 DSITEN of the RXCSR is also set It is possible that a data set change interrupt could be pending while a receiver interrupt is being serviced or the opposite could be true In either case the hardware ensures that both interrupt requests are recognized NOTE The modem status change circuit interprets any pulse of two microseconds or greater duration as a data set change This ensures that all legitimate transitions of modem status will be detected How ever on a poor line noise may be interpreted as a data set change Software written for the DPV11 must account for this possibility A transmitter interrupt request occurs if Transmit Interrupt Enable TXINTEN is set when Transmit Buffer Empty TBEMTY becomes asserted 3 21 APPENDIX A DIAGNOSTIC SUPERVISOR SUMMARY A 1 INTRODUCTION The PDP 11 diagnostic supervisor is a software package that performs the following functions e Provides run time support for diagnostic programs running on a PDP 11 in stand alone mode Provides a consistent operator interface to load and run a single diagnostic program or a script of programs Provides a common programmer interface for diagnostic development Imposes common structure upon diagnostic programs Guarantees compatibility with various load systems such as APT
8. A TISIFL MOV TISTRT R5 NEXT STATE SEND ADDRESS BYTE TISIFX MOV TXSTRM R4 SEND AN SDLC FLAG CHARACTER D 6 TISEXT SEND ADDR BYTE FOLLOWING FLAG e meee DEC MOV MOV BR R5 STISDAT R5 TISEXT D TADC D TCNT R5 R4 5535 DECREMENT COUNT FOR ADDR BYTE SEND ADDR CLEAR TXSTRM NEXT STATE DATA TRANSFER mm ISDAT BMI DEC BMI TISLAT 5 TISEND DF MSSMGE MOV MOV INC MOVB IFT MOV ENDC TISEXT KISAR6 SP R5 KISAR6 R5 R5 R4 SP KISAR6 SP 4 UNDERRUN ABORT AND RE TRANSMIT DECREMENT DATA BYTE COUNT ALL DONE SEND END MSG SEQUENCE 333 SAVE CURRENT MAPPING MAP TO THE TRANSMIT BUFFER ADVANCE THE BUFFER ADDRESS NEXT CHARACTER TO BE SENT RESTORE PREVIOUS MAPPING COMMON LEVEL 7 INTERRUPT EXIT RESTORE R4 EXIT INTERRUPT SERVICE TISEND S TXENDM R4 R5 iTISFLG R5 D FLAG D TSPA R5 TISEXT TISPAD R5 TISEXT TRANSMIT END OF MSG SEQUENCE ADJUST R5 AND CLEAR D TCNT NEXT STATE IDLE FLAGS ASSUMED TEST FOR LINE TURN AROUND NO IDLE THE LINE WITH FLAGS YES SEND PADS THEN DISABLE we wa we o up SEND ABORT AS PAD AFTER
9. REF LABEL RECEIVE ACTIVE TO FORCE RESYNC R3 R5 CLR BIC CLR BIS BIS BR DSABL ADDRESS OF RECEIVE DAT BUFFER ADDRESS OF RPRIM R5 CLEAR FLAGS WORD RRCVEN R3 CLEAR RECEIVE ACTIVE FOR RESYNC RPCNT RFLAG R5 RESET FARTIAL COUNT CS RSN RSTAT RFLAG RS INDICATE RESYNC RINIT R3 ENABLE RECEIVER REXTI FINISH IN COMMON CODE LSB INPUTS STACK CONTAINS lt s C o e e 0 5 INTERRUPTED R5 2 SP INTERRUPTED BIAS 4 SP INTERRUPTED PC 6 SP INTERRUPTED PS OUTPUTS ETC ENABL LSB SDPVTI MOV R4 SP MOV R5 R4 TST RA BMI 10 DEC TCNT TCSR 2 R5 BEQ 20 DF MSSMGE MOV KISAR6 SP MOV R5 KISAR6 IFTF MOVB 8 R5 R4 IFT MOV SP KISAR6 IFTF INC R5 MOV SP R4 SINTXT TRANSMITTER UNDERRUN DISABLE TRANSMITTER INTERRUPTS w SDPVTI DPV11 TRANSMIT INTERRUPT SERVICE THIS ROUTINE IS ENTERED ON TRANSMITTER INTERRRUPT VIA A JSR R5 DPVTI WITH R5 CONTAINING THE ADDRESS OF THE DEVICE LINE TABLE OFFSET BY TCSR R5 ADDRESS OF DEVICE LINE TABLE TCSR SAVE R4 GET TRANSMITTER CSR ADDRESS TEST FOR UNDEZZAUN IF MI UNDERRUN WAIT FOR TIMEOUT DECREMENT COUNT IF EQ BYTE COUNT RUNOUT C9 o w w we o SAVE CURRENT MAPPING MAP TO DATA BUFFER
10. aT 1 1 Jumper Locations odes beta es uita E es 2 4 H3259 Turn Around Test Connector 2 8 RS 423 A with H3259 Test Connector 2 10 H3260 On Board Test Connector a 2 11 DPVI11 Register Configurations and Bit 6 2 0 11 3 3 Receive Control and Status Register RXCSR Format 3 4 Receive Data and Status Register RDSR Format 3 8 Parameter Control Sync Address Register PCSAR 3 11 Parameter Control and Character Length Register PC SCR tud estu end miata apta dore quU Ev aa 3 13 Transmit Data and Status Register TDSR 3 17 Typical XXDP Diagnostic Supervisor Memory Layout A 2 Figure No B 1 B 2 C C 2 C 3 C 4 C 5 C 6 C 7 C 8 Table 2 D D D 62 t D Un P v D ILLUSTRATIONS Cont Title Page Terminal Connection Identification Diagram 2112517 0 0 Variation en tint rene B 2 5025 Internal Register Bit Map 2112517 0 0 Varliation B 3 DEDOS Logic Symbol e VE C 1 DC004 Simplified Logic Diagram l a aras C 4 DC005 Simplified Logic Diagram a aaa C 7 26LS32 Terminal Connection Diagram and Terminal A eer ee C
11. MOV D RDBF R5 R3 RECEIVER CSR ADDRESS SEL 2 TO R3 BIS TXRSET 2 R3 RESET THE DEVICE 1 US SINGLE SHOT ADD D DCHR 2 R5 POINT TO CHARACTERISTICS WORD 1 BIT DC ADR R5 16 BIT STATION ADDRESS BEQ 205 NO SHOULD BE ALL SET SWAB R5 USE THE HIGH ORDER BYTE IN DPV 11 BIC C lt DPADRC gt R5 CLEAR HIGH ORDER BYTE OF D STN WORD BIS INPRM R5 SETUP INITIAL PARAMETERS BIC KDC ADR R5 ADDRESS SIZE NO LONGER SIGNIFICANT 405 60 SSDDIS CMPB BIS BIS BICB BR MOV BR SBTTL MOV BITB BEQ MOV CLR MOVB BR DC SPS R5 SDLC PRIMARY STATION MODE 405 YES FLAGS ARE SETUP AS IS DC SSS R5 SDLC SECONDARY STATION MODE 605 OPERATING MODE INVALID FDPSECS 2 R5 ENABLE STATION ADDRESS CHECKING FDSDTR R3 ASSERT DATA TERMINAL READY LINE DD ENB D FLAG D DCHR 2 R5 LINE IS ENABLED CTLCMP POST CONTROL FUNCTION COMPLETE CS ERR ICS DEV R3 ERROR STATUS INVALID PROTOCOL CTLERR POST CONTROL COMPLETE WITH ERROR 550015 DISABLE THE LINE CS ERR CS ENB R3 ERROR CODE IF NOT STOPPED DD STR D FLAG R5 15 LINE STATE CORRECT CTLERR NO REJECT THE DISABLE D RDBF R5 R3 ADDRESS OF RECEIVER CSR SEL 2 R3 DISABLE RECEIVER TURN DTR OFF DD ENB DD STR D FLAG R5 LINE NO LONGER ENABLED CTLCMP CLEAR CARRY AND EXIT SDMSN SENSE MODEM STATUS O me
12. These lines control the operational of the trans ceiver as follows REC XMIT 0 0 DISABLE BUS and DAT open 0 XMIT DATA DAT to BUS 1 0 RECEIVE BUS to DAT 1 RECEIVE BUS to DAT To avoid tri state overlap conditions an internal circuit delays the change of modes between Transmit data mode and delays tri state drivers on the DAT lines from enabling This action is independent of the disable mode C 8 14 12 11 10 NOTE PIN 1 IS MARKED FOR ORIENTATION NUMBERS INDICATED DENOTE TERMINAL NUMBERS INPUT A INPUT A OUTPUT A ENABLE OUTPUTC INPUT C INPUT C GROUND DYNAN P Q N gt TERMINAL IDENTIFICATION 16 POSITIVE SUPPLY VOLTAGE Vcc 15 INPUT B 14 INPUT B 13 OUTPUT B 12 ENABLE 11 OUTPUT D _ INPUT D 9 INPUT D MK 1340 Figure C 4 26LS32 Terminal Connection Diagram and Terminal Identification C 9 Vcc PIN 8 GND PIN 1 MK 1321 Figure 5 8640 Equivalent Logic Diagram 1Y 1A 1B 2Y 2A 2B GND 1322 Figure 6 8881 Pin Identification 4 8 NOTE NUMBERS IN DENOTE TERMINAL NUMBERS TERMINAL IDENTIFICATION 1 WAVESHAPE CONTROL RISE AND FALL TIME 2 INPUT A 3 INPUT B 4 POWER AND SIGNAL GROUND 5 NEGATIVE SUPPLY VOLTAGE 6 OUTPUT B 7 OUTPUT A 8 POSITIVE SUPPLY VOLTAGE Vcc 1323 Figure C 7 9636A Logic Diagram and Terminal Identification C 11 IN 1 IN 2 GND NOTE NUMBERS
13. _ _ YC eee eee RESERVED XMIT TRANSMIT DATA BUFFER DATA GO LATE AHEAD ABORT START OF MESG MK 1508 Figure 3 1 DPV11 Register Configurations and Bit Assignments Sheet 2 of 2 7 6 5 4 3 2 0 s SF RL ITEN THIS IS RESET BY READING EITHER BYTE OF THIS REGISTER THESE BITS ARE RESET BY READING EITHER BYTE RSDR MK 1327 Figure 3 2 Receive Control and Status Register RXCSR Format 3 4 Table 3 2 Receive Control and Status Register RXCSR Bit Assignments Bit Name Description 15 Data Set Change This bit is set when transition occurs on any of the following DSCNG modem control lines Clear to Send Data Mode Receiver Ready Incoming Call Transition detectors for each of these four lines can be disabled by removing the associated jumper Data Set Change 15 cleared by reading either byte of the RXCSR or by Device Reset or Bus INIT Data Set Change causes a receive interrupt if DSITEN bit 5 and RXITEN bit 6 are both set 14 Incoming Call This bit reflects the state of the modem Incoming Call line Any IC transition of this bit causes Data Set Change bit bit 15 to be asserted unless the Incoming Call line is disabled by removing its jumper This bit is read only and cannot be cleared by soft ware 13 Clear to Send This bit reflects the state of the Clear to Send line of the CTS modem Any transition of this line causes Data Set Change bit 15 to be set unless the
14. ta OUTPUT CHARACTER RESTORE PREVIOUS MAPPING UPDATE BUFFER ADDRESS RESTORE R4 AND WAIT FOR TIMEOUT D 18 105 BISB TSOM 498 1 R4 MOV FTUNST TSTAT TCSR CLEAR UNDERRUN BIT R5 SET STATE TO DISABLE TRANSMITTER 2 TRANSMIT BYTE COUNT RUNOUT OUTPUT TO STATE PROCESSING ROUTINES R3 ADDRESS OF TRANSMITTER CSR R5 ADDRESS OF THREAD WORD CELL 20 ADD TPRI TCSR 2 R5 POINT TO PRIORITY DATA BIC FTXINT R4 CLEAR INTERRUPT ENABLE MOV SP 4 RESTORE R4 SO SINTSV IS HAPPY SINTSX SAVE WITH R5 ON STACK BUT NOT R4 KISAR6 SP SAVE CURRENT MAPPING R3 SP 7 SAVE AN ADDITIONAL REGISTER MOV TCSR TSTAT R5 R3 GET TRANSMITTER CSR ADDRESS CALLR R5 3 DISPATCH TO PROCESSING ROUTINE DSABL LSB DPASX ASSIGN TRANSMIT BUFFER THIS ROUTINE IS ENTERED VIA THE MATRIX SWITCH TO QUEUE A CCB FOR TRANSMISSION INPUTS R4 ADDRESS OF CCB TO TRANSMIT R5 ADDRESS OF DEVICE LINE TABLE OUTPUTS IF THE TRANSMITTER IS IDLE TRANSMISSION IS INITIATED OTHERWISE THE CCB OR CHAIN IS QUEUED TO THE END OF THE SECONDARY CHAIN REGISTERS MODIFIED R3 R4 AND R5 I w ws Sg ne a 94 I D 19 DPASX MOV BIC ADD MOV IFTF MOV TST BNE CALL BIT BEQ MOV BR 10 MOV 205 M
15. DPCRA BIT BNE MOV CALL MOV BR R5 TST BMI MOV BR MOV BEQ ADD SEC ROL INC MOV BR CLR MOV BIS CALL MOV CALL BCS BNE CLR BIS MOV RETURN CS MTL R3 MESSAGE TOO LONG 31 3 IF NE YES POST COMPLETION R5 4 854 RECOVER PRIMARY CCB ADDRESS BUFUSE SET UP THIS CCB AGAIN CLEARS RSTAT RDBF RPRIM R5 R3 SET POINTER TO REC DAT BUFF 40 CLEAR RECEIVE ACTIVE TO FORCE RESYNC POST COMPLETION ON RECEIVE COMPLETE POINTS TO PRIMARY CCB ADDRESS RCNT RPRIM R5 IS CRC ERROR FLAG SET 25 IF MI YES CRC IS VALID CS ERR CS DCR R3 ELSE SET CRC ERROR STATUS FOR DLC 31 7 GO RETURN BUFFER RPCNT RPRIM R5 RCNT RPRIM R5 SET REMAINING COUNT 305 NONE SO END OF MESSAGE RPCNT RPRIM R5 RTHRD RPRIM R5 SET TOTAL COUNT IN CCB FORCE C BIT RFLAG RPRIM R5 PUT Q SYNC BACK amp MARK NON HEADER RADD RPRIM R5 INCLUDE LAST CHAR IN BUFFER RDBF RPRIM R5 R3 GET CSR FOR EXIT we RPCNT RPRIM RS RXINT R3 SP R3 ENABLE RECEIVER INTERRUPTS RESTORE R3 RETURN TO SYSTEM REXT TAKE COMMON EXIT R3 GET GOOD STATUS R5 R4 GET PRIMARY CCB ADDRESS R5 R3 PICK UP ADDITIONAL STATUS SDDRCP POST RECEIVE COMPLETION RDBF RSTAT R5 R3 GET ADDRESS OF RECEIVE DATA BUFFER BUFSET SET UP NEXT RECEIVE BUFFER REXT1 IF CS NO BUFFER AVAILABLE TURN OFF RECEIVER 40 IF NE CLEAR RECEIVE ACTIVE TO RESYNC RESET PARTIAL COUNT me
16. STCRC SEND CRC STATE PROCESSING w ENABL LSB STCRC BIS TEOM 2 R3 SEND CRC CALL TPOST POST COMPLETION AND SET UP NEXT CCB BNE 195 IF NE NOTHING MORE TO SEND MOV STDAT R5 ASSUME NEXT STATE IS SEND SYNC S BIT ECF SYN C FLG C BUF R4 ARE SYNC S REQUIRED BEQ 205 LEAVE ASSUMED STATE MOV STSYN R5 ELSE CHANGE STATE TO SEND SYNC S BR 205 WAIT FOR CRC BE SENT 105 MOV FSTIDL R5 SET STATE TO IDLE BIC TXENA R3 SHUT DOWN TRANSMITTER 205 WAITI WAIT FOR INTERRUPT WAITI MOV 1 TCNT TSTAT R5 WAIT FOR ONE INTERRUPT MOVB TIMS TSTAT R5 TIME TSTAT R5 START TIMER BR TEXT2 FINISH IN COMMON CODE STIDL IDLE STATE PROCESSING STIDL BIC RTS 4 R3 DROP REQUEST TO SEND TST R5 H 30 CLRB TIME TSTAT R5 CLEAR TIMER BR TEXT3 FINISH IN COMMON CODE DSABL LSB TUNST TRANSMIT DATA UNDER RUN STATE RETURN ALL TRANSMIT BUFFERS HIGHER LEVEL TUNST ADD TTHRD R5 TIMEOUT EXPECTS DDM LINE TABLE POINTER CLRB R5 RESET TIMER CALL DPTIM FAKE A TIMEOUT TO RETURN BUFFERS MOV FSTIDL TSEC TSTAT R5 SET STATE TO IDLE BR TEXT3 TAKE COMMON EXIT D 21 STDAT DATA STATE PROCESSING STDAT MOV R5 RA GET ADDRESS OF FLAGS WORD FROM THREAD ADD C FLG C STS R5 UPDATE THREAD POINTER TST RA LAST BUFFER THIS CCB BIT 15 SET BPL 10 IF PL NO CALL TPOST POST CO
17. ACT SLIDE XXDP ABS Loader e Performs nondiagnostic functions for programs such as console I O data conversion test sequencing program options A 2 VERSIONS OF THE DIAGNOSTIC SUPERVISOR File Name Environment HSAA SYS XXDP HSAB SYS APT HSAC SYS ACT SLIDE HSAD SYS Paper Tape Absolute Loader In the above file names stands for revision and patch level such as 0 A 3 LOADING AND RUNNING A SUPERVISOR DIAGNOSTIC supervisor compatible diagnostic program may be loaded and started in the normal way using any of the supported load systems Using XXDP for example the program CVDPVA BIN is loaded and started by typing R CVDPVA The diagnostic and the supervisor will automatically be loaded as shown in Figure A 1 and the pro gram started The program types the following message DRS LOADED DIAG RUN TIME SERVICES CVDPV A 0 To determine if diagnostics are supervisor compatible use the List command under the Setup utility see Paragraph 5 XXDP DIAGNOSTIC SUPERVISOR MEMORY LAYOUT ON A 16KW MIN MEMORY SYSTEM ADDRESS 100000 0 070000 0 DIAGNOSTIC SUPERVISOR 6KW 040000 0 DIAGNOSTIC PROGRAM 7 5KW 000000 0 Figure Typical XXDP Diagnostic Supervisor Memory Layout MK 2216 DIAGNOSTIC TESTS UNIT IS DR gt DR gt 15 the prompt for the diagnostic supervisor routine At this point a supervisor command must be entered th
18. Incoming Call W26 to W27 Not connected Note W26 is input to DSCNG flip flop Receiver Ready W26 to W28 Not connected Carrier Detect Normal configuration is typically RS 423 A compatible AIDE option is typically RS 422 A compatible Table 2 1 Configuration Sheet Cont Device Address Jumpers GND A12 AIO 9 A8 A7 A6 AS A4 A3 W29 W31 W30 W36 W33 W32 W39 W38 W37 W34 W35 NOTE The address to which the DPV11 is to respond is daisy chain jumpered to W29 GND Vector Address Jumpers D8 D7 D6 D5 D4 D3 Source W43 W42 W41 W40 W44 W45 W46 NOTE Vector address to be asserted is daisy chain jump ered to W46 NOTE Table 2 1 shows the recommended normal and alter nate jumpering schemes Any deviation from these will cause diagnostics to fail and require restrapping for full testing and verification It is recommended that customer configurations that vary from this scheme not be contractually supported Prior to installing the DPV11 perform the following tasks 1 Verify that the following modem interface wire wrap jumpers are installed Figure 2 1 W26 to W25 to W24 to W28 to W27 W22 to W23 and W19 to W21 W18 to W20 W5 to W6 W3 to W4 W8 to W9 WI to W2 This is the normal RS 423 A shipped configuration Some of these jumpers may be changed when the module is connected to external equipment for a specific application The NULL MODEM CLK is set to 2 kHz as shipped 2 Based LSI 11 bus floating vec
19. RECOVER LINE TABLE START CLRB D FLAG R5 LINE HAS BEEN STARTED BIT DC HDX D DCHR R5 33 CHECK THAT ASSUMPTION BNE CTLCMP CORRECT STARTUP COMPLETE BIS FDSRTS R3 ASSERT REQUEST TO SEND LINE BR CTLCMP 33 AND POST START COMPLETE DP NOP CTLCMP CTLERR SSDSTP 205 20 MOV CS ERR CS DIS R3 37 STATUS LINE DISABLED BR CTLERR RETURN ERROR W COMPLETION CONTROL FUNCTION NO OPERATION CLR R3 STATUS SUCCESSFUL MOV SP R4 RECOVER SAVED R4 VALUE SYNRET SYNCHRONOUS RETURN SBTTL SDSTP STOP DEVICE AND LINE ACTIVITY 8 TOP CONTROL FUNCTION A L ESI USE A O es MOV D RDBF R5 R3 RECEIVER CSR ADDR SEL 2 TO R3 MOV DSDTR R3 DISABLE RECEIVER LEAVE DSDTR ACTIVE CLR 4 R3 DISABLE TRANSMITTER MOV D RCCB R5 R ACTIVE RECEIVE CCB TO R4 BEQ 205 NONE THERE SKIP IT CALL SRDBRT RETURN BUFFER TO THE POOL CLR D RCCB R5 NO RECEIVE CCB ASSIGNED CLR R4 CLEAR R4 FOR PARAMETER USE BISB D SLN R5 R4 SET SYSTEM LINE NUMBER IN R4 CALL SRDBQP PURGE BUFFER WAIT QUEUE REQUESTS BISB DD STR D FLAG RS LINE IS NO LONGER STARTED TST D TCCB R5 IS THERE AN ACTIVE TRANSMIT CCB BEQ CTLCMP NO POST CONTROL COMPLETE MOV SP D KCCB R5 SAVE THE CONTROL CCB FOR TIMEOUT MOVB 1 R5 77 MAKE SURE THE TIMER IS ACTIVE ASYRET 7 RETURN WITH ASYNCHRONOUS COMPLETION SBTTL S SDENB ENABLE THE LINE AND DEVICE ENABLE LINE A N D DEVICE
20. RXBFOV 010060 RXOVRN 094008 RXABRT 002000 RXENDM 001000 RXSTRM 009400 SEL 2 DPAPA 130006 DPDECM 9040000 DPSTRP 020000 DPSECS 210000 DPIDLE 004000 DPCRC 35400 DPADRC 609377 INPRM DPSTRP DPCRC SEE 4 TCLEN 150000 EXADD 410000 EXCON 0040600 RCLEN 003400 TXITEN 080120 TXREN 092020 TXMAI 000012 020004 09302 TXRES 000001 SEL 5 120000 TXGO 6042500 TXABRT 8002000 TXENDM 021000 TXSTRM 200460 DXPTB WORD WORD WORD WORD 4n 9 9 mo 55 5 SSDASR SSDKIL SSDCTL w w eo RECEIVER FLAG DETECT RECEIVER DONE RECEIVER INTERRUPT ENABLE RECEIVER ENABLE RECEIVER STATUS INPUTS Se RECEIVER CRC RECEIVER ASSEMBLED BIT COUNT RECEIVER BUFFER OVERFLOW SOFTWARE ERROR RECEIVER DATA OVERRUN RECEIVED ABORT RECEIVED END OF MESSAGE RECEIVED START OF MESSAGE MODE CONTROL OUTPUTS 4 ALL PARTIES ADDRESSED DDCMP BISYNC OPERATION STRIP SYNC OR LOOP MODE SDLC ADCCP SECONDARY STATION SELECT IDLE MODE SELECT USE CRC 15 ERROR DETECTION STATION ADDRESS OR SYNC CHARACTER INITIAL STARTUP PARAMETERS TRANSMITTER STATUS AND CONTROL Mo mo TRANSMIT CHARACTER LENGTH EXTENDED ADDRESS FIELD EXTENDED CONTROL FIELD RECEIVE CHARACTER LENGTH TRANSMITTER INTERRUPT EN
21. SHIFT RXABRT INTO C BIT USE INDICATORS AS TABLE INDEX R3 NOW CCB STATUS FLAGS FRAME NOT ABORTED POST COMPLETE COUNT NUMBER OF ABORTED FRAMES RE INITIALIZE WITH THE SAME BUFFER RE ENABLE INTERRUPTS FOR NEXT FRAME INCLUDE RE SYNC STATUS IF ANY SAVE STATUS REPORTED TO DLC POST RECEIVE COMPLETE RECOVER COMPLETION STATUS ASSIGN NEW TO THE RECEIVER FAILED LEAVE RECEIVER INACTIVE WAS AN ERROR REPORTED TO DLC YES DISABLE RCVR FOR RE SYNC RECEIVER CSR SEL 2 TO R3 RE ENABLE RECEIVER INTERRUPTS RESTORE REGISTER R3 EXIT THE SYSTEM FLAG IN ORDER TO FORCE RECEIVER THIS IS REQUIRED FOR ANY ERROR WHICH TERMINATES THE RECEIVE OPERATION IN MID FRAME RS MOV SP KISARS ENDC MOV RA R5 MOV R5 R4 BIC RXITEN R4 MOV SP R4 SINTSX CHECK FOR ERE MOV R3 SP MOV R5 R4 ADD FD RONT D RCCB R5 SUB R5 C CNT1 R4 CLR R3 BIC 61777 R5 2 465 ASR R5 2 ASR RS ASRB R5 MOVB 685 R3 MOV RCVERR 2 R3 R3 BCC 405 INC D RABT D RDB2 R5 CALL RBFUSE H BR 605 2 26 BIS C STS R4 R3 2 MOV R3 SP CALL SDDRCP 2 MOV SP R3 3 CALL RBFSET BCS DREXIT 2 R3 BMI DRCLRA 5 MOV RS 315 RXITEN R3 EXIT MOV SP R3 RETURN MOMENTARILY RESET RXREN RE SYNCHRONIZATION OM ENTRY ADDRESS OF D RCCB IN THE LINE TABLE R4 ADDRESS OF C STS IN THE NEWLY ASSIGNED
22. module runs Its intent is to isolate DPV11s which adversely affect the system operation For information on configuring and running the DEC X11 System Exerciser refer to DEC X11 User Manual AS F0503B MC and DEC X11 Cross Reference AS F055C MC 2 4 2 Connection to External Equipment Link Testing The DPV11 is now ready for connection to external equipment If the DPV11 is being connected to a synchronous modem remove the H3259 connector and install the EIA connection of the BC26L 25 cable into the connector on the modem Configure jumpers W1 W28 in accordance with operating requirements Table 2 1 Load and run DCLT CVCLH if a full link is available This will check the final configuration and isolate failures to the CPU the communications link or the modem If the connection to external equipment uses RS 422 A the user must provide the cable and test sup port 2 5 TEST CONNECTORS The only test connector provided with the DPV11 is the H3259 turn around connector Figure 2 2 Table 2 5 and Figure 2 3 show the relationship between pin numbers signal names and register bits when the H3259 is connected by means of the BC26L 26 cable to the M8020 module NULL MODEM TCP SEC XMIT SELECT FREQ SEC REC REMOTE LOOP SIGNAL QUALITY TEST MODE XMIT DATA REC DATA RTS CTS RR LOCAL LOOP DATA MODE 6 WI IS CUT FOR TESTING DPV11 DTR e INOMNGOAL IN MING CALL 22 CO
23. BIT ERXSRDY R3 BNE DPRCP MOVB R4 8 R5 MOV SP KISAR6 INC R5 MOV SP R4 MOV SP SINTXT BIS RXBFOV R4 lt LI SAVE REGISTERS GET CHARACTER AND FLAGS DON T WORRY ABOUT ASSEMBLED BIT COUNT SAVE CURRENT MAP MAP TO DATA BUFFER DECREMENT BUFFER BYTE COUNT BUFFER OVERFLOW POST COMPLETE GET CSR 2 ADDRESS ERROR OR END OF MESSAGE YES POST RECEIVE COMPLETE STORE CHARACTER IN RECEIVE BUFFER RESTORE PREVIOUS MAPPING ADVANCE BUFFER ADDRESS RESTORE REGISTERS EXIT THE INTERRUPT BUFFER OVERRUN HAS OCCURRED SET SOFTWARE ERROR INDICATOR END OF MESSAGE OR ERROR INDICATION me w e w we w ne w w T me me e 4 o RESTORE PREVIOUS MAPPING SAVE STATUS FLAGS IN D RVAD GET CSR 2 ADDR POINT TO D RPRI CLEAR RECEIVER INTERRUPT ENABLE RESTORE R4 SO SINTSV IS HAPPY AND R3 DO A TRICKY SINTSV R5 SAVED BUT NOT R4 FOR ERRORS POST RECEIVE COMPLETE ASSIGN NEW BUFFER mu 4 o we o e mo gt SAVE ADDITIONAL REGISTER CCB ADDRESS TO R4 R5 POPPED BACK UP TO THE RESI DUAL COUNT COMPUTE RECEIVED FRAME BYTE COUNT SET R3 FOR COMPLETION STATUS ue me we Be ue ANY ERRORS REPORTED NO POST RECEIVE COMPLETE SHIFT ERROR INDICATORS TWO PLACES RIGHT
24. BUFFER BCS 20 IF CS GO TO TRANSMITTER CLR 2 R5 CLEAR THE FLAGS WORD MOV ERINIT R3 INITIALIZE RECEIVER 20 MOV TINIT 4 R3 TURN ON TRANSMITTER MOVB DPVCH 3 RPRIM R5 TIMS RPRIM R5 SET DDM TIME INTERVAL BIT 1 DPVCH RPRIM R5 HALF DUPLEX BNE 305 NE YES DONT FORCE FD MODE BIC TINIT 4 R3 INDICATE FULL DUPLEX BIT CH MDT DPVCH 2 RPRIM RS IS THIS MULTIPOINT SLAVE BNE 305 YES DO SET REQUEST TO SEND BIS RTS R3 ASSERT REQUEST TO SEND FOR FULL DUPLEX 30 MOV SP R4 RESTORE THE CALLING CCB CLC CLEAR C BIT SYNCHRONOUS COMPLETION RETURN RETURN DPSTP STOP DEVICE RETURN OUTSTANDING BUFFERS AND CLEAR TIMERS DPSTP MOV R4 SP SAVE THE CALLING CCB MOV RDBF R5 R3 GET RECEIVE DATA BUFFER ADDRESS MOV EDTR R3 DISABLE RECEIVER LEAVE DTR UP CLR 4 R3 DISABLE TRANSMITTER MOV RPRIM R5 R4 GET PRIMARY RECEIVER CCB BEQ 10 IF EQ NONE ASSIGNED CALL SRDBRT RETURN BUFFER TO THE POOL 105 CLR RPRIM R5 CLEAR PRIMARY POINTER MOV LINE R5 R4 SET SYSTEM LINE NUMBER CALL SRDBQP REMOVE ANY WAIT REQUESTS MOV SP R4 RESTORE THE SAVED CCB TST TPRIM R5 IS ANYTHING ACTIVE BNE 205 YES SO SAVE FOR TIMEOUT D 23 20 305 CALL BR MOV SEC RETURN END DDCCP 30 R4 KICCB RS e NO SO GIVE THE COMPLETION NOW AND EXIT SAVE THE CCB FOR LATER INDICATE ASYNC AND EXIT D 24 GLOSSARY Asynchron
25. CCB SP SAVED R3 VALUE DRCLRA MOV R5 R3 RCVR CSR ADDRESS SEL 2 TO R3 BIC R3 RESET RCVR ENABLE FOR RE SYNC BIS CS RSN R4 SET RE SYNC IN CCB C STS BIS RXITEN R3 RE ENABLE THE RECEIVER BR DREXIT RESTORE R3 AND EXIT SBTTL SDPTI TRANSMIT INTERRUPT SERVICE ROUTINE FUNCTION THE DEVICE INTERRUPT IS VECTORED THE HARDWARE THE DEVICE LINE TABLE THE S SDPTI LABEL IS ENTERED VIA CALLING SEQUENCE IN THE LINE TABLE AT OFFSET D TXIN ONCE FRAME TRANSMISSION IS INITIATED EACH INTERRUPT IS HANDLED BY THE ROUTINE ADDRESSED VIA THE D TSPA WORD w 9 ENTRY 2 R5 ADDRESS OF D TCSR IN THE LINE TABLE 8 5 SAVED R5 2 SP INTERRUPTED PC 4 5 INTERRUPTED PS ON EXIT R5 ADDRESS OF D TCCB IN THE LINE TABL As Uy we SSDPTI MOV R4 SP SAVE 4 R5 84 TRANSMITT ISR ADDRESS TST R4 333 POINT SEL gt TEST UNDERRUN JMP R5 GO TO CORRECT STATE PROCESSOR 4 7 2 CURRENT STATE MONITOR CSR FOR CLEAR TO SEND TISCTS BIT DSCTS 6 R4 IS CLEAR TO SEND ACTIVE YET BNE TISIFL YES START TO SEND THE FRAME BITB DD SYN D FLAG D TCNT RS SYNC TRAIN REQUIRED BEQ TISIFX 533 NO SEND FLAGS UNTIL MOV TXSTRM TXENDM R4 373 START END SENDS SYNC STRING BR TISEXT H CURRENT STATE SEND INITIAL FRAME
26. Figure 2 2 H3259 Turn Around Test Connector MK 1329 2 8 Table 2 5 H3259 Test Connections _ To Pin No Pin No Pin No Pin No H3259 J1 J1 H3259 2 F J 3 Signal Name Signal Name SEND DATA RECEIVE DATA REQUEST TO SEND 4 V CLEAR TO SEND RTS RXCSR 2 CTS RXCSR 13 RECEIVER READY RR RXCSR 12 DATA MODE DM RXCSR 9 LOCAL LOOPBACK LL RXCSR 3 SELECT FREQ REMOTE 23 21 SIGNAL QUALITY LOOPBACK TEST MODE SF RL RXCSR 0 SQ TM PCSCR 5 NULL MODEM RCV CLOCK TX CLOCK DATA TERMINAL INCOMING CALL READY DTR IC RXCSR 14 RXCSR 1 The following accessories are available for interfacing and may be ordered separately e BC26L X cable Available in lengths of 3 1 8 2 4 3 0 3 6 6 1 and 7 6 meters 1 6 8 10 12 20 and 25 feet When ordering the dash number indicates the desired cable length in feet e g BC26L 25 or BC26L 1 e H3259 cable turn around connector H856 Berg connector Includes H856 Berg connector and 40 pins Crimping tools are avail able from Berg Electronics Inc New Cumberland 17070 H3260 on board test connector includes RS 422 A testing The H3260 on board test connector Figure 2 4 may be used to test the M8020 circuitry in its entirety RS 422 A circuitry is not tested with the H3259 cable turn around connector The H3260 on board test connector is shipped configured for testing RS 422 A It may be configured to
27. IN DENOTE TERMINAL NUMBERS TERMINAL IDENTIFICATION POSITIVE SUPPLY VOLTAGE CHANNEL 1 INPUT CHANNEL 2 OUTPUT SUPPLY AND SIGNAL GROUND CHANNEL 2 INVERTED OUTPUT CHANNEL 2 NON INVERTED OUTPUT CHANNEL 1 INVERTED OUTPUT 8 CHANNEL 1 NON INVERTED OUTPUT SNOOP WH MK 1324 Figure C 8 9638 Logic Diagram and Terminal Identification C 12 APPENDIX D PROGRAMMING EXAMPLES Two examples are included in this appendix The first is an example for bit oriented protocols and the second is an example for byte count oriented protocols These are only exampies and are not intended for any other purpose 4 9 x DC HDX DC PRT DC MPT DC SEC DC ADR DC SPS 0 555 DD ENE DD STR DD EOM DD SOM DD ABT DD SYN DD DD ACT DD DIS DSCHG DSRING DSCTS DSCARY DSMODR DSITEN DSLOOP DSRTS DSDTR DSSEL RXSRDY COPYRIGHT C DIGITAL EQUIPMENT CORPORATION MAYNARD MASS TITLE DPV11 IDENT 1982 BY rPV 11 DDM F R BIT ORIENTED PROTOCOLS EXAMPLE OF AN APPLICATION RSX 11M BIT ORIENTED DPV 11 DEVICE DRIVER NOTE THIS IS NOT RUNNING DRIVER HWDDFS SINTSX SINTXT MDCDFS CCBDFS TMPDF ASYRET SYNRET HWDDES CCBDFS MDCDFS TMPDES La DEFINE THE HARDWARE REGISTERS DEFINE THE CCB OFFSETS DEFINE THE MODEM CONTROL SYMBOLS DEFINE LINE TABLE TEMPLATE OPERATORS DEVICE CHARA
28. Lip Additional copies of this document are available from Digital Equipment Corporation Accessories and Supplies Group Cotton Road Nashua NH 03060 Attention Documentation Products Telephone 1 800 258 1710 Postage Necessary if Mailed in the United States ee BUSINESS REPLY MAIL FIRST CLASS PERMIT NO 33 MERRIMACK NH POSTAGE WILL PAID BY ADDRESSEE Digital Equipment Corporation Educational Services Development amp Publishing Continental Blvd MK1 2M26 Merrimack N H 03054 digital equipment corporation
29. POINT TO PRIORITY MOV RDBF RPRI R5 R4 GET RECEIVE DATA BUFFER ADDRESS BIC RXINT R4 CLEAR RECEIVER INTERRUPT ENABLE MOV SP R4 RESTORE R4 SO SINTSV IS HAPPY SINTSX DO TRICKY SINTSV R5 PRESAVED BUT NOT R4 MOV R3 SP SAVE AN ADDITIONAL REGISTER TST R5 POINT TO FLAGS WORD ASR RS LOAD C BIT FROM FLAGS BIT 0 BCS 205 IF CS DATA POST COMPLETION MOV R5 R4 GET PRIMARY CCB ADDRESS LIST MEB SLIBCL HDRA RPRIM R5 SDDHAR SAV CALL DDHAR THROUGH LINE TABLE NLIST MEB ROR 2 R5 SAVE FINAL SEEN IN FLAGS BIT 15 SET TST R3 EXAMINE BYTE COUNT FOR THIS MESSAGE BMI 10 IF MI AN INVALID HEADER RECEIVED BEQ 7 EQ SET TO RECEIVE REST OF HEADER ADD 2 R3 ACCOUNT FOR IN CURRENT COUNT MOV R3 RPCNT RPRIM R5 SAVE DATA COUNT UNTIL HEADER CRC gt IS CHECKED MOV 5 R3 GET REMAINING HEADER INC R5 MARK DATA IN PROGRESS IN FLAGS BIT 9 SET ADD 6 R5 INCLUDE CURRENT COUNT IN TOTAL COUNT ADD RCNT RTHRD R5 POINT TO CURRENT COUNT MOV R3 R5 SET UP CURRENT BYTE COUNT INC R5 MOVE BUFFER ADDRESS PAST BCC DF MSSMGE MOV 4 R5 R3 GET ADDRESS OF RECEIVE DATA BUFFER IFF MOV R5 R3 GET ADDRESS OF RECEIVE DATA BUFFER ENDC BR 0 FINISH COMMON CODE INVALID HEADER RECEIVED D 16 105 20 25 38 31S REXT REXT2 REXTI 405 CLEAR me
30. TDSR bit 8 is set This happens in one of two ways depending on the state of the IDLE bit PCSAR bit 11 When the IDLE bit is cleared the sync character is taken directly from the common sync register PCSAR bits 7 0 The sync register would have been previously loaded by the software If the IDLE bit is set the sync character must be loaded into the TDSR by the software when it is to be transmitted If multiple sync characters are to be transmitted the TDSR must only be loaded with the first one of the sequence This character will be transmitted until data information is loaded into the TDSR The TBEMTY signal is asserted at the end of each sync character but the TSOM signal allows it to be ignored without causing a data late error 3 20 With bit oriented protocols the USYNRT automatically generates control characters as initiated by the software and inserts necessary information into the data stream to maintain transparency Typical programming examples in bit and byte count oriented protocols appear in Appendix D 3 5 INTERRUPT VECTORS The DPV11 generates two vector addresses one for receive data and modem control and the other for transmit data The receive and modem control interrupt has priority over the transmit interrupt and is enabled by setting bit 6 RXITEN of the receiver control and status register RXCSR If bit 6 of the RXCSR is set a receiver interrupt may occur when any one of the following signals is asserted
31. causes the modem connected to the DPV11 to LL establish a data loopback test condition Clearing this bit restores normal modem operation Local Loopback is program read write and is cleared by Device Reset or Bus request to Send is program read write and is cleared by Device Reset or Bus INIT 2 Request to Send Setting this bit asserts the Request to Send signal at the modem RTS interface Request to Send is program read write and is cleared by Device Reset or Bus INIT 1 Terminal Ready TR When set this bit asserts the Terminal Ready signal to the Data Terminal modem interface Ready For auto dial and manual call origination it maintains the estab lished call For auto answer it allows handshaking in response to a Ring signal 3 7 Table 3 2 Receive Control and Status Register RXCSR Bit Assignments Cont 0 Select Frequency This bit can be wire wrap jumpered to function as either select or Remote frequency or remote loopback When jumpered as select fre Loopback SF RL quency W3 to W4 setting this bit selects the modem s higher frequency band for transmission to the line and the lower fre quency band for reception from the line The clear condition se lects the lower frequency for transmission and the higher fre quency for reception When jumpered for remote loopback W5 to W3 this bit when asserted causes the modem connected to the DPV11 to signal when a remote loopback test condition has been est
32. character 10 1 Five bits per character bit oriented protocol only 1 0 0 Four bits per character bit oriented protocol only 0 1 1 Three bits per character bit oriented protocol only 0 1 0 Two bits per character bit oriented protocol only 0 0 1 One bit per character bit oriented protocol only These bits can be changed while the transmitter is active in which case the new character length is assumed at the com pletion of the current character This field is set to a character length of eight by Device Reset or Bus INIT When VRC error detection is selected the default character length is eight bits plus parity This bit is used with bit oriented protocols and affects the ad dress portion of a message in receiver operations When it is set each address byte is tested for a one in the least significant bit position If the least significant bit is zero the next character is an extension of the address field If the least significant bit is one the current character terminates the address field and the next character is a control character EXADD is not used with Secondary Address Mode bit 12 of PCSAR EXADD is read write and is reset by Device Reset or Bus INIT This bit is used with bit oriented protocols and affects the con trol character of a message in receiver operations When EX 3 14 Table 3 5 Parameter Control and Character Length Register PCSCR Bit Assignments Cont Bit 10 8 Receiver Cha
33. control to include incoming test mode remote loopback and local loopback Program interrupt on transitions of modem control signals Operating speeds up to 56K b s may be limited by software or CPU memory Software selectable diagnostic loopback Operation with bit byte count or character oriented protocols Internal cyclic redundancy check CRC character generation and checking not usable with BISYNC Internal bit stuff and detection with bit oriented protocols Programmable sync character sync insertion and sync stripping with byte count oriented protocols O Recognition of secondary station address with bit oriented protocols 1 5 GENERAL SPECIFICATIONS This paragraph contains environmental electrical and performance specifications for the 11 1 5 1 Environmental Specifications The DPVI1 is designed to operate in a Class C environment as specified by DEC Standard 102 ex tended Operating Temperature 5 C 41 F to 60 C 140 F Relative Humidity 10 to 90 with a max wet bulb temperature of 28 C 82 F and a min dew point of 2 C 36 F The actual speed realized may be significantly less because of limitations imposed by the software and or CPU memory refresh 1 2 1 5 2 Electrical Specifications The DPV11 requires following voltages from the LSI 11 bus for proper operation 12 V at 0 30 A max 0 15 A typical 5 V at 1 2 A max 0 92 A typical T
34. jumper enabling the Clear to Send signal is removed Clear to Send is a program read only bit and cannot be cleared by software 12 Receiver Ready This bit is a direct reflection of modem Receiver Ready lead It RR indicates that the modem is receiving a carrier signal For exter nal maintenance loopback this signal must be high If the line is open RR is pulled high by the circuitry Any transition of this bit causes Data Set Change bit 15 to be asserted unless the jumper enabling the Receiver Ready signal is removed Receiver Ready is a read only bit and cannot be cleared by soft ware Receiver Active This bit is set when the USYNRT presents the first character of RXACT a message to the DPV11 It remains set until the receive data path of the USYNRT becomes idle Receiver Active is cleared by any of the following conditions a terminating control character is received in bit oriented protocol mode an off transition of Receiver Enable RXENA occurs or Device Reset or Bus INIT is issued 3 5 Table 3 2 Receive Control and Status Register RXCSR Assignments Cont Description Receiver Active is a read only bit which reflects the state of the USYNRT output pin 5 This bit indicates the availability of status information in the upper byte of the receive data and status register RDSR It is set when any of the following bits of the RDSR are set Receiver End of Message REOM Receiver Overrun
35. status bits in both bytes 3 3 2 Receive Data and Status Register RDSR Address 16xxx2 Figure 3 3 show the format for the receive data and status register RDSR It is a read only register and shares its address with the parameter control sync address register PCSAR which is write only Table 3 3 is a detailed description of the RDSR NOTE The RDSR can be read in either word or byte mode However reading either byte resets data and certain status bits in both bytes of this register as well as bits 7 and 10 of the RXCSR 3 3 3 Parameter Control Sync Address Register PCSAR Address 16xxx2 The parameter control sync address register PCSAR is a write only register which can be written in either byte or word mode Figure 3 4 shows the format and Table 3 4 is a detailed description of the PCSAR This register shares its address with the RDSR NOTE Bit set BIS and bit clear BIC instructions can not be executed on the PCSCR since they execute using a read modify write sequence 3 3 4 Parameter Control and Character Length Register PCSCR Address 16xxx4 The parameter control and character length register PCSCR can be read from or written into in either word or byte mode The low byte of this register is external to the USYNRT and the high byte is internal Figure 3 5 shows the format and Table 3 5 is a detailed description of the PCSCR 3 3 5 Transmit Data and Status Register TDSR Address 16xxx6 The format for the tran
36. 16 CRC regis ters set to all zeros 1 0 0 44 A parity bit is attached to each transmitted character Should be used only in character oriented protocols l O 1 Even VRC parity Resembles odd VRC ex cept that an even number of bits are gener ated 1 1 O Not used 1 1 1 All error detection is inhibited Sync Character The low byte of PCSAR is used as either the sync character for or Secondary character oriented protocols or as the secondary station address Address for bit oriented protocols 0 The bits are right justified with the least significant bit being bit EXTERNAL TO THE USYNRT 7 6 5 4 3 2 1 Ma MM TB RSVD INT 50 TXACT RESET EN SEL EMTY INTERNAL TO THE USYNRT 15 14 13 12 11 10 9 8 TRANSMITTER RECEIVER CHARACTER LENGTH EXCON CHARACTER LENGTH MK 1325 Figure 3 5 Parameter Control and Character Length Register PCSCR Format 3 13 15 13 12 11 Table 3 5 Parameter Control and Character Length Register PCSCR Bit Assignments Transmitter Character Length Extended Address Field EXADD Extended Control Field EXCON Description These bits can be read or written and are used to determine the length of the characters to be transmitted They are encoded to set up character lengths as follows 15 14 13 Character Length 0 0 0 Eight bits per character Y Seven bits per character 1 1 0 Six bits per
37. 18 H 0 8 L H MK 017 11 12 13 14 15 16 17 Table 2 DC004 Pin Signal Descriptions VECTOR H BDAL2 L BDAL1 L BDALO L BWTBT L BSYNC L BDIN L BRPLY L BDOUT L INWD L OUTLB L OUTHB L SELO L SEL2 L Description Vector This input causes BRPLY L to be generated through the delay circuit Independent of BSYNC L and ENB H Bus Data Address Lines These signals are latched at the assert edge of BSYNC L Lines 2 and 1 are decoded for the select out puts line O is used for byte selection Bus Write Byte While the BDOUT L input is asserted this signal indicates a byte or word operation asserted byte unas serted word Decoded with BDOUT L and latched BDALO L BWTBT L is used to form OUTLB L and OUTHB L Bus Synchronize At the assert edge of this signal address in formation is trapped in four latches While unasserted this sig nal disables all outputs except the vector term of BRPLY L Bus Data In This is a strobing signal to effect a data input transaction BDIN L generates BRPLY L through the delay cir cuit and INWD L Bus Reply This signal is generated through an RC delay by VECTOR H and strobed by BDIN L or DBOUT L and BSYNC L and latched ENB H Bus Data Out This is a stobing signal to effect a data output transaction Decoded with BWTBT L and BDALO it is
38. 9 8640 Equivalent Logic Diagram C 10 888 Pin Identification rita al C 10 9636A Logic Diagram and Terminal Identification C 11 9638 Logic Diagram and Terminal Identification C 12 TABLES Title Page Concurso 2 1 Vector Address Selectionata 2 5 Device Address Selec nee ESL nn nr 2 6 Voltage REQUIT MENTS ode aqlia sasan ne 2 7 H3259 Test Connections A Lie dt 2 9 DP Vil Registers p PES 3 1 Receive Control and Status Register RXCSR Bit SS Ace 3 5 Receive Data and Status Register RDSR Bit Assignments 3 8 Parameter Control Sync Address Register PCSAR Bit Assignments re oho uM D T ER 3 11 Parameter Control and Character Length Register PCSCR Bit Assignments codes cete aeo Eh Hosen ted tds 3 14 Transmit Data and Status Register TDSR Bit Assignments 3 17 DC003 Pin Signal Descriptions eee te os HIR es C 2 0 004 Pin Signal Descriptions geh be He qud C 5 DC005 Pin Signal Descriptions uio id C 8 PREFACE This manual is intended to provide an introduction to the DPV11 Interface and present informa tion required by the user for configuration installation and o
39. ABLE TRANSMITTER ENABLE MAINTENANCE MODE SELECT TRANSMITTER DONE TRANSMITTER ACTIVE DEVICE RESET TRANSMITTER OUTPUT CONTROLS wb mo PROCESS DISPATCH TABLE TRANSMITTER DATA LATE UNDERRUN TRANSMITTER GO AHEAD TRANSMITTER ABORT TRANSMIT END OF MESSAGE TRANSMIT START OF MESSAGE TRANSMIT ENABLE RECEIVE ENABLE ASSIGN BUFFER KILL 1 0 ENABLE CONTROL ENABLE D 3 7 4 e EUNCTI ON ENT OUTPUT SSDPRI IF IFT IFT DPRBO DPRCP IFT WORD SBTTL ON SSDTIM SSDPRI TIME OUT RECEIVE INTERRUPT SERVICE ROUTINE THE DEVICE INTERRUPT IS VECTORED BY THE HARDWARE TO THE DEVICE LINE TABLE THE SSDPRI LABEL IS ENTERED VIA CALLING SEQUENCE IN THE LINE TABLE AT OFFSET D RXIN we w me w w ue IN THE LINE TABLE IN THE LINE TABLE BITS FROM CSR SEL 2 we Ne we me MO ue lt w ue ve we e w RS ADDRESS OF D RDBF 0 5 SAVED R5 2 SP INTERRUPTED PC 4 SP INTERRUPTED PS 5 RS ADDRESS OF D RDB2 D RVAD RECEIVER STATUS MOV R3 SP MOV RA SP MOV 8 R5 R4 BIC RXABC R4 DF MSSMGE MOV KISAR6 SP MOV R5 KISAR6 F DEC 85 4 BMI DPRBO MOV 2 R5 R3
40. ADC WORD SET TRANSMIT BUFFER ADDRESS R4 D TCNT D TPRI R5 23 x we se R4 R5 SET TRANSMIT BUFFER RELOCATION R4 85 SAVE THE CURRENT MAPPING KISAR6 SP R5 KISARS MAP TO THE TRANSMIT BUFFER w ue a R5 5 MOVE ADDRESS BYTE TO D TADC SP KISAR6 RESTORE PREVIOUS APRG MAPPING D TSPA D TADC R5 D FLAG D TSPA R5 205 BACK UP STATE PROCESSOR CELL IS THE TRANSMITTER READY NOW NO ENABLE IT THEN START TISTRT R5 405 INITIAL STATE SEND ADDR ENABLE INTERRUPTS AND EXIT gt 2 R5 R3 DSRTS 4 R3 TXREN TRANSMITTER CSR SEL 4 R3 gt ASSERT REQUEST SEND ENABLE THE TRANSMITTER w TISCTS R5 i INITIAL STATE WAIT FOR RTXITEN G R5 RE ENABLE TRANSMIT INTERRUPTS SP R3 RESTORE R3 FROM ENTRY EXIT WHEREVER APPROPRIATE ASYNC STATE TRANSMIT KILL OR TIMEOUT i 5 5 SP TRANSMIT COMPLETION STATUS TXREN D TCSR D TCBQ RS DISABLE TRANSMITTER R5 R4 ADD SECONDARY CHAIN TO PRIMARY RS CLEAR SECONDARY CHAIN POINTER SP R3 COMPLETION STATUS TO R3 R4 SP NEXT CCB ADDRESS TO STACR 84 SURE LINK WORD IS ZERO SDDXMP POST CCB COMPLETE W ERROR SP R4 NEXT CCB ADDRESS TO R4 ve D 9 BNE 205 MORE C
41. CTERISTICS DEFINED IN D DCHR 002641 800007 0690619 000623 996040 000013 090033 HALF DUPLEX LINE INDICATOR WORD 0 PROTOCOL SELECTION FIELD WORD 1 MULTI POINT CONFIGURATION WORD 1 MULTI POINT SECONDARY MODE WORD 41 STATION ADDRESS IS 1 BITS WCRD 1 SDLC PRIMARY STATION COMPOSITE SDEC SECONDARY STATION COMPOSITE DEVICE STATUS FLAGS DEFINED IN D FLAG 991 002 CF EOM CF SOM 029 5 200 f oH H ow I Hou H H 1 d Hon SEL 4 100900 040000 020000 010000 001000 000040 000010 000004 000052 000001 H li SEL 0 004000 002000 DD ENB DD ST 4 r 4 R w we o RE IF ZERO LINE HAS BEEN ENABLED IF ZERO LINE HAS BEEN STARTED UNUSED UNUSED TRANSMIT ABORTED DUE O UNDERRUN TRANSMIT SYNC TRAIN REQUIRED TRANSMIT LINE TURN AROUND REQUIRED TRANSMITTER READY FOR NEXT FRAME INITIAL STATUS DISABLED STOPPED MODEM CONTROL BITS DATA SET CHANGE RING INDICATOR CLEAR TO SEND CARRIER INDICATOR MODEM READY DATA SET INTERRUPT ENABLE DATA SET LOOPBACK REQUEST TO SEND DATA TERMINAL READY SELECT FREQUENCY OR REMOTE LOOPBACK CEIVER CONTROL BITS RECEIVER ACTIVE RECEIVER STATUS READY D 2 RXFLAG 9000400 RXDONE 000200 RXITEN 000100 RXREN 000020 SEL 2 RXERR 100000 RXABC 070000
42. DPV 11 serial synchronous interface user guide digital EK DPV11 UG 001 DPV11 serial synchronous interface user guide digital equipment corporation merrimack new hampshire 15 Edition August 1980 Copyright 1980 by Digital Equipment Corporation All Rights Reserved The material in this manual is for informational pur poses and is subject to change without notice Digital Equipment Corporation assumes no responsi bility for any errors which may appear in this manual Printed in U S A This document was set on DIGITAL s DECset 8000 computerized typesetting system The following are trademarks of Digital Equipment Corporation Maynard Massachusetts DIGITAL DECsystem 10 MASSBUS DEC DECSYSTEM 20 OMNIBUS PDP DIBOL OS 8 DECUS EduSystem RSTS UNIBUS VAX RSX DECLAB VMS IAS MINC 11 CHAPTER 1 pb pb p ed just j O Ww N MO Un tn Q b Q b CHAPTER 2 2 1 2 2 2 3 2 4 2 4 1 2 4 2 2 5 CHAPTER 3 Us Lo Lo Lo U N 3 3 4 3 3 5 3 4 3 4 1 3 4 2 222 CONTENTS Page INTRODUCTION CO E SR aa 1 1 DPV11 GENERAL DESCRIPTION 2 2 220000000 1 1 DPVIT OPERATION ania E a 1 2 DPVILEEATUREBS 1 2 GENERAL SPECIFICATIONS 1 2 Environmental Specifications
43. EVICE LINE TABLE BY THE HARDWARE AND THIS ROUTINE IS ENTERED BY A JSR R5 SDPVRI INSTRUCTION AT THE BEGINNING OF THE LINE TABLE INPUTS R5 ADDRESS DEVICE LINE TABLE 4 mo ta Wa mp we 4 SP SAVED R5 2 SP INTERRUPTED BIAS 4 SP INTERRUPTED PC 6 SP INTERRUPTED PS OUTPUTS ETC SDPVRI MOV RA SP SAVE R4 MOV R5 R4 GET ADDRESS OF RECEIVER DATA BUFFER MOV RA 333 GET CHARACTER AND FLAGS BMI DPRHO ANY ERROR IS RECEIVER OVERRUN DF MSSMGE MOV KISAR6 SP 333 SAVE CURRENT MOV R5 KISAR6 MAP TO DATA BUFFER MOVB R5 ii STORE CHARACTER RECEIVE BUFFER MOV SP KISAR6 RESTORE PREVIOUS MAPPING ENDC DEC R5 77 DECREMENT REMAINING BYTE COUNT BEQ DPRCP IF EQ RECEIVE COMPLETE INC R5 ADVANCE BUFFER ADDRESS MOV SP 4 RESTORE REGISTERS SINTXT EXIT THE INTERRUPT EXCEPTIONAL RECEIVE SERVICE ROUTINES HARDWARE OVERRUN we D 15 ENABL DPRHO ADD DP 75 MOV MOV LSB lt RCNT RDBF 2 gt R5 POINT TO COUNT CELL 100001 RFLAG RCNT R5 SET FLAGS TO COMPLETE REQUEST AND CLEAR RECEIVE ACTIVE ON EXIT CS ERR CS ROV RSTAT RCNT R5 SET OVERRUN STATUS RECEIVE BYTE COUNT RUNOUT RCP MOV R4 R5 SAVE CRC FLAG AND
44. M and TEOM simultaneously provided the transmitter is in idle state and Transmit Enable is cleared This should not be done during the transfer of data and must only be done in byte mode NOTE When using the special space sequence function all registers in ternal to the USYNRT must be written in byte mode Normally at the completion of each sync flag go ahead or Abort character the TBEMTY indication is asserted This al lows the software to count the number of transmitted charac ters In certain applications the software may elect to ignore the service of the Transmitter Buffer Empty TBEMTY indication Normally during data transfers this would cause a transmit data late error The TSOM bit asserted suppresses this error and provides the necessary synchronization to automatically transmit another flag go ahead or sync character Data from the processor to be transmitted on the serial output line is loaded into this byte of the TDSR when Transmitter Buf fer Empty TBEMTY is asserted If the transmitter buffer is not loaded within one character time an underrun error occurs The characters are right justified with bit O being the least sig nificant bit Paragraphs 3 4 1 and 3 4 2 discuss receive and transmit data transfers as they relate to the system software 3 4 1 Receive Data Serial data to be presented to the DPV11 from the modem enters the receiver circuit and is presented to the USYNRT Recognition by the USY
45. MPLETION AND SET UP NEXT CCB 19 MOV STDAT R5 ASSUME DATA CONTINUES BIT CF EOM C FLG C BUF R4 SEND CRC FOLLOWING THIS BUFFER BEQ 205 IF LEAVE ASSUMED STATE MOV STCRC R5 ELSE CHANGE STATE FOR CRC SENT 205 SP CLEAR TSOM CLEAR TEOM TEXTO COMMON EXIT ROUTINES 1 s 2 TEXT3 MOVB TIMS TSTAT R5 TIME TSTAT R5 START TIMER TEXT1 ADD FTCSR TSTAT 2 R5 POINT TO CURRENT BUFFER CELL IFT MOV R4 R5 COPY RELOCATI N BIAS IFF TST RA SKIP OVER RELOCATION BIAS IN CCB MOV R4 RS COPY VIRTUAL ADDRESS MOV R4 R5 AND THE BYTE COUNT IFT MOV 4 R5 KISARS MAP TO DATA BUFFER 5 2 R5 SP BUILD CHARACTER TO OUTPUT INC 2 R5 UPDATE VIRTUAL ADDRESS MOV SP 2 R3 OUTPUT CHARACTER AND FLAGS TEXT2 BIS R3 ENABLE TRANSMITTER INTERRUPTS TEXT3 MOV SP R3 RESTORE R3 IFT D 22 MOV SP KISAR6 RESTORE PREVIOUS MAPPING ENDC SEC SET C BIT ASYNCHRONOUS COMPLETION RETURN RETURN TO CALLER DPSTR DEVICE START UP THIS ROUTINE IS CALLED TO ACTIVATE THE DEVICE y t DPSTR MOV R4 SP SAVE THE CALLING CCB MOV RDBF R5 R3 GET RECEIVER DATA BUFFER ADDRESS MOV SSYNC INPRM R3 SET INITIAL PARAMETERS TST R3 POINT TO RECEIVER CSR ADD ERSTAT R5 POINT TO STATUS WORD CALL BUFSET ASSIGN A PRIMARY CCB AND
46. NEW TO END OF CHAIN CLR RA MARK NEW END BIS TXITEN R3 RE ENABLE TRANSMITTER INTERRUPTS BR TREXIT RESTORE R3 AND EXIT SBTTL SDASR RECEIVE ENABLE AFTER BUFFER WAIT FUNCTION i THIS ROUTINE IS CALLED BY THE BUFFER POOL MANAGER WHEN s BUFFER ALLOCATION REQUEST CAN SATISFIED FOLLOWING AN ALLOCATION FAILURE AND CALL TO SRDBWT ON ENTRY R4 ADDRESS OF AND RECEIVE BUFFER R5 ADDRESS OF DEVICE LINE TABLE ON EXIT R5 ADDRESS OF D RCCB IN THE LINE TABLE R4 ADDRESS OF C STS IN THE CCB SP SAVED VALUE OF R3 SSDASR ADD D RDB2 R5 POINT TO SECOND RCVR CSR WORD CALL RBFUSE ASSIGN BUFFER TO THE RECEIVER BIS CS BUF R4 37 PREV ALLOC FAILURE TO CCB C STS MOV R3 SP PUSH R3 FOR EXIT AT DREXIT ABOVE JMP DRCLRA RESET AND ACTIVATE THE RECEIVER E SSDSTR START UP DEVICE AND LINE ACTIVITY SSDSTR BITB FDD ENB D FLAG R5 HAS THE LINE BEEN ENABLED BNE 60 NO REJECT THE START MOV D RDBF R5 R3 RECEIVER CSR ADDR SEL 2 TO R3 MOV D STN R5 R3 SET ADDRESS BYTE OPERATING MODE BIS RXREN R3 3 ENABLE THE RECEIVER MOV R5 SP 5 SAVE LINE TABLE START ADDRESS ADD D RDB2 R5 3 ADJUST R5 FOR BUFFER ROUTINE CALL RBFSET ASSIGN RECEIVE CCB AND BUFFER BCS 20 FAILED START THE TRANSMITTER BIS RXITEN R3 ENABLE RECEIVER INTERRUPTS 205 MOV SP R5
47. NRT of a control character initiates the transfer When a transfer has been initiated a character is assembled by the USYNRT and then placed in the low byte of the receive data and status register RDSR when it is available If the RDSR is not available the transfer is delayed until the previous character has been serviced This must take place before the next character is fully assembled or an overrun error exists Refer to ihe description of bit 11 in Table 3 3 for more details on Receiver Overrun 3 19 Servicing of the RDSR 15 the responsibility of the system software in response to the Receive Data Ready RDATRY signal This signal is asserted when a character has been transferred to the RDSR The setting of RDATRY would also cause a receive interrupt request if Receive Interrupt Enable RXITEN is set The software s response to RDATRY is to read the contents of the RDSR At the completion of this operation the new information is loaded into the RDSR and RDATRY is reas serted This operation continues until terminated by some control character The upper byte of the RDSR contains status and error indications which the software can also read The DPV11 will handle data in bit byte count or character oriented protocols With bit oriented protocol only flag characters are used to initiate the transfer of a message Informa tion inserted into the data stream for transparency or control is deleted before it is presented to the RDSR This
48. ONTINUE TST SP CLEAN STATUS OFF THE STACK MOV 85 R4 KILL CCB ADDRESS TO R4 BEQ TREXIT NONE RESTORE R3 AND EXIT CLR R5 gt KILL NO LONGER IN PROGRESS CLR R3 STATUS SUCCESSFUL CMPB FFC KIL C FNC R4 KILL I O OR CONTROL FUNCTION BNE 405 CONTROL POST IT COMPLETE CALL SDDKCP POST KILL I O COMPLETE BR TREXIT RESTORE R3 AND EXIT 40 CALL DDCCP POST CONTROL COMPLETE BR TREXIT RESTORE R3 AND EXIT SBTTL SDASX TRANSMIT ENABLE ENTRY FUNCTION SSDASX IS ENTERED VIA THE DISPATCH TABLE TO QUEUE CCB CONTAINING AN SDLC FRAME TO BE TRANSMITTED IF THE TRANSMITTER IS BUSY THE CCB IS QUEUED TO THE SECONDARY CCB CHAIN IF NOT THE TRANSMITTER IS ENABLED TO START TRANSMITTING THE NEW FRAME ON ENTRY RA ADDRESS OF TRANSMIT ENABLE CCB R5 ADDRESS OF DEVICE LINE TABLE PS PRIORITY OF CALLING DLC PROCESS ON EXIT ALL REGISTERS ARE UNPREDICTABLE SSDASX MOV R3 SP SAVE R3 FOR EXIT VIA TRSTRT MOV D TCSR R5 R3 TRANSMIT CSR ADDRESS SEL 4 TO R3 BIC TXITEN R3 DISABLE TRANSMITTER INTERRUPTS ADD 20 5 POINT TO ACTIVE ADDRESS CELL TST 5 IS THERE AN ACTIVE CCB BEQ TRSTRT NO START UP THE TRANSMITTER MOV RA SP SAVE POINTER TO FIRST CCB 20 MOV R5 R4 COPY THE CCB ADDRESS TO R4 MOV RA R5 ADDRESS OF THE NEXT CCB TO R5 BNE 20 LOOP UNTIL WE FIND THE END MOV SP 4 LINK
49. OV MOV BNE MOV BR w e STSTR BIS BIS MOVB STCTS BIT BNE MOV MOV MOV BR w STSYN MOV STCTS WAIT STSYN SYNC TCSR R5 R3 TXINT R3 GET TRANSMITTER CSR ADDRESS DISABLE TRANSMITTER INTERRUPTS w TPRIM RS POINT TO PRIMARY CELL KISAR6 SP SAVE CURRENT MAPPING R3 SP SAVE R3 R5 4 PRIMARY ASSIGNED 10 IF NE YES QUEUE TO SECONDARY CHAIN TBSET SET UP PRIMARY TXACT R3 TRANSMITTER ACTIVE STSTR IF EQ NO START IMMEDIATELY STSTR R5 SET STATE FOR STARTUP WAITI WAIT FOR INTERRUPT R4 SP SAVE POINTER TO FIRST CCB R5 R4 COPY POINTER TO CCB R4 R5 GET NEXT CCB 20 IF NE KEEP GOING SP R4 LINK NEW CCB CHAIN TO LAST CCB TEXT2 FINISH IN COMMON CODE STSTR STARTUP STATE PROCESSING RTS 4 R3 ASSERT REQUEST TO SEND TXENA R3 ENABLE TRANSMITTER TIMS TTHRD R5 TIME TTHRD R5 START TIMER FOR CLEAR TO SEND STATE PROCESSING CTS 4 R3 IS CLEAR TO SEND UP STSYN IF NE YES START SYNC TRAIN STCTS R5 SET STATE FOR CTS FSPADB R4 SET ADDRESS OF PAD BUFFER 50 SP SET 50 CLEAR 1 FINISH IN COMMON CODE TRAIN REQUIRED STATE PROCESSING STDAT R5 SET STATE FOR DATA D 20 MOV SSYNB R4 SET ADDRESS OF SYNC BUFFER MOV TSOM SP SET TSOM CLEAR BR TEXTO FINISH IN COMMON CODE
50. PDFS SLIBCL MCALL MDCDFS MCALL CHADFS MDCDFS DEFINE MODEM CONTROL SYMBOLS CCBDF DEFINE THE CCB OFFSETS TMPDES DEFINE LINE TABLE OFFSET MACROS CHADFS DEFINE DEVICE CHARACTERISTICS LOCAL SYMBOL DEFINITIONS TRANSMITTER FLAGS TINIT TXENA TXINT TXACT TSOM TEOM 000010 000020 000100 900002 000400 001090 RECEIVE CSR FLAGS RCVEN RXINT CRC SSYN PROSEL RINIT INPRM 000020 002100 3 400 020000 040000 RXINT RCVEN DTR SSYN PROSEL CRC MODEM STATUS FLAGS RTS CTS DTR DSR RING 000004 020000 000002 001000 040000 44 99 ue Ns Se o w w 4 INITIAL TRANSMIT STATUS HALF DUPLEX TRANSMIT TRANSMIT TRANSMIT TRANSMIT TRANSMIT ENABLE INTERRUPT ENABLE ACTIVE START MESSAGE END OF ESSAGE RECEIVE ENABLE RECEIVE INTERRUPT ENABLE RECEIVE CRC CHECK STRIP PROTOCOL BYTE INITIAL RECEIVE STATUS INITIALIZATION FLAGS REQUEST TO SEND LEAD CLEAR TO SEND DATA TERMINAL READY DATA SET READY RING INDICATOR DPV11 DEVICE DRIVER DISPATCH TABLE 4 SDPVTB WORD WORD WORD WORD WORD DPASX DPASR DPKIL DPCTL DPTIM mo TRANSMIT ENABLE RECEIVE ENABLE ASSIGN BUFFER KILL I O CONTROL INITIATION TIME OUT D 14 SDPVRI DPV11 RECEIVE INTERRUPT SERVICE ROUTINE THE DEVICE INTERRUPT IS VECTORED TO THE D
51. PV11 XX M8020 DEVICE ADDRESSING MSB LSB REA pS DES 760010 760020 760030 760040 760050 760060 760070 760100 760200 760300 760400 760500 760600 760700 761000 762000 763000 764000 INDICATES A CONNECTION TO W29 W29 IS TIED GROUND JUMPERS ARE DAISY CHAINED MK 1339 2 4 INSTALLATION The DPV11 can be installed in any LSI 11 bus compatible backplane such as H9270 LSI 11 con figuring rules must be followed Proceed with the installation as follows For additional information refer to PDP 11 03 User Manual EK LSI11 TM LSI 11 Installation Guide EK LSII11 IG l Configure the address and vector jumpers at this time if they have not been previously done Paragraph 2 3 WARNING Turn all power OFF 2 6 Connect the female Berg connector on BC26L 25 cable to J1 on the M8020 module 1 and plug the module into a dual LSI 11 bus slot of the backplane CAUTION Insert and remove modules slowly and carefully to avoid snagging module components on the card guides Connect the 32597 turn around connector to the EIA connection on the BC26L 25 cable The jumper W1 on the H3259 turn around connector must be removed Perform resistance checks from backplane pin AA2 5 V to ground and from AD2 12 V to ground to ensure that there are no shorts on the M8020 module or backplane Turn system power on Check the voltages to ensure that they a
52. RCV OVRUN Receiver Abort Go Ahead RABORT Error Check ERRCHK if VRC is selected Receiver Status Ready RSTARY 10 Receiver Status is cleared by any of the following conditions reading either byte of the RDSR clearing Receiver Enable bit 4 of RXCSR Device Reset or Bus Init When set Receiver Status Ready causes a receive interrupt if Receive Interrupt Enable bit 6 is also set Receiver Status Ready is a read only bit which reflects the state of USYNRT pin 7 Data Mode DM This bit reflects the state of the Data Mode signal from the Data Set Ready modem When this bit is set it indicates that the modem is powered on and not in test talk or dial mode Any transition of this bit causes the Data Set Change bit bit 15 to be asserted unless the Data Mode jumper has been re moved Data Mode is a read only bit and cannot be cleared by software Sync or Flag This bit is set for one clock time when a flag character is de Detect SFD tected with bit oriented protocols or a sync character is de tected with character oriented protocols SFD is a read only bit which reflects the state of USYNRT pin 4 Receive Data This bit indicates that the USYNRT has assembled a data char Ready RDATRY acter and is ready to present it to the processor If this bit becomes set while Receiver Interrupt Enable bit 6 is set a receive interrupt request will result Receive Data Ready is re
53. Reserved Transmit Go Ahead TGA Transmit Abort TXABORT Transmit End of Message TEOM Description TERR is cleared when TSOM TDSR bit 8 becomes set or by Device Reset or Bus INIT Clearing Transmitter Enable PCSCR bit 4 does not clear TERR and TERR is not set with Transmit End of Message Not used by the DPV11 This bit when asserted modifies the bit pattern of the control character initiated by either Transmit Start of Message TSOM or Transmit End of Message TEOM TSOM or TEOM normally causes a flag character to be sent If TGA is set a go ahead character is sent in place of the flag character TGA is only used with bit oriented protocols This bit is used only with bit oriented protocols to abnormally terminate a message or to transmit filler information used to es tablish data link timing When TXABORT is asserted the transmitter automatically transmits either flag or abort characters depending on the state of the IDLE mode bit If IDLE is cleared abort characters are sent If IDLE is set flag characters are sent This control bit is used to normally terminate a message in bit oriented protocol It also terminates a message in character ori ented protocols when CRC error detection is used As a second ary function it is used in conjunction with the Transmit Start of Message TSOM bit to transmit a SPACE SEQUENCE Re fer to the TSOM bit description bit 8 of this register for infor mation
54. T is cleared when the transmitter has nothing to send or when Device Reset or Bus INIT is issued TXACT reflects the state of USYNRT pin 34 When a one is written to this bit all components of the interface are initialized It performs the same function as Bus INIT with respect to this interface Modem Status Data Mode Clear to Send Receiver Ready Incoming Call Signal Quality or Test Mode is not affected RESET is write only it cannot be read by software 5 4 3 2 1 0 11 10 9 8 TERR RESERVED TGA TSOM 1331 Figure 3 6 Transmit Data and Status Register TDSR Format Table 3 6 Transmit Data and Status Register TDSR Bit Assignments Transmitter Error TERR Description This is a read only bit which becomes asserted when the Trans mitter Buffer Empty TBEMTY indication has not been ser viced for more than one character time When TERR occurs in bit oriented protocols the transmit sec tion of the USYNRT generates an abort or flag character based on the state of the IDLE bit PCSAR bit 11 If IDLE is set a flag character is sent If it is reset an abort character is sent When TERR occurs in character oriented protocols the state of the IDLE bit again determines the result If IDLE is set the transmit serial output is held in ihe MARK condition If it 1s cleared a sync character is transmitted 3 17 Table 3 6 Transmit Data and Status Register TDSR Bit Assignments Cont
55. W5 TT 55 W6 EA 5 H3260 TEST NOTE 1 W1 W2 IN 423 A TESTING W3 W6 OUT ii 2 W1 amp W2 OUT RS 422 A TESTING W3 W6 IN 1464 Figure 2 4 H3260 On Board Test Connector 2 11 CHAPTER 3 REGISTER DESCRIPTIONS AND PROGRAMMING INFORMATION 3 1 INTRODUCTION This chapter describes the bit assignments and programming considerations for the DPV11 Some typ ical start and receive sequences for both bit and character oriented protocols are included 3 2 DPV11 REGISTERS AND DEVICE ADDRESSES j The five registers used in the DPV11 are shown in Table 3 1 Note that two of the registers PCSAR and RDSR have the same address This does not constitute a conflict however because the PCSAR is a write only register and the RDSR is a read only register These five registers occupy eight con tiguous byte addresses which begin on a boundary where the low order three bits are zero and can be located anywhere between 1600008 and 1777764 Table 3 1 DPV11 Registers Receive Control and Status 16xxx0 Word or byte addressable Read write Receive Data and Status 16xxx2 _ Word or byte addressable Read only Parameter Control Sync Address 16xxx2 Word or byte addressable Write only f Parameter Control and Character Length PCSCR l6xxx4 Word or byte addressable Read write Transmit Data and Status TDSR 16xxx6 Word or byte addressable Read write Reading either byte of these regist
56. YNC RX SEC ADRS TS DATA LEN SEL EXADD EXCON DATA LEN SEL 00 1503 Figure 2 5025 Internal Register Bit Map 2112517 0 0 Variation Sheet 2 of 2 B 4 APPENDIX C IC DESCRIPTIONS C i GENERAL This appendix contains data on the LSI 11 chips and some of the unusual ICs used by the DPV11 The other ICs are common widely used logic devices Detailed specifications on these chips are readily available and hence are not included here C DC003 INTERRUPT CHIP The interrupt chip is an 18 pin DIP device It provides the circuits to perform an interrupt transaction in a computer system that uses a pass the pulse type arbitration scheme The device provides two interrupt channels labeled A and B with the A section at a higher priority than the B section Bus signals use high impedance input circuits or high drive open collector outputs which allow the device to directly attach to the computer system bus Maximum current required from the supply is 140 mA Figure C 1 is a simplified logic diagram of the DC003 IC Table C 1 describes the signals and pins of the ROSTA H ENA DATAH ENASTH CLK H BIROL BIAKI L BIAKO BINIT L INITO L BDIN L VECTOR H RQSTB H 02 ENB CLK H ENB DATA H ROSTB H ENB ST H MK 0164 Figure C 1 DC003 Logic Symbol C 1 17 10 16 11
57. ablished in the remote modem SF RL is program read write and is cleared by Device Reset Bus INIT 7 6 5 4 3 2 1 0 RECEIVE DATA BUFFER 15 14 13 12 11 10 9 8 ERR ASSEMBLED REC BIT COUNT 1326 Figure 3 3 Receive Data and Status Register RDSR Format Table 3 3 Receive Data and Status Register RDSR Bit Assignments Error Check This bit when set indicates a possible error It is used in con ERR CHK junction with the error detection selection bits of the parameter control sync address register bits 8 10 to indicate either an error or an all zeros state of the CRC register With bit oriented protocols ERR CHK indicates that a CRC error has occurred It is set when the Receive End of Message bit RDSR bit 9 is set With character oriented protocols ERR CHK is asserted with each data character if all zeros are in the CRC register The processor must then determine if this indicates an error free 3 8 Bit 14 12 11 Table 3 3 Receive Data and Status Register RDSR Bit Assignments Cont Assembled Bit Count ABC Receiver Overrun RCV OVRUN message or not If VRC parity is selected this bit is set for every character which has parity error CHK cleared by reading RDSR clearing RXENA RXCSR bit 4 Device Reset or Bus INIT Used only with bit oriented protocols these bits represent the number of valid bits in the last character of a message They ar
58. al MATCH The MATCH output is open collector which allows the output of several transceivers to be wire ANDed to form a composite address match signal The address jumpers can also be put into a third logical state that disconnects that jumper from the address match allowing for don t care ad dress bits In addition to the three address jumper inputs a fourth high impedance input line is used to enable disable the MATCH output Three vector jumper inputs are used to generate a constant that can be passed to the computer bus The three inputs directly drive three of the bus lines overriding the action of the control lines Two control signals are decoded to give three operational states receive data transmit data and dis able VECTOR 1 200 Vcc BDAL2 L C 2 19 H BDAL1 33 18 BDALO LCJ 4 17 15 16 L BWTBT L 5 169 SEL4 L BSYNC L C16 15 15 121 BDIN L 17 14 3 L BRPLY L 18 i3EJourHB L BDOUT L 19 12 JOUTLB L GND 10 11 inwo L VCC ENB H 19 D 1 ENB LATCH Loj gt 01 6 BDAL2 1 02 D 1 02 LATCH DAL 2 DECODER BDAL1 L 03 D 1 01 LATCH a DAL 1 ILE BDALO L 04 D 1 00 LATCH G 0 BwTBT L 05 gt O DID 1 1 DD 09 E gt rq Figure 2 DC004 Simplified Logic Diagram C 4 10 cno 17 sEL 6 L 16 1 41 M5 sEL 21 14 5 101 113JOUTHB L 12
59. as serious limitations for use in modern data communication systems The most critical limitations are in speed and distance 1 3 For this reason RS 449 standard has been developed to replace 5 232 It maintains a degree of compatibility with RS 232 C to accommodate an upward transition to RS 449 The most significant difference between RS 232 C and RS 449 is in the electrical characteristics of signals used between the data communication equipment DCE and the data terminal equipment DTE The RS 232 C standard uses only unbalanced circuits while the RS 449 uses both balanced and unbalanced electrical circuits The specifications for the types of electrical circuits supported by RS 449 are contained in standards RS 422 A for balanced circuits and RS 423 A for unbalanced circuits These new standards permit much greater transmission speed and will allow greater distance between DTE and DCE The maximum transmission speeds supported by RS 422 A and RS 423 A circuits vary with cable length the normal speed limits are 20K b s for RS 423 A and 2M b s for RS 422 A both at 61 m 200 feet Another major difference between RS 232 C and RS 449 is that additional leads are needed to support the balanced interface circuits and some new circuit functions Two new connectors have been specified to accommodate these new leads One connector is a 37 pin Cinch used in applications requiring sec ondary channel functions Some of the new circuits a
60. ata flow into and out of up to four word registers 8 bytes Bus signals can directly attach to the device because receivers and drivers are provided on the chip An RC delay circuit is provided to slow the response of the peripheral interface to data transfer requests The circuit is designed such that if tight tolerance is not required then only an external 1K X20 percent resistor is necessary External RCs can be added to vary the delay Maximum current required from the supply is 120 mA Figure C 2 is a simplified logic diagram of the DC004 IC Signal and pin definitions for the DC004 are shown in Table C 2 4 DC005 BUS TRANSCEIVER CHIP The 4 bit transceiver is a 20 pin DIP low power Schottky device for primary use in peripheral device interfaces functioning as a bidirectional buffer between a data bus and peripheral device logic In addition to the isolation function the device also provides comparison circuit for address selection and a constant generator useful for interrupt vector addresses The bus I O port provides high imped ance inputs and high drive 70 mA open collector outputs to allow direct connection to a computer s data bus On the peripheral device side a bidirectional port is also provided with standard TTL inputs and 20 mA tri state drivers Data on this port is the logical inversion of the data on the bus side Three address jumper inputs are used to compare against three bus inputs and to generate the sign
61. block of data by a predetermined binary number Data Link Escape DLE A control character used exclusively to provide supplementary line control signals control char acter sequences or DLE sequences These are 2 character sequences where the first character is DLE The second character varies according to the function desired and the code used Data Phone DIGITAL Service DDS communicaitons service of the Bell System in which data is transmitted in digital rather than analog form thus eliminating the need for modems DIGITAL Data Communications Protocol DDCMP DIGITAL s standard communications protocol for character oriented protocol Direct Memory Access DMA Permits I O transfer directly into or out of memory without passing through the processor s gen eral registers Electronic Industries Association EIA A standards organization specializing in the electrical and functional characteristics of interface equipment Full Duplex FDX Simultaneous 2 way independent transmission in both directions Field Replaceable Unit FRU Refers to a faulty unit not to be repaired in the field is replaced with a good unit and faulty unit is returned to predetermined location for repair Half Duplex HDX An alternate one way at a time independent transmission LARS Field Service Labor Activity Reporting System Non Processor Request NPR Direct memory access type transfers see Protocol A formal set o
62. bnormally When REOM becomes set it sets RSTARY bit 10 of RXCSR The go ahead character is defined as a zero bit followed by sev Message REOM REOM is cleared when RDSR is read or when Receive Enable bit 4 of RXCSR is reset Receiver Start of Used only with bit oriented protocols This bit is presented to Message RSOM the processor along with the first data character of a message and is synchronized to the last received flag character Setting of RSOM does not set RSTARY RXCSR bit 10 RSOM is cleared by Device Reset Bus INIT resetting Re ceiver Enable RXCSR bit 4 or the next transfer into the Re ceive Data buffer low byte of RDSR 7 0 Receive Data The low byte of the RDSR is the Receive Data buffer The se Buffer rial data input to the USYNRT 15 assembled and transferred to the low byte of the RDSR for presentation to the processor When the RDSR receives data Receive Data Ready bit 7 of RXCSR becomes set to indicate that the RDSR has data to be picked up If this data is not read within one character time a data overrun occurs 9 Receiver End of The characters in the Receive Data buffer are right justified with bit O being the least significant bit 3 10 7 6 5 4 3 2 1 0 SYNC CHARACTER SECONDARY STATION ADDRESS 15 14 13 12 11 10 9 8 SEC PROT STRIP PA IDLE ERR DET SEL 5 SEL SYNC MDE MK 1330 Figure 3 4 Parameter Control Sync Address Register PCSAR Format Tab
63. cols IDLE is used to select the type of control character issued when either Transmit Abort bit 19 of TDSR is set or a data underrun error occurs If IDLE is set flag characters are issued If IDLE is clear abort characters are issued With character oriented protocols IDLE is used to control the method in which initial sync characters are transmitted and the action of the transmit section of the USYNRT when an under run error occurs IDLE is cleared to cause sync characters from the low byte of PCSAR to be transmitted When IDLE is set the transmit data output is held asserted during an underrun er ror and at the end of a message Error Detection These bits are used to determine the type of error detection used Selection on received and transmitted messages In bit oriented protocols ERR DEL SEL the selection is independent of character length In character and byte count oriented protocols CRC error detection is us able only with 8 bit character lengths The maximum character length for VRC is seven The bits are encoded as follows 10 9 8 CRC Polynomial 0 0 0 xl6 x12 x5 1 CRC CCITT Both CRC data registers in the transmit and receive sec tions are set to all ones prior to the com putation 0 0 1 x 6 x12 x5 1 CRC CCITT Both CRC data registers set to all zeros 3 12 Bit 7 0 Table 3 4 Parameter Control Sync Address Register PCSAR Bit Assignments Cont 0 1 0 Not used 0 1 1 x16 x15 x2 1
64. complete one pass and give control back to the super visor EOP Used to specify how many passes of the diagnostic will occur before the end of pass message is printed the default is one UNITS Used to specify the units to be run This switch is valid only if was entered in response to the CHANGE HW question FLAGS Used to check for conditions and modify program execution accordingly The conditions checked for are as follows HOE an error transfers control back to the supervisor LOE Loop on error Inhibit error reports IBE Inhibit basic error information Inhibit extended error information PRI Print errors on line printer Print the number of the test being executed prior to execution BOE Ring bell on error Run in unattended mode bypass manual intervention tests ISR Inhibit statistical reports IOU Inhibit dropping of units by program 4 2 Control Escape Characters Supported The keyboard functions supported by the diagnostic supervisor are as follows CONTROL 1C Returns control to the supervisor The gt prompt would be typed in response to CONTROL C This function can be typed at any time A 4 e CONTROL Z 1Z Used during hardware or software dialogue to terminate the dialogue and select default values e CONTROL fO Disables all printouts This is valid only during a printout CONTROL 5 1S Used duri
65. connected to the USYNRT s serial input The serial send data output line from the interface is asserted and the receive data serial input is disabled Send timing and receive timing to the USYNRT are disabled and replaced with a clock signal generated on the interface The clock rate is either 49 152K b s or 1 9661K b s depending on the position of a jumper on the interface board Maintenance mode allows diagnostics to run in loopback with out disconnecting the modem cable MM SEL is a read write bit and is cleared by Device Reset or Bus INIT When it is cleared the interface is set for normal op eration This bit is asserted when the transmit data and status register TDSR is available for new data or control information It is also set after a Device Reset or Bus INIT The TDSR should be loaded only in response to TBEMTY being set When the TDSR is written into TBEMTY is cleared If TBEMTY becomes set while Transmit Interrupt Enable bit 6 of PCSCR is set a transmit interrupt request results TBEMTY reflects the state of USYNRT pin 35 3 16 Table 3 5 Parameter Control and Character Length Register PCSCR Bit Assignments Cont Bit 1 15 Transmitter Active TXACT Device Reset RESET 7 6 TRANSMIT DATA BUFFER Description This bit indicates the state of the transmit section of the US YNRT It becomes set when the first character of data or con trol information is transmitted TXAC
66. dded in RS 449 support local and remote loopback testing and stand by channel selection CHAPTER 2 INSTALLATION 2 1 INTRODUCTION This chapter provides all the information necessary for a successful installation and subsequent check out of the DPV11 Included are instructions for unpacking and inspection pre installation installation and verification of operation 2 2 UNPACKING AND INSPECTION The DPV11 is packaged in accordance with commercial packing practices Remove all packing mate rial and verify that the following are present M8020 module H3259 turn around connector BC26L 25 cable DPV11 User Manual EK DPV11 UG LIB kit ZJ314 RB Field Maintenance Print Set MP00919 Inspect all parts carefully for cracks loose components or other obvious damage Report damages or shortages to the shipper immediately and notify the DIGITAL representative 2 3 PRE INSTALLATION REQUIREMENTS Table 2 1 Configuration Sheet provides a convenient quick reference for configuring jumpers Table 2 1 Configuration Sheet W1 W2 Driver Attenuation Jumper Normal Alternate Configuration Option o W3 W11 Interface Selection Jumpers Driver Description Terminal Bypasses attenuation resistor Timing Jumper must be removed for cer tain modems to operate properly Alternate Option Normal Configuration Input Signals Description SQ TM Signal quality PCSCR 5 W7
67. e all zeros unless the message ends on an unstated boundary The bits are encoded to represent valid bits as shown below Number of Valid Bits 14 13 12 0 0 0 bits are valid 0 0 1 One valid bit 0 1 0 Two valid bits 0 1 1 Three valid bits 1 0 0 Four valid bits 1 0 1 Five valid bits 1 1 0 Six valid bits l 1 1 Seven valid bits These bits are presented simultaneously with the last bits of data and are cleared by reading the RDSR or by resetting RXENA bit 4 of RXCSR This bit is used to indicate that an overrun situation has oc curred Overrun exists when the data buffer bits 0 7 of RDSR has not been serviced within one character time As a general rule the overrun is indicated when the last bit of the current character has been received into the shift register of the USYNRT and the data buffer is not yet available for a new character Two factors exist which modify this general rule and apply only to bit oriented protocols The first factor is the number of bits inserted into the data stream for transparency For each bit inserted during the for matting of the current character the controller s maximum re sponse time is increased by one clock cycle The second factor is the result of termination of the current message When this occurs the data of the terminated message which is within the USYNRT is not overrunable If an attempt is made to displace this data by the reception of a subsequent message the data of the s
68. e selected length will be presented to the receive buffer Sync characters following the initial two will be presented to the buffer and included in the CRC computation unless the Strip Sync bit is set If vertical redundancy check VRC parity checking is selected the parity bit itself is deleted from the character before it is presented to the buffer 3 4 2 Transmit Data System software loads information to be transmitted to the modem into the transmit data and status register TDSR This does not ordinarily include error detection or control character information Loading of the TDSR occurs in response to the Transmitter Buffer Empty TBEMTY signal from the USYNRT The character length of information to be transmitted is established by the software when it loads the transmit character length register bits 13 14 and 15 of the PCSCR The default length of eight is assigned when the transmit character length register equals zero The length of characters presented to the TDSR should not exceed the assigned character length When the information in the TDSR is transmitted the signal is again asserted to request another character The setting of TBEMTY also causes a transmit interrupt request if Transmit Interrupt Enable is set Byte count or character oriented protocols require the transmission of synchronizing information nor mally referred to as sync characters The sync characters can be transmitted when Transmit Start of Message
69. e supervisor commands are listed in Paragraph A 4 Five Steps to Run a Supervisor Diagnostic l Enter Start command When the prompt DR gt is issued type STA PASS 1 FLAGS HOE lt CR gt The switches and flags are optional 2 Enter number of units to be tested The program responds to the Start command with UNITS At this point enter the number of devices to be tested A 2 Answer hardware parameter questions After the number of devices to be tested has been entered the program responds by asking a number of hardware questions The answers to these questions are used to build hardware parameter tables in memory A series of questions is posed for each device to be tested A Hardware P Table is built for each device Answer software parameter questions When all the Hardware P Tables are built the program responds with CHANGE SW If other than the default parameters are desired for the software type Y If the default pa rameters are desired type N If you type Y a series of software questions will be asked and the answers to these will be entered into the Software P Table in memory The software questions will be asked only once regardless of the number of units to be tested Diagnostic execution After the software questions have been answered the diagnostic begins to run What happens next is determined by the switch options selected with the Start command or errors occurring during execution of the dia
70. ers clears data and certain status bits in other bytes See Paragraphs 3 3 1 and 3 3 2 Registers contained within the USYNRT t It is not possible to do bit set or bit clear instructions on this register The high byte of this register is internal to USYNRT The DPV11 uses a universal synchronous receiver transmitter USYNRT chip which accounts for a large portion of the DPV11 s functionality The USYNRT provides complete serialization deserializa tion and buffering of data to and from the modem 3 1 Most of the DPV11 registers are internal to the USYNRT Only the receiver control and status regis ter RXCSR and the low byte of the parameter control and character length register PCSCR are external NOTE When using the special space sequence function all registers internal to the USYNRT must be written in byte mode 3 3 REGISTER BIT ASSIGNMENTS Bit assignments for the five DPV11 registers are shown in Figure 3 1 Paragraphs 3 3 1 3 3 5 provide a description of each register using a bit assignment illustration and an accompanying table with a de tailed description of each bit 3 3 1 Receive Control and Status Register RXCSR Address 16xxx0 Figure 3 2 shows the format for the receive control and status register RXCSR Table 3 2 is a de tailed description of the register This register is external to the USYNRT NOTE The RXCSR can be read in either word or byte mode However reading either byte resets certain
71. erted by the requesting device Asynchronous Bus Interrupt Request The request is generated by a true RQST signal along with the associated true Interrupt Enable signal The request is removed after the acceptance of the BDIN L signal and on the leading edge of the BAIKI L sig nal or the removal of the associated interrupt enable or due to the removal of the associated request signal Device Interrupt Request Signal When asserted with the en able A B flip flop asserted this signal causes the assertion of BIRQ L on the bus This signal line normally remains asserted until the request is serviced Interrupt Enable This signal indicates the state of the inter rupt enable A B internal flip flop which is controlled by the sig nal line ENA B DATA H and the ENA B CLK H clock line Table C 1 Pin Signal Descriptions Cont Description 15 ENA DATA H Interrupt Enable Data The level on this line in conjunction 12 ENB DATA H with the ENA B CLK H signal determines the state of the in ternal interrupt enable A flip flop The output of this flip flop is monitored by the ENA B ST H signal 14 ENA CLK H Interrupt Enable Clock When asserted on the positive edge 13 ENB CLK H interrupt enable A B flip flop assumes the state of the ENA B DATA H signal line C 3 DC004 PROTOCOL CHIP The protocol chip is a 20 pin DIP device that functions as a register selector providing the signals necessary to control d
72. f conventions governing the format and relative timing of message exchange be tween two communicating processes RS 232 C EIA standard single ended interface levels to modem KS 422 A EIA standard differential interface levels to modem RS 423 A EIA standard single ended interface levels to modem G 2 RS 449 standard connections for RS 422 A and RS 423 A to modem interface Synchronous Transmission Transmission in which the data characters and bits are transmitted at a fixed rate with the trans mitter and receiver synchronized V 35 CCITT Standard Differential current mode type signal interface for high speed modems DPV11 Serial Synchronous Reader s Comments interface User Guide EK DPV11 UG 001 Your comments and suggestions will help us in our continuous effort to improve the quality and useful ness of our publications What is your general reaction to this manual In your judgement is it complete accurate well organized well written etc Is it easy to use What features are most useful What faults or errors have you found in the manual Does this manual satisfy the need you think it was intended to satisfy Does it satisfy your needs O Please send me the current copy of the Technical Documentation Catalog which contains information on the remainder of DIGITAL s technical documentation Name C Ot Title ree Company ss State Country Department
73. gnostic A 4 SUPERVISOR COMMANDS The supervisor commands that may be issued in response to the DR prompt are as follows Start Starts a diagnostic program Restart When a diagnostic has stopped and control is given back to the supervisor this command restarts the program from the beginning Continue Allows a diagnostic to continue running from where it was stopped Proceed Causes the diagnostic to resume with the next test after the one in which it halted Exit Transfers control to the XXDP monitor Drop Drops units specified until an Add or Start command is given Add Adds units specified These units must have been previously dropped Print Prints out statistics if available Display Displays P Tables Flags Used to change flags ZFLAGS Clears flags All of the supervisor commands except Exit Print Flags and ZFLAGS can be used with switch op tions A 3 A 4 1 Command Switches Switch options may be used with most supervisor commands The available switches and their function are as follows TESTS Used to specify the tests to be run the default is all tests An example of the tests switch used with the Start command to run tests 1 through 5 19 and 34 through 38 would be DR gt START TESTS 1 5 19 34 38 lt CR gt PASS Used to specify the number of passes for the diagnostic to run For example DR gt START PASS 1 In this example the diagnostic would
74. haracter oriented protocols In character ori ented protocols all sync characters after the initial synchro nization are deleted from the message and not included in the CRC computation if this bit is set If it is cleared all sync char acters rem in in the message and are included in the CRC com putation Table 3 4 Parameter Control Sync Address Register PCSAR Bit Assignments Cont Description 2 Loop Mode bit oriented protocols With bit oriented pro tocols this bit is used to control the method of termination If it is set either a flag or go ahead character can cause a normal termination of a message If it is cleared only a flag character can cause a normal termination Secondary This bit is used with bit oriented protocols when automatic rec Address Mode ognition of the secondary station address is desired If it is set SEC ADR MDE the station address of the incoming message is compared with the address stored in the low byte of this register Only messages prefixed with the correct secondary address are presented to the processor If the addresses do not compare the receive section of the USYNRT goes back to searching for flag or go ahead characters When SEC ADR MDE is cleared the receive section of the USYNRT recognizes all incoming messages Idle Mode Select This bit is used with both bit and character oriented protocols IDLE With bit oriented proto
75. he interface includes a charge pump to generate a negative voltage required to power the RS 423 A drivers The DPV11 presents 1 ac load and 1 dc load to the LSI 11 bus 1 5 3 Performance Parameters Performance parameters for the DPV11 are listed as follows Operating Mode Full or half duplex Data Format Synchronous BISYNC DDCMP and SDLC Character Size Program selectable 5 8 bits with character oriented protocols and 1 8 bits with bit oriented protocols Max Configuration 16 DPV11 modules per LSI 11 bus Max Distance 15 m 50 ft for RS 232 C 61 m 200 ft for RS 423 A RS 422 A Distance is directly dependent on speed and 200 ft is a suggested average See RS 449 specifica tion for details Max Serial Data Rates 56K b s May be less because of software and memory refresh limitations 1 6 DPV11 CONFIGURATIONS There are two DPV11 configurations the DA and the DB DPV11 DA Unbundled version consists of M8020 module DPV11 Maintenance Reference Card EK DPV11 CG DPV11 DB Bundled version consists of M8020 module H3259 turn around connector BC26L 25 cable DPV11 User Manual EK DPV11 UG DPV11 Maintenance Reference Card EK DPV11 CG LIB kit ZJ314 RB Field Maintenance Print Set MP00919 Turn around connectors cables and documentation may be purchased separately 1 7 EIA STANDARDS OVERVIEW RS 449 RS 232 C The most common interface standard used in recent years has been the RS 232 C However this stand ard h
76. ice Interrupt control logic generates requests for the transfer of data between the DPV11 and the LSI 11 memory by means of the LSI 11 bus Figure 1 1 shows the DPV11 system RS 232 C MODEM TELEPHONE BC26L 25 LINE LSI BUS MK 1320 Figure 1 1 DPV11 System 1 1 13 DPV11 OPERATION The DPV11 is a double buffered program interrupt interface that provides parallel to serial conversion of data to be transmitted and serial to parallel conversion of received data The DPV11 can operate at speeds up to 56K b s It has five 16 bit registers which can be accessed in word or byte mode These registers are assigned a block of four contiguous LSI 11 bus word addresses that start on a boundary with the low order three bits being zeros This block of addresses is jumper selectable and may be located anywhere between 160000g and 1777768 Two of these registers share the same address One is accessed during a read from the address the other during a write to the address For a detailed descrip tion of each of the five registers refer to Chapter 3 These registers are used for status and control information as well as data buffers for both the transmitter and receiver portions of the DPV11 1 4 DPV11 FEATURES Features of the DPV11 include Full duplex or half duplex operation Double buffered transmitter and receiver o EIA RS 232 C compatibility All EIA RS 449 Category I modem control e Partial Category I modem
77. le 3 4 Parameter Control Sync Address Register PCSAR Bit Assignments 15 Parties Addressed APA 14 Protocol Select PROT SEL 13 Strip Sync or Loop Mode STRIP SYNC Description This bit is set when automatic recognition of the All Parties Ad dressed character is desired The All Parties Addressed charac ter is eight bits of ones with necessary bit stuffing so as not to be confused with the abort character Recognition of this character is done in the same way as the sec ondary station address see bit 12 of this register except that the broadcast address is essentially hardwired within the receive data path The logic inspects the address character of each frame for the broadcast address When the broadcast address is recognized the USYNRT makes it available and sets Receiver Start of Message bit 8 of RDSR If the broadcast address is not recognized one of two possible actions occurs 1 Ifthe Secondary Address Select mode bit bit 12 is set a test of the secondary station address is made 2 If bit 12 is not set or the secondary station address is not recognized the receive section of the USYNRT renews its search for synchronizing control characters This bit is used to select between character and byte count ori ented or bit oriented protocols It is set for character and byte count oriented protocols and reset for bit oriented protocols This bit serves the following two functions 1 Strip Sync c
78. means that only data characters are available to the software The first two characters of every message or frame are defined to be 8 bit characters and the USYNRT will handle them as such regardless of the programmed character length All subsequent data is formatted in the selected charac ter length When CRC error detection is selected the received CRC check characters are not present ed to the software but the error indication will be presented if an error has been detected If the secondary address mode is implemented the first received data character must be the selected address If this is not the case the USYNRT will renew its search for flag or go ahead characters Refer to the description of bit 12 of the PCSAR in Table 3 4 With byte count or character oriented protocols two consecutive sync characters are required to syn chronize the transfer of data The sync characters used in the message must be the same as the sync character loaded by the software into the low byte of the parameter control sync address register PCSAR If leading sync characters subsequent to the initial two syncs are to be deleted from the data stream the Strip Sync bit bit 13 must also be set in the upper byte of the PCSAR The charac ter length of the data to be received should also be set in bits 8 9 and 10 of the parameter control and character length register PCSCR Sync characters and data must have the same character length and only characters of th
79. ndicates that there is a high proba bility of errors in the received data Table 3 5 Parameter Control and Character Length Register PCSCR Bit Assignments Cont Transmitter Enable TXENA Maintenance Mode clect MM SEL Transmitter Buffer Empty TBEMTY Description When jumpered for the test mode W6 to W7 this bit indicates that the modem has been placed in a test condition when as serted The modem test condition could be established by assert ing Local Loopback bit 3 of RXCSR Remote Loopback bit 0 of RXCSR or other means external to the 11 When SQ TM is clear it indicates that the modem is not in test mode and is available for normal operation SQ TM is program read only and cannot be cleared by soft ware This bit must be set to initiate the transmission of data or con trol information When this bit is cleared the transmitter will revert back to the mark state once all indicated sequences have been completed TXENA should be cleared after the last data character has been loaded into the transmit data and status reg ister TDSR Transmit End of Message bit 9 of TDSR should be asserted when TXENA is reset if it is to be asserted at all and remain asserted until the transmitter enters the idle mode TXENA is connected directly to USYNRT pin 37 It is a read write bit and is reset by Device Reset or Bus INIT When this bit is asserted it causes the USYNRT s serial output to be internally
80. ng a printout to temporarily freeze the printout e CONTROL TQ Resumes a printout after a CONTROL 8 A 5 THE SETUP UTILITY Setup is a utility program that allows the operator to create parameters for a supervisor diagnostic prior to execution This is valid for either or ACT SLIDE environments Setup asks the hardware and software questions and builds the P Tables The following commands are available under Setup List list supervisor diagnostics Setup create P Tables Exit return control to the supervisor The format for the List command is LIST DDN FILE EXT Its function is to type the file name and creation date of the file specified if it is a revision C or later supervisor diagnostic If no file name is given all revision C or later supervisor diagnostics are listed The default for the device is the system device and wild cards are accepted The format for the Setup command is SETUP DDN FILE EXT DDN FILE EXT It reads the input file specified and prompts the operator for information to build P Tables An output file is created to run in the environment specified File names for the output and input files may be the same The output and input device may be the same The default for the device is the system device and wild cards are not accepted APPENDIX B USYNRT DESCRIPTION 5625 Universai Synchronous Receiver Transmitter USYNRT The data paths of the USYNRT provide complete serialization deserializa
81. ous Transmission Transmission in which time intervals between transmitted characters may be of unequal length Transmission is controlled by start and stop elements at the beginning and end of each character Also called start stop transmission BDIN Data Input on the LSI II bus BDOUT Data Output on the LSI II bus BIAKI Interrupt Acknowledge Bit Stuff Protocol Zero insertion by the transmitter after any succession of five continuous ones designed for bit oriented protocols such as IBM s Synchronous Data Link Control SDLC Bits per Second b s Bit transfer rate per unit of time BIRQ Interrupt Request priority level for LSI 11 bus BRPLY LSI 11 Bus Reply BRPLY is asserted in response to BDIN or BDOUT BSYNC Synchronize asserted by the bus master device to indicate that it has placed an address on the bus Buffer Storage device used to compensate for a difference in the rate of data flow when transmitting data from one device to another BWTBT Write Byte CCITT Comite Consultatif Internationale de Telegraphie et Telephonie An international consultative committee that sets international communications usage standards Control and Status Registers CSRs Communication of control and status information is accomplished through these registers Cyclic Redundancy Check CRC An error detection scheme in which the check character is generated by taking the remainder after dividing all the serialized bits in a
82. peration It contains the following categories of information O General description including features specifications and configurations e Installation Programming The manual also contains four appendixes which include diagnostic information integrated circuit de scriptions and programming examples The DPV11 Field Maintenance Print Set MP00919 contains useful additional information vii CHAPTER 1 INTRODUCTION 1 1 SCOPE This chapter contains introductory information about the DPV11 It includes a general description and a brief overview of the DPV11 operation features general specifications and configurations 1 2 DPV11 GENERAL DESCRIPTION The DPV11 is a serial synchronous line interface for connecting an LSI 11 bus to a serial synchronous modem that is compatible with RS 232 C interface standards and EIA RS 423 A and RS 422 A electrical standards EIA RS 422 A compatibility is provided for use in local communications only timing and data leads only The is intended for character oriented protocols such as BISYNC byte count oriented protocols such as DDCMP or bit oriented data communication protocols such as SDLC The DPV11 does not provide automatic error generating and checking for BISYNC The DPV11 consists of one double height module and may be connected to an EIA RS 232 C modem by a BC26L 25 RS 232 C cable The DPV11 is a bus request device only and must rely on the system software for serv
83. pin definitions for the DC005 are shown in Table C 3 C 5 26LS32 QUAD DIFFERENTIAL LINE RECEIVER 261 532 line receiver is 16 pin DIP device Terminal connections are shown in Figure C 4 C 6 8640 UNIBUS RECEIVER The 8640 is a quad 2 input NOR Its equivalent circuit is shown in Figure C 5 C 7 8881 NAND The 8881 is a quad 2 input NAND The schematic and pin identifications are shown in Figure C 6 C 8 9636A DUAL LINE DRIVER The 9636A is an 8 pin DIP device specified to satisfy the require 15 of EIA standards RS 423 A and RS 232 C Additionally it satisfies the requirements cf CCITT V 28 V 10 and the federal standard FIPS 1030 The output slew rates are adjustable by a single external resistor connected from pin 1 to ground The logic diagram and terminal identification are shew in Figure C 7 C 9 9638 DUAL DIFFERENTIAL LINE DRIVER The 9638 is an 8 pin DIP device specified to satisfy the requirements of EIA RS 422 A and CCITT V 11 specifications The logic diagram and terminal identification are shown in Figure C 8 C 6 DC005 TRANSCEIVER BUSO L BUS1 L JAI L BUS2 L 2 JA2 L gt BUS3 L JA3 L MENB L XMIT H REC H T 20 Vcc 10 GND JAIL 1 20 Vcc JA2L 2 19 JA3 L MATCH H 3 18 DATO H RECH 4 17 DATI H XMIT H 5 16 JV3 H DAT3H 6 15 JV2H DAT2H 7 14 JV1H BUS3 L 8 13 MENB L BUS2 L 9 12 BUSO L GND 10 11 BUSI L 0170 Figure C 3 DC005 Simplified Logic Diagram C 7
84. racter Length Reserved Transmit Interrupt Enable TXINTEN Signal Quality or Test Mode SQ TM Description CON is set it extends the control field from one 8 bit byte to two 8 bit bytes EXCON is not used with Secondary Address Mode bit 12 of PCSAR EXCON is read write and is reset by Device Reset or Bus INIT These bits are used to determine the length of the characters to be received They are encoded to set up character lengths as follows 10 9 8 Character Length 0 0 0 Eight bits per character 1 l 1 Seven bits character 1 1 O Six bits per character 1 0 1 Five bits per character 1 0 O Four bits per character bit oriented protocols only 0 1 1 Three bits per character bit oriented proto cols only 0 Two bits per character bit oriented protocols only 0 0 1 One bit character bit oriented protocols only Not used by the DPV11 When set this bit allows a transmitter interrupt request to be made to the transmitter vector when Transmit Buffer Empty 15 asserted Transmit Interrupt Enable TXIN TEN is read write and is cleared by Device Reset or Bus INIT This bit can be wire wrap jumpered to function as either Signal Quality or Test Mode When jumpered for signal quality W5 to W6 this bit reflects the state of the signal quality line from the modem When as serted it indicates that there is a low probability of errors in the received data When clear it i
85. re within the specified tolerances Table 2 4 If voltages are not within specified tolerances replace the associated regulator H780 P S Table 2 4 Voltage Requirements Backplane Pin ERE 5 25 4 75 2 4 1 Verification of Hardware Operation The M8020 module is now ready to be tested by running the CVDPV diagnostic Additional informa tion on the DPV11 diagnostics is contained in Appendix A Proceed as follows NOTE The represents the revision level of the diagnos tic Load and run CVDPV Three consecutive error free passes of this test is the minimum re quirement for a successful run If this cannot be achieved check the following Board seating Jumper connections Cable connection Test connector If a successful run is still unachievable corrective maintenance is required Load and run the DEC X11 System Exerciser configured to test the number of 115 in the system Each DEC X11 CXDPV module will test up to eight consecutively addressed 1 18 CXDPV uses a software switch register Refer to the DEC X11 Cross Reference AS 055 for switch register utilization If a BC26L 25 cable and H3259 turn around connector are not available an on board test connector H3260 can be or dered separately See Paragraph 2 5 2 7 The DEC X11 System Exerciser is designed to achieve maximum contention with all de vices that make up the system configuration It is within this environment that the CXDPV
86. regarding this sequence With bit oriented protocols asserting this bit causes the CRC information to be transmitted if CRC is enabied followed by flag or go ahead characters depending on the state of the Trans mit Go Ahead TGA bit See bit 11 of this register With character oriented protocols asserting this bit causes CRC information if CRC is enabled to be transmitted followed by either sync characters or a MARK condition depending on the state of the IDLE bit If IDLE is cleared sync characters are transmitted The character following the CRC information is repeated until the transmitter is disabled or the TEOM bit is cleared A subsequent message may be initiated while the transmit sec tion of the USYNRT is active This is accomplished by clearing the TEOM bit and supplying new message data without setting 7 0 3 4 DATA TRANSFERS Table 3 6 Transmit Data and Status Register TDSR Bit Assignments Cont Transmit Start of Message TSOM Transmit Data Buffer Description the Transmit Start Of Message bit However the CRC charac ter for the prior message must have completed transmission This bit is used with either bit or character oriented protocols As long as it remains asserted flag characters bit oriented pro tocols or sync characters character oriented protocols are transmitted With bit oriented protocols a space sequence byte mode only of 16 zero bits can be transmitted by asserting TSO
87. set when either byte of RDSR is read Receiver Enable bit 4 is cleared or Device Reset or Bus INIT is issued RDATRY is a read only bit which reflectes the state of US YNRT pin 6 Table 3 2 Receive Control and Status Register RXCSR Bit Assignments Cont 6 Receiver Interrupt When set this bit allows interrupt requests to be made to the Enable RXITEN receiver vector whenever RDATRY bit 7 becomes set The conditions which cause the interrupt request are the asser tion of Receive Data Ready bit 7 Receive Status Ready bit 10 or Data Set Change bit 15 if DSITEN bit 5 is also set RXITEN is a program read write bit and is cleared by Device Reset or Bus INIT 5 Data Set Interrupt This bit when set along with RXITEN allows interrupt Enable DSITEN requests to be made to the receiver vector whenever Data Set Change bit 15 becomes set DSITEN is a program read write bit and is cleared by Device Reset or Bus INIT 4 Receiver Enable This bit controls the operation of the receive section of the US RXENA YNRT When this bit is set the receive section of the USYNRT is en abled When it is reset the receive section is disabled In addition to disabling the receive section of the USYNRT re setting bit 4 reinitializes all but two of the USYNRT receive registers The two registers not reinitialized are the character length selection buffer and the parameter control register 3 Local Loopback Asserting this bit
88. smit data and status register TDSR is shown in Figure 3 6 and Table 3 6 is a detailed description The TDSR is a read write register which can be accessed in either word or byte mode with no restrictions All bits can be read from or written into and are reset by Device Reset or Bus INIT except where noted RXCSR 16XXX0 READ WRITE 15 14 13 12 11 10 09 08 07 06 05 04 03 02 0 00 DATA RCV RCV DATA LOCAL DATA SET ACTIVE CHANGE INCOMING RCVR RCVR SYNC RCV RX REQ SF RL CALL READY STATUS OR INTR ENA TO READY FLAG EN SEND DETECT RDSR 16XXX2 MK 1504 READ ONLY 15 14 13 12 11 10 09 08 07 00 ASSEMBLED ERROR RCVR CHECK OVER RUN RCV START ABORT OF MESG PCSAR 05 15 16 2 WRITE ONLY 15 14 13 12 11 10 09 08 07 00 ERROR DETECTION ENNMNEN OR DETECT SECOND ARE SUN E RECEIVE RINNE ALL PARTIES ADDR STRIP SYNC OR LOOP MODE PROTOCOL SECD SELECT ADRS MODE SEL IDLE MODE SELECT MK 1506 Figure 3 1 DPVI1 Register Configurations and Bit Assignments Sheet 1 of 2 3 3 PCSCR 16XXX4 READ WRITE 15 14 13 12 11 10 09 07 06 05 04 03 02 00 L TRANSMITTER EXTD RECEIVER RSVD SQ TM MAINT XMTR CHARACTER LENGTH ADDR CHARACTER LENGTH MODE ACTIVE FIELD SELECT EXTD XMIT XMTR XMTR DEVICE CONT INTR ENAB BUFFER RESET FIELD EN EMPTY MK 1507 TDSR 16XXX6 READ WRITE 15 14 13 12 11 10 09 08 07 00 R W R W R W R W R W RAN R W
89. t DAT2 16 JV3 DAT3 MATCH MENB L MATCH H Cam gt gt gt DN EEE XMIT H REC H Table C 3 DC005 Pin Signal Descriptions Description Bus Data This set of four lines constitutes the bus side of the transceiver Open collector output high impedance inputs Low Peripheral Device Data These four tri state lines carry the in verted received data from BUS 3 0 when the transceiver is in the receive mode When in transmit data mode the data carried on these lines is passed inverted to BUS 3 0 When in dis abled mode these lines go open high impedance High 1 Vector Jumpers These inputs with internal pull down resist ors directly drive BUS 3 1 A low or open on the jumper pin causes an open condition on the corresponding BUS pin if XMIT H is low A high causes a one low to be transmitted on the BUS pin Note that BUS Y L is not controlled by any jumpr input Match Enable A low on this line enables the MATCH output A high forces MATCH low overriding the match circuit Address Match When BUS 3 1 matches with the state of JA 3 1 and MENB L is low this output is open otherwise it is low Address Jumpers A strap to ground on these inputs allows a match to occur with a one low on the corresponding BUS line an open allows a match with a zero high a strap to Vec dis connects the corresponding address bit from the comparison Controi Inputs
90. test RS 422 A or RS 423 A as follows RS 422 A RS 423 A W1 W2 out W1 W2 installed W3 W 6 installed W3 W6 out The connector is installed into J1 with the jumper side up Since the H3260 on board test connector does not test the cable it is recommended that the DPV11 be tested with a turn around connector at the modem end of the cable if possible 2 9 SEND DATA 3 gt RECEIVE DATA J1 H3259 TX CLOCK TCP RCV CLOCK RCP LOCAL CLK SQ TM PCSCR 5 SF RL 7 JJ 127 MUST BE RXCSR O 3 3 6 W3 7 FF REMOVED WHEN OE wa ar 237 TESTING A DPV11 DATA SET wio 791 TN 14 RXCSR 3 LL 7 4 LA LOCAL LOOP BACK 22 10 13 RXCSR 14 INCOMING 20 CALL 9 9 10 RSCSR 1 DTR 3 2 DATA TERMINAL RSCSR 13 CTS 13 CLEAR TO SEND RSCSR 2 RTS 2 gt 8B N REQUEST TO SEND m READY 1 RXCSR 12 3 RECEIVER READY 2 NEGATIVE INPUT TO DIFFERENTIAL RECEIVERS OMITTED FOR CLARITY MK 1336 Figure 2 3 RS 423 A with H3259 Test Connector 2 10 TEST MODE SIGN QUAL SF RL SEND DATA RX DATA SEND DATA RS422 TERM TIMING SEND TIMING RX TIMING TERM TIMING RS422 CLEAR TO SEND TO SEND RX RDY INCOMING CALL TERM RDY DATA MODE DATA MODE RET LOCAL LOOP SEND TIM RET RX TIM RET TERM TIM RET RS422 SEND DATA RET RX DATA RET W1 W3 WA 5013970A RS422 RS423 11
91. tion and buffering Output signals are provided to the USYNRT controller to indicate the state of the data paths the command fields or recognition of extended address fields These tasks must be performed by the USYNRT con troller The USYNRT is a 40 pin dual in line package DIP Figure B 1 is a terminal connection identi fication diagram Data port bits DP07 DP00 are dedicated to service four 8 bit wide registers Bits DP15 DP08 service either control information or status registers The PCSCR register is reserved See Figure B 2 Purchase Specification 2112517 0 0 provides a detailed description of the 5025 USYNRT TBEMTY TXACT TERR RDATRY RSTARY RXACT SYNC ADR COMP ADR SEL 2 BIDIRECTIONAL TRI STATE LINES ADR SEL 1 ADR SEL BYTE GP WR LSI SEL RESET NOTE PIN 32 5V POWER SUPPLY 10 AT 100mA B PIN O1 12V POWER SUPPLY 10 AT 100mA C PIN 9 GROUND MK 1415 Figure B 1 Terminal Connection Identification Diagram 2112517 0 0 Variation B 2 ee o To To E Es TE EA ABORT ERR OVER CHK ASSY BIT ACCOUNT REOM RSOM G EAN ETA REE RER A s susu s CS s TX DATA aw aw aw aw aw aw aw MK 1502 Figure B 2 5025 Internal Register Bit Map 2112517 0 0 Variation Sheet 1 of 2 B 3 TX RX S
92. to W6 Test mode DM DSR Not connected W10 to W9 Data mode return for RS 422 A RXCSR 9 Normal configuration is typically RS 423 A compatible Alternate option is typically RS 422 A compatible 2 1 Table 2 1 Configuration Sheet Cont W3 W11 Interface Selection Jumpers Cont Output Normal Alternate Signals Configuration Option Description SF RL W3 to W4 Select frequency RXCSR 0 WS to W3 Remote loopback Local W8 to W9 Not connected Local loopback Loopback Not connected W38 to W11 Local loopback alternate pin W12 W17 Receiver Termination Jumpers Normal Alternate Receiver Configuration Option Description Receive Data Not connected W12 to W13 Connects terminating resistor for RS 422 A compatibility Send Timing Not connected Wi4to 15 Receive Timing Not connected W16to W17 W18 W23 Clock Jumpers Normal Alternate Function Configuration Option Description NULL MODEM W20 to W18 Sets NULL CLK MODEM CLK CLK to 2 kHz Sets NULL MODEM CLK to 50 kHz W21 to W18 W19 to W21 W22 to W23 Clock Enable 19 to W21 W22 to W23 Always installed except for factory testing W24 W28 Data Set Change Jumpers Modem Signal Normal Alternate Name Configuration Option Description Data Mode DSR W26 to W24 Not connected Connects the DSCNG flip flop to the respective modem status signal for transition detection Clear to Send W26 to W25 Not connected
93. tor scheme or user requirements determine the vector address for the specific DPV11 module being installed and configure W40 through W46 accordingly Table 2 2 3 Basedon the LSI 11 bus floating address scheme or user requirements determine the device address range for the DPV11 module and configure W30 through W39 accordingly Table 2 3 Devices may be physically addressed starting at 160000 and continuing through 177716 however there may be some software restrictions The normal addressing conven tion is as shown in Table 2 3 2 3 OO gogoo WI2 34656 8 91011 TERMINAL 2 12 ES INTERFACE TIMING O13 TERMINATING SELECTION O14 RESISTOR JUMPERS O15 f JUMPERS FOR RS 422 A O17 19 21 22 GGOO W18 20 23 CLOCK JUMPERS 25 27 00960 24 26 28 DATA SET CHANGE JUMPERS W26 IS INPUT TO DSCNG FLIP FLOP SHIPPED SHIPPED ADDRESS VECTOR 160010 300 DOS 23436 38 40 42 44 46 30 3 00000 O O JUMPERS ARE 00000 DAISY CHAINED 31 33 35 37 39 41 43 45 1338 Figure 2 1 DPV11 Jumper Locations Table 2 2 Vector Address Selection DPV11 M8020 VECTOR ADDRESSING MSB LSB Be PPP PPP PEEP EPpy 0000 0 wes ME a 4 JUMPER NUMBER 43 I 1 I VECTOR X X X x x X x x x x X X X X x x X INDICATES A CONNECTION TO W46 W46 IS THE SOURCE JUMPER FOR THE VECTOR ADDRESS JUMPERS ARE DAISY CHAINED 1341 Table 2 3 Device Address Selection D
94. ubsequent message is lost until the data of the prior message has been released 3 9 Table 3 3 Receive Data and Status Register RDSR Bit Assignments Cont Description This bit is used only with bit oriented protocols and indicates that either an abort character or a go ahead character has been received This is determined by the Loop Mode bit PCSAR bit 13 If the Loop Mode bit is clear RABORT indicates reception Receiver Abort or Go Ahead RABORT 10 of an abort character 1f the Loop Mode bit is set RABORT indicates a go ahead character has been received The setting of RABORT causes Receiver Status Ready bit 10 of RXCSR to be set RABORT 15 reset when the RDSR is read or when Receiver En able bit 4 of RXCSR is reset The abort character is defined to be seven or more contiguous one bits appearing in the data stream Reception of this bit pat tern when Loop Mode is clear causes the receive section of the USYNRT to stop receiving and set RSTARY bit 10 of RXCSR The abort character indicates abnormal termination of the current message en consecutive one bits This character is recognized as a normal terminating control character when the Loop Mode bit is set If Loop Mode is cleared this character is interpreted as an abort character This bit is used only with bit oriented protocols and is asserted if Receiver Active bit 11 of RXCSR is set and a message is ter minated either normally or a
95. used to form OUTLB L and OUTHB L BDOUT L generates BRPLY L through the delay circuit In Word Used to gate read data from a selected register ont the data bus It is enabled by BSYNC L and strobed by BDIN L Out Low Byte Out High Byte Used to load write data into the lower higher or both bytes of a selected register It is en abled by BSYNC L and the decode of BWTBT L and latched BDALO L It is strobed by BDOUT Select Lines One of these four signals is true as a function of BDAL2 L and BDALI L if ENB H is asserted at the assert edge of BYSNC L They indicate that a word register has been selected for a data transaction These signals never become as serted except at the assertion of BSYN L then only if ENB H is asserted at that time and once asserted are not negated until BSYNC L is negated External Resistor Capacitor Node This node is provided to vary the delay between the BDIN L BDOUT L and VECTOR H inputs and BRPLY L output The external resistor should be tied to and the capacitor to ground As an output it is the logical inversion of BRPLY L C 5 Table 2 0 004 Pin Signal Descriptions Cont Description Enable This signal is latched at the asserted edge of BSY NC L and is used to enable the select outputs and the address term of BRPLY L Maximum current required from the V supply is 100 mA Figure C 3 is a simplified logic diagram of the DC005 IC Signal and

DPV 11 serial synchronous interface user guide

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