User's Guide micro-line® C44CPU
Contents
1. 4 Pin Configuration pin 1 pin 24 pin 32 connector AA connector A connector B ZZ qug 1777708 810 TRI enna EBEE ET 2000 connector D connector E connector EE pin 1 pin 32 pin connector AA conn A conn B conn C connector D connector E connector EE 1 DE D D00 O Z A00 O Z GND I HINT O C2D0 I O 2 AE D D01 O Z A01 O Z GND I HWR D C2D1 V0 3 LOCK 0 D02 VO Z A02 O Z GND I HRD I C2D2 V0 4 STATO 0 D03 O Z A03 O Z GND I HEN 1 C2D3 I O 5 STATI 0 D04 I O Z A04 O Z 45V D HAI I C2D4 V0 6 STAT2 0 D05 I O Z A05 O Z 45V D HAO I C2D5 V0 7 STAT3 0 D06 I O Z A06 O Z RESETIN I HDO I O C2D6 V O 8 R W 1 O Z D07 O Z A07 O Z i RESETOUT O HDI I O C2D7 V0 9 STRB_1 O Z D08 UO Z A08 0 2 RESETOUT O HD2 1 0 CREQ2 I O 10 RDY 1 D09 I O Z A09 O Z CS1 O HD3 I O CACK2 I O 11 PAGE 1 O Z DIO O Z A10 O Z ICS2 O HD4 I O CSTRB2 I O 12 CE 1 D D112. 0000000 0000000 ooo oo VETERE CELOS SEGETES AISAT ooo SSGSSSSSSSSSSSSSSSSSSSSSSSESSSSSS ooo noo00000 oa 00000000 Baa activa te wa tch dog SSSSSSS eee set solder bridge L9 T SSISSSS di Da noD 5 ao SSSSSSS oooo0ococOcOoOOcOcOOOOcOcOOOO0OcOcOQ 2 11 Memory Map 2 11 1 RAM The complete 32 bit wide organized RAM can be used for program and data storing This applies to the local as well astothe global R
3. connector D connector E connector EE G GTRRC N 5 NxTxT D V D DSDS power supply RS232 interface Now theC44CPU board can beconnected to the power supply The installed user program TOGGLE_LED has to be booted automatically and the red and yellow LEDs have to toggle alternately When executing the command DIRML the development PC displays the C44CPU board directory which contains the TOGGLE_LED user program The command DIRML can also choose the PC s requested COM port to be used The syntax is DIRML Cx x 1 or 2 used COM port If a XDS510 emulator ora compatible emulator is available for software development thereis no need for a RS232 connection to the development PC in order to start operating In this case the application software can be directly loaded from the emulator to the C44CPU board s RAM where it can be started described in the emulator manual In this case the FILE software is not loaded to the C44CPU board The RS232 interface is only required to activate the FILE software forresidently storing the application program in the flash EPROM user s guide micro line CAACPU page 5 2 Hardware 2 1 C44CPU Block Diag
4. page 0 page 1 page 2 page 3 page 4 page 5 page 6 page 7 J18 closed open closed open closed open closed open J17 closed closed open open closed closed open open J16 closed closed closed closed open open open open default state m pram TTT J16 nnmmmmm ool oxo Oxo oO on TITULI J17 Therunning application software can find the latest page configuration because a process is activated during the ORSYS firmware booting procedure which tests the hardware page configuration and enters anumber from 0 to 7 into the memory address 0x002FFFFF the highest address of the TMS320C44 processor s J18 o00000000000000000000000000060 Sees ri 00000000 00000000 n o oo ono00000 c3 0000000
5. OO66666660060600006666666666606666 OU pEreaeap o Eg OO o D oo o E B5 TETETSRRRTTTEEERETTITESRERTEEUNT H io o ke 2 o S B B SH BE gr DOOOooooo 8 8 H E E B TMS320C44 ROMEN 0 DDDDDDDDD g E set solder bridge J13 SSSSSSS ASSSSSSSSSSSSSSSSSISSSSSSSSSSSSS1 H g 2 2 B oo 00m Z 2 B o000 default State ROMEN 1 sssssss l COO 6 6000005000000 00000508 4 2 3 TMS320C44 RESETLOCO RESETLOCI1 Reset Vector Location The TMS320C44 processor has the two signals RESETLOCO and RESETLOCI to determine the program start addresses after reset see TMS320C4x user s guide pages 3 17 The value of these signals can be selected by solder bridges J14 and J15 B mimm TTT mmm TMS320C44 RESETLOCI 1 open solder bridge J15 T LLL TIITLIHLULLLLLITIOAT LLL LLL
6. In order to set up the C44CPU system drive the first instruction sequence of the loaded program has to be a dummy read access to read port 3 read write host port register address 0x8023C000 D addresses are only valid for global memory page 0 default state after delivery user s guide micro line CAACPU page 36 4 2 2 TMS320C44 ROMEN Rom Enable Solder bridge J13 can be closed to deactivate the TMS320C44 internal boot ROM see TMS320C4x user s guide pages 3 18
7. SSSSSss SSSSSSS SSLSESLESSSSSSSSSSSSSSSSSSTSSSSES SSLSCSSSSSSSSSSSSSSSSSSSSSSSSSSSS EAR EE oo 000 na 000 Ooo ooo SSSSSSS ooog SSSSSSS 0999999999099999 90909090090900900 internal RAM This RAM address should not be accessed by the application software user s guide micro line CA4CPU page 38 4 4 Application Examples 4 4 1 Connecting a Parallel Port 82C55 Device via an I O Port RESETOUT RESET CSn ICS PORT 0 RD 0 RD PORT 1 WR 0 WR AO Al AO Al PORT 2 DO D7 DO D7 C44CPU board 82C55 Anapplication exampleexplains the connecting of acustomary peripheral device to the C44CPU board with a82C55 p
8. user s guide micro line CAACPU page 10 2 12 C44CPU Memory Model Local Bus Ox7FFFFFFF 0x01000000 0x00320000 0x00308000 0x00300000 Ox002FFFFF 0x002FFC00 Ox002FF800 0x00100100 0x00100000 0x00001000 0x00000000 The local memory space is not affected by the global memory page configuration 20x00307E00 0x00307FFF is reserved on the 2 x 32K word RAM equipment 0x0031FE00 0x003 1 FFFF is reserved on the 2 x 128K word RAM equipment invalid memory space reserved external RAM space reserved CPU register reserved boot loader 128K words 32K words global memory RAM block 1 page RAM block 0 0x001000FO0 0x001000FF DMA coprocessor channel 5 0x001000E0 0x001000EF DMA coprocessor channel 4 0x001000D0 0x001000DF DMA coprocessor channel 3 0x001000CO0 0x001000CF DMA coprocessor channel 2 0x001000B0 0x001000BF DMA coprocessor channel 1 0x001000A0 0x001000AF DMA coprocessor channel 0 0x00100090 0x0010009F communication port 5 register 0x00100080 0x0010008F communication port 4 register 0x00100070 0x0010007F reserved 0x00100060 0x0010006F communication port 2 register 0x00100050 0x0010005F communication port 1l register 0x00100040 0x0010004F reserved 0x00100030 0x0010003F timer register 0x00100020 0x0010002F timer O register 0x00100010 0x0010001F analysis board block register
9. ODODUN ONO E N A AA A TMS320C44 RESETLOCO 1 open solder bridge J14 default state RESETLOCO 0 RESETLOCI 0 user s guide micro line C44CPU page 37 4 3 Setup of the Global Memory Pages 0 7 The C44CPU board has three solder bridges in order to set up the global memory pages 0 to7 There are eight combinations possible
10. In order to set up DSP link booting solder bridge J20 on the C44CPU board has to be open o000000000000000000000000000000 0000000 0000000 ooo oo VERSER RELES REGE STEELS TSRSTES ooo SSSSCSSASSSSSSSSSSSSSSSSSSCSSSSES ooo noo000000 oa 00000000 Bao activate DSP link booting open solder bridge J20 EAE oo iu SSSSSSS SSSSSSS Baja 5 ao SSSSSSS oooooocoooooOoO0O0O0OcOcoOO0O0OcOcQ
11. global memory page 6 global memory page 7 C44CPU Control Register 0x80228000 0x8022BFFF 0x80268000 0x8026BFFF 0x802A8000 0x802ABFFF 0x802E8000 0x802EBFFF 0x80328000 0x8032BFFF 0x80368000 0x8036BFFF 0x803A8000 0x803ABFFF 0x803E8000 0x803EBFFF global memory page 0 global memory page 1 global memory page 2 global memory page 3 global memory page 4 global memory page 5 global memory page 6 global memory page 7 Read Port 0 Set Reset Broadcast Interr Reg 0x80230000 0x80233FFF 0x80270000 0x80273FFF 0x802B0000 0x802B3FFF 0x802F0000 0x802F3FFF 0x80330000 0x80333FFF 0x80370000 0x80373FFF 0x803B0000 0x803B3FFF 0x803F0000 0x803F3FFF global memory page 0 global Memory Pa ge 1 global memory page 2 global memory page 3 global memory page 4 global memory page 5 global memory page 6 global memory page 7 Read Port 2 Read Host Port Rx Status Reg 0x80238000 0x8023BFFF 0x80278000 0x8027BFFF 0x802B8000 0x802BBFFF Ox802F8000 0x802FBFFF 0x80338000 0x8033BFFF 0x80378000 0x8037BFFF 0x803B8000 0x803BBFFF Ox803F8000 0x803FBFFF global memory page 0 global memory page 1 global memory page 2 global memory page 3 global memory page 4 global memory page 5 global memory page 6 global memory page 7 Wait State Control Register 2 0x80224000 0x80227FFF 0x80264000 0x80267FFF 0x802A4000 0x802A7FFF Ox802EA000 0x802E7FFF 0x803
12. 0x8024FFFF 0x8028C000 0x8028FFFF 0x802CC000 0x802CFFFF 0x8030C000 0x8030FFFF 0x8034C000 0x8034FFFF 0x8038C000 0x8038FFFF 0x803CC000 0x803CFFFF global memory page 0 global memory page 1 global memory page 2 global memory page 3 global memory page 4 global memory page 5 global memory page 6 global memory page 7 I O Port 5 CS5 0x80214000 0x80217FFF 0x80254000 0x80257FFF 0x80294000 0x80297FFF 0x802D4000 0x802D7FFF 0x80314000 0x80317FFF 0x80354000 0x80357FFF 0x80394000 0x80397FFF 0x803D4000 0x803D7FFF global memory page 0 global memory page 1 global memory page 2 global memory page 3 global memory page 4 global memory page 5 global memory page 6 global memory page 7 T O Port 7 CS7 0x8021C000 0x8021FFFF 0x8025C000 0x8025FFFF 0x8029C000 0x8029FFFF 0x802DCO000 0x802DFFFF 0x8031C000 0x803 1FFFF 0x8035C000 0x8035FFFF 0x8039C000 0x8039FFFF 0x803DC000 0x803DFFFF global memory page 0 global memory page 1 global memory page 2 global memory page 3 global memory page 4 global memory page 5 global memory page 6 global memory page 7 T O Port 2 CS2 0x80208000 0x8020BFFF 0x80248000 0x8024BFFF 0x80288000 0x8028BFFF 0x802C8000 0x802CBFFF 0x80308000 0x8030BFFF 0x80348000 0x8034BFFF 0x80388000 0x8038BFFF 0x803C8000 0x803CBFFF global memory page 0 global memory page 1 global memory page 2 glo
13. global memory pages 0 7 global RAM 32K word RAM equipment 0x80400000 0x80407FFF global memory page 0 0x80408000 0x8040FFFF global memory page 1 0x80410000 0x80417FFF global memory page 2 0x80418000 0x8041FFFF global memory page 3 0x80420000 0x80427FFF global memory page 4 0x80428000 0x8042FFFF global memory page 5 0x80430000 0x80437FFF global memory page 6 0x80438000 0x8043FFFF global memory page 7 global RAM 128K word R AM equipment 0x80400000 0x8041FFFF global memory page 0 0x80420000 0x8043FFFF global memory page 1 0x80440000 0x8045FFFF global memory page 2 0x80460000 0x8047FFFF global memory page 3 0x80480000 0x8049FFFF global memory page 4 0x804A0000 0x804BFFFF global memory page 5 0x804C0000 0x804DFFFF global memory page 6 0x804E0000 0x804FFFFF global memory page 7 default state global memory page 0 user s guide micro line CAACPU page 13 2 14 2 I O Port Addresses global memory pages 0 7 I O Port 1 CS1 0x80204000 0x80207FFF 0x80244000 0x80247FFF 0x80284000 0x80287FFF 0x802C4000 0x802C7FFF 0x80304000 0x80307FFF 0x80344000 0x80347FFF 0x80384000 0x80387FFF 0x803C4000 0x803C7FFF global memory page 0 global memory page 1 global memory page 2 global memory page 3 global memory page 4 global memory page 5 global memory page 6 global memory page 7 T O Port 3 CS3 0x8020C000 0x8020FFFF 0x8024CO000
14. HRD lo ANE p HDO 8 1 uia Host Read access HEN controlled HEN HRD HDO 8 FPGA device EPX780 10 EPX780 15 trd read cycle time min 23 ns min 34 ns tdv data valid time min 20 ns min 30 ns tr data release time min 20 ns min 30 ns user s guide micro line CA4CPU page 43 4 5 2 Important Notes to External Hardware Configurations Due to the C44CPU board s high clock frequencies and fast transients the following rules always have to be observed when connecting external hardware components to the C44CPU board Buslinesas wellas fastcontrol lines should not be longer than 15 cm otherwise the signals on the critical lines need to be measured during C44CPU board operation and ifnecessary impedances of the lines have to be adapted by serial resistors theexternal ground and power supply should be realized as copper planes The tracks between the power supply ground planes and peripheral devices have to be short thick and be decoupled by a support capacitor of about 100 nF to 5 V Incase of experimental bread boards all ground and 5V wires should beat least 1 5 mm thick The basic rule is the thicker the better For connections of noise sensitive AD or DA converters the analog and the digital ground configurations have to comply with the instructions of the converter data sheet 4 5 3 Signal Loads The following guidelines apply to all fast processor signals DO D31 A0 A
15. be considered for the 128K word RAM 92 TMS320C44 cache memory inactive program and data are in the external local and global RAM memory of the C44CPU board user s guide micro line CAACPU page 45 4 5 6 C44CPU Board Dimensions All dimensions are provided in mm 55 88 omm dmm m amaaan anann KARUA LLL E HAE HPV AA eo0o00999 H loooooo 2 54 2 54 2 54 user s guide micro line C44CPU page 46
16. control register should be set EC e C Wait State Control Register 2 D31 D1 DO x x x x x x x x x x x x xi x x x x x x x x xi x x x x x x x x notused 1 DO T O port 4 5 6 7 O wait states 1 wait state 4 wait states 7 wait states address 0x80224000 P only writable notreadable 7 waitstates after reset both STRBO SWW bits software wait mode of the TMS320C44 global memory interface control register should be set ocoU mdi eo Ec D addresses are only valid for global memory page 0 default state after delivery user s guide micro line C44CPU page 17 C44CPU Control Register D31 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO X X X X X xXx x x x x x x x x x x x x x X x not used Bit 0 1 DO D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 HDO HD8 host port port pins HDO HD3 are inputs host port transmit interrupt disabled host port receive interrupt disabled INTI 3 IIOF1 3 pins inputs PC FILE operations disabled red LED OFF board operation RS232 driver active disable broadcast interrupt yellow LED OFF HD0 HD8 port pin port pins HDO HD3 areoutputs host port transmitinterrupt enabled host port receive interrupt enabl
17. during read or write accesses to the I O address space 0x80204000 P to 0x80207FFF The signal is decoded out of the global bus address and becomes valid after a FPGA delay to the address output CS2 Chip Select output active low of I O port 2 CS2 is activated during read or write accesses to the I O address space 0x80208000 to 0x8020BFFF The signal is decoded out of the global bus address and becomes valid after a FPGA delay to the address output D addresses are only valid for global memory page 0 default state after delivery user s guide micro line C44CPU page 31 CS3 Chip Select output active low of I O port3 CS3 is activated during read or write accesses to the I O address space 0x8020C000 to0x8020FFFF P The signal is decoded out of the global bus address and becomes valid aftera FPGA delay to the address output CS4 Chip Select output active low of I O port4 CS4 is activated during read or write accesses to the I O address space 0x80210000 to0x80213FFF The signal is decoded out of the global bus address and becomes valid aftera FPGA delay to the address output CSS Chip Select output active low of I O port5 CS5 is activated during read or write accesses to the I O address space 0x802 14000 to0x80217FFF P The signal is decoded out of the global bus address and becomes valid aftera FPGA delay to the address output CS6 Chip Select output active low of I O port
18. 0x00100000 0x0010000F local and global port control for global memory page recognition 0 7 reserved for software requests entered by the boot system user s guide micro line CA4CPU page 11 2 13 C44CPU Memory Model Global Bus OxFFFFFFFF invalid memory space 0x81000000 free S S E memory space eS E STRB1 mi Bp SS og aos rhe oos 0x80800000 reserved 0x80420000 128K words external RAM space 0x80408000 32K words S Sa 0x80400000 gt ie E read port 3 read write Host Port Register a reserved read port 2 read Host Port Rx Status Register c 0x8023C000 Q 0x80738000 read port 1 read Host Port Tx Status Register 0x80230000 NN read port O set reset Broadcast Interrupt S 0x8022C000 UA Register S 0x80228000 SCC2691 Regist 0x80224000 NN arn ay gt 0x80220000 RS S Ox8021C000 NN C44CPU Control Register E CRM b NZ raise Control Register 2 z EOOD 2 waitstate Control Register 1 amp Ox80208000 7 RED amp 0x80204000 I O port 1 7 CS1 7 a reserved 0x80080000 512 kbytes flash EPROM 0x80020000 128 kbytes 0x80000000 D addresses are only valid for global memory page 0 default state after delivery the access to the flash EPROM space by external busmasters is blocked user s guide micro line CA4CPU page 12 2 14 Global Memory Page 0 7 Shared Memory The C
19. 23 R W n STRB n RD 0 WR O STATO 3 PAGE nandH1 signalloads are usually about 80 pF signalloads above 160 pF should be avoided All other C44CPU board signals should be below 200 pF 4 5 4 Ambient Temperature Storage temperature 25 85 C Opertion temperature 0 70 C user s guide micro line CA4CPU page 44 4 5 5 Power Consumption Theactual C44CPU board power consumption mostly depends on the number of external RAM accesses The power consumption can be reduced by activating the powerdown modes of the SCC269 1 device see SCC269 1 data sheet and of the RS232 driver C44CPU control register The TMS320C44 processor supports a powerdown mode which stops the processor The processor is reactivated by an external interrupt signal see TMS320C44 user s guide The powerdown mode is generally used for a power reduction during pauses between the sequence of data bursts TMS320C44 all memory accesses idle only internal external 32K words clock frequency mode memory accesses 0 WS RAM 40 MHz about 40 mA about 440 mA about 830 mA 50MHz about 45 mA about 470 mA about 860 mA 60MHz about 50 mA about 500 mA about 890 mA 80 MHz about 55 mA about 530 mA about 920 mA D processor clock 0 idle mode SCC2691 and RS232 drivers in the powerdown mode local RAM bank inactive d maximum system speed SCC2691 and RS232 driver active 2 an additional power consumption of about 15 has to
20. 24000 0x80327FFF 0x80364000 0x80367FFF 0x803A4000 0x803A7FFF Ox803EA4000 0x803E7FFF global memory page 0 global memory page 1 global memory page 2 global memory page 3 global memory page 4 global memory page 5 global memory page 6 global memory page 7 SCC2691 Register 0x8022C000 0x8022FFFF 0x8026C000 0x8026FFFF 0x802ACO00 0x802AFFFF 0x802ECO000 0x802EFFFF 0x8032C000 0x8032FFFF 0x8036C000 0x8036FFFF 0x803ACO00 0x803 AFFFF 0x803ECO000 0x803EFFFF global memory page 0 global memory page 1 global memory page 2 global memory page 3 global memory page 4 global memory page 5 global memory page 6 global memory page 7 Read Port 1 Read Host Port Tx Status Reg 0x80234000 0x80237FFF 0x80274000 0x80277FFF 0x802B4000 0x802B7FFF 0x802F4000 0x802F7FFF 0x80334000 0x80337 FFF 0x80374000 0x80377FFF 0x803B4000 0x803B7FFF 0x803F4000 0x803F7FFF global memory page 0 global memory page 1 global memory page 2 global memory page 3 global memory page 4 global memory page 5 global memory page 6 global memory page 7 Read Port 3 Read Write Host Port Register 0x8023C000 0x8023 FFF 0x8027C000 0x8027FFFF 0x802BC000 0x802BFFFF Ox802FC000 0x802FFFFF 0x8033C000 0x8033FFFF 0x8037C000 0x8037FFFF 0x803BC000 0x803BFFFF Ox803FC000 0x803FFFFF global memory page 0 global memory page 1 global memory page 2 global memory page 3 glo
21. 44CPU board has an integrated memory page mechanism which enables that up to eight boards can directly becoupled with each other via the global busin orderto implementa shared memory multiprocessor architecture A separate address space within the entire shared memory space is assigned to each C44CPU board when an increasing global memory page from0 to7 is determined Physically the memory is located on the processor boards global RAM Logically the memory is increasing in linear and can be addressed equally by each processor board The entire shared memory increases if more processor boards are connected Additionally to the shared memory function this bus coupling provides that the entire external I O space CSO 7 SCC2691 host port etc of each processor board can be addressed equally by any other processor board Furthermore additional external shared memory components can be coupled in orderto meet application specific requirements Viathe global bus each processor can trigger an interrupt signal or set a polling bit to any other processor as handshake between the processors The C44CPU board s data and address buses are directly connected with each other in order to implement this multiprocessor architecture Thecontrol lines DE AE LOCK STATO 3 R W STRB RDY PAGE and CE can each be connected with a suitable external bus arbiter unit ORS YS provides arespective bus arbiter unit as FPGA solution 2 14 1 RAM Addresses
22. 6 CS6 is activated during read or write accesses to the I O address space 0x80218000 to 0x8021BFFF The signal is decoded out of the global bus address and becomes valid aftera FPGA delay to the address output CS7 Chip Select output active low of I O port 7 CS7 is activated during read or write accesses to the I O address space0x8021C000 to0x8021FFFF The signal is decoded out of the global bus address and becomes valid aftera FPGA delay to the address output INTO IIOFO INT3 IIOF3 Interrupt input lines active low of the TMS320C44 processor All four interrupt inputs can optionally be either edge or level triggered An alternative to the interrupt function is to conifgurate the lines as universal input output ports The C44CPU board has one pullup resistor for each interrupt line INTO IIOFO must not be activated by an external device during aC44CPU board reset or while booting which means INTO IIOF0 must remain high IACK Interrupt Acknowledge output signal active low ofthe TMS320C44 processor The line can be pulsed within an interrupt routine by the software instruction IACK to acknowledge the interruptat the requested system RD_0 Global bus memory interface 0 read signal output active low The signal is always in low impedance state and cannot be switched into tristate RD _0 is in high state during internal read accesses of the TMS320C44 processor WR 0 Global bus memory interface 0 writ
23. AM A large number of memory allocations can be selected due to the dual bus architecture on a single processor system program code and data areas can be splitted and freely devided by the local and the global bus Itis often ofadvantage to exchange fast throughput data e g during DMA operations on abus system while on the second bus system the program code is simultanously operated without any speed losses When no large data blocks are transfered within a single processor system itis recommended to allocate the program code to thelocal RAM and datato the global RAM inorderto achievethe maximum speed user s guide micro line CAACPU page 9 Due to speed reasons only the generally used global variables should be allocated to the global bus for shared memory systems via the global RAM All other variables shoul be allocated to the local bus together with the program code The allocation of the program code and data to the local or the global RAMis exclusively performed by allocating the program code and data to the respective address space Address space 0x00000000 to Ox7FFFFFFF addresses the local RAM and address space 0x80000000 to OXFFFFFFFF the global RAM and I O The C44CPU board is available in two RAM versions 0 wait stateRAM 1 2x 32K words 64K words 256 kbytes 2 2x 128K words 256K words 1 Mbyte Besides thetwo external RAM banks the TMS320C44 processor has two additional internal RAM blocks with an altogether 2
24. D31 I O Z i z FLA CS I O user s guide micro line CA4CPU page 28 4 1 1 Pin Description Connector AA The connector AA is a specific C44CPU expansion connector which is not included in the micro line standard This connector transmits only specific TMS320C44 signals to the outside These signals are mostly global bus control and C4x communication port signals DE Global Data Bus Enable input active low The signal is low during normal C44CPU board operation For multiprocessor systems with external busmaster DE has to be deactivated during external accesses in order to switch the data bus drivers into tristate DE is provided with a pulldown resistor on the C44CPU board The pin remains open if there is ashared memory system with an uncoupled bus AE Global Address Bus Enable input active low The signal is low during normal C44CPU board operation Formultiprocessor systems with external busmaster AE has to be deactivated during external accesses in order to switch the address bus drivers into tristate AE is provided with a pulldown resistor on the C44CPU board The pin remains open if there is a shared memory system with an uncoupled bus LOCK Global Bus Locking signal output active low For multiprocessor systems LOCK can be activated during global memory accesses in orderto stop theexternal bus arbiter from passing on the global bus The pin remains open if there is no shared memory system on the g
25. K word 8 kbyte deep memory 2 11 2 Flash EPROM The flash EPROM is the system s boot memory It contains all user programs when the processor is in bootloader mode The flash EPROM should not be directly read or written from the user program it is directly handled by the boot program or the FILE system software The C44CPU board provides an integrated protection mechanism to ensure the data security of the flash EPROM and to avoid an accidental deletion of the user programs All programs necessary for booting download operations and FILE handling are residently stored in the flash EPROM The stored programs cannot be deleted The C44CPU board supports two flash EPROM versions 1 128 kbytes 2 512 kbytes 2 11 3 Program Cache The TMS320C44 processor has an integrated 128 word program cache memory to buffer instructions which were read from the external RAM When using the cache memory the processor speed improves and the processor achieves optimum results for its internal parallel resources The TMS320C44 cache memory is divided into four 32 word segments which are separately checked for any chache misses This means that after a failed cache access the maximum reconstruction of the cache contents is only one quarter of the cache while the other program words three quarters remain unchanged in the cache memory In order to activate the cache memory bit 1 1 CE Cache Enable of the TMS320C44 processor status register has to be set
26. O Z A11 O Z i ICS3 O HD5 I O CRDY2 VO 13 CE 0 D D12 VO Z A12 O Z ICS4 O HD6 I O CDIR2 0 14 NMI D D13 O Z A13 O Z i ICS5 O HD7 I O C4D0 V0 15 C1D0 O D14 O Z A14 O Z CS6 O HD8 I O C4D1 V0 16 CIDI O D15 O Z A15 O Z i ICS7 0 HOST_OUT_CLK O C4D2 I O 17 CID2 O D16 O Z A16 O Z INTO IIOFO VO HOST OUT OE O C4D3 I O 18 CID3 W O D17 VO Z AIT O Z INTI IIOFI VO HOST_IN_CLK O C4D4 I O 19 CID4 VO D18 O Z A18 O Z INT2 IIOF2 VO HOST IN OE O C4D5 I O 20 C1D5 O D19 l O Z A19 O Z INT3 IIOF3 VO C5D0 O C4D6 I O 21 CID6 VO D20 I O Z A20 O Z MACK O Z C5D1 I O C4D7 I O 22 CID7 VO D21 O Z A21 O Z RD 0 0 C5D2 V0 CREQ4 V O 23 CREQI VO D22 VO Z A22 O Z WR 0 O C5D3 I O ICACK4 1 0 24 ICACKI VO D23 O Z A23 O Z i R W 0 O Z C5D4 JO CSTRB4 I O 25 CSTRBI W O D24 I O Z STRB 0 O Z C5D5 I O ICRDY4 I O 26 CRDYI VO D25 I O Z 3 TXD 0 C5D6 I O CDIR4 0 27 CDIRI 0 D26 l O Z RTS 0 C5D7 I O CREQS I O 28 TDO_FPGA O D27 O Z i RXD D TCLKO I O Z ICACKS I O 29 TDI FPGA I D28 I O Z CTS D TCLKI I O Z CSTRBS I O 30 TCK FPGA D D29 I O Z RDY 0 1 CLK_3 68MHZ O CRDYS5 I O 31 TMS FPGA D D30 I O Z HI 0 CDIRS 0 32 VPP FPGA I
27. The following lines belong to the host port signals HDO HD8 data HAO HA1 addresses HEN host port enable chip select HRD read HWR write and HINT interrupt If the host port is not needed for a specific application it can alternatively be configurated to nine digital outputs or to four digital inputs and five digital outputs by respective software initialization 2 5 TO Input Output Port 1 7 The altogether seven I O input output ports enable the simultaneous and direct connection of up to seven different customary peripheral boards e g parallel port devices serial port devices clock boards AD converters display boards etc without any additional external components Timing differences between the fast signal processor and the normally slower peripheral boards can be offset by the two integrated programmable wait state generators Wait state generator controls the bus timing of the I O ports 1 to 3 and wait state generator 2 controls the bus timing of the I O ports 4 to 7 The number of wait states can be programmed via the wait state control registers land 2 After a reset the default value is 7 wait states each The I O ports consist of the signal lines DO D31 data AO A23 addresses CS 1 CS7 chip select RD read WR_O write R W 0 read write STRB 0 Strobe INTO IIOFO INT3 IIOF3 interrupt IACK interrupt acknowledge RESETOUT reset active low and RESETOUT reset acti
28. The host address 0x01 is reserved and should not be addressed Host Data Register HD8 HDO read write host dataregister write data to C44CPU DO D8 read data from C44CPU DO D8 host address 0x00 readable read data from C44CPU and writable transmit data to C44CPU only usable if C44CPU control register bit DO 20 Host Read Transmit Status Register Host Write Control Register x not used HD8 HDO HD8 HDO x x xxx x x x x x x x x x x read write hostread transmit status register HDO host write control register HD1 HDO transmit buffer full 0 disable all host interrupts HINT 0 0 transmit buffer empty 1 enablereceive interrupt HINT 0 enable transmit interrupt HINT 1 0 enable both interrupts HINT 1 1 host address 0x02 all interrupts are disabled after reset only usable if C44CPU control register bit DO 0 Host Read Receive Status Register HD8 HDO x x x x x x x x x not used read hostread receive status register HDO receive buffer full 0 receive bufferempty 1 host address 0x03 only usable if C44CPU control register bit DO 0 user s guide micro line C44CPU page 22 2 17 Interrupts Additionally to the processor s internal interrupt sources the C44CPU board provides four external inte
29. User s Guide micro line C44CPU Revision 03 96 Orsys Orth System GmbH Am Stadtgraben 1 88677 Markdorf Germany phone 49 0 7544 9561 0 fax 9561 29 e mail sales orsys de web site http www orsys de 1 1 1 2 2 1 2 2 2 3 2 4 2 9 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 2 19 2 20 Index General Introduction Quick Start Hardware C44CPU Block Diagram Dual Bus Architecture RS232 Interface Parallel Host Port I O Input Output Port 1 7 DSP Links DMA Coprocessor Timer 0 Timer 1 Auxiliary Timer Reset Generator Watchdog Memory Map 2 11 1 RAM 2 11 2 Flash EPROM 2 11 3 Program Cache C44CPU Memory Model Local Bus C44CPU Memory Model Global Bus global memory page 0 7 Shared Memory 2 14 1 RAM Addresses global memory pages 0 7 2 14 2 I O Port Addresses global memory pages 0 7 2 14 3 External Register Addresses global memory pages 0 7 I O Register Host Port Register Host Side Interrupts Port Pins LEDs Clock Frequency Processor Performance user s guide micro line CA4CPU A O ODO wJoJOccococccoco 1 1o00 0 0 m 16 22 23 23 24 24 page 2 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 3 10 3 11 3 12 3 13 3 14 4 1 4 2 4 3 4 4 4 5 Software Summary DIR44 DEL44 REN44 FORMAT44 CHKDSK44 RUN44 FLOAD44 SLOAD44 C Compiler and Assembler C Compiler and ADA Compiler Emulator Simu
30. ace Afterentering acommand the active user program on the CA4CPU board is interrupted the FILE system software is loaded the command is executed and the active user program is restarted Inorderto selecttherequested COM interface ofthe development PC the command can be entered with aparameter following e g DIRML Cn n 1 or 2 The COM interface provided by the development PC will be stored and automatically used for all following commands The commands DIRML H or DIRML start the help function This applies to all FILE commands 32 DIRML The command DIRML lists the actual C44CPU board directory on the screen of the development PC including name date time and FILE size of the maximum 63 FILES The autobooting user program and the remaining flash EPROM are additionally displayed 3 3 DELML The command Delete DELML lt Name gt deletes the entered FILE on the C44CPU board The afterwards free memory space on the C44CPU board s flash EPROM becomes automatically available for other FILES 3 4 RENML The command Rename RENML lt OldName NewName gt replaces the name OldName of a FILE by anew name NewName on the C44CPU board The maximum length of a FILE nameis 15 characters 35 FORMATML Thecommand FORMATML executes an unirrevocable formating of the flash EPROM on the C44CPU board All user programs are deleted 36 CHKDSKML Thecommand Checkdisk CHKDSKML executes a verification of every single FILE on the CA4CPU b
31. arallel port device For the 82C55 the active high RESETOUT signal of the C44CPU board has to be used because the 82C55 reset input signal is also active high TheC44CPU board interrupt inputs INTO IIOFO to INT3 IIOF3 are not used for the 82C55 because the 82C55 does not have any interrupt outputs 4 4 2 Connecting the C44CPU board as Coprocessor toa MOTOROLA 68000 System via a Parallel Host Port 1 RESET RESETIN IPLn HINT DO D8 HDO HD8 R W e 2l HRD LDS gt l HWR AO An e HAO HAL DTACK HEN address I decoder 68000 host processor C44CPU board The above block diagram is an example for connecting the C44CPU board toa MOTOROLA 68000 system The address decoder selects the I O base of the four C44CPU host port registers in the 68000 system The signal pairs R W Read Write and LDS Lower Data Strobe are connected to the signals HRD host read and HWR host write via two OR logic gates No further hardware components are necessary optional user s guide micro line CAACPU page 39 4 4 3 Connecting the C44CPU Board as Coprocessor to an INTEL 80C51 System via the parallel Host Port 1 1 o 1 e RESET RESETIN INTn HINT DO D7 HDO HD7 RD HRD WR HWR AO An HAO HAI PSEN T HEN 80C51 host pr
32. bal memory page 3 global memory page 4 global memory page 5 global memory page 6 global memory page 7 T O Port 4 CS4 0x80210000 0x80213FFF 0x80250000 0x80253FFF 0x80290000 0x80293FFF 0x802D0000 0x802D3FFF 0x80310000 0x803 13FFF 0x80350000 0x80353FFF 0x80390000 0x80393FFF 0x803D0000 0x803D3FFF global memory page 0 global memory page 1 global memory page 2 global memory page 3 global memory page 4 global memory page 5 global memory page 6 global memory page 7 I O Port 6 CS6 0x80218000 0x8021BFFF 0x80258000 0x8025BFFF 0x80298000 0x8029BFFF 0x802D8000 0x802DBFFF 0x80318000 0x8031BFFF 0x80358000 0x8035BFFF 0x80398000 0x8039BFFF 0x803D8000 0x803DBRFF global memory page 0 global memory page 1 global memory page 2 global memory page 3 global memory page 4 global memory page 5 global memory page 6 global memory page 7 default state global memory page 0 user s guide micro line C44CPU page 14 2 14 3 External Register Addresses global memory pages 0 7 Wait State Control Register 1 0x80220000 0x80223 FFF 0x80260000 0x80263FFF 0x802A0000 0x802A3FFF 0x802B0000 0x802E3FFF 0x80320000 0x80323FFF 0x80360000 0x80363FFF 0x803A0000 0x803A3FFF 0x803B0000 0x803E3FFF global memory page 0 global memory page 1 global memory page 2 global memory page 3 global memory page 4 global memory page 5
33. bal memory page 4 global memory page 5 global memory page 6 global memory page 7 default state global memory page 0 user s guide micro line CA4CPU page 15 2 15 TO Register The I O space partly operates with 7 firmly adjusted wait states This concerns the following registers waitstate control register 1 wait state control register 2 C44CPU control register SCC2691 register Thefollowing host port registers are firmly adjusted to 0 wait states read portO set reset broadcast interrupt register read port1 read host port Tx status register read port2 read host port Rx status register read port3 read write host port register The wait states of the following I O channels can be adjusted with the help of wait state control register 1 T O port 1 CS1 I O port 2 CS2 T O port 3 CS3 The wait states of following I O channels can be adjusted with the help of wait state control register 2 I O port 4 CS4 I O port 5 CS5 I O port 6 CS6 I O port 7 CS7 The three STRBO WTCNT bits waitcount in the global memory interface control register of the TMS320C44 processor must not be programmed to a larger number of wait states as there arein the wait state control registers and 2 The two STRBO SWW bits software wait mode of the global memory interface control register should be left unchanged to binary 1 1 For global RAM shared memory systems the busmaster
34. development PC in order to perform the loading process The application program is first loaded and then started The application program loaded by SLOADAA is deleted if aC44CPU board restart or a reset occurs 3 10 C Compiler and Assembler The standard software languages offered by Texas Instruments TI are available in two versions The basic version consists of an assembler anda linker The basic version is sufficient to implement C44CPU software projects in assembler programming language The TI order number for the basic version is TMDS3243850 02 PC version The extended version consists of a ANSI C compiler assembler and linker With the extended version C44CPU software projects can be implemented in the C and assembler programming languages Single assembler lines can also be inlined into C software projects or complete assembler algorithms can be integrated into C software projects The TI order number for the extended version is TMDS3243855 02 PC version ORSYS provides both software packages 3 11 C Compiler and ADA Compiler Compilers for the program languages C and ADA are additionally available to the above listed software languages user s guide micro line CAACPU page 26 3 12 Emulator Tl as wellas other providers offer several emulator systems for comfortable software debugging Emulators usually consist of a PC interface card whichis connected to the C44CPU board emulator pin connector by an emulator cabe
35. e 2 18 Port Pins Some pins of unused interfaces can freely be used as programmable digital input output ports Timer 0 and Timer 1 Lines The lines TCLKO and TCLK1 ofthe TMS320C44 processor can be used as digital input output ports if the external timer function is not used Parallel Host Port The lines HDO HD8 can beused as a digital output port by respective initialization of the C44CPU control register ifthe host portisnotused The lines HDO to HD4 can alternatively be switched to digital input output ports by software user s guide micro line CAACPU page 23 Lines INTO IIOFO INT1 NOF 1 INT2 IIOF2 and INT3 IIOF3 The lines INTO IIOFO INT1 IIOFI INT2 IIOF2 and INT3 IIOF3 can be used as digital input ports or as digital output ports In the processor s IF Interrupt Flag register the line INTO IIOFO can be configured separately from port function input or output to interrupt function In the C44CPU control register the lines INT1 IIOF1 INT2 IIOF2 and INT3 IIOF3 can only be switched commonly to either inputs or outputs A mixed function of these lines is only possible for interrupt inputs and port pin inputs and not for outputs When the lines INT 1 IIOF1 INT2 IIOF2 and INT3 IIOF3 of the C44CPU control register are switched to outputs the signal INTO IIOFO can only be used as interrupt input An initialized combination where the lines INTI IIOF1 INT2 IIOF2 and INT3 IIOF3 are switched to inp
36. e the power supply has to beconnected tothe pins D1 D2 D3 D4 ground and D5 D6 5V Important The voltage supply must not exceed 5 5 V and must not be reversed otherwise the C44CPU board could be permanently damaged The next step is toestablisha RS232 connection between the development PC und the C44CPU board The according pins on the C44CPU board are D28 RxD D26 TxD D27 RTS D29 CTS andD1 ground The pin configuration on the 9 pole RS232 plug is 2 RxD 3 TxD 7 RTS 8 CTS and 5 ground The RS232 cable between the C44CPU board and the PC has to be a null modem cable TxD PC gt RxD C44CPU and vica versa The RTS and CTS lines have to be crossed respectively pin 1 pin 24 pin 32 connector AA connector A connector B Ia mimm ETIANI TAA mmm N LU TLUUL da loooooo eseeeeo mnm HAE A AA A
37. e connector EE is a specific C44CPU expansion connector which is not included in the micro line standard The connector EE provides only specific TMS320C44 signals to the outside These signals are mostly global bus control signals and C4x communication port signals C2D0 C2D7 Communication port 2 Data Bus bidirectional CREQ2 Communication port 2 token Request bidirectional CACK2 Communication port 2 token Request Acknowledge bidirectional CSTRB2 Communication port 2 Data Strobe bidirectional CRDY2 Communication port 2 Data Ready bidirectional CDIR2 Communication port 2 Direction output C4D0 C4D7 Communication port 4 Data Bus bidirectional CREQ4 Communication port 4 token Request bidirectional CACK4 Communication port 4 token Request Acknowledge bidirectional CSTRB4 Communication port 4 Data Strobe bidirectional CRDY4 Communication port 4 Data Ready bidirectional CDIR4 Communication port 4 Direction output FLA_CS Special pin for ORS YS internal board configurations This pin is notrequired for any applications and must remain open user s guide micro line CAACPU page 35 4 2 Alternative Processor and Boot Modes 4 2 1 Booting viaa DSP Link Instead of the booting via the preset automatic FILE system user program the C44CPU board can also be booted via one of the four DSP links Further information is provided in the TMS320C4x user s guide
38. e signal output active low The signal is always in low impedance state and cannot be switched into tristate WR_0 is in high state during internal write accesses of the TMS320C44 processor D addresses are only valid for global memory page 0 default state after delivery user s guide micro line C44CPU page 32 R W_0 Global bus memory interface 0 Read Write Output signal of the TMS320C44 processor An external read cycle occurs if the signal is high and an external write cycle occurs if the signal is low STRB_0 Global bus memory interface 0 Strobe output signal active low of the TMS320C44 processor It signals an external read or write access TXD Transmit Data output of the RS232 interface The required 10V line drivers are integrated on the C44CPU board RTS Request To Send output of the RS232 interface The required 10V line drivers are integrated on the C44CPU board RXD Receive Data input of the RS232 interface The required 10V linedrivers are integrated on the C44CPU board CTS Clear To Send input of the RS232 interface The required 10V line drivers are integrated on the C44CPU board RDY 0 Global bus memory interface0 bus Ready input signal active low Thesignalcan beused toinsert additional T O wait states on external accesses to the TMS320C44 processor When activating the signal during an external memory access all lines of the bus are statically stored until the RD Y_0 signal is i
39. ed INTI 3 IIOFI 3 pins outputs PC FILE operations possible red LED ON hardware reset RS232 drivershutdown enable broadcast interrupt yellow LED ON address 0x80228000 P only writable not readable default state after reset default state when using signals INT1 IIOF1 INT2 IIOF2 and INT3 IIOF3 as interrupt pins The function of signal pins INTO IIOFOcan only be initialized in the HF interrupt flag register of the TMS320C44 processor see TMS320CAx user s guide pages 3 12 whenPC FILE operation is disabled all FILE commands e g DIRML after entering themon the development PC can only be executed by a manually triggered reset signal on the C44CPU board D addresses are only valid for global memory page 0 default state after delivery user s guide micro line C44CPU page 18 SCC2691Register see data sheet SCC269 1 in the appendix MR 1 Mode Register 1 and MR2 Mode Register 2 address 0x8022C000 both registers are writable and readable SR Status Register and CSR Clock Select Register address 0x8022C001 SR readable CSR writable CR Command Register and Test Register 1 address 0x8022C002 P test register 1 readable CR writable RHR Receive Holding Register and THR Transmit Holding Register address 0x8022C003 RHR readable THR writable ACR Auxiliary Control Register and Test Register 2 address 0x8022C004 testregis
40. ftware can also be tested by a TI simulator The simulator offers the same debugging techniques as the emulator and provides the same user interface The difference in debugging between the emulator and the simulator 1s that the emulator actually performs the software on the C44CPU hardware and the simulator merely performs a target processor simultation on the PC The Tl order number for the simulator package is TMDS324585 1 02 PC version and can be obtained from ORSYS 3 14 Real Time Operating Systems For larger software projects the real time operation systems SPOX from SPECTRON and VIRTUOSO from EONIC SYSTEMS can be used for the C44CPU board They are real time multitasking operation systems with excellentresults for Digital Signal Processors Additionally to the operation system core there are various libraries with mathematic functions or special DSP algorithms available which provide protocol communication with other host systems e g MS DOS Windows LynxOS OS 9 SunOS and VxWorks user s guide micro line CA4CPU page 27 Appendix
41. h transition This signal can be used to trigger an external latch device in transmit direction for expansions of the host port interface HOST_OUT_OE Host Port Out Output Enable signal output active low This signal can beused to enable the output drivers of an external latch device in transmit direction for expansions of the host port interface HOST_IN_CLK Host Port In Clock signal output active low to high transition This signal can be used to trigger an external latch device in receive direction for expansions of the host port interface HOST_IN_OE Host Port In Output Enable signal output active low This signal can be used to enable the output drivers of an external latch device in receive direction for expansions of the host port interface TCLKO TCLK1 Timer Clock pins of the TMS320C44 processor The lines can either be used as outputs to generate external clock signals via the internal timer or they can be switched to inputs in order to count external events or to supply the timers with external clocks As an alternative they can be configurated as universal input and output port pins CLK_3 68MHz 3 6864 MHz Clock output signal of the SCC2691 board This clock is stopped when the SCC2691 board is switched to powerdown mode H1 Bus Clock output signal ofthe TMS320C44 processor The frequency is half the frequency of the C44CPU board s oscillator user s guide micro line CAACPU page 34 Connector EE Th
42. imum development risk In order to operate the C44CPU board developers don t need to have any knowledge about the processor memory map the CPU mode or booting procedures Developers always have the option to operate the processor in various modes or touse their own boot software Basically allnecessary TMS320C44 signals are connected to the pins of the C44CPU board Various solder bridges on the C44CPU board enable all processor modes This user s guide covers all C44CPU board functionalities Details of the TMS320C44 signal processor can be found in the Texas Instruments TMS320C44 user s guide with reference to the TMS320C4x user s guide 1 2 Quick Start Prior to operating the following FILE software has to be copied to the development PC DIR44 EXE DIR44 SET DEL44 EXE DEL44 SET REN44 EXE REN44 SET FORMAT44 EXE FORMAT44 SET CHKDSK44 EXE CHKDSK44 SET RUN44 EXE RUN44 SET FLOAD44 EXE FLOADAA SET SLOAD44 EXE and SLOAD44 SET The FILES can either be copied to a directory known to the system e g copy b c K NOWN_PATH or anew directory can be established by the md MICROLIN make directory command Now the FILES can be copied cd MICROLIN copy b In order to make the program accessible from any directory the command line PATH in the system FILE AUTOEXEC BAT has to be extended by the new directory user s guide micro line C44CPU page 4 Prior to starting the C44CPU board has to be supplied with 5V In this cas
43. l to activate the C44CPU board s on chip emulator Emulators enable symbolic debugging with the follwing important debugging functions breakpoints single step display of register contents as well as variable and memory contents simultanous debugging of C and assembler code etc A windows oriented user interface facilitates the emulator handling ORSYS provides the TI emulator package XDS510 mm aT hii nnn emulator port TU LEU TERETE TTT E TERETE ETT HAIR LN ON A N AA A o00090999 H loooooo 3 13 Simulator As an alternative to the emulator the developed so
44. lator Real Time Operation Systems Appendix Pin Configuration 4 1 1 Pin Description Alternative Processor and Boot Modes 4 2 1 Booting viaa DSP Link 4 2 2 TMS320C44 ROMEN Rom Enable 4 2 3 TMS320C44 RESETLOCO RESETLOC1 Reset Vector Location Setup of the Global Memory Pages 0 7 Application Examples 4 4 1 Connecting a Parallel Port 82C55 Device via an I O Port 4 4 2 Connecting the C44CPU Board as Coprocessor toa MOTOROLA 68000 System via the Parallel Host Port 4 4 3 Connecting the C44CPU Board as Coprocessor to an INTEL 80C51 System viathe Parallel Host Port 4 4 4 Setup ofa DSP Link Coupled C44CPU Multiprocessor System 4 4 5 Extension of the Parallel Host Port to 32 Bits Further Remarks 4 5 1 Host PortTiming 4 5 2 Important Notes to external Hardware Configurations 4 5 3 Signal Loads 4 5 4 Ambient Temperature 4 5 5 Power Consumption 4 5 6 C44CPU Board Dimensions 4 5 7 SCC2691 Data Sheets user s guide micro line CA4CPU 25 25 25 25 25 25 26 26 26 26 26 27 27 27 28 29 36 36 37 37 38 39 39 39 40 40 41 42 42 44 44 44 45 46 page 3 1 General 1 1 Introduction The C44CPU board is a high performance embedded system from the ORSYS micro line xxCPU product family of modern Digital Signal Processor DSP boards The C44CPU operates with a Texas Instruments 32 bit floating point TMS320C44 signal processor The TMS320C44 signal processor provides an extraordinar
45. lobal bus STATO STAT3 These four output signals encode themomentary bus state of the TMC320C44 processor see TMS320C4x user s guide pages 7 5 The pin remains open if there is no shared memory system on the global bus R W_1 Global bus memory interface 1 Read Write output signal of the TMS320C44 processor In high state it signals an external read cycle and in the low state an external write cycle The signal is only required if an external global bus memory expansion is implemented via memory interface 1 The pin remains open during normal operation R W 1 is provided with a pullup resistor on the C44CPU board STRB_1 Global bus memory interface 1 Strobe output signal active low of the TMS320C3 1 processor It signals aglobal bus read or write access The signal is only required if an external global bus memory expansion is implemented via memory interface 1 The pin remains open during normal operation STRB 1 is provided with a pullup resistor on the C44CPU board RDY 1 Global bus memory interface 1 Ready input signal active low of the TMS320C44 processor For an additional memory interface 1 memory expansion RDY 1 can be used to insert additional wait states on external processor accesses by external hardware RDY 1 is provided with a pulldown resistor on the C44CPU board The pin remains open during normal operation user s guide micro line CAACPU page 29 PAGE 1 Global bus memory interface 1 page output sig
46. me The extension can be implemented with an external device together with the C44CPU control signals HOST_OUT_CLK HOST_OUT_OE HOST_IN_CLK and HOST_IN_OE The external board is a bidirectional 32 bit latch buffer SN74ABT32374 from Texas Instruments including four bidirectional74374 latch buffers A 17 bit ora 25 bit extension is possible when correspondingly smaller latches are used SN74ABT32374 n OEAB nLEAB nLEBA n OEBA nAl nA8 nBI nB8 D9 D31 RESET INTn DO D8 RD AO An host processor address decoder D9 D31 HOST OUT CLK RESETIN HINT HOST OUT OE HDO HD8 ARD HWR HOST IN CLK HAO HAI TEN HOST_IN_OE C44CPU board user s guide micro line C44CPU 4 5 FurtherRemarks 4 5 Host PortTiming Thefollowing timing parameters are important when connecting an external processor to the C44CPU host port Host Write access HWR controlled HEN HWR lo pu m ta HDO 8 M uia Host Write access HEN controlled HEN HWR HDO 8 FPGA device EPX780 10 EPX780 15 twr writecycletime min 16ns min 21 ns ts data setup time min 4ns min 6ns td data hold time min 6ns min 9ns user s guide micro line CA4CPU page 42 Host Read access HRD controlled HEN trd
47. nactive again The pin remains open if the hardware does not produce any external wait states The required pulldown resistor is integrated on the C44CPU board Connector E HINT Host Port Interrupt output signal active low This signal can be used as interrupt input signal fora host processor HWR Host Write input signal active low The signal can be connected with the WR output signal of a host processor The pin remains open if no host processor is connected HRD Host Read input signal active low The signal can be connected with the RD output signal of a host processor The pin remains open if no host processor is connected user s guide micro line CAACPU page 33 HEN Host Enable input signal active low The signal can be connected with the chip select output signal decoded address space of ahost processor The C44CPU board has an integrated pullup resistor The pin remains open if no host processor is connected HAO HA1 Host Address input signals The signals can be connected with the address signals AO and A1 of a host processor HD0 HD8 Host Data input output signals In the host port mode the signals can be connected with data ports DO D8 of ahost processor In the port pin mode they are used as programmable digital I O input output pins After reset and configuring the port pins to outputs all signals are set to 1 HOST_OUT_CLK Host Port Out clock signal output active low to hig
48. nal active high of the TMS320C44 processor For a memory interface DRAM expansion the signal can beusedto transfer anew page address to the memory components by external hardware PAGE 1 is provided with a pulldown resistor on the C44CPU board The pin remains open during normal operations CE_1 Global bus memory interface 1 Control Enable input active low The signalis low duringnormal CAACPU board operation For multiprocessor systems with an external busmaster CE_1 has to be deactivated during external accesses By deactivating CE_1 the global bus control signals STRB_1 PAGE 1 and R W_1 areswitched into tristate CE_1 is provided with a pulldown resistor on the C44CPU board The pin remains open if there is no shared memory system on the global bus CE_0 Global bus memory interface 0 Control Enable input active low The signal is low duringnormal C44CPU board operation For multiprocessor systems with an external busmaster CE_0 has to be deactivated during external accesses By deactivating CE_0 the global bus control signals STRB_0 PAGE_O and R W_O are switched into tristate CE_0 is provided with a pull down resistor on the C44CPU board The pin remains open if there is no shared memory system on the global bus NMI Non Maskable Interrupt input negative edge triggered The signal can be used toconnect high prioritised non maskable interrupt signals to the TMS320C44 processor NMIis provided with a pullup resist
49. nd the driver have to be short and thick 2 7 DMA Coprocessor The TMS320C44 processor integrated DMA coprocessor with its six separate DMA channels enables data transfer rates of up to hundreds of Mbytes s The DMA coprocessor can perform memory to memory transfers transfers from I O device to memory and vica versa transfers between the communication link ports and memory and transfers of single values to a block of memory Prior to operating the DMA coprocessor please refer to the initialization information provided in the Texas Instruments TMS320C4x user s guide chapt 9 1 to 9 44 2 8 Timer0O Timer 1 The TMS320C44 processor has two programmable timers which can universally be used to generate application specific clocks and system times Besides the generation of periodical interrupts the two signal lines TCLKO and TCLK I can deliver the output signal of the respective timer The two signal lines TCLKO and TCLK1 can furthermore be used as timer clock inputs to count external events For detailed information please refer to the Texas Instruments TMS320C4x user s guide chapter 9 45 to 9 53 2 9 Auxiliary Timer The SCC2691 peripheral device has an additional timer with a trigger function for periodical system interrupts The SCC2691 is also used as serial interface The FILE handling ofthe external development PC viathe SCC2691 is not impaired by the timer function and does not have to be considered when the timer is activa
50. oard s flash EPROM The result of the verification is the number of available FILES as well as the complete memory and the still free flash EPROM displayed on the development PC screen user s guide micro line CAACPU page 25 3 7 RUNML The command RUNML Names sets the status of the provided user program to autobooting and starts iton the C44CPU board The program is automatically booted after every C44CPU board restart or reset 3 8 FLOAD44 Thecommand Flash Load FLOAD44 is adownload program which loads a linker produced application program tothe C44CPU board after the conversion into the extended tektronix format with the command C44CPU control register HEX30 lt Name gt via the RS232 interface The application programis residently stored on the C44CPU board as FILE including program name date time and program size After the loading procedure the program automatically has the status booting program andis started The program is booted automatically after every C44CPU board restart or reset The command FLOAD44 lt Name gt has to be entered on the development PC in order to perform the loading process 3 9 SLOAD44 The command Speed Load SLOAD44 is adownload program which temporary loads a linker produced application program to the RAM ofthe C44CPU board after the conversion into the extended tektronix format with the command HEX30 lt Name gt via the RS232 interface The command SLOAD44 Name has to be entered on the
51. ocessor C44CPU board address decoder In order to connect a C44CPU board to an INTEL 80C51 system the I O base of the C44CPU board has to be decoded via an address decoder within the 80C51 system to generate the HEN signal The use of the PSEN signal Program Strobe Enable of the 80C51 is optional The C44CPU board has an independent reset generator therefore the connection of the inverted RESET signal to the 80C51 system is not mandatorily required 4 4 4 Setup ofa DSP Link Coupled C44CPU Multiprocessor System CREQn CREQm CACKn CACKm CSTRBn CSTRBm CRDYn CRDYm CnDO 7 CmDO 7 C44CPU board 1 C44CPU board 2 The easiest way to set upa DSP link coupled multiprocessor system is to connect the signal ports of the link ports see TMS320C4x user s guide pages 8 5 There is no need to use CDIRn ports for solutions without external line drivers Important Without external line drivers the ground connections between the processor boards must be short and thick For multiprocessor solutions the four DSP links of each processor can be connected with the links of any other processor P optional eas user s guide micro line C44CPU page 40 4 4 5 Extension of the Parallel Host Port to 32 Bits The extension of the parallel host port to 32 bits enables faster data transfers via the host port because with each transmission cycle four bytes can be transfered at the same ti
52. or on the C44CPU board The pin remains open during normal operations C1D0 C1D7 Communication port 1 Data bus bidirectional CREQI Communication port 1 Token Request bidirectional CACK1 Communication port 1 Token Request Acknowledge bidirectional CSTRBI Communication port Data Strobe bidirectional CRDY1 Communication port 1 Data Ready bidirectional CDIRI Communication port Direction output TDO FPGA TDI FPGA TCK FPGA TMS FPGA VPP FPGA JTAG IEEE 1149 1 interface to program the FPGA component user s guide micro line CAACPU page 30 Connector A D00 D31 Bidirectional global bus data lines of the TMS320C44 processor Connector B A00 A23 global bus address lines of the TMS320C44 processor Connector C Not provided on the C44CPU board Connector D GND Power supply ground 5V Power supply 5V The board asserts a reset signal for voltages below 4 65V The valid maximum voltageis 5 5V RESETIN Reset Input line active low for an external reset button The signal does not have to be debounced The required pullup resistor is integrated on the C44CPU board RESETOUT Reset Output line active low no open collector for external peripheral devices The signal is activated with every C44CPU board reset RESETOUT Inverted RESETOUT output signal active high no open collector CS1 Chip Select output active low of I O port 1 CS1 is activated
53. processor board produces the necessary wait states even if it accesses the I O space of another processor board The number of inserted wait states in the I O port space 1 to 7 CS1 to CS7 depends on the adjusted wait states of the busmaster processor board and not on the adjusted wait states of the accessed processor board T O Port 1 to I O Port 7 address 0x80204000 0x80207FFF CS1 I O port 1 freely usable address 0x80208000 0x8020BFFF CS2 I O port 2 freely usable address 0x8020C000 0x8020FFFF P CS3 I O port 3 freely usable address 0x80210000 0x80213FFF CS4 I O port 4 freely usable address 0x80214000 0x80217FFF CS5 I O port 5 freely usable address 0x80218000 0x8021BFFF P CS6 I O port 6 freely usable address 0x8021C000 0x8021FFFF P CS7 I O port 7 freely usable D addresses are only valid for global memory page 0 default state after delivery user s guide micro line CAACPU page 16 Wait State Control Register 1 D31 D1 DO x x x x x x x x x x x x xix x x x x x x x xi x x x x x x x x not used 1 DO T O port 1 2 3 O wait states 1 wait state 4 wait states 7 wait states address 0x80220000 only writable not readable 7 wait states after reset both STRBO SWW bits software wait mode of the TMS320C44 global memory interface
54. put if C44CPU control register bits DO 1 and D1 0 host port function if C44CPU control register bit DO 2 0 Read Port 3 Read Write Host Port Register D31 D8 D7 D6 D5 D4 D3 D2 D1 DO x ix x xix x x x x x x x x x x x x xix x x x x x not used Port Pin Function input Host Port Function HD3 input DO host port data register 0 0 write data to HDO HD8 1 1 read data from HDO HD8 Port Pin Function output DO D8 port pin HDO HD8 address 0x8023C000 if port pin function and output DO D8 are only writable not readable HD4 HD8 are always outputs if port pin function and only writable port pin function HD3 input if C44CPU control register bits DO 1 and D1 0 port pin function HDO HD8 output if C44CPU control register bits DO 1 and D1 1 with the reset signal all port pin outputs are internally set to 1 host port function if C44CPU control register bit DO 0 D addresses are only valid for global memory page 0 default state after delivery user s guide micro line C44CPU page 21 2 16 Host Port Register Host Side The host port registers are the four C44CPU registers which can be addressed by the connected host processor They are decoded by the respective selection of the C44CPU host processor address ports HAO and HA1
55. ram IO Yo IO YO YO VO YO global host in waitstate generator l waitstate generator 2 waitstate local RAM 0 waitstate global bus local bus TMS320C4x floating point CPU core DMA DMA DMA DMA DMA DMA DSP DSP DSP DSP pro emu timer timer watch chan chan chan chan chan chan link link link link 1 2 do gramm lator 1 4 5 6 112 3 4 8 cache port 2 2 DualBusArchitecture The used TMS320C44 processor provides two physically separated external buses local bus and global bus The program code fetch and data move can for example be executed externally by separate bus systems which leads to a significantly improved performance Another possibility is to directly combine the global buses of several C44CPU boards to a shared memory in a multiprocessor configuration with up to eight boards In this case the global memory and the I O space of each board are attached with a page on an increasing address space Therefore each processor has a direct access to the entire global RAM of all boards as well as to their I O space Forimplementing a shared memory system itis necessary to have an external bus arbiter componentin orderto manage the hardware access rights 2 3 RS232 Interface TheRS232 interface with its integrated line drivers is acommunication interface between the development PC and the C44CPU board The RS232 interface performs all downloading p
56. rocesses and FILE operations between the development PC and the C44CPU board The RS232 interface can additionally be used as a universal interface for various applications The SCC2691 device and the line drivers enable maximum asynchronous transfer rates of up to 115200 baud The SCC2691 component data sheets are listed in the appendix The interface consists of the signal ports TxD transmit RxD receive RTS request to send and CTS clear to send If the RS232 interface is not used the SCC269 1 componentas well as the line drivers can be switched to powerdown mode via software in order to reduce the power consumption In this case the 3 68 MHz output clock pin E30 is deactivated user s guide micro line CAACPU page 6 2 4 Parallel Host Port The parallel host port enables either a direct connection of two or several C44CPU boards or of one or several C44CPU boards to any host processor The host port establishes a fast parallel bus connection between the communication partners The C44CPU board is connected as a bus participant to the host processor just like a normal peripheral device and can be accessed via various registers The implemented bus width on the board is 9 bits and can be extended to 32 bits with only one external device see appenix Here the following control signals are available HOST_OUT_CLK HOST_OUT_OE HOST_IN_CLK and HOST_IN_OE The host port data exchange can be performed in polling interruptor DMA mode
57. rrupt lines INTO IIOFO to INT3 IIOF3 on the micro line bus as well as interupt triggering for the broadcast interrupt the host port interrupt and the RS232 interface After asserting the low signal the external interrupt lines trigger a respective interrupt on the processor The signals can either be acitvated or disabled in the processor s IF Interrupt Flag register and can optionally be programmed as edge and state triggered inputs The CPU interrupt signals TOF 1 IIOF2 and IIOF3 havea double function on the C44CPU board 1 they are located on the pin for the external hardware interruptand 2 additional board internal interrupt sources are eventually also switched to the interrupt lines see the following table CPU interrupt interruptsource 1 interrupt source 2 IIOFO INTO IIOFO0 pin HOF INTI IIOFI pin broadcast interrupt IIOF2 INT2 IIOF2 pin host port interrupt IIOF3 INT3 IIOF3 pin RS232 interrupt If necessary the double occupied interrupt sources can be determined by software via respective polling within the interrupt program For the host port this is possible by querying the register read port 1 read host port Tx status register transmit status or read port 2 read host port Rx status register receive status For the RS232 interface the status register SR of the SCC2691 device can be queried For the broadcast interrupt polling can only be performed via the additional external interrupt souc
58. smaster which affects the processor interrupt IIOF1 The broadcast interrupt bit has to be reset in the interrupt program Read Port 1 Read Host Port Tx Status Register D31 DO x ix x xix x x x x x x x x x x x x xix x ix x x x x xx x x x x x not used Port Pin Function HDI input DO 0 1 1 Host Port Function read host port Tx status DO Tx bufferempty 1 Tx buffer full 0 address 0x80234000 only readable not writable HD4 HD8 are always outputs if configured to port pin function port pin function input if C44CPU control register bits DO 1 and D1 0 host port function if C44CPU control register bit DO 0 D addresses are only valid for global memory page 0 default state after delivery user s guide micro line CAACPU page 20 Read Port 2 Read Host Port Rx Status Register D31 DO x x x x x x x x x x x x x xix x x x x x x x x x x x x x x x x x not used Port Pin Function HD2 input DO 0 1 1 Host Port Function read host port Rx status DO Rx buffer full 1 Rx buffer empty 0 address 0x80238000 only readable not writable HD4 HD8 are always outputs if configured to port pin function port pin function in
59. ted The SCC2691 data sheets are listed in the appendix user s guide micro line CAACPU page 8 2 10 Reset Generator Watchdog The C44CPU board provides a reset generator which generates a defined reset pulse during power ON during a manual reset e g with a RESETIN pin switch during a power supply drop below 4 65V or incase of a watchdog event The generated reset pulse has a duration of at least 140 ms and activates the RESETOUT and RESETOUT lines during the 140 ms period The watchdog is activated by solder bridge L9 If the watchdog is not required solder bridge L9 remains open default state watchdog not active The maximum watchdog retrigger interval is 1 6 seconds A system reset pulseis generated after every exceeded retrigger interval The watchdog is retriggered by a read or write access to the SCC2691 device on the following addresses 0x8022C000 0x8022C007 global memory page 0 default stateafter delivery 0x8026C000 0x8026C007 global memory page 1 0x802ACO000 0x802AC007 global memory page 2 0x802ECO000 0x802EC007 global memory page 3 0x8032C000 0x8032C007 global memory page 4 0x8036C000 0x8036C007 global memory page 5 0x803ACO000 0x803AC007 global memory page 6 0x803ECO000 0x803EC007 global memory page 7 o000000000000000000000000000000
60. ter 2 readable ACR writable ISR Interrupt Status Register and IMR Interrupt Mask Register address 0x8022C005 ISR readable IMR writable CTU Counter Timer Upper and CTUR Counter Timer Upper Register address 0x8022C006 CTU readable CTUR writable CTL Counter Timer Lower and CTLR Counter Timer Lower Register address 0x8022C007 P CTL readable CTLR writable D addresses are only valid for global memory page 0 default state after delivery user s guide micro line CAACPU page 19 Read Port 0 Set Reset Broadcast Interrupt Register D31 DO x x x x x x x x x x x x x xi x x x x x x x x x x x x x x x x x x not used PortPin Function HDO input DO 0 0 1 1 Host Port Function broadcast interrupt DO force broadcast interrupt release broadcast Interrupt 0 O address 0x80230000 only readable if the host portis switched to port pin function C44CPU control register bit DO 1 and if the host port pins HDO HD3 are switched to inputs C44CPU control register bit D1 20 HD4 HD8 are always outputs if configured to port pin function only writable broadcast interrupt if the host portis activated C44CPU control register bit DO 1 A broadcast interrupt can be triggered via software e g via the global bus of an external bu
61. uts in the C44CPU control register and to outputs in the processor s IF Interrupt Flag register should be avoided 2 19 LEDs The C44CPU processor board has one green one red and one yellow LED The green LED is the visual control light for flash EPROM accesses It operates similar to the LEDs on the hard disk and flashes with every flash memory access The red LED can be controlled by software and be switched ON or OFF by setting or resetting the bit D6 of the C44CPU control register The yellow LED can also be switched ON or OFF by bit D10 of the C44CPU control register 2 20 Clock Frequency Processor Performance The C44CPU board s available clock frequencies are 40 50 60 and 80 MHz The resulting maximum processor performances are 40 50 60 and 80 MFLOPS Million Floatingpoint Operations Per Second or 20 25 30 and 40 MIPS Million Instructions Per Second user s guide micro line CA4CPU page 24 3 Software 3 1 Summary The FILE system of the C44CPU board consists of the commands DIRML DELML RENML FORMATML CHKDSKML RUNML FLOAD44 and SLOADAA All instructions are residently installed in the C44CPU board s flash EPROM and the corresponding commands are stored as EXE and SET FILES on the development PC In order to execute a FILE command the respective command e g DIRML has to be entered on the development PC under MS DOS 3 3 or higher The communication with the C44CPU board is carried out via the RS232 interf
62. ve high Ifnecessary the IACK output pin can be pulsed within the interruptroutine by the assembler command TACK The signal pair RD_Oand WR_Oisan alternative to the signal pair R W Ound STRB 9O Either signal pair can be used depending on the manufacturer and the type of the peripheral boards As a rule INTEL compatible boards require signal pair RD_Ound WR_0and MOTOROLA compatible boards require signal pair R W Ound STRB O0 user s guide micro line CA4CPU page 7 2 6 DSPLinks The TMS320C44 processor provides altogether four 8 bit wide link ports Each of the four ports can transfer one byte per H1 clock For the 40 MHz processor theresultis a transfer rate of 20 Mbytes per second per link for the SOMHz processor the rate is 25 Mbytes per second per link for the 60 MHz type the rate is 30 Mbytes per second per link and for the 80 MHz type the rate is 40 Mbytes per second per link Each link port consists of the signal lines CnDO to CnD7 data CREQn token request CACKn token request acknowledge CSTRBn data strobe CRD Yn data ready and CDIR direction For the signal configuration please refer to the informations provided in the Texas Instruments TMS320C4x user s guide chapt 8 1 to 8 32 For link lines over 20 cm it is furthermore recommended to buffer the data and control signals viaa driver e g 74HC245 The data direction is determined by the CDIR signal The ground connections between the processor board a
63. y powerful Arithmetic Logic Unit ALU which performs additions multiplications divisions and root functions with hardware support in just oneclock cycle The TMS320C44 processor s multiplier operates with an accuracy of 40 bits floating point or 2 x 32 bits with a 64 bit result integer The ALU accuracy is 40 bits floating point or 32 bits integer The CPU core furthermore has a 32 bit barrel shifter and two independent address calculation units in order to execute parallel commands by several operands The local and global address width is 2 x 24 bits and enables a maximum memory size of 2 x 16M words The available processor speeds are 40 50 60 and 80 MHz Additionally to the TMS320C44 processor s internal 2K word RAM there are two external static O wait state RAM banks with optionally 2 x 32K words 256 kbytes or2 x 128K words 1 Mbyte as program and data memory available The RAM banks can be buffered via the internal 128 words deep program cache memory of the TMS320C44 processor The size of the flash EPROM boot memory is optionally either 128 kbytes or 512 kbytes Operations withORSYS micro line systems are virtually problem free ORS YS processor boards are pin and softwarecompatibleand price and performance categorized They are available with an extensive system software and universal peripheral components ORS YS offers a powerful application end product which leads to a short development time low development costs and a min
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