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IXDP465 Development Platform User's Guide

1. IXDP465 Baseboard Hardware Design Figure 14 LED Locations Power LEDs 12 0V 5 0V T Power LED 12 0V HLEV 3 3v Oo 1 al i 1 2020 PCILEDs EN 1 CPU Power LEDs 4 ar gt Optio 66 MHz 33MHz Host 10n ees 1 i e ai aa ONDE MINI ES o MUT dE i GPIO LEDs 25V FLASH GPIO 15 GPIO 14 STATUS GPIO 13 GPIO 12 GPIO 11 GPIO 10 9 5 GPIO 8 GPIO 7 GPIO 6 GPIO 5 GPIO 4 GPIO 3 GPIO 2 GPIO 1 I GPIO 0 B5022 01 September 2005 82 UG Inte IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 In 3 17 3 18 Table 56 UG IXDP465 Baseboard Hardware Design Debug Circuitry An Intel 10 100 EthernetPro Adapter card using the Intel 82559 Ethernet PHY component can be plugged into a PCI slot and used as the debug Ethernet port JTAG Interface The IXP465 network processor is controlled during debug through a JTAG interface to the processor The Macraigor Raven and Wind River visionPROBE visionICE systems plug into the JTAG interface through a 20 pin connector Figure 15 shows the JTAG interfac
2. Power Board to Board Supply Connector sheet 8 sheet 3 Dee JTAG x INT Controller Controller m HPF SDRAM Alcatel gt Alcatel wap pis Hybrid sheet 7 MTC 20156 MTC 20154 sheet sheet 6 sheet 5 sheet 6 2 27 mel INT Board to Board Connector for Stacking iiu Figure23 ADSL Card Component Placement Address Space Jumpers JP3 AD2 JP2 AD1 JP1 ADO JP4 JP5 GND GND qe 2 a a JP6 GND B5039 01 To have multi channel PHY support multiple IXPDSM465 ADSL cards are stacked top of each other through the board to board stacking connector Each card has a plug connector on the bottom side and a receptacle connector on the top side to allow them to stack as shown in Figure 3 on page 21 September 2005 Intel IXDP465 Development Platform User s Guide UG 112 Order Number 306462 Revision 004 Mezzanine Card Hardware Design Each ADSL card has its own address space and three 3 pin jumpers that allow a user defined address space for that particular card JP3 JP2 JP1 A single expansion bus chip select along with the expansion bus addresses defined on each card allows individual communication to each device Figure 24 shows the ADSL Stacking Logic The top three expansion bus address lines are compared to the address set on the jumpers If the address matches and an expansion bus chip select has
3. The IXDP465 platform MII 0 expansion connector signal definition is described in Table 35 The power signals are 1 8 V 3 3 V and 5 0 V The expansion bus signals provide the 16 MSB of the Signal Pin Signal Pin Signal Pin EX_DATA8 18 GND 58 GND 98 EX DATA11 19 EX CLK MIIO 59 ETHB RXDATA2 99 EX DATA10 20 EX RD N 60 ETHB TXCLK 100 21 GND 61 ETHB RXDATA1 101 22 EX WR N 62 ETHB COL 102 EX DATA13 23 EX ALE 63 ETHB RXDATAO 103 EX DATA12 24 EX RDY NO 64 ETHB_TXDATA3 104 EX_DATA15 25 EX_IOWAIT_N 65 GND 105 EX_DATA14 26 ETHB_INT_N 66 ETHB_TXDATA2 106 GND 27 EX_CS_N4 67 ETHB TXDATA1 107 GND 28 3 3V 68 GND 108 EX ADDR1 29 69 ETHB TXDATAO 109 EX ADDRO 30 3 3V 70 ETH MDC 110 EX ADDR3 31 5 0 V 71 ETHB_CRS 111 EX_ADDR2 32 3 3V 72 ETH_MDIO 112 EX_ADDR5 33 5 0 V 73 12V 113 EX_ADDR4 34 23v 74 25V 114 EX ADDR7 35 5 0 V 75 12 115 EX_ADDR6 36 3 3V 76 25 V 116 GND 24 5 0 V 77 12V GND 38 2v 78 2 5 V 118 EX_ADDR9 39 5 0 V 79 119 EX_ADDR8 40 8 3 V 80 25V 120 Legend power signals purple IXP4XX Network Processor extended expansion bus signals green GPIO signals maroon MII signals connected to NPE B black MII signals common red not used JTAG signals gray interrupt signal gold data bus and the 1 MSB of the address bus The common among all mezzanine cards and dedicated this mezzanine card only future expansion signals connect to the network processor module an
4. 1 of 2 Signal Pin 4 Signal Pin Signal Pin EX_REQ_N3 1 GND 41 C_FN_66 81 EX_GNT_N3 2 C_FN_40 42 C_FN_67 82 EX_REQ_N2 3 C_FN_41 43 C_FN_68 83 EX_GNT_N2 4 GND 44 C_FN_69 84 EX REQ N1 5 C FN 42 45 C FN 70 85 EX GNT N1 6 C FN 43 46 C FN 71 86 EX REQ GNT N 7 GND 47 C_FN_72 87 EX_GNT_REQ_N 8 C_FN_44 48 C_FN_73 88 EX_WAIT_N 9 C FN 45 49 C FN 74 89 EX SLAVE CS N 10 GND 50 C FN 75 90 C FN 10 11 FN 46 51 C FN 76 91 C FN 11 12 FN 47 52 C FN 77 92 C FN 12 13 GND 53 C FN 78 93 C FN 13 14 FN 48 54 C FN 79 94 C FN 14 15 FN 49 55 C_FN_80 95 C_FN_15 16 GND 56 C_FN_81 96 C_FN_16 17 C_FN_50 57 C_FN_82 97 C_FN_17 18 C_FN_51 58 C_FN_83 98 C_FN_18 19 GND 59 C_FN_84 99 C_FN_19 20 C_FN_52 60 C_FN_85 100 C_FN_20 21 C_FN_53 61 C_FN_86 101 C_FN_21 22 GND 62 C_FN_87 102 C_FN_22 23 C_FN_54 63 C_FN_88 103 C_FN_23 24 C_FN_55 64 C_FN_89 104 C_FN_24 25 GND 65 C_FN_90 105 C_FN_25 26 C_FN_56 66 C_FN_91 106 C_FN_26 27 C_FN_57 67 C_FN_92 107 C_FN_27 28 2 5 V 68 C_FN_93 108 C_FN_28 29 2 5 V 69 C_FN_94 109 C_FN_29 30 C_FN_58 70 C_FN_95 110 C_FN_30 31 C_FN_59 71 C_FN_96 111 C_FN_31 32 5 0 V 72 C_FN_97 112 C_FN_32 33 45 0 V 73 C FN 98 113 C FN 33 34 FN 60 74 C FN 99 114 C FN 34 35 FN 61 75 C FN 100 115 C FN 35 36 C FN 76 SYS RST N 116 Intel IXDP465 Development Platform User s Guide UG Order Number 306462 Revision 004 intel Table 74 UG Network Processor Module Hardware
5. 161 Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 9 Revision History Revision History September 2005 10 Date Revision Description September 2005 004 Corrected document order number no other changes from 003 version Updates for this release include Figure 13 added new figure describing MAC Address Label Table 55 rewrote LED definitions to match the silkscreen Figure 14 corrected typo for 1 8 V Power LED to make it match the silkscreen August 2005 003 Section 3 19 updated core voltage references from 1 4 V to 1 5 V for Intel IXP465 Network Processor at 667 MHz Figure 19 updated figure with new voltage regulator and resistor value Appendix A added fis command clarifications Added more than 200 document clarifications that resulted from a review cycle of technical grammar and overall formatting These changes not shown with change bars Updates for this release include May 2005 002 Added new switch jumper and LED figures revised SMII section added software enabled features section in Introduction added IXP460 and IXP45X emulation section in Overview updated Appendix A miscellaneous edits for consistency among headings captions etc April 2005 001 First edition Intel IXDP465 Development Platform User s Guide UG Order Number 306462 Revision 004 intel Inte IXDP465 Developme
6. Signal Pin Signal Pin Signal Pin 1 EX_ADDR11 41 5 0 V 81 2 EX_ADDR10 42 ao V 82 3 EX_ADDR13 43 GPIO2 83 4 EX_ADDR12 44 GPIO3 84 EX_DATA1 5 EX_ADDR15 45 GND 85 EX_DATAO 6 EX_ADDR14 46 GND 86 EX_DATA3 7 GND 47 87 EX_DATA2 8 GND 48 GPIO4 88 GPIOO 9 EX ADDR17 49 89 GPIO1 10 EX ADDR16 50 EX DATA5 11 EX ADDR19 51 91 EX DATA4 12 EX ADDR18 52 HSS SEC TXFRAME 92 EX DATA7 13 ADDR 1 53 93 EX_DATA6 14 EX_ADDR20 54 HSS_SEC_TXCLK 94 GND 15 EX ADDR23 55 GND 95 GND 16 EX_ADDR22 56 HSS_SEC_TXDATA 96 EX DATA9 17 GND 57 HSS_PRI_TXDATA 97 EX_DATA8 18 GND 58 GND 98 EX_DATA11 19 EX_CLK 59 HSS PRI TXFRAME 99 EX DATA10 20 EX RD N 60 HSS PRI RXDATA 100 21 GND 61 101 22 WR_N 62 HSS PRI RXFRAME 102 EX DATA13 23 EX ALE 63 HSS PRI TXCLK 103 EX DATA12 24 EX RDY N 64 104 EX DATA15 25 EX IOWAIT N 65 GND 105 EX DATA14 26 HSS INT OUT N 66 HSS PRI RXCLK 106 GND 27 EX CS N 67 107 GND 28 3 3 V 68 GND 108 EX ADDR1 29 69 HSS SEC RXCLK 109 EX ADDRO 30 33V 70 110 EX_ADDR3 31 5 0 V Ti HSS SEC RXFRAME 111 EX ADDR2 32 3 9 V 72 HSS_SEC_RXDATA 112 Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 145 Mezzanine Card Hardware Design Table 91 5 4 2 4 Table 92 September 2005 146 Stacking Interface S
7. Intel IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 113 Mezzanine Card Hardware Design Table 75 September 2005 114 ADSL Connector Signals Sheet 2 of 2 Signal Pin Signal Pin Signal Pin GND 4 3 3 V 44 UTP_OP_DATA1 84 DSL_INT_N 5 45 UTP_OP_DATA7 85 EX_ADDRO 6 33V 46 UTP_OP_DATA3 86 GND 7 47 UTP_OP_DATA4 87 EX_ADDR2 8 3 3 V 48 UTP_OP_DATA5 88 ADDR1 9 GND 49 UTP OP DATA6 89 GND 10 GND 50 GND 90 EX ADDR3 11 3 3 V 51 GND 91 ADDR4 12 3 3 M 52 UTP OP FCI 92 GND 18 53 UTP_IP_DATA7 93 EX ADDR6 14 54 UTP_OP_SOC 94 EX_ADDR5 15 2 5 V 55 UTP_IP_DATA3 95 EX_ADDR8 16 2 5V 56 GND 96 EX_ADDR7 17 GND 57 UTP_IP_DATA5 97 GND 18 GND 58 UTP_IP_DATA4 98 EX_ADDR9 19 EX_ADDR21 59 UTP_IP_SOC 99 EX_CLK_ADSL 20 EX_ADDR22 60 UTP_IP_DATA6 100 GND 21 GND 61 UTP_IP_FCO 101 GND 22 GND 62 UTP_GPIO3 102 EX_DATAO 23 3 3V 63 GND 103 EX DATA2 24 EX IOWAIT N 64 GND 104 EX DATA1 25 65 UTP_IP_ADDR4 105 EX_DATA4 26 GND 66 UTP_OP_ADDR4 106 UTP_GPIOO 27 GND 67 UTP_IP_ADDR3 107 UTP_GPIO1 28 EX_ADDR23 68 UTP_OP_ADDR3 108 EX_DATA3 29 UTP_IP_CLK 69 GND 109 EX_DATA6 30 GND 70 UTP_OP_ADDR2 110 EX_DATA5 31 GND fl UTP_IP_ADDR2 111 EX_DATA7 32 UTP_OP_CLK 72 GND 112 GND 33 UTP_IP_DATA1 73 UTP_IP_ADDR1 113 GND 34 GND 74 UTP_OP_ADDR1 114
8. gi Access Type Address 0 0 0 0 0 Control Status 0x54000000 R W 0 0 0 0 1 PCI Host Present 0x54000001 RO 0 0 0 1 0 PCI Host 66 MHz Enable 0 54000002 RO 0 0 0 1 1 FPGA Programming 0x54000003 R W 1 1 1 X X Reserved I Note Since the IXDP465 platform uses a 32 Mbyte flash device extended addressing must be used for the expansion bus decode versus the 16 Mbyte addressing used on the IXDP425 platform 0 54 versus 0 52 Control Status Register The expansion bus is software programmable for 33 MHz 40 MHz 66 MHz or 80 MHz The USB device pull up enable is also software programmable The LCD timer status is Read Only The Expansion Bus Clock select is a Read or Write register whose bit definitions are defined in Table 62 Control Status Register Bit Definitions D7 D6 D5 D4 D3 D2 D1 DO LCD TIME LCD TIME LCD TIME LCD TIME LCD TIME Table 63 lists the definitions of the Control Status register s expansion bus frequency control bits The expansion bus clock frequency is controlled by F 1 0 of the Control Status register The default frequency after a reset is 33 MHz Expansion Bus Frequency Select Bit Definitions F1 FO Expansion Bus Frequency 0 0 33 MHz default after reset 0 1 40 MHz 1 0 66 MHz 1 1 80 MHz The Control Status Register s USB De
9. Inte IXDP465 Development Platform User s Guide UG Order Number 306462 Revision 004 I ntel Network Processor Module Hardware Design Figure 24 IXDP465 Mezzanine Card Connector Pin out Table 71 shows the PCI Bus connector signal assignment The signals include all IXP465 signals There are 10 reserved signals that must be left unconnected The USB signals connect directly to the IXP465 The 16 GPIO signals connect directly to the IXP465 The PCI signals connect directly to the 465 and the pin locations were chosen to allow for direct connection to the PCI fingers without crossover The PCI finger number is shown in the table for reference Table 71 IXP465 Network Processor Module PCI Bus Connector Signals Sheet 1 of 2 Signal Pin PCI Pin Signal Pin PCI Pin Signal Pin PCI Pin C PCI 0 1 GND 41 GPIO10 81 C PCI 1 2 PCI ADD29 42 B21 GPIO11 82 USB_DPOS 3 PCI_ADD28 43 A22 GPIO12 83 USB DNEG 4 GND 44 PCI SERR 84 B42 USB HPOS 5 PCI ADD26 45 A23 PCI PAR 85 A43 USB HNEG 6 PCI ADD27 46 B23 GND 86 USB HPEN 7 GND 47 PCI ADD15 87 A44 USB HPWR 8 PCI ADD25 48 B24 PCI CBE 88 B44 GPIOO 9 PCI ADD24 49 A25 GND 89 GPIO1 10 GND 50 PCI ADD14 90 B45 PCI INTA N 11 A6 PCI IDSEL 51 A26 PCI ADD13 91 A46 GND 12 PCI CBE N3 52 B26 PCI REQ 13 GND 53 PCI ADD11 93 A
10. a l TERES sg sssi SN ee LI ctp Table 84 Control Byte Bit Definition Indicates a broadcast operation for all devices in the daisy chain This is only valid for d BROT Write operations because it causes contention on the SDO pin during a Read Read Write Bit 6 R W 1 Read operation 0 Write operation 1 This bit must always be 1 4 0 This bit must always be 0 This field indicates the channel that is targeted by the operation The 4 bit channel value is provided with the LSB first The devices reside on the daisy chain with device 0 nearest to the controller and device 15 farthest away in the SDI SDITHRU chain See Figure 31 3 0 CID 0 3 As the CID information propagates down the daisy chain each channel decrements the CID by one The device that receives a value of 0 in the CID field responds to the SPI transaction See Figure 31 If a broadcast to all devices connected to the chain is requested the CID does not decrement In this case the same 8 or 16 bit data is presented to all channels regardless of the CID values 5 3 4 2 FXS SPI Interface The SPI interface for access control and status information for the FXS Silicon Laboratories 513210 uses 16 bit serial interface Four signals from the CPLD control this interface These signals are routed to the SPI interface for IXDP465 applications or to GPIO f
11. sese 134 86 Internal CPLD Registers U a 135 87 PCM E oL Ec 137 88 PCM Slot en rens 138 89 IXDP465 Interface Standard Connector Signals 142 90 IXDP465 Interface Expansion Connector 143 91 Stacking Interface Standard Connector Signals sese 145 92 Stacking Interface Expansion Connector 10 146 93 T1 E1 Unique Stacking 105 reote rnc toc 148 94 T1 E1 Unique Stacking IDs and Expansion Bus Addresses 149 September 2005 Intel IXDP465 Development Platform User s Guide UG 8 Order Number 306462 Revision 004 ntel Contents UG 95 CPLD Pin ASsignimenls U UU Luna reete Eae eoo tendi aite ed 149 96 Quad T1 E1 Card CPLD Voltage Filtering 151 97 Quad T1 E1 Card CPLD JTAG Interface Pin 152 98 Quad Framer Processor Interface Pin Assignments sse 154 99 Quad Framer Line Interface Pin Assignments nennen 155 100 Quad Framer Power Interface Pin Assignments 155 101 Quad Port Transformer Interface Pin 159 102 RJ 45 Connector Pin
12. 121 5 3 2 1 IXDP465 Interface Standard 121 5 3 2 2 IXDP465 Interface Expansion Connector 123 5 3 2 8 Stacking Interface Standard 125 5 3 2 4 Stacking Interface Expansion 126 5 3 3 Analog Voice Card Stacking 11 128 53 31 Board D uuu 128 5 3 3 2 Expansion Bus Accesses 129 5 9 9 3 Glocki ng Frarmming s iiiter tret ettet en ete terere 129 5 3 4 Analog Voice Card SPI 131 53 44 FXO SPI Interface eet t tendon eadein deben 131 5 9 4 2 EXS SPI Interface aient erste trea sacco runde 132 5 3 5 Analog Voice Card 134 5 3 5 1 Internal CPLD lt 135 5 3 52 E 137 5 3 5 3 POM Clocks and Framing essen 137 5 3 5 4 M ster C lo6K u ua tete dct rte inia ne dada 139 53 5 5 126 Interface en cs vea e ae ede 139 5 3 5 6 Relay 139 5 9257 LED Indicators es
13. 00 n nennen 58 Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 3 Contents ntel 3 9 1 MII 0 Mezzanine 58 392 1 Mezzanine 62 393 2 Mezzanine 66 SNLMESIIARTUT 70 DSBH081u EET 70 3 12 Serial 70 3 12 1 DB 9 Connector EMI Considerations 71 3 12 2 Serial Port Pull Ups Pull Downs a 72 Eae do TE 72 3 131 GPIO FPGA ACCESS 73 3 13 2 GPIO FPGA 0 441 esses enne aaiae nennen 73 3 13 3 GPIO FPGA Configuration 75 3 14 2G riterfaGe eni eere AN nte ea Lace Rer Ren don Ree op ERR an TRA 78 3 144 J2C Addressing ait a e Ru 78 3 15 SPlLIntetfaGe uuu tetra trant ean te e e rne ng Re n n 80 3 16 LED Indicators t 80 3 17 Debug a 83 318 FERE u uuu uuu u Lm 83 SNAM UI 84 3 19 1 Monitoring 3 3 V 86 3 19 2 Monitoring 2 5 V Gurfe tusu uuu
14. or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them Intel processor numbers are not a measure of performance Processor numbers differentiate features within each processor family not across different processor families See http www intel com products processor_number for details This User s Guide as well as the software described in it is furnished under license and may only be used or copied in accordance with the terms of the license The information in this manual is furnished for informational use only is subject to change without notice and should not be construed as a commitment by Intel Corporation Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this document or any software that may be provided in association with this document Except as permitted by such license no part of this document may be reproduced stored in a retrieval system or transmitted in any form or by any means without the express written consent of Intel Corporation Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an order number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or by visiting Intel s website at
15. 33 Configuration Strapping Options enemies 35 Configuration Strapping Clock 36 Expansion Bus Chip Select Assignments nennen 38 IXDP465 Overall Address Mapping nennen nennen nnns nnne nens 38 IXDP465 Expansion Bus Address 39 Flash Secti hing ides 40 UTOPIA Level 2 u a p a A 41 CE 42 HSS 0 Mezzanine Card Standard Connector Signals sss 43 HSS 0 Mezzanine Card Expansion Connector Signals sss 44 HSS 1 Mezzanine Card Standard Connector 46 HSS 1 Mezzanine Card Expansion Connector Signals sss 48 NPE SMII Configurations diel ante 54 Jumper Block JP1 Pin 54 NPE A MII Jumper Block JP2 Pin 55 NPE A UTOPIA Jumper Block Pin 56 NPE B MII Jumper Block JP4 Pin 57 NPE C MII Jumpers JP65 JP93 Pin Assignments aa 57 INC T 58 MII 0 Mezzanine Card
16. IXDP465 Baseboard Hardware Design Table 48 GPIO FPGA Configuration Register Bit Definitions D7 D6 D5 D4 D3 D2 D0 Dir Attach6 Attach5 Attach4 Attach3 Attach2 Attach1 Attach0 The Dir bit defines the mezzanine card GPIO signal direction Table 49 defines the Dir bit settings Table 49 GPIO FPGA Direction Bit Definition Dir Direction from FPGA Pin to Network Processor 0 Input 1 Output a Default direction is Input to the FPGA after reset The attach value defines the mezzanine card GPIO signal that the associated network processor GPIO is attached to or it is not attached Table 50 shows the GPIO attach values the associated mezzanine card GPIO signal and the FPGA pin to which the signal is routed Table 50 GPIO FPGA Attach Values and FPGA Pin Assignments Sheet 1 of 2 Att Signal Att Signal Signal RA Att Signal E 0 ETHB GPIOO 187 32 ETHA GPIOO 132 64 HSS1 GPIOO 102 96 Reserved 1 ETHB_GPIO1 188 33 ETHA_GPIO1 133 65 HSS1_GPIO1 57 97 Reserved n a 2 ETHB GPIO2 189 34 ETHA GPIO2 134 66 HSS1 GPIO2 58 98 Reserved 3 ETHB GPIO3 191 35 ETHA GPIO3 136 67 HSS1 GPIO3 59 99 Reserved n a 4 ETHB GPIO4 192 36 GPIO4 138 68 HSS1 GPIO4 60 10 Reserved 5 ETHB_GPIO5 193 37 ETHA_GPIO5 139 69 HSS1_GPIO5 61 101 Reserved n a 6 ETHB_GPIO
17. Intel IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 September 2005 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT Intel products are not intended for use in medical life saving life sustaining critical control or safety systems or in nuclear facility applications Intel may make changes to specifications and product descriptions at any time without notice Intel Corporation may have patents or pending patent applications trademarks copyrights or other intellectual property rights that relate to the presented subject matter The furnishing of documents and other materials and information does not provide any license express or implied by estoppel or otherwise to any such patents trademarks copyrights or other intellectual property rights Designers must not rely on the absence or characteristics of any features or instructions marked reserved
18. PAR B11 PCI HST PRSNT2 NO B43 3 3 V A14 44 PCI 5 AD15 B14 B44 PCI HST CBE 1 A15 PCI HST RST N A45 3 3V B15 GND B45 PCILHST_AD14 A16 3 3V A46 PCILHST_AD13 B16 PCILHST_CLKO B46 GND A17 PCILHST_GNT_NO A47 PCI HST AD11 B17 GND B47 PCI HST AD12 A18 GND A48 GND B18 PCI REQ NO B48 PCI_LHST_AD10 A19 A49 PCILHST_AD9 B19 3 3V B49 PCILHST_M66ENO A20 PCILHST_AD30 A50 GND B20 PCILHST_AD31 B50 GND A21 3 3 V A51 GND B21 PCILHST_AD29 B51 GND A22 5 28 A52 PCI HST CBE NO B22 GND B52 PCI_HST_AD8 A23 PCILHST_AD26 A53 3 3V B23 HST AD27 B53 HST 07 A24 GND A54 PCILHST_AD6 B24 PCILHST_AD25 B54 3 3V A25 PCI HST AD24 A55 PCI HST AD4 B25 3 3 V B55 PCILHST_AD5 A26 HST IDSELO A56 GND B26 PCI CBE B56 PCILHST_AD3 A27 3 3V A57 PCILHST_AD2 B27 PCILHST_AD23 B57 GND A28 PCI HST AD22 A58 PCI HST ADO B28 GND B58 5 AD1 A29 PCI HST AD20 59 3 3V B29 PCILHST_AD21 B59 3 3V September 2005 28 Inte IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 UG intel IXDP465 Baseboard Hardware Design Table 10 PCI Host Slot 0 Pin Assignments Sheet 2 of 2 Pin Signal Pin Signal Pi
19. gt load r v b 0x00100000 redboot_ROM bin gt fis create Redboot bak b 0x00100000 1 0x0007A000 0 51000000 e 0x00000000 fis create command is entered on a single line Switch off the power to the board and remove the JP128 jumper Verify that RedBoot boots The following information is displayed t waiting for BOOTP information Ethernet eth0 MAC address 00 07 9 16 34 72 IP 192 168 200 100 255 255 255 0 Gateway 192 168 200 254 Default server 192 168 200 254 RedBoot tm bootstrap and debug environment ROM Red Hat certified release version 2 01 built 08 07 53 Feb 22 2005 Platform IXDP465 Development Platform XScale BE Copyright C 2000 2001 2002 2003 2004 Red Hat Inc RAM 0x00000000 0x08000000 0x0002a488 0x07f d1000 available FLASH 0x50000000 0x52000000 256 blocks of 0x00020000 bytes each Executing boot script in 3 000 seconds enter C to abort Once you have verified that the RedBoot image is functional you can update the primary image Using RedBoot to Update RedBoot RedBoot must execute from RAM to program the image into flash since the primary RedBoot image runs from flash To update the primary image follow these steps 1 Load and execute redboot RAM srec gt load v redboot RAM srec Using default protocol TFTP Entry point 0x00100040 address range 0x00100000 0x001761d4 gt go Inte IXDP465 Development Platform User s Guide Septemb
20. 118 27 Analog Voice Card Logical Block Diagram a 121 28 Analog Voice Card Stacking PCM Interface a 130 29 FXO Read Operation Using 8 Bit SPI 131 30 FXO Write Operation Using 8 Bit na a 131 e m m 132 32 FXS Port SPI Daisy Chaining a 133 33 FXS Read Operation Through 8 Bit 133 34 FXS Write Operation Through 8 Bit 134 35 PCM Operation with 8 Bit Slots c cceccccceesseeeeeeeeeeaeeeeeeeeeeeeaeeeeeeseeaaeeseeeeeeseaaeseceeeeeeaeeseanees 138 36 Analog Voice Mezzanine Card Port Status 140 37 Quad T1 E1 Mezzanine Card Logical Block 144 38 TDM Interface External Clock Circuitry nnne 150 39 Quad 1 1 Mezzanine Card CPLD Core Voltage 151 40 Quad 1 1 Mezzanine Card Jumper and CPLD Header Locations 153 41 Transmit Analog Power Decoupling 1 u ull l 156 43 Transmit Analog Power Decoupling 2 and 3 157 42 Receive Analog Power Decoupling 1 and 2 u uu 157 44 Quiet Analog Power Decoupling n ns 158 Septemb
21. 2 Adda wire loop across the JP47 3 Attach an inductive current probe to the wire loop to measure the current See Figure 17 on page 98 for the JP47 IXP COREV jumper location Reset Logic The system reset is generated for several cases the IXDP465 platform Power rails are not at appropriate levels System reset generated out of JTAG circuitry ICE or boundary scan PCI Option Mode reset The IXDP465 platform is reset when a system reset is generated In addition it is reset when it is in PCI Option mode and the PCI host asserts reset Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 87 Li IXDP465 Baseboard Hardware Design ntel 3 21 September 2005 88 JTG_TRST_N must be asserted driven low during reset Otherwise the TAP controller may not initialize and lock the processor There is a weak 10 pull down resistor on JTG_TRST_N Clocking The following interfaces require oscillators on the board 465 system clock 33 33 MHz UTOPIA transmit and receive clock 33 33 MHz may be disabled through jumper option PCIhost clock 33 0 MHz and 66 0 MHz selectable Expansion bus clock 80 0 MHz external oscillator or GPIO15 selectable jumper option SMII clock 125 MHz The expansion bus and PCI can share their 33 00 MHz oscillator The expansion bus clock is selected from the following frequencies under software control processor read
22. 21 5K Soy 17180 1 1 i The output voltage is controlled by the resistor network attached to the adjust signal ADJ by the following equation Vout R1 R2 1 1 216 1 3376 V From the manufacturer s data sheet the filter capacitor on the adjust signal must be between 68 pF and 100 pf It is recommended that the output capacitor C618 must be at least 47 pF The delay circuit driving the shutdown signal must be at least lus after 3 3 V and 42 5 V to achieve its positive rail Since the voltage for the IXP465 I O has a 5 tolerance this circuit guarantees release of SHUTDOWN N no higher than 3 135 V The resistor divider network guarantees that the timer will not start until the 3 3 V has achieved 85 to 9896 of its voltage taking into account tolerances on the supply and VIN of the MAX6423 16 This avoids the lengthy rise time of the 3 3 V supply seen on heavily loaded PCI systems The resistor divider network also guarantees that the timer will not start until the 2 5 V has achieved 85 to 98 of its voltage taking into account tolerances on the supply and VIN of the MAX6423 16 This avoids the lengthy rise time of the 42 5 V supply seen on heavily loaded PCI systems A heat sink of at least 1 2 square inch 1 oz unmasked copper is necessary for proper heat dissipation To achieve the output voltage for 667 MHz 1 5 V the JP48 jumper shown in Figure 17 on page 98 must be removedto series the 1 65 KO R466 r
23. DO PCI Host Present Register Bit Definitions D7 D6 D5 D4 D3 D2 D1 DO 53 2 53 1 52 2 52 1 51 2 51 1 50 2 50 1 Note Where Sn 2 and Sn 1 00 Add in card present 7 5 W max 01 Add in card present 15 W max 10 Add in card present 25 W max 11 No add in card present PCI Host 66 MHz Enable Register The PCI Host 66 MHz Enable register Table 65 is a Read Only register that allows the software to determine if a board plugged into one of the four PCI host slots valid in PCI Host mode only is capable of 66 MHz operation PCI Host Slot 3 is represented by D3 Slot 2 by D2 Slot 1 by D1 and Slot 0 by DO PCI Host 66 MHz Enable Register Bit Definitions D7 D6 D5 D4 D3 D2 D1 DO X X X X M66EN3 M66EN2 M66EN1 M66ENO Note Where X is undefined and M66ENn is 0 2 33 MHz only 1 33 MHz or 66 MHz FPGA Programming Register The FPGA Programming register Table 66 is a Read or Write register that is used for programming configuration the GPIO FPGA FPGA Programming Register Bit Definitions D7 D6 D5 D4 D3 D2 D1 D0 x x x X X DONE INIT PROG N Notes Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 91 Li IXDP465 Baseboard Hardware Design ntel 6 1 Where X is undefined and PROG_N is an active low output 0 Program the FPGA 1 Normal Operation 2
24. EX_WR_N 35 75 UTP_IP_ADDRO 115 EX_RD_N 36 UTP_OP_DATA2 76 UTP_OP_ADDRO 116 UTP GPIO2 37 UTP_IP_DATAO 77 UTP_GPIO4 117 GASP_INT_N 38 UTP_OP_FCO 78 UTP_GPIO5 118 RST_N 39 UTP_IP_DATA2 79 5 0 V 119 EX_CS_N 40 GND 80 5 0 V 120 Inte IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 5 2 5 2 1 UG Mezzanine Card Hardware Design Legend power signals purple IXP4XX Network Processor extended green expansion bus signals UTOPIA signals red Other signals black not used JTAG signals gray IXPETM465 Ethernet Mezzanine Card Introduction The IXPETM465 Ethernet mezzanine card plugs into one of the three MII connectors on the IXDP465 baseboard through the 2x60 pin J1 connector MII 0 NPE B MII 1 NPE C or MII 2 NPE A See Section 3 9 for the IXDP465 baseboard connector description The MII Ethernet PHY mezzanine card uses the LXT971A PHY a dual speed full duplex 10 100 Fast Ethernet transceiver It provides a Media Independent Interface MII for connecting to one of the three 10 100 Media Access Controllers MACs within the IXP465 network processor Figure 26 shows the connectors on the Ethernet mezzanine card The Intel LXT971A 3 3V Dual Speed Fast Ethernet Transceiver Datasheet contains more information about the LXT971A Figure 25 identifies eight jumper locations JP1 JP8 on the Ethernet PHY mezzanine card The five address jumpers JP2 JP5 JP6 JP7 JP8
25. LSB Least Significant Byte MAC Media Access Controller MDIO Management Data Input Output mezzanine A circuit board that attaches to the development platform baseboard and provides additional card functionality Mezzanine cards may be stackable Also called daughtercard MII Media Independent Interface MSB Most Significant Byte NPE Network Processor Engine NPM Network Processor Module PCI Peripheral Component Interface PHY Physical Layer Layer 1 Interface Reserved A field that may be used by an implementation Software should not modify reserved fields or depend on any values in reserved fields RX Receive HSS is receiving from off chip SDRAM Synchronous Dynamic Random Access Memory SMII Serial Media Independent Interface T1 Type 1 trunk line September 2005 Intel IXDP465 Development Platform User s Guide UG 14 Order Number 306462 Revision 004 UG Inte IXDP465 Development Platform Introduction Table 4 List of Terminology Sheet 2 of 2 Acronym Descriptions TDM Time Division Multiplex TX Transmit HSS is transmitting off chip UART Universal Asynchronous Receiver Transmitter UTOPIA Universal Test and Operation PHY Interface for ATM WAN Wide Area Network Inte IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 September 2005 15 Intel IXDP465 Development Platform Introduction September 2005 Intel IXDP465 Development
26. Li IXDP465 Baseboard Hardware Design ntel 29 NPE A Jumper Block JP2 Pin Assignments Sheet 2 of 2 JP2 Network Processor JP2 MII Signal CFG CFG CFG CFG CFG CFG CFG CFG Pin Signal Pin 9 1 2 3 4 5 6 7 8 23 IP DATA 24 ETHA_RXDV OPT 25 C_UTP_IP_DATA5 26 ETHA_COL OPT OPT OPT OPT 27 C_UTP_IP_DATA6 28 CRS OPT Notes Table Key JP2 jumpers must NOT be installed OPT JP2 jumpers can optionally be installed all 14 jumpers IN to enable NPE A MII Mode with NPE A UTOPIA Mode disabled 3 8 3 NPE A UTOPIA Jumper Block JP3 The IXP465 network processor contains NPE pins that have multiple functions The UTOPIA jumper block connects UTOPIA specific signals to the UTOPIA mezzanine card connectors J35 and P36 Table 30 shows the pin definitions for the UTOPIA jumper block as well as the JP3 jumper pin assignments which depend on the SMII Configuration CFG selected in Table 27 To find the location of JP3 on the IXDP465 baseboard see Figure 11 Table 30 NPE A UTOPIA Jumper Block JP3 Pin Assignments JP3 Network Processor JP3 CFG CFG CFG CFG CFG CFG CFG CFG Pin Signal pin UTOPIA Sig
27. NPE 1 57 GND 97 EX_DATA24 18 C_NPE_2 58 GND 98 EX_DATA27 19 C_NPE_3 59 GPIO8 99 EX_DATA26 20 C_NPE_4 60 GPIO9 100 GND 21 NPE 5 61 GPIO10 101 GND 22 C NPE 6 62 GPIO11 102 EX DATA29 23 C NPE 7 63 GND 103 EX DATA28 24 C NPE 8 64 GND 104 EX DATAS1 25 C NPE 9 65 GPIO12 105 EX DATASO 26 C NPE 10 66 GPIO13 106 GND 27 C NPE 11 67 GPIO14 107 GND 28 C NPE 12 68 GPIO15 108 EX ADDR24 29 CLK32 IN 69 GND 109 SSPS CLK 30 C FN 48 70 GND 110 SSPS FRM 31 C FN 49 71 IDO 111 SSPS TXD 32 C FN 50 72 ID1 112 SSPS RXD 33 C FN 51 73 ID2 113 SSPS EXTCLK 34 C FN 52 74 ID3 114 5 0 V 35 C_FN_53 75 104 115 5 0 V 36 C_FN_54 76 ID5 116 C PCI 0 a7 C FN 55 77 ID6 117 PCI 1 38 FN 56 78 ID7 118 C_PCI_2 39 C_FN_57 79 I2C SDA 119 C PCI 3 40 C FN 58 80 2 SCL 120 Legend power signals purple expansion bus signals green common future needs expansion signals blue dedicated future needs expansion signals black this card only SPI signals red 2 signals gold GPIO signals maroon ID signals teal UG intel 5 3 2 3 Table 80 UG Mezzanine Card Hardware Design Stacking Interface Standard Connector The stacking interface standard connector contains the expansion bus interface GPIO HSS interface and power signals to enable stacking multiple boards on an IXDP465 HSS site This connector is pin for pin compatible with the IXDP425 development platform HSS interface connectors All signals necessary to communicate with the analog ports are available
28. UG Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 79 Li IXDP465 Baseboard Hardware Design ntel the Ethernet Figure 13 illustrates the location and identification of the six labels which are positioned next to the multi pack MII interfaces If MAC addresses are required for development the MII Ethernet card must be temporarily removed to view the MAC address labels Figure 13 Address Labels BOARD EDGE SEE DETAIL A A Serial Numbers to be consecutive incrementing in hexadecimal ZX Barcode 3 of 9 full ASCII 3 Labels to be placed approx as shown DETAIL A 1 50 MAC ADDRESS 000 0 1HHHHHE Scaled 2X TYP 6 PLCS B5111 01 3 15 SPI Interface The SPI interface on the IXDP465 platform supports the following interfaces National Semiconductor Corporation MICROWIRE Texas Instruments Incorporated Synchronous Serial Protocol SSP Motorola Serial Peripheral Interface SPI This interface operates in a master mode and supports serial bit rates from 7 2 KHz to 1 84 MHz DMA support is not required for this interface The SPI interface is routed to each mezzanine card through the expansion connector 3 16 LED Indicators Figure 55 describes the LEDs placed on the IXDP465 platform as indicators Figure 14 shows the LED locati
29. except where indicated Intel IXDP465 Development Platform User s Guide UG September 2005 76 Order Number 306462 Revision 004 intel IXDP465 Baseboard Hardware Design Table 50 GPIO FPGA Attach Values and FPGA Pin Assignments Sheet 2 of 2 FPGA FPGA FPGA FPGA Att Signal Pin Att Signal Pin Att Signal Pin Att Signal Pin 18 ETHC_GPIO2 164 50 550 2 83 82 PCI_INTC_N 120 114 Reserved n a 19 ETHC_GPIO3 165 51 HSS0_GPIO3 84 83 PCI INTD N 121 115 Reserved n a 20 ETHC_GPIO4 166 52 550 4 86 84 125 116 Reserved n a 21 ETHC_GPIO5 167 53 550 5 87 85 127 117 Reserved n a 22 ETHC_GPIO6 168 54 550 GPIO6 88 86 ETHC INT 129 118 Reserved n a 23 GPIO7 172 55 HSS0_GPIO7 89 87 HSS0_INT_N 49 119 Reserved n a 24 ETHC_GPIO8 173 56 HSSO_GPIO8 90 88 HSS1_INT_N 27 120 Reserved n a 25 ETHC GPIO9 174 57 550 GPIO9 94 89 UTP GPIOO 154 121 Reserved n a 26 ETHC_GPIO10 175 58 HSSO GPIO10 95 90 GASP INT 101 122 Reserved n a 27 ETHC_GPIO11 176 59 HSSO_GPIO11 96 91 UTP_GPIO1 3 123 Reserved n a 28 ETHC_GPIO12 178 60 HSSO_GPIO12 97 92 UTP_GPIO2 4 124 Reserved n a 29 ETHC_GPIO13 179 61 HSSO_GPIO13 98 93 UTP_GPIO3 122 125 Reserved n a 3
30. generic steps that apply to any bootloader or image to be placed into flash and made available at system Start Up to run Creating a backup copy of RedBoot Using RedBoot to update RedBoot Using the Abatron BDI2000 to load RedBoot These procedures cover typical scenarios for using the IXDP465 platform RedBoot commands entered at the RedBoot command prompt are prefaced with an gt and appear in boldface type Generic Flash Updating Using RedBoot 1 Place the image to be loaded in the tftp root directory On Linux this is t tpboot 2 Switch off the power to the board 3 Verify that JP127 JP128 labeled A23 and A24 on the PWB are installed For jumper location see Figure 11 Jumper Locations and Default Settings on page 53 4 Connect the board to the network and serial console 5 Switch on the power to the board Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 163 Updating the IXDP465 Flash Memory ntel 6 Boot RedBoot prompt Press AC Ctrl C if necessary to cancel the boot script execution The default fconfig setting has no boot script 7 Use the fis list command to view the existing flash partitions and their content Selecting flash images to run is done using jumpers as described in Table 20 Flash Sectioning on page 40 The flash segments selected with the JP127 JP128 jumpers and mapped to 0x00000000 at boot up are sp
31. pins 2 3 Low pins 2 3 High pins 1 2 Low pins 2 3 12 18 High pins 1 2 Low pins 2 3 Low pins 2 3 High pins 1 2 High pins 1 2 13 19 High pins 1 2 Low pins 2 3 High pins 1 2 Low pins 2 3 Low pins 2 3 14 20 High pins 1 2 Low pins 2 3 High pins 1 2 Low pins 2 3 High pins 1 2 15 21 High pins 1 2 Low pins 2 3 High pins 1 2 High pins 1 2 Low pins 2 3 16 22 High pins 1 2 Low pins 2 3 High pins 1 2 High pins 1 2 High pins 1 2 17 23 High pins 1 2 High pins 1 2 Low pins 2 3 Low pins 2 3 Low pins 2 3 18 24 High pins 1 2 High pins 1 2 Low pins 2 3 Low pins 2 3 High pins 1 2 19 25 High pins 1 2 High pins 1 2 Low pins 2 3 High pins 1 2 Low pins 2 3 1A 26 High pins 1 2 High pins 1 2 Low pins 2 3 High pins 1 2 High pins 1 2 1B 27 High pins 1 2 High pins 1 2 High pins 1 2 Low pins 2 3 Low pins 2 3 1C 28 High pins 1 2 High pins 1 2 High pins 1 2 Low pins 2 3 High pins 1 2 1D 29 High pins 1 2 High pins 1 2 High pins 1 2 High pins 1 2 Low pins 2 3 1E 30 High pins 1 2 High pins 1 2 High pins 1 2 High pins 1 2 High pins 1 2 1F 31 UG Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 117 Li Mezzanine Card Hardware Design ntel Figure 26 5 2 2 Note September 2005 118 The LXT971A c
32. 0 3 3 V 10 KQ ETHA_RXDV 3 3 V 10 KQ ETHA_COL GND 10 KQ ETHA_CRS 3 3 V 10 KQ ETH_MDIO 3 3 V 10 KQ ETHB_RXDATA 3 0 3 3 V 10 KQ ETHB_RXDV 3 3 V 10 KQ ETHB_COL GND 10 KQ ETHB_CRS 3 3 V 10 KQ RXDATA 3 0 3 3 V 10 KQ ETHC_RXDV 3 3 V 10 KQ ETHC_COL GND 10 KQ ETHC_CRS 3 3 V 10 KQ ETHA_TXCLK 3 3 V 10 KQ ETHA_RXCLK 3 3 V 10 KQ ETHB_TXCLK 3 3 V 10 KQ ETHB_RXCLK 3 3 V 10 KQ ETHC_TXCLK 3 3 V 10 KQ ETHC_RXCLK 3 3 V 10 KQ MII 0 Mezzanine Cards To achieve compatibility with the IXDP425 IXCDP1100 platform the following features have been designed into the IXDP465 platform MII 0 mezzanine card standard connector Connector part number Amp 5 179010 5 Exactpin out match with the IXDP425 connector Inte IXDP465 Development Platform User s Guide UG Order Number 306462 Revision 004 intel IXDP465 Baseboard Hardware Design Connection to MII on NPE B Use of expansion bus chip select 4 Use of expansion bus ready 0 The mezzanine card expansion connector has the following signal groups IXP465 SPI IXP465 IXP465 extended expansion bus 16 GPIO Mezzanine Card ID byte for stacking 32 pins for future expansion common to all mezzanine cards 16 pins for future expansion dedicated to this mezzanine card Additional power The IXDP465 platform MII 0 standard connector signals are described in Table 34 The power signals are 2 5 V 3 3 V 5 0 V and 12 0 V The expansion bus signals provide the 16
33. 15 C_ETHB_RXDATA2 16 ETHB RXDATA2 OPT OPT OPT OPT 17 C_ETHB_RXDATA3 18 ETHB_RXDATA3 OPT OPT OPT OPT 19 C_ETHB_CRS 20 ETHB_CRS 3 8 5 Note Table 32 Notes Table Key JP4 jumpers must NOT be installed OPT JP4 jumpers can optionally be installed all 10 jumpers IN to enable NPE B MII Mode NPE C Mil Jumpers JP65 JP93 JP65 and JP93 are currently identified as ETH C on the baseboard To find the jumper location see Figure 11 The IXP465 network processor contains NPE pins that have multiple functions The NPE C jumpers connect specific shared NPE signals to the NPE C mezzanine card Table 32 shows the pin definitions for the NPE C MII jumpers as well as the JP65 JP93 jumper pin assignments which depend on the SMII Configuration CFG selected in Table 27 NPE C MII Jumpers JP65 JP93 Pin Assignments JP Pin Network Processor Lien JP Pin MII Signal CFG CFG CFG CFG CFG CFG CFG CFG 1 2 3 44 5 6 7 8 JP65 pin 1 JP65 C_ETHC_TXDATAO vin ETHC_TXDATAO OPT JP93 pin 1 JP93 C_ETHC_RXDATAO in ETHC_RXDATAO UG Notes Table Key J
34. 2 2 is used In Option mode the IXDP465 baseboard can still receive its power from the ATX power supply connected to the baseboard and not use the PCI power This feature eliminates both non compliance with the PCI power rails and also any issues related to PCI power limitations The external power must be applied before the PCI host power is applied The isolation buffers are disabled until PCI host power is recognized to remove the possibility of the IXDP465 baseboard trying to power up the PCI host indirectly through the PCI interface Table 14 PCI Option Fingers Pin Assignments Sheet 1 of 2 Pin Signal Pin Signal Pin Signal Pin Signal A1 s A32 PCI AD16 B1 B32 PCI OPT AD17 A2 A33 PCI 3 3V B2 l B33 PCI OPT CBE N2 A3 A34 PCI FRAME GND B34 GND 4 PCI JTAG A35 GND 4 PCI JTAG 5 PCI IRDY 5 A36 PCI_OPT_TRDY_N B5 B36 PCI_3 3V A6 PCI OPT INTA N A37 GND B6 a B37 PCIOPT_DEVSEL_N A7 PCI_OPT_INTC_N A38 B7 PCI OPT INTB N B38 GND A8 A39 PCI_3 3V B8 PCI OPT INTD N B39 PCI OPT LOCK N A9 A40 PCI SMBCLK B9 PCI PRSNT1 B40 PCI A10 A41 PCI SMBDAT B10 B41 PCI_3 3V A11 l A42 GND B11 PRSNT2 B42 PCI SERR 14 A43 PCI OPT PAR B14 B43 PCI 3 3V A15 PCI OPT RST N A44 PCI OPT AD15 B15 GND B44 PCI OPT CBE N1 A16 A
35. 24 78 3 3 V 107 118 POI 2 39 25 79 I2C SDA 119 C PULS 40 C FN 26 80 I2C_SCL 120 Legend power signals purple expansion bus signals green common future expansion signals blue UG Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 65 Li IXDP465 Baseboard Hardware Design ntel 3 9 3 Note September 2005 66 Legend Continued 2 expansion signals black SPI signals red 2 signals gold GPIO signals maroon Mil 2 Mezzanine Cards The following features have been designed into the IXDP465 platform interface standard connector for the MII 2 mezzanine card Connector part number Amp 5 179010 5 Pin out similar to that used on the IXDP425 development platform Connection to MII on NPE A Uses expansion bus chip select 7 Uses expansion bus ready 2 The mezzanine card expansion connector contains the following signal groups XP465 SPI IXP465 PC XP465 extended expansion bus 16 GPIO Mezzanine card ID byte for stacking 32 pins for future expansion common to all mezzanine cards 17 pins for future expansion dedicated to this mezzanine card Additional power The IXDP465 platform MII 2 standard connector signal definition is described in Table 38 The power signals are 2 5 V 3 3 V 5 0 V and 12 0 V The expansion bus signals provide the 16 LSB of the data bus the 24 LSB of the addre
36. 9 46 GND 86 EX DATA19 T EX_BE_N3 47 C_FN_59 87 EX_DATA18 8 EX BE N2 48 C_FN_60 88 GND 9 EXBEN 49 29 Intel IXDP465 Development Platform User s Guide UG intel Table 81 UG Mezzanine Card Hardware Design Stacking Interface Expansion Connector Signals Sheet 2 of 2 Signal Pin Signal Pin Signal Pin GND 10 EX BE NO 50 C FN 62 90 EX DATA21 11 EX BURST 5il GND 91 EX DATA20 12 EX 52 GND 92 EX_DATA23 13 EX_PAR2 53 C_FN_63 93 EX_DATA22 14 EX_PAR1 54 GPIO5 94 GND 15 EX_PARO 55 GPIO6 95 GND 16 C NPE 0 56 GPIO7 96 EX DATA25 17 C NPE 1 57 GND 97 EX_DATA24 18 C_NPE 2 58 GND 98 EX_DATA27 19 C_NPE 3 59 GPIO8 99 EX_DATA26 20 C_NPE_4 60 GPIO9 100 GND 21 C NPE 5 61 GPIO10 101 GND 22 C NPE 6 62 GPIO11 102 EX DATA29 23 C_NPE 7 63 GND 103 EX_DATA28 24 C NPE 8 64 GND 104 EX DATAS1 25 C NPE 9 65 GPIO12 105 EX DATASO 26 C NPE 10 66 GPIO13 106 GND er C NPE 11 67 GPIO14 107 GND 28 C NPE 12 68 GPIO15 108 EX ADDR24 29 GND 109 SSPS CLK 30 C FN 48 70 GND 110 SSPS FRM 31 C FN 49 71 111 SSPS TXD 32 C FN 50 72 IDO 112 SSPS RXD 33 C FN 51 73 ID1 113 SSPS EXTCLK 34 C FN 52 74 ID2 114 5 0 V 35 C_FN_53 75 ID3 115 5 0 V 36 C_FN_54 76 ID4 116 G POLO 37 C FN 55 77 ID5 Mig POI 3 38 C FN 56 78 ID6 118 G POI 2 39 C FN 57 79 2 SDA 119 G POL S 40 C FN 58 80 I2C_SCL 120 L
37. 95 EX ADDR6 16 GND 56 EX DATA15 96 EX ADDR7 17 EX PARO 57 EX DATA16 97 EX ADDR8 18 EX PAR1 58 EX DATA17 98 EX ADDR9 19 GND 59 EX DATA18 99 EX ADDR10 20 EX PAR2 60 EX DATA19 100 EX ADDR11 21 EX PARS3 61 EX DATA20 101 EX ADDR12 22 GND 62 EX DATA 21 102 EX ADDR 13 23 EX REQ N1 63 EX DATA22 103 EX ADDR14 24 EX REQ N2 64 EX DATA23 104 EX ADDR15 25 GND 65 EX DATA24 105 EX ADDR16 26 EX REQ N3 66 EX DATA25 106 EX ADDR17 27 EX REQ GNT N 67 EX DATA26 107 EX ADDR18 28 2 5 V 68 EX DATA27 108 EX_ADDR19 29 2 5 V 69 EX DATA28 109 EX_ADDR20 30 EX_GNT_N1 70 EX_DATA29 110 EX_ADDR21 31 EX_GNT_N2 71 EX_DATA30 111 EX_ADDR22 32 45 0 V 78 EX_DATA31 112 EX_ADDR23 33 45 0 V 73 EX BE NO 113 EX ADDR24 34 EX_GNT_N3 74 1 114 EX_WR_N 35 EX_GNT_REQ_N 75 EX BE N2 115 EX RD N 36 GND 76 EX BE N3 116 EX CS NO 37 EX CS N4 77 3 3 V 117 Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 105 Network Processor Module Hardware Design Table 72 4 1 5 Table 73 September 2005 106 intel IXP465 Network Processor Module Expansion Bus Connector Signals Sheet 2 of 2 NPE and Peripheral Connector Signal Pin Signal Pin Signal Pin EX CS N1 38 EX CS N5 78 3 3 V 118 EX CS N2 39 EX CS N6 79 43 3 V 119 EX CS N3 40 EX CS N7 80 3 3 V 120 Legend power signals purple expansion bus signals green The NPE and Peripheral connector cont
38. A29 20 A59 3 3 V B29 PCILHST_AD21 B59 3 3 V A30 GND A60 PCILHST_REQ64_N2 B30 PCI HST AD19 B60 PCI HST ACK64 2 A31 PCI AD18 A61 5 0V B31 33V B61 5 0V A32 PCI AD16 A62 5 0V B32 PCI HST AD17 B62 5 0V For PCB designs that use PCI Host slots the following Host slot 2 signals need pull up resistors attached PCI_LHST_TMS2 PCI TDI2 PCI HST SMBCLK2 PCI SMBDAT2 PCI HST REQ64 2 PCI PRSNT2 PCI PRSNT2 PCI REQ PCI HST M66EN2 PCI 64 2 For PCB designs that use PCI Host slots the following Host slot 2 signals need pull down resistors attached PCI TRST 2 PCI HST TCK2 Table 13 PCI Host Slot 3 Pin Assignments Sheet 1 of 2 Pin Signal Pin Signal Pin Signal Pin Signal A1 PCI N3 3 3 B1 PCI 12V B33 HST CBE 2 A2 12 0 V A34 PCI HST FRAME B2 PCI HST TCK3 B34 GND A3 PCI_HST_TMS3 A35 GND B3 GND B35 PCILHST_IRDY_N A4 PCI_HST_TDI3 A36 PCILHST_TRDY_N B4 PCI_HST_TDO3 B36 3 3 V A5 5 0V A37 GND B5 5 0 V B37 PCI DEVSEL A6 HST INTAN 8 POL HST STOP B6 50 B38 GND UG Inte IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 September 2005 31 IXDP465 Baseboard Hardware Design n Table 13 PCI Host Slot 3 Pin Assignment
39. A41 PCI SMBDAT1 B9 PCI PRSNT1 N1 41 3 3V A10 3 3 A42 GND B10 B42 PCILHST_SERR_N 11 43 PCILHST_PAR B11 PCILLHST_PRSNT2_N1 BA3 3 3V A14 A44 PCI_HST_AD15 B14 B44 PCI HST CBE 1 A15 PCILHST_RST_N A45 3 3V B15 GND B45 PCILHST_AD14 A16 3 3V A46 PCILHST_AD13 B16 PCILHST_CLK1 B46 GND A17 PCI N1 47 PCI HST AD11 B17 GND B47 PCI HST AD12 A18 GND A48 GND B18 PCI HST 1 B48 PCI HST AD10 A19 49 PCI AD9 B19 3 3V B49 PCI M66EN1 A20 PCI HST AD30 A50 GND B20 PCI AD31 B50 GND UG Inte IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 September 2005 29 IXDP465 Baseboard Hardware Design Intel Table 11 PCI Host Slot 1 Pin Assignments Sheet 2 of 2 Pin Signal Pin Signal Pin Signal Pin Signal 21 3 3V A51 GND B21 PCILHST_AD29 B51 GND A22 PCI_HST_AD28 A52 B22 GND B52 PCI_HST_AD8 A23 PCILHST_AD26 A53 3 3V B23 PCILHST_AD27 B53 PCILHST_AD7 A24 GND A54 PCILHST_AD6 B24 PCILHST_AD25 B54 33V A25 PCILHST_AD24 A55 PCILHST_AD4 B25 3 3 V B55 PCI AD5 A26 PCI IDSEL1 A56 GND B26 PCI CBE B56 PCI A27 3 3V A57 PCI HST AD2 B27 PCI HST AD23 B57 GND A28 PCI HST AD22 58 PCI
40. AD19 B60 PCI HST ACK64 N3 A31 PCI HST AD18 A61 5 0V B31 33V B6 50V A32 PCI HST AD16 A62 5 0V B32 PCI HST AD17 B62 50V September 2005 32 For PCB designs that use PCI Host slots the following Host slot 3 signals need pull up resistors attached PCI PCI HST TDI3 PCI HST SMBCLK3 PCI SMBDAT3 PCI HST REQ64 N3 PCI HST PRSNT3 N PCI PRSNT2N PCI HST REQ PCI M66EN3 PCI HST ACK64 N3 For PCB designs that use PCI Host slots the following Host slot 3 signals need pull down resistors attached PCI HST TRST N38 PCI HST Inte IXDP465 Development Platform User s Guide UG Order Number 306462 Revision 004 In IXDP465 Baseboard Hardware Design 3 2 5 PCI Option Mode Operation In PCI option mode the IXDP465 baseboard is plugged into a standard PCI backplane through a card edge connection on the board When the IXDP465 baseboard is an Option device the PCI slots and all associated circuitry are not accessible The isolation buffers are tri stated and do not allow access to the four PCI host slots Isolation buffers are placed between the IXP465 network processor and the PCI fingers to allow for support of Universal PCI A mini PCI interface is achieved through a PCI to miniPCI adapter card to allow capabilities such as wireless LAN for example 802 11 a or b PCI version
41. Clock Control CPLD PCI LEDs There are four LEDs that indicate the PCI status on the IXDP465 platform Table 68 shows what each one means when it is on LED control is performed by the Clock Control CPLD based on PCI mode and Host Clock Frequency When in PCI Option mode the only LED illuminated is the OPTION MODE LED In Host mode two of the final three will be illuminated the HOST MODE LED and either the 33 MHz LED or 66 MHz LED See Figure 14 on page 82 for the LED location LED Definitions LED LED Indication When ON Color PCI Host PCI is in host mode Green PCI Option PCI is in option mode Green PCI 66 MHz PCI is 66 MHz host mode only Green PCI 33 MHz PCI is 33 MHz host mode only Green Mechanical Guidelines The IXDP465 platform fits in a PCI chassis The board height is not restricted to PCI standard While the board can plug into a full size PCI slot the cover does not have to fit and the adjacent slots do not have to be usable i e the board can violate the board to board spacing restrictions of PCI Environmental Guidelines The IXDP465 platform complies with the environmental conditions defined in Table 69 Inte IXDP465 Development Platform User s Guide UG Order Number 306462 Revision 004 I n IXDP465 Baseboard Hardware Design Table 69 Environmental Ranges Temperature Humidity Range Range As Measured From 2 pue tam Measured from the component with the mo
42. EX DATA18 8 EX BE N2 48 C FN 28 88 Inte IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 UG I ntel IXDP465 Baseboard Hardware Design Table 37 MII 1 Mezzanine Card Expansion Connector Signals Sheet 2 of 2 Signal Pin Signal Pin Signal Pin GND 9 EX_BE_N1 49 C_FN_29 89 GND 10 EX_BE_NO 50 C_FN_30 90 EX_DATA21 11 EX_BURST 51 GND 91 EX DATA20 12 EX PAR3 52 GND 92 EX DATA23 13 EX PAR2 53 C FN 31 93 EX DATA22 14 EX PAR1 54 MII1 GPIO5 94 GND 15 EX PARO 55 GPIO6 95 GND 16 C NPE 0 56 MII1_GPIO7 96 EX_DATA25 17 C_NPE_1 57 GND 97 EX_DATA24 18 C_NPE_2 58 GND 98 EX_DATA27 19 G NPE 3 59 GPIO8 99 EX DATA26 20 C NPE 4 60 GPIO9 100 GND 21 C NPE 5 61 MII1 GPIO10 101 GND 22 C NPE 6 62 GPIO11 102 EX DATA29 23 G NPE 7 63 GND 103 EX_DATA28 24 C_NPE_8 64 GND 104 EX_DATA31 25 C_NPE_9 65 MII1_GPIO12 105 EX_DATA30 26 C_NPE_10 66 MII1_GPIO13 106 GND 27 C_NPE_11 67 MII1_GPIO14 107 GND 28 C_NPE_12 68 MII1_GPIO15 108 EX_ADDR24 29 GND 109 SSPS_CLK 30 C_FN_16 70 GND 110 SSPS_FRM 31 C_FN_17 71 GND IDO 111 SSPS_TXD 32 C_FN_18 72 3 3 V ID1 112 SSPS RXD 33 C FN 19 73 3 3 V ID2 113 SSPS EXTCLK 34 C FN 20 74 2 9 V IDS 114 50 35 FN 21 75 3 3 V 104 115 5 0 V 36 C_FN_22 76 3 3 V ID5 116 C PCI 0 37 C FN 23 77 3 3 V ID6 117 1 38
43. EX DATA19 7 EX BE 47 87 EX_DATA18 8 EX_BE_N2 48 88 GND 9 EX_BE_N1 49 89 GND 10 EX_BE_NO 50 90 EX_DATA21 11 EX_BURST 51 GND 91 EX_DATA20 12 EX_PAR3 52 GND 92 EX_DATA23 13 EX_PAR2 53 es 93 EX DATA22 14 EX PAR1 54 GPIO5 94 Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 21 Intel IXDP465 Development Platform Overview Table 6 September 2005 22 Mezzanine Card Expansion Connector Common Signals Sheet 2 of 2 In Signal Pin Signal Pin Signal Pin GND 15 EX_PARO 55 MCE_GPIO6 95 GND 16 C_NPE 0 56 MCE_GPIO7 96 EX_DATA25 17 C_NPE_1 57 GND 97 EX_DATA24 18 C_NPE_2 58 GND 98 EX_DATA27 19 C_NPE_3 59 MCE_GPIO8 99 EX_DATA26 20 C_NPE_4 60 MCE_GPIO9 100 GND 21 C_NPE_5 61 MCE GPIO10 101 GND 22 C NPE 6 62 MCE GPIO11 102 EX DATA29 23 C NPE 7 63 GND 103 EX DATA28 24 C NPE 8 64 GND 104 EX DATA31 25 C NPE 9 65 MCE GPIO12 105 EX DATA30 26 C NPE 10 66 MCE GPIO13 106 GND 27 C_NPE_11 67 MCE_GPIO14 107 GND 28 C_NPE_12 68 MCE_GPIO15 108 EX_ADDR24 29 CLK32 69 GND 109 SSP_CLK 30 70 GND 110 SSP_FRM 31 71 ID0 111 SSP_TXD Bg 72 ID1 112 SSP_RXD 33 73 2 113 SSP_EXTCLK 34 74 ID3 114 45 0 V 35 75 ID4 115 5 0 V 36 76 ID5 116 C PCI 0 37 77 ID6 117 PCI 1 38 78 ID7 118 C PCI 2 39 79 I2C_SDA 119 C_PCI_3 40 80 2 SCL 120 Legen
44. Guide September 2005 Order Number 306462 Revision 004 49 Li IXDP465 Baseboard Hardware Design ntel 3 7 1 Figure 8 3 7 2 Note September 2005 50 disabled To exercise all six ports of Ethernet the proper configuration of NPE functions must be selected through proper software programming of fuse bits in the EXP UNIT FUSE RESET register immediately after reset For information about the possible NPE function configurations see the Intel IXP45X and Intel IXP46X Product Line of Network Processors Developer s Manual Multi Gang Jack The IXDP465 platform contains a 6 port RJ 45 gang jack Pulse Engineering part number J8064D668A with integrated magnetics Each port has two LEDs one green one yellow controlled by the PHY The software programs the PHY through the MII interface to illuminate the LEDs according to certain events such as activity half full duplex 10 100 MHz etc Figure 8 shows the integrated magnetics within the gang jack RJ 45 Jack with Integrated Magnetics RX 10 O1 Rx e 40 z GREEN RX 20 RX 1CT 1CT 9 gt RECEIVE LEFT LED Txt 36 O3 T 0 e cr 50 C 2 YELLOW e 11 Tx 6 Q6 x RIGHT 1CT 1CT LED ow _ TRANSMIT 15 in 9 4 75 70 Z ww 5 s V 7 0 001UF 75 80 1 e WA Og SMII PHY Connection The IXDP465 platform co
45. HST 28 GND B58 PCILHST_AD1 A29 20 59 3 3 B29 PCI 21 B59 33V A30 GND A60 PCI_LHST_REQ64_N1 B30 PCI HST AD19 B60 PCI 64 1 A31 PCILHST_AD18 A61 5 0V B31 33V B61 5 0 V A32 PCILHST_AD16 A62 5 0 V B32 PCI HST AD17 B62 5 0V For PCB designs that use PCI Host slots the following Host slot 1 signals need pull up resistors attached PCI_HST_TMS1 PCI HST TDH PCI SMBCLK1 PCI SMBDAT1 PCI REQ64 1 PCI HST PRSNT1 N PCI HST PRSNT2 N PCI HST REQ 1 PCI HST M66EN1 PCI ACK64 N1 For PCB designs that use PCI Host slots the following Host slot 1 signals need pull down resistors attached PCI HST TRST PCI HST TCK1 Table 12 PCI Host Slot 2 Pin Assignments Sheet 1 of 2 Pin Signal Pin Signal Pin Signal Pin Signal Ai PCILHST_TRST_N2 A33 3 3V B1 PCI_ 12V_N2 B33 PCI HST CBE N2 A2 12 0 V A34 PCI HST FRAME N B2 PCI HST TCK2 B34 GND A3 PCI HST TMS2 A35 GND B3 GND B35 PCI HST IRDY N A4 PCI HST TDI2 A36 PCI HST TRDY N B4 PCI HST TDO2 B36 3 3 5 5 0 V A37 GND B5 5 0 V B37 PCILHST_DEVSEL_N A6 A38 PCI_HST_STOP_N B6 5 0V B38 GND PCI INTC N A39 3 3 V B7 PCI_HST_INTB_N B39 PCI HST LOCK N A8 5 0V A40 PCI HST SMBCLK2 B8 PCI INTD B40 PCI HST A9 A41 PCI SMBDAT2 B9 PCI PRSNT1 2 41 3 3 V A10 33V A42 GND B10 B42 PCI HST SERR A11 43 P
46. IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 UG intel Updating the IXDP465 Flash Memory Updating the IXDP465 Flash Memory A Note Note A 1 UG RedBoot is the primary boot loader and it is used to boot Linux plus some other sections of flash that are populated with bootrom for VxWorks RedBoot is also used to update RedBoot The IXDP465 platform ships with RedBoot v2 01 installed It reports its version as follows RedBoot tm bootstrap and debug environment ROM Red Hat certified release version 2 01 built 08 07 53 Feb 22 2005 Platform IXDP465 Development Platform XScale BE Copyright C 2000 2001 2002 2003 2004 Red Hat Inc Once you have the IXDP465 platform running with your OS set up and running you may want to organize the flash content for your particular design Leaving the RedBoot image in place is recommended A host system connects through a network or serial port to provide the images The procedures in this section assume that you have a host system set up to support loading images from a TFTP server Host system setup and installation are beyond the scope of this document For detailed information about using the RedBoot v2 01 software and host system requirements see the Intel IXP400 Software RedBoot v2 01 Software Release Notes This appendix provides the following procedures needed to maintain the boot images in flash Updating flash
47. OPT JP3 jumpers can optionally be installed all 16 jumpers IN to enable NPE A UTOPIA Mode with NPE A MII Mode disabled September 2005 Intel IXDP465 Development Platform User s Guide UG 56 Order Number 306462 Revision 004 intel 3 8 4 Table 31 IXDP465 Baseboard Hardware Design NPE B MII Jumper Block JP4 The IXP465 network processor contains NPE pins that have multiple functions The NPE B MII jumper block connects specific shared NPE signals to the MII NPE B mezzanine card Table 31 shows the pin definitions for the NPE B MII jumper block as well as the JP4 jumper pin assignments which depend on the SMII Configuration CFG selected in Table 27 To find the location of JP4 on the IXDP465 baseboard see Figure 11 NPE B MII Jumper Block JP4 Pin Assignments JP4 Pin Network Processor JP4 Signal Pin CFG CFG CFG CFG CFG CFG CFG CFG MII Signal 1 2 3 4 5 6 7 8 C_ETHB_TXCLK 2 ETHB_TXCLK OPT OPT OPT aas C_ETHB_TXDATAO 4 ETHB_TXDATAO OPT OPT OPT OPT see ud C ETHB TXDATA1 6 ETHB TXDATA1 OPT OPT OPT OPT Ed m C ETHB TXDATA2 8 ETHB TXDATA2 OPT OPT OPT OPT N oa C_ETHB_TXDATA3 10 ETHB_TXDATA3 OPT OPT OPT ae ses un 11 C ETHB RXDATAO 12 ETHB RXDATAO OPT OPT OPT s C ETHB RXDATA1 14 ETHB RXDATA1 OPT OPT OPT OPT
48. Pin Signal Pin Signal Pin UTP_OP_ADDR0 22 GND 62 102 UTP OP ADDR1 23 UTP IP DATA2 63 SSP FRM 103 UTP OP ADDR2 24 UTP DATA3 64 SSP TXD 104 UTP OP ADDRS3 25 GND 65 SSP RXD 105 UTP ADDR4 26 UTP IP DATA4 66 SSP EXTCLK 106 ETH MDC 27 DATA5 67 ETH MDIO 28 2 5 V 68 ETHC_TXEN 29 2 5 V 69 ETHC_RXDATAO 30 UTP_IP_DATA6 70 ETHC_RXDATA1 31 UTP_IP_DATA7 71 ETHC_RXDATA2 32 5 0 V 72 ETHC_RXDATA3 33 5 0 V 78 ETHC_RXDV 34 ETHB_TXCLK 74 ETHC_COL 85 ETHB_RXCLK 75 ETHC_CRS 36 GND 76 ETHC_TXDATAO 37 ETHB_TXDATAO 77 3 3 V 117 ETHC_TXDATA1 38 ETHB TXDATA1 78 43 3 V 118 ETHC_TXDATA2 39 ETHB_TXDATA2 79 3 3 V 119 ETHC_TXDATA3 40 ETHB_TXDATA3 80 3 3 V 120 Legend power signals purple MII signals green HSS signals red I2C signals black SPI signals blue UTOPIA signals gold Future Needs Connector The Future Needs connector contains the power signaling and expansion bus arbitration signals The remaining pins are reserved for future needs and are not routed on this module they will be routed on the IXDP465 platform baseboard to mezzanine card connectors Inte IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 September 2005 107 Network Processor Module Hardware Design Table 74 September 2005 108 In IXP465 Network Processor Module Future Needs Connector Pin Definitions Sheet
49. Signal Pin Signal N8 GND A6 TAVD11 D7 GND C11 TAVD12 A9 GND T6 TAVD13 N7 GND P11 TAVD14 R9 GND A4 A5 TAVD21_TAVD31 D6 GND D13 C12 TAVD22 TAVD32 B10 GND T4 T5 TAVD23_TAVD33 N6 GND P13 P12 TAVD24 TAVD34 R10 GND N9 CAVD D9 GND B8 B7 RAVD11_RAVD21 T14 GND B9 A10 RAVD12_RAVD22 G1 2 5 V R8 R7 RAVD13_RAVD23 H3 2 5 V T9 T10 RAVD14_RAVD24 J 2 5V C8 QAVD1 L1 2 5 V R14 QAVD1 Transmit Analog Power Decoupling 1 3 3V TAVD1 lt X gt Cl C2 0 01uF 0 1uF Inte IXDP465 Development Platform User s Guide UG Order Number 306462 Revision 004 intel Figure 42 Figure 43 UG Mezzanine Card Hardware Design Receive Analog Power Decoupling 1 and 2 N T 0 01uF 7 47uF 3 3V RAVD1 lt X gt _RAVD2 lt X gt m 4 AV R1 1 0 01 C2 T 0 01uF 0 1uF Transmit Analog Power Decoupling 2 and 3 3 3V TAVD2 lt X gt _TAVD3 lt X gt T R1 1 0 Inte IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 September 2005 157 Mezzanine Card Hardware Design Figure 44 5 4 5 4 September 2005 158 Quiet Analog Power Decoupling QAVD lt X gt CAVD 0 01uF zw 22uF 3 3V R1 4 7 3 3V AA R1 4 7 Clock Interface The Comet Quad Framer LIU is designed to operate in either T1 or E1 mode A 1 544 MHz oscillator circuit is the interface to the Quad Framer device clock input for T1 operation A 2 048 MHz oscil
50. Speed Mode is not supported Three Network Processor Engines NPEs DDRI SDRAM interface Up to three MII interfaces Master target capable expansion bus Up to six SMII interfaces Two UARTs One UTOPIA Level 2 interface Internal Bus Performance Monitoring Unit IEEE 1588 Hardware Assist 16 GPIOs Four internal timers Synchronous Serial Protocol SSP port interface Spread spectrum clocking for reduced EMI Packaging 544 pin PBGA Commercial extended temperature Lead free support It is recommended that users have access to the documents listed in Table 2 and refer to them when necessary This document does not explore the 465 network processor internal architecture but describes the processor s interfaces to peripherals that are used on the IXDP465 platform Schematics and a bill of materials are available in the IXDP465 platform documentation kit zip file at http developer intel com design network products npfamily ixdp465 htm or through your local Intel sales representative Related Documentation Table 2 and Table 3 list documentation from Intel and from other sources that provide additional information for the development of hardware and software based on the Intel Processor IXP465 Network Inte IXDP465 Development Platform User s Guide UG Order Number 306462 Revision 004 In Table 2 Table 3 UG Inte IXDP465 Development P
51. Standard Connector 59 MII 0 Mezzanine Card Expansion Connector 61 MII 1 Mezzanine Card Standard Connector 63 MII 1 Mezzanine Card Expansion Connector Signals 64 MII 2 Mezzanine Card Standard Connector 67 MII 2 Mezzanine Card Expansion Connector Signals 68 USB Device Connector Pin Definition a a 70 USB Host Connector Pin Definition sess nnns 70 Serial Port DB 9 Connector Pin Definitions a 71 Serial Port DB 9 Modem Signal Alternate Functions sse 71 Serial Port ResIStOre eee baee ceti e cud det erase 72 Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 T Contents ntel 45 GPIO Header Pin Definition aa 73 46 GPIO FPGA Access Registers nn 73 47 GPIO FPGA Access Signals hte nter it eei E x na 74 48 GPIO FPGA Configuration Register Bit 76 49 GPIO FPGA Direction Bit Definition U 76 50 GPIO FPGA Attach Values and FPGA Pin Assignments 76 51 Alternate GPIO F nctioniSu ett sedeat rd taz gu Ere et e
52. The UTOPIA level 2 and Expansion Bus signals are routed to this connector to allow a variety of DSL PHY modules to be configured including PHY modules from the IXDP425 development platform See Table 75 on page 113 for the connector pin definitions All IXP465 network processor engine NPE functions require Intel supplied software For information about using this software see the Intel IXP400 Software Programmer s Guide For information about the availability of this enabling software contact your Intel sales representative Table 21 lists the pull up resistors used on the UTOPIA level 2 interface These signals are IXP465 network processor signals that must not be left floating when a module is not plugged into the connector The 10 KQ resistor value was chosen so that a DSL module can easily over drive the signal state provided by the pull up Decoupling is handled on each module Inte IXDP465 Development Platform User s Guide UG Order Number 306462 Revision 004 I ntel IXDP465 Baseboard Hardware Design Table 21 UTOPIA Level 2 Resistors Signal Pull to Value Resistor Value UTP_OP_CLK 3 3 V 10 KQ UTP_IP_CLK 3 3 V 10 KQ UTP_IP_DATA 7 0 3 3 V 10 KQ UTP_IP_FCI 3 3 V 10 KQ UTP_IP_SOC 3 3 V 10 KQ UTP_OP_FCI 3 3 V 10 KQ UTP_OP_FCO 3 3 V 10 KQ UTP_IP_FCO 3 3 V 10 KQ 3 6 HSS Connectors The IXDP465 platform implements two sets of connectors dedicated to HSS devices The HSS
53. V 5 0 V and 3 3 V 2 2 5 V 3 1 3 V 1 5 V 1 5 V for IXP465 network processor operating at 667 MHz only The only power sequencing requirement on the board comes from the IXP465 network processor which requires that 3 3 V and 2 5 V comes up before 1 3 V 1 5 V This voltage is generated on the network processor module When the IXDP465 platform is the host PCI system power must be provided by an external power supply connected to the platform plug connection When the IXDP465 baseboard is used as an option card in a PCI system power is still provided by the external module eliminating complications generated by the PCI 25W limitation The 1 3 V 1 5 V core voltage required by the IXP465 network processor has been designed directly onto the IXDP465 platform network processor module 1 3 V 1 5 V is generated from 3 3 V using the National Semiconductor LP3966ES ADJ power regulator To meet the overall power requirements the IXDP465 platform uses an external ATX supply Table 57 depicts the IXDP465 platform s typical power distribution although mezzanine cards can draw more power as long as the total system wattage does not exceed 180W If needed a higher wattage supply can be purchased separately IXDP465 Development Platform Power Distribution Peripheral Power Dissipation max Host PCI Slot 0 25W Host PCI Slot 1 25W Host PCI Slot 2 25W Host PCI Slot 3 25W Network Processor module 3
54. Where INIT_N is an active low input output RO write has no effect 0 FPGA initializing internal resources after PROG_N active 1 Normal Operation 3 Where INIT N is an active high input output RO write has no effect 0 Programming not complete 1 Programming complete 3 22 1 1 GPIO FPGA Chip Select The GPIO FPGA Chip Select is a pass through active low chip select that is generated when the proper address range is accessed on the expansion bus 3 22 1 3 LCD Display Instruction Register The LCD Display Instruction is a Write Only register that sends commands such as Reset Blank Display Position Cursor etc to the LCD display After each write of the display the Control Status register LCD TIME bits must be monitored before the next command is sent to the LCD display Refer to the Seiko 1 1672 LCD display Model L167200J00 data sheet for programming information 3 22 1 4 LCD Display Data Register The LCD Display Data is a Write Only register that sends alpha numeric character data to the LCD display After each write of the display the Control Status register LCD TIME bits must be monitored before the next display data is sent to the LCD display Refer to the Seiko L1672 LCD display Model L167200J00 data sheet for programming information 3 22 2 Expansion Bus Address Switch Configuration Overrides The clock control CPLD overrides the user selectable switches attached to the expansion bus to ensure that the har
55. a uu aa eana aaea aaa nnns 87 3 19 3 Monitoring Core Voltage Current 1 3 V 41 5 87 3 20 Reset LO ien eerie rec pce Eun co vo oe vao E Cn neut Lug xn 87 3 21 88 3 22 Clock Control CPLD uu 89 3 22 58 D uu a saka awkis 89 3 22 1 1 CPLD Internal Registers 0 44 4040 90 3 22 1 2 GPIO FPGA Chip 92 3 22 1 3 LCD Display Instruction 92 3 22 1 4 LCD Display Data 92 3 22 2 Expansion Bus Address Switch Configuration Overrides 92 3 22 3 PCI Host Clock Generation n n 93 3 22 4 PCI Sensing cere Benet in ee t ad 93 3 22 5 PCI Isolation Buffer 94 9 22 06 POLEEDS ie ire ret et ha qaqaqa evtes Exe Hoa ua Eee da ua d 94 3 23 Mechanical 94 3 24 Environmental 94 3 25 Regulatory Guidelines r 95 4 Network Processor Module Hardware 2 24 2 1 97 4 1
56. applied on D USB pin to indicate the IXDP465 baseboard is a full speed USB device This pull up is enabled disabled through software control The USB design is identical to that on the IXDP425 IXCDP1100 platform Table 40 shows the USB device connector pin definition USB Device Connector Pin Definition USB Device J8 Signal 1 5 0V_USB input 2 USB_DNEG 3 USB_DPOS 4 GND The IXDP465 baseboard cannot be powered as a downstream device through the USB interface due to the board s high power requirements The interface is capable of operation at 1 5 Mbits s and 12 Mbits s USB Host A Type A USB host receptacle is provided at the board edge The USB host interface is compliant with USB 2 0 Table 41 shows the USB host connector pin definition USB Host Connector Pin Definition USB Device J7 Signal 1 5 0V USB output 2 USB HNEG 3 USB HPOS 4 GND The interface is capable of operation at 1 5 Mbits s and 12 Mbits s Serial Ports Two dedicated asynchronous serial I O ports UARTs with flow control are provided Both ports are routed to 9 pin DB connectors with RTS and CTS flow control Both serial ports include support for full modem control through four GPIOs The interface supports baud rates of 1200 to 921 6 Kbits s The ports are wired according to the RS 232 specification for data communication equipment Straight serial cable connects to the host PC Table 42 sho
57. are valid when full modem control is not used Since the transceiver inverts its inputs the DSR RI and DCD signals are de asserted active high when they are driven through the connector Table 44 shows the serial port resistor signals and values Serial Port Resistors Signal Pull to Value Resistor Value URT_CTSO_N None None URT_CTS1_N None None URT_RXDO None None URT_RXD1 None None URT_DSRO 3 3 V 10 KQ URT DSR1 43 3 V 10 KQ URT RIO 43 3 V 10 KQ URT_RI1 3 3 V 10 KQ URT_DCDO 3 3 V 10 KQ URT_DCD1 3 3 V 10 KQ URT_DTRO None None URT DTR1 None None GPIO The GPIOs are mapped to many purposes on the IXDP465 platform An FPGA routes GPIO to I O any GPIO to any I O or interrupt signals for all peripherals eliminating the need for jumpers This FPGA places the routing of signals to all 16 GPIOs under software control Any I O from the mezzanine cards or onboard peripherals is routed internally by the FPGA through software control to any of the GPIOs Each GPIO has a green LED indicator attached to it which when illuminated indicates a low state 0 VDC The LEDs are shown in Figure 14 on page 82 DIP switches are placed on each LED to allow the LED to be disconnected from the GPIO and reduce loading See Figure 7 on page 37 for the DIP switch locations The default setting for these switches is LEDs illuminated ON position GPIO15 is a user programmable output with the default stat
58. circuit that generates the core voltage is shown inFigure 19 Note Figure 19 is provided for reference only For greater detail see the schematics files in the Intel IXDP465 Development Platform Documentation Kit September 2005 Inte IXDP465 Development Platform User s Guide UG 100 Order Number 306462 Revision 004 In Figure 19 Note UG Network Processor Module Hardware Design IXP465 Core Voltage Generation Logic 3 3V v 1602 VRI LP3966ESX ADJ e COREV VIN 1 w 4 gt COREV R605 COREV_SD_N p 102055 peoo 0018 10 GROUND 10 10 Mew Os COREV ADJR E C174 R466 Wt JPAB Yw JP48 CORE VOLTAGE k 1 x COREVADJ i N 13V R606 EN 10K 15V 3 3V_IXP Y mL LA VCC 38 x 1 eo Reser srt 1 SRT O38 C13 R463 soms 680PF AUF 10 7K 30 10 M9 U24 MAX6423 ENSURES THAT THE 3 3V RAIL HAS STABILIZED BEFORE THE COREV STABILIZES U22 ate alt L MAX6423 ENSURES THAT THE 2 5V RAIL HAS STABILIZED BEFORE THE COREV STABILIZES EACH RAIL MUST BE POWERED UP 1USEC BEFORE THE CORE VOLTAGE COREV 2 5V_IXP Y C173 AND C245 MUST BE CALCULATED FOR EACH APPLICATION USING THE FOLLOWING FORMULA CSRT 27506 273 X 106 WHERE ua IS IN SECONDS AND CSRT IS IN FARADS anew MAX6423 A veo Vcc_25 4 4 RESET sm 3 SRT_25 C245 C246 465 ws 680PF AUF
59. connectors support the HSS interfaces The first connector of this connector pair is the same connector physically and in pinout that is supported on the IXDP425 IXCDP1100 platform for compatibility with previous platform versions The second connector provides for increased expansion bus capability on the IXP465 network processor The primary HSS interface for the HSS 0 connector is HSS0 with HSS1 as the secondary alternate HSS interface This arrangement allows for stacking up to eight mezzanine cards using reserved pins on the IXDP465 interface standard connector The primary HSS interface for the HSS 1 connector is HSS1 with HSSO as the secondary HSS interface This connector supports the following mezzanine cards using the HSS interface IXPVM465 Analog Voice mezzanine card 4 FXS 1 e XPFRMA65 Quad mezzanine card Note Although previous platforms have combined the HSS and UTOPIA interfaces on one connector the IXDP465 platform separates the interfaces to allow more flexible configuration options The mezzanine card connector Amp 179031 5 has been designed to accommodate the signals needed for these supported devices The expansion bus is routed to the connector for a control interface Both HSSO and HSS signals are routed to this connector The expansion bus signal pinout on the connector is the same as on the MII connector to provide an option for designing an HPI module to fit on either connector Table
60. gt o o gt 1 e gt D amp 5z s 6 uu lt 5 m lt w Sele e om lt lt 2 z 7 5 9 a lt lt Processor 2 2 u 5 E 2 5 e 2 u S S S Intel IXP465 533 MHz Intel IXP460 533 MHz 1 1 1 Intel IXP455 533 MHz 1 1 Fuse Bit Numbert 23 22 21 20 19 18 17 16 1310 9 8 7 6 5 4 3 2 1 0 T Available to software via EXP UNIT FUSE RESET register 2 3 UG Mezzanine Cards Each IXDP465 mezzanine card has two 120 pin connectors associated with it The first connector referred to in this document as the standard connector shares the identical pinout as the mezzanine connector developed for the previous generation IXDP425 platform The standard connector reuses standard signals such as HSS MII Expansion Bus and Status thus allowing the IXDP425 mezzanine cards to directly plug into the new IXDP465 platform Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 19 Intel IXDP465 Development Platform Overview ntel Note Figure 2 2 4 September 2005 20 The se
61. http www intel com AnyPoint AppChoice BoardWatch BunnyPeople CablePort Celeron Chips CT Media Dialogic DM3 EtherExpress ETOX FlashFile i386 i486 i960 iCOMP InstantlP Intel Intel Centrino Intel logo Intel386 Intel486 Intel740 IntelDX2 IntelDX4 IntelSX2 Intel Create amp Share Intel GigaBlade Intel InBusiness Intel Inside Intel Inside logo Intel NetBurst Intel NetMerge Intel NetStructure Intel Play Intel Play logo Intel SingleDriver Intel SpeedStep Intel StrataFlash Intel TeamStation Intel Xeon Intel XScale IPLink Itanium MCS MMX MMX logo Optimizer logo OverDrive Paragon PC Dads PC Parents PDCharm Pentium Pentium Il Xeon Pentium III Xeon Performance at Your Command RemoteExpress SmartDie Solutions960 Sound Mark StorageExpress The Computer Inside The Journey Inside TokenExpress VoiceBrick VTune and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries Other names and brands may be claimed as the property of others Copyright 2005 Intel Corporation All Rights Reserved September 2005 Intel IXDP465 Development Platform User s Guide UG 2 Order Number 306462 Revision 004 ntel Contents Contents UG Intel IXDP465 Development Platform 22 11 1 1 PUTOS 5 sss sss ass sss 11 1 2 Intended Audience rettet tnt LY d Etat EE ntu uv
62. o o o e e x e x FXS FXO IN PCLK lt gt IN PLD FSYNC lt gt IN 5 DRX lt gt IN DTX Y Y Y Y Y Analog 4x1 IXDP465 Interface Standard Connector ID 00111111 s g ux ux lt 2 o o a a gt lt gt lt gt x tc gt c t 9 75 n 75 L n FXS FXO o OUT PCLK lt e OUT CPLD FSYNC lt OUT DRX lt OUT DIX The IXDP465 platform delivers a 32 768 MHz clock to each of the mezzanine cards on the IXDP465 interface expansion connector CLK32_IN The IXDP425 development platform does not provide a 32 768 MHz clock Therefore an optional 32 768 MHz oscillator circuit that is not populated for the IXDP465 platform Analog Voice mezzanine cards is designed into the Analog Voice mezzanine card Only the first board in the stack uses this and propagates it to the next card in the stack See Section 5 3 5 Analog Voice Card CPLD for further information September 2005 Intel IXDP465 Development Platform User s Guide UG 130 Order Number 306462 Revision 004 In 5 3 4 5 3 4 1 Figure 29 Figure 30 UG Mezzanine Card Hardware Design Analog Voice Card SPI Interface The SPI interface accesses control and status information from the FXO and FXS channels Since the interface is different for FXO and FXS two SPI protocols are used For the IXDP465 platform the d
63. on this connector Table 80 shows the stacking interface standard connector signal definitions The Legend describing the color codes for the signals follows the table Stacking Interface Standard Connector Signals Sheet 1 of 2 Signal Pin Signal Pin Signal Pin 4 1 EX ADDR11 41 5 0V 81 2 EX ADDR10 42 82 3 EX_ADDR13 43 GPIO2 83 4 EX ADDR12 44 GPIO3 84 EX DATA1 5 EX ADDR15 45 GND 85 EX DATAO 6 EX ADDR14 46 GND 86 EX DATA3 7 GND 47 87 EX_DATA2 8 GND 48 GPIO4 88 GPIO0 9 EX_ADDR17 49 89 GPIO1 10 EX_ADDR16 50 EX_DATA5 11 EX_ADDR19 51 91 EX_DATA4 12 EX_ADDR18 52 HSS_TXFRAME1 92 EX_DATA7 13 EX_ADDR21 53 93 EX_DATA6 14 EX_ADDR20 54 HSS_TXCLK1 94 GND 15 EX_ADDR23 55 GND 95 GND 16 EX_ADDR22 56 HSS TXDATA1 96 EX DATAS 17 GND 57 HSS_TXDATAO 97 EX_DATA8 18 GND 58 GND 98 EX_DATA11 19 EX_CLK 59 HSS TXFRAMEO 99 EX DATA10 20 EX RD N 60 HSS RXDATAO 100 21 GND 61 101 22 EX WR N 62 HSS RXFRAMEO 102 EX DATA13 23 EX ALE 63 HSS TXCLKO 103 EX DATA12 24 EX RDY N 64 104 EX DATA15 25 EX IOWAIT N 65 GND 105 EX DATA14 26 INT IN 66 HSS RXCLKO 106 GND ay EX CS N 67 107 GND 28 3 9 V 68 GND 108 EX ADDR1 29 69 HSS RXCLK1 109 EX ADDRO 30 3 3V 70 110 EX ADDR3 31 5 0 V 71 HSS_RXFRAME1 111 Intel IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 125 Mezzanine Card Hardw
64. output clock that is fed to the next board in the stack because all analog ports in the stack must run from the same 32 768 MHz clock to function properly The clock source is controlled by the analog clock source register See IXDP425 IXDP465 Mode Register on page 136 for details I C Interface The CPLD supports Reads only Write is not supported The Board Status register contains detailed information about the board Status Register A typical example of the Status register for the HSS Analog Voice mezzanine card is shown in the table below This example is based on Board ID 4 shown in light gray and board revision 2 shown in dark gray Relay Control The CPLD controls the five relays with the RELAY P signal When the RST N signal is active the CPLD drives RELAY P to an inactive state logic 0 The relays are engaged or disengaged through expansion bus writing of the relay control register See Section 5 3 5 1 Internal CPLD Registers for more information LED Indicators There are five LEDs that indicate the status of each analog port When the port is being held in a Reset under software control the LEDs are not illuminated When the ports are in an active state the LEDs are illuminated Figure 36 shows the LED locations Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 139 Li Mezzanine Card Hardware Design ntel Figure
65. stacking 32 pins for future expansion common to all mezzanine cards 16 pins for future expansion dedicated to this mezzanine card Additional power The IXDP465 platform 55 0 standard interface connector signal definitions are defined in Table 23 The power signals are 2 5 V 3 3 V 5 0 V and 12 0 V The expansion bus signals provide the 16 LSB of the data bus the 24 LSB of the address bus chip select 3 clocking and control to the mezzanine card The interrupt signal from the mezzanine card is routed to the GPIO FPGA The JTAG signals are not used The primary HSS signals are connected to HSS 0 The secondary HSS signals are connected to HSS 1 The GPIO signals route to the GPIO FPGA The Legend describing the color codes for the signals follows the table Inte IXDP465 Development Platform User s Guide UG Order Number 306462 Revision 004 I n IXDP465 Baseboard Hardware Design Table 23 HSS 0 Mezzanine Card Standard Connector Signals Sheet 1 of 2 Signal Pin Signal Pin Signal Pin 1 EX_ADDR11 41 5 0 V 81 2 EX_ADDR10 42 3 3 V 82 3 EX_ADDR13 43 HSS0_GPIO2 83 4 EX_ADDR12 44 HSS0_GPIO3 84 EX DATA1 5 EX_ADDR15 45 GND 85 EX_DATAO 6 EX_ADDR14 46 GND 86 EX_DATA3 if GND 47 87 EX_DATA2 8 GND 48 550 GPIO4 88 550 GPIOO 9 EX ADDR17 49 89 HSSO GPIO1 10 EX ADDR16 50 RST 90 EX DATA5 11 EX ADDR19 51
66. the IXDP465 baseboard for an HSS clock The IXP465 network processor drives the clock at a software programmable frequency out to the HSS mezzanine cards The IXDP465 platform defaults to an external HSS clock source External clocks are placed on the mezzanine cards as the HSS clock source and a 32 768 MHz clock signal propagated by the IXDP465 platform is available to all mezzanine cards for telephony applications Inte IXDP465 Development Platform User s Guide UG Order Number 306462 Revision 004 I ntel IXDP465 Baseboard Hardware Design 3 22 Clock Control CPLD The Clock Control CPLD is used for the following Address Decode for expansion bus chip select 2 CPLD Internal Registers GPIO FPGA Chip Select LCD Display Control Expansion Bus Clock Generation 33 MHz 40 MHz 66 MHz 80 MHz Expansion Bus Address Configuration Switch Overrides PCI Functions Host Clock Generation Option Sensing Isolation Buffer Control LEDs The Clock Control CPLD is pre programmed by the factory with the features defined in this manual A JTAG Header is provisioned on the platform to allow re programming of the CPLD for designs that require customized modes See Figure 15 on page 84 for the header location 3 22 1 Address Decode The Clock Control CPLD uses the upper five address bits of the expansion bus EX_ADDR24 EX_ADDR20 to further divide the address space for expansion bus slot 2
67. the IXPVM465 Analog Voice mezzanine card for address decode Clocking Framing The PCM analog voice bus clocking and framing source is dependent on the board ID The HSS interface on the IXDP465 platform host network processor is used as the communication path for the PCM data Since the HSS internal clock generation has too much jitter for analog applications an external clock is generated by the Analog Voice mezzanine card CPLD along with the frame Only the first of eight maximum mezzanine card drives these signals with the HSS and the rest of the stacked mezzanine cards receiving them Figure 28 shows a PCM interface signal flow drawing Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 129 Mezzanine Card Hardware Design n Figure 28 Analog Voice Card Stacking PCM Interface g x x s s lt lt z a a gt lt gt lt x x gt o x o H a Fi 2 wn 40 75 V5 I FXS FXO r T e 2 IN PCLK lt 1 gt IN PLD FSYNC gt IN DRX lt IN DTX L Y Y Y Y Y ID 00011111 Analog 4x1 Stacking Interface Standard Connector A lt lt x x lt lt a gt lt gt lt x LE F gt m gt e
68. the voltage jumpers location Monitoring 3 3 V Current To monitor the IXP465 network processor s current requirements for a given application perform the hardware modifications described below Intel IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 UG 3 19 2 3 19 3 3 20 UG IXDP465 Baseboard Hardware Design For the 3 3 V rail 1 Remove R443 and R444 from the IXP465 network processor module near the IXP 3 3 V jumper 2 Add a wire loop across the IXP 3 3 V jumper 3 Attach an inductive current probe to the wire loop to measure the current See Figure 17 on page 98 for the IXP 3 3 V jumper location Monitoring 2 5 V Current To monitor the IXP465 network processor s current requirements for a given application perform the hardware modifications described below For the 42 5 V rail 1 Remove R445 and R446 from the IXP465 network processor module near the JP46 IXP 2 5 V jumper 2 Add a wire loop across JP46 3 Attach an inductive current probe to the wire loop to measure the current See Figure 17 on page 98 for the JP46 IXP 2 5 V jumper location Monitoring Core Voltage Current 41 3 V 1 5 V To monitor the IXP465 network processor s current requirements for a given application perform the hardware modifications described below For the core voltage rail 1 Remove R447 and R448 from 465 network processor module near the JP47 IXP COREV jumper
69. to the FXO port connector isolating it from the IXDP465 baseboard FXS and FXO circuitry When power is applied the relays are switched under software control This design is compatible with the IXDP425 development platform The HSS Analog Voice 4x1 mezzanine card plugs into the IXDP465 baseboard through the standard 120 pin connector also used by the IXDP425 development platform The pin out is the same as the HSS connectors on the IXDP425 with the second alternate HSS port being routed to the IXDP425 connector s unused pins allowing the device to be stackable up to eight cards high The stacking connector is physically identical as is the signaling with the exception of routing the alternate HSS port up to the next card A Silicon Laboratories 513210 circuit is used for the FXS solution and a Silicon Laboratories 513050 part is used for the FXO solution A standard four circuit RJ11 gang jack is used for the FXS connectors and a single RJ11 jack is used for the FXO connector The IXDP465 platform achieves control and status of the FXS and FXO ports via the SPI interface GPIO for the IXDP425 development platform the voice interface via the HSS interface Inte IXDP465 Development Platform User s Guide UG Order Number 306462 Revision 004 I ntel Mezzanine Card Hardware Design GPIO is used for hook state control ring indication and interrupts Figure 27 contains the block diagram for this mezzanine card Figure
70. write of clock control CPLD 33 0 MHz 40 0 MHz 66 0 MHz 80 0 MHz Although UTOPIA also requires 33 MHz oscillators a separate oscillator allows the oscillator frequency to be altered or disabled independently The IXDP465 platform contains 33 33 MHz oscillator that is used for test mode only Installation of JP9 and JP11 places a 33 33 MHz signal on both the OP and the IP See Figure 11 for these jumper locations and Table 30 for the JP3 UTOPIA jumper block pin assignments The PCI clock is driven from the PCI option fingers when the IXDP465 platform is in Option mode and is driven by the Clock Control CPLD when the IXDP465 platform is the host The clock is driven through a clock driver in Host mode and clock selection is automatic The core voltage is adjustable with processor speed For example for 667 MHz operations the 667 MHz jumper must be removed See Figure 17 on page 98 for the jumper location The expansion bus clock is generated by the clock control CPLD The frequency of this clock is software selectable The UTOPIA transmit and receive clock is disabled through a jumper option when the clock is driven from the Network Processor Module i e when the IXP465 network processor is acting as the PHY See Figure 11 on page 53 for the jumper location and settings The HSS clocks are sourced either out of the IXP465 network processor from an HSS mezzanine card There is no oscillator on
71. 0 ETHC GPIO14 180 62 550 GPIO14 99 94 DSL INT N 123 126 Reserved n a Not 31 ETHC GPIO15 181 63 HSSO_GPIO15 100 95 Reserved n a 127 Reserved Attached5 Notes 1 PCI_INTA_N is an output from FPGA attached to network processor GPIO11 after reset as PCI Host interrupt 2 PCI_INTB_N is an output from FPGA attached to network processor GPIO10 after reset as PCI Host interrupt 3 PCI INTC N is an output from FPGA attached to network processor GPIO9 after reset as PCI Host interrupt 4 PCI INTD N is an output from FPGA attached to network processor GPIO8 after reset as PCI Host interrupt 5 Network processor GPIOs default to Not Attached after a reset except where indicated Table 51 Alternate GPIO Functions Resistor Signal Description Reference g g Designator GPIO4 signal from the IXDP425 development platform ETHA_GPIO10 UTP_GPIO4 UTOPIA connector R32N ETHA_GPIO11 MDINT_N1 Interrupt from the LXT9785 Octal Ethernet PHY R33N ETHA GPIO12 MDINT N2 Interrupt from the LXT9785 Octal Ethernet PHY R34N ETHA GPIO13 UTP RDY N Ready signal from the ADSL mezzanine card R35N ETHA GPIO14 UTP MODE Mode signal from the ADSL mezzanine card R36N GPIOS signal from the IXDP425 development platform ETHA GPIO15 UTP GPIO5 UTOPIA connector R37N Note Because of hardware limitations some GPIOs are shared with the mezzanine card for NPE A These shared signals involve installing 0 Qresistors that do not come factory installed For further infor
72. 00000 00000000 O O G IXDP465 expansion bus contains twenty five address bits ADDR24 EX_ADDR0 The expansion address signals EX_ADDR23 through EX_ADDR21 select one of two stacked modules Table 94 shows the unique IDs along with the upper expansion bus address signals for each stacked Quad mezzanine card These signals are used for expansion bus accesses Inte IXDP465 Development Platform User s Guide UG Order Number 306462 Revision 004 Mezzanine Card Hardware Design Table 94 T1 E1 Unique Stacking IDs and Expansion Bus Addresses Stacking Slot ID7 ID0 EX_ADDR23 EX_ADDR21 0 11111110 000 1 11111100 001 2 11111000 010 3 11110000 011 4 11100000 100 5 11000000 101 6 10000000 110 7 00000000 111 Note The IXP425 network processor on the IXDP425 development platform only uses 24 bits EX ADDR 4 does not exist so for compatibility it is not used on the Quad mezzanine card for address decode 5 4 4 Quad T1 E1 Card CPLD The CPLD on the IXPFRM465 Quad mezzanine card generates the PCM clocks PCM frame synchronization pulses oscillator enables and board interrupt status Table 95 shows the CPLD pin assignments Table 95 CPLD Pin Assignments Sheet 1 of 2 Pin Signal Pin Signal Pin Signal Pin Signal 1 26 1 8V 51 3
73. 08 EX ADDR24 29 CLK32 768M R R 69 GND 109 SSPS CLK 30 C FN 48 70 GND 110 SSPS FRM 31 C FN 49 71 IDO 111 SSPS TXD 32 C_FN_50 72 ID1 112 SSPS_RXD 33 C_FN_51 73 ID2 113 SSPS_EXTCLK 34 C_FN_52 74 ID3 114 5 0 V 35 C_FN_53 75 ID4 115 5 0 V 36 C FN 54 76 ID5 116 C PCI 0 27 55 77 ID6 H7 1 38 56 78 ID7 118 C PCI 2 29 57 79 2 SDA 119 C PCI 3 40 C FN 58 80 2 5 120 Legend power signals purple expansion bus signals green common future needs expansion signals blue dedicated future needs expansion signals black this card only SPI signals red 2 signals gold GPIO signals maroon ID signals teal September 2005 Intel IXDP465 Development Platform User s Guide 144 Order Number 306462 Revision 004 intel 5 4 2 3 Table 91 UG Mezzanine Card Hardware Design Stacking Interface Standard Connector The stacking interface standard connector contains the expansion bus interface GPIO HSS interface and power signals This connector is pin for pin compatible with the IXDP425 HSS interface connectors All signals necessary to communicate with the analog ports are available on this connector Table 91 defines the stacking interface standard connector signals The Legend describing the color codes for the signals follows the table Stacking Interface Standard Connector Signals Sheet 1 of 2
74. 0W HSS 0 mezzanine card 7W HSS 1 mezzanine card 7W MII 0 mezzanine card 7W MII 1 mezzanine card 7W MII 2 mezzanine card 7W ADSL mezzanine card 7W IXDP465 baseboard 8 w Total 180 W The power module plugs into the baseboard through a standard ATX 20 pin power supply connector P1 Table 58 defines the pinout for this connector Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 85 IXDP465 Baseboard Hardware Design Table 58 Table 59 3 19 1 September 2005 86 ATX Power Supply Connector Pin Assignments Connector Pin Signal 1 3 3 V 2 3 3 V 3 4 5 0 V 5 6 5 0 V 7 8 9 10 12 0 V 11 3 3 V 12 12 0 V 13 14 ATX_ENB_N 15 16 17 18 19 5 0 V 20 5 0 V The power supply shipped with the IXDP465 platform is the Autec PSG180B 80 This is an 180 W 6 output 1U power supply Table 59 lists the power supply maximum current output PSG180B 80 Power Supply Output Specifications Voltage 5 0 V 12 0 V 3 3 V 12 0 V Max Current 25 0 A 11 0 A 22 0 A 3 0 A Regulation 5 5 5 5 Ripple 50 mV 120 mV 50 mV 120 mV The IXDP465 platform has the capability to monitor the total wattage required by the IXP465 network processor for a given application There are three jumpers on the Network Processor Module for monitoring current See Figure 17 on page 98 for
75. 1 1 Low 2 3 Low 2 3 Low 2 3 High 1 2 Low 2 3 02 2 Low 2 3 Low 2 3 Low pins 2 3 High pins 1 2 High pins 1 2 03 3 Low pins 2 3 Low pins 2 3 High pins 1 2 Low pins 2 3 Low pins 2 3 04 4 Low pins 2 3 Low pins 2 3 High pins 1 2 Low pins 2 3 High pins 1 2 05 5 Low pins 2 3 Low pins 2 3 High pins 1 2 High pins 1 2 Low pins 2 3 06 6 Low pins 2 3 Low pins 2 3 High pins 1 2 High pins 1 2 High pins 1 2 07 7 Low pins 2 3 High pins 1 2 Low pins 2 3 Low pins 2 3 Low pins 2 3 08 8 Low pins 2 3 High pins 1 2 Low pins 2 3 Low pins 2 3 High pins 1 2 09 9 Low pins 2 3 High pins 1 2 Low pins 2 3 High pins 1 2 Low pins 2 3 A 10 Low pins 2 3 High pins 1 2 Low pins 2 3 High pins 1 2 High pins 1 2 B 11 Low pins 2 3 High pins 1 2 High pins 1 2 Low pins 2 3 Low pins 2 3 C 12 Low pins 2 3 High pins 1 2 High pins 1 2 Low pins 2 3 High pins 1 2 D 13 Low pins 2 3 High pins 1 2 High pins 1 2 High pins 1 2 Low pins 2 3 E 14 Low pins 2 3 High pins 1 2 High pins 1 2 High pins 1 2 High pins 1 2 F 15 High pins 1 2 Low pins 2 3 Low pins 2 3 Low pins 2 3 Low pins 2 3 10 16 High pins 1 2 Low pins 2 3 Low pins 2 3 Low pins 2 3 High pins 1 2 11 17 High pins 1 2 Low
76. 10 NPE Function Connections Table 27 through Table 32 define the NPE signals and their associated functions for each type of MII interface The IXDP465 platform has a separate oscillator for use with SMI mode The clock frequency is jumper selectable via JP9 and JP11 as shown in Figure 11 A clock driver minimizes noise Each clock signal contains a series resistor and parallel capacitor to reduce noise The SMII interface requires a 125 MHz 50ppm reference The reference clock must be enabled at all times The 125 MHz clock characteristics include Duty cycle distortion no greater than 40 to 60 Voltage levels gt 2 0 V for VCCIO 3 3 5 VOH gt 1 75 V for VCCIO 2 5 5 A recommended clock for 125 MHz operation is the Saronix ST4130A The reference clock generates transmit signals and recovers receive signals A crystal based clock is recommended over a derived clock i e PLL based to minimize transmit jitter Regardless of clock source careful consideration must be given to physical placement board layout and signal routing of the source to maintain the highest possible level of signal integrity September 2005 Intel IXDP465 Development Platform User s Guide UG 52 Order Number 306462 Revision 004 IXDP465 Baseboard Hardware Design Figure 11 Jumper Locations and Default Settings IMEL 097 240 A23 JP128 A24 JP127 FLASH JUMPERS UTOPIA U
77. 103 EX DATA12 24 RDY 64 104 DATA15 25 EX IOWAIT 65 GND 105 DATA14 26 INT OUT N 66 HSS PRI RXCLK 106 GND 27 EX CS N 67 107 GND 28 3 3 68 GND 108 ADDR1 29 69 HSS_SEC_RXCLK 109 EX_ADDRO 30 3 3V 70 110 EX ADDR3 31 5 0 V 71 HSS SEC RXFRAME 111 EX_ADDR2 32 3 3V 72 HSS_SEC_RXDATA 112 EX_ADDR5 33 5 0V 73 12V 113 EX_ADDR4 34 3 3V 74 2 5 V 114 EX_ADDR7 35 5 0V 75 12V 115 EX_ADDR6 36 3 3V 76 25y 116 GND 37 5 0 V 77 12V 117 September 2005 142 Inte IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 UG I ntel Mezzanine Hardware Design Table 89 IXDP465 Interface Standard Connector Signals Sheet 2 of 2 Signal Pin Signal Pin Signal Pin GND 38 3 3 V 78 25V 118 EX_ADDR9 39 5 0 V 79 12V 119 EX ADDR8 40 3 3V 80 2 5 V 120 Legend power signals purple IXPAXX Network Processor extended expansion bus signals green GPIO signals maroon HSS signals primary black HSS signals secondary red not used JTAG signals gray interrupt signal gold 5 4 2 2 IXDP465 Interface Expansion Connector The IXDP465 interface expansion connector contains the extended expansion bus interface IXP465 specific GPIO SPI I2C ID future needs and power signals Table 90 defines the IXDP465 interface expansion connector signals The Legend describing the color codes for the sign
78. 12 22_T 9 RXTIP3 29 NC 10 RXRING3 30 TXTIP12 22 T 11 TXTIP12 22 31 RXRING3 T UG Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 159 Mezzanine Card Hardware Design In Table 101 Quad Port Transformer Interface Pin Assignments Sheet 2 of 2 Pin Signal Pin Signal 12 3 3 V 32 RXTIP3 T 13 XRING12 22 33 XRING13 23 T 14 RXTIP2 34 NC 15 RXRING2 35 TXTIP13 23 T 16 TXTIP11 21 36 RXRING4 T 17 GND 37 4 18 XRING11 21 38 XRING14 24_T 19 RXTIP1 39 NC 20 RXRING1 40 TXTIP14 24_T 5 4 5 6 Protection Interface The Quad mezzanine card is designed to protect against over voltage and over current power surges from lightning strikes or AC power cross disturbances The protection circuitry consists of four 4 fuses in conjunction with six 6 Teccor SIDACtor devices for each port This combination satisfies the regulatory requirements The fuses provide the over current protection and the Teccor SIDACtor devices provide the over voltage protection Figure 46 represents the required analog interface circuitry for one channel This circuitry must be repeated for the number of channels required Figure 47 represents the required protection circuitry for one channel This circuitry must be repeated for the number of channels required Figure 46 External Analog Interface Circuitry for One Channel RXTIP1 oo ut TXT
79. 2 Expansion Bus Configuration Straps 34 3 3 8 Expansion Bus Clock Generation sse 38 3 3 4 Expansion Bus Chip Selects r 38 3 3 5 Expansion Bus Address 38 3 3 6 Expansion Bus LCD Display 39 rie c 40 39 5 ier ei tee o Een Lex 40 96 HSSCORnNSGLUIS gu 41 3 6 1 HSS 0 Mezzanine Card Interface I 42 3 6 HSS 1 Mezzanine Card Interface sess 46 37 SMII Multi Pack Interface enne nennen nnns 49 3 74 Multi Gang Jack eer ett cx ea e toa 50 3 7 2 PHY Connection ssssssssssssssseseee eene nnne nnne nnns nennen 50 3 7 8 SMII Configurations 54 3 8 NPE Jumper Block Pin Assignments U 54 3 8 1 Jumper Block 54 3 8 2 MII Jumper Block 2 55 3 8 3 UTOPIA Jumper Block 3 56 3 8 4 MII Jumper Block 57 3 85 Jumpers 65 93 57 39 Mezzanine Card Connectors
80. 2 GPIO Resistor UARTO DCD MII2 lt 10 gt R301N UARTO DSR MII2 GPIO 11 R299N UARTO RI MII2 GPIO 12 R297N UARTO DTR MII2 lt 13 gt R295N UART1 DCD 2 GPIO 6 R300N UART1_DSR MII2_GPIO lt 7 gt R298N UART1_RI MII2 lt 8 gt R296N UART1 DTR MII2 lt 9 gt R294N DB 9 Connector EMI Considerations To reduce susceptibility to EMI from the cable 0 1 uF capacitors are placed on all nine signals including ground These capacitors are discharged routed to earth ground Inte IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 September 2005 71 Li IXDP465 Baseboard Hardware Design ntel 6 3 12 2 Table 44 3 13 September 2005 72 Serial Port Pull Ups Pull Downs Receive signal lines are pulled down through a 5 KQ resistor on the RS 232 side within the transceiver Since data signals are inverted the IXDP465 baseboard sees a pull up on these lines To allow additional signal conditioning in case the internal pull down is not strong enough an unpopulated pull up has been placed on the IXDP465 baseboard side Receive signals A 10 KQ resistor strength is suggested for these pull ups in the Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet The transceiver does not include pull ups on transmitter inputs Unused inputs must be pulled to valid logic levels Therefore DSR RI and DCD are pulled high to ensure that these inputs
81. 22 lists the pull up resistors placed on the IXDP465 baseboard The resistor placement follows the requirements listed in the Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet The 10 resistor value was chosen so that a DSL module can easily over drive the signal state provided by the pull up Decoupling is handled on each module UG Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 41 a IXDP465 Baseboard Hardware Design ntel 6 Table 22 3 6 1 September 2005 42 550 1 Resistors Signal Pull to Value Resistor Value HSS0 1_TXDATA0 1 3 3 V 10 KQ HSS0 1_TXFRAME0 1 3 3 V 10 KQ HSS0 1_TXCLK0 1 3 3 V 10 KQ HSS0 1_RXDATA0 1 3 3 V 10 KQ HSS0 1 RXFRAMEO 1 3 3 V 10 KQ HSS0 1 RXCLKO 1 3 3 V 10 KQ HSS 0 Mezzanine Card Interface To achieve compatibility with the IXDP425 IXCDP1100 platform the following features are designed into the IXDP465 platform interface standard connector for the HSS mezzanine card slot Connector part number Amp 5 179010 5 Exact pin out match with the IXDP425 development platform Primary connection to HSSO Use of expansion bus chip select 3 Use of expansion bus ready 3 The IXDP465 platform expansion bus connector for the HSS mezzanine card slot contains the following signal groups XP465 SPI IXP465 C XP465 extended expansion bus 16 GPIO Mezzanine ID byte
82. 27 Analog Voice Card Logical Block Diagram 5 2 2 Analog Voice Card Connector Interfaces 5 3 2 1 IXDP465 Interface Standard Connector The IXDP465 interface standard connector contains the expansion bus interface GPIO HSS interface and power signals This connector is pin for pin compatible with the IXDP425 HSS interface connectors All signals necessary to communicate with the analog voice ports are available on this connector Table 78 lists the IXDP465 interface standard connector signal definitions The Legend describing the color codes for the signals follows the table UG Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 121 Mezzanine Card Hardware Design Table 78 IXDP465 Interface Standard Connector Signals Sheet 1 of 2 Signal Pin Signal Pin Signal Pin 1 EX_ADDR11 41 5 0 V 81 2 EX ADDR10 42 3 3 V 82 3 ADDR13 43 GPIO2 83 4 ADDR12 44 GPIO3 84 EX DATA1 5 EX_ADDR15 45 GND 85 EX_DATAO 6 EX_ADDR14 46 GND 86 EX_DATA3 7 GND 47 87 EX_DATA2 8 GND 48 GPIO4 88 GPIOO 9 ADDR17 49 89 GPIO1 10 EX ADDR16 50 DATA5 11 ADDR19 51 91 DATA4 12 ADDR18 52 HSS_TXFRAME1 92 EX_DATA7 13 EX_ADDR21 53 93 DATA6 14 EX_ADDR20 54 HSS TXCLK1 94 GND 15 EX ADDR23 55 GND 95 GND 16 ADDR22 56 HSS TXDATA1 96 DATA9 17 GND
83. 3 V 76 EX_DATA3 2 CT_CLK 27 E1_T1_CLK 52 E1_CLK_EN 77 ID6 3 CPLD TEST2 28 CPLD 5 5 53 T1_CLK_EN 78 ID7 4 CPLD_TEST1 29 CPLD_TEST6 54 ID5 79 SSPS_RXD 5 3 3 V 30 BRSIG4 55 ID4 80 CLK32 768MHZ_EN 6 EX_ADDR0 31 GND 56 ID3 81 SSPS_EXTCLK 7 EX ADDR1 32 BRSIG3 57 1 8 V 82 HSS_PRI_RXDATA 8 EX_ADDR2 33 BRSIG2 58 ID2 83 TDO 9 EX_ADDR3 34 BRSIG1 59 ID1 84 GND 10 EX_ADDR4 35 EX_WR_N 60 IDO 85 CMVFPB 11 EX_ADDR21 36 EX_RD_N 61 EX_DATAO 86 CMVFPC 12 EX_ADDR22 37 PIO 62 GND 87 MVBTD CCSBRD 13 EX_ADDR23 38 3 3 V 63 EX_DATA1 88 3 3 V 14 HSS PRI RXCLK 39 I2C SDA 64 EX DATA2 89 E1 T1 CS N 15 CPLD TEST3 40 I2C_SCL 65 GPIOO 90 MVBRD 16 HSS PRI RXFRAME 41 BTSIG1 66 GPIO1 91 RSYNC 17 HSS PRI TXCLK 42 BTSIG2 67 GPIO2 92 E1 T1 INT N 18 HSS PRI TXDATA 43 BTSIG3 68 GPIO3 93 EX_CS_N UG Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 149 Mezzanine Card Hardware Design Table 95 5 4 4 1 Note Figure 38 intel CPLD Pin Assignments Sheet 2 of 2 Pin Signal Pin Signal Pin Signal Pin Signal 19 HSS PRI TXFRAME 44 BTSIG4 69 GND 94 HSS_INT_IN_N 20 3 3V 45 TDI 70 GPIO4 95 CLK_32 768M_R_R 21 GND 46 CMV8MCLK EX_DATA7 96 SSPS_FRM 22 EX_CLK 47 TMS 72 EX_DATA6 97 SSPS_TXD 23 SSPS_CLK 48 TCK 73 EX DATA5 98 3 3 V 24 RST 49 CCSBTD 74 EX DATA4 99 CPLD TEST4 25 GND 50 HSS_INT_OUT_N 75 GND 100 G
84. 36 5 4 5 4 1 September 2005 140 Analog Voice Mezzanine Port Status LEDs FXS3 CR4 338 dU m Y FXO X MQ CR5 ese B5038 01 IXPFRM465 Quad T1 E1 Mezzanine Card Introduction The IXPFRM465 Quad mezzanine card plugs into the baseboard through the standard 120 pin connector which is the same as that used on the Intel IXDP425 IXCDP1100 Development Platform The pin out is the same as the HSS connectors on the IXDP425 IXCDP1100 platform with the second alternate HSS port being routed to IXDP425 connector unused pins allowing the device to be stackable two high The stacking connector is physically identical and the signaling is copied with the exception of routing the alternate HSS port up to the second card The IXDP465 platform achieves control and status of the T1 ports via the expansion bus interface the voice interface via the HSS interface GPIO is used for interrupts Figure 37 shows the IXPFRM465 Quad T1 E1 mezzanine card components Inte IXDP465 Development Platform User s Guide UG Order Number 306462 Revision 004 I ntel Mezzanine Card Hardware Design Figure 37 Quad T1 E1 Mezzanine Card Logical Block Diagram Protection Circuitry Quad Transformer Quad T1 E1 Framer 5 4 2 Quad T1 E1 Card Connector Interfaces 5 4 2 1 IXDP465 Interface Standard Connector The IXDP465 interface standard connector contains the expansion bus interf
85. 4 5 5 Quad Port Transformer 159 5 4 5 6 Protection Interfa06 u uuu usu 160 5 4 5 7 RJ 45 Connector 161 Updating the IXDP465 Flash Memory sese 163 Generic Flash Updating Using RedBootl a 163 A 2 Creating a Backup Copy of RedBool a 165 Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 5 Contents ntel Using RedBoot to Update 165 A 4 Using an External Debugger to Update 167 Figures 1 IXDP465 Baseboard Functional Block emen 18 2 IXDP465 Mezzanine Card Attachment sessi 20 3 IXDP465 Mezzanine Card Stacking eene enne 21 4 IXDP465 Development Platform Components Top 23 5 I XDP465 Development Platform Components Bottom 24 6 de ArGh ite Ctr MEER 26 7 Switch Locations and Default Settings sess 37 8 RJ 45 Jack with Integrated 50 9 Octal PHY Connection to Magnetics r 51 10 NPE Function Connections sssaaa
86. 4 C_NPE_8 64 GND 104 EX_DATA31 25 C_NPE_9 65 MII0_GPIO12 105 EX_DATA30 26 C_NPE_10 66 GPIO13 106 GND 27 C NPE 11 67 GPIO14 107 GND 28 C NPE 12 68 GPIO15 108 EX ADDR24 29 GND 109 SSPS CLK 30 C FN 0 70 GND 110 SSPS FRM 31 C FN 1 71 GND IDO 111 SSPS TXD 32 C FN 2 72 3 3 V ID1 112 SSPS RXD 33 C FN 3 73 3 3 V ID2 113 SSPS_EXTCLK 34 C_FN_4 74 3 3 V ID3 114 5 0 V 35 C_FN_5 75 3 3 V ID4 115 Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 61 IXDP465 Baseboard Hardware Design Table 35 3 9 2 September 2005 62 MII 0 Mezzanine Card Expansion Connector Signals Sheet 2 of 2 intel Signal Pin Signal Pin Signal Pin 5 0 V 36 C_FN_6 76 3 3 V ID5 116 C_PCI_O 27 7 77 3 3 V ID6 PCI 1 38 8 78 3 3 V ID7 118 2 39 C FN 9 79 2 SDA 119 GPCL 8 40 C_FN_10 80 2 SCL 120 Legend power signals purple expansion bus signals green common future expansion signals blue a expansion signals black SPI signals red I2C signals gold GPIO signals maroon MII 1 Mezzanine Card To achieve compatibility with the IXDP425 IXCDP1100 platform the following features have been designed into the IXDP465 platform interface standard connector for the MII 1 mezzanine card Connector part number Amp 5 179010 5 Exact pi
87. 45 POI 3 3V B16 PCI OPT CLK B45 PCI AD14 17 PCLOPT_GNT_N A46 PCI AD13 B17 GND B46 GND A18 GND A47 PCI AD11 B18 PCI OPT REQ N B47 PCI OPT AD12 A19 A48 GND B19 B48 PCI OPT AD10 A20 PCI 49 PCI AD9 B20 PCI ADS1 B49 PCI OPT M66EN A21 PCI 3 3V 52 PCI CBE NO B21 PCI AD29 B52 OPT AD8 A22 PCI AD28 A53 PCI 3 3V B22 GND B53 OPT AD7 A23 PCI AD26 A54 PCI AD6 B23 AD27 B54 POI 3 3V A24 GND A55 PCI OPT AD4 B24 PCI AD25 B55 PCI OPT AD5 A25 PCI AD24 A56 GND B25 PCI 3 3V B56 PCI A26 PCI IDSEL A57 PCI AD2 B26 PCI OPT CBE N3 B57 GND UG Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 33 Li IXDP465 Baseboard Hardware Design ntel Table 14 PCI Option Fingers Pin Assignments Sheet 2 of 2 Pin Signal Pin Signal Pin Signal Pin Signal A27 PCI_3 3V A58 PCI OPT ADO B27 PCI OPT AD23 B58 PCI AD1 A28 PCI AD22 A59 B28 GND B59 29 PCI AD20 A60 PCI REQ64 29 PCI 21 B60 PCI OPT ACK64 N A30 GND A61 B30 PCI OPT AD19 B61 A31 PCI AD18 A62 B31 PCI 3 3V B62 3 3 3 3 1 3 3 2 Pull up resistors are required for the following PCI Opti
88. 47 PCI 1 14 PCI_ADD23 54 B27 PCI ADD12 94 B47 PCI REQ N2 15 PCI ADD22 55 A28 PCI 2 16 GND 56 PCI_ADD10 96 B48 PCI REQ N3 17 PCI ADD20 57 A29 PCI ADD9 97 A49 PCI N3 18 PCI ADD 1 58 B29 GPIO2 19 GND 59 GPIO13 99 UG Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 103 Li Network Processor Module Hardware Design ntel Table 71 465 Network Processor Module PCI Bus Connector Signals Sheet 2 of 2 Signal Pin PCI Pin Signal Pin PCI Pin Signal Pin PCI Pin 4 GPIO3 20 PCI ADD19 60 B30 GPIO14 100 gt TXDATA0 21 PCI_ADD18 61 A31 GPIO15 101 RXDATAO 22 5 GND 62 s CTS NO 23 i PCI ADD16 63 A32 PCI CBE NO 103 A52 RTS NO 24 PCI ADD17 64 B32 PCI ADD8 104 B52 TXDATA1 25 GND 65 RXDATA1 26 PCI CBE N2 66 B33 PCI ADD7 106 B53 CTS N1 27 PCI FRAME N 67 A34 PCI ADD6 107 54 RTS_N1 28 2 5 V 68 12 0 V 29 2 5 V 69 PCI ADD4 109 A55 412 0 V 30 PCI IRDY N 70 B35 PCI ADD5 110 B55 PCI N 31 B PCI TRDY N 71 A36 PCI CLK 32 B16 5 0 V 72 PCI_ADD3 112 B56 PCI GNT NO 33 A17 5 0 V 73 PCI_ADD2 113 A57 GPIO4 34 PCI DEVSEL N 74 B37 GPIO5 35 PCI STOP N 75 A38 PCI ADDO 115 A58 PCI REQ NO 36 B18 GND 76 5 PCI_ADD1 116 B58 GPIO6 37 GPIO8
89. 5 4 3 5 4 3 1 93 September 2005 148 Legend Continued SPI signals red 2 signals gold GPIO signals maroon ID signals teal not used gray one signal in group Quad T1 E1 Card Stacking The IXDP465 platform design supports stacking up to two IXPFRM465 Quad mezzanine cards The board ID accesses these two interfaces Board ID Eight signals on the IXDP465 expansion interface connector define a unique address on each stacked HSS Quad mezzanine card Since this connector does not exist on the IXDP425 development platform a mechanism has been implemented on the Quad mezzanine card to emulate connection to the IXDP465 platform when the card is used on an IXDP425 platform The IXDP465 platform ties IDO to ground and ID7 ID1 to 3 3 V The Quad mezzanine card pulls down IDO using 100 resistor and pulls up 107 ID1 using 49 9 resistor to function on the IXDP425 platform The signals must be shifted from the IXDP465 interface expansion connector to the stacking interface expansion connector i e IXDP465 ID6 IDO shifted to Stacking ID7 ID1 with the 100 kQ pull down on the next module up the chain filling in a logic low for IDO Table 93 shows the unique IDs for each stacked HSS Quad T1 E1 mezzanine card T1 E1 Unique Stacking IDs Stacking Slot ID7 IDO 0 11111110 1 11111100 11111000 11110000 11100000 11000000 100
90. 57 HSS TXDATAO 97 DATA8 18 GND 58 GND 98 EX DATA11 19 EX CLK 59 HSS TXFRAMEO 99 EX DATA10 20 EX RD N 60 HSS RXDATAO 100 21 GND 61 101 22 EX WR N 62 HSS RXFRAMEO 102 EX DATA13 23 EX ALE 63 HSS TXCLKO 103 EX DATA12 24 EX RDY N 64 104 EX DATA15 25 EX IOWAIT 65 GND 105 EX DATA14 26 INT OUT N 66 HSS RXCLKO 106 GND 27 EX CS N 67 107 GND 28 3 3V 68 GND 108 ADDR1 29 69 HSS RXCLK1 109 ADDRO 30 3 3 V 70 110 ADDR3 31 5 0 V 71 HSS RXFRAME 1 111 ADDR2 32 3 3 V 72 HSS RXDATA1 112 ADDR5 33 5 0 V 73 12V 113 ADDR4 34 3 3 V 74 2 5 V 114 ADDR7 35 5 0 V 75 12V 115 EX ADDR6 36 3 3 V 76 2 5 V 116 GND 37 5 0 V 77 12 V 117 September 2005 122 Inte IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 UG I ntel Mezzanine Hardware Design Table 78 IXDP465 Interface Standard Connector Signals Sheet 2 of 2 Signal Pin Signal Pin Signal Pin GND 38 3 9 V 78 BV 118 EX ADDR9 39 5 0 V 79 12V 119 EX ADDR8 40 3 3 V 80 25 120 Legend power signals purple IXP4XX Network Processor extended expansion bus signals green GPIO signals maroon 550 signals primary black HSS1 signals secondary red not used JTAG signals gray interrupt signal gold 5 3 2 2 IXDP465 Interface Expansion Connector The IXDP465 interface expansion connector contains the exte
91. 6 194 38 ETHA_GPIO6 140 70 HSS1_GPIO6 62 102 Reserved n a 7 ETHB_GPIO7 195 39 ETHA_GPIO7 141 71 HSS1 GPIO7 63 103 Reserved 8 ETHB GPIO8 199 40 GPIO8 147 72 HSS1 GPIO8 67 104 Reserved n a 9 ETHB GPIO9 200 41 ETHA_GPIO9 148 73 HSS1_GPIO9 68 105 Reserved n a 10 10 201 42 ETHA_GPIO10 149 74 HSS1_GPIO10 69 106 Reserved n a 11 ETHB GPIO11 202 43 ETHA_GPIO11 150 75 HSS1 GPIO11 70 107 Reserved n a 12 ETHB GPIO12 203 44 ETHA_GPIO12 151 76 HSS1 GPIO12 71 108 Reserved 13 ETHB_GPIO13 204 45 GPIO13 152 77 HSS1 GPIO13 73 109 Reserved 14 GPIO14 205 46 GPIO14 109 78 HSS1 GPIO14 74 110 Reserved 15 ETHB GPIO15 206 47 GPIO15 110 79 HSS1 GPIO15 75 111 Reserved 16 0 162 48 HSSO_GPIOO 81 80 PCI INTA N 113 112 Reserved 17 ETHC GPIO1 163 49 550 GPIO1 82 81 PCI INTB N 114 113 Reserved Notes 1 PCI INTA N is an output from FPGA attached to network processor GPIO11 after reset as PCI Host interrupt 2 PCI INTB N is an output from FPGA attached to network processor GPIO10 after reset as PCI Host interrupt 3 PCI INTC N is an output from FPGA attached to network processor GPIOO after reset as PCI Host interrupt 4 PCI INTD N is an output from FPGA attached to network processor GPIO8 after reset as PCI Host interrupt 5 Network processor GPIOs default to Not Attached after a reset
92. 7 SSPS_EXTCLK 23 CLK32 768M_L_R 48 TCK 73 EX_DATA5 98 3 3 V 24 RST_N 49 SDI 74 EX_DATA4 99 TEST4 25 GND 50 SDO 75 GND 100 GND 5 3 5 1 Internal CPLD Registers The expansion bus accesses internal CPLD registers The CPLD must decode the proper upper expansion bus address based upon its ID in the stack See Section 5 4 2 4 Stacking Interface Expansion Connector for further details The lower five expansion address bits decode which register is accessed Table 86 lists the internal CPLD registers on the Analog Voice mezzanine card Table 86 Internal CPLD Registers Register Name EX_ADDR4 EX ADDRO Access Type Board Status 00000 Read Only Analog IC Chip Selects 00001 Read Write Interrupt Status 00010 Read Only Relay Control 00011 Read Write IXDP425 IXDP465 Mode 00100 Read Write PCM Mode 00101 Read Write Port Reset 00110 Read Write Reserved 00111 11111 n a The Board Status register is a read only register that contains the same information that is accessed using the interface See Section 5 3 5 5 I2C Interface for details Analog IC Chip Selects Register The Analog IC Chip Selects register is a read write register that selects which analog port is accessed by the SPI interface See Section 5 3 5 2 SPI Interface for details Care must be taken to ensure that only one chip select is in the active state logic low The val
93. 74 Inte IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 UG I ntel IXDP465 Baseboard Hardware Design Table 47 GPIO FPGA Access Signals Sheet 2 of 2 FPGA FPGA Signal Description Pin Signal Description Pin Expansion bus data 5 Used EX_DATA5 during configuration and 119 GPIO19 Network Processor GPIO19 8 register access Expansion bus data 4 Used EX DATA4 during configuration and 126 GPlIO20 Network Processor GPIO20 9 register access Expansion bus data 3 Used EX DATA3 during configuration and 135 GPIO21 Network Processor GPIO21 10 register access Expansion bus data 2 Used EX DATA2 during configuration and 142 GPlO22 Network Processor GPIO22 14 register access Expansion bus data 1 Used EX DATA1 during configuration and 146 GPIO23t Network Processor GPIO23 15 register access Expansion bus data 0 Used EX DATA0 during configuration and 153 GPIO24 Network Processor GPIO24 16 register access Expansion bus write signal 80 EX WR N Used during configuration and 155 25 Network Processor GPIO25 17 register access Expansion bus read signal EX_RD_N Used during register access 182 GPIO26 Network Processor GPIO26 18 Expansion bus clock signal t EX CLK FPGA Used during register access 77 GPIO27 Network Processor GPIO27 20 System reset signal Initializes t RST N default
94. 77 3 3 V 117 GPIO7 38 GPIO9 78 3 3 V 118 PCI_ADD30 39 A20 GND 79 3 3 V 119 PCI ADDS1 40 B20 PCI PERR N 80 B40 3 3 V 120 E Legend power signals purple PCI signals green USB signals gold GPIO signals maroon 4 1 4 Expansion Bus Connector The expansion connector contains the signaling from the IXP465 network processor for the Expansion Bus Table 72 shows the expansion bus connector signal assignment The signals include all IXP465 signals There are nine reserved signals The reserved signals must be left unconnected The expansion bus signals connect directly to the IXP465 September 2005 Intel IXDP465 Development Platform User s Guide UG 104 Order Number 306462 Revision 004 Table 72 UG Network Processor Module Hardware Design IXP465 Network Processor Module Expansion Bus Connector Signals Sheet 1 of 2 Signal Pin Signal Pin Signal Pin GND 41 EX_DATA0 81 EX_CLK 42 EX_DATA1 82 EX ALE 43 EX DATA2 83 GND 44 EX DATA3 84 EX WAIT N 45 EX DATA4 85 EX SLAVE CS N 46 EX DATA5 86 GND 47 EX DATA6 87 EX IOWAIT N 48 EX 88 EX BURST 49 EX DATA8 89 EX ADDRO 10 GND 50 EX DATA9 90 EX ADDR1 11 EX RDY NO 51 EX DATA10 91 EX ADDR2 12 EX RDY N1 52 EX DATA11 92 EX ADDRS3 13 GND 53 EX DATA12 93 EX ADDRA4 14 EX RDY N2 54 EX DATA13 94 EX ADDR5 15 EX RDY 55 EX DATA14
95. 9 3 V 82 3 EX_ADDR13 43 MII1_GPIO2 83 4 EX ADDR12 44 1 GPIO3 84 EX DATA1 5 EX ADDR15 45 GND 85 EX DATAO 6 EX ADDR14 46 GND 86 EX DATA3 GND 47 87 EX DATA2 8 GND 48 MII1_GPIO4 88 MIl1_GPIOO 9 EX_ADDR17 49 89 GPIO1 10 EX ADDR16 50 RST 90 EX DATA5 11 EX ADDR19 51 91 EX DATA4 12 EX ADDR18 52 92 EX 13 EX_ADDR21 53 93 EX_DATA6 14 EX_ADDR20 54 ETHC_RXDV 94 GND 15 EX_ADDR23 55 GND 95 GND 16 EX_ADDR22 56 ETHC_RXCLK 96 EX_DATA9 17 GND 57 ETHC_RXDATA3 97 EX DATA8 18 GND 58 GND 98 EX DATA11 19 EX CLK MII1 59 ETHC_RXDATA2 99 EX_DATA10 20 EX_RD_N 60 ETHC_TXCLK 100 21 GND 61 ETHC_RXDATA1 101 22 EX_WR_N 62 ETHC_COL 102 EX_DATA13 23 EX_ALE 63 ETHC_RXDATAO 103 EX_DATA12 24 EX_RDY_N1 64 ETHC_TXDATA3 104 EX_DATA15 25 EX_IOWAIT_N 65 GND 105 EX_DATA14 26 ETHC_INT_N 66 ETHC_TXDATA2 106 GND 27 EX CS 5 67 ETHC_TXDATA1 107 GND 28 8 3 V 68 GND 108 EX_ADDR1 29 69 ETHC_TXDATAO 109 EX_ADDRO 30 ae V 70 ETH_MDC 110 Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 63 IXDP465 Baseboard Hardware Design Table 36 Table 37 September 2005 64 MII 1 Mezzanine Card Standard Connector Signals Sheet 2 of 2 Signal Pin Signal Pin Signal Pin EX_ADDR3 31 5 0 V 71 ETHC_CRS 111 EX_ADDR2 32 35V 72 ETH MDIO 112 EX ADDR5 33 5 0 V 73 12V 119 EX ADDR4 34 3 3V 74 25 V 114 EX_AD
96. 91 EX DATA4 12 EX_ADDR18 52 HSS_TXFRAME1 92 EX_DATA7 19 ADDR21 53 93 EX_DATA6 14 EX_ADDR20 54 HSS_TXCLK1 94 GND 15 EX_ADDR23 55 GND 95 GND 16 EX_ADDR22 56 HSS TXDATA1 96 EX DATA9 17 GND 57 HSS TXDATAO 97 EX DATA8 18 GND 58 GND 98 DATA11 19 EX CLK HSSO 59 HSS TXFRAMEO 99 EX DATA10 20 EX RD N 60 HSS RXDATAO 100 21 GND 61 101 22 EX_WR_N 62 HSS_RXFRAMEO 102 EX_DATA13 23 EX_ALE 63 HSS_TXCLKO 103 EX DATA12 24 EX RDY N3 64 104 EX DATA15 25 EX IOWAIT N 65 GND 105 EX DATA14 26 HSSO INT N 66 HSS RXCLKO 106 GND 27 EX CS 67 107 GND 28 3 3 V 68 GND 108 EX ADDR1 29 69 HSS RXCLK1 109 EX ADDRO 30 93V 70 110 EX ADDR3 31 5 0V 71 HSS RXFRAME1 111 EX ADDR2 32 3 3 V 72 HSS RXDATA1 112 EX_ADDR5 33 5 0 V 73 12V 113 EX_ADDR4 34 3 3 V 74 2 5 V 114 EX_ADDR7 35 5 0 V 75 12V 445 EX_ADDR6 36 RE 76 2 5 V 116 GND 37 5 0 V 77 12V 117 UG Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 43 Li IXDP465 Baseboard Hardware Design ntel 23 24 September 2005 44 HSS 0 Mezzanine Card Standard Connector Signals Sheet 2 of 2 Signal Pin Signal Pin Signal Pin GND 38 33 V 78 2 5 V 118 EX_ADDR9 39 5 0 V 79 12V 119 EX ADDR8 40 3 3 V 80 25V 120 Legend power signals purple IXPAXX Network Processor extended expansion bus signals green GPIO signals maroon 550 signals pri
97. 91 493 495 497 499 501 503 505 507 509 51 0 511 HSS_RXCLKO N HSS RXDATAO Slot 0 In Slot 1 In Slot 2 In Slot 3 In lt Slot 67 In Slot 62 In Slot 63 In HSS TXDATAO lt SOTO Out Slot 1 Out Sot2Ou gt Set sO Slo6iOut gt Sht62Out gt Slot 63 Out Each analog port must transmit and receive its analog voice data on a unique PCM slot Table 88 defines the PCM slot configuration Table 88 PCM Slot Assignments Slot Board Channel Board Channel Slot Board Channel Slot Board Channel 0 0 FXO 16 3 FXSO 32 6 FXS1 48 1 0 FXS0 17 3 FXS1 33 6 FXS2 49 2 0 FXS1 18 3 FXS2 34 6 FXS3 50 3 0 FXS2 19 3 FXS3 35 7 FXO 51 4 0 FXS3 20 4 FXO 36 7 FXS0 52 5 1 FXO 21 4 FXS0 37 71 1 53 6 1 50 22 4 FXS1 38 7 FXS2 54 7 1 FXS1 23 4 FXS2 39 7 FXS3 55 8 1 FXS2 24 4 FXSS3 40 56 9 1 FXS3 25 5 FXO 4 57 10 2 FXO 26 5 50 42 58 11 2 FXSO 27 5 FXS1 43 59 12 2 FXS1 28 5 FXS2 44 60 13 2 FXS2 29 5 FXS3 45 61 14 2 FXS3 30 6 FXO 46 62 15 3 FXO 31 6 FXS0 47 63 September 2005 Intel IXDP465 Development Platform User s Guide UG 138 Order Number 306462 Revision 004 In 5 3 5 4 5 3 5 5 5 3 5 6 5 3 5 7 UG Mezzanine Card Hardware Design Master Clock The CPLD generates an
98. A This signal must be tied to GND 54 GPIO9 Network Processor GPIO9 42 FPGA CFG WR N Used during configuration of FPGA This signal must be tied to GND 161 GPIO10 Network Processor GPIO10 43 FPGA TCK Unused This signal must be tied to 3 3 V with a 1 kQ resistor 207 GPIO11 Network Processor GPIO11 44 FPGA TMS Unused This signal must be tied to 3 3 V with a 10 kQ resistor GPIO12 Network Processor GPIO12 45 FPGA TDI Unused This signal must be tied to 3 3 V with a 10 kQ resistor 159 GPIO13 Network Processor GPIO13 46 FPGA TDO Unused This signal must be tied to 3 3 V with a 10 kQ resistor 157 GPIO14 Network Processor GPIO14 47 EX ADDR1 Expansion bus address 1 Used for address decode of internal FPGA registers 111 GPIO15 Network Processor GPIO15 48 EX ADDRO Expansion bus address 10 Used for address decode of internal FPGA registers 112 GPIO16t Network Processor GPIO16 EX DATA7 Expansion bus data 7 Used during configuration and register access 108 GPIO17 Network Processor GPIO17 EX DATA6 Expansion bus data 6 Used during configuration and register access 115 18 Network Processor GPIO18 1 Network Processor GPIO16 GPIO31 are not available on the IXP465 network processor and are reserved for future use September 2005
99. CI PAR B11 PCI HST PRSNT2 2 B43 3 3 V 14 A44 PCI HST AD15 B14 B44 PCI HST CBE 1 September 2005 30 Inte IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 UG intel IXDP465 Baseboard Hardware Design Table 12 PCI Host Slot 2 Pin Assignments Sheet 2 of 2 Pin Signal Pin Signal Pin Signal Pin Signal A15 A45 3 3V B15 GND B45 PCILHST_AD14 A16 3 3V 46 PCI HST AD13 B16 PCI HST CLK2 B46 GND A17 PCILHST_GNT_N2 47 PCI HST AD11 B17 GND B47 PCI AD12 A18 GND A48 GND B18 PCI HST REQ 2 B48 PCI HST AD10 A19 A49 PCI HST AD9 B19 3 3V B49 PCI HST M66EN2 A20 PCI AD30 A50 GND B20 1 B50 GND 21 3 3V A51 GND B21 PCILHST_AD29 B51 GND A22 PCI HST AD28 A52 PCI HST CBE NO B22 GND B52 PCI HST AD8 A23 PCI AD26 AB3 3 3V B23 PCILHST_AD27 B53 PCILHST_AD7 A24 GND A54 PCILHST_AD6 B24 PCILHST_AD25 B54 3 3 V A25 PCILHST_AD24 A55 PCI_HST_AD4 B25 3 3 V B55 PCILHST_AD5 A26 PCI_HST_IDSEL2 A56 GND B26 PCILHST_CBE_N3 B56 PCILHST_AD3 A27 3 3V A57 PCILHST_AD2 B27 PCILHST_AD23 B57 GND A28 22 58 PCI B28 GND B58 PCILHST_AD1
100. DP465 Development Platform Overview IXDP465 Mezzanine Card Stacking v v Mezzanine Card Expansion Connector The mezzanine card expansion connector has 465 network processor specific features such as the expansion bus extension along with SPI and all 16 General Purpose Input Output GPIOs This IXP465 specific expansion connector includes a board identification scheme and future expansion signals Table 6 describes the expansion connector signals that are common across all mezzanine cards The Legend describing the color codes for the signals follows the table The standard connector signal definitions for each type of mezzanine card are listed in Chapter 5 Mezzanine Card Hardware Design The mezzanine card GPIO signals are routed to the network processor GPIO through the GPIO FPGA as shown in Figure The expansion signals n are connected to the network processor expansion signals for future expansion of processor peripherals Mezzanine Card Expansion Connector Common Signals Sheet 1 of 2 Signal Pin Signal Pin Signal Pin 1 8 V 1 C PCI 4 41 43 3 V 81 41 8V B C PCI 5 42 43 3 V 82 GND 3 C PCI 6 43 3 3 V 83 GND 4 C PCI 7 44 43 3 V 84 EX DATA17 5 C PCI 8 45 GND 85 EX DATA16 6 C PCI 9 46 GND 86
101. DR7 35 5 0 V 75 12 V 115 EX_ADDR6 36 3 3 V 76 2 5V 116 GND 87 5 0 V 77 12V 117 GND 38 9 3 V 78 2 5 V 118 EX_ADDR9 39 6 0 V 79 12V 119 EX ADDR8 40 3 3 V 80 25 120 Legend power signals purple IXP4XX Network Processor extended expansion bus signals green GPIO signals maroon MII signals connected to NPE B black MII signals common red interrupt signal gold The IXDP465 platform MII 1 expansion connector signal definition is described in Table 37 The power signals are 1 8 V 3 3 V and 5 0 V The expansion bus signals provide the 16 MSB of the data bus and the 1 MSB of the address bus The common amons all mezzanine cards and dedicated this mezzanine card only future expansion signals connect to the network processor module and are intended for use with future peripherals The SPI signals connect to the IXP465 network processor SPI peripheral The pe signals connect to the IXP465 re peripheral The GPIO signals connect to the GPIO FPGA The mezzanine card ID signals are used for board ID when stacking The Legend describing the color codes for the signals follows the table MII 1 Mezzanine Card Expansion Connector Signals Sheet 1 of 2 Signal Pin 4 Signal Pin 4 Signal Pin 1 8V 1 C PCI 4 41 3 8 V 81 1 8V 2 C PCI 5 42 3 9 V 82 GND 2 C PCI 6 43 3 9 V 83 GND 4 G POLT 44 3 3 V 84 EX DATA17 5 8 45 GND 85 EX DATA16 6 C PCI 9 46 GND 86 EX DATA19 7 EX BE N3 47 C FN 27 87
102. DY NO 64 ETHB TXDATA3 104 EX DATA15 25 EX IOWAIT N 65 GND 105 EX DATA14 26 ETHB INT N 66 ETHB TXDATA2 106 GND 27 EX_CS_N4 67 ETHB TXDATA1 107 GND 28 68 GND 108 EX_ADDR1 29 69 ETHB_TXDATAO 109 EX_ADDRO 30 3 3 V 70 ETH_MDC 110 EX_ADDR3 31 5 0 V 71 ETHB CRS 111 EX ADDR2 32 3 3 V 72 ETH_MDIO 112 EX_ADDR5 33 5 0 V 73 12V 113 EX_ADDR4 34 da V 74 2 5 V 114 EX_ADDR7 35 5 0 V 75 12V 115 Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 119 Mezzanine Card Hardware Design Table 77 5 3 5 3 1 September 2005 120 Ethernet PHY Connector Signals Sheet 2 of 2 Signal Pin Signal Pin Signal Pin EX_ADDR6 36 22 76 2 5V 116 GND 37 5 0 V 77 12V 117 GND 38 3 8 V 78 25V 118 EX ADDR9 39 5 0 V 79 12V 119 EX ADDR8 40 3 8 V 80 2 5 V 120 Legend power signals purple IXP4XX Network Processor extended expansion bus signals green GPIO signals maroon MII signals connected to NPE B black MII signals common red not used JTAG signals gray interrupt signal gold IXPVM465 Analog Voice Mezzanine Card Introduction The IXPVM465 Analog Voice mezzanine card 4x1 provides four ports of FXS phone and one port of FXO central office connectivity When power is not applied to the IXDP465 baseboard relays must automatically switch control from the baseboard and connect the four FXS port connectors directly
103. Design IXP465 Network Processor Module Future Needs Connector Pin Definitions Sheet 2 of 2 Signal Pin Signal Pin Signal Pin C_FN_36 37 C_FN_62 77 3 3 V 117 C_FN_37 38 C_FN_63 78 3 3 V 118 C_FN_38 39 C_FN_64 79 3 3 119 39 40 C FN 65 80 3 3 V 120 Legend power signals purple expansion bus signals green reserved black Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 109 Network Processor Module Hardware Design September 2005 110 Inte IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 UG I ntel Mezzanine Card Hardware Design Mezzanine Hardware Design 5 This chapter covers the following mezzanine cards that are used with the IXDP465 baseboard Section 5 1 IXPDSM465 ADSL UTOPIA Level 2 Mezzanine Card on page 111 Section 5 2 IXPETMA65 Ethernet Mezzanine Card on page 115 Section 5 3 IXPVMA65 Analog Voice Mezzanine Card on page 120 Section 5 4 IXPFRM465 Quad TI E1 Mezzanine Card on page 140 5 1 IXPDSM465 ADSL UTOPIA Level 2 Mezzanine Card 5 1 1 Introduction The IXPDSM465 ADSL UTOPIA level 2 mezzanine card for IXDP465 baseboard uses the Alcatel MTK 20150 chipset which consists of the Alcatel MTC 20156 and Alcatel MTC 20154 The MTC 20156 is the DMT modem ATM framer and controller chip of the chipset The MTC 20154 i
104. FPGA Indirect Data register 0x54100002 CS2 1 byte GPIO FPGA Revision register 0x54100003 CS2 1 byte GPIO FPGA Scratchpad register 0x54200000 CS2 1 byte LCD Display Command register 0x54300000 CS2 1 byte LCD Display Data register 0x54400000 CS2 1 byte CPU CPLD Revision register 0x54400001 CS2 1 byte CPU CPLD 2 Enable register 32 Mbytes MII 0 mezzanine card 32 Mbytes MII 1 mezzanine card 32 Mbytes MII 2 mezzanine card 3 3 6 Expansion Bus LCD Display A 2 x16 digit LCD display is provided on the expansion bus for software debug EX DATA 7 0 drives the display For information about accessing the LCD display refer to Section 3 22 1 3 LCD Display Instruction Register UG Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 39 IXDP465 Baseboard Hardware Design 3 4 Table 20 Note September 2005 40 intel BootROM An Intel 28F256J3C 64 pin BGA packaged flash is installed on the IXDP465 platform The flash is connected to IXP465 network processor s expansion bus The IXDP465 platform supports 8 Mbytes to 32 Mbytes of flash and ships with 32 Mbytes The IXDP465 platform always requests a starting boot address of 0x0 on EX ADDR 24 0 The IXDP465 platform is based on a 16 bit data bus The Clock Control CPLD sets the expansion bus after reset to 16 bit mode The Clock Control CPLD design does not suppo
105. Guide September 2005 Order Number 306462 Revision 004 97 Network Processor Module Hardware Design n Figure 17 September 2005 98 Network Processor Module Jumper Locations and Default Settings M IXP 3 3V XTAL OUT XTAL IN BYP SSCLK installed by default REFCLK SSCLK EN SSCLK JP46 667 MHz JP47 IXP 2 5V IXP COREV B5036 01 Four 120 pin connectors meet the IXP465 network processor module signaling and power requirements These are the same connectors as used on the IXDP425 development platform network processor The connectors are low profile 13 mm stack height surface mount with center ground planes The connectors are divided into four groups of signals NPE and peripherals expansion bus PCI Bus and future needs The 1 3 V core voltage 1 5 V for the 667 MHz version for the IXP465 is generated on this module Inte IXDP465 Development Platform User s Guide UG Order Number 306462 Revision 004 Table 70 UG Network Processor Module Hardware Design The JTAG header on this module is for standalone debugging A JTAG header with compatible connectors converters for the following ICE interfaces is provided Raven ICE Vision ICE A 10 nF decoupling capacitor is placed for each and Vccp pin in keeping with the silicon design guidelines The IXP465 network processor runs at 266 400 533 or 667 MHz selectab
106. Hardware Design Table 18 IXDP465 Overall Address Mapping Sheet 2 of 2 Start Address End Address Size Use 0x48000000 0x4FFFFFFF 128 Mbytes PCI 0x50000000 0x5FFFFFFF 256 Mbytes Expansion bus 0x60000000 0x63FFFFFF 64 Mbytes Queue manager 0xC0000000 0xCFFFFFFF 256 Mbytes Configuration 0xCD000000 0xCDFFFFFF 256 Mbytes USB Host Controller a After reset the expansion bus is mapped to 0x00000000 When the remap bit of the IXP465 network pro cessor expansion bus configuration register is set to 1 DDR is mapped to 0x00000000 and the expan sion bus is still accessible at 0x50000000 The IXDP465 platform expansion bus address map is defined in Table 19 Table 19 IXDP465 Expansion Bus Address Mapping Start Address Size Use 0x50000000 CSO 32 Mbytes Flash 0x52000000 CS1 32 Mbytes UTOPIA mezzanine card 0x56000000 CS3 0x58000000 CS4 0x5A000000 CS5 0x5C000000 CS6 32 Mbytes HSS 1 mezzanine card 0x5E000000 CS7 32 Mbytes HSS 0 mezzanine card 0x54000000 CS2 1 byte Clock Control CPLD Control Status register 0x54000001 CS2 1 byte Clock Control CPLD PCI Host Present register 0x54000002 CS2 1 byte Clock Control CPLD PCI Host 66 MHz Enabled register 0x54000003 CS2 1 byte Clock Control CPLD GPIO FPGA Programming register 0x54100000 CS2 1 byte GPIO FPGA Indirect Address register 0x54100001 CS2 1 byte GPIO
107. IXP465 Network Processor Module x16 Memory 97 97 41 2 IXP465 Core Voltage 100 4 1 3 PCI Bus 102 4 1 4 Expansion Bus 104 4 1 5 NPE and Peripheral Connector nnns 106 4 1 6 Future Needs Connector 2 2 4 00000 eene nennen enters nennen 107 5 Mezzanine Card Hardware Design n a 111 5 1 IXPDSM465 ADSL UTOPIA Level 2 Mezzanine Card 111 5 115 Introduction reri Pr eer nad 111 September 2005 Intel IXDP465 Development Platform User s Guide UG 4 Order Number 306462 Revision 004 In A UG tel Contents 5 1 2 ADSL Signals tac u a 113 5 2 465 Ethernet Mezzanine 4 00604040000 115 5 21 AMTPOCUCTON DD 115 5 2 2 Ethernet Card Signals 118 5 3 465 Analog Voice Mezzanine Card nenne 120 52321 ANTOdUCUON u oett RR wa atas asna qusanqa aus 120 5 3 2 Analog Voice Card Connector Interfaces
108. Illuminated gr GPIO LED Illuminated GPIO 6 GPIO 4 GPIO 2 GPIO 0 B5020 01 Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 37 Li IXDP465 Baseboard Hardware Design ntel 6 3 3 3 3 3 4 Table 17 3 3 5 Table 18 September 2005 38 Expansion Bus Clock Generation The expansion bus clock is generated from a CPLD and its frequency is software selectable by writing to the registers defined in Section 3 22 1 1 1 The selectable frequencies are 33 MHz 40 MHz 66 MHz or 80 MHz Individual expansion bus clocks are generated for the mezzanine cards including the network processor module by a 9 port zero delay buffer Cypress CY2309 The default setting after a reset is 33 MHz Expansion Bus Chip Selects The IXDP465 platform supports up to eight devices on the expansion bus The expansion bus chip selects listed in Table 17 are assigned to allow for support of IXDP425 mezzanine cards 1 legacy support Also the connectors used are identical in size and pinout as those used on the IXDP425 IXCDP1100 platform A second connector on each mezzanine card allows for expansion of the expansion data bus to 32 bits and future expansion Expansion Bus Chip Select Assignments Chip Select D
109. LD Voltage Filtering Pin Signal 5 3 3 V 20 3 3 V 38 3 3 V 51 3 3 V 88 3 3 V 98 3 3 V 26 1 8V 57 1 8V 5 4 4 4 CPLD JTAG Interface The CPLD JTAG interface consists of a 14 pin header P3 for programming the CPLD The connector uses the signals listed in Table 97 The CPLD signals TMS and TDI are pulled up to 3 3 V through a 10 resistor The signal has a 33 2 Q series resistor and is also pulled up to 3 3 V through a 1 KQ resistor See Figure 40 for the JTAG connector location UG Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 151 Mezzanine Card Hardware Design Table 97 Quad T1 E1 Card CPLD JTAG Interface Pin Assignments Pin Signal Pin Signal 1 GND 8 TDO 2 3 3 V 9 GND 3 GND 10 TDI 4 TMS 11 GND 5 GND 12 NC 6 TCK 13 GND T GND 14 NC September 2005 Intel IXDP465 Development Platform User s Guide 152 Order Number 306462 Revision 004 I ntel Mezzanine Hardware Design Figure 40 Quad T1 E1 Mezzanine Card Jumper and CPLD Header Locations JP13 1 8V_SEC 1 8v P3 P4 CPLD JTAG Header CPLD Debug Header JP15 T1 E1 Framer TDM Interface Jumpers B5042 01 5 4 5 T1 E1 Interface The IXPFRM465 Quad T1 E1 mezzanine card interface for the line signaling uses a PMC Sierra Framer LIU Quad Comet The Framer LIU device supports four 4 T1 E1 ch
110. LSB of the data bus the 24 LSB of the address bus chip select 4 clocking and control to the mezzanine card for switching I O and GPIO through software There are MII signals connected to NPE B and a few MII signals that are common across the MII devices The GPIO signals route to the GPIO FPGA The Legend describing the color codes for the signals follows the table Note The JTAG signals are not used Table 34 MII 0 Mezzanine Card Standard Connector Signals Sheet 1 of 2 Signal Pin Signal Pin Signal Pin 1 EX ADDR11 41 5 0V 81 2 EX ADDR10 42 3 8 V 82 3 EX ADDR13 43 MIIO GPIO2 83 4 EX ADDR12 44 GPIO3 84 EX DATA1 5 EX ADDR15 45 GND 85 EX DATAO 6 EX ADDR14 46 GND 86 EX DATA3 7 GND 47 87 EX DATA2 8 GND 48 GPIO4 88 MIIO GPIOO 9 EX ADDR17 49 89 GPIO1 10 EX ADDR16 50 RST N 90 EX DATA5 11 EX ADDR19 51 91 EX DATA4 12 EX ADDR18 52 ETHB TXEN 92 EX 19 ADDR 21 53 93 EX DATA6 14 EX ADDR20 54 ETHB RXDV 94 GND 15 EX ADDR23 55 GND 95 GND 16 EX_ADDR22 56 ETHB_RXCLK 96 EX_DATA9 17 GND 57 ETHB_RXDATA3 97 UG Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 59 IXDP465 Baseboard Hardware Design Table 34 September 2005 60 MII 0 Mezzanine Card Standard Connector Signals Sheet 2 of 2
111. ND CPLD Clock The input clock to the CPLD is a 32 768 MHz 50ppm oscillator This oscillator provides the clocking for the TDM interface as well as the clock to the other T1 E1 cards in the chain The oscillator is installed only when using the card in a standalone configuration or when the card is installed on the IXDP425 baseboard The IXDP465 platform provides the 32 768 MHz clock through the IXDP465 interface expansion connector Figure 38 shows the CPLD clock circuitry Two jumpers JP14 and JP15 are connected to the TI E1 framer TDM interface pins They are not currently used on the IXDP465 platform by default but they are used for easy access to the TDM signals for debugging JP14 connects the signals using the HMVIP mode of TDM on the framer and JP15 connects the signals to the backplane interface TDM mode of the framer Since the 465 network processor supports only 32 ports of voice on each HSS port HMVIP is the recommended mode of operation No jumpers need to be installed in these locations for the Quad card to use this mode See Figure 40 on page 153 for the jumper location TDM Interface External Clock Circuitry 3 3V 1 544MHz CLK32 768MHZ_EN CLK_32 768M CLK_32 768M_R 32 768 P_3 3V_FB4 R1 R1 Cin 600ohms 100MHz 33 2 33 2 aa Co 0 1uF 22pF 22pF 5 4 4 2 September 2005 150 CPLD Core Voltag
112. P11 2 I gt RxTP J R18 21 Ew gx RXRING1 men gt sien gt RVREF AS RVREF TXCM d TXCM1 I XRING11 XRING21 September 2005 160 Inte IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 UG intel Mezzanine Card Hardware Design Figure47 External Protection Circuitry for One Channel D gt XRING 11 21 S TXTIiP1121 mn B 1_ 3 gt RXRING1 T x miTE 5 TXTIP11 21 T pu 4 XRING11 21 T F TF RXTIP1_T_ r 2 RXRING1 T F 5 4 5 7 RJ 45 Connector Interface The Quad mezzanine card connects to the T1 E1 lines through an RJ 45 connector This connector is a 4 port ganged jack The housing is shielded for EMC compliance with only two 2 ground tabs on the connector There are no ground tabs on the rear of the connector due to the creepage and clearance specifications that need to be met for compliance Table 102 defines the pinout required on the RJ 45 jack Table 102 RJ 45 Connector Pin Assignments Pin Signal RXRING X RXTIP X NC TXRING X TXTIP X NC NC CO NI O om O N UG NC Inte IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 September 2005 161 Mezzanine Card Hardware Design September 2005 162 Inte
113. P465 Baseboard Hardware Design Table 28 SMII Jumper Block JP1 Pin Assignments Sheet 2 of 2 x Network Processor JP1 SMII Signal CFG CFG CFG CFG CFG CFG CFG CFG Signal Pin 1 2 4 5 6 7 8 7 C_UTP_IP_DATA7 8 SMII RXDATA4 IN IN IN IN 9 C ETHB TXCLK 10 SMII REFCLK R2 E i IN IN IN IN 11 C_ETHB_TXDATAO 12 SMII TXDATAO 13 ETHB TXDATA1 14 SMII TXDATA1 s IN IN IN IN 15 C_ETHB_TXDATA2 16 SMII TXDATA2 p sss 17 ETHB TXDATA3 18 SMII TXDATA3 19 RXDATAO 20 SMII_RXDATA0 a IN IN IN IN 21 C_ETHB_RXDATA1 22 SMII_RXDATA1 23 C ETHB RXDATA2 24 SMII_RXDATA2 IN IN IN IN 25 C_ETHB_RXDATA3 26 SMII_RXDATA3 IN IN IN IN 27 C_ETHB_CRS 28 SMII SYNC EE ss IN IN IN IN Notes Table Key JP1 Jumpers must NOT be installed IN JP1 Jumpers must be installed 3 8 2 NPE A MII Jumper Block JP2 The IXP465 network processor contains NPE pins that have multiple functions The NPE A MII jumper block connects specific shared NPE signals to the MII NPE A mezzanine card Table 29 shows the pin definitions for the NPE A MII jumper block as well as the JP2 jumper pin assignments which depend on the SMII Configu
114. P65 JP93 jumper must NOT be installed OPT JP65 JP93 jumpers can optionally be installed both jumpers IN to enable NPE C MII Mode Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 57 Li IXDP465 Baseboard Hardware Design ntel 6 3 9 Table 33 3 9 1 September 2005 58 Mil Mezzanine Card Connectors Support for MII is through three MII connectors When the six pack SMII is enabled these connectors are disabled through the clock control CPLD To be compatible with the IXDP425 IXCDP1100 platform the default mode is MII Mode That is enable the three mezzanine card connectors and disable the 6 port SMI IC by holding in reset A module containing a single Ethernet PHY wireless LAN Home PNA switch or repeater is supported on each connector The 802 3 standard MII connector can also be placed on a module to connect to the board s MII signals An SMII PHY can also be used on this interface For detailed information about the MII mezzanine cards see Section 5 2 IXPETM465 Ethernet Mezzanine Card The connector on the baseboard is Amp 179031 5 Table 33 describes the pull up and pull down resistors required on the MII interface The 10 KQ resistor value was chosen so a module can easily drive over the pull down Decoupling is handled on each module MII Resistors Signal Pull To Value Resistor Value RXDATA S3
115. Platform User s Guide 16 Order Number 306462 Revision 004 UG a ntel Intel IXDP465 Development Platform Overview Intel IXDP465 Development Platform Overview 2 The Intel IXDP465 Development Platform consists of a baseboard and network processor module plus add on mezzanine cards The IXDP465 baseboard features are USB connectors 1 Host 1 Device Two serial ports Four PCI slots for the IXDP465 as a PCI host system One PCI finger for the IXDP465 as a PCI option card PC EEPROM Flash memory SMII Multi Pack Interface LCD Display and LEDs Switches and Jumpers Power Regulators and Interface Connectors and Standoff provisions to Network Processor Module and all mezzanine cards The network processor module and mezzanine cards that are delivered as part of the IXDP465 platform are Intel IXP465 Network Processor DDR module x16 memory model One Intel IXPETM465 Ethernet PHY mezzanine card used in one of three MII mezzanine slots Optional mezzanine cards purchased separately include Intel IXPDSM465 ADSL UTOPIA level 2 mezzanine card Note This card is the same design as the one for the Intel IXDP425 Development Plat form Intel IXPVM465 Analog Voice mezzanine card 4 FXS 1 FXO Intel IXPFRM465 Quad mezzanine card Two additional Intel IXPETM465 Ethernet PHY mezzanine cards 3 total for the platform The following sections describe the features
116. TA13 23 EX ALE 63 ETHA RXDATAO 103 EX DATA12 24 EX RDY N2 64 TXDATA3 104 EX DATA15 25 EX IOWAIT N 65 GND 105 EX DATA14 26 ETHA INT N 66 ETHA TXDATA2 106 GND 27 EX CS N7 67 ETHA TXDATA1 107 GND 28 3 3 V 68 GND 108 EX ADDR1 29 69 ETHA TXDATAO 109 EX ADDRO 30 3 3 V 70 ETH MDC 110 EX ADDRS 31 5 0 V 71 ETHA_CRS 111 EX_ADDR2 32 29V ETH_MDIO 112 EX ADDR5 33 5 0 V 73 12V 113 EX ADDRA4 34 33 74 25V 114 EX ADDR7 95 5 0 V 7 12V 115 EX ADDR6 36 33 76 2 5 V 116 GND 37 5 0 V 7 12V 117 Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 67 IXDP465 Baseboard Hardware Design Table 38 Table 39 September 2005 68 MII 2 Mezzanine Card Standard Connector Signals Sheet 2 of 2 Signal Pin Signal Pin Signal Pin GND 38 78 25V 118 EX ADDR9 39 5 0 V 79 12V 119 ADDR8 40 3 3 V 80 25V 120 Legend power signals purple IXP4XX Network Processor extended expansion bus signals green GPIO signals maroon MII signals connected to NPE B black MII signals common red not used JTAG signals gray interrupt signal gold The IXDP465 platform MII 2 expansion connector signal definition is described in Table 39 The power signals are 1 8 V 3 3 V and 5 0 V The expansion bus signals provide the 16 MSB of the data bus and the 1 MSB of the address bus The common amons all mezzanine cards and dedicated t
117. TP Clock WRITE 583 OB J ETH SMII JP2 1 KEY Installed OO NOT Installed OO MII SMII UTOPIA B5021 01 Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 53 Li IXDP465 Baseboard Hardware Design ntel 6 3 7 3 Table 27 3 8 Configurations SMII features be disabled enabled each of the three NPEs when they connected to SMII ports As a result there are eight unique SMII configurations with different implementations of NPE functionality These eight possible configurations as defined in Table 27 and referred to in subsequent sections that cover NPE jumper pin assignments Select one of the following configurations which range from disabling all six SMII interface modes CFG 1 to enabling all six SMII interface modes across all three NPEs CFG 8 NPE SMII Configurations SMII Configuration Number HER SME Port CFG CFG CFG CFG CFG CFG CFG CFG 1 2 3 4 5 6 7 8 NPE C SMII 5 OFF ON OFF ON OFF ON OFF ON NPE A SMII 4 OFF OFF ON ON OFF OFF ON ON NPE B SMII 3 0 OFF OFF OFF OFF ON ON ON ON Notes Table Key OFF SMII functionality is disabled for this NPE ON SMII functionality is enabled for this NPE Once a specific SMII configuration is selected from Table 27 then the required NPE jumper pin assignmen
118. This decoding is necessary to multiplex this CPLD s internal registers the GPIO FPGA s internal registers and to access the LCD display Table 60 shows the external address decode performed by this CPLD Table 60 Clock Control CPLD External Address Decode EX_ADDR xx Expansion Bus Resource Physical Expansion Bus Address 24 23 22 21 20 0 0 0 0 0 Clock Gen CPLD Registers 0x54000000 0x5407FFFF 0 0 0 0 1 GPIO FPGA Chip Select 0x54100000 0x541FFFFF 0 0 0 1 0 LCD Display Instruction 0x54200000 0x542FFFFF 0 0 0 1 1 LCD Display Data 0x54300000 0x543FFFFF 1 1 1 x x Reserved 0x54400000 0x54FFFFFF Note Since the IXDP465 platform uses a 32 Mbyte flash device extended addressing must be used for the expansion bus decode versus the 16 Mbyte addressing used on the IXDP425 platform 0x54xxxxxx versus 0 52 UG Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 89 IXDP465 Baseboard Hardware Design 3 22 1 1 Table 61 3 22 1 1 1 Table 62 Table 63 September 2005 90 intel The Clock Control CPLD uses the lower five address bits of the expansion bus EX_ADDR4 EX ADDRO to further divide the address space for expansion bus slot 2 Table 61 shows the internal address decode performed by this CPLD CPLD Internal Registers Clock Control CPLD Internal Address Decode
119. _ALE 63 HSS_TXCLK1 103 EX_DATA12 24 EX_RDY_N2 64 104 EX DATA15 25 EX IOWAIT N 65 GND 105 EX DATA14 26 HSS1 INT N 66 HSS RXCLK1 106 GND 27 EX CS N6 67 107 GND 28 9 3 V 68 GND 108 EX ADDR1 29 69 HSS RXCLKO 109 EX ADDRO 30 3 9 V 70 110 EX ADDRS3 31 5 0V 71 HSS RXFRAMEO 111 EX ADDR2 32 23 72 HSS_RXDATAO 112 EX_ADDR5 33 5 0 V 73 12V 113 ADDR4 34 dua M 74 2 5 V 114 EX ADDR7 35 5 0V 75 12V 115 EX ADDR6 36 33 76 2 5 116 GND 37 5 0 V Jy 12V 117 GND 38 3 9 V 78 2 5 V 118 EX_ADDR9 39 5 0 V 79 12V 119 ADDR8 40 0 8 V 80 25V 120 UG Intel IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 47 IXDP465 Baseboard Hardware Design n Table 26 September 2005 48 Legend power signals purple extended expansion bus signals green GPIO signals maroon HSS1 signals primary black 550 signals secondary red interrupt signal gold The IXDP465 platform HSS 1 expansion connector signal definition is described in Table 26 The power signals are 1 8 V 3 3 V and 5 0 V The expansion bus signals provide the 16 MSB of the data bus and the 1 MSB of the address bus The common among all mezzanine cards and dedicated this mezzanine card only future expansion signals connect to the network processor module and are intended for use with future peripherals The SPI signals connect to the IXP465 network processor SPI peripheral Th
120. ace GPIO HSS interface and power signals This connector is pin for pin compatible with the IXDP425 HSS interface connectors All signals necessary to communicate with the analog ports are available on this connector Table 89 defines the IXDP465 interface standard connector signals The Legend describing the color codes for the signals follows the table UG Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 141 Mezzanine Card Hardware Design Table 89 IXDP465 Interface Standard Connector Signals Sheet 1 of 2 Signal Pin Signal Pin Signal Pin 1 ADDR11 41 5 0 V 81 2 EX ADDR10 42 3 3 V 82 3 EX ADDR13 43 GPIO2 83 4 EX ADDR12 44 GPIO3 84 EX DATA1 5 EX ADDR15 45 GND 85 EX DATA0 6 EX ADDR14 46 GND 86 EX_DATA3 7 GND 47 87 EX_DATA2 8 GND 48 GPIO4 88 GPIOO 9 EX_ADDR17 49 89 GPIO1 10 EX ADDR16 50 RST N 90 DATAS 11 EX ADDR19 51 91 EX DATA4 12 EX ADDR18 52 HSS SEC TXFRAME 92 13 ADDR21 53 93 DATA6 14 EX ADDR20 54 HSS_SEC_TXCLK 94 GND 15 EX_ADDR23 55 GND 95 GND 16 EX_ADDR22 56 HSS_SEC_TXDATA 96 EX DATA9 17 GND 57 HSS PRI TXDATA 97 DATA8 18 GND 58 GND 98 11 19 59 HSS_PRI_TXFRAME 99 EX_DATA10 20 EX_RD_N 60 HSS_PRI_RXDATA 100 21 GND 61 101 22 EX WR_N 62 HSS PRI RXFRAME 102 EX DATA13 23 EX ALE 63 HSS PRI TXCLK
121. ains the signaling from the IXP465 for the HSS MII UTOPIA SPI and interfaces IXP465 Network Processor Module NPE and Peripheral Connector Signals Sheet 1 of 2 Signal Pin Signal Pin Signal Pin 4 GND 41 ETHB TXEN 81 TXCLK 42 ETHB RXDATAO 82 ETHC RXCLK 43 ETHB RXDATA1 83 GND 44 ETHB RXDATA2 84 UTP OP CLK 45 ETHB RXDATAS3 85 IP 46 ETHB_RXDV 86 GND 47 ETHB COL 87 UTP OP DATAO 48 ETHB CRS 88 UTP OP DATA1 49 UTP OP FCO 89 HSS TX FRAMEO 10 GND 50 UTP OP SOC 90 HSS TX DATAO 11 UTP OP DATA2 51 UTP OP FCI 91 HSS TX CLKO 12 UTP_OP_DATA3 52 UTP_IP_FCO 92 HSS RX FRAMEO 18 GND 53 UTP_IP_SOC 93 HSS_RX_DATAO 14 UTP_OP_DATA4 54 UTP IP FCI 94 HSS RX CLKO 15 UTP OP DATA5 55 UTP IP ADDRO 95 HSS TX FRAME 1 16 GND 56 UTP IP ADDR1 96 HSS TX DATA1 17 UTP OP DATAG 57 IP ADDR2 97 HSS TX CLK1 18 UTP DATA7 58 UTP IP ADDR3 98 HSS RX FRAME 1 19 GND 59 P ADDR4 99 HSS RX DATA1 20 UTP IP DATAO 60 2 SDA 100 HSS RX CLK1 21 UTP DATA1 61 I2C_SCL 101 Inte IXDP465 Development Platform User s Guide UG Order Number 306462 Revision 004 intel Table 73 4 1 6 UG Network Processor Module Hardware Design IXP465 Network Processor Module NPE and Peripheral Connector Signals Sheet 2 of 2 Signal
122. al Pin Signal Pin GND 16 C NPE 0 56 2 GPIO7 96 EX DATA25 17 C NPE 1 57 GND 97 EX_DATA24 18 C_NPE_2 58 GND 98 EX_DATA27 19 C_NPE_3 59 MII2_GPIO8 99 EX_DATA26 20 C_NPE_4 60 MII2_GPIO9 100 GND 21 C NPE 5 61 2 GPIO10 101 GND 22 C NPE 6 62 2 GPIO11 102 EX DATA29 23 C NPE 7 63 GND 103 EX DATA28 24 C NPE 8 64 GND 104 EX DATAS1 25 C NPE 9 65 2 GPIO12 105 EX DATAS30 26 NPE 10 66 2 1 106 GND 27 C NPE 11 67 2 GPIO14 107 GND 28 C NPE 12 68 2 GPIO15 108 EX ADDR24 29 GND 109 SSPS CLK 30 C FN 32 70 GND 110 SSPS FRM 31 C FN 33 71 GND IDO 111 SSPS TXD 32 C FN 34 pis 3 3 V ID1 SSPS_RXD 33 C_FN_35 73 3 3 V ID2 113 SSPS_EXTCLK 34 C_FN_36 74 3 3 V ID3 114 5 0V 35 C FN 37 75 3 3 V ID4 115 5 0 V 36 C_FN_38 76 9 3 V ID5 116 C PCI 0 37 C FN 39 77 3 3 V ID6 G POI 1 38 C FN 40 78 3 3 V ID7 118 Q POL 2 39 FN 41 79 I2C SDA 119 G PGI 3 40 C FN 42 80 2 SCL 120 Legend power signals purple expansion bus signals green common future expansion signals blue on expansion signals bl ck SPI signals red 12C signals gold GPIO signals maroon UG Intel IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 69 Li IXDP465 Baseboard Hardware Design ntel 6 3 10 Table 40 3 11 Table 41 3 12 September 2005 70 USB Device A Type B USB device receptacle is provided at the board edge A 1 5 KQ pull up resistor is
123. als Sheet 2 of 2 Signal Pin Signal Pin Signal Pin EX_DATA21 11 EX_BURST 51 GND 91 EX_DATA20 12 EX_PAR3 52 GND 92 EX_DATA23 13 EX_PAR2 53 C_FN_63 93 EX_DATA22 14 EX_PAR1 54 GPIO5 94 GND 15 EX_PARO 55 GPIO6 95 GND 16 C NPE 0 56 GPIO7 96 EX DATA25 17 1 57 GND 97 EX_DATA24 18 C_NPE_2 58 GND 98 EX_DATA27 19 C_NPE 3 59 GPIO8 99 EX_DATA26 20 C_NPE 4 60 GPIO9 100 GND 2 C NPE 5 61 GPIO10 101 GND 22 C NPE 6 62 GPIO11 102 EX DATA29 23 C NPE 7 63 GND 103 EX DATA28 24 C NPE 8 64 GND 104 EX DATAS1 25 C NPE 9 65 GPIO12 105 EX DATASO 26 C NPE 10 66 GPIO13 106 GND 27 C_NPE_11 67 GPIO14 107 GND 28 C_NPE_12 68 GPIO15 108 EX ADDR24 29 GND 109 SSPS CLK 30 C FN 48 70 GND 110 SSPS FRM 31 C FN 49 71 111 SSPS TXD 32 C FN 50 72 IDO 112 SSPS RXD 33 C FN 51 73 ID1 113 SSPS_EXTCLK 34 C_FN_52 74 ID2 114 5 0V 35 C FN 53 75 ID3 115 5 0 V 36 C FN 54 76 ID4 116 C PCI 0 37 C_FN_55 77 ID5 117 PCI 1 38 C FN 56 78 ID6 118 39 C FN 57 79 2 SDA 119 C PCI 3 40 C FN 58 80 2 SCL 120 Legend power signals purple expansion bus signals green common future needs expansion signals blue dedicated future needs expansion signals black this card only Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 147 Li Mezzanine Card Hardware Design ntel
124. als follows the table Table 90 IXDP465 Interface Expansion Connector Signals Sheet 1 of 2 Signal Pin Signal Pin Signal Pin 18V 1 C PCI 4 41 3 3 V 81 18V 2 C POL 5 42 3 3 V 82 GND 3 C PCI 6 43 33V 83 GND 4 C PCI 7 44 3 3 V 84 EX DATA17 5 C PCI 8 45 GND 85 EX DATA16 6 C PCI 9 46 GND 86 EX DATA19 EX BE N3 47 C_FN_59 87 EX_DATA18 8 EX_BE_N2 48 C_FN_60 88 GND 9 EX_BE_N1 49 FN 61 89 GND 10 EX BE NO 50 C FN 62 90 EX DATA 1 11 EX_BURST 51 GND 91 EX_DATA20 12 EX_PAR3 52 GND 92 EX_DATA23 13 EX_PAR2 53 C_FN_63 93 EX_DATA22 14 EX PAR1 54 GPIO5 94 GND 15 EX PARO 55 GPIO6 95 GND 16 C NPE 0 56 GPIO7 96 UG Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 143 Mezzanine Card Hardware Design n Table 90 IXDP465 Interface Expansion Connector Signals Sheet 2 of 2 Signal Pin Signal Pin Signal Pin EX_DATA25 17 NPE 1 57 GND 97 EX_DATA24 18 C NPE 2 58 GND 98 EX DATA27 19 C NPE 3 59 GPIO8 99 EX DATA26 20 C NPE 4 60 GPIO9 100 GND 21 NPE 5 61 GPIO10 101 GND 22 C_NPE_6 62 GPIO11 102 EX DATA29 23 C NPE 7 63 GND 103 EX DATA28 24 NPE 8 64 GND 104 EX DATAS31 25 C NPE 9 65 GPIO12 105 EX DATAS3O 26 C NPE 10 66 GPIO13 106 GND 27 C_NPE_11 67 GPIO14 107 GND 28 C_NPE_12 68 GPIO15 1
125. amily docs ixp4xx htm Related External Documentation Title and Revision Location PCI Local Bus Specification Rev 2 2 http www pcisig com Specification 1 0 http www pcisig com UTOPIA Level 2 Specification Revision 1 0 http Awww atmforum com Universal Serial Bus Specification Revision 1 1 http Awww usb org JEDEC Double Data Rate DDR SDRAM Specification JESD79D http www jedec org Inte IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 September S Intel IXDP465 Development Platform Introduction n 1 5 Terminology Table 4 lists the acronyms and common terms used in this manual Table 4 List of Terminology Sheet 1 of 2 Acronym Descriptions ADSL Asymmetric Digital Subscriber Line Assert Logically active value of a signal or bit ATM Asynchronous Transfer Mode CPE Customer Premise Equipment CPLD Complex Programmable Logic Device DDR Double Data Rate DMA Direct Memory Access DSL Digital Subscriber Line E1 Euro 1 trunk line FPGA Field Programmable Gate Array FXO Foreign Exchange Office FXS Foreign Exchange Subscriber GPIO General Purpose Input Output HPI Host Port Interface HSS High Speed Serial port IP Internet Protocol IXP Internet Exchange Processor LAN Local Area Network
126. and interfaces on the IXDP465 baseboard and the mezzanine cards in more detail UG Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 17 Intel IXDP465 Development Platform Overview n 2 1 IXDP465 Baseboard The connections between the devices on the baseboard and mezzanine cards are shown in Figure 1 Details on each device are described in the following sections Figure 1 IXDP465 Baseboard Functional Block Diagram Ethernet 6 pack 7 g 1 2 2 z 8 o 0 5 I I m m lt O lt B P a Bog u w 2 z 5 z gt gt 2 E FA lt lt lt LLI a a a Z z 2 ER Expansion Bus 2 SPI GPIO UARTO SPI USB Host lt l USB Device Note Components yellow represent separate module mezzanine assemblies that external to the UART1 2 IXDP465 baseboard September 2005 Intel IXDP465 Development Platform User s Guide UG 18 Order Number 306462 Revision 004 Intel IXDP465 De velopment Platform Overview Network Processor Module The Network Processor Module NPM for the Intel IXDP465 Development Platform is Intel IXP465 Network Processor DDR Module x16 memory model See Chapter 4 Network Pro
127. annels The interfaces to the device are described in the following sections Section 5 4 5 1 Processor Interface Section 5 4 5 2 Line Interface Section 5 4 5 3 Power Interface UG Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 153 Mezzanine Card Hardware Design 5 4 5 1 Table 98 5 4 5 2 September 2005 154 Section 5 4 5 4 Clock Interface Section 5 4 5 5 Quad Port Transformer Interface Section 5 4 5 6 Protection Interface Section 5 4 5 7 RJ 45 Connector Interface Processor Interface Table 98 lists the Framer LIU processor interface pin definitions Quad Framer Processor Interface Pin Assignments Pin Signal B13 EX ADDR0 A14 EX_ADDR1 B14 EX_ADDR2 A15 EX_ADDR3 B15 EX_ADDR4 A16 EX_ADDR5 B16 EX_ADDR6 C15 EX_ADDR7 C16 EX_ADDR8 D16 EX_ADDR9 D15 EX_ADDR10 B3 EX_DATAO A2 EX_DATA1 Al EX_DATA2 B1 EX_DATA3 C1 EX_DATA4 C2 EX DATA5 D2 EX_DATA6 D3 EX_DATA7 D14 EX RD N E15 EX WR N E16 E1 T1 CS N E14 EX ALE E13 RST N F15 E1 T1 INT N Line Interface Table 99 defines the Quad Framer line interface pin definitions Inte IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 UG In Table 99 5 4 5 3 Table 100 UG Quad Framer Line Interface Pin Assignments Mezzanine Card Hard
128. are Design Table 80 5 3 2 4 Table 81 September 2005 126 Stacking Interface Standard Connector Signals Sheet 2 of 2 Signal Pin Signal Pin Signal Pin EX_ADDR2 32 3 3 V 72 HSS RXDATA1 112 EX ADDR5 33 5 0 V 73 12V 118 EX_ADDR4 34 3 3 V 74 25V 114 EX_ADDR7 35 5 0 V 75 12 118 EX_ADDR6 36 20 V 76 25 116 GND 37 5 0 V 77 12V 117 GND 38 78 2 5 V 118 EX ADDR9 39 5 0 V 79 12V 119 EX ADDR8 40 3 3 V 80 25 V 120 Legend power signals purple IXP4XX Network Processor extended expansion bus signals green GPIO signals maroon 550 signals primary black HSS1 signals secondary red not used JTAG signals gray interrupt signal gold Stacking Interface Expansion Connector The stacking interface expansion connector contains the extended expansion bus interface IXDP465 specific GPIO SPI future needs power signals Table 81 shows the stacking interface expansion connector signal definitions The Legend describing the color codes for the signals follows the table Stacking Interface Expansion Connector Signals Sheet 1 of 2 Order Number 306462 Revision 004 Signal Pin Signal Pin Signal Pin 1 8V 1 C PCI 4 41 33V 81 1 8V 2 C PCI 5 42 mov 82 GND 3 C PCI 6 43 83 83 GND 4 C_PCI_7 44 33V 84 EX DATA17 5 C PCI 8 45 GND 85 EX DATA16 6 C PCI
129. ate when the board recognizes it has been installed as an option card No soldering or rework is required to change from Host to Option mode There are four 3 3 V slots capable of holding full length PCI 2 2 cards PCI to miniPCI converters support miniPCI cards on the platform When configured as a 4 port PCI host the IXDP465 baseboard slots can operate at either 66 MHz or 33 MHz When the IXDP465 baseboard is the PCI host resets are driven to the PCI devices from the IXDP465 platform reset circuit When the IXDP465 baseboard is a PCI option device resets are driven to the IXDP465 platform through the PCI option fingers The IXDP465 platform has LEDs that indicate the PCI interface status Table 7 describes the PCI LEDs See Figure 14 on page 82 for the LED locations on the board Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 25 IXDP465 Baseboard Hardware Design n 6 6 Table 7 3 2 1 Table 8 PCI Architecture PCI to Adapter 1 1 1 1 1 1 1 I y PCI Host Slot 0 PCI Host Slot 1 PCI Host Slot 2 PCI Host Slot 3 PCI Option PCI LED Indicators LED LED Indication When ON Color PCI Host PCI is in host mode Green PCI Option PCI is in option mode Green PCI 66 MHz PCI is 66 MHz host mode only Green PCI 33 MHz PCI is 33 MHz host mode only Gree
130. been asserted then the expansion bus chip select drives that particular card The interrupt on each card is open drain to allow sharing of the interrupt sent to the IXP465 network processor Figure 24 ADSL Stacking Logic 3V3 JP1 t 1 3 EXPB A23 T t pre 310 OR GATE 9 JP3 QUAD XOR p 10 8 gt gt ADSL C8 N 1 OF OR GATE 21 D EXPB CS N OR GATE 5 1 2 Table 75 UG ADSL Card Signals The IXPDSM465 ADSL mezzanine card plugs into the UTOPIA level 2 connector on the IXDP465 baseboard using a 2x60 pin connector on the ADSL card This connector is compatible with the UTOPIA level 2 connector on the baseboard The ADSL card connector has on board signals used by the devices MTC 20156 DMT MTC 20154 AFE transmit driver LEDs on the ADSL card that are routed to it These signals include the following e Power ground e JTAG signals e UTOPIA signals Expansion bus signals Other connector signals The signals that exist on the ADSL UTOPIA level 2 mezzanine card are listed in Table 75 The Legend describing the color codes for the signals follows the table ADSL Connector Signals Sheet 1 of 2 Signal Pin Signal Pin Signal Pin 12 0 V 1 GND 41 UTP IP FCI 81 12 0 V R GND 42 UTP_OP_DATAO 82 GND 3 EX_ALE 43 GND 83
131. board is an option device the IDSEL is driven straight out of the PCI option connector to the IXDP465 baseboard Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 27 IXDP465 Baseboard Hardware Design Table 9 IDSEL Mappings Device IDSEL Signal Slot 0 Host mode PCI AD31 Slot 1 Host mode PCI 0 Slot 2 Host mode PCI AD29 Slot 3 Host mode PCI AD28 IXDP465 baseboard Option mode PCI IDSEL Note The PCI IDSEL signals for the IXDP465 baseboard are the same as those used on the baseboard IXMB425 for the IXDP425 development platform Table 10 PCI Host Slot 0 Pin Assignments Sheet 1 of 2 Pin Signal Pin Signal Pin Signal Pin Signal Al PCI_LHST_TRST_NO 3 3 V B1 PCI 12V NO B33 PCI HST CBE 2 A2 12 0 V A34 PCI HST FRAME 2 PCI HST TCKO B34 GND A3 PCI TMSO A35 GND B3 GND B35 IRDY A4 PCI HST TDIO A36 PCI TRDY B4 PCI HST TDOO B36 3 3V A5 5 0V A37 GND B5 5 0V B37 PCILHST_DEVSEL_N A6 PCI_HST_INTA_N A38 PCILHST_STOP_N B6 5 0 V B38 GND A7 PCI_HST_INTC_N A39 3 3V B7 PCI_HST_INTB_N B39 PCILHST_LOCK_N A8 5 0 V A40 PCILHST_SMBCLKO B8 PCI_HST_INTD_N B40 PCI A9 A41 PCI HST SMBDATO B9 PCI PRSNT1 NO B41 3 3 V A10 3 3V A42 GND B10 B42 PCI SERH A11 A43 PCI
132. cessor Module Hardware Design for details about this NPM The IXDP465 platform is used for development of products using the Intel IXP45X and Intel IXP46X Product Line of Network Processors Although the IXDP465 platform is shipped with a fully featured IXP465 network processor operating at 533 MHz the platform can be used to develop products that require either an Intel IXP460 Network Processor or an Intel IXP455 Network Processor These processors support subsets of the IXP465 processor features so certain features on the IXP465 can be disabled through software to emulate the IXP460 and IXP455 processors Emulation is accomplished by accessing the EXP UNIT FUSE RESET register via software and writing a 1 to the fuse bit number that corresponds to the feature to be disabled For a full description of this register see the Intel IXP45X and Intel IXP46X Product Line of Network Processors Developer s Manual See Table 2 on page 13 for the document order number Table 5 shows the default fuse bit settings for the fully featured IXP465 network processor Other rows in the table show the fuse bit settings that can disable a feature to emulate IXP460 or 455 network processor operation Table 5 Fuse Bit Settings for Network Processor Emulation Features of Intel IXP45X and Intel IXP46X Product Line of Network Processors G amp 8 2 5 ae
133. cond connector is for IXDP465 specific features and is referred to in this document as the expansion connector This second connector includes the expansion bus extension along with SPI C and all 16 GPIOs The IXDP465 specific expansion connector contains a board identification scheme and future expansion signals The IXPDSM465 ADSL UTOPIA level 2 mezzanine card uses the standard 120 pin connector only not the expansion connector because it is the same card designed for the IXDP425 development platform All mezzanine cards supported by the IXDP465 platform can be accessed simultaneously It is possible to boot and operate the IXDP465 platform over the NPE Ethernet ports with all the mezzanine cards installed and still have access to all test points All mezzanine cards are provided with the following voltages 1 8 V 2 5 V 43 3 V 5 0 V 12 0 V IXDP465 Mezzanine Card Attachment IXDP465 Standard Connector IXDP465 Expansion Connector Mezzanine Card Stacking Some IXDP465 mezzanine cards include the ability to stack up to eight cards This feature requires the mezzanine card to mirror the connectors from the bottom to the top to propagate the signals from the IXDP465 baseboard to each stacked card Figure 3 shows an example of stacking mezzanine cards two high Inte IXDP465 Development Platform User s Guide UG Order Number 306462 Revision 004 intel Figure 3 2 5 Note Table 6 UG Intel IX
134. ctor signals Expansion bus GPIO and expansion bus clock signals on NPE connectors on the IXDP465 baseboard are not used on the IXPETMA65 card and therefore are not routed to the 465 connector Inte IXDP465 Development Platform User s Guide UG Order Number 306462 Revision 004 In Table 77 UG Mezzanine Card Hardware Design The signals used on the IXPETM465 Ethernet mezzanine card are listed in Table 77 The Legend describing the color codes for the signals follows the table Ethernet PHY Connector Signals Sheet 1 of 2 Signal Pin Signal Pin Signal Pin 1 EX ADDR11 41 5 0 V 81 2 EX ADDR10 42 V 82 3 EX ADDR13 43 GPIO2 83 4 EX ADDR12 44 MIIO GPIO3 84 EX DATA1 5 EX ADDR15 45 GND 85 EX DATAO 6 EX ADDR14 46 GND 86 EX DATA3 f GND 47 87 EX_DATA2 8 GND 48 MIIO_GPIO4 88 MIIO_GPIOO 9 EX ADDR17 49 89 MIIO GPIO1 10 EX ADDR16 50 EX DATA5 11 EX ADDR19 51 91 EX DATA4 12 EX ADDR18 52 ETHB TXEN 92 EX DATA7 13 EX ADDR21 53 A 93 EX_DATA6 14 EX_ADDR20 54 ETHB_RXDV 94 GND 15 EX_ADDR23 55 GND 95 GND 16 EX_ADDR22 56 ETHB_RXCLK 96 EX_DATA9 17 GND 57 ETHB_RXDATA3 97 EX DATA8 18 GND 58 GND 98 EX DATA11 19 EX CLK MIIO 59 ETHB RXDATA2 99 EX DATA10 20 EX RD N 60 ETHB TXCLK 100 21 GND 61 ETHB RXDATA1 101 22 EX WR N 62 ETHB COL 102 EX DATA13 23 EX ALE 63 ETHB RXDATAO 103 EX DATA12 24 EX R
135. d power signals purple IXP4XX Network Processor extended expansion bus signals green SPI signals blue mezzanine card GPIO signals maroon expansion signals xxx n black mezzanine card ID signals red 2 signals gray 32 768 MHz clock signal gold Inte IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 UG Figure 4 UG Intel IXDP465 Development Platform Overview Component Placement Diagrams Figure 4 and Figure 5 show the placement drawings for the top and bottom of the IXDP465 platform IXDP465 Development Platform Components Top View BBBBBBBBEBBB PCI Host 0 PCI Host 1 PCI Host 2 2x16 LCD Display PCI Host 3 Inte IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 September 2005 23 Li Inte IXDP465 Development Platform Overview ntel Note Figure 5 displays two options for ADSL cards Either a UTOPIA or ST Micro mezzanine card may be installed in the appropriate connector slot Figure 5 IXDP465 Development Platform Components Bottom View o o o oo olo o September 2005 Inte IXDP465 Development Platform User s Guide UG 24 Order Number 306462 Revision 004 intel IXDP465 Baseboard Hardware Design IXDP465 Baseboard Hardware Design 3 3 1 3 2 UG This chapter covers th
136. d are intended for use with future peripherals The SPI signals connect to the IXP465 Order Number 306462 Revision 004 Inte IXDP465 Development Platform User s Guide Table 35 UG IXDP465 Baseboard Hardware Design network processor SPI peripheral The PC signals connect to the IXP465 Pc peripheral The GPIO signals connect to the GPIO FPGA The mezzanine card ID signals are used for board ID when stacking The Legend describing the color codes for the signals follows the table MII 0 Mezzanine Card Expansion Connector Signals Sheet 1 of 2 Signal Pin Signal Pin Signal Pin 1 8 V 1 C_PCI_4 41 22 V 81 1 8 V 2 POI 5 42 dv 82 GND 9 C PCI 6 43 3 3 V 83 GND 4 C_PCI_7 44 28V 84 EX DATA17 5 C PCI 8 45 GND 85 EX DATA16 6 C PCI 9 46 GND 86 EX DATA19 7 EX BE N3 47 C FN 11 87 EX DATA18 8 EX BE N2 48 C FN 12 88 GND 9 EX BE 1 49 C FN 13 89 GND 10 EX BE NO 50 C FN 14 90 DATA21 11 EX BURST 51 GND 91 EX DATA20 12 EX PAR3 52 GND 92 EX DATA23 13 EX PAR2 53 C FN 15 93 EX DATA22 14 EX PAR1 54 MIIO_GPIO5 94 GND 15 EX PARO 55 0 GPIO6 95 GND 16 C NPE 0 56 GPIO7 96 EX DATA25 17 G NPE 1 57 GND 97 EX DATA24 18 C NPE 2 58 GND 98 EX DATA27 19 G NPE 3 59 0 GPIO8 99 EX DATA26 20 C NPE 4 60 0 GPIO9 100 GND 21 C NPE 5 61 MIIO_GPIO10 101 GND 22 C_NPE_6 62 MIIO_GPIO11 102 EX_DATA29 23 C_NPE_7 63 GND 103 EX_DATA28 2
137. duca 11 11 1 4 Belated Documentation lll 12 1 5 Temio jo ogp ET 14 Intel IXDP465 Development Platform Overview sse 17 2 1 IXDP465 Baseboard ettet te teu e Re ERE edes 18 2 2 Network Processor ModuIe U U eee n nennen eren nennen nnn nennen 19 2 3 Mezzanine Cards aeter tug e 19 2 4 Mezzanine Card 20 2 5 Mezzanine Card Expansion Connector sse eene nennen 21 2 6 Component Placement Diagrams n nennen nene 23 IXDP465 Baseboard Hardware Design a 25 3 1 Network Processor Module 25 39 2 P qayna 25 3 2 1 PCI Signal Naming Conventions 26 3 22 PCI Mode of Operation 27 3 2 9 POL CIOCKING nm dee Eten neat ct tenente eee one Reap ee OPE xe sabi 27 3 2 4 PCI Host Mode Operation U nnns 27 3 2 5 PCI Option Mode Operation sess 33 3 9 34 33 1 Expansion Bus Loading 34 3 3
138. dware is set to the proper configuration values This is necessary for proper PCI operation Host vs Option and proper flash width The remaining configuration straps are not overridden Table 67 shows the configuration straps that are overridden by the clock control CPLD Table 67 Configuration Straps Override Configuration Strap Overridden Expansion Bus address Hardware Locked Value 0 16 bit logic 0 by CPLD 1 8 bit illegal PCI HOST 1 0 PCI Option when PCI OPT GND logic 0 T 1 PCI Host when PCI OPT GND logic 1 PCI 2 0 Arbiter disabled when PCI OPT GND logic 0 1 Arbiter Enabled when PCI OPT GND logic 1 PCI Test M illegal PCI TEST 3 0 PCI Test Mode illegal 1 PCI Normal Operation logic 1 by CPLD 0 8 16 bit logic 0 by CPLD 1 32 bit illegal 32 FLASH 7 September 2005 Intel IXDP465 Development Platform User s Guide UG 92 Order Number 306462 Revision 004 In 3 22 3 3 22 4 Figure 16 UG IXDP465 Baseboard Hardware Design PCI Host Clock Generation The clock control CPLD when in Host mode monitors the M66EN signal from each of the four host slots during Reset Active to determine the PCI Host slots frequency If any of the four are not in their active state logic 1 then the PCI host clock frequency is 33 MHz If all four are in their active state then the PCI host clock frequency is 66 MHz PCI Option Sensing T
139. e The CPLD core voltage is generated by a 1 8 V linear regulator The regulator is only installed when using a standalone configuration or when the card is installed on the IXDP425 baseboard The IXDP465 platform provides the core voltage through the IXDP465 interface expansion connector There is a jumper located on the Quad card that must be installed when using the Inte IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 UG I ntel Mezzanine Hardware Design card standalone or on the IXDP425 development platform This Jumper JP13 connects the signal 1 8V_SEC to the 1 8 V signal See Figure 40 for the location of this jumper Figure 39 shows the core voltage regulator circuitry Figure 39 Quad T1 E1 Mezzanine Card CPLD Core Voltage Regulator 3 3V 1 8V SEC 4 Lin R1 Ci Cout 7 4 75k 100pF 0 1uF 47uF R3 1k g _ Cin Cint R2 100uF gt 00u 0 1u Z 40k 5 4 4 3 CPLD Voltage Filtering The CPLD has two sources for input voltages The bank power is supplied by the 3 3 V supply Each power pin is decoupled with a 0 01 uF capacitor The CPLD core input voltage is powered by 1 8 V Each 1 8 V power pin is decoupled with a 0 01 uF capacitor Table 96 lists the CPLD voltage pins that are filtered using the capacitor values Table 96 Quad T1 E1 Card CP
140. e 54 IC EEPROM Addresses Address Length in Bytes Description 0x000 256 Free form configuration string used by VxWorks 0x100 6 Ethernet MAC address for NPE BO 0x106 6 Ethernet MAC address for NPE C 0x10C 6 Ethernet MAC address for NPE A 0x112 6 Ethernet MAC address for NPE B1 0x118 6 Ethernet MAC address for NPE B2 0x11E 6 Ethernet MAC address for NPE B3 0x124 20 Ethernet IP address for NPE B0 0x138 20 Ethernet IP address for NPE C 0x14C 20 Ethernet IP address for NPE A 0x160 20 Ethernet IP address for NPE B1 0x174 20 Ethernet IP address for NPE B2 0x188 20 Ethernet IP address for NPE B3 0x19C 20 Ethernet IP address for PCI NIC Slot 0 0x1B0 20 Ethernet IP address for PCI NIC Slot 1 0x1C4 20 Ethernet IP address for PCI NIC Slot 2 0x1D8 20 Ethernet IP address for PCI NIC Slot 3 Ox1EC 20 Reserved Notes addresses 6 bytes long and stored as binary For example 00 0E 0C 74 FF 08 is stored as 0x00 0x0E 0x0C 0x74 0xFF 0x08 2 IP addresses are up to 20 bytes long and stored as character strings For example 192 168 111 222 is stored as 0x31 0x39 0x32 0x2E 0x31 0x36 0x38 0x2E 0x31 0x31 0x31 0x2E 0x32 0x32 0x32 0x00 Most of the illustrations and photos in this manual show the factory default installation of the MII Ethernet PHY mezzanine card plugged into the MII 0 NPE B position As a result the six NPE MAC address labels on IXDP465 baseboard top side are not visible because they are underneath
141. e Abatron BDI2000 documentation for information about preparing to use the BDI2000 debugger The following steps assume the default configuration A server set up and running on your host system redboot bin and the BDI2000 configuration files for your hardware in your default TFTP directory Use telnet to connect to the BDI2000 and program flash as follows update myhost telnet bdi2000 Trying 192 168 200 100 Connected to bdi2000 Escape character is BDI Debugger for XScale 030918 Core 0 gt erase Erasing flash at 0x50000000 Erasing flash at 0x50020000 Erasing flash at 0x50040000 Erasing flash at 0x50060000 Erasing flash at 0x50080000 Erasing flash passed Core 0 gt prog redboot bin BIN Programming flash passed Core 0 gt verify Programming redboot bin please wait Verifying redboot bin please wait Verifying target memory passed Core 0 gt Inte IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 September 2005 167
142. e PC signals connect to the IXP465 IC peripheral The GPIO signals connect to the GPIO FPGA The mezzanine card ID signals are used for the board ID when stacking HSS mezzanine cards The Legend describing the color codes for the signals follows the table HSS 1 Mezzanine Card Expansion Connector Signals Sheet 1 of 2 Signal Pin Signal Pin 4 Signal Pin 1 8V 1 C PCI 4 41 3 3V 81 1 8V 2 C PCI 5 42 3 3V 82 GND 3 PCI 6 43 33V 83 GND 4 PCI 7 44 Bu NM 84 EX DATA17 5 C PCI 8 45 GND 85 EX DATA16 6 C PCI 9 46 GND 86 EX DATA19 7 EX BE N3 47 C FN 75 87 EX DATA18 8 EX BE N2 48 C FN 76 88 GND 9 EX 49 FN 77 89 GND 10 EX BE NO 50 C FN 78 90 EX DATA21 11 EX_BURST 51 GND 91 EX_DATA20 12 _ 52 GND 92 EX_DATA23 13 EX PAR2 53 C FN 79 93 EX DATA22 14 EX PAR1 54 HSS1 GPIO5 94 GND 15 EX PARO 55 HSS1 GPIO6 95 GND 16 NPE 0 56 HSS1_GPIO7 96 EX_DATA25 17 C_NPE_1 57 GND 97 EX_DATA24 18 C NPE 2 58 GND 98 EX DATA27 19 C NPE 3 59 HSS1 GPIO8 99 EX DATA26 20 NPE 4 60 HSS1 GPIO9 100 GND 21 NPE 5 61 HSS1 GPIO10 101 Inte IXDP465 Development Platform User s Guide UG Order Number 306462 Revision 004 I ntel IXDP465 Baseboard Hardware Design Table 26 HSS 1 Mezzanine Card Expansion Connector Signals Sheet 2 of 2 Signal Pi
143. e being a 33 MHz clock output The clock supports a maximum frequency of 33 MHz with various duty cycle steps The default state for GPIO14 is an input that is configured as an output user programmable The clock supports a maximum frequency of 33 MHz with various duty cycle steps Inte IXDP465 Development Platform User s Guide UG Order Number 306462 Revision 004 I ntel IXDP465 Baseboard Hardware Design The GPIO is designed for easy access by probing through a header Table 45 lists the GPIO header pin definitions Table 45 GPIO Header Pin Definition Pin Signal Pin Signal 1 3 3 V 11 GPIO8 2 5 0 V 12 GPIO9 3 GPIOO 13 GPIO10 4 GPIO1 14 GPIO11 5 GPIO2 15 GPIO12 6 GPIO3 16 GPIO13 7 GPIO4 17 GPIO14 8 GPIO5 18 GPIO15 9 GPIO6 19 GND 10 GPIO7 20 GND 3 13 1 GPIO FPGA Access Because of pin limitations on the FPGA access to this device is through indirect addressing Only the lower two address bits of the expansion bus are available to the FPGA for address decode To access the GPIO configuration registers the software must first set up the configuration register address in the Indirect Address register and then the actual access can occur by reading or writing to the Indirect Data register FPGA BASE ADD is found in the address decode table for expansion bus chip select 2 Table 46 lists the FPGA registers Table 46 GPIO FPGA Access Registers Expansio
144. e design details of all interfaces components and features contained on the Intel IXDP465 Development Platform baseboard Network Processor Module Interface The interface to the Network Processor Module NPM for the Intel IXDP465 Development Platform is provisioned on the baseboard assembly using four 120 pin connectors for the signaling and power requirements These connectors are low profile 13mm stack height surface mount connectors with center ground planes The connectors support NPES and peripherals the expansion bus the PCI bus and one connector which is reserved for future needs See Chapter 4 Network Processor Module Hardware Design for full details of the NPM interface connectors and pinouts For more information about the IXP465 network processor see the Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet PCI Interface The IXDP465 platform baseboard and network processor module can function as a four port PCI host or as a PCI option card When plugged into a PCI slot as an option card the IXDP465 baseboard senses that it is plugged in and automatically reverts to Option mode bootstraps using one of the option slot grounds The PCI architecture is shown in Figure 6 A set of isolation buffers placed between the IXP465 network processor and the four PCI host connectors ensures that PCI trace routing lengths are not violated in Option mode These buffers are placed in a high impedance st
145. e location The main difference between the Raven and visionICE systems is the specific implementation of nTRST for each debugger The Macraigor Raven implementation actively drives nTRST high and low The Wind River visionPROBE visionICE can configure nTRST Active or Open Collector only drive low The application note Recommended JTAG Circuitry for Debug with Intel XScale Microarchitecture Intel Document Number 273538 recommends a 10 kQ pull down on TRST Table 56 shows the emulator header pin definitions Emulator Connector Pin Assignments Pin Signal Pin Signal 1 3 3 V 2 3 3 V 3 IXP_TRST_N 4 GND 5 IXP_TDI 6 GND 7 IXP_TMS 8 GND 9 IXP_TCLK 10 GND 11 GND 12 GND 13 IXP_TDO 14 GND 15 SYSRESET_IXP_N 16 GND 17 GND 18 GND 19 GND 20 GND Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 83 IXDP465 Baseboard Hardware Design tel B Figure 15 JTAG Emulator and CPLD Programming Headers 2 B5023 01 3 19 Power Power rails are generated on the IXDP465 platform through a connector to an external standard ATX power supply The following voltages are provided 3 3 V 5 V 12 V 12 V and GND September 2005 Inte IXDP465 Development Platform User s Guide UG 84 Order Number 306462 Revision 004 Table 57 UG IXDP465 Baseboard Hardware Design The power sequence is 1 12 0 V 12 0
146. eatures such as the IXP465 network processor engine NPE functions are enabled by a specific revision of the Intel supplied software Refer to Table 2 Related Intel Documentation on page 13 for a list of all hardware software and platform documents that will assist in the development process In particular the following documents provide details on feature availability Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet has a complete list of available product features Intel IXP400 Software Programmer s Guide provides information on the features that are enabled in a particular software release The IXDP465 platform features that require enabling by software supplied by Intel are summarized in Table 1 Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 11 Intel IXDP465 Development Platform Introduction Table 1 1 4 September 2005 12 INTel Intel IXDP465 Development Platform Features Summary Features that do not require enabling software Features that require enabling software from Intel Intel XScale Core up to 667 MHz Cryptography unit random number generator and exponentiation unit PCI v 2 2 33 66 MHz Host Option Encryption Authentication AES AES CCM 3DES DES SHA 1 SHA 256 SHA 384 SHA 512 MD 5 USB 1 1 Device Controller Two High Speed Serial HSS interfaces USB 2 0 Host Controller High
147. ecified in Table 19 IXDP465 Expansion Bus Address Mapping on page 39 Note If you are updating an existing image that is in the FIS partition list then you must unlock the partition before you can update it using the command fis unlock lt NAME gt If there was no previous image then it is not possible to give NAME as an argument for the fis unlock command so it is recommended to unlock it using the command fis unlock f lt FLASH ADDRESS gt 1 IMAGE LENGTH When the update is complete lock the partition using the command fis lock NAME See Section A 3 Using RedBoot to Update RedBoot for an example 8 Load the image into RAM using the RedBoot load command load r v b 0x00100000 image bin 9 Check the output of the load command for the image length RedBoot reports this address range 0x00100000 0x00181234 The image length to store is 0x00181234 minus 0x00100000 This value is used when storing the image to flash 10 Use the fis unlock command to prevent the occurrence of an error report which states Illegal command Not a String 0x25DB8 gt fis unlock f lt FLASH ADDRESS gt 1 IMAGE LENGTH 11 Use the fis create command to store the image to flash gt fis create lt IMAGE NAME gt b 0 00100000 1 IMAGE LENGTH f XFLASH ADDRESS e 0x00000000 Note The fis create command is entered on a single line lt IMAGE NAME gt lt IMAGE LENGTH gt and FLASH ADDRESS are placeholders f
148. edicated SPI interface is used while on the IXDP425 development platform three GPIOs emulate the SPI interface FXO SPI Interface The SPI interface for access control and status information for the FXO Si3050 uses a 24 bit serial interface Four signals from the CPLD control this interface These signals are routed to the SPI interface for IXDP465 applications or to GPIO for IXDP425 applications The signals are FXO_CS_N shown as CSB in Figure 29 and Figure 30 SCLK SDI and SDO Figure 29 shows a typical SPI read of status information from the FXO port FXO Read Operation Using 8 Bit SPI CSB l Ny CONTROL XX ADDRESS OOO spo Figure 30 shows a typical SPI write of control information to the FXO port FXO Write Operation Using 8 Bit SPI SDO Figure 31 and Table 84 define the control byte for accesses through the SPI interface Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 131 Mezzanine Card Hardware Design Figure 31 Control Byte SPI Control Byte nw CID CID 2 TO CT CQ L C b T b J F n j eT a WESEZI EEESL t L ee L 4
149. egend power signals purple expansion bus signals green common future needs expansion signals blue Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 127 Li Mezzanine Card Hardware Design ntel z 5 3 3 5 3 3 1 Table 82 September 2005 128 Legend Continued dedicated future needs expansion signals black this card only SPI signals red 2 signals gold GPIO signals maroon ID signals teal not used gray one signal in group Analog Voice Card Stacking The IXDP465 platform supports stacking up to eight IXPVM465 Analog Voice mezzanine cards The board ID accesses the following four interfaces expansion bus accesses clocking framing and PCM voice interface Board ID Eight signals on the IXDP465 expansion interface connector define a unique address on each of the stacked analog voice mezzanine cards Since this connector does not exist on the IXDP425 development platform a mechanism has been implemented on the IXPVM465 Analog Voice mezzanine card 4x1 to emulate connection to the IXDP465 platform when the card is used an IXDP425 platform The IXDP465 platform ties IDO to ground and 107 ID1 to 3 3 V The XDVM465 Analog Voice mezzanine card pulls down IDO using a 100 kQ resistor and pulls up ID7 ID1 using a 49 9 resistor to function on the IXDP425 platform The signals must be shifted from the IXDP465 interface expan
150. er 2005 Order Number 306462 Revision 004 165 Updating the IXDP465 Flash Memory n Note September 2005 166 waiting for BOOTP information Ethernet eth0 MAC address 00 07 e9 16 34 72 IP 192 168 200 100 255 255 255 0 Gateway 192 168 200 254 Default server 192 168 200 254 RedBoot tm bootstrap and debug environment RAM Red Hat certified release version 2 01 built 08 06 48 Feb 22 2005 Platform IXDP465 Development Platform XScale BE Copyright C 2000 2001 2002 2003 2004 Red Hat P Ines RAM 0x00000000 0x08000000 0x00196c68 0x07f d1000 available FLASH 0x50000000 0x52000000 256 blocks of 0x00020000 bytes each Executing boot script in 3 000 seconds enter C to abort Load the primary RedBoot image to overwrite the current image in flash gt load r v b 0x00200000 redboot ROM bin Using default protocol TFTP N Raw file loaded 0x00200000 0x00278edb assumed entry at 0x00200000 gt fis unlock RedBoot gt fis create RedBoot b 0x00200000 1 0x0007A000 0x50000000 e 0x00000000 An image named RedBoot exists continue y n y Unlock from 0x51fe0000 0x52000000 Erase from 0x51fe0000 0x52000000 Program from 0x07fe0000 0x08000000 at 0x51fe0000 Lock from 0x51fe0000 0x52000000 fis lock RedBoot Lock from 0x50000000 0x50080000 Since RedBoot is running from RAM up to 0x00196c68 the image must be placed above this address at 0x00200000 3 Reset the boa
151. er 2005 Intel IXDP465 Development Platform User s Guide UG 6 Order Number 306462 Revision 004 ntel Contents 45 46 47 TAZE1 Input Clock tette 159 External Analog Interface Circuitry for One Channel sse 160 External Protection Circuitry for One Channel sse 161 Tables UG Intel IXDP465 Development Platform Features Summary sse 12 Related Intel Documentation na a 13 Related External Documentation u uu uu Q 13 EISt Of TerminOlogy EE 14 Fuse Bit Settings for Network Processor Emulation a 19 Mezzanine Card Expansion Connector Common 21 PGI LED Indicators Da ea ace Mawes albanien ede ved 26 PCI Signal Naming Conventions sse ennemi na 26 IDSEL 6 ua l He s eee ee en ence PRAE ERR el 28 PCI Host Slot 0 Pin Assignments 0000 28 PCI Host Slot 1 Pin Assignments 4 222 1 1 nenas 29 PCI Host Slot 2 Pin 30 PCI Host Slot 3 Pin 31 PCI Option Fingers Pin Assignments
152. esistor into the regulator compensation circuit JP48 is currently identified as 667 on the Network Processor Module To find the location of this jumper see Figure 17 on page 98 Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 101 Li Network Processor Module Hardware Design ntel 4 1 3 Figure 20 September 2005 102 PCI Bus Connector The PCI connector contains the signaling from the IXP465 network processor for the PCI Bus the USB the two UARTS and the GPIO The connector signal definition was chosen to allow for the best case PCI routing to the PCI option fingers on the IXDP465 platform Figure 20 depicts the mezzanine card connector pin out on the IXDP465 platform The even numbered pins are nearest to the bottom of the card near the PCI fingers on the platform and farthest from the network processor IXDP465 Development Platform Mezzanine Card Connector Pin out VA VN kN _ r3 J Z J x 4 d match the PCI bus connector with the PCI fingers the IXDP465 platform the PCI fingers definition must be analyzed Figure 21 depicts the PCI fingers with the fingers shown in green at the bottom of the figure being on the PCI B side or component side while the fingers shown in red at the top of the figure are on the PCI A side or solder side
153. evice Assignment CS0 Flash CS1 ADSL UTOPIA level 2 CS2 LCD Display GPIO FPGA Clock Control CPLD CS3 5509 CS4 MII 0 Ethernet Module 0 CS5 MII 1 Ethernet Module 1 CS6 5519 CS7 MII 2 Ethernet Module 2 a The LCD display the GPIO FPGA and the clock control CPLD share this chip select The clock control CPLD decodes upper address signals and produce three separate chip selects b CS3 and CS6 are routed to both HSS connectors so that mezzanine card modules can be stacked The chip selects are routed through zero Q resistors on the IXDP465 baseboard If a chip select is needed for a different device the resistor can be depopulated and the signal routed from the resistor to the new device as a jumper wire Expansion Bus Address Map Table 18 defines the overall address map for the IXDP465 platform The IXDP465 platform expansion bus address map is defined in Table 19 For additional memory mapping details of all 465 network processor interfaces and registers please refer to the Intel IXP45X and Intel IXP46X Product Line of Network Processors Developer s Manual IXDP465 Overall Address Mapping Sheet 1 of 2 Start Address End Address Size Use 0x00000000 OxOFFFFFFF 246 Mbytes Expansion bus DDR 0x00000000 Ox3FFFFFFF 1 Gbytes DDR 0x40000000 0x47FFFFFF 128 Mbytes Reserved Inte IXDP465 Development Platform User s Guide UG Order Number 306462 Revision 004 I ntel IXDP465 Baseboard
154. f 32 FLASH bit 0 0 16 bit data bus if 32 FLASH 0 1 8 bit data bus if 32 FLASH 0 UG Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 35 IXDP465 Baseboard Hardware Design Table 16 September 2005 36 Configuration Strapping Clock Settings In me Speed FX ADDR 23 EX_ADDR 22 EX_ADDR 21 Actual Core Speed 667 MHz 1 x X 667 MHz 667 MHz 0 0 0 667 MHz 667 MHz 0 0 1 533 MHz 667 MHz 0 1 0 266 MHz 667 MHz 0 1 1 400 MHz 533 MHz 1 x X 533 MHz 533 MHz 0 0 0 533 MHz 533 MHz 0 0 1 533 MHz 533 MHz 0 1 0 266 MHz 533 MHz 0 1 1 400 MHz 400 MHz 1 X X 400 MHz 400 MHz 0 0 0 400 MHz 400 MHz 0 0 1 400 MHz 400 MHz 0 1 0 266 MHz 400 MHz 0 1 1 400 MHz 266 MHz X x x 266 MHz Figure 7 shows the location and default settings of all Expansion Bus Address Strap Switches Figure 7 also shows the location of all GPIO LED switches which are discussed in more detail in Section 3 13 GPIO Inte IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 UG In Figure 7 UG IXDP465 Baseboard Hardware Design Switch Locations and Default Settings Expansion Bus Address Strap Switches Switch Position EI 1 Address Strap Floating Address Strap to Ground R148 rm GPIO 14 GIO 12 Switch Position GPIO 10 GPIO LED Not
155. frequency This determines the number of bits per frame The number of slots per frame is dependent upon the data type u Law A Law linear The data type is important to the IXP465 network processor HSS and the Silicon Laboratories analog interface IC configuration not this CPLD configuration Table 87 shows the bits and slots per frame for each PCM configuration PCM Modes PCM Mode Data Type Bits per Frame Slots per Frame PCM Clock 00 16 bit 256 16 2 048 MHz 00 8 bit 256 32 2 048 MHz 01 16 bit 512 32 4 096 MHz 01 8 bit 512 64 4 096 MHz 10 16 bit 1024 64 8 192 MHz 10 8 bit 1024 128 8 192 MHz 11 X X X Reserved Analog Port Reset Register The Analog Port Reset register is a read write register that resets each analog port A logic low 0 indicates the port is in a Reset state while a logic high 1 indicates that the port is in a normal mode of operation The value of this register after reset is xxx00000 The table below defines this register s bit definition x x x FXS3 FXS2 FXS1 FXS0 FXO SPI Interface The CPLD controls which analog port is being accessed using the SPI interface through the Analog Chip Select register The FXO SPI Interface and the FXS SPI Interface are not identical so care must be taken when communicating with the analog ports through these interfaces PCM Clocks and Framing The CPLD generates the PCM clocks and framing information fro
156. he IXDP465 platform automatically determines at reset time whether or not it is plugged into a PCI slot If it determines that it is plugged in it places itself in the PCI Option mode state In this case the clock control CPLD will override whatever the user configuration strap settings are set to If not then it automatically places itself in the Host mode state In this case the clock control CPLD overrides whatever the user configuration strap settings are set to Figure 16 depicts the circuit that generates the PCI HOST_N and PCI_OPT_N signals that generate the proper configuration bootstraps as well as in the PCI clock control CPLD PCI OPT CLK or onboard generated host clock PCI Mode Select Circuit Diagram PCI OPT GND NN NN A H N Intel IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 93 Li IXDP465 Baseboard Hardware Design ntel 6 3 22 5 3 22 6 Table 68 3 23 3 24 September 2005 94 PCI Isolation Buffer Control The PCI Bus is divided into three segments One section connects to the network processor module The second is connected to the four PCI slots Host mode The third is connected to the PCI fingers Option mode A set of tri state buffers isolates these sections The PCI mode select circuit shown in Figure 16 determines which set of buffers is enabled and which are tri stated The Enables for these buffers are controlled by the
157. his mezzanine card only future expansion signals connect to the network processor module and are intended for use with future peripherals The SPI signals connect to the IXP465 network processor SPI peripheral The PC signals connect to the IXP465 PC peripheral The GPIO signals connect to the GPIO FPGA The mezzanine card ID signals are used for board ID when stacking The Legend describing the color codes for the signals follows the table MII 2 Mezzanine Card Expansion Connector Signals Sheet 1 of 2 Signal Pin 4 Signal Pin 4 Signal Pin 4 1 8V 1 C PCI 4 41 V 81 1 8V 2 C PCI 5 42 2 9 V 82 GND 3 PCI 6 43 3 3 V 83 GND 4 C PCI 7 44 9 8 V 84 EX DATA17 5 PCI 8 45 GND 85 EX DATA16 6 C_PCI_9 46 GND 86 EX_DATA19 7 EX_BE_N3 47 C_FN_43 87 EX_DATA18 8 EX_BE_N2 48 C_FN_44 88 GND 9 EX_BE_N1 49 C_FN_45 89 GND 10 EX_BE_NO 50 C_FN_46 90 EX_DATA21 11 EX_BURST 51 GND 91 EX_DATA20 12 EX_PAR3 52 GND 92 EX_DATA23 13 EX_PAR2 53 C_FN_47 93 EX_DATA22 14 EX PAR1 54 2 GPIO5 94 GND 15 EX PARO 55 MIIl2 GPIO6 95 Inte IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 UG I ntel IXDP465 Baseboard Hardware Design Table 39 MII 2 Mezzanine Card Expansion Connector Signals Sheet 2 of 2 Signal Pin 4 Sign
158. icates that the IXP465 network processor SPI interface is being used for all SPI signals only on the IXDP465 platform while a logic high 1 will use GPIO for the SPI interface IXDP425 or IXDP465 development platforms The value of this register after reset is 00 The table below defines this register s bit definitions 7 6 5 4 3 2 1 0 SSPS Analog x x x x x x GPIO Clock Mode Source September 2005 136 PCM Mode Register The PCM Mode register is a read write register that selects the mode of operation for the PCM bus When operating in u Law or A Law mode an 8 bit PCM data width is required When operating in linear mode a 16 bit PCM data width is required The value of this register after reset is xxxxx000 The table below defines this register s bit definition Inte IXDP465 Development Platform User s Guide UG Order Number 306462 Revision 004 Table 87 5 3 5 2 5 3 5 3 UG Mezzanine Card Hardware Design The I2C_Enb bit is for mezzanine card identification discovery purposes only This function is performed at power up to identify the type of mezzanine cards installed on the IXDP465 platform The bus is shared between the onboard IXDP465 platform serial EEPROM and all five mezzanine card slots This bit is enabled 1 only during discovery of the IXDP465 platform mezzanine cards and must be disabled 0 during normal operation PCM 1 0 selects the PCM clock
159. ip select 0 If EXP TIMING CSO is reconfigured to Intel Synchronous mode during boot up the Expansion bus controller only ignores EX IOWAIT N during write cycles EXP MEM DRIVE See the values defined for Bit 5 EXP DRIVE USB CLOCK Controls the USB clock select 1 USB Host Device clock is generated internally 0 USB Device clock is generated from GPIO 0 USB Host clock is generated from GPIO 1 When generating a spread spectrum clock on OSC GPIO 0 is driven from the system board to generate a 48 MHz clock for the USB Device and GPIO 1 is driven from the system board to generate a 60 MHz clock for the USB Host 32 FLASH 1 32 bit data bus 0 8 16 bit data bus based on 8 16 FLASH bit EXP Configures the Expansion bus arbiter 0 External arbiter for Expansion bus 1 Expansion bus controller arbiter enabled EXP DRIVE Expansion bus low medium high drive strength The drive strength depends on the configuration of EXP DRIVE and EXP MEM DRIVE Bit 9 00 Reserved 01 Medium drive 10 Low drive 11 High drive PCI CLK Sets the PCI interface clock speed 0 33 MHz 1 66 MHz Reserved Reserved PCI ARB Enables the PCI Controller arbiter 0 PCI arbiter disabled 1 PCI arbiter enabled PCI HOST Configures the PCI Controller as PCI bus host 0 PCI as non host 1 PCI as host 8 16 Specifies the data bus width of the flash memory device i
160. latform Introduction Related Intel Documentation Title Document Location m IXDP465 Development Platform Quick Start 305825 IXPAXX Documentation Web Paget Inte IXDP465 Development Platform Specification 306509 Intel Representative Update Ee IXDP465 Development Platform Documentation N A IXP4XX Documentation Web Paget Inte IXP45X and Inte IXP46X Product Line of 306262 Documentation Web Paget Network Processors Developer s Manual Inte IXP45X and Intel IXP46X Product Line of 306261 IXPAXX Documentation Web Paget Network Processors Datasheet Inte IXP400 Software Programmer s Guide 252539 IXPAXX Documentation Web Paget Inte 400 Software Specification Update 273795 Documentation Web Paget Designing Embedded Networking Applications Essential Insights for Developers of Intel N A ia Network Processor Systems SART Inte XScale Core Developer s Manual 273473 IXP4XX Documentation Web Paget http www intel com design flcomp Intel StrataFlash Memory J3 Datasheet 290667 products j3 techdocs htm Intel PRO 100 Desktop Adapter technical Bp WWE documentation N A connectivity products desktop_adapters htm http www intel com design 2 Fast Ethernet Octal Transceiver 249241 network products lan docs Ixt9785_docs htm T This document is available at http www intel com design network products npf
161. lator circuit is the interface to the Quad Framer clock input for E1 operation The oscillator enable pins are software controlled to allow for easy switching between and modes of operation Figure 45 represents the circuitry required for the T1 E1 clock input Inte IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 UG I n Mezzanine Card Hardware Design Figure 45 Input Clock Circuitry 3 3v 7 1 544MHz T1_CLK_EN CLK 4 544M 2 048M CLK 1 544M 2 048M E1_T1_CLK VV NAA FPWR 1 544M L R1 R1 Lin t 33 2 0 600ohms 100MHz Cin Cou 0 1uF 0 1uF 22pF 22pF 3 3v 7 2 048MHz E1_CLK_EN 2 048M L l i i 600ohms 100MHz Cin Cint 0 1uF 0 1uF 5 4 5 5 Quad Port Transformer Interface The Quad T1 E1 mezzanine card interface to the line signaling on the PMC Sierra Framer LIU is through a quad port transformer The transformer provides IC side protection on each channel to suppress low voltage transients Table 101 defines the transformer interface pin definitions Table 101 Quad Port Transformer Interface Pin Assignments Sheet 1 of 2 Pin Signal Pin Signal 1 TXTIP14 24 21 RXRING1 T 2 3 3V 22 RXTIP1 T 3 XRING14 24 23 XRING11 21_T 4 RXTIP4 24 NC 5 RXRING4 25 TXTIP11 21_T 6 TXTIP13 23 26 RXRING2_T 7 GND 27 RXTIP2_T 8 XRING13 23 28 XRING
162. le through configuration straps with 533 MHz the default The IXP465 supports DDR Type 1 SDRAM operating at 266 MHz for 8 bit and 16 bit wide devices only The banks are accessed 32 bits at a time The maximum configuration is two banks Table 70 lists the supported memory configurations The IXP465 network processor module is designed to support the full range of DDR memory from 32 Mbytes through 512 Mbytes The module ships with 128 Mbytes and includes a user configurable option for ECC IXP465 Network Processor Module Supported Memory Configurations Total Memory 128 Mbyte Device 256 Mbyte Device 512 Mbyte Device 1024 Mbyte Device 32 Mbytes 2 chips 8M x16 64 Mbytes 4 chips 8M x16 2 chips 16M x16 128 Mbytes 4 chips 16M x16 2 chips 32M x16 256 Mbytes 4 chips 32M x16 2 chips 64M x16 512 Mbytes 4 chips 64M x16 A 10 nF decoupling capacitor is placed near each power pin A 4 7 uF capacitor is placed for each bank Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 99 Network Processor Module Hardware Design ntel m Figure 18 IXP465 Network Processor x16 Module Logical Block Diagram 4 1 2 IXP465 Core Voltage Generation The core voltage required for the IXP465 network processor is 1 3 V except for the 667 MHz version where the core voltage is 1 5 V The maximum current generated by this circuit is 3 0 A 2 A required The
163. lock REFCLK X1 on each MII Ethernet card is clocked using a 25 MHz oscillator on the IXDP465 baseboard A 25 MHz crystal can be used if desired but this is not populated on the IXPETM465 card The LXT971A TX and RX CLK supply transmit and receive clocks to the IXP465 network processor through the connector ENET TX CLK ENET RX CLK There are three LEDs DL 1 located at the sides of the MII Ethernet PHY mezzanine card They indicate 10 100 mode link and activity status 3V3_ENET analog power is generated on the MII Ethernet PHY mezzanine card from the 3 3 V power delivered to it by the IXDP465 baseboard This is needed for the LXT971A PHY and the transformer MII Ethernet Card Connectors IXP465 Network Processor Module IXP465 processor Board to Board Connector mo pe Board to Board Connector v INT 25 MHz Ethernet PHY Clock gt INT Magnetics RJ 45 Ethernet Card Signals The IXPETM465 Ethernet mezzanine card plugs into a 2x60 pin connector J1 on the mezzanine card that is compatible with the NPE B P14 NPE C P16 or NPE A P18 connector on the IXDP465 baseboard The mezzanine card connector carries on board signals used by devices LXT971A oscillator LEDs on the MII Ethernet card These signals include the following Power ground JTAG signals MII signals Other conne
164. m User s Guide UG Order Number 306462 Revision 004 I ntel IXDP465 Baseboard Hardware Design Table 24 HSS 0 Mezzanine Card Expansion Connector Signals Sheet 2 of 2 Signal Pin Signal Pin Signal Pin EX_DATA23 13 EX_PAR2 53 C_FN_63 93 EX_DATA22 14 EX_PAR1 54 550 5 94 GND 15 EX_PARO 55 HSSO_GPIO6 95 GND 16 C NPE 0 56 550 GPIO7 96 EX DATA25 17 1 57 GND 97 EX_DATA24 18 NPE 2 58 GND 98 EX_DATA27 19 C_NPE_3 59 HSSO_GPIO8 99 EX_DATA26 20 C_NPE_4 60 550 GPIO9 100 GND 21 C NPE 5 61 550 GPIO10 101 GND 22 C NPE 6 62 HSSO_GPIO11 102 EX_DATA29 23 C_NPE 7 63 GND 103 EX_DATA28 24 C_NPE_8 64 GND 104 EX_DATA31 25 C NPE 9 65 550 GPIO12 105 EX DATAS30 26 C NPE 10 66 550 GPIO13 106 GND 27 C NPE 11 67 550 GPIO14 107 GND 28 C NPE 12 68 HSSO_GPIO15 108 EX_ADDR24 29 GND 109 SSPS_CLK 30 C_FN_48 70 GND 110 SSPS_FRM 31 C_FN_49 71 GND IDO 111 SSPS_TXD 32 C_FN_50 72 3 3 V UDT 112 SSPS RXD 33 C FN 51 73 3 3 V ID2 113 SSPS EXTCLK 34 C FN 52 74 3 3 V ID3 114 5 0 V 35 C FN 53 75 3 3 V 104 115 5 0 V 36 C_FN_54 76 3 9 V 105 116 C_PCI 0 37 C_FN_55 77 3 3 V ID6 117 PCI 1 38 C FN 56 78 3 3 V ID7 118 G POI 2 39 C FN 57 79 2 SDA 119 C PCI 3 40 C FN 58 80 SCL 120 Legend power signals purple expansion bus signals green common future expansion signals blue 0 e
165. m the 32 768 MHz clock Only the CPLD on the first IXPVM465 Analog Voice mezzanine card in the stack generates these signals CPLDs on modules further up the stack receive these signals from the first mezzanine card See Section 5 3 3 3 Clocking Framing for further details The maximum number of Analog Voice cards in a stack is eight With five slots of PCM voice data per card the PCM is designed to support 64 slots Table 88 defines the clock frequency and number of bits in a frame clocks between frame synchronization pulses Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 137 Mezzanine Card Hardware Design n The CPLD must generate a frame synchronization pulse at the following rates In 2 048 MHz mode frame synchronization pulse every 256 PCM clocks In 4 096 MHz mode frame synchronization pulse every 512 PCM clocks In 8 192 MHz mode frame synchronization pulse every 1024 PCM clocks Figure 35 shows the 4 096 MHz mode with the 8 bit data type clocking and framing generated by the CPLD Figure 35 Operation with 8 Bit Slots HSS_TXFRAMEO 0 12 3 4 5 6 7 8 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 485 487 489 491 493 495 497 499 501 503 505 507 509 5 0 51 e HSS TXCLKO xl HSS RXFRAMEO 0 1 2 3 4 5 6 7 8 910 11 12 13 14 15 16 1718 19 20 21 22 23 24 25 26 27 28 29 30 31 323334 485 487 489 4
166. mary black HSS1 signals secondary red not used JTAG signals gray interrupt signal gold The IXDP465 platform HSS 0 mezzanine card expansion connector signal definitions are defined in Table 24 The power signals are 1 8 V 3 3 V and 5 0 V The expansion bus signals provide the 16 MSB of the data bus and the 1 MSB of the address bus The common among all mezzanine cards and dedicated this mezzanine card only future expansion signals connect to the network processor module and are intended for use with future peripherals The SPI signals connect to the IXP465 network processor SPI peripheral The PC signals connect to the IXP465 network processor Pc peripheral The HSS 0 GPIO signals connect to the GPIO FPGA The mezzanine card ID signals are used for board ID when the cards are stacked The Legend describing the color codes for the signals follows the table HSS 0 Mezzanine Card Expansion Connector Signals Sheet 1 of 2 Signal Pin Signal Pin Signal Pin 1 8V 1 C PCI 4 41 doi M 81 1 8V 2 5 42 V 82 GND 3 PCI 43 3 3 V 83 GND 4 C PGI 7 44 33 V 84 EX_DATA17 5 C_PCI_8 45 GND 85 EX_DATA16 6 C_PCI_9 46 GND 86 EX_DATA19 7 EX_BE_N3 47 C_FN_59 87 EX_DATA18 8 EX_BE_N2 48 C_FN_60 88 GND 9 EX_BE_N1 49 C FN 61 89 GND 10 EX BE NO 50 C FN 62 90 EX DATA21 11 EX BURST 51 GND 91 EX DATA20 EX PAR3 52 GND 92 Intel IXDP465 Development Platfor
167. mation please reference the baseboard schematics for exact resistor installation options that support different NPE A related platform configurations UG Inte IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 September 2005 77 IXDP465 Baseboard Hardware Design 3 14 Table 52 Table 53 3 14 1 September 2005 78 intel IC Interface This interface conforms to the IC bus standard developed by Phillips Corporation For detailed information refer to Peripherals for Microcontrollers The interface consists of a Serial Data Address signal SDA and a Serial Clock SCL The interface supports two performance modes standard 100 kbits s and fast 400 kbits s A 512 byte Philips PCF8594C 2TD is connected to the IXP465 network processor through the PC peripheral interface The 2 interface is routed to each mezzanine card through the expansion connector A jumper is included that write protects the device when it s not installed See Figure 11 for the jumper location All mezzanine cards respond to inquiries across the interface with their board status This status includes the Board ID type and Board Revision The status information provided by the interface is defined in Table 52 I C Status Information Bit 7 6 5 4 3 2 1 0 Status Board ID Board Revision The Board IDs for IXDP465 platform mezzanine cards are listed in Table 53 Mez
168. n PCI Signal Naming Conventions Table 8 describes how the PCI bus is divided into three distinct sections for naming convention purposes These conventions are also used for naming the signals in the IXDP465 platform schematics PCI Signal Naming Conventions PCI Section PCI Signal Naming for Section PCI host slots 1 4 PCI HOST abc xyz PCI option fingers PCI OPT abc xyz PCI connection to the processor PCI CPU abc xyz Note represents the signal name from the PCI specification September 2005 Intel IXDP465 Development Platform User s Guide UG 26 Order Number 306462 Revision 004 In 3 2 2 3 2 3 3 2 4 UG IXDP465 Baseboard Hardware Design PCI Mode of Operation Selection The PCI mode of operation is automatically sensed by the clock control CPLD See Section 3 22 4 PCI Option Sensing for more detailed information PCI Clocking A CPLD Complex Programmable Logic Device controls the PCI clock In Option mode the PCI clock is generated by the host through the PCI finger and the CPLD drives the PCI clock output to logic 1 to reduce noise In Host mode the CPLD drives the PCI clock The CPLD monitors the M66EN signals from the four slots and automatically sets up the proper clock frequency If all slots are 66 MHz capable the CPLD selects the 66 MHz clock If any slots are not 66 MHz capable the CPLD selects the 33 MHz clock A 66 MHz oscillator clocks
169. n Signal Pin Signal A30 GND A60 PCI HST REQ64 0 0 PCI HST AD19 B60 PCI ACK64 NO A31 PCI AD18 A61 5 0V B31 33 B61 5 0V A32 PCI HST AD16 A62 5 0V B32 PCI AD17 B62 5 0V For PCB designs that use PCI Host slots the following Host slot 0 signals need pull up resistors attached PCI TMSO PCI TDIO PCI INTA PCI HST INTB N PCI INTC PCI INTD PCI INTD PCI TRDY PCI STOP PCI HST SMBCLKO SMBDATO PCI PRSNT1 PCI PRSNT2 PCI HST IRDY PCI HST DEVSEL N PCI HST LOCK N PCI PERR PCI SERR PCI M66ENO PCI 64 NO PCI REQ64 NO PCI HST NO For PCB designs that use PCI Host slots the following Host slot 0 signals need pull down resistors attached PCI TRST NO PCI PCI HST TCKO Table 11 PCI Host Slot 1 Pin Assignments Sheet 1 of 2 Pin Signal Pin Signal Pin Signal Pin Signal A1 1 3 3V B1 PCI 12 N1 B33 PCI HST CBE 2 A2 12 0 V A34 PCI HST FRAME N B2 PCI HST TCK1 B34 GND A3 PCI TMS1 A35 GND B3 GND B35 PCILHST_IRDY_N A4 PCI HST TDH A36 PCI TRDY B4 PCI B36 3 3 V A5 5 0 V A37 GND B5 5 0 V B37 PCI HST_DEVSEL A6 PCI HST INTA N A38 PCI HST STOP N B6 5 0V B38 GND A7 PCI HST INTC N A39 3 3 B7 PCI HST INTB N B39 PCI HST LOCK N A8 50V A40 PCI HST SMBCLK1 B8 PCI HST INTD N B40 PCI HST PERR A9
170. n Signal Pin Signal Pin GND NPE 6 62 HSS1 GPIO11 102 EX DATA29 23 C NPE 7 63 GND 103 EX DATA28 24 C NPE 8 64 GND 104 EX DATAS31 25 C NPE 9 65 HSS1 GPIO12 105 EX DATAS3O 26 C NPE 10 66 HSS1 GPIO13 106 GND 27 C NPE 11 67 HSS1 GPIO14 107 GND 28 C NPE 12 68 551 GPIO15 108 EX ADDR24 29 GND 109 SSPS CLK 30 C FN 64 70 GND 110 SSPS FRM 31 C FN 65 71 GND IDO Tt SSPS TXD 32 C FN 66 72 3 3 V ID1 412 SSPS_RXD 33 C_FN_67 73 3 3 V ID2 113 SSPS_EXTCLK 34 C_FN_68 74 3 3 V ID3 114 5 0 V 35 C FN 69 75 3 3 V ID4 115 50V 36 C FN 70 76 3 3 V ID5 116 C PCI 0 37 C FN 71 77 3 3 V ID6 117 PCI 1 38 72 78 3 3 V ID7 118 C PCI 2 39 C FN 73 79 SDA 119 PCI 3 40 C FN 74 80 SCL 120 Legend power signals purple expansion bus signals green common future expansion signals blue expansion signals black SPI signals red I2C signals gold GPIO signals maroon 3 7 SMII Multi Pack Interface The IXDP465 platform supports a six pack SMII This interface uses a 6 gang RJ 45 connector with integrated magnetics It is designed as a 6 port switch function that supports simple 802 1 bridging as well as future expansion to 802 1Q VLAN For further information about what features are currently supported see the Intel IXP400 Software Programmer s Guide When the IXDP465 platform is configured to use the 6 pack SMII the three mezzanine card MII connectors are UG Inte IXDP465 Development Platform User s
171. n Bus Address Register FPGA_BASE_ADD 0 Indirect Address R W FPGA_BASE_ADD 1 Indirect Data R W FPGA BASE ADD 2 Revision RO FPGA BASE ADD 3 Scratch Pad R W 3 13 2 GPIO FPGA Control Signals The GPIO FPGA is configured and accessed through the expansion bus chip select 2 Table 47 defines the signals and FPGA pin locations for the expansion bus connection UG Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 73 IXDP465 Baseboard Hardware Design Table 47 GPIO FPGA Access Signals Sheet 1 of 2 Signal Description FPGA Pin Signal Description FPGA Pin FPGA_PROG_N Used during configuration of FPGA 106 GPIO3 Network Processor GPIO3 33 FPGA_INIT_N Used during configuration of FPGA 107 4 Network ProcessorGPIO4 34 FPGA_DONE Used during configuration of FPGA 104 GPIO5 Network Processor GPIO5 35 FPGA_CS_N Used during configuration of FPGA and during normal access by IXP465 network processor 160 GPIO6 Network Processor GPIO6 36 FPGA MODEO Used during configuration of FPGA This signal must be tied to GND 52 GPIO7 Network Processor GPIO7 37 FPGA_MODE1 Used during configuration of FPGA This signal must be tied to 3 3 V with a 10 kQ resistor 50 GPIO8 Network Processor GPIO8 41 FPGA MODE2 Used during configuration of FPG
172. n out match Connection to MII on NPE C Uses expansion bus chip select 5 Uses expansion bus ready 1 The mezzanine card expansion connector contains the following signal groups 465 SPI IXP465 C 465 extended expansion bus 16 GPIO Mezzanine Card ID byte stacking 32 pins for future expansion common to all mezzanine cards 16 pins for future expansion dedicated to this mezzanine card Additional power Inte IXDP465 Development Platform User s Guide UG Order Number 306462 Revision 004 Note Table 36 UG IXDP465 Baseboard Hardware Design The IXDP465 platform MII 1 standard connector signal definition is described in Table 36 The power signals are 2 5 V 3 3 V 5 0 V and 12 0 V The expansion bus signals provide the 16 LSB of the data bus the 24 LSB of the address bus chip select 5 clocking and control to the mezzanine card The interrupt signal from the mezzanine card is routed to the GPIO FPGA There are MII signals connected to NPE C and some MII signals are common across the MII devices The GPIO signals route to the GPIO FPGA The Legend describing the color codes for the signals follows the table The JTAG signals are not used Mil 1 Mezzanine Card Standard Connector Signals Sheet 1 of 2 Signal Pin Signal Pin Signal Pin 1 EX_ADDR11 41 5 0 V 81 2 EX_ADDR10 42
173. nal Jii l45 3 a 5 6 s7 8 1 C UTP OP DATA7 2 UTP_OP_DATA7 OPT OPT OPT OPT 3 C UTP IP 4 IP OPT OPT OPT 5 C UTP IP CLK 6 UTP IP OPT 7 C_UTP_OP_CLK 8 UTP_OP_CLK OPT OPT 9 C UTP OP 10 OP OPT OPT OPT OPT 11 C UTP OP DATA1 12 UTP OP DATA1 OPT OPT zs 13 C UTP OP 14 UTP OP DATA 15 UTP OP DATA3 16 UTP OP DATA3 OPT OPT OPT OPT 17 UTP OP DATM 18 DATA 19 C_UTP_IP_DATAO 20 UTP_IP_DATAO OPT OPT OPT OPT 21 UTP IP 22 UTP_IP_DATA1 23 UTP IP 24 UTP_IP_DATA2 OPT OPT 25 DATA3 26 UTP DATA3 OPT OPT OPT OPT 27 UTP IP 28 UTP_IP_DATA4 OPT OPT 29 C DATA5 30 UTP DATA5 OPT OPT OPT 31 DATA6 32 DATA6 OPT OPT OPT Notes Table Key JP3 jumpers must NOT be installed
174. nded expansion bus interface IXP465 specific GPIO SPI ID future needs power signals Table 79 shows the IXDP465 interface expansion connector signal definitions The Legend describing the color codes for the signals follows the table Table 79 IXDP465 Interface Expansion Connector Signals Sheet 1 of 2 Signal Pin Signal Pin Signal Pin 1 8 V 1 C PCI 4 41 3 3V 81 1 8V 2 C PCI 5 42 3 3V 82 GND 3 C PCI 6 43 3 3V 83 GND 4 C PCI 7 44 3 3V 84 EX DATA17 5 C PCI 8 45 GND 85 DATA16 6 C PCI 9 46 GND 86 DATA19 7 EX BE N3 47 FN 59 87 EX DATA18 8 EX BE N2 48 60 88 GND 9 EX BE N1 49 C FN 61 89 GND 10 EX BE NO 50 C FN 62 90 DATA 1 11 EX BURST 51 GND 91 DATA20 12 PAR3 52 GND 92 EX DATA23 13 EX PAR2 53 63 93 DATA22 14 PAR1 54 GPIO5 94 GND 15 55 GPIO6 95 UG Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 123 Mezzanine Card Hardware Design Table 79 September 2005 124 IXDP465 Interface Expansion Connector Signals Sheet 2 of 2 Inte IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 Signal Pin Signal Pin 4 Signal Pin GND 16 C NPE 0 56 GPIO7 96 EX DATA25 17 C
175. neesii nennen nennen nennen serene k aa nennen nns 52 11 Jumper Locations and Default Settings u 53 12 2G Address Bytes EE dee Ene ER REESE XR S rx dene 79 13 MAG Address Labels uu uuu terre treten orte irse eee gus ud du gane 80 14 EP oC Opin u 82 15 JTAG Emulator and CPLD Programming Headers 84 16 PCI Mode Select Circuit Diagram eene nten nnne nennen nnns 93 17 Network Processor Module Jumper Locations and Default Settings 98 18 IXP465 Network Processor x16 Module Logical Block 100 19 465 Core Voltage Generation Logic sse nnne 101 20 IXDP465 Development Platform Mezzanine Card Connector Pin out 102 21 IXDP465 Mezzanine Card Connector Pin out aa 103 22 ADSL Card Block Diagram ssssssssssssssessseee nennen senten enn aasma nnne nnns 112 23 ADSL Card Component 112 24 ADSL Stacking LogiC 5 2 t fenore reo p ER pa ean ra Eae agis 113 25 Ethernet Card Jumper Locations and Default Settings 116 26 MII Ethernet Card Connectors
176. nges A ede Coe teo EE a DS CP dade de 95 70 465 Network Processor Module Supported Memory Configurations 99 71 465 Network Processor Module PCI Bus Connector 103 72 465 Network Processor Module Expansion Bus Connector Signals 105 73 465 Network Processor Module NPE and Peripheral Connector Signals 106 74 465 Network Processor Module Future Needs Connector Pin Definitions 108 75 ADSL Connector Signals rette tu baee aed ca dd bare e 113 76 Jumper Address Bit nnns 117 77 Ethernet PHY Connector Signals sssssssssssssssseseeeee nennen nnne nnne 119 78 IXDP465 Interface Standard Connector 122 79 IXDP465 Interface Expansion Connector 123 80 Stacking Interface Standard Connector 125 81 Stacking Interface Expansion Connector 126 82 Analog Voice Card Unique Stacking 128 83 Analog Voice Card Unique Stacking IDs and Expansion Bus Addresses 129 84 Control Byte Bit 132 85 Analog Voice Card CPLD Pin Assignments
177. nt Platform Introduction Inte IXDP465 Development Platform Introduction 1 1 1 1 2 1 3 UG Purpose This document provides detailed design information for the Intel IXDP465 Development Platform The IXDP465 platform includes the basic blocks of an Intel IXP465 Network Processor based system including the IXP465 network processor DDR memory PCI and connectors through which UTOPIA level 2 MIL EXS FXO and power devices are connected Several mezzanine cards designed in conjunction with the IXDP465 baseboard plug in through the UTOPIA level 2 MIL or HSS connectors See Chapter 5 Mezzanine Card Hardware Design for detailed information about the design of these mezzanine cards Intended Audience The intended audience for this document includes hardware architects and developers who are developing both hardware and software for applications based on the Intel IXP45X and Intel 46 Product Line of Network Processors The IXDP465 platform is designed in conjunction with the design of several modules to meet the market requirements for a flexible customer oriented platform This platform demonstrates the IXP465 network processor capabilities in a system and enables 465 software development Customers can base their designs on portions of the IXDP465 platform design Prerequisites The Intel IXDP465 Development Platform supports all available features for the Intel IXP465 Network Processor Many f
178. ntains 8 port SMII PHY Intel HBLXT9785HC DO 853353 to connect the NPE SMII interface to the onboard Ethernet magnetics not the mezzanine card MII interface Figure 9 depicts this connection Only six of the eight SMII PHY Ethernet ports ports 0 5 are used by the IXDP465 platform Inte IXDP465 Development Platform User s Guide UG Order Number 306462 Revision 004 Figure 9 UG IXDP465 Baseboard Hardware Design Octal PHY Connection to Magnetics To Twisted Pair Network 0 001 uF 20kV 20 1 The 1000 transmit load termination resistor typically required is integrated in the LXT9785 9785E 2 The 1000 receive load termination resistor typically required is integrated in the LXT9785 9785E 3 Recommended 0 1 capacitor to improve EMI performance The IXDPA465 platform applies impedance matching techniques to the differential Tx and Rx pairs of each Ethernet port The IXDP465 platform allows all Ethernet modes to be tested This includes MII through the three mezzanine cards and SMII through the multi port PHY The IXDP465 platform has user selectable jumpers to test these options as shown in Figure 11 Figure 10 shows the logical connections of NPE signals to the specific types of configurations i e MIT SMII UTOPIA Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 51 IXDP465 Baseboard Hardware Design ntel Figure
179. on signals PCI INTB PCI INTC PCI INTD PCI OPT SMBCLK PCI OPT SMBDAT Expansion Bus Expansion Bus Loading The IXDP465 platform has been tuned to drive up to eight loads but the devices on the expansion bus may not be able to quickly drive such a large load To compensate for this timings on the expansion bus are adjusted using network processor internal registers If an edge rises slowly due to low drive strength the IXP465 network processor must wait an extra cycle before the value is read There are no buffers to increase drive strength on the expansion bus although customers can choose to add buffers in their own designs To test the maximum performance of the expansion bus 80 MHz there is a set of isolation resistors 0 Q on the expansion bus All isolation resistors are identified on one of the last pages of the baseboard schematics provided in the IXDP465 documentation kit The resistors break the expansion bus into two sections Removal of these resistors will reduce the expansion bus load When removed the only devices on the expansion bus are the HSS 1 mezzanine card connectors flash and configuration switches Expansion Bus Configuration Straps The expansion bus address lines EX_ADDR24 EX ADDRO are used for configuration strapping options during boot up At the de assertion of reset the values on these lines are read to determine the board configuration The defined configuration stra
180. on the card define this Ethernet address which must be defaulted to Address 0 by setting all jumpers to shunt pin 2 and pin 3 The remaining three ground jumpers JP1 JP3 JP4 are not installed Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 115 Mezzanine Card Hardware Design Figure 25 Ethernet Card Jumper Locations and Default Settings GND JP1 Not installed GND JP4 Not installed i ETHERNET ADDRESS JUMPERS A1 A2 A3 A4 Q Q Q 9 Q 9 JP7 JP8 AO 6 O JP2 JP5 JP6 GND JP3 Not installed B5037 01 map Table 76 shows the PHY mapping for the jumpers The IXDP465 platform can accommodate up to three IXPETMA65 Ethernet mezzanine cards Each MII Ethernet PHY mezzanine card maps its own address to the IXP465 network processor s PHY Inte IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 September 2005 6 UG Intel Mezzanine Card Hardware Design Table 76 Jumper Address Bit Mapping Jumper JP8 JP7 JP6 JP5 JP2 PHY Address Bit A4 A3 A2 A1 A0 Low 2 3 Low 2 3 Low 2 3 Low 2 3 Low 2 3 00 0 Low 2 3 Low 2 3 Low 2 3 Low 2 3 High 1 2 0
181. ons for all LEDs on the IXDP465 platform September 2005 Intel IXDP465 Development Platform User s Guide UG 80 Order Number 306462 Revision 004 In Table 55 UG Intel IXDP465 Development Platform LED Indicator Definitions IXDP465 Baseboard Hardware Design Frome i LED Indication when ON Color nad Location Power LED 12 V 12 V power is on Green ON Baseboard Power LED 5 V 5 V power is on Green ON Baseboard Power LED 12 V 12 V power is on Green ON Baseboard Power LED 43 3 V 3 3 V power is on Green ON Baseboard Power LED 41 8 V 1 8 V power is on Green ON Baseboard PCI LED Option PCI operating as option Green OFF Baseboard PCI LED 66 MHz PCI operating at 66 MHz Green ON Baseboard PCI LED 33 MHz PCI operating at 33 MHz Green OFF Baseboard PCI LED Host PCI operating as host Green ON Baseboard CPU Power LED Reset IXP465 system is in reset Green OFF NPM CPU Power LED 3 3 V 3 3 V power is applied to IXP465 Green ON NPM CPU Power LED 2 5 V 2 5 V power is applied to IXP465 Green ON NPM CPU Power LED COREV 1 3 V 1 5 V power is applied to IXP465 Green ON NPM EL m 15 GPIO 15 0 driven low Green ON Baseboard GPIO LEDs Power LED 2 5 V power is on Green ON Baseboard FLASH STATUS Flash device is being programmed Yellow OFF Baseboard Inte IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 September In
182. or arguments that are required by the fis create command lt gt the name that identifies the image in flash A corresponding load command can use this name lt IMAGE LENGTH gt the length in bytes of the image previously loaded into RAM Use the length as determined in step 9 lt IMAGE ADDRESS gt the location in flash where the image will be written If the image will be loaded at boot up by jumper selection use the address specified in Table 20 on page 40 The flash addresses available to be mapped to 0 0 by the jumpers are 0x50800000 0x51000000 0x51800000 Check the output of the fis list command to see which segments have been programmed as available September 2005 Intel IXDP465 Development Platform User s Guide UG 164 Order Number 306462 Revision 004 A 2 Note A 3 Note UG Updating the IXDP465 Flash Memory Creating a Backup Copy of RedBoot As a precaution before updating the primary RedBoot image create a backup RedBoot image in flash The backup version can be used in case there is a problem updating the primary RedBoot image and or the new image fails to operate properly To load an additional copy of RedBoot into flash follow these steps 1 The Verify that JP127 JP128 labeled A23 and A24 on the PWB are installed For jumper location see Figure 11 Jumper Locations and Default Settings on page 53 Load the redboot_ROM bin image into flash
183. or IXDP425 applications The signals are FXSn CS N shown as CS in Figure 32 Figure 33 and Figure 34 SCLK SDI and SDO The four FXS ports are daisy chained as shown in Figure 32 September 2005 132 Inte IXDP465 Development Platform User s Guide UG Order Number 306462 Revision 004 Figure 32 Figure 33 UG Mezzanine Card Hardware Design FXS Port SPI Daisy Chaining SDITHRU SDIO 5011 Figure 33 shows typical SPI read of status information from FXS port FXS Read Operation Through 8 Bit SPI Cara ES 771 s High Impedance 3 SCLK s e SDO Figure 34 shows a typical SPI write of control information to the FXS port Inte IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 September 2005 133 Mezzanine Card Hardware Design n Figure 34 FXS Write Operation Through 8 Bit SPI Dorit Cara SCLK s e s jeje eju u o ot ae a oo 500 High Impedance 5 3 5 Analog Voice Card CPLD The CPLD on the IXPVM465 Analog Voice mezzanine card generates the following signals PCM clocks PCM frame synchronization pulses analog port resets analog port chip selects interrupt to the IXDP465 platform engaged disengage relays and the master clock reports board and interrupt status Table 85 defines the CPLD pin definitions Table 85 Analog Voice Card CPLD Pin Assignments Shee
184. pping is shown in Table 15 The expansion bus address lines are connected to DIP switches SW3 SW4 and SWS in Figure 7 allowing a line to be pulled low 0 level in Table 15 and Table 16 using an on board 1 pull down resistor with the switch in ON position If the line is not pulled down using the switch in OFF position then a weak pull up internal to the IXP465 network processor will pull the line high 1 level in Table 15 and Table 16 The expansion bus address lines address lines correspond to the bits in Table 15 Several of the straps are overridden by the clock control CPLD for the hardware to operate properly The DIP switch locations on the board and the default values are shown in Figure 7 on page 37 September 2005 Intel IXDP465 Development Platform User s Guide UG 34 Order Number 306462 Revision 004 Intel Table 15 IXDP465 Baseboard Hardware Design Configuration Strapping Options EX_ADDR Bit Name Description 24 Reserved Reserved 23 21 Clock Setting See Table 16 for details 20 17 Customer Customer defined bits 16 11 Reserved Reserved 10 IOWAIT CSO 1 EX IOWAIT N is sampled during the read write Expansion bus cycles 0 EX IOWAIT N is ignored for read and write cycles to Chip select 0 if EXP TIMING CSO is configured to Intel mode Typically IOWAIT 50 must be pulled down to Vss when attaching Synchronous Intel StrataFlash on Ch
185. ration CFG selected in Table 27 To find the location of 7 2 on the IXDP465 baseboard see Figure 11 Table 29 NPE A MII Jumper Block JP2 Pin Assignments Sheet 1 of 2 in Network Processor JP2 Signal CFG CFG CFG CFG CFG CFG CFG CFG in Signal Pin 1 2 3 4 5 6 7 8 1 C_UTP_IP_CLK 2 ETHA_RXCLK C_UTP_OP_CLK 4 ETHA_TXCLK OPT OPT 5 OP DATAO 6 ETHA_TXDATAO 7 C OP DATA 8 ETHA_TXDATA1 OPT OPT 9 C UTP OP DATA2 10 ETHA_TXDATA2 OPT OPT OPT OPT 11 C UTP OP DATAS 12 TXDATA3 OPT OPT 13 C UTP OP DATA4 14 TXEN OPT OPT 15 16 OPT 17 C IP DATA 18 RXDATA1 19 C UTP IP 20 2 21 C DATA3 22 RXDATA3 OPT m UG Inte IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 September 2005 55
186. rd by powering it off and on and verify that RedBoot starts up gt Checking for SMII configuration EthAcc Mac cannot enable port 2 MAC address not set Initializing SMII for NPE B NPE C NPE A done Trying NPE B no PHY found waiting for BOOTP information Ethernet eth0 MAC address 00 0e 0c 63 cd cf IP 192 168 200 100 255 255 255 0 Gateway 192 168 200 254 Default server 192 168 200 254 RedBoot tm bootstrap and debug environment ROM Red Hat certified release version 2 01 built 08 07 53 Feb 22 2005 Inte IXDP465 Development Platform User s Guide UG Order Number 306462 Revision 004 A 4 UG Platform IXDP465 Development Platform Copyright C 2000 2001 2002 2003 2004 Red Ha RAM 0x00000000 0x08000000 Redboot gt Updating the IXDP465 Flash Memory XScale BE 0 0002 488 0 07 41000 FLASH 0 50000000 0 52000000 available 256 blocks of 0x00020000 bytes each 4 Use the RedBoot fis list command to review the flash segment contents as known to RedBoot Example RedBoot gt fis list Name FLASH addr RedBoot 0x50000000 redboot bak 0x50800000 FIS directory 0x51 FE0000 RedBoot config Ox51FFF000 Mem addr 0x50000000 0x50800000 0 51 0000 Ox51FFFO000 Length 0x00080000 0x00080000 0x0001F000 0x00001000 Entry point 0x00000000 0x00000000 0x00000000 0x00000000 Using an External Debugger to Update RedBoot Refer to th
187. register values 185 28 Network Processor GPIO28 21 GPIOO Network Processor GPIOO 29 GPIO291 Network Processor GPIO29 22 GPIO1 Network Processor GPIO1 30 GPIO30t Network Processor GPIO30 23 GPIO2 Network Processor GPIO2 31 GPIO31f Network Processor GPIO31 24 T Network Processor GPIO16 GPIO31 are not available on the IXP465 network processor and are reserved for future use 3 13 3 GPIO FPGA Configuration Registers To avoid conflicts where multiple hardware drivers are driving the same signal simultaneously the following rule must be followed to properly configure the I O The destination signal input must be configured first then the source output is configured As an example if GPIO4 is to be connected to HSS0 INT then GPIO4 must be configured first since it is an input then HSS0 INT configured since it is an output All signals GPIO from the network processor and all signals from the mezzanine cards are configured as inputs after a reset Each mezzanine card GPIO has two configuration registers associated with the signal The Attach register defines to which network processor GPIO the signal is attached The Direction register defines the signal direction The mezzanine card signal direction must be the opposite direction of the network processor GPIO Table 48 defines the configuration register bit definitions UG Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 75
188. rt 8 bit mode A JTAG Header is provisioned on the platform to allow re programming of the CPLD for designs that require customized modes See Figure 15 on page 84 for the header location The FLASH STS pin on the flash is tied to a yellow LED to indicate when the device is being programmed on the IXDP465 platform It is pulled up through a 10 KQ resistor since it is an open drain output A 0 1 uF ceramic capacitor is connected between each of the device s three Vcc pins and ground In addition a 4 7 uF electrolytic capacitor is placed between V cc and GND at the array s power supply connection Two jumpers JP127 JP128 on expansion bus address signals EX ADDR24 and EX ADDR23 partition the flash device into four sections Table 20 defines the flash sectioning See Appendix A Updating the IXDP465 Flash Memory for information about how to use RedBoot to update the content of these sections Flash Sectioning installed installed 0x00000000 0x01FFFFFFF 32 Mbyte RedBoot installed not installed 0x00800000 0x00FFFFFFF 8 Mbyte VxWorks bootrom not installed installed 0x01000000 0x01FFFFFFF 16 Mbyte not installed not installed 0x01800000 0x01FFFFFFF 8 Mbyte UTOPIA Connector The IXDP465 platform supports up to 31 PHYs on the UTOPIA level 2 interface the maximum amount supported by the IXP465 network processor through a 2x60 pin mezzanine card connector Amp 5 179010 5
189. s Sheet 2 of 2 Pin Signal Pin Signal Pin Signal Pin Signal A7 PCI HST A39 3 3 V B7 INTB B39 PCI HST LOCK A8 50V A40 PCILHST_SMBCLK3 B8 PCI HST INTD N B40 PCI HST PERR A9 A41 HST SMBDAT3 9 HST PRSNT1 N3 B41 33V A10 33V A42 GND B10 B42 PCI HST SERR AM A43 PAR B11 PCI HST PRSNT2 N3 B43 3 3 14 A44 PCI HST AD15 B14 B44 PCI HST CBE 1 A15 PCI HST 45 3 3 B15 GND B45 PCILHST_AD14 A16 33V 46 HST AD13 B16 PCI CLK3 B46 GND A17 PCI HST N3 A47 PCI HST AD11 B17 GND B47 PCI HST AD12 A18 GND A48 GND B18 PCI HST REQ B48 PCI HST AD10 A19 A49 PCI HST AD9 B19 33V B49 PCI M66EN3 A20 PCI 5 AD30 A50 GND B20 PCI HST_AD31 B50 GND A21 33V A51 GND B21 PCI HST_AD29 B51 GND A22 PCI 5 AD28 A52 HST CBE NO B22 GND B52 PCILHST_AD8 A23 PCILHST_AD26 A53 3 3 V B23 PCI HST_AD27 B53 PCILHST_AD7 A24 GND A54 PCI_HST_AD6 B24 PCI HST_AD25 B54 33V A25 PCI 5 AD24 A55 PCILHST_AD4 B25 33V B55 PCI AD5 A26 HST IDSEL3 A56 GND B26 PCI HST CBE B56 PCI HST AD3 A27 33V A57 PCI HST AD2 B27 PCI HST AD23 B57 GND A28 PCI 5 AD22 A58 PCI HST ADO B28 GND B58 PCI HST AD1 A29 PCI 5 AD20 A59 33V B29 PCI HST AD 1 B59 33V A30 GND A60 PCI HST REQ64 3 PCI HST
190. s the supporting analog front end The 2x60 pin J3 connector on the IXPDSM465 ADSL card plugs into the 2x60 pin UTOPIA level 2 connector on the IXDP465 baseboard See Section 3 5 UTOPIA Connector for a description of this UTOPIA connector on the baseboard Figure 22 shows connectors on the card and Figure 23 shows the JTAG header and jumper locations The IXPDSM465 ADSL mezzanine card design supports multiple channels through the single channel Alcatel MTK 20150 chipset using a stackable design 12 V 5 V 3 3 V and 42 5 V digital voltage rails are provided from the IXDP465 baseboard to the UTOPIA level 2 connector Other voltages both digital and analog required for the card are derived from these voltages on the IXPDSM465 ADSL card The 12 V voltage rail is derived from the 3 3 V voltage rail on the card JP4 JP5 JP6 headers provide access to the GND plane The majority of the signals needed to support the DSL card are Expansion Bus and UTOPIA level 2 data interface signals The Alcatel DMT on the ADSL card receives its RX and UTP TX CLK through the 33 33 MHz oscillator already implemented on the IXDP465 baseboard The same oscillator on the baseboard provides OP CLK and IP CLK signals to the IXP465 network processor UG Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 111 Mezzanine Card Hardware Design n Figure 22 ADSL Card Block Diagram
191. sion connector to the stacking interface expansion connector i e IXDP465 ID6 IDO shifted to Stacking ID7 ID1 with the 100 kQ pull down on the next module up the chain filling in a logic low for IDO Table 82 shows the unique IDs for each stacked analog voice 4x1 mezzanine card Analog Voice Card Unique Stacking IDs Stacking Slot ID7 IDO 0 11111110 11111100 11111000 11110000 11100000 11000000 10000000 00000000 NI oJ mo AJOJN Intel IXDP465 Development Platform User s Guide UG Order Number 306462 Revision 004 intel 5 3 3 2 Table 83 Note 5 3 3 3 UG Mezzanine Card Hardware Design Expansion Bus Accesses The IXDP465 platform expansion bus contains 25 address bits EX_ADDR24 EX_ADDR0 The expansion address signals EX_ADDR23 through EX_ADDR21 select one of up to eight stacked mezzanine cards Table 83 shows the unique IDs along with the upper expansion bus address signals of each stacked Analog Voice 4x1 card used for expansion bus accesses Analog Voice Card Unique Stacking IDs and Expansion Bus Addresses Stacking Slot ID7 IDO EX_ADDR23 EX_ADDR21 0 11111110 000 1 11111100 001 2 11111000 010 3 11110000 011 4 11100000 100 5 11000000 101 6 10000000 110 7 00000000 111 The IXP425 network processor on the IXDP425 development platform only uses 24 bits EX_ADDR24 does not exist so for compatibility it is not used on
192. ss bus chip select 7 clocking and control to the mezzanine card The interrupt signal from the mezzanine card is routed to the GPIO FPGA The MII signals are connected to NPE A The MII signals are common across the MII devices The GPIO signals route to the GPIO FPGA The Legend describing the color codes for the signals follows the table The JTAG signals are not used Inte IXDP465 Development Platform User s Guide UG Order Number 306462 Revision 004 In Table 38 UG IXDP465 Baseboard Hardware Design MII 2 Mezzanine Card Standard Connector Signals Sheet 1 of 2 Signal Pin 4 Signal Pin Signal Pin 1 EX ADDR11 41 5 0V 81 2 EX ADDR10 42 3 9 V 82 3 EX ADDR13 43 MII2 GPIO2 83 4 EX ADDR12 44 MII2_GPIO3 84 EX_DATA1 5 EX_ADDR15 45 GND 85 EX DATAO 6 EX ADDR14 46 GND 86 EX DATAS 7 GND 47 87 EX DATA2 8 GND 48 MII2 GPIO4 88 2 GPIOO 9 EX ADDR17 49 89 MII2 GPIO1 10 EX ADDR16 50 RST N 90 EX DATA5 11 EX ADDR19 51 91 EX DATA4 12 EX ADDR18 52 ETHA TXEN 92 EX DATA7 13 EX ADDR21 53 93 EX DATA6 14 EX ADDR20 54 ETHA RXDV 94 GND 15 EX ADDR23 55 GND 95 GND 16 EX ADDR22 56 ETHA RXCLK 96 EX DATA9 17 GND 57 RXDATAS3 97 EX DATA8 18 GND 58 GND 98 EX DATA11 19 EX CLK MII2 59 ETHA RXDATA2 99 EX DATA10 20 EX RD N 60 ETHA TXCLK 100 21 GND 61 ETHA RXDATA1 101 22 EX WR N 62 ETHA COL 102 EX DA
193. st power external fo P 0 80 consumption on the board processor Must be less than Operational System on con 70 C with ambient of 50 C Ambient temperature must be cenam 9 maintained at 50 C as measured at least 2 inches from the 9 System under test product Non 0 80 Operational 20 70 C non condensing Ambient for a 30 day duration 3 25 Regulatory Guidelines The IXDP465 platform complies with all regulations for sale of laboratory telecommunications equipment in the following countries regions USA Canada EU Asia Australia New Zealand Note This product contains encryption logic and must meet all applicable export regulations for sale outside of the USA UG Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 95 IXDP465 Baseboard Hardware Design September 2005 96 Inte IXDP465 Development Platform User s Guide Order Number 306462 Revision 004 UG intel Network Processor Module Hardware Design Network Processor Module Hardware Design 4 4 1 4 1 1 UG This chapter covers the following Network Processor Module NPM that is compatible with the IXDP465 baseboard IXP465 Network Processor Module x16 DDR memory model 465 Network Processor Module x16 Memory Model Introduction This section presents the target specifications for the IXP465 Network Processor Module NPM x16 memor
194. t 1 of 2 Pin Signal Pin Signal Pin Signal Pin Signal 1 TEST3 26 1 8V 51 3 3 V 76 EX_DATA3 2 SSPS_CLK 27 EX_CLK 52 SCLK 77 ID6 3 TEST2 28 TEST5 53 FXO_TGD_N 78 ID7 4 TEST1 29 RELAY_P 54 ID5 79 FXO_RGDT_N 5 3 3 V 30 EX_WR_N 55 ID4 80 FXO_RESET_N 6 EX_ADDRO 31 GND 56 ID3 81 FXSO_RESET_N 7 EX ADDR1 32 EX RD N 57 1 8 V 82 FXS1_RESET_N 8 EX_ADDR2 33 INT_OUT_N 58 ID2 83 TDO 9 EX_ADDR3 34 FXO_INT_N 59 ID1 84 GND 10 EX ADDR4 35 FXSO INT N 60 IDO 85 FXS2 RESET N 11 EX ADDR 21 36 FXS1 INT N 61 EX DATAO 86 FXS3 RESET N 12 EX ADDR22 37 FXS2 INT N 62 GND 87 FXO RC 13 EX ADDR23 38 33V 63 EX DATA1 88 3 3 V 14 HSS_RXCLK0 39 FXS3 INT_N 64 EX_DATA2 89 FXO_TGDE_N 15 HSS_RXDATAO 40 INT_N_IN 65 GPIOO 90 FXSO_CS_N 16 HSS RXFRAMEO 41 12C_SCL 66 GPIO1 91 FXS1_CS_N September 2005 Intel IXDP465 Development Platform User s Guide UG 134 Order Number 306462 Revision 004 I ntel Mezzanine Card Hardware Design Table 85 Analog Voice Card CPLD Pin Assignments Sheet 2 of 2 Pin Signal Pin Signal Pin Signal Pin Signal 17 HSS TXCLKO 42 I2C_SDA 67 GPIO2 92 FXS2_CS_N 18 HSS_TXDATAO 43 SSPS_FRM 68 GPIO3 93 FXS3_CS_N 19 HSS TXFRAMEO 44 SSPS_RXD 69 GND 94 FXO_CS_N 20 33 45 TDI 70 GPIO4 95 EX_CS_N 21 GND 46 SSPS_TXD 71 EX_DATA7 96 CLK32_OUT 22 CLK32_IN 47 TMS 72 EX_DATA6 9
195. t used The primary HSS signals are connected to HSS 1 The secondary HSS signals are connected to HSS 0 The GPIO signals route to the GPIO FPGA The Legend describing the color codes for the signals follows the table Table 25 HSS 1 Mezzanine Card Standard Connector Signals Sheet 1 of 2 Signal Pin 4 Signal Pin Signal Pin 1 EX ADDR11 41 50V 81 2 EX ADDR10 42 3 3 V 82 3 EX_ADDR13 43 HSS1_GPIO2 83 4 EX_ADDR12 44 HSS1_GPIO3 84 EX_DATA1 5 EX_ADDR15 45 GND 85 EX DATAO 6 EX ADDR14 46 GND 86 September 2005 Inte IXDP465 Development Platform User s Guide UG 46 Order Number 306462 Revision 004 I ntel IXDP465 Baseboard Hardware Design Table 25 HSS 1 Mezzanine Card Standard Connector Signals Sheet 2 of 2 Signal Pin Signal Pin Signal Pin EX DATA3 GND 47 87 EX DATA2 8 GND 48 HSS1_GPIO4 88 HSS1 GPIOO 9 EX ADDR17 49 89 HSS1 GPIO1 10 EX ADDR16 50 RST N 90 EX DATAS 11 EX ADDR19 51 91 EX_DATA4 12 EX_ADDR18 52 HSS TXFRAMEO 92 EX DATA7 13 ADDR 1 53 5 93 EX DATA6 14 EX_ADDR20 54 HSS_TXCLKO 94 GND 15 EX_ADDR23 55 GND 95 GND 16 EX_ADDR22 56 HSS_TXDATAO 96 EX DATA9 17 GND 57 HSS_TXDATA1 97 EX DATA8 18 GND 58 GND 98 EX_DATA11 19 EX_CLK_HSS1 59 HSS_TXFRAME1 99 EX_DATA10 20 EX_RD_N 60 HSS RXDATA1 100 S 21 GND 61 101 22 EX_WR_N 62 HSS_RXFRAME1 102 EX_DATA13 23 EX
196. tandard Connector Signals Sheet 2 of 2 Signal Pin Signal Pin Signal Pin EX_ADDR5 39 5 0 V p 12 V 113 EX_ADDR4 34 30V 74 2 5 V 114 EX_ADDR7 35 5 0 V 8 12 115 EX_ADDR6 36 dad M 76 250 116 GND 37 5 0 V 77 12V 117 GND 38 9 8 V 78 25 118 EX_ADDR9 39 50 y 79 12V 119 EX ADDR8 40 3 3 V 80 2 5 V 120 Legend power signals purple IXP4XX Network Processor extended expansion bus signals green GPIO signals maroon 550 signals primary black HSS1 signals secondary red not used JTAG signals gray interrupt signal gold Stacking Interface Expansion Connector The stacking interface expansion connector contains the extended expansion bus interface IXP465 specific GPIO SPI ID future needs and power signals Table 92 defines the stacking interface expansion connector signals The Legend describing the color codes for the signals follows the table Stacking Interface Expansion Connector Signals Sheet 1 of 2 Signal Pin Signal Pin Signal Pin 1 8V 1 C_PCI_4 41 3 0 V 81 1 8V 2 C PCI 5 42 3 3 V 82 GND 3 C PCI 6 43 Bo V 83 GND 4 C PCI 7 44 949 V 84 EX DATA17 5 C PCI 8 45 GND 85 EX DATA16 6 C PCI 9 46 GND 86 EX DATA19 7 EX BE N3 47 C FN 59 87 EX DATA18 8 EX BE N2 48 C FN 60 88 GND 9 EX BE 1 49 C FN 61 89 GND 10 EX BE NO 50 C FN 62 90 Inte IXDP465 Development Platform User s Guide UG Order Number 306462 Revision 004 intel Table 92 UG Mezzanine Card Hardware Design Stacking Interface Expansion Connector Sign
197. the CPLD A four port zero delay buffer Cypress CY2305 drives the four PCI slot clocks and the network processor module PCI clock When the IXDP465 baseboard is in Option mode CPLD drives the four PCI slot clock outputs to logic 1 to reduce noise CPLD programming is accomplished through the CPLD JTAG Programming Header See Figure 15 for the location and settings of the JTAG Emulator and CPLD Programming Headers For an overall memory address map and the expansion bus memory map for the IXDP465 platform see Section 3 3 5 Expansion Bus Address Map PCI Host Mode Operation The IXDP465 baseboard supports four external 32 bit PCI devices 3 3 V only when configured as a PCI host Both 33 MHz and 66 MHz PCI bus operation are supported In PCI host mode the IXDP465 baseboard supports up to four PCI expander cards in PCI slots In PCI option mode the IXDP465 baseboard baseboard is plugged into a standard PCI backplane through a card edge connection on the board See Section 3 2 5 PCI Option Mode Operation for details See the following tables for pin assignment details Table 10 PCI Host Slot 0 Pin Assignments on page 28 Table 11 PCI Host Slot 1 Pin Assignments on page 29 Table 12 PCI Host Slot 2 Pin Assignments on page 30 Table 13 PCI Host Slot 3 Pin Assignments on page 31 In Host mode the IDSEL signals on the PCI slots are connected to the PCI AD bus as listed in Table 9 When the IXDP465 base
198. tie 139 5 4 465 Quad T1 E1 Mezzanine 140 EE 140 5 4 2 Quad T1 E1 Card Connector Interfaces 141 5 4 2 1 IXDP465 Interface Standard 141 5 4 2 2 IXDP465 Interface Expansion Connector 143 5 4 2 3 Stacking Interface Standard Connector 145 5 4 2 4 Stacking Interface Expansion Connector 146 543 Quad TVET Card Stacking eoe tenete retenir Le etude 148 543 1 Board ID u 148 5 44 Quad T1 E1 iere estet titi Pat a 149 BAA CPLD GIOCK eet re ee aa 150 5 4 4 2 CPLD Core Voltage 150 5 443 CPLD Voltage 151 5 4 4 4 CPLD JTAG Interface nnne 151 5 445 eM aspa ia a A aaea 153 5 4 5 1 Processor Interface uuu u R RAAR 154 5 4 5 2 Line Interface roe eret e EY ATE 154 5 4 5 9 Powerlnterface iecit 155 5 4 5 4 Clock 2 0444400000 ennt nnn nnns 158 5
199. ts for JP1 JP2 JP3 JP4 and JP65 JP93 shown in Figure 11 are determined by using the appropriate SMII Configuration Number column in the tables provided in Section 3 8 NPE Jumper Block Pin Assignments NPE Jumper Block Pin Assignments Note The CFG columns in the tables in this section refer to SMII configurations defined in Table If you are not using SMII with any of the NPEs then CFG 1 is the correct column to use for NPE jumper settings 3 8 1 NPE A B C SMII Jumper Block JP1 The IXP465 network processor contains NPE pins that have multiple functions The SMII jumper block connects specific shared NPE signals to the multi port PHY Table 28 shows the pin definitions for the SMII jumper block as well as the JP1 jumper pin assignments which depend on the SMII Configuration CFG selected in Table 27 To find the location of JP1 on the IXDP465 baseboard see Figure 11 Table 28 SMII Jumper Block JP1 Pin Assignments Sheet 1 of 2 JP1 Network Processor JP1 SMII Sianal CFG CFG CFG CFG CFG CFG CFG CFG Pin Signal Pin 9 1 2 3 4 5 6 7 8 1 C_ETHC_TXDATA0 2 SMII_TXDATA5 IN x IN IN 3 C_ETHC_RXDATA0 4 SMII_RXDATA5 Wc IN IN IN IN 5 C_UTP_OP_DATA7 6 SMII_TXDATA4 sss dem IN IN IN IN September 2005 Intel IXDP465 Development Platform User s Guide UG 54 Order Number 306462 Revision 004 intel IXD
200. tu aeu daa 77 52 I2C Status Information I tute uan 78 53 Mezzanine Card Board DS cree Dr et ee E Ex Ite ca eie La aut ARR RE ad 78 54 2 EEPROM Addresses 2 22 100 00000000 saksa nnne nennen en 79 55 Intel IXDP465 Development Platform LED Indicator Definitions 81 56 Emulator Connector Pin nennen nennen nennen 83 57 IXDP465 Development Platform Power Distribution 85 58 ATX Power Supply Connector Pin Assignments nennen 86 59 PSG180B 80 Power Supply Output Specifications 86 60 Clock Control CPLD External Address 89 61 Clock Control CPLD Internal Address Decode sse ene 90 62 Control Status Register Bit Definitions a 90 63 Expansion Bus Frequency Select Bit Definitions a 90 64 PCI Host Present Register Bit Definitions a 91 65 PCI Host 66 MHz Enable Register Bit Definitions ene 91 66 FPGA Programming Register Bit Definitions en 91 67 Configuration Straps Override U 92 s LED e t 94 09 Environmental Ra
201. ue of this register after reset is xxxxxx11 The table below defines this register s bit definition x x x x x x FXO FXS UG Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 135 Mezzanine Card Hardware Design intel The Interrupt Status register is a read only and active high bit is high interrupt is pending register that indicates which analog port is requesting interrupt service Multiple ports can request interrupt service simultaneously The table below defines this register s bit definition Interrupt Status Register FXO FXS3 FXS2 FXS1 FXSO Relay Control Register The Relay Control register is a read write register that selects the five switchover relays state The active logic high or inactive logic low relay state is set by writing this register The value of this register after reset is Xxxxxxx0 The table below defines this register s bit definition Relay IXDP425 IXDP465 Mode Register The IXDP425 IXDP465 Mode register is a read write register that selects the clock source for analog clocking and framing and it also selects which interface to run all SPI signals on A logic low 0 on bit 0 indicates that the analog clock source is the IXDP465 Interface Expansion connector while a logic high 1 indicates that the clock source is an onboard oscillator for IXDP425 support A logic low 0 on bit ind
202. vice Pull Up Enable USB_DEV_PU_ENB bit allows under software control enabling and disabling the pull up on the USB Device positive signal of the differential output pair This indicates to the USB Host that a valid USB device is present Any Inte IXDP465 Development Platform User s Guide UG Order Number 306462 Revision 004 intel 3 22 1 1 2 Table 64 3 22 1 1 3 Table 65 3 22 1 1 4 Table 66 UG IXDP465 Baseboard Hardware Design IXDP465 platform reset disables this pull up default after reset is disabled and indicates to the host that no device is present Once this pull up is re enabled through software the USB Host re configures re initializes for the new device The Control Status register s LCD_TIME 4 0 bits indicate how many expansion bus clock cycles are left before the next LCD access begins Before the LCD Display Instruction register or the LCD Display Data register is written the software verifies these bits have a value of 00000 The default value after reset is 00000 PCI Host Present Register The PCI Host Present Register Table 64 is a Read Only register that allows the software to determine if a board is physically plugged into one of the four PCI host slots valid in PCI Host mode only The software can also determine the power that the add in card requires by the state of these bits PCI Host Slot 3 is represented by D7 D6 Slot 2 by D5 D4 Slot 1 by D3 D2 and Slot 0 by D1
203. ware Design Pin Signal Pin Signal C7 RXTIP1 P7 7 RXRING1 T7 RXRING3 A8 RVREF1 T8 RVREF3 B4 TXTIP11 21 P4 TXTIP13 23 B6 TXTIP11 21 R6 TXTIP13 23 C5 TXCM1 P5 XRING11 21 R4 XRING13 23 D5 XRING11 21 N5 XRING13 23 D10 RXTIP2 N10 RXTIP4 C10 RXRING2 P10 RXRING4 C9 RVREF2 P9 RVREF4 A13 TXTIP12 22 R13 TXTIP 14 24 A11 TXTIP12 22 T11 TXTIP14 24 D12 TXCM2 N12 TXCM4 C13 XRING12 22 T13 XRING14 24 B11 XRING12 22 R11 XRING14 24 Power Interface Table 100 lists the Quad Framer power interface pin definitions Each 3 3 V and 2 5 V pin is filtered using a 0 01 uF capacitor All other pins require special filtering as shown in Figure 41 through Figure 44 Quad Framer Power Interface Pin Assignments Sheet 1 of 2 Pin Signal Pin Signal C6 GND H15 25 V D11 GND K15 2 5 V P6 GND M13 2 5 V N11 GND J16 2 5 V C4 GND H2 3 3 V B12 GND K14 3 3 V N4 GND C3 3 3 V R12 GND D4 3 3 V B5 GND K4 3 3 V A12 GND N2 3 3 V R5 GND G16 3 3 V T12 GND N14 3 3 V Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 155 Mezzanine Card Hardware Design Table 100 Figure 41 September 2005 156 In Quad Framer Power Interface Pin Assignments Sheet 2 of 2 Pin
204. ws the pin definitions for the serial port DB 9 connectors Inte IXDP465 Development Platform User s Guide UG Order Number 306462 Revision 004 intel Table 42 Note Table 43 3 12 1 UG IXDP465 Baseboard Hardware Design Serial Port DB 9 Connector Pin Definitions UARTO J9 Signal UARTI1 J5 Signal 1 UARTO_DCD_B_L 1 UART1_DCD_B_L 2 UARTO_TXD_B_L 2 UART1_TXD_B_L 3 UARTO_RXD_B_L 3 UART1_RXD_B_L 4 UARTO_DTR_B_L 4 UART1_DTR_B_L 5 UARTO_GND_B_L 5 UART1_GND_B_L 6 UARTO DSR BL 6 UART1 DSR BL 7 UARTO CTS BL 7 UART1 CTS B L 8 UARTO RIS BL 8 UART1 RTS BL 9 UARTORI BL 9 UART1 RI B L To allow full modem control on the UART connections four GPIOs generate the RS 232 signals DTR DSR RI and DCD that are not explicitly generated by the IXDP465 platform Because of pin limitations in the GPIO FPGA and the low priority of modem signaling the modem control signals are shared with the GPIO from MII 2 Allowing full modem control on UART connections provides legacy support for the IXDP425 IXCDP1100 platform Hardware modifications the addition of 0 Qresistors were necessary to enable modem control signals for both serial ports Table 43 shows the modem signals that are shared with MII 2 GPIO and the associated resistor that has been added to the IXDP465 platform Serial Port DB 9 Modem Signal Alternate Functions Signal Shared MII
205. xpansion signals black SPI signals red UG Inte IXDP465 Development Platform User s Guide September 2005 Order Number 306462 Revision 004 45 Li IXDP465 Baseboard Hardware Design ntel 6 Legend Continued I2C signals gold GPIO signals maroon 3 6 2 HSS 1 Mezzanine Card Interface To achieve compatibility with the IXDP425 IXCDP1100 platform the following features are designed into the IXDP465 platform interface standard connector for the HSS 1 mezzanine card Connector part number Amp 5 179010 5 Exact pinout match Primary connection to HSS1 Use of expansion bus chip select 6 Use of expansion bus ready 2 The mezzanine card expansion connector contains the following signal groups XP465 network processor SPI XP465 network processor Pc IXP465 network processor extended expansion bus 16 GPIO Mezzanine ID byte for stacking 32 pins for future expansion common to all mezzanine cards 16 pins for future expansion dedicated to this mezzanine card Additional power The IXDP465 platform HSS 1 standard connector signal definition is described in Table 25 The power signals are 42 5 V 43 3 V 5 0 V and 12 0 V The expansion bus signals provide the 16 LSB of the data bus the 24 LSB of the address bus chip select 6 clocking and control to the mezzanine card The interrupt signal from the mezzanine card is routed to the GPIO FPGA The JTAG signals are no
206. y model and provides information on which devices are supported through the connectors The Intel IXP465 Network Processor is the next generation of processor in the IXPAXX family The IXP465 network processor design has many peripheral components that must be verified The Intel IXDP465 Development Platform validates that these peripherals are functional This 465 NPM consists of the IXP465 network processor its associated memory subsystem DDR in a x16 configuration and connectors for attachment to the IXDP465 platform To pass FCC Class B emissions spread spectrum clocking is used Two different footprints are available for an external clock Canned oscillator Spread spectrum clocking chip The IXP465 network processor uses a set of jumpers for clock configuration Figure 17 shows the jumper locations on the Network Processor Module The clock is taken directly from the oscillator output when the BYP SSCLK jumper is installed default setting The clock is driven through the spread spectrum IC as a buffer only no frequency alterations occur when the REFCLK jumper is installed The clock is driven through the spread spectrum IC with frequency alterations when the SSCLK jumper is installed Also the spread spectrum enable EN SSCLK jumper must be installed Since the crystal option for the 465 network processor is not supported do not install the XTAL IN or XTAL OUT jumpers Inte IXDP465 Development Platform User s
207. zanine Card Board IDs Board ID Mezzanine Card 0000 Reserved 0001 Network Processor Module x16 0010 Reserved 0011 Reserved 0100 Analog Voice 4x1 0101 Quad T1 E1 0110 Reserved 0111 1111 Reserved The network processor module has jumpers that allow switching between using GPIO and the PC network processor pins The default factory configuration uses the PC pins of the IXP465 network processor See Figure 17 on page 98 for the JP46 jumper location Addressing To avoid conflicts where multiple devices are connected to the same bus unique addresses must be used The IXDP465 platform has an onboard EEPROM the CPLD on the CPU mezzanine card plus up to five other mezzanine cards connected to the PC bus Figure 12 shows the PC address byte Intel IXDP465 Development Platform User s Guide UG Order Number 306462 Revision 004 I n IXDP465 Baseboard Hardware Design Figure 12 Address Byte The first four bits shown in blue are a fixed alternating pattern The next three bits shown in yellow are the address bits for each peripheral The last bit shown in green defines if this is a read or a write The EEPROM on the IXDP465 platform must have 2 0 set to 000 for access Any other pattern can be used in the design of mezzanine cards The C EEPROM is 512 bytes Table 54 lists the addresses Tabl

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