DSP Development Kit User's Guide
Contents
1. 4 2 7 Connector P Connector P can be used for supplying power to the IEEE1394 cable connector pin P2 Pe reserved 8 V 30 V IEEE1394 interface P7 GND P8 reserved SS P9 CABLE_GND CABLE POWER IEEE1394 interface Table 23 Pinout for micro line connector P 4 2 8 Connector X Connector X carries the IC signals micro line Signal Interface connector pin x1 x2 reserved n a X3 X4 DA C interface L X5 X6 X7 X8 reserved KL X10 Table 24 Pinout for micro line connector X USER GUIDE LY I DSP DEVELOPMENT KIT orsys Date 20 January 2005 Doc no DSP_DevKit_UG Iss Rev 1 00 Page 49 4 2 9 Other Connectors reserved n a i RTS UART interface reserved n a ee NER AINO analog inputs AIN3 Table 26 Pinout for the analog input connector 4 2 10 JTAG Connector Pin G FPGA PROM ch 00 NJ oO A ON o SE NO GA DSP B13 CPU_TRST Table 27 Pinout for the JTAG connector USER GUIDE Date 20 January 2005 u Doc no DSP_DevKit_UG DSP DEVELOPMENT KIT Iss Rev 1 00 orsys Page 50 4 3 Signal Levels and Loads All digital I O lines on the micro line connector except the RS 232 signals use 3 3 V LVTTL compatible signal levels CAUTION Applying more than 3 6 V to any logic input will damage the device 4 4 micro2. gt Verbunden 04 37 20 ANSI 1152008 N 1 RF y Figure 32 Isochronous receive operation isoch_1394 Date 20 January 2005 LY USER GUIDE Doc no DSP_DevKit_UG I DSP DEVELOPMENT KIT Iss Rev 1 00 orsys Page 39 4 Technical Data 4 1 Connector Pinout Summary by Interface The tables in this chapter list the connector pin assignments for each interface separately The pin assignments show both pinouts for the carrier board and the UC1394a 1 MCM This allows easy migration from the DSP development kit to a standalone system ADDRO _ Bt DB 5 ADDRi T WS DO MCM connector pin DIDP JIa OI 212 3 0 ADDR2 _ B3 ADDR3 ADDR4 D10 ADDR5 ADDR6__ B7 ADDR7_ B8 DATA CH DATA DATA DATA DATA DATA5 DATA6 DATA7 DATA DATA DATA DATA11 DATA12 DATA gt CH CH mu N gt gt le oJI D NID gt UO oO I wo W W agaleels CH O gt OD Q Q 00 0090 gt gt gt gt gt SSIS P P gt gt gt AJOIN oO TE B3 B4 B5 B7 B8 EI gt gt Wu i EI gt z gt Oo Le 00 Nj O O71 Go Po N J I I Ro _ N IK I I B10 9 C10 C11 C12 C13 C14 DATA14 C15 DATA15 C16 D10 D12 D13 D14 D15 D16 E5 E6 E3 E2 D17 D18 Table 7 Connector pin assignments for the peripheral interface Oo gt a gt N gt P gt gt gt gt
3. 3 2 LED Control toggle_led This is the most basic application example It initializes the MCM loads the FPGA and then enters a main loop The main loop waits for a constant delay and then toggles the MCM s LED The carrier board LEDs are not used in this example After loading and starting this example the MCM s LED is blinking This application example can also be used as a rudimentary test to check if the kit or the MCM is working properly 3 3 UART hello The UART example shows how to set up and use the UART First the MCM is set up and the FPGA is loaded Then the UART is initialized for 115200 baud and hardware RTS CTS handshake Then an output message is assembled using the stdio function sprintf The output message contains some information about the MCM The output message is sent to RS 232 by accessing the UART registers Finally the main loop is entered In the main loop the UART interface is checked for incoming characters Whenever a character comes in it is simply echoed a COM1_115200_8_N_1_HW HyperTerminal Datei Bearbeiten Ansicht Anruf bertragung Hello world UC1394a 1 200HHz S N 6753 asdasdasd ad v gt Verbunden 01 17 59 115200 8 N 1 R Figure 13 Sample session of the hello example 3 4 Buffered Character I O dbg_out This example uses the UART interface at a slightly higher level of abstraction buffered character I O as provided by the module support library see 1 fo
4. n Date 20 January 2005 Ly USER GUIDE Doc no DSP_DevKit_UG iJ Iss Rev 1 00 orsys Page 21 Orsys Orth System GmbH Am Stadtgraben 25 88677 Markdorf Germany User Guide DSP Development Kit for the UC1394a 1 http www orsys de LE USER GUIDE aE ee LJ DSP DEVELOPMENT KIT ee ee EE orsys Page 12 Contents 1 PREPAGE 20000 ee 6 1 1 Document Organizatlon une 6 1 2 Documentation Overview cccccceeesseeseeeeeeeeceeeseeeeneeeeseeeoenseseeeeeeesuoneaseseeeeeeeesuauenseeeseseeesoons 6 1 3 NotoatonalGopmventiong gue kuek ENEE Reech ENKEN VE EE KR nn nein andern nun DEENEN SNKSERNE nenne 6 1 4 Trademarks saaana anna nn ENER EEN cadunsessheeednavachesoulnneulebandenuteavene 7 1 3 Revision stop suis unsinnig na nn Kara anna ababa As eres we enn 7 St KIT OVERVIEW enee 8 2 1 UC1394a 1 MOM RE 9 2 2 UC1394a Carrier BOard sss cctictecinstusasssssccveuscusssdva sexecuduuvaicevedsscusesuansssvesnnnboednevaunvddsctednedadugvetahuee 9 2 3 micro line Power Supply Board 2 22242222222222000202022220002000000000020200000 000000000000 0n 000000000 10 2 4 Interfaces and Connectors 2222220ununn0n0000n0nunnnnnnnnnnnnnnnnnnn ann nnnnnnnnnnnnn ann nnnnnnnnnnnnn ennnen nna 10 241 REESEN 10 24 2 miere line Peripheral Interfabea un unnseanenn een 11 2 4 3 EEET1894 lNHterFacek aaa EE EE Ran nen 13 2 4 4 IEEE1394 Data Transfer Methods 13 2 4 5 LUTTE EE eenegen Eed anne anne
5. orsys Page Date 20 January 2005 LY USER GUIDE Doc no DSP_DevKit_UG I DSP DEVELOPMENT KIT Iss Rev 1 00 42 4 2 Connector Pinout Summary by Connector The tables in this chapter list the connector pinout for e each micro line connector row e the analog input connector e the alternative RS 232 connector separately 4 2 1 Connector A Connector A is used with the peripheral interface It carries the micro line data bus micro line Signal Interface connector pin peripheral interface reserved n a Table 17 Pinout for micro line connector A Ly Yorsys USER GUIDE DSP DEVELOPMENT KIT Date 20 January 2005 Doc no DSP_DevKit_UG Iss Rev 1 00 Page 143 4 2 2 Connector B Connector B carries the address lines of the peripheral interface and the signal ground micro line connector pin B1 ADDRO peripheral interface B2 BE ADDRS B7 ADDR6 B8 ADDR7 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 reserved B25 SIGNAL_GND B9 E E Be BI Ps Ete BiG Et E B19 B20 Ba _ Be B23 B24 B26 SIGNAL_GND SIGNAL_GND SIGNAL_GND SIGNAL_GND SIGNAL _GND SIGNAL_GND SIGNAL_GND power supply Table 18 Pinout for micro line connector B Ly Yorsys USER GUIDE DSP DEVELOPMENT KIT D
6. Names of signals are also given in capital letters active low signals are marked with a at the beginning of the name Example RESETIN Configuration parameters function names path names and file names are written in italic typeface Example dev_id Source code examples are given in a small fixed width typeface Example int a 10 Menus and commands from menus and submenus are enclosed in double quotes Example Create a new project using the Create Project command from the File menu The members of a bit field or a group of signals are numbered starting at zero which is the least significant bit z Date 20 January 2005 f USER GUIDE Doc no DSP_DevKit_UG N DSP DEVELOPMENT KIT Iss Rev 1 00 orsys Page 7 Example CFG 4 0 identifies a group of five signals where CFGO is the least significant bit and CFG4 is the most significant bit If necessary numbers are represented with a suffix that specifies their base Example 12AB s is a hexadecimal number base 16 hexadecimal and is equal to 477940 The bit fields of a register are displayed with the most significant bit to the left Below each bit field is a description of its read write accessibility and its default value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B C D E F G H l J K L N O r w Q r w 0 r w 0 r w 0 r w 0 r w 0 r w 0102 r 0 r wc 0 w r w 0 rc 0 r w 0 r w 0 acces
7. 1 00 orsys Page 152 RAM random access memory SDRAM synchronous dynamic random access memory ROM read only memory SDK software development kit TBC to be changed value not 100 tested and may change in future TBD to be defined value is not yet specified Tl Texas Instruments UART universal asynchronous receiver transmitter
8. Single Wite Continuous wite gt Trying to open device 0 Device successfully opened 4 bytes successfully read 0x63 Ox4B OxBF OxFC Figure 17 Incoming asynchronous transactions VHPD demo Date 20 January 2005 LY USER GUIDE Doc no DSP_DevKit_UG ig DSP DEVELOPMENT KIT Iss Rev 1 00 orsys Page 20 gt COM1_115200_8_N_1_HW HyperT erminal Datei Bearbeiten Ansicht Anruf bertragung Ole 213 ele Bus reset 0000003 nodes on the netuork foun node has index ol idx cur vendor ser nunber status node H L o O00 DOBD2A 01 00001A61 local node 000 001 081443 53 00001668 present 001 002 081443 51 0000273F present NFY R 0004 bytes addr 0000 node 001 v gt Verbunden 03 52 39 1152008N1 RF 4 Figure 18 Incoming asynchronous transactions terminal window 3 7 3 Outgoing transactions In the terminal window see Figure 22 press the s key to select the PC as target for outgoing transactions select the PC usually index 0 set the packet size to 1 quadlets On the PC VHPD demo select the Async Slave tab Click on Setup gt gt in the Generic Request Handler section see Figure 19 Set start address high to 0 Set start address high to 4 Set Length to 4 In the Notification after section enable Read and Write select the Control tab click on Allocate Range click on Enable Change back to the main window Do not close the Generi
9. 40 Table 9 UART interface connector pin assignments for the carrier board and the MCM 40 Table 10 McBSP interface pin assignments for the carrier board and the MOM gt 40 Table 11 I C interface pin assignments for the carrier board and the MCNM 41 Table 12 Analog input pin assignments for the carrier board and the MCH nenn 41 Table 13 Reset signal pin assignments for the carrier board and the MOM nennen 41 Table 14 Power pin assignments for the Carrier board ne nnnnnnnnnnnnnnnnnnnnnnnnnnnnn nn 41 Table 15 Reset signal pin assignments for the carrier board and the MOM sssssnsssnnnnnnssnnsennrrnnn 41 Table 16 IEEE1394 cable power supply for the Carrier hoa 41 Table 17 Pinout for micro line connector A 42 Table 18 Pinout for micro line connector BR 43 Table 19 Pinout for micro line Connector BR 44 Table 20 Pinout for micro line connector cccccscscssessesessessssessusesesseceuesesesessesevsesessesessuseneases 45 Table 21 Pinout for micro line connector D 46 Table 22 Pinout for micro line connector E 47 Table 23 Pinout for micro line connector P 48 Table 24 Pinout for micro line connector X cccccsccscssessssssessesessessesesesseceusesessesessesevsesesseseveusenenses 48 Table 25 Pinout for the alternative RS 232 connector s ssseesrrrrrsrtreeerertrrtrteeerrrrnnnnnnnnnnrrrnn nnne 49 Table 26 Pinout for the analog input COMNECTHON ccccceeeeeeeeeeeeeceeeeee
10. Setup gt gt Output Window Show Dock Clear www thesycon de Figure 19 Setup for outgoing asynchronous transactions 1 YHPDAPP Generic Asynch Request Handler EN Address Range Control Start ddress Length 0x0 Ox4 4 high low Bytes Allowed Access Notification after V Read V Read IV Write V Write IV Lock T Lock Size of single buffer Bytes Pending Buffers max 20480 4 Figure 20 Setup for outgoing asynchronous transactions 2 Ly USER GUIDE DSP DEVELOPMENT KIT Date Doc no Iss Rev Page 20 January 2005 DSP_DevKit_UG 1 00 31 YHPDAPP Generic Asynch Request Handler Meere Figure 21 Setup for outgoing asynchronous transactions 3 COM1_115200_8_N_1_HW HyperTerminal ola ala als press for help page lt space gt to start a transaction test setup ee partner device for test idx column adjust packet sizes neu packet size in quadlets 1 Quadlets per Packet 0001 Figure 22 Outgoing asynchronous transactions terminal window Date 20 January 2005 Ly USER GUIDE Doc no DSP_DevKit_UG DSP DEVELOPMENT KIT Iss Rev 1 00 orsys Page 32 YHPD1394 Output Window oj EX Address space access detected Base address of monitored range is 0x0 0x4 access to 4 bytes at offset 0x0 access type 0x20 WRITE Data 4 Bytes 0x00 Ox00 Ox41 OxA Address space access detected
11. Setup for outgoing asynchronous transactions A7 31 Figure 22 Outgoing asynchronous transactions terminal wimdow 31 Date 20 January 2005 ES DSP ar KIT ee f orsys Page 5 Figure 23 Outgoing asynchronous transactions VHPD output window uurs2snnnennnnnnnnnnnnnn 32 Figure 24 Startup of Isoch 1394 en anne een 33 Figure 25 lsochr nous setup 1 VHPD demo ae a 34 Figure 26 lsochronous setup 2 VHPD demo en 35 Figure 27 lsochronous setup 3 VHPD demo urr444nannannannnnnnnnnnnnnnnnannnnnnnnnnnnnnnannnnn 35 Figure 28 Isochronous transmit isoch_1394 u nee ehe 36 Figure 29 Receiving transmitted data VHPD demo 4 umsmnnnnennnnnnannnnnnn nennen 36 Figure 30 Isochronous setup for transmitting data VHPD demo 37 Figure 31 Isochronous transmit to the receiver VHPD demo urz442444444440 RnB nnnnnnn anne 37 Figure 32 Isochronous receive operation isoch_1394 2 uus4444444nHnnnannnnnnn nn nennen 38 Date 20 January 2005 Ly USER GUIDE Doc no DSP_DevKit_UG iJ DSP DEVELOPMENT KIT Iss Rev 1 00 orsys Page 6 1 Preface This document describes the basic usage of the DSP Development Kit It is intended as a starting point for new users The DSP development is described in its main features with focus on easy understanding The DSP development kit supports software development for the
12. gt gt gt SJ SS a a gt D gt gt gt gt gt gt gt fj st sch S CO CO O1 R O PO O 2 42 2 2 2 2 0o Solo RK do fo So OO G Po O Im Directly connected to the MCM Do not use USER GUIDE LY WI DSP DEVELOPMENT KIT orsys Date 20 January 2005 Doc no DSP_DevKit_UG Iss Rev 1 00 Page 40 po gt gt EEE HE SE Table 10 McBSP interface pin assignments for the carrier board and the MCM 3 3 3V signal level Level converter required Ly USER GUIDE DSP DEVELOPMENT KIT Date 20 January 2005 Doc no DSP_DevKit_UG Iss Rev 1 00 Page 41 UC1394a 1 pin Table 11 TC interface pin assignments for the carrier board and the MCM Analog input connector pin UC1394a 1 pin 1 AIN1 Table 12 Analog input pin assignments for the carrier board and the MCM UC1394a 1 pin RESETIN MRESETOUT D8 A9 Table 13 Reset signal pin assignments for the carrier board and the MCM UC13942 1 pin D5 D6 ma see 1 D1 D4 Table 14 Power pin assignments for the carrier board UC1394a 1 pin RESETIN RESETOUT Table 15 Reset signal pin assignments for the carrier board and the MCM UC1394a 1 pin 8 V 30 V PB na GND CABLE_POWER CABLE_GND Ir na Table 16 IEEE1394 cable power supply for the carrier board
13. reserved n a D10 CS1 ICS3 ICS4 D14 CS5 peripheral interface D15 CS6 INT4 reserved NORD pe peripheral interface D26 TxD GH CTS IORDY peripheral interface D31 reserved n a Table 21 Pinout for micro line connector D Date 20 January 2005 Ly USER GUIDE Doc no DSP_DevKit_UG DSP DEVELOPMENT KIT Iss Rev 1 00 orsySs Page 47 4 2 6 Connector E Connector E is used for the McBSP signals of port 0 and 1 and for some directly connected control signals of the peripheral interface It is strongly recommended to use leave these control signals unconnected and to use the corresponding signals on the D connector instead micro line Signal Interface connector pin en interface IOSTRB reserved n a NORD peripheral L VIORW _ interface reserved n a DR1 x1 D CLKR1 CLKX1 FSR1 FSX1 McBSP1 reserved DRO DXO CLKRO CLKXO FSRO FSXO XFOUT 04 McBSPO I O pins reserved Table 22 Pinout for micro line connector E These signals should not be used on this connector Instead the signals on the A connector should be used VO 4 should not be used on this connector Instead the signals on the A connector should be used Date 20 January 2005 LY USER GUIDE Doc no DSP_DevKit_UG I DSP DEVELOPMENT KIT Iss Rev 1 00 orsySs Page 48
14. UC1394a 1 MCM Detailed information about programming FPGA usage and technical data is contained in other documents that will be referenced throughout this document FPGA development is not supported by the DSP development kit but available as a separate product 1 1 Document Organization This document is organized as follows e Chapter 2 gives a brief overview of the whole system and its interfaces Chapter 3 tells how to do the very first steps Chapter 4 lists technical data of the UC1394a 1 such as pinning Chapter 5 lists documents that contain further information Chapter 6 explains the abbreviations that are used throughout this document 1 2 Documentation Overview This chapter lists the documentation from Orsys that is shipped together with the DSP development kit Further documents from other vendors may also be listed in chapter 5 and are referenced throughout the document in square brackets DSP Master BSP User s Guide 1 osp_master_Bsp_ve par Describes the DSP Master Board Support Package BSP This includes FPGA register description programming documentation technical data of the UC1394a 1 MCM micro line Power Supply Kit 2 power supply pae Describes the micro line Power Supply board IEEE1394 API User s Guide 3 emb_1394_apr_uc pa Describes the API for IEEE1394 programming 1 3 Notational conventions Names of registers bit fields and single bits are written in capital letters Example LLC_VERSION
15. operation CS7 highest address pattern OxFFFF is immediately followed by a read operation CS1 Since the write operation needs some pipeline steps to prepare the peripheral access the read operation appears before the write operation Such situations must be avoided as described in 1 z Date 20 January 2005 Ly USER GUIDE Doc no DSP_DevKit_UG J DSP DEVELOPMENT KIT Iss Rev 1 00 orsys Page 125 Tek 200M575 62 Acqs j JA 1 66545 1 1 66545 XFOUT isk EN ER ics Zut AOSTRB Zb da w vw vk NW vw NM MN El WE EE EE GE Ee S pw Chi 500V ch 5 00 Cou 19 Jan 2005 ch3 5 00W chg 14 36 42 Figure 14 Waveforms generated by the periph_ifexample 3 7 IEEE1394 asynchronous transactions async_1394 The async_1394 example is a more complex example It uses buffered character I O to create an application with user interaction over RS 232 The purpose of this example is to show how to perform asynchronous transactions with the IEEE1394 embedded API Before entering the main loop the following steps are performed e MCM setup FPGA is loaded buffered character I O is initialized the IEEE1394 API is initialized and started An address range for incoming asynchronous transactions is allocated The connected IEEE1394 devices are listed a default remote device is selected The main loop processes API callbacks and incoming characters Incoming characters are interpreted as comma
16. the carrier board and I O pin programming is described in 1 2 4 7 McBSP Interfaces The DSP of the UC1394a 1 provides 3 McBSP ports These interfaces are high speed serial interfaces They support multiple channels and a lot of different operation modes such as SPI MMC SD or AC97 Using this interface a wide range of peripherals such as codecs ADCs DACs or other DSP s can be directly connected to the UC1394a 1 Details of the McBSP interfaces are described in 1 On the carrier board port 0 and port a are directly routed to the respective micro line connectors McBSP2 is not externally available but has a loop back connection within the carrier board FPGA as shown in Figure 10 This loop back connection can be useful for testing McBSP configurations Please note The McBSP pins can also be configured and used as general purpose UO pins DSP DEVELOPMENT KIT Iss Rev 1 00 Date 20 January 2005 ky USER GUIDE Doc no DSP_DevKit_UG orsys Page 18 micro line connector E20 E21 E22 E23 E24 E25 Carrier board FPGA Figure 10 McBSP block diagram 2 4 8 USB Interface The USB interface is directly connected to the respective connector of the carrier board It can be used as described in 1 2 4 9 DC Interface The TC signals are directly routed to the micro line connector They can be used as described in 1 ML Connector pin X5 SDA__ X4 Table 4 I C connectors of the car
17. 4104 dotal4 oe E CycleStart 20 EE Streaming 4104 x Acknowledge code none Vi Figure 5 Isochronous data recorded from the IEEE1394 bus with an analyzer Date 20 January 2005 LY USER GUIDE Doc no DSP_DevKit_UG I DSP DEVELOPMENT KIT Iss Rev 1 00 orsys Page 15 one isochronous packet 20 samples one 16 bit sample empty cycles UC1394a 1 Peripheral IEEE1394 gt interface Der a interface u 5 H i I I I I l 10us ai bal 125us i one isochronous Transfer direction cycle Figure 6 Isochronous packet assembly sampling at 100kHz 16bit packet size 40 bytes 2 4 4 2 Asynchronous Streaming Asynchronous streaming is similar to isochronous streaming Asynchronous streaming uses the same data packets as an isochronous transfer Packets may be sent anytime provided that the bus is free Bus bandwidth is not guaranteed here so the transmission of a packet may be blocked by other transfers on the bus At the receiver side it makes no difference whether isochronous or asynchronous streaming is used Asynchronous streaming should be used when latency requirements don t allow isochronous streaming and bus bandwidth can be guaranteed by system design 2 4 4 3 Asynchronous Transactions Asynchronous transactions are handled by the IEEE1394 API Each data packet that is sent receives a response from the addressed device Asynchronous transfers can occur at any time provided t
18. A JTAG O 4 0 Configuration interface switches Carrier Board FPGA FH McBSP2 McBSP oe amp interfaces red green LED LED IC McBSP0 1 interface 5V Cable power option Figure 1 DSP development Kit block diagram o micro line connector 00000 Power connector 9 V 18 V unregulated AC adapter Date 20 January 2005 LY USER GUIDE Doc no DSP_DevKit_UG iJ DSP DEVELOPMENT KIT Iss Rev 1 00 orsys Page 9 2 1 UC1394a 1 MCM The UC1394a 1 MCM is the heart of the DSP development kit It provides all of the interfaces shown in Figure 1 and a complete hardware environment for user applications After software development is finished the UC1394a 1 can be easily integrated into a customized hardware environment Its small size and low cost make it an ideal solution for end product usage Further the implementation as a multi chip module MCM allows similar handling as of integrated circuits therefore mass production is supported The MCM is equipped with the DSP master board support package BSP This BSP provides software driven access to IEEE1394 streaming data and a peripheral interface to connect a wide range of peripherals The DSP master BSP is described in 1 2 2 UC1394a Carrier Board The carrier board turns the MCM into a micro line module It provides most of the available interfaces on standard 0 1 inch spaced connectors so that breadboar
19. Base address of monitored range is 0x0 0x4 access to 4 bytes at offset 0x0 access type 0x10 READ Figure 23 Outgoing asynchronous transactions VHPD output window Date 20 January 2005 SS USER GUIDE Doc no DSP_DevKit_UG I DSP DEVELOPMENT KIT iss Rev 1 00 orsys Page 33 3 8 Software Streaming isoch_1394 The isoch_1394 example has a similar structure as the async_1394 example After startup a main loop is entered which accepts user commands Programming details are documented in the source code as well as in 1 The basic operation when used in conjunction with the VHPD demo application is shown below For further details of this test application please refer to the built in help page which is displayed with the or h key The part of code of isoch_1394 that is related to the IEEE1394 API is described in 3 Below are transaction examples that were done with the kit connected to a PC running the VHPD demo application 3 8 1 Initial steps start the terminal program load the isoch_1394 example to the kit as described in chapter 3 1 in the terminal window the startup messages of isoch_1394 are printed as shown in Figure 24 start the VHPD demo application The VHPD startup screen appears as shown in Figure 16 select the kit which must have a UID starting with 00BO2A click on the Open button a COM1_115200_8_N_1_HW HyperTerminal Datei Bearbeiten Ansicht Anruf bertragung O
20. C1394a 1 MCM Orsys psp_master_BSP_UG 2 User s Guide micro line Power Supply Kit Orsys Power_Supply pdf 3 User Guide IEEE1394 embedded API Orsys emb_1394_API_UG pdf 6 List of Abbreviations Used in this Document API application programming interface BSP board support package a combination of software and FPGA design that provides a dedicated functionality to the UC1394a 1 MCM CCS Code Composer Studio Tl s development environment CPU central processing unit processor DSP Digital Signal Processor EMIF external memory interface an interface of the TMS320VC5509 DSP FIFO first in first out a special type of memory firmware software installed on the UC1394a 1 MCM firmly installed software FPGA field programmable gate array FG inter integrated circuit a low speed interface between integrated circuits KB kilobyte 1024 byte KBps KB per second LED light emitting diode LLC IEEE1394 link layer controller LSB least significant bit or byte MB Megabyte 1204 KB 1048576 byte MBps Megabytes per second Mbps Megabits per second McBSP multi channel buffered serial port a peripheral of the TMS320C6713 DSP MCM multi chip module ML micro line a proprietary quasi standard for micro controller buses defined by Orsys MSB most significant bit or byte n a not available Phy IEEE1394 physical layer transceiver Date 20 January 2005 Ly DSP hed planta KIT Doc no DSP DevKit UG VS Iss Rev
21. Connector pin RESETIN RESETOUT D8 _ _ _ Table 6 I C connectors of the carrier board Please note that RESETIN is driven for a short period of about 1us in case of a software reset or watchdog reset Note for users of other micro line boards In contrast to micro line CPU modules the non inverted RESETOUT signal on pin D9 is not available on the carrier board If a high active reset is required an inverter must be implemented in the surrounding hardware 2 4 14 DSP JTAG interface The JTAG interface of the DSP is used for downloading and debugging DSP software All JTAG signals are available at the JTAG connector of the carrier board together with the FPGA JTAG signals Table 27 lists the pinning of the JTAG connector USER GUIDE Date 20 January 2005 LO Doc no DSP_DevKit_UG DSP DEVELOPMENT KIT Iss Rev 1 00 f orsys Page 21 The DSP JTAG interface is used with a JTAG emulator such as the TI XDS series which can be connected to the carrier board by an adapter The JTAG adapter is included in the DSP development kit Usually the JTAG connector is used in conjunction with the JTAG adapter This JTAG adapter provides connectors which are compatible with standard development tools e the Texas Instruments emulator cables such as the XDS510 or compatible e the Xilinx parallel download cable FPGA JAG connector TEE DP JAG connector fits T emulator POD top view Figure 11 JTAG Adapt
22. according to the direction predefined by the carrier board see also Figure 9 In the main loop the red LED of the carrier board is continuously toggled so that it is blinking The green LED is controlled by the state of I O 3 For testing 1 03 micro line connector pin BB4 can be connected to one of the following connector pins by a 1kQ series resistor a none The green LED is lighting caused by IO3 s built in pull up resistor b GND pin D1 The green LED is switched off b 1 01 controls the red LED pin BB2 The green LED is also blinking 3 6 Peripheral Interface periph_if This application example has neither any text output nor does it control the LEDs It is mainly intended as a source code example Further the peripheral interface signals can be viewed with an oscilloscope or a logic analyzer After the usual initialization the main loop performs the following sequence e pulse XFOUT as a trigger signal write an all zeros pattern to the first address of CS1 write an all ones pattern to the last address of CS1 repeat the last 2 steps for CS2 through CS7 do a dummy read from the first address of CS1 repeat the last step for CS2 through CS7 repeat the complete sequence Figure 14 shows some waveforms that were generated by this example The left cursor shows the start of the sequence The right cursor shows a common programming issue for the DSP EMIF which is also described in 1 chapter Pipeline The last write
23. ate 20 January 2005 Doc no DSP_DevKit_UG Iss Rev 1 00 Page 44 4 2 3 Connector BB Connector BB is used for the FPGA UO pins micro line Signal Interface connector pin I O pins BB9 BB26 reserved n a Table 19 Pinout for micro line connector BB Date 20 January 2005 LY USER GUIDE Doc no DSP_DevKit_UG I DSP DEVELOPMENT KIT Iss Rev 1 00 orsys Page 45 4 2 4 Connector C Connector C carries the directly connected data lines of the peripheral interface It is strongly recommended to leave this connector unconnected an to prefer the data lines on the A connector micro line Signal Interface connector pin IC DATAO peripheral C2 DATA1 interface C6 DATA15 reserved C26 C27 C28 C29 C30 C31 C32 Table 20 Pinout for micro line connector C These signals should not be used on this connector Instead the signals on the A connector should be used USER GUIDE LY WI DSP DEVELOPMENT KIT orsys Date 20 January 2005 Doc no DSP_DevKit_UG Iss Rev 1 00 Page 46 4 2 5 Connector D Connector D is used for RS 232 UART interface converted to RS 232 levels power supply reset signals control and interrupt lines of the peripheral interface connector pin D3 GND D5 5V Dom RESETIN LC DR mmeserour 2 Ee wae
24. by Connector uusrersunnnennnnnnnnennnnnnnnennnnnnnnnnnnnnnnnnnnnnannnnnnnnn 42 42 1 ene ef E 42 42 2 SM eg E 43 42 3 SOMO CIO BB ea IE ae 44 424 Connector RE 45 4 2 5 Connector RE 46 426 e lt E E A Eee 47 42 7 CGonneclor E 48 428 GEREENT EE 48 WE Eer 49 4 2 10 JTAG CONNEC O a ee ee 49 4 3 Signal Levels and LO AAS GPRREERPEESBRERDRRERPEAERRREREBEPERRRREREEEEDRNBEELURPERBEEEEERESEHEEERERERSEREREEEERRERSEBEREREEEBER 50 AA micro line Connectors for Customized Hardware 2 22u2u222202020000020200000000000000000000000 50 4 5 Connectors for the Analog Input and Alternative RS 232 Connector sssssseeeereeees 51 5 ZEECHNEN 51 6 LIST OF ABBREVIATIONS USED IN THIS DOCUMENT nunserssnnnnnnnnnnnnnnnnnnnnnnnnnnn 51 ny Date 20 January 2005 LJ DSP en KIT feet er EE f orsys Page A List of Tables Table 1 Peripheral interface le E 12 Table 2 Direct connection to some peripheral interface signals nn nnnnnnnnnnnnnn nn 13 Table 3 UART connector pin assignments 2244444444440H4Hnn nn nnnnannnnnnnnnnnnnnnnnnnnannnnnnnnnnnnnnnannnnnnnen 17 Table 4 I C connectors of the Carrier board 19 Table 5 Analog iNput CONN GCI x is een 20 Table 6 C connectors of the Carrier board 20 Table 7 Connector pin assignments for the peripheral interface ccccceeeeeeeeeseneeeeeeeeneeeeees 39 Table 8 I O pin connector pin assignments for the carrier board and the MCM
25. c Request handler Window Click on Setup gt gt in the Write Request Handler section Set start address high to 0 Set start address high to 4 Set Length to 4 select the Control tab click on Allocate Range click on Enable In the terminal window press the t key or any other key that is not bound to a command In the terminal the callbacks involved in the transaction display some short messages as shown in Figure 22 In the Output window of VHPD demo the transactions are reported as shown in Figure 23 Date 20 January 2005 Ly USER GUIDE Doc no DSP_DevKit_UG iJ DSP DEVELOPMENT KIT Iss Rev 1 00 orsys Page 30 E YHPD1394 Demo Application gesnssnnnsnssnnennsnnssnasnnsnnennes Device Async Read Write Async Lock Async Slave Isochronous Configuration Topology D r Generic Request Handler A range of the local node s address space will be configured in buffer store mode The address range may be considered as a software register that is accessible by the device Write Request Handler A range of the local node s address space will be configured in buffer queue mode Set The address range can handle a contiquous sequence of ants asynchronous write requests Read Request Handler A range of the local node s address space will be configured in buffer queue mode The address range can handle a contiquous sequence of asynchronous read requests P
26. cified by Orsys This protocol can be used on a host PC to load appropriate device drivers Customized protocol identification is available at Orsys on request Date 20 January 2005 I USER GUIDE Doc no DSP_DevKit_UG DSP DEVELOPMENT KIT Iss Rev 1 00 orsySs Page 16 2 4 4 5 Power Distribution Over IEEE1394 The IEEE1394 standard defines a 6 wire cable that allows to supply devices over the cable This is often used for digital cameras To operate the UC1394a 1 powered from the IEEE1394 cable an external voltage regulator is required The IEEE1394 standard allows up to 10W power consumption for a device Figure 7 shows the power supply options that are available for the carrier board in standard configuration Option1 supplying remote micro line devices over the cable connector IEEE1394 14 porto 2 Option2 supplying the kit from i IEEE1394 1 SCH the cable Dot 2 Voltage 7 TT regulator supply Figure 7 IEEE1394 power supply options of the carrier board 2 4 4 6 Isolation The IEEE1394 interface of the UC1394a 1 is directly connected to the remaining circuit There is no galvanic isolation between the IEEE1394 cable and the local power supply In a custom hardware design the VG pin of the 1394 connector must be connected to the GND pins of the UC1394a 1 2 4 5 UART Interface The UC1394a 1 MCM has an UART interface that can be used for standard asynchronous communication Differen
27. d prototypes can easily be built Other connectors are available for use with dedicated cables The carrier board provides the following features e Regulated 3 3 V supply for the MCM e A level converter that converts the 3 3 V LVTTL signal levels of the MCM UART interface to RS 232 levels Two 400 Mbps IEEE 1394 ports with standard 6 pin connectors micro line connector for easy connection of external hardware A DIP switch for controlling the configuration inputs and FPGA JTAG routing Three LEDs for visual feedback A JTAG connector for DSP software download software debugging and FPGA design download e A connector for the MCM s analog inputs e An alternative RS 232 connector not used with the DSP development kit e An USB connector The carrier board is intended as a development aid which is used in the prototyping stage of a project In the end product the UC1394a 1 MCM will typically be used standalone analog in connector BB connector JIAG connector WU ut Bin E E Cem A FH De II F E mom red LED FPGA not configured BE A Gei red LED user programmable mu i an im SE green LED userprogrammable MM E connectors I i m figuration DIPswitch E configurato Swit ag gp FO LLL eer eT H H e m on Bin z l 7 mmm HE CEE altemative P5232 Cu connector com Gu EGND Eu Eu m micro line connectors xP Figure 2 UC1394a carrier board connectors and control elements 1 MCM FPGA developme
28. eceiver side Isochronous streaming is well suited for e large amounts of data e data distribution to several devices e data that occurs in regular intervals Figure 5 shows a part of an isochronous stream recorded with an analyzer The large blocks are isochronous packets with maximum size 4096 bytes The isochronous packets are preceded by a cycle start packet which indicates the start of a new cycle On the UC1394a 1 MCM packets are only transmitted when enough data is present in the FIFO Otherwise the corresponding cycle will be empty thus no packet is transmitted Figure 6 shows an example for this ES Firespy Recorder E JD x File Search FireSpy Recorder View OOO Ti ol a Sl else 134109640 of 128M af dieses lil pfiffi Time Viom Bi D od id PP Pe Packets View packet event size source destination label retry response code Packet Type Stream PS CycleStart 20 a EE Streaming 4104 Show As Packet Stream m a Am 00H C Int CG 400M ft G E CycleStart 20 5 u Streaming 4104 Fees Layout PS CycleStart 20 EE Steaming 4104 field value PS CycleStart 20 data length 4092 I Streaming 4104 tag 0 Wu CycleStart 20 channel 0 E Streaming 4104 tcode Stream EE CycleStart 20 synchronisation 0 nd So header CRC Ox99F SFE 1F conia data 0 009460947 ees 2 data oxO9480949 data 2 0 094 4 094B E Streaming 4104 EE CycleStart 20 data 3 Ox094C094D EE Streaming
29. eeeeeeeeeeeeeseeeeeseeeneeseeeeeeeess 49 Table 27 Pinout for the JTAG connector ae na 49 List of Figures Figure 1 DSP development Kit block dagram EEN 8 Figure 2 UC1394a carrier board connectors and control elememts nennen eennnenenen 9 Figure 3 Power supply board connectors and control elements nenne nennen 10 Figure 4 Block diagram of the peripheral interface urr44444444HH nennen nnnnnnnnannnnnnnnnnnnnnn anne 11 Figure 5 Isochronous data recorded from the IEEE1394 bus with an analyzer eneeeneneee 14 Figure 6 Isochronous packet assembly sampling at 100kHz 16bit packet size 40 bytes 15 Figure 7 IEEE1394 power supply options of the Carrier Doan 16 Figure 8 UART interface block dagram nann nes 17 Figure 9 VO pin Block diagram EE 18 Figure 10 MEBSP eege Ee Tun nee ae 19 Figure 11 JTAG Adapter en eege ee eege eege eege 21 Figure 12 JTAG Adapter with FPGA JTAG signals shown ssssssesssssrnseennresserrrneernnnnsrnrressrrrnne 21 Figure 13 Sample session of the beiloevample EEN 23 Figure 14 Waveforms generated by the perph Vevample 25 Figure 15 Startup of asyn 1394 nee ae 26 Figure 16 Opening the kit with VHPD demo 27 Figure 17 Incoming asynchronous transactions VHPD demo 28 Figure 18 Incoming asynchronous transactions terminal window Rennen 29 Figure 19 Setup for outgoing asynchronous transactions Bi 30 Figure 20 Setup for outgoing asynchronous transactions A7 30 Figure 21
30. er 2 4 15 FPGA JTAG interface The FPGA JTAG interface is used for e updating the carrier board FPGA code by programming a PROM on the carrier board e temporarily downloading FPGA code to the carrier board FPGA and e temporarily downloading FPGA code to the MCM All JTAG signals are available at the JTAG connector of the carrier board together with the DSP JTAG signals Table 27 lists the pinning of the JTAG connector The FPGA JTAG interface is used with programming hardware such as the Xilinx parallel download cable A JTAG adapter which is included in the DSP development kit provides a suitable connector I I Bains El 433V GND TCK TDO TO TMS FPGA JAG connector Sim D JAG connector fits T emulator POD Meee top view Figure 12 JTAG Adapter with FPGA JTAG signals shown FPGA development for the MCM or the carrier board is available as a separate product 2 4 16 Power Supply Input The UC1394a 1 MCM requires a single regulated 3 3V power supply The carrier board generates this voltage from the power input of the micro line connectors which is 5 V nominal The micro line power supply board supplies 5V to the micro line connector from a switching regulator It allows unregulated power input of 9 V 12 V The power supply board can be supplied from a usual AC adapter which must be capable of delivering 9 V 18 V and AN Optionally connected IEEE1394 devices can be supplied over the cable In turn power from t
31. hat the bus is free They are point to point transfers so the originator of the transfer must know who to talk to An asynchronous transfer consists of a request that is sent to the destination device and a response that the destination device sends back This enables error checking at the sender Asynchronous transfers are well suited for e data that occurs randomly e g control and status information e transfers where the originator of the transfer must be informed about the status of each single transfer 2 4 4 4 Plug amp Play features of IEEE1394 When devices are connected to or disconnected from the IEEE1394 network node ID s are automatically assigned for the connected devices This is done by the chipset without any software intervention Independent of the node ID most devices provide some more information about themselves There is an area within the IEEE1394 address space that is called configuration ROM The configuration ROM holds information about e the manufacturer of the device e device serial number e software interface of the device The serial number together with the manufacturer form a world wide unique 64 bit ID Using this 64 bit ID the device can be identified independently of the network topology or the currently assigned node ID The next higher level of identification is the protocol level By default the UC1394a 1 when equipped with the DSP Master BSP identifies itself as a device running a generic protocol spe
32. he cable is also available at micro line connector P Please refer to chapter 2 4 4 5 for details Ce USER GUIDE Date 20 January 2005 Doc no DSP_DevKit_UG WI DSP DEVELOPMENT KIT Iss Rev 1 00 orsys Page 22 3 Application Examples The distribution media contains several application examples They can be downloaded to the kit by using a JTAG emulator or they can be programmed to the MCM s flash memory as described in 1 To download an application example to the MCM please proceed as follows Required items e a development PC with the software listed below installed e Texas Instruments Code Composer Studio V2 2x A run time limited version is downloadable from www ti com e adJTAG emulator a terminal program such as Hyperterminal which is usually part of Windows distributions e Optional IEEE1394 evaluation software such as the VHPD demo application A demo version of the VHPD software is downloadable from www thesycon de e a DSP development kit including a JTAG adapter all cables and a suitable power supply All application examples are provided as a CCS project The project has two available configurations Debug and Release Debug is the default configuration and should be used during development The Release configuration differs from Debug in two points e no debugging symbols are created the code is not suitable for source code debugging but better optimized e The Release version of the m
33. in 40 ms Number of Buffers 2 Status Data rate 21600 bytes s Totally transferred 1 363 200 bytes Figure 29 Receiving transmitted data VHPD demo 3 8 3 Receiving streaming data Setting up isoch_1394 for receive operation terminal window e press C to start receive operation without data comparison Setting up and transmitting isochronous data VHPD demo e select the Isochronous tab as shown in Figure 25 click on Setup gt gt in the TALK section Set Bytes per frame to 4 as shown in Figure 30 Select the Run tab Click on Start see Figure 31 terminal window is increasing see Figure 31 Now VHPD demo transmits data and the number of received packets displayed in the ss USER GUIDE DSP DEVELOPMENT KIT orsys Date 20 January 2005 Doc no DSP_DevKit_UG Iss Rev 1 00 Page 37 YHPDAPP Isoch Transmit Chano S 400 Mbit s ei WEG EtS to Sti og Figure 30 Isochronous setup for transmitting data VHPD demo YHPDAPP Isoch Transmit Chan 0 Figure 31 Isochronous transmit to the receiver VHPD demo USER GUIDE DSP DEVELOPMENT KIT Q orsys Date 20 January 2005 Doc no DSP_DevKit_UG Iss Rev 1 00 Page 38 COM1_115200_8_N_1_HW HyperTerminal Datei Bearbeiten Ansicht Anruf bertragung De slal ls press 27 to get help page BR Receive operat ion Any key aborts 4910_
34. ing uses isochronous streaming as defined by the IEEE1394 standard Isochronous streaming is explained in chapter 2 4 3 Software streaming programming is described in 1 The distribution media contains an example for software streaming in the isoch_ 1394 folder Date 20 January 2005 USER GUIDE Doc no DSP_DevKit_UG DSP DEVELOPMENT KIT Iss Rev 1 00 orsySs Page SN 2 4 2 micro line Peripheral Interface The micro line peripheral interface allows to connect micro line peripheral boards as well as a wide range of user defined peripherals The micro line peripheral interface is implemented as a parallel bus interface with asynchronous control signals All signals of the peripheral interface of the MCM are routed to the micro line connectors through the carrier board FPGA Additionally some signals are directly routed to the C and E connectors However user defined hardware should only use the default micro line signals routed through the FPGA in order to be compatible with other micro line CPU boards Further the directly connected data lines on the C connector are used at system startup for booting the carrier board FPGA micro line connector Peripheral Carrier Board interface FPGA B1 8 A1 16 D10 16 D22 25 30 D17 18 C1 16 E1 3 5 6 Figure 4 Block diagram of the peripheral interface A detailed functional description of the peripheral interface can be found in 1 The s
35. le 23 ele isochronous streaning exanple UC1394a 1 200442 S H 0000006753 FPGA 407 02 HAL version 18041221 API version 18041221 Default packet size is D001h quadlets Default frane size is OU quadlets Default speed is 100 press 97 to get help page Node vendor ID chipID high and serial nunber OOBO2A 01 O0001A61 000000675 press 97 to get help page BR gt Verbunden 04 37 20 115200 8 N 1 RF y Ui Figure 24 Startup of isoch_1394 USER GUIDE Date 20 January 2005 Ly Doc no DSP_DevKit_UG RSI DSP DEVELOPMENT KIT Iss Rev 1 00 orsys Page 134 3 8 2 Transmitting streaming data Prepare the VHPD application for isochronous receive e Select the Isochronous tab as shown in Figure 25 Click on Setup gt gt in the LISTEN section Set quadlets to strip to 0 as shown in Figure 26 Set Bytes per frame to 4 Select the Run tab Click on Start see Figure 27 Transmit a packet with isoch1394 e inthe terminal window press T to start continuous transmission as shown in Figure 28 e the number of packets starts counting and VHPD demo displays receiver statistics as shown in Figure 29 e press any key to stop transmission E YHPD1394 Demo Application gensensnneonsnnsnnssnnsnnnsnennnns Configuration Topology Secesvessscesnecncnsconseassccend Device Asyne Read witte Asyne Lock Async Slave Available lsochronous Resources Speed Selector A
36. line Connectors for Customized Hardware For building customized carrier boards and daughtercards standard 0 1 inch breadboards can be used Suitable connectors that fit to the carrier board s micro line connector can be purchased from Preci Dip Durtal SA Rue St Maurice 34 P O Box 341 CH 2800 D lemont Switzerland Phone 41 0 32 421 04 00 Fax 41 0 32 421 04 01 E mail sales precidip com http www precidip com peripheral board 10mm board spacing single row peripheral board 10mm board spacing double row or from Fischer Elektronik GmbH amp Co KG D 58465 L denscheid Germany Phone 49 0 23 51 4 350 Fax 49 0 23 51 4 57 54 E mail info fischerelektronik de http www fischerelektronik de peripheral board 10mm board spacing double row carrier board single row thruhole MKO1 xxZ carrier board double row SMT MK220SMD xx Z e USER GUIDE En I DSP DEVELOPMENT KIT ae a rsys Page 51 or from Mill Max Mfg Corp 190 Pine Hollow Road Oyster Bay NY 11771 USA Phone 516 922 6000 Fax 516 922 9253 E mail sales mill max com http www mill max com Connector type all types see table for Preci Dip 4 5 Connectors for the Analog Input and Alternative RS 232 Connector Suitable receptacles for the alternative RS 232 connector and the analog input connector are lumberg www lumberg com MICA 10 5 Literature references 1 DSP Master BSP User s Guide for the U
37. nase nn 16 246 WO PIAS isc se nn a ee ee 17 24 0 MeBSP lNterfaces 22 2 een 18 2 4 8 USBilnterlace EE 19 P Re So I ee ee ee er 19 24 0 Na A ul TE 20 2AIV a E T T A EET T a en ee E 20 2412 RE 20 24 13 Enn E EE 20 24 14 RTR ER EE 20 2 4 15 FPGA JTAG Imtertace cee aiandi neari arai aaaea kaaa Tear AAEEen anaa aai 21 24 16 Power SUPDIY INPUT ausser 21 3 APPLICATION EXAMPLES u22u20022000000000n0000nnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 22 3 1 Download procedure anna ae 22 3 2 LED Control toggle Jegdts euesrasssgeesgegesgeeee eege r pa EEE RER 23 3 3 UART hello ee 23 3 4 Buffered Character I O dbg_out uureunnnanannnnnennnnunnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnunnrnnnnnnnnannnnenne 23 35 VO Pins 10 Pi nasse 24 LE USER GUIDE en I DSP DEVELOPMENT KIT He eran Tan orsys Page 13 3 6 Peripheral Interface periphi il 0 004040 0000 na nn ann nenn 24 3 7 IEEE1394 asynchronous transactions async_1394 uuu00000000000n00nnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 25 3 7 1 MA STEDS nenne ernennen 26 3 7 2 MOOI transactions een era 27 3 7 3 Eelere Te 29 3 8 Software Streaming isoch 1394 cs nen 33 38 1 MIA STE Sr ee re een ee 33 3 8 2 Transmitting streaming laser 34 3 8 3 Receiving streaming Blasien 36 A TECHNICAL DATA EE 39 4 1 Connector Pinout Summary by Interface uuusuunsnnnnennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnannnnnnnnn 39 4 2 Connector Pinout Summary
38. nds Incoming asynchronous transactions are displayed by API callbacks Outgoing asynchronous transactions are sent when pressing a key that is not bound to a function The available commands are listed when the or the h key is pressed Most of the code of async_1394 is related to the IEEE1394 API which is described in 3 Below are transaction examples that were done with the kit connected to a PC running the VHPD demo application IE USER GUIDE Date 20 January 2005 Doc no DSP_DevKit_UG I DSP DEVELOPMENT KIT Iss Rev 10 orsys Page 26 3 7 1 Initial steps start the terminal program e load the async_1394 example to the kit as described in chapter 3 1 in the terminal window the startup messages of async_1394 are printed as shown in Figure 15 start the VHPD demo application The VHPD startup screen appears as shown in Figure 16 select the kit which must have a UID starting with 00B02A click on the Open button COM1_115200_8_N_1_HW HyperTerminal Datei Bearbeiten Ansicht Anruf bertragung asynchronous transact ion exanple HAL version 18041221 API version 18041221 Node vendor ID chipID high and serial number OOBO2A 01 O0001A61 0000006753 press 97 to get help page BR Bus reset 0000001 nodes on the netuork foun node has index ol idx cur vendor ser nunber status node Ho L o 000 OOB02A 01 00001A61 local node press for help page lt space gt to start a transacti
39. ns of the MCM are implemented in the FPGA whereas the on chip GPIO pins of the DSP are not available on the UC1394a 1 The available I O pins are divided into three groups e FPGA I O a part of these pins is used as outputs by the carrier board the other part is used as inputs e configuration inputs e external flag XF output of the DSP If further I O pins are required unused McBSP interfaces can also be configured as I O pins Date 20 January 2005 USER GUIDE Doc no DSP_DevKit_UG DSP DEVELOPMENT KIT Iss Rev 1 00 orsySs Page 18 green red LED LED Bin ZN Carrier board micro line FPGA connector BB1 BB2 BB3 BB4 BBS DSP XF output Figure 9 I O pin block diagram Notes for the carrier board environment 1 The FPGA UO pins are routed through the carrier board FPGA Their direction is therefore fixed and can t be changed Application software must set up the FPGA UO pins for the proper direction before using them 2 The CFG inputs are connected to the carrier board s DIP switch and are not externally available Application software can use the CFG inputs for basic configuration of operation 3 I O 4 is also directly connected the micro line pin E27 Please use always 1 04 with micro line pin BB5 to avoid signal contention 4 The green and a red carrier board LED are controlled by I O0 and O1 respectively Behavior of the I O pins in stand alone environment without
40. nt is available as a separate product Date 20 January 2005 USER GUIDE Doc no DSP_DevKit_UG iJ DSP DEVELOPMENT KIT orsys page 9 2 3 micro line Power Supply Board The micro line power supply board acts as a desk carrier board It provides connectors for RS 232 and unregulated power input Further it provides a button for resetting the MCM and the carrier board The power supply board generates a regulated 5 V supply for the carrier board from an unregulated 12 V input power indicator LED micro line connectors E AU6666660666066660606666060606086600 m S EI HE H zen reset button bed Bes CR OR i e BEBB EI sg OH e S Je ww ll GD KEZZIKIKIIEIIIIIIIIEIIIIIIIIIII s Pap RS232 A connector EB u DEB EB U DE e Se See SG e See SI D N LZ e ee eee ee eee power input from extemal AC adapter Figure 3 Power supply board connectors and control elements 2 4 Interfaces and Connectors 2 4 1 Software Streaming Software streaming allows to transfer large amount of data between the DSP and IEEE1394 with minimal overhead Data transfers are buffered by a FIFO so that the DSP can operate independent of the IEEE1394 timing Streaming transfers are unidirectional and must be set up for a particular direction before operation is started The maximum transfer rate for streaming is 32 768 000 byte s Software stream
41. odule support library is used The Release configuration should be used for the final application after development is finished Further all example projects contain a final build step that creates a hex file This file can be programmed to flash memory as described in 1 3 1 Download procedure e connect the kit to the development PC using the JTAG emulator JTAG adapter and the RS 2332 cable e for async_1394 and isoch_1394 connect an IEEE1394 device e g the development PC to the kit using the IEEE1394 cable power on the system start Code Composer Studio select the Load GEL command from the File menu locate uc1394a 1_master gel from the GEL folder on the distribution media and open it select the Initialization gt CPU_reset_and_init_144Mhz command from the GEL menu select the Load Program command from the File menu locate one of the application examples from the examples folder on the distribution media and open it e g toggle_led ouf e select the Run command from the Debug menu Please note the application examples do not use the usual printf function Instead where necessary output is sent over the UART interface using 115200 baud and RTS CTS handshake This allows to store the examples in flash memory and then to execute them without the JTAG emulator Date 20 January 2005 LY USER GUIDE Doc no DSP_DevKit_UG DSP DEVELOPMENT KIT 4 Iss Rev 1 00 orsySs Page 123
42. on 4 Verbunden 00 00 49 ANS 1 15200 8 N 1 RF GR 4 Figure 15 Startup of async_1394 Date 20 January 2005 USER GUIDE Doc no DSP_DevKit_UG DSP DEVELOPMENT KIT Iss Rev 1 00 f orsys Page 27 Q E YHPD1394 Demo Application Asyne Read wite Asyne Lock Asyne Slave Isochronous Configuration Topology Available Devices r Device Parameters Scan for YHPD1394 devices Device 0 UID 006024 0100001461 M Driver monitors Reset Generation Request Timeout O ms Open Close Get Set IEEE1394 Node Addresses Device currently opened Local Host Controller Current Driver Version Not connected to device driver m Output Window Show Dock Clear www thespcon de Figure 16 Opening the kit with VHPD demo 3 7 2 Incoming transactions e inthe Asynchronous Read Operation section of VHPD demo change address offset high from OxFFFF to 0x0 as shown in Figure 17 e click on single read e now the status and the read data are displayed also shown in Figure 17 e in the terminal window async_1394 displays the incoming event through the notify callback as shown in Figure 18 Date 20 January 2005 USER GUIDE Doc no DSP_DevKit_UG or Sy s DSP DEVELOPMENT KIT Iss Rev 1 00 Page 28 E YHPD1394 Demo Application WG WC WE BE D 0x00 0x00 0x00 0x00
43. r details This is an alternative to using the stdio functions such as sprintf sscanf etc dbg_out prints out the same startup message as hello but the main loop is programmed as a command interpreter This shows how to implement an application that is interactively controlled over RS 232 Pressing the key within the terminal program causes a help page to be displayed Other command keys can easily be added by inserting appropriate case statement in the command switch Below is an example that shows how insert a command that toggles the MCM LED by the t key Date 20 January 2005 Ly USER GUIDE Doc no DSP_DevKit_UG I DSP DEVELOPMENT KIT Iss Rev 1 00 orsys Page 24 below is a command switch that could be used in applications that require user interaction over RS_232 switch c case F i case bi DebugOutConstString Debug interface example r n DebugOutConstString h and show this help page r n no other commands keys defined r n break case t toggle the red MCM LED UC1394A SYS CTL UC1394A SYS LED break default DebugOutConstString invalid command 1 shows a help page r n break 3 5 I O Pins io_pin The io_pin example works together with the carrier board LEDs It doesn t generate any output except for the visual feedback through the carrier board LEDs After the usual startup OO and O1 are configured as outputs and I O3 is configured as an input
44. ransferring data e isochronous streaming e asynchronous streaming e asynchronous transactions Asynchronous transactions are handled by the IEEE1394 API whereas isochronous and asynchronous streaming is only set up by the API and then performed by FPGA register accesses 2 4 4 1 lsochronous Streaming In isochronous streaming data is transferred in regular intervals called cycles In each cycle one data packet can be transferred The size of these data packets determines the maximum data bandwidth which can be calculated as max_bandwidth packet_size 8000 packets_per_second The cycle clock is 8kHz therefore packets get sent every 125 us Before transmission is started the transmitter reserves the necessary amount of bus bandwidth at a central location on the bus the isochronous resource manager This and the fact that isochronous packets have precedence over asynchronous packets guarantees that the bus provides enough capacity for the transfer Isochronous streaming is an excellent solution for transferring image data from a camera Isochronous transfers are multicast transfers which are identified by a channel so there is always Le USER GUIDE Date 20 January 2005 Doc no DSP_DevKit_UG I DSP DEVELOPMENT KIT Iss Rev 1 00 orsys Page 14 one talker but there may be one or more listeners The transfer is typically done without any software overhead and is therefore quite fast Error detection is done at the r
45. rier board LY USER GUIDE Date 20 January 2005 e Doc no DSP_DevKit_UG I DSP DEVELOPMENT KIT be ba 20 orsys Page 20 2 4 10 Analog Inputs The analog inputs are directly connected to a 10 pin connector on the carrier board They can be used as described in 1 A suitable receptacle for this connector is listed in chapter 4 5 Table 5 Analog input connector 2 4 11 RTC Usage of the DSP RTC is not supported by the default carrier board configuration If RTC usage is required please contact Orsys for further information 2 4 12 LEDs The carrier board provides three LEDs Two of them are controlled by I O pins as described in chapter 2 4 6 A third red LED lights at system startup while the carrier board FPGA isn t configured It must go off after about one second If this LED stays on one of the following reason may prevent configuration of the carrier board FPGA e the PROM with the FPGA code is not correctly programmed e Abus conflict on micro line connectors C1 C8 corrupts the FPGA code during startup Location of the carrier board LEDs is shown in Figure 2 The MCM also has a red LED which is controlled over the MCM s FPGA How to access this LED is described in 1 2 4 13 System Reset The reset signals of the MCM are directly connected to the respective micro line connector On the power supply board the reset input is connected to a pushbutton The reset signals are described in 1 ML
46. sibility and default value legend r bit is readable rc this bit is cleared after a read rw bit is readable and writeable reading yields the previously written value unless otherwise specified w bit is writeable read value is undefined wc writing a 1 to this bit clears it w 0 bit is write only reading always yields 0 0 default value 1 4 Trademarks TI Code Composer DSP BIOS and TMS320C5000 are registered trademarks of Texas Instruments Microsoft and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and or other countries Hypterterminal is a trademark of Hilgraeve Inc All other brand or product names are trademarks or registered trademarks of their respective companies or organizations 1 5 Revision history De orsys USER GUIDE DSP DEVELOPMENT KIT Date 20 January 2005 Doc no DSP_DevKit_UG Iss Rev 1 00 Page 8 2 Kit Overview The DSP development kit consists of three modules e An UC1394a 1 MCM soldered on a carrier board for easier handling e AnUC1394a carrier board e Amicro line power supply board RS 232 connector IEEE1394 porto IEEE1394 port1 JTAG connector Analog in conector USB connector Power Supply Board UC1394a Carrier Board LVTTL Level UART converter IEEE1394 interface Peripheral Carrier Board interface FPGA DSP JTAG XFOUT interface 7 VO pins CFG 4 0 FPG
47. t baud rates are supported as well as RTS CTS handshake The carrier board uses a level converter to convert these signals to RS 232 level How to program the UART interface is described in 1 The distribution media contains an application example for the UART in the hello folder The UART interface uses 2 data lines and 2 handshake lines A detailed description of the UART signals can be found in 1 Date 20 January 2005 SE USER GUIDE Doc no DSP_DevKit_UG DSP DEVELOPMENT KIT Iss Rev 1 00 orsySs Page 17 Power Supply Board mer Board 10 pin connector UC1394a 1 micro line with DSP master BSP connector Level Si RS 232 iy 9 pin sub D converter j D26 D29 connector 00000 0000 O Figure 8 UART interface block diagram The RS 232 signals are available at two connectors e on a 9 pin sub D connector on the power supply board routed via the standard micro line connectors e onan alternative connector located on the carrier board This connector can be used for direct cable connections to the carrier board A suitable receptacle is listed in chapter 4 5 Connector Cable connection to a remote PC carrier board Sub D 9 pin Sub D 9 pin Sub D 25 pin Table 3 UART connector pin assignments TxD RxD RTS CTS GND w gt RxD 3 O 4 E EC E J 2 2 3 4 a a u 8 7 5 5 2 4 6 WO Pins Please note With exception of the XF pin all I O pi
48. tandard micro line signals are listed in Table 1 whereas the directly connected signals are listed in Table 2 USER GUIDE DSP DEVELOPMENT KIT Date 20 January 2005 Doc no DSP_DevKit_UG Iss Rev 1 00 Page 12 Signal ADDRO B1 B1 B3 ADDR3 B4 gt gt UDO UDO WO Mil o Wu DATA4 DATA14 A15 A16 CS1 D10 CS2 D11 CS3 D12 CS4 D13 CS5 CS6 CS7 IORD IOWR DATA4 DATA14 ML Connector pin Signal group address lines data lines chip select lines control signals Table 1 Peripheral interface signals Ly USER GUIDE Date _ 20 January 2005 d Doc no DSP_DevKit_UG I DSP DEVELOPMENT KIT be ba 20 orsys Page 13 control signals Table 2 Direct connection to some peripheral interface signals 2 4 3 IEEE1394 Interface The UC1394a 1 MCM has two 400 Mbps IEEE1394 ports These ports are routed to two standard 6 pin IEEE1394 connectors on the carrier board Using these two ports the DSP development kit can be inserted anywhere in an existing IEEE1394 network Since the IEEE1394 physical layer acts as a repeater no processing power is required for transferring data from one port to the other For transferring data between the DSP development kit and the IEEE1394 network three transfer methods are available which are described in the following chapter 2 4 4 IEEE1394 Data Transfer Methods IEEE1394 provides three different methods for t
49. vailable Bandwidth Available Channels bitmask 400 Mbit s DI Query Resources 0 0x0 0x0 Bytes per sec 0 ay BF 63 lsochronous Data Transfer Transmit data over an isochronous channel TALK Setup gt gt Receive data from an isochronous channel LISTEN Setup gt gt Current Cycle Time Second Count Cycle Count Cycle Offset I Auto Update 0 0 0 r Output Window Show Dock Clear www thesycon de Figure 25 Isochronous setup 1 VHPD demo d USER GUIDE DSP DEVELOPMENT KIT Date 20 January 2005 Doc no DSP_DevKit_UG Iss Rev 1 00 Page 135 400 Mbit s e Figure 26 Isochronous setup 2 VHPD demo YHPDAPP Isoch Receive Chan 0 Figure 27 Isochronous setup 3 VHPD demo in USER GUIDE KSI DSP DEVELOPMENT KIT orsys Date 20 January 2005 Doc no DSP_DevKit_UG Iss Rev 1 00 Page 36 COM1_115200_8_N_1_HW HyperTerminal Datei Bearbeiten Ansicht Anruf bertragung press 97 to get help page BR Transnit operat ion Cont inuous operation Any key aborts 40A gt Verbunden 04 47 33 ANSI ECO Figure 28 Isochronous transmit isoch_1394 YHPDAPP Isoch Receive Chan 0 EN Channel Settings Buffer Settings File Run Start Stop Elapsed Time EH K 116 sec r Parameters Channel No 0 Bandwidth 32000 Bytes s Buffer size 3840 bytes filled
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